[SCSI] qla2xxx: Correct ISP24xx soft-reset handling.
A driver must wait 100us before attempting an MMIO operation
to the RISC after a soft-reset has been initiated. A
similar delay was needed with earlier ISPs.
Note: a PCI config-space read is used to flush the MMIO
write to the ISP, since the ISP's state machines are unable
to respond to any MMIO read during the reset process.
Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c
index 89793c1..5c5d231 100644
--- a/drivers/scsi/qla2xxx/qla_dbg.c
+++ b/drivers/scsi/qla2xxx/qla_dbg.c
@@ -970,7 +970,7 @@
int rval;
uint32_t cnt, timer;
uint32_t risc_address;
- uint16_t mb[4];
+ uint16_t mb[4], wd;
uint32_t stat;
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
@@ -1514,10 +1514,10 @@
WRT_REG_DWORD(®->ctrl_status,
CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
- RD_REG_DWORD(®->ctrl_status);
+ pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
+ udelay(100);
/* Wait for firmware to complete NVRAM accesses. */
- udelay(5);
mb[0] = (uint32_t) RD_REG_WORD(®->mailbox0);
for (cnt = 10000 ; cnt && mb[0]; cnt--) {
udelay(5);
@@ -1525,7 +1525,7 @@
barrier();
}
- udelay(20);
+ /* Wait for soft-reset to complete. */
for (cnt = 0; cnt < 30000; cnt++) {
if ((RD_REG_DWORD(®->ctrl_status) &
CSRX_ISP_SOFT_RESET) == 0)
diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c
index 8fb084b..2d72012 100644
--- a/drivers/scsi/qla2xxx/qla_init.c
+++ b/drivers/scsi/qla2xxx/qla_init.c
@@ -567,6 +567,7 @@
unsigned long flags = 0;
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
uint32_t cnt, d2;
+ uint16_t wd;
spin_lock_irqsave(&ha->hardware_lock, flags);
@@ -581,10 +582,10 @@
WRT_REG_DWORD(®->ctrl_status,
CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
- RD_REG_DWORD(®->ctrl_status);
+ pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
+ udelay(100);
/* Wait for firmware to complete NVRAM accesses. */
- udelay(5);
d2 = (uint32_t) RD_REG_WORD(®->mailbox0);
for (cnt = 10000 ; cnt && d2; cnt--) {
udelay(5);
@@ -592,7 +593,7 @@
barrier();
}
- udelay(20);
+ /* Wait for soft-reset to complete. */
d2 = RD_REG_DWORD(®->ctrl_status);
for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
udelay(5);