| commit | 2c6b473bfabdca1be95612543d7b31376df30caa | [log] [tgz] |
|---|---|---|
| author | Maxime Ripard <maxime.ripard@free-electrons.com> | Sun Dec 29 22:31:53 2013 +0100 |
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | Sun Dec 29 22:31:53 2013 +0100 |
| tree | d982eea37271c51d519baa12aa53148fe166b16a | |
| parent | 81ee429ffdd021626bf191bb8a3ae886dd94adcc [diff] | |
| parent | 118c07aedad55de8be81845e6d6429d266906b7d [diff] |
Merge tag 'sunxi-clk-3.14-for-maxime' of https://bitbucket.org/emiliolopez/linux into sunxi/dt-for-3.14 Allwinner sunXi SoCs DT changes for clocks This contains the DT parts of the "[PATCH v3 00/13] clk: sunxi: add PLL5 and PLL6 support" series. It adds DT nodes for PLL4/5/6 and mod0 clocks on most sunxi platforms.