| commit | 2c63a555e8495f3d6db443ca73094a6a3508df4a | [log] [tgz] |
|---|---|---|
| author | Ido Schimmel <idosch@mellanox.com> | Wed Apr 06 17:10:07 2016 +0200 |
| committer | David S. Miller <davem@davemloft.net> | Wed Apr 06 17:24:18 2016 -0400 |
| tree | 215ad30ac521090da86d60de89188ff1a04f6b58 | |
| parent | b9b7cee405797cc395f699d8dee4747b96b1e0a8 [diff] |
mlxsw: reg: Add QoS Switch Traffic Class Table register As part of DCB ops we'll have to configure the priority to traffic class mapping of a port. Add the QoS Switch Traffic Class Table (QTCT) register, which configures the mapping between the packet switch priority and traffic class on the transmit port. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>