| commit | 2b935d524d851830b68dd8c58d3098d775d6047a | [log] [tgz] |
|---|---|---|
| author | Geert Uytterhoeven <geert+renesas@glider.be> | Thu Mar 15 10:44:37 2018 +0100 |
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | Wed Mar 21 17:35:00 2018 +0100 |
| tree | 3a610ea9b6cf5ba661622072d55ec62a444c5551 | |
| parent | f046d6a6bf2a1f0db5e2f61b5236efb1b6bebfde [diff] |
clk: renesas: rcar-gen3: Always use readl()/writel()
The R-Car Gen3 CPG/MSSR driver (again) uses a mix of
clk_readl()/clk_writel() and readl()/writel() to access the clock
registers. Settle on the generic readl()/writel().
Cfr. commit 30ad3cf00e94f4a7 ("clk: renesas: rcar-gen3-cpg: Always use
readl()/writel()").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>