| commit | 29dbe3bcd2e28e71823febdca989d63d5c27d152 | [log] [tgz] |
|---|---|---|
| author | Alex Deucher <alexander.deucher@amd.com> | Fri Oct 05 10:22:02 2012 -0400 |
| committer | Alex Deucher <alexander.deucher@amd.com> | Mon Oct 15 13:21:00 2012 -0400 |
| tree | 167612c387fdc175e2b8aa9d74da30d9a751339e | |
| parent | cd23492af3d4401c02c48a4bebe5995c9498eac5 [diff] |
drm/radeon: allocate PPLLs from low to high The order shouldn't matter, but there have been problems reported on certain older asics. This behaves more like the original code before the PPLL allocation rework. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Markus Trippelsdorf <markus@trippelsdorf.de>