| commit | 285541647a816e00348916ba7387eeacea30eba9 | [log] [tgz] |
|---|---|---|
| author | Rodrigo Vivi <rodrigo.vivi@gmail.com> | Mon May 06 19:37:37 2013 -0300 |
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | Fri May 10 21:56:50 2013 +0200 |
| tree | 7fbf02d900bb2865ac6f3230a16df557a708637a | |
| parent | 891348b2bf08d8946e0621bec49802897b28c1c4 [diff] |
drm/i915: HSW FBC WaFbcAsynchFlipDisableFbcQueue Display register 420B0h bit 22 must be set to 1b for the entire time that Frame Buffer Compression is enabled. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>