| commit | 2631ed00b0498810f8d5c2163c6b5270d893687b | [log] [tgz] |
|---|---|---|
| author | Peter Zijlstra (Intel) <peterz@infradead.org> | Thu Jun 25 16:03:12 2020 +0800 |
| committer | Catalin Marinas <catalin.marinas@arm.com> | Tue Jul 07 11:23:46 2020 +0100 |
| tree | 6480bf9dcda9ef3f0f7695ea025804b91049c990 | |
| parent | e735b98a5fe08c0f50f9fdc3e3a844e3638e6649 [diff] |
tlb: mmu_gather: add tlb_flush_*_range APIs
tlb_flush_{pte|pmd|pud|p4d}_range() adjust the tlb->start and
tlb->end, then set corresponding cleared_*.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20200625080314.230-5-yezhenyu2@huawei.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>