| commit | 26269af95af83145a3bccca41344c66502fdded9 | [log] [tgz] |
|---|---|---|
| author | Hyungwon Hwang <human.hwang@samsung.com> | Fri Jun 12 21:59:03 2015 +0900 |
| committer | Inki Dae <inki.dae@samsung.com> | Mon Jun 22 20:05:00 2015 +0900 |
| tree | 10d7d375f751e2a61cc1a9c0a51c4d6c07cb7ee0 | |
| parent | 77bbd8914a91fab25f567772db60e2d1372de8c6 [diff] |
drm/exynos: dsi: rename pll_clk to sclk_clk This patch renames pll_clk to sclk_clk. The clock referenced by pll_clk is actually not the pll input clock for dsi. The pll input clock comes from the board's oscillator directly. But for the backward compatibility, the old clock name "pll_clk" is also OK. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>