commit 1b85066bb1332e4298e533b7f15e04d82990ceaf
author Jordan Justen <jordan.l.justen@intel.com> Sun Mar 06 23:30:29 2016 -0800
committer Daniel Vetter <daniel.vetter@ffwll.ch> Mon Mar 21 10:03:17 2016 +0100
tree ce5efb418e2d802c1b3fa9c2115a7b2289d03a42
parent 99c5aeca94a506a2b279022fae5de3f8606730bd

drm/i915: Add Haswell CS GPR registers to whitelist

This is needed for the Mesa Vulkan driver on Haswell.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1457335830-30923-5-git-send-email-jordan.l.justen@intel.com

drivers/gpu/drm/i915/i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 264885f..06fb589 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -588,6 +588,10 @@
 #define GEN7_GPGPU_DISPATCHDIMY         _MMIO(0x2504)
 #define GEN7_GPGPU_DISPATCHDIMZ         _MMIO(0x2508)
 
+/* There are the 16 64-bit CS General Purpose Registers */
+#define HSW_CS_GPR(n)                   _MMIO(0x2600 + (n) * 8)
+#define HSW_CS_GPR_UDW(n)               _MMIO(0x2600 + (n) * 8 + 4)
+
 #define OACONTROL _MMIO(0x2360)
 
 #define _GEN7_PIPEA_DE_LOAD_SL	0x70068