| commit | 187e5cd2d133771e978e7e4ea6aa684dfd1ce6ab | [log] [tgz] |
|---|---|---|
| author | Xiaolong Zhang <xiaolong.zhang@unisoc.com> | Wed Mar 04 15:27:24 2020 +0800 |
| committer | Stephen Boyd <sboyd@kernel.org> | Tue Mar 24 19:03:56 2020 -0700 |
| tree | cb09afa67e7e7b1743cd51b76cedad563fc59713 | |
| parent | bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9 [diff] |
clk: sprd: add gate for pll clocks Some sprd's gate clocks are used to the switch of pll, which need to wait a certain time for stable after being enabled. Signed-off-by: Xiaolong Zhang <xiaolong.zhang@unisoc.com> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Link: https://lkml.kernel.org/r/20200304072730.9193-2-zhang.lyra@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>