| commit | 161996a8003faa22baaac9f379ef580af551d26f | [log] [tgz] |
|---|---|---|
| author | Chris Wilson <chris@chris-wilson.co.uk> | Wed Mar 06 08:24:47 2019 +0000 |
| committer | Chris Wilson <chris@chris-wilson.co.uk> | Wed Mar 06 11:08:32 2019 +0000 |
| tree | bdc60c4df2940b401a5161f5d0dbb8c8fca4ec24 | |
| parent | b146e5efe660e03eee2b2c4a2e02410d9a8824ec [diff] |
drm/i915/selftests: Fix MI_STORE_DWORD_IMM alignment MI_STORE_DWORD_IMM wants to write into a dword-aligned (4B) address, we mistakenly cleared bit2 and not bits 0 and 1. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Matthew Auld <matthew.auld@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190306082447.21563-1-chris@chris-wilson.co.uk
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c index 30111c0..0346ff2 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -1433,7 +1433,7 @@ static int igt_vm_isolation(void *arg) div64_u64_rem(i915_prandom_u64_state(&prng), vm_total, &offset); - offset &= ~sizeof(u32); + offset &= -sizeof(u32); offset += I915_GTT_PAGE_SIZE; err = write_to_scratch(ctx_a, engine,