| commit | be8408e1440cbc86683e4e1c65270ad517b4274a | [log] [tgz] |
|---|---|---|
| author | Jiri Pirko <jiri@mellanox.com> | Tue Jun 06 14:12:04 2017 +0200 |
| committer | David S. Miller <davem@davemloft.net> | Tue Jun 06 12:45:23 2017 -0400 |
| tree | c18da9da37f5abda6d8e1d5ef52e21fb6a21a16e | |
| parent | 5a4d1fee2f844813cb2092b7a06b0e20ed9e2fa4 [diff] |
mlxsw: pci: Fix size of trap_id field in CQE
The "trap_id" is 9bits long. So far, this was not a problem since we
used only traps with ids that fit into 8bits. But the ACL traps that are
going to be introduced use the 9th bit.
Fixes: eda6500a987a ("mlxsw: Add PCI bus implementation")
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Reviewed-by: Yotam Gigi <yotamg@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>