| commit | 06613e38f1f2b098d46e9549756c0d5c040f2ef8 | [log] [tgz] |
|---|---|---|
| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | Fri Jul 17 00:28:38 2015 +0300 |
| committer | David S. Miller <davem@davemloft.net> | Mon Jul 20 20:42:02 2015 -0700 |
| tree | d0df3b2e38679b11a188903b809e360a0a05a6f6 | |
| parent | 194ac06e39238685abc0eeb436efa82e6571b90f [diff] |
ravb: fix race updating TCCR The TCCR.TSRQn bit may get clearead after TCCR gets read, so that TCCR write would get skipped. We don't need to check this bit before setting. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>