| commit | 190f73ab4c43ecfc8e93843fe249efeff7d69a90 | [log] [tgz] |
|---|---|---|
| author | Voon Weifeng <weifeng.voon@intel.com> | Tue Aug 27 09:38:11 2019 +0800 |
| committer | David S. Miller <davem@davemloft.net> | Tue Aug 27 21:59:38 2019 -0700 |
| tree | 2fb35df8641af5aad5fdd0a4b276cb05932b136a | |
| parent | f6256585fecc9b9d2f0a335a92e864ccae98ea24 [diff] |
net: stmmac: setup higher frequency clk support for EHL & TGL EHL DW EQOS is running on a 200MHz clock. Setting up stmmac-clk, ptp clock and ptp_max_adj to 200MHz. Signed-off-by: Voon Weifeng <weifeng.voon@intel.com> Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>