| commit | 871370308675e477abd57a69ce66ca4730a4249c | [log] [tgz] |
|---|---|---|
| author | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | Sun Mar 03 22:29:21 2019 +0200 |
| committer | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | Thu Mar 28 06:12:38 2019 +0200 |
| tree | 6fbd2e830e7d43745a1a02cdf515631aa304af5b | |
| parent | b764f2f66ed48c7f0df2c4b1350c7973109a1d14 [diff] |
drm: rcar-du: lvds: Adjust operating frequency for D3 and E3 The D3 and E3 SoCs have different pixel clock frequency limits for the LVDS encoder than the other SoCs in the Gen3 family. Adjust the mode fixup implementation accordingly. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>