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review.shift-gmbh.com / SHIFTPHONES / android_kernel_shift_sdm845 / f8bcbe62acd0e1ce9004b83e98a4af87ae385dcf / drivers / clk / rockchip / clk.h
  1. 4a1caed clk: make several parent names const by Uwe Kleine-König · 10 years ago
  2. 692d832 clk: don't use __initconst for non-const arrays by Uwe Kleine-König · 10 years ago
  3. 89bf26c clk: rockchip: Add support for the mmc clock phases using the framework by Alexandru M Stan · 10 years ago
  4. 0bb66d3 clk: rockchip: add optional sync to pll rate parameters by Heiko Stuebner · 10 years ago
  5. 4f8a7c5 clk: rockchip: add ability to specify pll-specific flags by Heiko Stuebner · 10 years ago
  6. 49ed9ee clk: rockchip: change PLL setting for better clock jitter by Kever Yang · 10 years ago
  7. 6f1294b clk: rockchip: add restart handler by Heiko Stübner · 11 years ago
  8. f6fba5f clk: rockchip: add new clock-type for the cpuclk by Heiko Stuebner · 11 years ago
  9. fe94f97 clk: rockchip: protect critical clocks from getting disabled by Heiko Stübner · 11 years ago
  10. b9e4ba5 clk: rockchip: add clock controller for rk3288 by Heiko Stübner · 11 years ago
  11. 85fa0c7 clk: rockchip: add reset controller by Heiko Stübner · 11 years ago
  12. 90c5902 clk: rockchip: add clock type for pll clocks and pll used on rk3066 by Heiko Stübner · 11 years ago
  13. a245fec clk: rockchip: add basic infrastructure for clock branches by Heiko Stübner · 11 years ago