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Asutosh Das0ef24812012-12-18 16:14:02 +05301/*
2 * drivers/mmc/host/sdhci-msm.c - Qualcomm Technologies, Inc. MSM SDHCI Platform
3 * driver source file
4 *
Venkat Gopalakrishnan0a92d532014-12-16 17:31:00 -08005 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
Asutosh Das0ef24812012-12-18 16:14:02 +05306 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 and
9 * only version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/module.h>
19#include <linux/mmc/host.h>
20#include <linux/mmc/card.h>
21#include <linux/mmc/sdio_func.h>
22#include <linux/gfp.h>
23#include <linux/of.h>
24#include <linux/of_gpio.h>
25#include <linux/regulator/consumer.h>
26#include <linux/types.h>
27#include <linux/input.h>
28#include <linux/platform_device.h>
29#include <linux/wait.h>
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -070030#include <linux/io.h>
31#include <linux/delay.h>
32#include <linux/scatterlist.h>
33#include <linux/slab.h>
Sahitya Tummala581df132013-03-12 14:57:46 +053034#include <linux/mmc/slot-gpio.h>
Sahitya Tummalaeaa21862013-03-20 19:34:59 +053035#include <linux/dma-mapping.h>
Sahitya Tummala66b0fe32013-04-25 11:50:56 +053036#include <linux/iopoll.h>
Pratibhasagar V9acf2642013-11-21 21:07:21 +053037#include <linux/pinctrl/consumer.h>
38#include <linux/iopoll.h>
Sahitya Tummala8a3e8182013-03-10 14:12:52 +053039#include <linux/msm-bus.h>
Konstantin Dorfman98377d32015-02-25 10:09:41 +020040#include <linux/pm_runtime.h>
Konstantin Dorfmanddab0cc2015-02-25 16:23:50 +020041#include <trace/events/mmc.h>
Asutosh Das0ef24812012-12-18 16:14:02 +053042
Sahitya Tummala56874732015-05-21 08:24:03 +053043#include "sdhci-msm.h"
Venkat Gopalakrishnand371f142015-05-29 17:49:46 -070044#include "cmdq_hci.h"
Asutosh Das0ef24812012-12-18 16:14:02 +053045
Venkat Gopalakrishnan0a92d532014-12-16 17:31:00 -080046#define CORE_POWER 0x0
47#define CORE_SW_RST (1 << 7)
48
Venkat Gopalakrishnana58f91f2012-09-17 16:00:15 -070049#define SDHCI_VER_100 0x2B
Venkat Gopalakrishnan0a92d532014-12-16 17:31:00 -080050#define CORE_MCI_DATA_CNT 0x30
51#define CORE_MCI_STATUS 0x34
52#define CORE_MCI_FIFO_CNT 0x44
53
54#define CORE_VERSION_STEP_MASK 0x0000FFFF
55#define CORE_VERSION_MINOR_MASK 0x0FFF0000
56#define CORE_VERSION_MINOR_SHIFT 16
57#define CORE_VERSION_MAJOR_MASK 0xF0000000
58#define CORE_VERSION_MAJOR_SHIFT 28
59#define CORE_VERSION_TARGET_MASK 0x000000FF
60
61#define CORE_GENERICS 0x70
62#define SWITCHABLE_SIGNALLING_VOL (1 << 29)
Pratibhasagar Vd8acb7c2013-11-11 01:32:21 +053063
64#define CORE_VERSION_MAJOR_MASK 0xF0000000
65#define CORE_VERSION_MAJOR_SHIFT 28
66
Asutosh Das0ef24812012-12-18 16:14:02 +053067#define CORE_HC_MODE 0x78
68#define HC_MODE_EN 0x1
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -070069#define FF_CLK_SW_RST_DIS (1 << 13)
Asutosh Das0ef24812012-12-18 16:14:02 +053070
Sahitya Tummala67717bc2013-08-02 09:21:37 +053071#define CORE_MCI_VERSION 0x050
72#define CORE_TESTBUS_CONFIG 0x0CC
73#define CORE_TESTBUS_ENA (1 << 3)
Venkat Gopalakrishnan0a92d532014-12-16 17:31:00 -080074#define CORE_TESTBUS_SEL2_BIT 4
75#define CORE_TESTBUS_SEL2 (1 << CORE_TESTBUS_SEL2_BIT)
Sahitya Tummala67717bc2013-08-02 09:21:37 +053076
Asutosh Das0ef24812012-12-18 16:14:02 +053077#define CORE_PWRCTL_STATUS 0xDC
78#define CORE_PWRCTL_MASK 0xE0
79#define CORE_PWRCTL_CLEAR 0xE4
80#define CORE_PWRCTL_CTL 0xE8
81
82#define CORE_PWRCTL_BUS_OFF 0x01
83#define CORE_PWRCTL_BUS_ON (1 << 1)
84#define CORE_PWRCTL_IO_LOW (1 << 2)
85#define CORE_PWRCTL_IO_HIGH (1 << 3)
86
87#define CORE_PWRCTL_BUS_SUCCESS 0x01
88#define CORE_PWRCTL_BUS_FAIL (1 << 1)
89#define CORE_PWRCTL_IO_SUCCESS (1 << 2)
90#define CORE_PWRCTL_IO_FAIL (1 << 3)
91
92#define INT_MASK 0xF
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -070093#define MAX_PHASES 16
94
Venkat Gopalakrishnan9e069632013-06-12 11:16:37 -070095#define CORE_DLL_CONFIG 0x100
96#define CORE_CMD_DAT_TRACK_SEL (1 << 0)
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -070097#define CORE_DLL_EN (1 << 16)
98#define CORE_CDR_EN (1 << 17)
99#define CORE_CK_OUT_EN (1 << 18)
100#define CORE_CDR_EXT_EN (1 << 19)
101#define CORE_DLL_PDN (1 << 29)
102#define CORE_DLL_RST (1 << 30)
Venkat Gopalakrishnan9e069632013-06-12 11:16:37 -0700103
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700104#define CORE_DLL_STATUS 0x108
Venkat Gopalakrishnan9e069632013-06-12 11:16:37 -0700105#define CORE_DLL_LOCK (1 << 7)
Krishna Konda2faa7bb2014-06-04 01:25:16 -0700106#define CORE_DDR_DLL_LOCK (1 << 11)
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700107
108#define CORE_VENDOR_SPEC 0x10C
Krishna Konda46fd1432014-10-30 21:13:27 -0700109#define CORE_CLK_PWRSAVE (1 << 1)
110#define CORE_HC_MCLK_SEL_DFLT (2 << 8)
111#define CORE_HC_MCLK_SEL_HS400 (3 << 8)
112#define CORE_HC_MCLK_SEL_MASK (3 << 8)
113#define CORE_HC_AUTO_CMD21_EN (1 << 6)
114#define CORE_IO_PAD_PWR_SWITCH_EN (1 << 15)
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700115#define CORE_IO_PAD_PWR_SWITCH (1 << 16)
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -0700116#define CORE_HC_SELECT_IN_EN (1 << 18)
117#define CORE_HC_SELECT_IN_HS400 (6 << 19)
118#define CORE_HC_SELECT_IN_MASK (7 << 19)
Venkat Gopalakrishnan17edb352015-06-24 14:46:49 -0700119#define CORE_VENDOR_SPEC_POR_VAL 0xA1C
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700120
Venkat Gopalakrishnan0a92d532014-12-16 17:31:00 -0800121#define CORE_VENDOR_SPEC_ADMA_ERR_ADDR0 0x114
122#define CORE_VENDOR_SPEC_ADMA_ERR_ADDR1 0x118
123
Krishna Konda7feab352013-09-17 23:55:40 -0700124#define CORE_VENDOR_SPEC_CAPABILITIES0 0x11C
Pratibhasagar Vd8acb7c2013-11-11 01:32:21 +0530125#define CORE_8_BIT_SUPPORT (1 << 18)
126#define CORE_3_3V_SUPPORT (1 << 24)
127#define CORE_3_0V_SUPPORT (1 << 25)
128#define CORE_1_8V_SUPPORT (1 << 26)
Gilad Broner2a10ca02014-10-02 17:20:35 +0300129#define CORE_SYS_BUS_SUPPORT_64_BIT BIT(28)
Krishna Konda7feab352013-09-17 23:55:40 -0700130
Venkat Gopalakrishnan0a92d532014-12-16 17:31:00 -0800131#define CORE_SDCC_DEBUG_REG 0x124
Sahitya Tummala67717bc2013-08-02 09:21:37 +0530132
Venkat Gopalakrishnan9e069632013-06-12 11:16:37 -0700133#define CORE_CSR_CDC_CTLR_CFG0 0x130
134#define CORE_SW_TRIG_FULL_CALIB (1 << 16)
135#define CORE_HW_AUTOCAL_ENA (1 << 17)
136
137#define CORE_CSR_CDC_CTLR_CFG1 0x134
138#define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138
139#define CORE_TIMER_ENA (1 << 16)
140
141#define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C
142#define CORE_CSR_CDC_REFCOUNT_CFG 0x140
143#define CORE_CSR_CDC_COARSE_CAL_CFG 0x144
144#define CORE_CDC_OFFSET_CFG 0x14C
145#define CORE_CSR_CDC_DELAY_CFG 0x150
146#define CORE_CDC_SLAVE_DDA_CFG 0x160
147#define CORE_CSR_CDC_STATUS0 0x164
148#define CORE_CALIBRATION_DONE (1 << 0)
149
150#define CORE_CDC_ERROR_CODE_MASK 0x7000000
151
152#define CORE_CSR_CDC_GEN_CFG 0x178
153#define CORE_CDC_SWITCH_BYPASS_OFF (1 << 0)
154#define CORE_CDC_SWITCH_RC_EN (1 << 1)
155
156#define CORE_DDR_200_CFG 0x184
157#define CORE_CDC_T4_DLY_SEL (1 << 0)
Ritesh Harjaniea709662015-05-27 15:40:24 +0530158#define CORE_CMDIN_RCLK_EN (1 << 1)
Venkat Gopalakrishnan9e069632013-06-12 11:16:37 -0700159#define CORE_START_CDC_TRAFFIC (1 << 6)
Ritesh Harjaniea709662015-05-27 15:40:24 +0530160
Krishna Konda2faa7bb2014-06-04 01:25:16 -0700161#define CORE_VENDOR_SPEC3 0x1B0
162#define CORE_PWRSAVE_DLL (1 << 3)
Ritesh Harjani4a5ffd12015-07-15 13:32:07 +0530163#define CORE_CMDEN_HS400_INPUT_MASK_CNT (1 << 13)
Krishna Konda2faa7bb2014-06-04 01:25:16 -0700164
165#define CORE_DLL_CONFIG_2 0x1B4
166#define CORE_DDR_CAL_EN (1 << 0)
Venkat Gopalakrishnanc0a5c3a2015-02-03 16:10:07 -0800167#define CORE_FLL_CYCLE_CNT (1 << 18)
168#define CORE_DLL_CLOCK_DISABLE (1 << 21)
Krishna Konda2faa7bb2014-06-04 01:25:16 -0700169
170#define CORE_DDR_CONFIG 0x1B8
171#define DDR_CONFIG_POR_VAL 0x80040853
172
Sahitya Tummala56874732015-05-21 08:24:03 +0530173#define MSM_MMC_DEFAULT_CPU_DMA_LATENCY 200 /* usecs */
174
Venkat Gopalakrishnan450745e2014-07-24 20:39:34 -0700175/* 512 descriptors */
176#define SDHCI_MSM_MAX_SEGMENTS (1 << 9)
Sahitya Tummalaa7f3c572013-01-11 11:30:45 +0530177#define SDHCI_MSM_MMC_CLK_GATE_DELAY 200 /* msecs */
Asutosh Das648f9d12013-01-10 21:11:04 +0530178
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -0700179#define CORE_FREQ_100MHZ (100 * 1000 * 1000)
Venkat Gopalakrishnanc0a5c3a2015-02-03 16:10:07 -0800180#define TCXO_FREQ 19200000
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -0700181
Venkat Gopalakrishnan9e069632013-06-12 11:16:37 -0700182#define INVALID_TUNING_PHASE -1
183
Krishna Konda96e6b112013-10-28 15:25:03 -0700184#define NUM_TUNING_PHASES 16
185#define MAX_DRV_TYPES_SUPPORTED_HS200 3
Konstantin Dorfman98377d32015-02-25 10:09:41 +0200186#define MSM_AUTOSUSPEND_DELAY_MS 100
Krishna Konda96e6b112013-10-28 15:25:03 -0700187
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700188static const u32 tuning_block_64[] = {
189 0x00FF0FFF, 0xCCC3CCFF, 0xFFCC3CC3, 0xEFFEFFFE,
190 0xDDFFDFFF, 0xFBFFFBFF, 0xFF7FFFBF, 0xEFBDF777,
191 0xF0FFF0FF, 0x3CCCFC0F, 0xCFCC33CC, 0xEEFFEFFF,
192 0xFDFFFDFF, 0xFFBFFFDF, 0xFFF7FFBB, 0xDE7B7FF7
193};
194
195static const u32 tuning_block_128[] = {
196 0xFF00FFFF, 0x0000FFFF, 0xCCCCFFFF, 0xCCCC33CC,
197 0xCC3333CC, 0xFFFFCCCC, 0xFFFFEEFF, 0xFFEEEEFF,
198 0xFFDDFFFF, 0xDDDDFFFF, 0xBBFFFFFF, 0xBBFFFFFF,
199 0xFFFFFFBB, 0xFFFFFF77, 0x77FF7777, 0xFFEEDDBB,
200 0x00FFFFFF, 0x00FFFFFF, 0xCCFFFF00, 0xCC33CCCC,
201 0x3333CCCC, 0xFFCCCCCC, 0xFFEEFFFF, 0xEEEEFFFF,
202 0xDDFFFFFF, 0xDDFFFFFF, 0xFFFFFFDD, 0xFFFFFFBB,
203 0xFFFFBBBB, 0xFFFF77FF, 0xFF7777FF, 0xEEDDBB77
204};
Asutosh Das0ef24812012-12-18 16:14:02 +0530205
Venkat Gopalakrishnan270580a2013-03-11 12:17:57 -0700206static int disable_slots;
207/* root can write, others read */
208module_param(disable_slots, int, S_IRUGO|S_IWUSR);
209
Asutosh Das0ef24812012-12-18 16:14:02 +0530210enum vdd_io_level {
211 /* set vdd_io_data->low_vol_level */
212 VDD_IO_LOW,
213 /* set vdd_io_data->high_vol_level */
214 VDD_IO_HIGH,
215 /*
216 * set whatever there in voltage_level (third argument) of
217 * sdhci_msm_set_vdd_io_vol() function.
218 */
219 VDD_IO_SET_LEVEL,
220};
221
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700222/* MSM platform specific tuning */
223static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host,
224 u8 poll)
225{
226 int rc = 0;
227 u32 wait_cnt = 50;
228 u8 ck_out_en = 0;
229 struct mmc_host *mmc = host->mmc;
230
231 /* poll for CK_OUT_EN bit. max. poll time = 50us */
232 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
233 CORE_CK_OUT_EN);
234
235 while (ck_out_en != poll) {
236 if (--wait_cnt == 0) {
237 pr_err("%s: %s: CK_OUT_EN bit is not %d\n",
238 mmc_hostname(mmc), __func__, poll);
239 rc = -ETIMEDOUT;
240 goto out;
241 }
242 udelay(1);
243
244 ck_out_en = !!(readl_relaxed(host->ioaddr +
245 CORE_DLL_CONFIG) & CORE_CK_OUT_EN);
246 }
247out:
248 return rc;
249}
250
Asutosh Dase5e9ca62013-07-30 19:08:36 +0530251/*
252 * Enable CDR to track changes of DAT lines and adjust sampling
253 * point according to voltage/temperature variations
254 */
255static int msm_enable_cdr_cm_sdc4_dll(struct sdhci_host *host)
256{
257 int rc = 0;
258 u32 config;
259
260 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
261 config |= CORE_CDR_EN;
262 config &= ~(CORE_CDR_EXT_EN | CORE_CK_OUT_EN);
263 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
264
265 rc = msm_dll_poll_ck_out_en(host, 0);
266 if (rc)
267 goto err;
268
269 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
270 CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
271
272 rc = msm_dll_poll_ck_out_en(host, 1);
273 if (rc)
274 goto err;
275 goto out;
276err:
277 pr_err("%s: %s: failed\n", mmc_hostname(host->mmc), __func__);
278out:
279 return rc;
280}
281
282static ssize_t store_auto_cmd21(struct device *dev, struct device_attribute
283 *attr, const char *buf, size_t count)
284{
285 struct sdhci_host *host = dev_get_drvdata(dev);
286 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
287 struct sdhci_msm_host *msm_host = pltfm_host->priv;
288 u32 tmp;
289 unsigned long flags;
290
291 if (!kstrtou32(buf, 0, &tmp)) {
292 spin_lock_irqsave(&host->lock, flags);
293 msm_host->en_auto_cmd21 = !!tmp;
294 spin_unlock_irqrestore(&host->lock, flags);
295 }
296 return count;
297}
298
299static ssize_t show_auto_cmd21(struct device *dev,
300 struct device_attribute *attr, char *buf)
301{
302 struct sdhci_host *host = dev_get_drvdata(dev);
303 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
304 struct sdhci_msm_host *msm_host = pltfm_host->priv;
305
306 return snprintf(buf, PAGE_SIZE, "%d\n", msm_host->en_auto_cmd21);
307}
308
309/* MSM auto-tuning handler */
310static int sdhci_msm_config_auto_tuning_cmd(struct sdhci_host *host,
311 bool enable,
312 u32 type)
313{
314 int rc = 0;
315 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
316 struct sdhci_msm_host *msm_host = pltfm_host->priv;
317 u32 val = 0;
318
319 if (!msm_host->en_auto_cmd21)
320 return 0;
321
322 if (type == MMC_SEND_TUNING_BLOCK_HS200)
323 val = CORE_HC_AUTO_CMD21_EN;
324 else
325 return 0;
326
327 if (enable) {
328 rc = msm_enable_cdr_cm_sdc4_dll(host);
329 writel_relaxed(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
330 val, host->ioaddr + CORE_VENDOR_SPEC);
331 } else {
332 writel_relaxed(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) &
333 ~val, host->ioaddr + CORE_VENDOR_SPEC);
334 }
335 return rc;
336}
337
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700338static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
339{
340 int rc = 0;
341 u8 grey_coded_phase_table[] = {0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
342 0xC, 0xD, 0xF, 0xE, 0xA, 0xB, 0x9,
343 0x8};
344 unsigned long flags;
345 u32 config;
346 struct mmc_host *mmc = host->mmc;
347
348 pr_debug("%s: Enter %s\n", mmc_hostname(mmc), __func__);
349 spin_lock_irqsave(&host->lock, flags);
350
351 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
352 config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
353 config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
354 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
355
356 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
357 rc = msm_dll_poll_ck_out_en(host, 0);
358 if (rc)
359 goto err_out;
360
361 /*
362 * Write the selected DLL clock output phase (0 ... 15)
363 * to CDR_SELEXT bit field of DLL_CONFIG register.
364 */
365 writel_relaxed(((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
366 & ~(0xF << 20))
367 | (grey_coded_phase_table[phase] << 20)),
368 host->ioaddr + CORE_DLL_CONFIG);
369
370 /* Set CK_OUT_EN bit of DLL_CONFIG register to 1. */
371 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
372 | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
373
374 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
375 rc = msm_dll_poll_ck_out_en(host, 1);
376 if (rc)
377 goto err_out;
378
379 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
380 config |= CORE_CDR_EN;
381 config &= ~CORE_CDR_EXT_EN;
382 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
383 goto out;
384
385err_out:
386 pr_err("%s: %s: Failed to set DLL phase: %d\n",
387 mmc_hostname(mmc), __func__, phase);
388out:
389 spin_unlock_irqrestore(&host->lock, flags);
390 pr_debug("%s: Exit %s\n", mmc_hostname(mmc), __func__);
391 return rc;
392}
393
394/*
395 * Find out the greatest range of consecuitive selected
396 * DLL clock output phases that can be used as sampling
397 * setting for SD3.0 UHS-I card read operation (in SDR104
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -0700398 * timing mode) or for eMMC4.5 card read operation (in
399 * HS400/HS200 timing mode).
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700400 * Select the 3/4 of the range and configure the DLL with the
401 * selected DLL clock output phase.
402 */
403
404static int msm_find_most_appropriate_phase(struct sdhci_host *host,
405 u8 *phase_table, u8 total_phases)
406{
407 int ret;
408 u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
409 u8 phases_per_row[MAX_PHASES] = {0};
410 int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
411 int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
412 bool phase_0_found = false, phase_15_found = false;
413 struct mmc_host *mmc = host->mmc;
414
415 pr_debug("%s: Enter %s\n", mmc_hostname(mmc), __func__);
416 if (!total_phases || (total_phases > MAX_PHASES)) {
417 pr_err("%s: %s: invalid argument: total_phases=%d\n",
418 mmc_hostname(mmc), __func__, total_phases);
419 return -EINVAL;
420 }
421
422 for (cnt = 0; cnt < total_phases; cnt++) {
423 ranges[row_index][col_index] = phase_table[cnt];
424 phases_per_row[row_index] += 1;
425 col_index++;
426
427 if ((cnt + 1) == total_phases) {
428 continue;
429 /* check if next phase in phase_table is consecutive or not */
430 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
431 row_index++;
432 col_index = 0;
433 }
434 }
435
436 if (row_index >= MAX_PHASES)
437 return -EINVAL;
438
439 /* Check if phase-0 is present in first valid window? */
440 if (!ranges[0][0]) {
441 phase_0_found = true;
442 phase_0_raw_index = 0;
443 /* Check if cycle exist between 2 valid windows */
444 for (cnt = 1; cnt <= row_index; cnt++) {
445 if (phases_per_row[cnt]) {
446 for (i = 0; i < phases_per_row[cnt]; i++) {
447 if (ranges[cnt][i] == 15) {
448 phase_15_found = true;
449 phase_15_raw_index = cnt;
450 break;
451 }
452 }
453 }
454 }
455 }
456
457 /* If 2 valid windows form cycle then merge them as single window */
458 if (phase_0_found && phase_15_found) {
459 /* number of phases in raw where phase 0 is present */
460 u8 phases_0 = phases_per_row[phase_0_raw_index];
461 /* number of phases in raw where phase 15 is present */
462 u8 phases_15 = phases_per_row[phase_15_raw_index];
463
464 if (phases_0 + phases_15 >= MAX_PHASES)
465 /*
466 * If there are more than 1 phase windows then total
467 * number of phases in both the windows should not be
468 * more than or equal to MAX_PHASES.
469 */
470 return -EINVAL;
471
472 /* Merge 2 cyclic windows */
473 i = phases_15;
474 for (cnt = 0; cnt < phases_0; cnt++) {
475 ranges[phase_15_raw_index][i] =
476 ranges[phase_0_raw_index][cnt];
477 if (++i >= MAX_PHASES)
478 break;
479 }
480
481 phases_per_row[phase_0_raw_index] = 0;
482 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
483 }
484
485 for (cnt = 0; cnt <= row_index; cnt++) {
486 if (phases_per_row[cnt] > curr_max) {
487 curr_max = phases_per_row[cnt];
488 selected_row_index = cnt;
489 }
490 }
491
492 i = ((curr_max * 3) / 4);
493 if (i)
494 i--;
495
496 ret = (int)ranges[selected_row_index][i];
497
498 if (ret >= MAX_PHASES) {
499 ret = -EINVAL;
500 pr_err("%s: %s: invalid phase selected=%d\n",
501 mmc_hostname(mmc), __func__, ret);
502 }
503
504 pr_debug("%s: Exit %s\n", mmc_hostname(mmc), __func__);
505 return ret;
506}
507
508static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
509{
510 u32 mclk_freq = 0;
511
512 /* Program the MCLK value to MCLK_FREQ bit field */
513 if (host->clock <= 112000000)
514 mclk_freq = 0;
515 else if (host->clock <= 125000000)
516 mclk_freq = 1;
517 else if (host->clock <= 137000000)
518 mclk_freq = 2;
519 else if (host->clock <= 150000000)
520 mclk_freq = 3;
521 else if (host->clock <= 162000000)
522 mclk_freq = 4;
523 else if (host->clock <= 175000000)
524 mclk_freq = 5;
525 else if (host->clock <= 187000000)
526 mclk_freq = 6;
527 else if (host->clock <= 200000000)
528 mclk_freq = 7;
529
530 writel_relaxed(((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
531 & ~(7 << 24)) | (mclk_freq << 24)),
532 host->ioaddr + CORE_DLL_CONFIG);
533}
534
535/* Initialize the DLL (Programmable Delay Line ) */
536static int msm_init_cm_dll(struct sdhci_host *host)
537{
Venkat Gopalakrishnanc0a5c3a2015-02-03 16:10:07 -0800538 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
539 struct sdhci_msm_host *msm_host = pltfm_host->priv;
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700540 struct mmc_host *mmc = host->mmc;
541 int rc = 0;
542 unsigned long flags;
543 u32 wait_cnt;
Subhash Jadavani99bca3b2013-05-28 18:21:57 +0530544 bool prev_pwrsave, curr_pwrsave;
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700545
546 pr_debug("%s: Enter %s\n", mmc_hostname(mmc), __func__);
547 spin_lock_irqsave(&host->lock, flags);
Subhash Jadavani99bca3b2013-05-28 18:21:57 +0530548 prev_pwrsave = !!(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) &
549 CORE_CLK_PWRSAVE);
550 curr_pwrsave = prev_pwrsave;
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700551 /*
552 * Make sure that clock is always enabled when DLL
553 * tuning is in progress. Keeping PWRSAVE ON may
554 * turn off the clock. So let's disable the PWRSAVE
555 * here and re-enable it once tuning is completed.
556 */
Subhash Jadavani99bca3b2013-05-28 18:21:57 +0530557 if (prev_pwrsave) {
558 writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
559 & ~CORE_CLK_PWRSAVE),
560 host->ioaddr + CORE_VENDOR_SPEC);
561 curr_pwrsave = false;
562 }
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700563
Venkat Gopalakrishnanc0a5c3a2015-02-03 16:10:07 -0800564 if (msm_host->use_updated_dll_reset) {
565 /* Disable the DLL clock */
566 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
567 & ~CORE_CK_OUT_EN),
568 host->ioaddr + CORE_DLL_CONFIG);
569
570 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2)
571 | CORE_DLL_CLOCK_DISABLE),
572 host->ioaddr + CORE_DLL_CONFIG_2);
573 }
574
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700575 /* Write 1 to DLL_RST bit of DLL_CONFIG register */
576 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
577 | CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);
578
579 /* Write 1 to DLL_PDN bit of DLL_CONFIG register */
580 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
581 | CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);
582 msm_cm_dll_set_freq(host);
583
Venkat Gopalakrishnanc0a5c3a2015-02-03 16:10:07 -0800584 if (msm_host->use_updated_dll_reset) {
585 u32 mclk_freq = 0;
586
587 if ((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2)
588 & CORE_FLL_CYCLE_CNT))
589 mclk_freq = (u32) ((host->clock / TCXO_FREQ) * 8);
590 else
591 mclk_freq = (u32) ((host->clock / TCXO_FREQ) * 4);
592
593 writel_relaxed(((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2)
594 & ~(0xFF << 10)) | (mclk_freq << 10)),
595 host->ioaddr + CORE_DLL_CONFIG_2);
596 /* wait for 5us before enabling DLL clock */
597 udelay(5);
598 }
599
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700600 /* Write 0 to DLL_RST bit of DLL_CONFIG register */
601 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
602 & ~CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);
603
604 /* Write 0 to DLL_PDN bit of DLL_CONFIG register */
605 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
606 & ~CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);
607
Venkat Gopalakrishnanc0a5c3a2015-02-03 16:10:07 -0800608 if (msm_host->use_updated_dll_reset) {
609 msm_cm_dll_set_freq(host);
610 /* Enable the DLL clock */
611 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2)
612 & ~CORE_DLL_CLOCK_DISABLE),
613 host->ioaddr + CORE_DLL_CONFIG_2);
614 }
615
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700616 /* Set DLL_EN bit to 1. */
617 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
618 | CORE_DLL_EN), host->ioaddr + CORE_DLL_CONFIG);
619
620 /* Set CK_OUT_EN bit to 1. */
621 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
622 | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
623
624 wait_cnt = 50;
625 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
626 while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) &
627 CORE_DLL_LOCK)) {
628 /* max. wait for 50us sec for LOCK bit to be set */
629 if (--wait_cnt == 0) {
630 pr_err("%s: %s: DLL failed to LOCK\n",
631 mmc_hostname(mmc), __func__);
632 rc = -ETIMEDOUT;
633 goto out;
634 }
635 /* wait for 1us before polling again */
636 udelay(1);
637 }
638
639out:
Subhash Jadavani99bca3b2013-05-28 18:21:57 +0530640 /* Restore the correct PWRSAVE state */
641 if (prev_pwrsave ^ curr_pwrsave) {
642 u32 reg = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
643
644 if (prev_pwrsave)
645 reg |= CORE_CLK_PWRSAVE;
646 else
647 reg &= ~CORE_CLK_PWRSAVE;
648
649 writel_relaxed(reg, host->ioaddr + CORE_VENDOR_SPEC);
650 }
651
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700652 spin_unlock_irqrestore(&host->lock, flags);
653 pr_debug("%s: Exit %s\n", mmc_hostname(mmc), __func__);
654 return rc;
655}
656
Venkat Gopalakrishnan9e069632013-06-12 11:16:37 -0700657static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
658{
Krishna Konda2faa7bb2014-06-04 01:25:16 -0700659 u32 calib_done;
Venkat Gopalakrishnan9e069632013-06-12 11:16:37 -0700660 int ret = 0;
661 int cdc_err = 0;
Venkat Gopalakrishnan9e069632013-06-12 11:16:37 -0700662
663 pr_debug("%s: Enter %s\n", mmc_hostname(host->mmc), __func__);
664
Venkat Gopalakrishnan9e069632013-06-12 11:16:37 -0700665 /* Write 0 to CDC_T4_DLY_SEL field in VENDOR_SPEC_DDR200_CFG */
666 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DDR_200_CFG)
667 & ~CORE_CDC_T4_DLY_SEL),
668 host->ioaddr + CORE_DDR_200_CFG);
669
670 /* Write 0 to CDC_SWITCH_BYPASS_OFF field in CORE_CSR_CDC_GEN_CFG */
671 writel_relaxed((readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG)
672 & ~CORE_CDC_SWITCH_BYPASS_OFF),
673 host->ioaddr + CORE_CSR_CDC_GEN_CFG);
674
675 /* Write 1 to CDC_SWITCH_RC_EN field in CORE_CSR_CDC_GEN_CFG */
676 writel_relaxed((readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG)
677 | CORE_CDC_SWITCH_RC_EN),
678 host->ioaddr + CORE_CSR_CDC_GEN_CFG);
679
680 /* Write 0 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */
681 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DDR_200_CFG)
682 & ~CORE_START_CDC_TRAFFIC),
683 host->ioaddr + CORE_DDR_200_CFG);
684
685 /*
686 * Perform CDC Register Initialization Sequence
687 *
688 * CORE_CSR_CDC_CTLR_CFG0 0x11800EC
689 * CORE_CSR_CDC_CTLR_CFG1 0x3011111
690 * CORE_CSR_CDC_CAL_TIMER_CFG0 0x1201000
691 * CORE_CSR_CDC_CAL_TIMER_CFG1 0x4
692 * CORE_CSR_CDC_REFCOUNT_CFG 0xCB732020
693 * CORE_CSR_CDC_COARSE_CAL_CFG 0xB19
694 * CORE_CSR_CDC_DELAY_CFG 0x3AC
695 * CORE_CDC_OFFSET_CFG 0x0
696 * CORE_CDC_SLAVE_DDA_CFG 0x16334
697 */
698
699 writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
700 writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
701 writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
702 writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
703 writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
704 writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
Subhash Jadavanibe406d92014-06-17 16:47:48 -0700705 writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
Venkat Gopalakrishnan9e069632013-06-12 11:16:37 -0700706 writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
707 writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
708
709 /* CDC HW Calibration */
710
711 /* Write 1 to SW_TRIG_FULL_CALIB field in CORE_CSR_CDC_CTLR_CFG0 */
712 writel_relaxed((readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0)
713 | CORE_SW_TRIG_FULL_CALIB),
714 host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
715
716 /* Write 0 to SW_TRIG_FULL_CALIB field in CORE_CSR_CDC_CTLR_CFG0 */
717 writel_relaxed((readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0)
718 & ~CORE_SW_TRIG_FULL_CALIB),
719 host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
720
721 /* Write 1 to HW_AUTOCAL_ENA field in CORE_CSR_CDC_CTLR_CFG0 */
722 writel_relaxed((readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0)
723 | CORE_HW_AUTOCAL_ENA),
724 host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
725
726 /* Write 1 to TIMER_ENA field in CORE_CSR_CDC_CAL_TIMER_CFG0 */
727 writel_relaxed((readl_relaxed(host->ioaddr +
728 CORE_CSR_CDC_CAL_TIMER_CFG0) | CORE_TIMER_ENA),
729 host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
730
731 mb();
732
733 /* Poll on CALIBRATION_DONE field in CORE_CSR_CDC_STATUS0 to be 1 */
Krishna Konda2faa7bb2014-06-04 01:25:16 -0700734 ret = readl_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
735 calib_done, (calib_done & CORE_CALIBRATION_DONE), 1, 50);
736
737 if (ret == -ETIMEDOUT) {
738 pr_err("%s: %s: CDC Calibration was not completed\n",
Venkat Gopalakrishnan9e069632013-06-12 11:16:37 -0700739 mmc_hostname(host->mmc), __func__);
Krishna Konda2faa7bb2014-06-04 01:25:16 -0700740 goto out;
Venkat Gopalakrishnan9e069632013-06-12 11:16:37 -0700741 }
742
743 /* Verify CDC_ERROR_CODE field in CORE_CSR_CDC_STATUS0 is 0 */
744 cdc_err = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
745 & CORE_CDC_ERROR_CODE_MASK;
746 if (cdc_err) {
747 pr_err("%s: %s: CDC Error Code %d\n",
748 mmc_hostname(host->mmc), __func__, cdc_err);
749 ret = -EINVAL;
750 goto out;
751 }
752
753 /* Write 1 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */
754 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DDR_200_CFG)
755 | CORE_START_CDC_TRAFFIC),
756 host->ioaddr + CORE_DDR_200_CFG);
757out:
758 pr_debug("%s: Exit %s, ret:%d\n", mmc_hostname(host->mmc),
759 __func__, ret);
760 return ret;
761}
762
Krishna Konda2faa7bb2014-06-04 01:25:16 -0700763static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
764{
Ritesh Harjani764065e2015-05-13 14:14:45 +0530765 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
766 struct sdhci_msm_host *msm_host = pltfm_host->priv;
Krishna Konda2faa7bb2014-06-04 01:25:16 -0700767 u32 dll_status;
768 int ret = 0;
769
770 pr_debug("%s: Enter %s\n", mmc_hostname(host->mmc), __func__);
771
772 /*
773 * Currently the CORE_DDR_CONFIG register defaults to desired
774 * configuration on reset. Currently reprogramming the power on
775 * reset (POR) value in case it might have been modified by
776 * bootloaders. In the future, if this changes, then the desired
777 * values will need to be programmed appropriately.
778 */
779 writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + CORE_DDR_CONFIG);
780
Ritesh Harjaniea709662015-05-27 15:40:24 +0530781 if (msm_host->enhanced_strobe)
782 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DDR_200_CFG)
783 | CORE_CMDIN_RCLK_EN),
784 host->ioaddr + CORE_DDR_200_CFG);
785
Krishna Konda2faa7bb2014-06-04 01:25:16 -0700786 /* Write 1 to DDR_CAL_EN field in CORE_DLL_CONFIG_2 */
787 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2)
788 | CORE_DDR_CAL_EN),
789 host->ioaddr + CORE_DLL_CONFIG_2);
790
791 /* Poll on DDR_DLL_LOCK bit in CORE_DLL_STATUS to be set */
792 ret = readl_poll_timeout(host->ioaddr + CORE_DLL_STATUS,
793 dll_status, (dll_status & CORE_DDR_DLL_LOCK), 10, 1000);
794
795 if (ret == -ETIMEDOUT) {
796 pr_err("%s: %s: CM_DLL_SDC4 Calibration was not completed\n",
797 mmc_hostname(host->mmc), __func__);
798 goto out;
799 }
800
Ritesh Harjani764065e2015-05-13 14:14:45 +0530801 /*
802 * set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3.
803 * when MCLK is gated OFF, it is not gated for less than 0.5us
804 * and MCLK must be switched on for at-least 1us before DATA
805 * starts coming. Controllers with 14lpp tech DLL cannot
806 * guarantee above requirement. So PWRSAVE_DLL should not be
807 * turned on for host controllers using this DLL.
808 */
809 if (!msm_host->use_14lpp_dll)
810 writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC3)
811 | CORE_PWRSAVE_DLL),
812 host->ioaddr + CORE_VENDOR_SPEC3);
Krishna Konda2faa7bb2014-06-04 01:25:16 -0700813 mb();
814out:
815 pr_debug("%s: Exit %s, ret:%d\n", mmc_hostname(host->mmc),
816 __func__, ret);
817 return ret;
818}
819
Ritesh Harjaniea709662015-05-27 15:40:24 +0530820static int sdhci_msm_enhanced_strobe(struct sdhci_host *host)
821{
822 int ret = 0;
823 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
824 struct sdhci_msm_host *msm_host = pltfm_host->priv;
825 struct mmc_host *mmc = host->mmc;
826
827 pr_debug("%s: Enter %s\n", mmc_hostname(host->mmc), __func__);
828
829 if (!msm_host->enhanced_strobe) {
830 pr_debug("%s: host does not support hs400 enhanced strobe\n",
831 mmc_hostname(mmc));
832 return -EINVAL;
833 }
834
835 if (msm_host->calibration_done ||
836 !(mmc->ios.timing == MMC_TIMING_MMC_HS400)) {
837 return 0;
838 }
839
840 /*
841 * Reset the tuning block.
842 */
843 ret = msm_init_cm_dll(host);
844 if (ret)
845 goto out;
846
847 ret = sdhci_msm_cm_dll_sdc4_calibration(host);
848out:
849 if (!ret)
850 msm_host->calibration_done = true;
851 pr_debug("%s: Exit %s, ret:%d\n", mmc_hostname(host->mmc),
852 __func__, ret);
853 return ret;
854}
855
Krishna Konda2faa7bb2014-06-04 01:25:16 -0700856static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
857{
858 int ret = 0;
859 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
860 struct sdhci_msm_host *msm_host = pltfm_host->priv;
861
862 pr_debug("%s: Enter %s\n", mmc_hostname(host->mmc), __func__);
863
864 /*
865 * Retuning in HS400 (DDR mode) will fail, just reset the
866 * tuning block and restore the saved tuning phase.
867 */
868 ret = msm_init_cm_dll(host);
869 if (ret)
870 goto out;
871
872 /* Set the selected phase in delay line hw block */
873 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
874 if (ret)
875 goto out;
876
Krishna Konda0e8efba2014-06-23 14:50:38 -0700877 /* Write 1 to CMD_DAT_TRACK_SEL field in DLL_CONFIG */
878 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
879 | CORE_CMD_DAT_TRACK_SEL),
880 host->ioaddr + CORE_DLL_CONFIG);
881
Krishna Konda2faa7bb2014-06-04 01:25:16 -0700882 if (msm_host->use_cdclp533)
883 /* Calibrate CDCLP533 DLL HW */
884 ret = sdhci_msm_cdclp533_calibration(host);
885 else
886 /* Calibrate CM_DLL_SDC4 HW */
887 ret = sdhci_msm_cm_dll_sdc4_calibration(host);
888out:
889 pr_debug("%s: Exit %s, ret:%d\n", mmc_hostname(host->mmc),
890 __func__, ret);
891 return ret;
892}
893
Krishna Konda96e6b112013-10-28 15:25:03 -0700894static void sdhci_msm_set_mmc_drv_type(struct sdhci_host *host, u32 opcode,
895 u8 drv_type)
896{
897 struct mmc_command cmd = {0};
898 struct mmc_request mrq = {NULL};
899 struct mmc_host *mmc = host->mmc;
900 u8 val = ((drv_type << 4) | 2);
901
902 cmd.opcode = MMC_SWITCH;
903 cmd.arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
904 (EXT_CSD_HS_TIMING << 16) |
905 (val << 8) |
906 EXT_CSD_CMD_SET_NORMAL;
907 cmd.flags = MMC_CMD_AC | MMC_RSP_R1B;
908 /* 1 sec */
909 cmd.busy_timeout = 1000 * 1000;
910
911 memset(cmd.resp, 0, sizeof(cmd.resp));
912 cmd.retries = 3;
913
914 mrq.cmd = &cmd;
915 cmd.data = NULL;
916
917 mmc_wait_for_req(mmc, &mrq);
918 pr_debug("%s: %s: set card drive type to %d\n",
919 mmc_hostname(mmc), __func__,
920 drv_type);
921}
922
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700923int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
924{
925 unsigned long flags;
Sahitya Tummala9fe16532013-06-13 10:36:57 +0530926 int tuning_seq_cnt = 3;
Krishna Konda96e6b112013-10-28 15:25:03 -0700927 u8 phase, *data_buf, tuned_phases[NUM_TUNING_PHASES], tuned_phase_cnt;
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700928 const u32 *tuning_block_pattern = tuning_block_64;
929 int size = sizeof(tuning_block_64); /* Tuning pattern size in bytes */
930 int rc;
931 struct mmc_host *mmc = host->mmc;
Sahitya Tummala22dd3362013-02-28 19:50:51 +0530932 struct mmc_ios ios = host->mmc->ios;
Venkat Gopalakrishnan9e069632013-06-12 11:16:37 -0700933 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
934 struct sdhci_msm_host *msm_host = pltfm_host->priv;
Krishna Konda96e6b112013-10-28 15:25:03 -0700935 u8 drv_type = 0;
936 bool drv_type_changed = false;
937 struct mmc_card *card = host->mmc->card;
Sahitya Tummalafaff7f82015-02-25 14:24:52 +0530938 int sts_retry;
Sahitya Tummala22dd3362013-02-28 19:50:51 +0530939
940 /*
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -0700941 * Tuning is required for SDR104, HS200 and HS400 cards and
942 * if clock frequency is greater than 100MHz in these modes.
Sahitya Tummala22dd3362013-02-28 19:50:51 +0530943 */
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -0700944 if (host->clock <= CORE_FREQ_100MHZ ||
945 !((ios.timing == MMC_TIMING_MMC_HS400) ||
946 (ios.timing == MMC_TIMING_MMC_HS200) ||
947 (ios.timing == MMC_TIMING_UHS_SDR104)))
Sahitya Tummala22dd3362013-02-28 19:50:51 +0530948 return 0;
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700949
950 pr_debug("%s: Enter %s\n", mmc_hostname(mmc), __func__);
Venkat Gopalakrishnan9e069632013-06-12 11:16:37 -0700951
Krishna Konda2faa7bb2014-06-04 01:25:16 -0700952 /* CDC/SDC4 DLL HW calibration is only required for HS400 mode*/
Venkat Gopalakrishnan9e069632013-06-12 11:16:37 -0700953 if (msm_host->tuning_done && !msm_host->calibration_done &&
954 (mmc->ios.timing == MMC_TIMING_MMC_HS400)) {
Krishna Konda2faa7bb2014-06-04 01:25:16 -0700955 rc = sdhci_msm_hs400_dll_calibration(host);
Venkat Gopalakrishnan9e069632013-06-12 11:16:37 -0700956 spin_lock_irqsave(&host->lock, flags);
957 if (!rc)
958 msm_host->calibration_done = true;
959 spin_unlock_irqrestore(&host->lock, flags);
960 goto out;
961 }
962
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700963 spin_lock_irqsave(&host->lock, flags);
964
965 if ((opcode == MMC_SEND_TUNING_BLOCK_HS200) &&
966 (mmc->ios.bus_width == MMC_BUS_WIDTH_8)) {
967 tuning_block_pattern = tuning_block_128;
968 size = sizeof(tuning_block_128);
969 }
970 spin_unlock_irqrestore(&host->lock, flags);
971
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700972 data_buf = kmalloc(size, GFP_KERNEL);
973 if (!data_buf) {
974 rc = -ENOMEM;
975 goto out;
976 }
977
Sahitya Tummala9fe16532013-06-13 10:36:57 +0530978retry:
Krishna Konda96e6b112013-10-28 15:25:03 -0700979 tuned_phase_cnt = 0;
980
Sahitya Tummala9fe16532013-06-13 10:36:57 +0530981 /* first of all reset the tuning block */
982 rc = msm_init_cm_dll(host);
983 if (rc)
984 goto kfree;
985
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700986 phase = 0;
987 do {
988 struct mmc_command cmd = {0};
989 struct mmc_data data = {0};
990 struct mmc_request mrq = {
991 .cmd = &cmd,
992 .data = &data
993 };
994 struct scatterlist sg;
Sahitya Tummalafaff7f82015-02-25 14:24:52 +0530995 struct mmc_command sts_cmd = {0};
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -0700996
997 /* set the phase in delay line hw block */
998 rc = msm_config_cm_dll_phase(host, phase);
999 if (rc)
1000 goto kfree;
1001
1002 cmd.opcode = opcode;
1003 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1004
1005 data.blksz = size;
1006 data.blocks = 1;
1007 data.flags = MMC_DATA_READ;
1008 data.timeout_ns = 1000 * 1000 * 1000; /* 1 sec */
1009
1010 data.sg = &sg;
1011 data.sg_len = 1;
1012 sg_init_one(&sg, data_buf, size);
1013 memset(data_buf, 0, size);
1014 mmc_wait_for_req(mmc, &mrq);
1015
Sahitya Tummalafaff7f82015-02-25 14:24:52 +05301016 if (card && (cmd.error || data.error)) {
1017 sts_cmd.opcode = MMC_SEND_STATUS;
1018 sts_cmd.arg = card->rca << 16;
1019 sts_cmd.flags = MMC_RSP_R1 | MMC_CMD_AC;
1020 sts_retry = 5;
1021 while (sts_retry) {
1022 mmc_wait_for_cmd(mmc, &sts_cmd, 0);
1023
1024 if (sts_cmd.error ||
1025 (R1_CURRENT_STATE(sts_cmd.resp[0])
1026 != R1_STATE_TRAN)) {
1027 sts_retry--;
1028 /*
1029 * wait for at least 146 MCLK cycles for
1030 * the card to move to TRANS state. As
1031 * the MCLK would be min 200MHz for
1032 * tuning, we need max 0.73us delay. To
1033 * be on safer side 1ms delay is given.
1034 */
1035 usleep_range(1000, 1200);
1036 pr_debug("%s: phase %d sts cmd err %d resp 0x%x\n",
1037 mmc_hostname(mmc), phase,
1038 sts_cmd.error, sts_cmd.resp[0]);
1039 continue;
1040 }
1041 break;
1042 };
1043 }
1044
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -07001045 if (!cmd.error && !data.error &&
1046 !memcmp(data_buf, tuning_block_pattern, size)) {
1047 /* tuning is successful at this tuning point */
1048 tuned_phases[tuned_phase_cnt++] = phase;
Krishna Konda96e6b112013-10-28 15:25:03 -07001049 pr_debug("%s: %s: found *** good *** phase = %d\n",
1050 mmc_hostname(mmc), __func__, phase);
1051 } else {
1052 pr_debug("%s: %s: found ## bad ## phase = %d\n",
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -07001053 mmc_hostname(mmc), __func__, phase);
1054 }
1055 } while (++phase < 16);
1056
Sahitya Tummaladfdb4af2014-04-01 14:29:13 +05301057 if ((tuned_phase_cnt == NUM_TUNING_PHASES) &&
1058 card && mmc_card_mmc(card)) {
Krishna Konda96e6b112013-10-28 15:25:03 -07001059 /*
1060 * If all phases pass then its a problem. So change the card's
1061 * drive type to a different value, if supported and repeat
1062 * tuning until at least one phase fails. Then set the original
1063 * drive type back.
1064 *
1065 * If all the phases still pass after trying all possible
1066 * drive types, then one of those 16 phases will be picked.
1067 * This is no different from what was going on before the
1068 * modification to change drive type and retune.
1069 */
1070 pr_debug("%s: tuned phases count: %d\n", mmc_hostname(mmc),
1071 tuned_phase_cnt);
1072
1073 /* set drive type to other value . default setting is 0x0 */
1074 while (++drv_type <= MAX_DRV_TYPES_SUPPORTED_HS200) {
1075 if (card->ext_csd.raw_driver_strength &
1076 (1 << drv_type)) {
1077 sdhci_msm_set_mmc_drv_type(host, opcode,
1078 drv_type);
1079 if (!drv_type_changed)
1080 drv_type_changed = true;
1081 goto retry;
1082 }
1083 }
1084 }
1085
1086 /* reset drive type to default (50 ohm) if changed */
1087 if (drv_type_changed)
1088 sdhci_msm_set_mmc_drv_type(host, opcode, 0);
1089
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -07001090 if (tuned_phase_cnt) {
1091 rc = msm_find_most_appropriate_phase(host, tuned_phases,
1092 tuned_phase_cnt);
1093 if (rc < 0)
1094 goto kfree;
1095 else
1096 phase = (u8)rc;
1097
1098 /*
1099 * Finally set the selected phase in delay
1100 * line hw block.
1101 */
1102 rc = msm_config_cm_dll_phase(host, phase);
1103 if (rc)
1104 goto kfree;
Venkat Gopalakrishnan9e069632013-06-12 11:16:37 -07001105 msm_host->saved_tuning_phase = phase;
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -07001106 pr_debug("%s: %s: finally setting the tuning phase to %d\n",
1107 mmc_hostname(mmc), __func__, phase);
1108 } else {
Sahitya Tummala9fe16532013-06-13 10:36:57 +05301109 if (--tuning_seq_cnt)
1110 goto retry;
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -07001111 /* tuning failed */
1112 pr_err("%s: %s: no tuning point found\n",
1113 mmc_hostname(mmc), __func__);
Sahitya Tummala9fe16532013-06-13 10:36:57 +05301114 rc = -EIO;
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -07001115 }
1116
1117kfree:
1118 kfree(data_buf);
1119out:
Venkat Gopalakrishnan9e069632013-06-12 11:16:37 -07001120 spin_lock_irqsave(&host->lock, flags);
1121 if (!rc)
1122 msm_host->tuning_done = true;
1123 spin_unlock_irqrestore(&host->lock, flags);
1124 pr_debug("%s: Exit %s, err(%d)\n", mmc_hostname(mmc), __func__, rc);
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -07001125 return rc;
1126}
1127
Asutosh Das0ef24812012-12-18 16:14:02 +05301128static int sdhci_msm_setup_gpio(struct sdhci_msm_pltfm_data *pdata, bool enable)
1129{
1130 struct sdhci_msm_gpio_data *curr;
1131 int i, ret = 0;
1132
1133 curr = pdata->pin_data->gpio_data;
1134 for (i = 0; i < curr->size; i++) {
1135 if (!gpio_is_valid(curr->gpio[i].no)) {
1136 ret = -EINVAL;
1137 pr_err("%s: Invalid gpio = %d\n", __func__,
1138 curr->gpio[i].no);
1139 goto free_gpios;
1140 }
1141 if (enable) {
1142 ret = gpio_request(curr->gpio[i].no,
1143 curr->gpio[i].name);
1144 if (ret) {
1145 pr_err("%s: gpio_request(%d, %s) failed %d\n",
1146 __func__, curr->gpio[i].no,
1147 curr->gpio[i].name, ret);
1148 goto free_gpios;
1149 }
1150 curr->gpio[i].is_enabled = true;
1151 } else {
1152 gpio_free(curr->gpio[i].no);
1153 curr->gpio[i].is_enabled = false;
1154 }
1155 }
1156 return ret;
1157
1158free_gpios:
1159 for (i--; i >= 0; i--) {
1160 gpio_free(curr->gpio[i].no);
1161 curr->gpio[i].is_enabled = false;
1162 }
1163 return ret;
1164}
1165
Pratibhasagar V9acf2642013-11-21 21:07:21 +05301166static int sdhci_msm_setup_pinctrl(struct sdhci_msm_pltfm_data *pdata,
1167 bool enable)
1168{
1169 int ret = 0;
1170
1171 if (enable)
1172 ret = pinctrl_select_state(pdata->pctrl_data->pctrl,
1173 pdata->pctrl_data->pins_active);
1174 else
1175 ret = pinctrl_select_state(pdata->pctrl_data->pctrl,
1176 pdata->pctrl_data->pins_sleep);
1177
1178 if (ret < 0)
1179 pr_err("%s state for pinctrl failed with %d\n",
1180 enable ? "Enabling" : "Disabling", ret);
1181
1182 return ret;
1183}
1184
Asutosh Das0ef24812012-12-18 16:14:02 +05301185static int sdhci_msm_setup_pins(struct sdhci_msm_pltfm_data *pdata, bool enable)
1186{
1187 int ret = 0;
1188
Pratibhasagar V9acf2642013-11-21 21:07:21 +05301189 if (pdata->pin_cfg_sts == enable) {
Asutosh Das0ef24812012-12-18 16:14:02 +05301190 return 0;
Pratibhasagar V9acf2642013-11-21 21:07:21 +05301191 } else if (pdata->pctrl_data) {
1192 ret = sdhci_msm_setup_pinctrl(pdata, enable);
1193 goto out;
1194 } else if (!pdata->pin_data) {
1195 return 0;
1196 }
Asutosh Das0ef24812012-12-18 16:14:02 +05301197
Sahitya Tummala1cd7e072014-02-14 13:19:01 +05301198 if (pdata->pin_data->is_gpio)
1199 ret = sdhci_msm_setup_gpio(pdata, enable);
Pratibhasagar V9acf2642013-11-21 21:07:21 +05301200out:
Asutosh Das0ef24812012-12-18 16:14:02 +05301201 if (!ret)
Pratibhasagar V9acf2642013-11-21 21:07:21 +05301202 pdata->pin_cfg_sts = enable;
Asutosh Das0ef24812012-12-18 16:14:02 +05301203
1204 return ret;
1205}
1206
Sahitya Tummala8a3e8182013-03-10 14:12:52 +05301207static int sdhci_msm_dt_get_array(struct device *dev, const char *prop_name,
1208 u32 **out, int *len, u32 size)
1209{
1210 int ret = 0;
1211 struct device_node *np = dev->of_node;
1212 size_t sz;
1213 u32 *arr = NULL;
1214
1215 if (!of_get_property(np, prop_name, len)) {
1216 ret = -EINVAL;
1217 goto out;
1218 }
1219 sz = *len = *len / sizeof(*arr);
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -07001220 if (sz <= 0 || (size > 0 && (sz > size))) {
Sahitya Tummala8a3e8182013-03-10 14:12:52 +05301221 dev_err(dev, "%s invalid size\n", prop_name);
1222 ret = -EINVAL;
1223 goto out;
1224 }
1225
1226 arr = devm_kzalloc(dev, sz * sizeof(*arr), GFP_KERNEL);
1227 if (!arr) {
1228 dev_err(dev, "%s failed allocating memory\n", prop_name);
1229 ret = -ENOMEM;
1230 goto out;
1231 }
1232
1233 ret = of_property_read_u32_array(np, prop_name, arr, sz);
1234 if (ret < 0) {
1235 dev_err(dev, "%s failed reading array %d\n", prop_name, ret);
1236 goto out;
1237 }
1238 *out = arr;
1239out:
1240 if (ret)
1241 *len = 0;
1242 return ret;
1243}
1244
Asutosh Das0ef24812012-12-18 16:14:02 +05301245#define MAX_PROP_SIZE 32
1246static int sdhci_msm_dt_parse_vreg_info(struct device *dev,
1247 struct sdhci_msm_reg_data **vreg_data, const char *vreg_name)
1248{
1249 int len, ret = 0;
1250 const __be32 *prop;
1251 char prop_name[MAX_PROP_SIZE];
1252 struct sdhci_msm_reg_data *vreg;
1253 struct device_node *np = dev->of_node;
1254
1255 snprintf(prop_name, MAX_PROP_SIZE, "%s-supply", vreg_name);
1256 if (!of_parse_phandle(np, prop_name, 0)) {
Asutosh Dasc58cc7a2013-06-28 15:03:44 +05301257 dev_info(dev, "No vreg data found for %s\n", vreg_name);
Asutosh Das0ef24812012-12-18 16:14:02 +05301258 return ret;
1259 }
1260
1261 vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL);
1262 if (!vreg) {
1263 dev_err(dev, "No memory for vreg: %s\n", vreg_name);
1264 ret = -ENOMEM;
1265 return ret;
1266 }
1267
1268 vreg->name = vreg_name;
1269
1270 snprintf(prop_name, MAX_PROP_SIZE,
1271 "qcom,%s-always-on", vreg_name);
1272 if (of_get_property(np, prop_name, NULL))
1273 vreg->is_always_on = true;
1274
1275 snprintf(prop_name, MAX_PROP_SIZE,
1276 "qcom,%s-lpm-sup", vreg_name);
1277 if (of_get_property(np, prop_name, NULL))
1278 vreg->lpm_sup = true;
1279
1280 snprintf(prop_name, MAX_PROP_SIZE,
1281 "qcom,%s-voltage-level", vreg_name);
1282 prop = of_get_property(np, prop_name, &len);
1283 if (!prop || (len != (2 * sizeof(__be32)))) {
1284 dev_warn(dev, "%s %s property\n",
1285 prop ? "invalid format" : "no", prop_name);
1286 } else {
1287 vreg->low_vol_level = be32_to_cpup(&prop[0]);
1288 vreg->high_vol_level = be32_to_cpup(&prop[1]);
1289 }
1290
1291 snprintf(prop_name, MAX_PROP_SIZE,
1292 "qcom,%s-current-level", vreg_name);
1293 prop = of_get_property(np, prop_name, &len);
1294 if (!prop || (len != (2 * sizeof(__be32)))) {
1295 dev_warn(dev, "%s %s property\n",
1296 prop ? "invalid format" : "no", prop_name);
1297 } else {
1298 vreg->lpm_uA = be32_to_cpup(&prop[0]);
1299 vreg->hpm_uA = be32_to_cpup(&prop[1]);
1300 }
1301
1302 *vreg_data = vreg;
1303 dev_dbg(dev, "%s: %s %s vol=[%d %d]uV, curr=[%d %d]uA\n",
1304 vreg->name, vreg->is_always_on ? "always_on," : "",
1305 vreg->lpm_sup ? "lpm_sup," : "", vreg->low_vol_level,
1306 vreg->high_vol_level, vreg->lpm_uA, vreg->hpm_uA);
1307
1308 return ret;
1309}
1310
Pratibhasagar V9acf2642013-11-21 21:07:21 +05301311static int sdhci_msm_parse_pinctrl_info(struct device *dev,
1312 struct sdhci_msm_pltfm_data *pdata)
1313{
1314 struct sdhci_pinctrl_data *pctrl_data;
1315 struct pinctrl *pctrl;
1316 int ret = 0;
1317
1318 /* Try to obtain pinctrl handle */
1319 pctrl = devm_pinctrl_get(dev);
1320 if (IS_ERR(pctrl)) {
1321 ret = PTR_ERR(pctrl);
1322 goto out;
1323 }
1324 pctrl_data = devm_kzalloc(dev, sizeof(*pctrl_data), GFP_KERNEL);
1325 if (!pctrl_data) {
1326 dev_err(dev, "No memory for sdhci_pinctrl_data\n");
1327 ret = -ENOMEM;
1328 goto out;
1329 }
1330 pctrl_data->pctrl = pctrl;
1331 /* Look-up and keep the states handy to be used later */
1332 pctrl_data->pins_active = pinctrl_lookup_state(
1333 pctrl_data->pctrl, "active");
1334 if (IS_ERR(pctrl_data->pins_active)) {
1335 ret = PTR_ERR(pctrl_data->pins_active);
1336 dev_err(dev, "Could not get active pinstates, err:%d\n", ret);
1337 goto out;
1338 }
1339 pctrl_data->pins_sleep = pinctrl_lookup_state(
1340 pctrl_data->pctrl, "sleep");
1341 if (IS_ERR(pctrl_data->pins_sleep)) {
1342 ret = PTR_ERR(pctrl_data->pins_sleep);
1343 dev_err(dev, "Could not get sleep pinstates, err:%d\n", ret);
1344 goto out;
1345 }
1346 pdata->pctrl_data = pctrl_data;
1347out:
1348 return ret;
1349}
1350
Asutosh Das0ef24812012-12-18 16:14:02 +05301351#define GPIO_NAME_MAX_LEN 32
1352static int sdhci_msm_dt_parse_gpio_info(struct device *dev,
1353 struct sdhci_msm_pltfm_data *pdata)
1354{
1355 int ret = 0, cnt, i;
1356 struct sdhci_msm_pin_data *pin_data;
1357 struct device_node *np = dev->of_node;
1358
Pratibhasagar V9acf2642013-11-21 21:07:21 +05301359 ret = sdhci_msm_parse_pinctrl_info(dev, pdata);
1360 if (!ret) {
1361 goto out;
1362 } else if (ret == -EPROBE_DEFER) {
1363 dev_err(dev, "Pinctrl framework not registered, err:%d\n", ret);
1364 goto out;
1365 } else {
1366 dev_err(dev, "Parsing Pinctrl failed with %d, falling back on GPIO lib\n",
1367 ret);
Sahitya Tummala1cd7e072014-02-14 13:19:01 +05301368 ret = 0;
Pratibhasagar V9acf2642013-11-21 21:07:21 +05301369 }
Asutosh Das0ef24812012-12-18 16:14:02 +05301370 pin_data = devm_kzalloc(dev, sizeof(*pin_data), GFP_KERNEL);
1371 if (!pin_data) {
1372 dev_err(dev, "No memory for pin_data\n");
1373 ret = -ENOMEM;
1374 goto out;
1375 }
1376
1377 cnt = of_gpio_count(np);
1378 if (cnt > 0) {
1379 pin_data->gpio_data = devm_kzalloc(dev,
1380 sizeof(struct sdhci_msm_gpio_data), GFP_KERNEL);
1381 if (!pin_data->gpio_data) {
1382 dev_err(dev, "No memory for gpio_data\n");
1383 ret = -ENOMEM;
1384 goto out;
1385 }
1386 pin_data->gpio_data->size = cnt;
1387 pin_data->gpio_data->gpio = devm_kzalloc(dev, cnt *
1388 sizeof(struct sdhci_msm_gpio), GFP_KERNEL);
1389
1390 if (!pin_data->gpio_data->gpio) {
1391 dev_err(dev, "No memory for gpio\n");
1392 ret = -ENOMEM;
1393 goto out;
1394 }
1395
1396 for (i = 0; i < cnt; i++) {
1397 const char *name = NULL;
1398 char result[GPIO_NAME_MAX_LEN];
1399 pin_data->gpio_data->gpio[i].no = of_get_gpio(np, i);
1400 of_property_read_string_index(np,
1401 "qcom,gpio-names", i, &name);
1402
1403 snprintf(result, GPIO_NAME_MAX_LEN, "%s-%s",
1404 dev_name(dev), name ? name : "?");
1405 pin_data->gpio_data->gpio[i].name = result;
1406 dev_dbg(dev, "%s: gpio[%s] = %d\n", __func__,
1407 pin_data->gpio_data->gpio[i].name,
1408 pin_data->gpio_data->gpio[i].no);
Asutosh Das0ef24812012-12-18 16:14:02 +05301409 }
1410 }
Sahitya Tummala1cd7e072014-02-14 13:19:01 +05301411 pdata->pin_data = pin_data;
Asutosh Das0ef24812012-12-18 16:14:02 +05301412out:
1413 if (ret)
1414 dev_err(dev, "%s failed with err %d\n", __func__, ret);
1415 return ret;
1416}
1417
Maya Erez994cf2f2014-10-21 20:22:04 +03001418#ifdef CONFIG_SMP
1419static void sdhci_msm_populate_affinity_type(struct sdhci_msm_pltfm_data *pdata,
1420 struct device_node *np)
1421{
1422 const char *cpu_affinity = NULL;
1423
1424 pdata->cpu_affinity_type = PM_QOS_REQ_AFFINE_IRQ;
1425 if (!of_property_read_string(np, "qcom,cpu-affinity",
1426 &cpu_affinity)) {
1427 if (!strcmp(cpu_affinity, "all_cores"))
1428 pdata->cpu_affinity_type = PM_QOS_REQ_ALL_CORES;
1429 else if (!strcmp(cpu_affinity, "affine_cores"))
1430 pdata->cpu_affinity_type = PM_QOS_REQ_AFFINE_CORES;
1431 else if (!strcmp(cpu_affinity, "affine_irq"))
1432 pdata->cpu_affinity_type = PM_QOS_REQ_AFFINE_IRQ;
1433 }
1434}
1435#else
1436static void sdhci_msm_populate_affinity_type(struct sdhci_msm_pltfm_data *pdata,
1437 struct device_node *np)
1438{
1439}
1440#endif
1441
Asutosh Das0ef24812012-12-18 16:14:02 +05301442/* Parse platform data */
Dov Levenglickc9033ab2015-03-10 16:00:56 +02001443static
1444struct sdhci_msm_pltfm_data *sdhci_msm_populate_pdata(struct device *dev,
1445 struct sdhci_msm_host *msm_host)
Asutosh Das0ef24812012-12-18 16:14:02 +05301446{
1447 struct sdhci_msm_pltfm_data *pdata = NULL;
1448 struct device_node *np = dev->of_node;
1449 u32 bus_width = 0;
Sahitya Tummalac6f48d42013-03-10 07:03:17 +05301450 u32 cpu_dma_latency;
Asutosh Das0ef24812012-12-18 16:14:02 +05301451 int len, i;
Sahitya Tummala22dd3362013-02-28 19:50:51 +05301452 int clk_table_len;
1453 u32 *clk_table = NULL;
Sujit Reddy Thumma1958d3d2013-06-03 09:54:32 +05301454 enum of_gpio_flags flags = OF_GPIO_ACTIVE_LOW;
Asutosh Das0ef24812012-12-18 16:14:02 +05301455
1456 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1457 if (!pdata) {
1458 dev_err(dev, "failed to allocate memory for platform data\n");
1459 goto out;
1460 }
1461
Sujit Reddy Thumma1958d3d2013-06-03 09:54:32 +05301462 pdata->status_gpio = of_get_named_gpio_flags(np, "cd-gpios", 0, &flags);
1463 if (gpio_is_valid(pdata->status_gpio) & !(flags & OF_GPIO_ACTIVE_LOW))
1464 pdata->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
Sahitya Tummala581df132013-03-12 14:57:46 +05301465
Asutosh Das0ef24812012-12-18 16:14:02 +05301466 of_property_read_u32(np, "qcom,bus-width", &bus_width);
1467 if (bus_width == 8)
1468 pdata->mmc_bus_width = MMC_CAP_8_BIT_DATA;
1469 else if (bus_width == 4)
1470 pdata->mmc_bus_width = MMC_CAP_4_BIT_DATA;
1471 else {
1472 dev_notice(dev, "invalid bus-width, default to 1-bit mode\n");
1473 pdata->mmc_bus_width = 0;
1474 }
1475
Sahitya Tummalac6f48d42013-03-10 07:03:17 +05301476 if (!of_property_read_u32(np, "qcom,cpu-dma-latency-us",
1477 &cpu_dma_latency))
1478 pdata->cpu_dma_latency_us = cpu_dma_latency;
Asutosh Das598a4d42014-02-05 16:38:23 +05301479 else
1480 pdata->cpu_dma_latency_us = MSM_MMC_DEFAULT_CPU_DMA_LATENCY;
Talel Shenhar7dc5f792015-05-18 12:12:48 +03001481
1482 if (sdhci_msm_dt_get_array(dev, "qcom,devfreq,freq-table",
1483 &msm_host->mmc->clk_scaling.freq_table,
1484 &msm_host->mmc->clk_scaling.freq_table_sz, 0))
1485 pr_debug("%s: no clock scaling frequencies were supplied\n",
1486 dev_name(dev));
1487 else if (!msm_host->mmc->clk_scaling.freq_table ||
1488 !msm_host->mmc->clk_scaling.freq_table_sz)
1489 dev_err(dev, "bad dts clock scaling frequencies\n");
1490
Sahitya Tummala22dd3362013-02-28 19:50:51 +05301491 if (sdhci_msm_dt_get_array(dev, "qcom,clk-rates",
1492 &clk_table, &clk_table_len, 0)) {
1493 dev_err(dev, "failed parsing supported clock rates\n");
1494 goto out;
1495 }
1496 if (!clk_table || !clk_table_len) {
1497 dev_err(dev, "Invalid clock table\n");
1498 goto out;
1499 }
1500 pdata->sup_clk_table = clk_table;
1501 pdata->sup_clk_cnt = clk_table_len;
1502
Asutosh Das0ef24812012-12-18 16:14:02 +05301503 pdata->vreg_data = devm_kzalloc(dev, sizeof(struct
1504 sdhci_msm_slot_reg_data),
1505 GFP_KERNEL);
1506 if (!pdata->vreg_data) {
1507 dev_err(dev, "failed to allocate memory for vreg data\n");
1508 goto out;
1509 }
1510
1511 if (sdhci_msm_dt_parse_vreg_info(dev, &pdata->vreg_data->vdd_data,
1512 "vdd")) {
1513 dev_err(dev, "failed parsing vdd data\n");
1514 goto out;
1515 }
1516 if (sdhci_msm_dt_parse_vreg_info(dev,
1517 &pdata->vreg_data->vdd_io_data,
1518 "vdd-io")) {
1519 dev_err(dev, "failed parsing vdd-io data\n");
1520 goto out;
1521 }
1522
1523 if (sdhci_msm_dt_parse_gpio_info(dev, pdata)) {
1524 dev_err(dev, "failed parsing gpio data\n");
1525 goto out;
1526 }
1527
Asutosh Das0ef24812012-12-18 16:14:02 +05301528 len = of_property_count_strings(np, "qcom,bus-speed-mode");
1529
1530 for (i = 0; i < len; i++) {
1531 const char *name = NULL;
1532
1533 of_property_read_string_index(np,
1534 "qcom,bus-speed-mode", i, &name);
1535 if (!name)
1536 continue;
1537
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -07001538 if (!strncmp(name, "HS400_1p8v", sizeof("HS400_1p8v")))
1539 pdata->caps2 |= MMC_CAP2_HS400_1_8V;
1540 else if (!strncmp(name, "HS400_1p2v", sizeof("HS400_1p2v")))
1541 pdata->caps2 |= MMC_CAP2_HS400_1_2V;
1542 else if (!strncmp(name, "HS200_1p8v", sizeof("HS200_1p8v")))
Asutosh Das0ef24812012-12-18 16:14:02 +05301543 pdata->caps2 |= MMC_CAP2_HS200_1_8V_SDR;
1544 else if (!strncmp(name, "HS200_1p2v", sizeof("HS200_1p2v")))
1545 pdata->caps2 |= MMC_CAP2_HS200_1_2V_SDR;
1546 else if (!strncmp(name, "DDR_1p8v", sizeof("DDR_1p8v")))
1547 pdata->caps |= MMC_CAP_1_8V_DDR
1548 | MMC_CAP_UHS_DDR50;
1549 else if (!strncmp(name, "DDR_1p2v", sizeof("DDR_1p2v")))
1550 pdata->caps |= MMC_CAP_1_2V_DDR
1551 | MMC_CAP_UHS_DDR50;
1552 }
1553
1554 if (of_get_property(np, "qcom,nonremovable", NULL))
1555 pdata->nonremovable = true;
1556
Guoping Yuf7c91332014-08-20 16:56:18 +08001557 if (of_get_property(np, "qcom,nonhotplug", NULL))
1558 pdata->nonhotplug = true;
1559
Venkat Gopalakrishnan9a62e042015-03-03 16:14:55 -08001560 pdata->largeaddressbus =
1561 of_property_read_bool(np, "qcom,large-address-bus");
1562
Maya Erez994cf2f2014-10-21 20:22:04 +03001563 sdhci_msm_populate_affinity_type(pdata, np);
1564
Dov Levenglickc9033ab2015-03-10 16:00:56 +02001565 if (of_property_read_bool(np, "qcom,wakeup-on-idle"))
1566 msm_host->mmc->wakeup_on_idle = true;
1567
Asutosh Das0ef24812012-12-18 16:14:02 +05301568 return pdata;
1569out:
1570 return NULL;
1571}
1572
Sahitya Tummala8a3e8182013-03-10 14:12:52 +05301573/* Returns required bandwidth in Bytes per Sec */
1574static unsigned int sdhci_get_bw_required(struct sdhci_host *host,
1575 struct mmc_ios *ios)
1576{
Sahitya Tummala2886c922013-04-03 18:03:31 +05301577 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1578 struct sdhci_msm_host *msm_host = pltfm_host->priv;
1579
Sahitya Tummala8a3e8182013-03-10 14:12:52 +05301580 unsigned int bw;
1581
Sahitya Tummala2886c922013-04-03 18:03:31 +05301582 bw = msm_host->clk_rate;
Sahitya Tummala8a3e8182013-03-10 14:12:52 +05301583 /*
1584 * For DDR mode, SDCC controller clock will be at
1585 * the double rate than the actual clock that goes to card.
1586 */
1587 if (ios->bus_width == MMC_BUS_WIDTH_4)
1588 bw /= 2;
1589 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1590 bw /= 8;
1591
1592 return bw;
1593}
1594
1595static int sdhci_msm_bus_get_vote_for_bw(struct sdhci_msm_host *host,
1596 unsigned int bw)
1597{
1598 unsigned int *table = host->pdata->voting_data->bw_vecs;
1599 unsigned int size = host->pdata->voting_data->bw_vecs_size;
1600 int i;
1601
1602 if (host->msm_bus_vote.is_max_bw_needed && bw)
1603 return host->msm_bus_vote.max_bw_vote;
1604
1605 for (i = 0; i < size; i++) {
1606 if (bw <= table[i])
1607 break;
1608 }
1609
1610 if (i && (i == size))
1611 i--;
1612
1613 return i;
1614}
1615
1616/*
1617 * This function must be called with host lock acquired.
1618 * Caller of this function should also ensure that msm bus client
1619 * handle is not null.
1620 */
1621static inline int sdhci_msm_bus_set_vote(struct sdhci_msm_host *msm_host,
1622 int vote,
Sujit Reddy Thumma024c0582013-08-06 11:21:33 +05301623 unsigned long *flags)
Sahitya Tummala8a3e8182013-03-10 14:12:52 +05301624{
1625 struct sdhci_host *host = platform_get_drvdata(msm_host->pdev);
1626 int rc = 0;
1627
Sujit Reddy Thumma024c0582013-08-06 11:21:33 +05301628 BUG_ON(!flags);
1629
Sahitya Tummala8a3e8182013-03-10 14:12:52 +05301630 if (vote != msm_host->msm_bus_vote.curr_vote) {
Sujit Reddy Thumma024c0582013-08-06 11:21:33 +05301631 spin_unlock_irqrestore(&host->lock, *flags);
Sahitya Tummala8a3e8182013-03-10 14:12:52 +05301632 rc = msm_bus_scale_client_update_request(
1633 msm_host->msm_bus_vote.client_handle, vote);
Sujit Reddy Thumma024c0582013-08-06 11:21:33 +05301634 spin_lock_irqsave(&host->lock, *flags);
Sahitya Tummala8a3e8182013-03-10 14:12:52 +05301635 if (rc) {
1636 pr_err("%s: msm_bus_scale_client_update_request() failed: bus_client_handle=0x%x, vote=%d, err=%d\n",
1637 mmc_hostname(host->mmc),
1638 msm_host->msm_bus_vote.client_handle, vote, rc);
1639 goto out;
1640 }
1641 msm_host->msm_bus_vote.curr_vote = vote;
1642 }
1643out:
1644 return rc;
1645}
1646
1647/*
1648 * Internal work. Work to set 0 bandwidth for msm bus.
1649 */
1650static void sdhci_msm_bus_work(struct work_struct *work)
1651{
1652 struct sdhci_msm_host *msm_host;
1653 struct sdhci_host *host;
1654 unsigned long flags;
1655
1656 msm_host = container_of(work, struct sdhci_msm_host,
1657 msm_bus_vote.vote_work.work);
1658 host = platform_get_drvdata(msm_host->pdev);
1659
1660 if (!msm_host->msm_bus_vote.client_handle)
1661 return;
1662
1663 spin_lock_irqsave(&host->lock, flags);
1664 /* don't vote for 0 bandwidth if any request is in progress */
1665 if (!host->mrq) {
1666 sdhci_msm_bus_set_vote(msm_host,
Sujit Reddy Thumma024c0582013-08-06 11:21:33 +05301667 msm_host->msm_bus_vote.min_bw_vote, &flags);
Sahitya Tummala8a3e8182013-03-10 14:12:52 +05301668 } else
1669 pr_warning("%s: %s: Transfer in progress. skipping bus voting to 0 bandwidth\n",
1670 mmc_hostname(host->mmc), __func__);
1671 spin_unlock_irqrestore(&host->lock, flags);
1672}
1673
1674/*
1675 * This function cancels any scheduled delayed work and sets the bus
1676 * vote based on bw (bandwidth) argument.
1677 */
1678static void sdhci_msm_bus_cancel_work_and_set_vote(struct sdhci_host *host,
1679 unsigned int bw)
1680{
1681 int vote;
1682 unsigned long flags;
1683 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1684 struct sdhci_msm_host *msm_host = pltfm_host->priv;
1685
1686 cancel_delayed_work_sync(&msm_host->msm_bus_vote.vote_work);
1687 spin_lock_irqsave(&host->lock, flags);
1688 vote = sdhci_msm_bus_get_vote_for_bw(msm_host, bw);
Sujit Reddy Thumma024c0582013-08-06 11:21:33 +05301689 sdhci_msm_bus_set_vote(msm_host, vote, &flags);
Sahitya Tummala8a3e8182013-03-10 14:12:52 +05301690 spin_unlock_irqrestore(&host->lock, flags);
1691}
1692
1693#define MSM_MMC_BUS_VOTING_DELAY 200 /* msecs */
1694
1695/* This function queues a work which will set the bandwidth requiement to 0 */
1696static void sdhci_msm_bus_queue_work(struct sdhci_host *host)
1697{
1698 unsigned long flags;
1699 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1700 struct sdhci_msm_host *msm_host = pltfm_host->priv;
1701
1702 spin_lock_irqsave(&host->lock, flags);
1703 if (msm_host->msm_bus_vote.min_bw_vote !=
1704 msm_host->msm_bus_vote.curr_vote)
1705 queue_delayed_work(system_wq,
1706 &msm_host->msm_bus_vote.vote_work,
1707 msecs_to_jiffies(MSM_MMC_BUS_VOTING_DELAY));
1708 spin_unlock_irqrestore(&host->lock, flags);
1709}
1710
1711static int sdhci_msm_bus_register(struct sdhci_msm_host *host,
1712 struct platform_device *pdev)
1713{
1714 int rc = 0;
1715 struct msm_bus_scale_pdata *bus_pdata;
1716
1717 struct sdhci_msm_bus_voting_data *data;
1718 struct device *dev = &pdev->dev;
1719
1720 data = devm_kzalloc(dev,
1721 sizeof(struct sdhci_msm_bus_voting_data), GFP_KERNEL);
1722 if (!data) {
1723 dev_err(&pdev->dev,
1724 "%s: failed to allocate memory\n", __func__);
1725 rc = -ENOMEM;
1726 goto out;
1727 }
1728 data->bus_pdata = msm_bus_cl_get_pdata(pdev);
1729 if (data->bus_pdata) {
1730 rc = sdhci_msm_dt_get_array(dev, "qcom,bus-bw-vectors-bps",
1731 &data->bw_vecs, &data->bw_vecs_size, 0);
1732 if (rc) {
1733 dev_err(&pdev->dev,
1734 "%s: Failed to get bus-bw-vectors-bps\n",
1735 __func__);
1736 goto out;
1737 }
1738 host->pdata->voting_data = data;
1739 }
1740 if (host->pdata->voting_data &&
1741 host->pdata->voting_data->bus_pdata &&
1742 host->pdata->voting_data->bw_vecs &&
1743 host->pdata->voting_data->bw_vecs_size) {
1744
1745 bus_pdata = host->pdata->voting_data->bus_pdata;
1746 host->msm_bus_vote.client_handle =
1747 msm_bus_scale_register_client(bus_pdata);
1748 if (!host->msm_bus_vote.client_handle) {
1749 dev_err(&pdev->dev, "msm_bus_scale_register_client()\n");
1750 rc = -EFAULT;
1751 goto out;
1752 }
1753 /* cache the vote index for minimum and maximum bandwidth */
1754 host->msm_bus_vote.min_bw_vote =
1755 sdhci_msm_bus_get_vote_for_bw(host, 0);
1756 host->msm_bus_vote.max_bw_vote =
1757 sdhci_msm_bus_get_vote_for_bw(host, UINT_MAX);
1758 } else {
1759 devm_kfree(dev, data);
1760 }
1761
1762out:
1763 return rc;
1764}
1765
1766static void sdhci_msm_bus_unregister(struct sdhci_msm_host *host)
1767{
1768 if (host->msm_bus_vote.client_handle)
1769 msm_bus_scale_unregister_client(
1770 host->msm_bus_vote.client_handle);
1771}
1772
1773static void sdhci_msm_bus_voting(struct sdhci_host *host, u32 enable)
1774{
1775 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1776 struct sdhci_msm_host *msm_host = pltfm_host->priv;
1777 struct mmc_ios *ios = &host->mmc->ios;
1778 unsigned int bw;
1779
1780 if (!msm_host->msm_bus_vote.client_handle)
1781 return;
1782
1783 bw = sdhci_get_bw_required(host, ios);
Sahitya Tummala79edc6a2013-05-23 15:59:22 +05301784 if (enable) {
Sahitya Tummala8a3e8182013-03-10 14:12:52 +05301785 sdhci_msm_bus_cancel_work_and_set_vote(host, bw);
Sahitya Tummala79edc6a2013-05-23 15:59:22 +05301786 } else {
1787 /*
1788 * If clock gating is enabled, then remove the vote
1789 * immediately because clocks will be disabled only
1790 * after SDHCI_MSM_MMC_CLK_GATE_DELAY and thus no
1791 * additional delay is required to remove the bus vote.
1792 */
1793#ifdef CONFIG_MMC_CLKGATE
1794 if (host->mmc->clkgate_delay)
1795 sdhci_msm_bus_cancel_work_and_set_vote(host, 0);
1796 else
1797#endif
1798 sdhci_msm_bus_queue_work(host);
1799 }
Sahitya Tummala8a3e8182013-03-10 14:12:52 +05301800}
1801
Asutosh Das0ef24812012-12-18 16:14:02 +05301802/* Regulator utility functions */
1803static int sdhci_msm_vreg_init_reg(struct device *dev,
1804 struct sdhci_msm_reg_data *vreg)
1805{
1806 int ret = 0;
1807
1808 /* check if regulator is already initialized? */
1809 if (vreg->reg)
1810 goto out;
1811
1812 /* Get the regulator handle */
1813 vreg->reg = devm_regulator_get(dev, vreg->name);
1814 if (IS_ERR(vreg->reg)) {
1815 ret = PTR_ERR(vreg->reg);
1816 pr_err("%s: devm_regulator_get(%s) failed. ret=%d\n",
1817 __func__, vreg->name, ret);
1818 goto out;
1819 }
1820
Asutosh Dasc58cc7a2013-06-28 15:03:44 +05301821 if (regulator_count_voltages(vreg->reg) > 0) {
1822 vreg->set_voltage_sup = true;
1823 /* sanity check */
1824 if (!vreg->high_vol_level || !vreg->hpm_uA) {
1825 pr_err("%s: %s invalid constraints specified\n",
1826 __func__, vreg->name);
1827 ret = -EINVAL;
1828 }
Asutosh Das0ef24812012-12-18 16:14:02 +05301829 }
1830
1831out:
1832 return ret;
1833}
1834
1835static void sdhci_msm_vreg_deinit_reg(struct sdhci_msm_reg_data *vreg)
1836{
1837 if (vreg->reg)
1838 devm_regulator_put(vreg->reg);
1839}
1840
1841static int sdhci_msm_vreg_set_optimum_mode(struct sdhci_msm_reg_data
1842 *vreg, int uA_load)
1843{
1844 int ret = 0;
1845
1846 /*
1847 * regulators that do not support regulator_set_voltage also
1848 * do not support regulator_set_optimum_mode
1849 */
1850 if (vreg->set_voltage_sup) {
1851 ret = regulator_set_load(vreg->reg, uA_load);
1852 if (ret < 0)
1853 pr_err("%s: regulator_set_load(reg=%s,uA_load=%d) failed. ret=%d\n",
1854 __func__, vreg->name, uA_load, ret);
1855 else
1856 /*
1857 * regulator_set_load() can return non zero
1858 * value even for success case.
1859 */
1860 ret = 0;
1861 }
1862 return ret;
1863}
1864
1865static int sdhci_msm_vreg_set_voltage(struct sdhci_msm_reg_data *vreg,
1866 int min_uV, int max_uV)
1867{
1868 int ret = 0;
Asutosh Dasc58cc7a2013-06-28 15:03:44 +05301869 if (vreg->set_voltage_sup) {
1870 ret = regulator_set_voltage(vreg->reg, min_uV, max_uV);
1871 if (ret) {
1872 pr_err("%s: regulator_set_voltage(%s)failed. min_uV=%d,max_uV=%d,ret=%d\n",
Asutosh Das0ef24812012-12-18 16:14:02 +05301873 __func__, vreg->name, min_uV, max_uV, ret);
1874 }
Asutosh Dasc58cc7a2013-06-28 15:03:44 +05301875 }
Asutosh Das0ef24812012-12-18 16:14:02 +05301876
1877 return ret;
1878}
1879
1880static int sdhci_msm_vreg_enable(struct sdhci_msm_reg_data *vreg)
1881{
1882 int ret = 0;
1883
1884 /* Put regulator in HPM (high power mode) */
1885 ret = sdhci_msm_vreg_set_optimum_mode(vreg, vreg->hpm_uA);
1886 if (ret < 0)
1887 return ret;
1888
1889 if (!vreg->is_enabled) {
1890 /* Set voltage level */
1891 ret = sdhci_msm_vreg_set_voltage(vreg, vreg->high_vol_level,
1892 vreg->high_vol_level);
1893 if (ret)
1894 return ret;
1895 }
1896 ret = regulator_enable(vreg->reg);
1897 if (ret) {
1898 pr_err("%s: regulator_enable(%s) failed. ret=%d\n",
1899 __func__, vreg->name, ret);
1900 return ret;
1901 }
1902 vreg->is_enabled = true;
1903 return ret;
1904}
1905
1906static int sdhci_msm_vreg_disable(struct sdhci_msm_reg_data *vreg)
1907{
1908 int ret = 0;
1909
1910 /* Never disable regulator marked as always_on */
1911 if (vreg->is_enabled && !vreg->is_always_on) {
1912 ret = regulator_disable(vreg->reg);
1913 if (ret) {
1914 pr_err("%s: regulator_disable(%s) failed. ret=%d\n",
1915 __func__, vreg->name, ret);
1916 goto out;
1917 }
1918 vreg->is_enabled = false;
1919
1920 ret = sdhci_msm_vreg_set_optimum_mode(vreg, 0);
1921 if (ret < 0)
1922 goto out;
1923
1924 /* Set min. voltage level to 0 */
1925 ret = sdhci_msm_vreg_set_voltage(vreg, 0, vreg->high_vol_level);
1926 if (ret)
1927 goto out;
1928 } else if (vreg->is_enabled && vreg->is_always_on) {
1929 if (vreg->lpm_sup) {
1930 /* Put always_on regulator in LPM (low power mode) */
1931 ret = sdhci_msm_vreg_set_optimum_mode(vreg,
1932 vreg->lpm_uA);
1933 if (ret < 0)
1934 goto out;
1935 }
1936 }
1937out:
1938 return ret;
1939}
1940
1941static int sdhci_msm_setup_vreg(struct sdhci_msm_pltfm_data *pdata,
1942 bool enable, bool is_init)
1943{
1944 int ret = 0, i;
1945 struct sdhci_msm_slot_reg_data *curr_slot;
1946 struct sdhci_msm_reg_data *vreg_table[2];
1947
1948 curr_slot = pdata->vreg_data;
1949 if (!curr_slot) {
1950 pr_debug("%s: vreg info unavailable,assuming the slot is powered by always on domain\n",
1951 __func__);
1952 goto out;
1953 }
1954
1955 vreg_table[0] = curr_slot->vdd_data;
1956 vreg_table[1] = curr_slot->vdd_io_data;
1957
1958 for (i = 0; i < ARRAY_SIZE(vreg_table); i++) {
1959 if (vreg_table[i]) {
1960 if (enable)
1961 ret = sdhci_msm_vreg_enable(vreg_table[i]);
1962 else
1963 ret = sdhci_msm_vreg_disable(vreg_table[i]);
1964 if (ret)
1965 goto out;
1966 }
1967 }
1968out:
1969 return ret;
1970}
1971
1972/*
1973 * Reset vreg by ensuring it is off during probe. A call
1974 * to enable vreg is needed to balance disable vreg
1975 */
1976static int sdhci_msm_vreg_reset(struct sdhci_msm_pltfm_data *pdata)
1977{
1978 int ret;
1979
1980 ret = sdhci_msm_setup_vreg(pdata, 1, true);
1981 if (ret)
1982 return ret;
1983 ret = sdhci_msm_setup_vreg(pdata, 0, true);
1984 return ret;
1985}
1986
1987/* This init function should be called only once for each SDHC slot */
1988static int sdhci_msm_vreg_init(struct device *dev,
1989 struct sdhci_msm_pltfm_data *pdata,
1990 bool is_init)
1991{
1992 int ret = 0;
1993 struct sdhci_msm_slot_reg_data *curr_slot;
1994 struct sdhci_msm_reg_data *curr_vdd_reg, *curr_vdd_io_reg;
1995
1996 curr_slot = pdata->vreg_data;
1997 if (!curr_slot)
1998 goto out;
1999
2000 curr_vdd_reg = curr_slot->vdd_data;
2001 curr_vdd_io_reg = curr_slot->vdd_io_data;
2002
2003 if (!is_init)
2004 /* Deregister all regulators from regulator framework */
2005 goto vdd_io_reg_deinit;
2006
2007 /*
2008 * Get the regulator handle from voltage regulator framework
2009 * and then try to set the voltage level for the regulator
2010 */
2011 if (curr_vdd_reg) {
2012 ret = sdhci_msm_vreg_init_reg(dev, curr_vdd_reg);
2013 if (ret)
2014 goto out;
2015 }
2016 if (curr_vdd_io_reg) {
2017 ret = sdhci_msm_vreg_init_reg(dev, curr_vdd_io_reg);
2018 if (ret)
2019 goto vdd_reg_deinit;
2020 }
2021 ret = sdhci_msm_vreg_reset(pdata);
2022 if (ret)
2023 dev_err(dev, "vreg reset failed (%d)\n", ret);
2024 goto out;
2025
2026vdd_io_reg_deinit:
2027 if (curr_vdd_io_reg)
2028 sdhci_msm_vreg_deinit_reg(curr_vdd_io_reg);
2029vdd_reg_deinit:
2030 if (curr_vdd_reg)
2031 sdhci_msm_vreg_deinit_reg(curr_vdd_reg);
2032out:
2033 return ret;
2034}
2035
2036
2037static int sdhci_msm_set_vdd_io_vol(struct sdhci_msm_pltfm_data *pdata,
2038 enum vdd_io_level level,
2039 unsigned int voltage_level)
2040{
2041 int ret = 0;
2042 int set_level;
2043 struct sdhci_msm_reg_data *vdd_io_reg;
2044
2045 if (!pdata->vreg_data)
2046 return ret;
2047
2048 vdd_io_reg = pdata->vreg_data->vdd_io_data;
2049 if (vdd_io_reg && vdd_io_reg->is_enabled) {
2050 switch (level) {
2051 case VDD_IO_LOW:
2052 set_level = vdd_io_reg->low_vol_level;
2053 break;
2054 case VDD_IO_HIGH:
2055 set_level = vdd_io_reg->high_vol_level;
2056 break;
2057 case VDD_IO_SET_LEVEL:
2058 set_level = voltage_level;
2059 break;
2060 default:
2061 pr_err("%s: invalid argument level = %d",
2062 __func__, level);
2063 ret = -EINVAL;
2064 return ret;
2065 }
2066 ret = sdhci_msm_vreg_set_voltage(vdd_io_reg, set_level,
2067 set_level);
2068 }
2069 return ret;
2070}
2071
Pavan Anamula53ffa0b2015-07-22 21:46:32 +05302072void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)
2073{
2074 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2075 struct sdhci_msm_host *msm_host = pltfm_host->priv;
2076
2077 pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
2078 mmc_hostname(host->mmc),
2079 readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS),
2080 readl_relaxed(msm_host->core_mem + CORE_PWRCTL_MASK),
2081 readl_relaxed(msm_host->core_mem + CORE_PWRCTL_CTL));
2082}
2083
Asutosh Das0ef24812012-12-18 16:14:02 +05302084static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
2085{
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -07002086 struct sdhci_host *host = (struct sdhci_host *)data;
2087 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2088 struct sdhci_msm_host *msm_host = pltfm_host->priv;
Asutosh Das0ef24812012-12-18 16:14:02 +05302089 u8 irq_status = 0;
2090 u8 irq_ack = 0;
2091 int ret = 0;
Sahitya Tummala1f52eaa2013-03-20 19:24:01 +05302092 int pwr_state = 0, io_level = 0;
2093 unsigned long flags;
Pavan Anamula53ffa0b2015-07-22 21:46:32 +05302094 int retry = 10;
Asutosh Das0ef24812012-12-18 16:14:02 +05302095
2096 irq_status = readb_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS);
2097 pr_debug("%s: Received IRQ(%d), status=0x%x\n",
2098 mmc_hostname(msm_host->mmc), irq, irq_status);
2099
2100 /* Clear the interrupt */
2101 writeb_relaxed(irq_status, (msm_host->core_mem + CORE_PWRCTL_CLEAR));
2102 /*
2103 * SDHC has core_mem and hc_mem device memory and these memory
2104 * addresses do not fall within 1KB region. Hence, any update to
2105 * core_mem address space would require an mb() to ensure this gets
2106 * completed before its next update to registers within hc_mem.
2107 */
2108 mb();
Pavan Anamula53ffa0b2015-07-22 21:46:32 +05302109 /*
2110 * There is a rare HW scenario where the first clear pulse could be
2111 * lost when actual reset and clear/read of status register is
2112 * happening at a time. Hence, retry for at least 10 times to make
2113 * sure status register is cleared. Otherwise, this will result in
2114 * a spurious power IRQ resulting in system instability.
2115 */
2116 while (irq_status &
2117 readb_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS)) {
2118 if (retry == 0) {
2119 pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
2120 mmc_hostname(host->mmc), irq_status);
2121 sdhci_msm_dump_pwr_ctrl_regs(host);
2122 BUG_ON(1);
2123 }
2124 writeb_relaxed(irq_status,
2125 (msm_host->core_mem + CORE_PWRCTL_CLEAR));
2126 retry--;
2127 udelay(10);
2128 }
2129 if (likely(retry < 10))
2130 pr_debug("%s: success clearing (0x%x) pwrctl status register, retries left %d\n",
2131 mmc_hostname(host->mmc), irq_status, retry);
Asutosh Das0ef24812012-12-18 16:14:02 +05302132
2133 /* Handle BUS ON/OFF*/
2134 if (irq_status & CORE_PWRCTL_BUS_ON) {
2135 ret = sdhci_msm_setup_vreg(msm_host->pdata, true, false);
Sahitya Tummala1f52eaa2013-03-20 19:24:01 +05302136 if (!ret) {
Asutosh Das0ef24812012-12-18 16:14:02 +05302137 ret = sdhci_msm_setup_pins(msm_host->pdata, true);
Sahitya Tummala1f52eaa2013-03-20 19:24:01 +05302138 ret |= sdhci_msm_set_vdd_io_vol(msm_host->pdata,
2139 VDD_IO_HIGH, 0);
2140 }
Asutosh Das0ef24812012-12-18 16:14:02 +05302141 if (ret)
2142 irq_ack |= CORE_PWRCTL_BUS_FAIL;
2143 else
2144 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
Sahitya Tummala1f52eaa2013-03-20 19:24:01 +05302145
2146 pwr_state = REQ_BUS_ON;
2147 io_level = REQ_IO_HIGH;
Asutosh Das0ef24812012-12-18 16:14:02 +05302148 }
2149 if (irq_status & CORE_PWRCTL_BUS_OFF) {
2150 ret = sdhci_msm_setup_vreg(msm_host->pdata, false, false);
Sahitya Tummala1f52eaa2013-03-20 19:24:01 +05302151 if (!ret) {
Asutosh Das0ef24812012-12-18 16:14:02 +05302152 ret = sdhci_msm_setup_pins(msm_host->pdata, false);
Sahitya Tummala1f52eaa2013-03-20 19:24:01 +05302153 ret |= sdhci_msm_set_vdd_io_vol(msm_host->pdata,
2154 VDD_IO_LOW, 0);
2155 }
Asutosh Das0ef24812012-12-18 16:14:02 +05302156 if (ret)
2157 irq_ack |= CORE_PWRCTL_BUS_FAIL;
2158 else
2159 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
Sahitya Tummala1f52eaa2013-03-20 19:24:01 +05302160
2161 pwr_state = REQ_BUS_OFF;
2162 io_level = REQ_IO_LOW;
Asutosh Das0ef24812012-12-18 16:14:02 +05302163 }
2164 /* Handle IO LOW/HIGH */
2165 if (irq_status & CORE_PWRCTL_IO_LOW) {
2166 /* Switch voltage Low */
2167 ret = sdhci_msm_set_vdd_io_vol(msm_host->pdata, VDD_IO_LOW, 0);
2168 if (ret)
2169 irq_ack |= CORE_PWRCTL_IO_FAIL;
2170 else
2171 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
Sahitya Tummala1f52eaa2013-03-20 19:24:01 +05302172
2173 io_level = REQ_IO_LOW;
Asutosh Das0ef24812012-12-18 16:14:02 +05302174 }
2175 if (irq_status & CORE_PWRCTL_IO_HIGH) {
2176 /* Switch voltage High */
2177 ret = sdhci_msm_set_vdd_io_vol(msm_host->pdata, VDD_IO_HIGH, 0);
2178 if (ret)
2179 irq_ack |= CORE_PWRCTL_IO_FAIL;
2180 else
2181 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
Sahitya Tummala1f52eaa2013-03-20 19:24:01 +05302182
2183 io_level = REQ_IO_HIGH;
Asutosh Das0ef24812012-12-18 16:14:02 +05302184 }
2185
2186 /* ACK status to the core */
2187 writeb_relaxed(irq_ack, (msm_host->core_mem + CORE_PWRCTL_CTL));
2188 /*
2189 * SDHC has core_mem and hc_mem device memory and these memory
2190 * addresses do not fall within 1KB region. Hence, any update to
2191 * core_mem address space would require an mb() to ensure this gets
2192 * completed before its next update to registers within hc_mem.
2193 */
2194 mb();
2195
Krishna Konda46fd1432014-10-30 21:13:27 -07002196 if ((io_level & REQ_IO_HIGH) && (msm_host->caps_0 & CORE_3_0V_SUPPORT))
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -07002197 writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) &
2198 ~CORE_IO_PAD_PWR_SWITCH),
2199 host->ioaddr + CORE_VENDOR_SPEC);
Krishna Konda46fd1432014-10-30 21:13:27 -07002200 else if ((io_level & REQ_IO_LOW) ||
2201 (msm_host->caps_0 & CORE_1_8V_SUPPORT))
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -07002202 writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
2203 CORE_IO_PAD_PWR_SWITCH),
2204 host->ioaddr + CORE_VENDOR_SPEC);
2205 mb();
2206
Asutosh Das0ef24812012-12-18 16:14:02 +05302207 pr_debug("%s: Handled IRQ(%d), ret=%d, ack=0x%x\n",
2208 mmc_hostname(msm_host->mmc), irq, ret, irq_ack);
Sahitya Tummala1f52eaa2013-03-20 19:24:01 +05302209 spin_lock_irqsave(&host->lock, flags);
2210 if (pwr_state)
2211 msm_host->curr_pwr_state = pwr_state;
2212 if (io_level)
2213 msm_host->curr_io_level = io_level;
2214 complete(&msm_host->pwr_irq_completion);
2215 spin_unlock_irqrestore(&host->lock, flags);
2216
Asutosh Das0ef24812012-12-18 16:14:02 +05302217 return IRQ_HANDLED;
2218}
2219
Sahitya Tummala8a3e8182013-03-10 14:12:52 +05302220static ssize_t
Sahitya Tummala5c55b932013-06-20 14:00:18 +05302221show_polling(struct device *dev, struct device_attribute *attr, char *buf)
2222{
2223 struct sdhci_host *host = dev_get_drvdata(dev);
2224 int poll;
2225 unsigned long flags;
2226
2227 spin_lock_irqsave(&host->lock, flags);
2228 poll = !!(host->mmc->caps & MMC_CAP_NEEDS_POLL);
2229 spin_unlock_irqrestore(&host->lock, flags);
2230
2231 return snprintf(buf, PAGE_SIZE, "%d\n", poll);
2232}
2233
2234static ssize_t
2235store_polling(struct device *dev, struct device_attribute *attr,
2236 const char *buf, size_t count)
2237{
2238 struct sdhci_host *host = dev_get_drvdata(dev);
2239 int value;
2240 unsigned long flags;
2241
2242 if (!kstrtou32(buf, 0, &value)) {
2243 spin_lock_irqsave(&host->lock, flags);
2244 if (value) {
2245 host->mmc->caps |= MMC_CAP_NEEDS_POLL;
2246 mmc_detect_change(host->mmc, 0);
2247 } else {
2248 host->mmc->caps &= ~MMC_CAP_NEEDS_POLL;
2249 }
2250 spin_unlock_irqrestore(&host->lock, flags);
2251 }
2252 return count;
2253}
2254
2255static ssize_t
Sahitya Tummala8a3e8182013-03-10 14:12:52 +05302256show_sdhci_max_bus_bw(struct device *dev, struct device_attribute *attr,
2257 char *buf)
2258{
2259 struct sdhci_host *host = dev_get_drvdata(dev);
2260 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2261 struct sdhci_msm_host *msm_host = pltfm_host->priv;
2262
2263 return snprintf(buf, PAGE_SIZE, "%u\n",
2264 msm_host->msm_bus_vote.is_max_bw_needed);
2265}
2266
2267static ssize_t
2268store_sdhci_max_bus_bw(struct device *dev, struct device_attribute *attr,
2269 const char *buf, size_t count)
2270{
2271 struct sdhci_host *host = dev_get_drvdata(dev);
2272 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2273 struct sdhci_msm_host *msm_host = pltfm_host->priv;
2274 uint32_t value;
2275 unsigned long flags;
2276
2277 if (!kstrtou32(buf, 0, &value)) {
2278 spin_lock_irqsave(&host->lock, flags);
2279 msm_host->msm_bus_vote.is_max_bw_needed = !!value;
2280 spin_unlock_irqrestore(&host->lock, flags);
2281 }
2282 return count;
2283}
2284
Sahitya Tummala1f52eaa2013-03-20 19:24:01 +05302285static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
Asutosh Das0ef24812012-12-18 16:14:02 +05302286{
2287 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2288 struct sdhci_msm_host *msm_host = pltfm_host->priv;
Sahitya Tummala1f52eaa2013-03-20 19:24:01 +05302289 unsigned long flags;
2290 bool done = false;
Sahitya Tummala481fbb02013-08-06 15:22:28 +05302291 u32 io_sig_sts;
Asutosh Das0ef24812012-12-18 16:14:02 +05302292
Sahitya Tummala1f52eaa2013-03-20 19:24:01 +05302293 spin_lock_irqsave(&host->lock, flags);
2294 pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
2295 mmc_hostname(host->mmc), __func__, req_type,
2296 msm_host->curr_pwr_state, msm_host->curr_io_level);
Sahitya Tummala481fbb02013-08-06 15:22:28 +05302297 io_sig_sts = readl_relaxed(msm_host->core_mem + CORE_GENERICS);
2298 /*
2299 * The IRQ for request type IO High/Low will be generated when -
2300 * 1. SWITCHABLE_SIGNALLING_VOL is enabled in HW.
2301 * 2. If 1 is true and when there is a state change in 1.8V enable
2302 * bit (bit 3) of SDHCI_HOST_CONTROL2 register. The reset state of
2303 * that bit is 0 which indicates 3.3V IO voltage. So, when MMC core
2304 * layer tries to set it to 3.3V before card detection happens, the
2305 * IRQ doesn't get triggered as there is no state change in this bit.
2306 * The driver already handles this case by changing the IO voltage
2307 * level to high as part of controller power up sequence. Hence, check
2308 * for host->pwr to handle a case where IO voltage high request is
2309 * issued even before controller power up.
2310 */
2311 if (req_type & (REQ_IO_HIGH | REQ_IO_LOW)) {
2312 if (!(io_sig_sts & SWITCHABLE_SIGNALLING_VOL) ||
2313 ((req_type & REQ_IO_HIGH) && !host->pwr)) {
2314 pr_debug("%s: do not wait for power IRQ that never comes\n",
2315 mmc_hostname(host->mmc));
2316 spin_unlock_irqrestore(&host->lock, flags);
2317 return;
2318 }
2319 }
2320
Sahitya Tummala1f52eaa2013-03-20 19:24:01 +05302321 if ((req_type & msm_host->curr_pwr_state) ||
2322 (req_type & msm_host->curr_io_level))
2323 done = true;
2324 spin_unlock_irqrestore(&host->lock, flags);
Asutosh Das0ef24812012-12-18 16:14:02 +05302325
Sahitya Tummala1f52eaa2013-03-20 19:24:01 +05302326 /*
2327 * This is needed here to hanlde a case where IRQ gets
2328 * triggered even before this function is called so that
2329 * x->done counter of completion gets reset. Otherwise,
2330 * next call to wait_for_completion returns immediately
2331 * without actually waiting for the IRQ to be handled.
2332 */
2333 if (done)
2334 init_completion(&msm_host->pwr_irq_completion);
2335 else
2336 wait_for_completion(&msm_host->pwr_irq_completion);
2337
2338 pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc),
2339 __func__, req_type);
Asutosh Das0ef24812012-12-18 16:14:02 +05302340}
2341
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -07002342static void sdhci_msm_toggle_cdr(struct sdhci_host *host, bool enable)
2343{
2344 if (enable)
2345 writel_relaxed((readl_relaxed(host->ioaddr +
2346 CORE_DLL_CONFIG) | CORE_CDR_EN),
2347 host->ioaddr + CORE_DLL_CONFIG);
2348 else
2349 writel_relaxed((readl_relaxed(host->ioaddr +
2350 CORE_DLL_CONFIG) & ~CORE_CDR_EN),
2351 host->ioaddr + CORE_DLL_CONFIG);
2352}
2353
Asutosh Das648f9d12013-01-10 21:11:04 +05302354static unsigned int sdhci_msm_max_segs(void)
2355{
2356 return SDHCI_MSM_MAX_SEGMENTS;
2357}
2358
Sahitya Tummala22dd3362013-02-28 19:50:51 +05302359static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
Sahitya Tummalaa7f3c572013-01-11 11:30:45 +05302360{
Sahitya Tummalaa7f3c572013-01-11 11:30:45 +05302361 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2362 struct sdhci_msm_host *msm_host = pltfm_host->priv;
Sahitya Tummalaa7f3c572013-01-11 11:30:45 +05302363
Sahitya Tummala22dd3362013-02-28 19:50:51 +05302364 return msm_host->pdata->sup_clk_table[0];
2365}
2366
2367static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
2368{
2369 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2370 struct sdhci_msm_host *msm_host = pltfm_host->priv;
2371 int max_clk_index = msm_host->pdata->sup_clk_cnt;
2372
2373 return msm_host->pdata->sup_clk_table[max_clk_index - 1];
2374}
2375
2376static unsigned int sdhci_msm_get_sup_clk_rate(struct sdhci_host *host,
2377 u32 req_clk)
2378{
2379 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2380 struct sdhci_msm_host *msm_host = pltfm_host->priv;
2381 unsigned int sel_clk = -1;
2382 unsigned char cnt;
2383
2384 if (req_clk < sdhci_msm_get_min_clock(host)) {
2385 sel_clk = sdhci_msm_get_min_clock(host);
2386 return sel_clk;
2387 }
2388
2389 for (cnt = 0; cnt < msm_host->pdata->sup_clk_cnt; cnt++) {
2390 if (msm_host->pdata->sup_clk_table[cnt] > req_clk) {
2391 break;
2392 } else if (msm_host->pdata->sup_clk_table[cnt] == req_clk) {
2393 sel_clk = msm_host->pdata->sup_clk_table[cnt];
2394 break;
2395 } else {
2396 sel_clk = msm_host->pdata->sup_clk_table[cnt];
2397 }
2398 }
2399 return sel_clk;
2400}
2401
Asutosh Das9d7ee2f2013-11-08 12:33:47 +05302402static int sdhci_msm_enable_controller_clock(struct sdhci_host *host)
2403{
2404 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2405 struct sdhci_msm_host *msm_host = pltfm_host->priv;
2406 int rc = 0;
2407
2408 if (atomic_read(&msm_host->controller_clock))
2409 return 0;
2410
2411 sdhci_msm_bus_voting(host, 1);
2412
2413 if (!IS_ERR(msm_host->pclk)) {
2414 rc = clk_prepare_enable(msm_host->pclk);
2415 if (rc) {
2416 pr_err("%s: %s: failed to enable the pclk with error %d\n",
2417 mmc_hostname(host->mmc), __func__, rc);
2418 goto remove_vote;
2419 }
2420 }
2421
2422 rc = clk_prepare_enable(msm_host->clk);
2423 if (rc) {
2424 pr_err("%s: %s: failed to enable the host-clk with error %d\n",
2425 mmc_hostname(host->mmc), __func__, rc);
2426 goto disable_pclk;
2427 }
2428
2429 atomic_set(&msm_host->controller_clock, 1);
2430 pr_debug("%s: %s: enabled controller clock\n",
2431 mmc_hostname(host->mmc), __func__);
2432 goto out;
2433
2434disable_pclk:
2435 if (!IS_ERR(msm_host->pclk))
2436 clk_disable_unprepare(msm_host->pclk);
2437remove_vote:
2438 if (msm_host->msm_bus_vote.client_handle)
2439 sdhci_msm_bus_cancel_work_and_set_vote(host, 0);
2440out:
2441 return rc;
2442}
2443
2444
2445
Sahitya Tummala22dd3362013-02-28 19:50:51 +05302446static int sdhci_msm_prepare_clocks(struct sdhci_host *host, bool enable)
2447{
2448 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2449 struct sdhci_msm_host *msm_host = pltfm_host->priv;
2450 int rc = 0;
2451
2452 if (enable && !atomic_read(&msm_host->clks_on)) {
2453 pr_debug("%s: request to enable clocks\n",
2454 mmc_hostname(host->mmc));
Sahitya Tummala79edc6a2013-05-23 15:59:22 +05302455
Asutosh Das9d7ee2f2013-11-08 12:33:47 +05302456 /*
2457 * The bus-width or the clock rate might have changed
2458 * after controller clocks are enbaled, update bus vote
2459 * in such case.
2460 */
2461 if (atomic_read(&msm_host->controller_clock))
2462 sdhci_msm_bus_voting(host, 1);
2463
2464 rc = sdhci_msm_enable_controller_clock(host);
2465 if (rc)
2466 goto remove_vote;
Sahitya Tummala79edc6a2013-05-23 15:59:22 +05302467
Sahitya Tummalaa7f3c572013-01-11 11:30:45 +05302468 if (!IS_ERR_OR_NULL(msm_host->bus_clk)) {
2469 rc = clk_prepare_enable(msm_host->bus_clk);
2470 if (rc) {
2471 pr_err("%s: %s: failed to enable the bus-clock with error %d\n",
2472 mmc_hostname(host->mmc), __func__, rc);
Asutosh Das9d7ee2f2013-11-08 12:33:47 +05302473 goto disable_controller_clk;
Sahitya Tummalaa7f3c572013-01-11 11:30:45 +05302474 }
2475 }
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -07002476 if (!IS_ERR(msm_host->ff_clk)) {
2477 rc = clk_prepare_enable(msm_host->ff_clk);
2478 if (rc) {
2479 pr_err("%s: %s: failed to enable the ff_clk with error %d\n",
2480 mmc_hostname(host->mmc), __func__, rc);
Asutosh Das9d7ee2f2013-11-08 12:33:47 +05302481 goto disable_bus_clk;
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -07002482 }
2483 }
2484 if (!IS_ERR(msm_host->sleep_clk)) {
2485 rc = clk_prepare_enable(msm_host->sleep_clk);
2486 if (rc) {
2487 pr_err("%s: %s: failed to enable the sleep_clk with error %d\n",
2488 mmc_hostname(host->mmc), __func__, rc);
2489 goto disable_ff_clk;
2490 }
2491 }
Sahitya Tummalaa7f3c572013-01-11 11:30:45 +05302492 mb();
Sahitya Tummalaa7f3c572013-01-11 11:30:45 +05302493
Sahitya Tummala22dd3362013-02-28 19:50:51 +05302494 } else if (!enable && atomic_read(&msm_host->clks_on)) {
Sahitya Tummalaa7f3c572013-01-11 11:30:45 +05302495 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
2496 mb();
Sahitya Tummaladc182982013-08-20 15:32:09 +05302497 /*
2498 * During 1.8V signal switching the clock source must
2499 * still be ON as it requires accessing SDHC
2500 * registers (SDHCi host control2 register bit 3 must
2501 * be written and polled after stopping the SDCLK).
2502 */
2503 if (host->mmc->card_clock_off)
2504 return 0;
2505 pr_debug("%s: request to disable clocks\n",
2506 mmc_hostname(host->mmc));
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -07002507 if (!IS_ERR_OR_NULL(msm_host->sleep_clk))
2508 clk_disable_unprepare(msm_host->sleep_clk);
2509 if (!IS_ERR_OR_NULL(msm_host->ff_clk))
2510 clk_disable_unprepare(msm_host->ff_clk);
Sahitya Tummalaa7f3c572013-01-11 11:30:45 +05302511 clk_disable_unprepare(msm_host->clk);
2512 if (!IS_ERR(msm_host->pclk))
2513 clk_disable_unprepare(msm_host->pclk);
2514 if (!IS_ERR_OR_NULL(msm_host->bus_clk))
2515 clk_disable_unprepare(msm_host->bus_clk);
Sahitya Tummala79edc6a2013-05-23 15:59:22 +05302516
Asutosh Das9d7ee2f2013-11-08 12:33:47 +05302517 atomic_set(&msm_host->controller_clock, 0);
Sahitya Tummala79edc6a2013-05-23 15:59:22 +05302518 sdhci_msm_bus_voting(host, 0);
Sahitya Tummalaa7f3c572013-01-11 11:30:45 +05302519 }
Sahitya Tummala22dd3362013-02-28 19:50:51 +05302520 atomic_set(&msm_host->clks_on, enable);
Sahitya Tummalaa7f3c572013-01-11 11:30:45 +05302521 goto out;
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -07002522disable_ff_clk:
2523 if (!IS_ERR_OR_NULL(msm_host->ff_clk))
2524 clk_disable_unprepare(msm_host->ff_clk);
Sahitya Tummalaa7f3c572013-01-11 11:30:45 +05302525disable_bus_clk:
2526 if (!IS_ERR_OR_NULL(msm_host->bus_clk))
2527 clk_disable_unprepare(msm_host->bus_clk);
Asutosh Das9d7ee2f2013-11-08 12:33:47 +05302528disable_controller_clk:
2529 if (!IS_ERR_OR_NULL(msm_host->clk))
2530 clk_disable_unprepare(msm_host->clk);
2531 if (!IS_ERR_OR_NULL(msm_host->pclk))
2532 clk_disable_unprepare(msm_host->pclk);
2533 atomic_set(&msm_host->controller_clock, 0);
Sahitya Tummala79edc6a2013-05-23 15:59:22 +05302534remove_vote:
2535 if (msm_host->msm_bus_vote.client_handle)
2536 sdhci_msm_bus_cancel_work_and_set_vote(host, 0);
Sahitya Tummalaa7f3c572013-01-11 11:30:45 +05302537out:
Sahitya Tummala22dd3362013-02-28 19:50:51 +05302538 return rc;
2539}
2540
2541static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
2542{
2543 int rc;
2544 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2545 struct sdhci_msm_host *msm_host = pltfm_host->priv;
2546 struct mmc_ios curr_ios = host->mmc->ios;
Krishna Konda2faa7bb2014-06-04 01:25:16 -07002547 u32 sup_clock, ddr_clock, dll_lock;
Sahitya Tummala043744a2013-06-24 09:55:33 +05302548 bool curr_pwrsave;
Sahitya Tummala22dd3362013-02-28 19:50:51 +05302549
2550 if (!clock) {
Sujit Reddy Thummabf1aecc2014-01-10 10:58:54 +05302551 /*
2552 * disable pwrsave to ensure clock is not auto-gated until
2553 * the rate is >400KHz (initialization complete).
2554 */
2555 writel_relaxed(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) &
2556 ~CORE_CLK_PWRSAVE, host->ioaddr + CORE_VENDOR_SPEC);
Sahitya Tummala22dd3362013-02-28 19:50:51 +05302557 sdhci_msm_prepare_clocks(host, false);
2558 host->clock = clock;
2559 goto out;
2560 }
2561
2562 rc = sdhci_msm_prepare_clocks(host, true);
2563 if (rc)
2564 goto out;
2565
Sahitya Tummala043744a2013-06-24 09:55:33 +05302566 curr_pwrsave = !!(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) &
2567 CORE_CLK_PWRSAVE);
Sahitya Tummalae000b242013-08-29 16:21:08 +05302568 if ((clock > 400000) &&
Venkat Gopalakrishnanc0a367272015-02-24 13:09:09 -08002569 !curr_pwrsave && mmc_host_may_gate_card(host->mmc->card))
Sahitya Tummala043744a2013-06-24 09:55:33 +05302570 writel_relaxed(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
2571 | CORE_CLK_PWRSAVE,
2572 host->ioaddr + CORE_VENDOR_SPEC);
2573 /*
2574 * Disable pwrsave for a newly added card if doesn't allow clock
2575 * gating.
2576 */
Venkat Gopalakrishnanc0a367272015-02-24 13:09:09 -08002577 else if (curr_pwrsave && !mmc_host_may_gate_card(host->mmc->card))
Sahitya Tummala043744a2013-06-24 09:55:33 +05302578 writel_relaxed(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
2579 & ~CORE_CLK_PWRSAVE,
2580 host->ioaddr + CORE_VENDOR_SPEC);
2581
Sahitya Tummala22dd3362013-02-28 19:50:51 +05302582 sup_clock = sdhci_msm_get_sup_clk_rate(host, clock);
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -07002583 if ((curr_ios.timing == MMC_TIMING_UHS_DDR50) ||
Venkat Gopalakrishnan0a29da92015-01-09 12:19:16 -08002584 (curr_ios.timing == MMC_TIMING_MMC_DDR52) ||
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -07002585 (curr_ios.timing == MMC_TIMING_MMC_HS400)) {
Sahitya Tummala22dd3362013-02-28 19:50:51 +05302586 /*
2587 * The SDHC requires internal clock frequency to be double the
2588 * actual clock that will be set for DDR mode. The controller
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -07002589 * uses the faster clock(100/400MHz) for some of its parts and
2590 * send the actual required clock (50/200MHz) to the card.
Sahitya Tummala22dd3362013-02-28 19:50:51 +05302591 */
2592 ddr_clock = clock * 2;
2593 sup_clock = sdhci_msm_get_sup_clk_rate(host,
2594 ddr_clock);
2595 }
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -07002596
2597 /*
2598 * In general all timing modes are controlled via UHS mode select in
2599 * Host Control2 register. eMMC specific HS200/HS400 doesn't have
2600 * their respective modes defined here, hence we use these values.
2601 *
2602 * HS200 - SDR104 (Since they both are equivalent in functionality)
2603 * HS400 - This involves multiple configurations
2604 * Initially SDR104 - when tuning is required as HS200
2605 * Then when switching to DDR @ 400MHz (HS400) we use
2606 * the vendor specific HC_SELECT_IN to control the mode.
2607 *
2608 * In addition to controlling the modes we also need to select the
2609 * correct input clock for DLL depending on the mode.
2610 *
2611 * HS400 - divided clock (free running MCLK/2)
2612 * All other modes - default (free running MCLK)
2613 */
2614 if (curr_ios.timing == MMC_TIMING_MMC_HS400) {
2615 /* Select the divided clock (free running MCLK/2) */
2616 writel_relaxed(((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
2617 & ~CORE_HC_MCLK_SEL_MASK)
2618 | CORE_HC_MCLK_SEL_HS400),
2619 host->ioaddr + CORE_VENDOR_SPEC);
2620 /*
2621 * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
2622 * register
2623 */
Ritesh Harjaniea709662015-05-27 15:40:24 +05302624 if ((msm_host->tuning_done || msm_host->enhanced_strobe) &&
2625 !msm_host->calibration_done) {
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -07002626 /*
2627 * Write 0x6 to HC_SELECT_IN and 1 to HC_SELECT_IN_EN
2628 * field in VENDOR_SPEC_FUNC
2629 */
2630 writel_relaxed((readl_relaxed(host->ioaddr + \
2631 CORE_VENDOR_SPEC)
2632 | CORE_HC_SELECT_IN_HS400
2633 | CORE_HC_SELECT_IN_EN),
2634 host->ioaddr + CORE_VENDOR_SPEC);
2635 }
Krishna Konda2faa7bb2014-06-04 01:25:16 -07002636 if (!host->mmc->ios.old_rate && !msm_host->use_cdclp533) {
2637 /*
2638 * Poll on DLL_LOCK and DDR_DLL_LOCK bits in
2639 * CORE_DLL_STATUS to be set. This should get set
2640 * with in 15 us at 200 MHz.
2641 */
2642 rc = readl_poll_timeout(host->ioaddr + CORE_DLL_STATUS,
2643 dll_lock, (dll_lock & (CORE_DLL_LOCK |
2644 CORE_DDR_DLL_LOCK)), 10, 1000);
2645 if (rc == -ETIMEDOUT)
2646 pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
2647 mmc_hostname(host->mmc),
2648 dll_lock);
2649 }
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -07002650 } else {
Krishna Konda2faa7bb2014-06-04 01:25:16 -07002651 if (!msm_host->use_cdclp533)
2652 /* set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3 */
2653 writel_relaxed((readl_relaxed(host->ioaddr +
2654 CORE_VENDOR_SPEC3) & ~CORE_PWRSAVE_DLL),
2655 host->ioaddr + CORE_VENDOR_SPEC3);
2656
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -07002657 /* Select the default clock (free running MCLK) */
2658 writel_relaxed(((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
2659 & ~CORE_HC_MCLK_SEL_MASK)
2660 | CORE_HC_MCLK_SEL_DFLT),
2661 host->ioaddr + CORE_VENDOR_SPEC);
2662
2663 /*
2664 * Disable HC_SELECT_IN to be able to use the UHS mode select
2665 * configuration from Host Control2 register for all other
2666 * modes.
2667 *
2668 * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
2669 * in VENDOR_SPEC_FUNC
2670 */
2671 writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
2672 & ~CORE_HC_SELECT_IN_EN
2673 & ~CORE_HC_SELECT_IN_MASK),
2674 host->ioaddr + CORE_VENDOR_SPEC);
2675 }
2676 mb();
2677
Sahitya Tummala22dd3362013-02-28 19:50:51 +05302678 if (sup_clock != msm_host->clk_rate) {
2679 pr_debug("%s: %s: setting clk rate to %u\n",
2680 mmc_hostname(host->mmc), __func__, sup_clock);
2681 rc = clk_set_rate(msm_host->clk, sup_clock);
2682 if (rc) {
2683 pr_err("%s: %s: Failed to set rate %u for host-clk : %d\n",
2684 mmc_hostname(host->mmc), __func__,
2685 sup_clock, rc);
2686 goto out;
2687 }
2688 msm_host->clk_rate = sup_clock;
2689 host->clock = clock;
Sahitya Tummala79edc6a2013-05-23 15:59:22 +05302690 /*
2691 * Update the bus vote in case of frequency change due to
2692 * clock scaling.
2693 */
2694 sdhci_msm_bus_voting(host, 1);
Sahitya Tummala22dd3362013-02-28 19:50:51 +05302695 }
2696out:
2697 sdhci_set_clock(host, clock);
Sahitya Tummalaa7f3c572013-01-11 11:30:45 +05302698}
2699
Sahitya Tummala14613432013-03-21 11:13:25 +05302700static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
2701 unsigned int uhs)
2702{
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -07002703 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2704 struct sdhci_msm_host *msm_host = pltfm_host->priv;
Sahitya Tummala14613432013-03-21 11:13:25 +05302705 u16 ctrl_2;
2706
2707 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2708 /* Select Bus Speed Mode for host */
2709 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
Venkat Gopalakrishnan0a29da92015-01-09 12:19:16 -08002710 if ((uhs == MMC_TIMING_MMC_HS400) ||
2711 (uhs == MMC_TIMING_MMC_HS200) ||
2712 (uhs == MMC_TIMING_UHS_SDR104))
Sahitya Tummala14613432013-03-21 11:13:25 +05302713 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
2714 else if (uhs == MMC_TIMING_UHS_SDR12)
2715 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
2716 else if (uhs == MMC_TIMING_UHS_SDR25)
2717 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
2718 else if (uhs == MMC_TIMING_UHS_SDR50)
2719 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
Venkat Gopalakrishnan0a29da92015-01-09 12:19:16 -08002720 else if ((uhs == MMC_TIMING_UHS_DDR50) ||
2721 (uhs == MMC_TIMING_MMC_DDR52))
Sahitya Tummala14613432013-03-21 11:13:25 +05302722 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
Sahitya Tummala22dd3362013-02-28 19:50:51 +05302723 /*
2724 * When clock frquency is less than 100MHz, the feedback clock must be
2725 * provided and DLL must not be used so that tuning can be skipped. To
2726 * provide feedback clock, the mode selection can be any value less
2727 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
2728 */
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -07002729 if (host->clock <= CORE_FREQ_100MHZ) {
2730 if ((uhs == MMC_TIMING_MMC_HS400) ||
2731 (uhs == MMC_TIMING_MMC_HS200) ||
2732 (uhs == MMC_TIMING_UHS_SDR104))
2733 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
Sahitya Tummala22dd3362013-02-28 19:50:51 +05302734
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -07002735 /*
2736 * Make sure DLL is disabled when not required
2737 *
2738 * Write 1 to DLL_RST bit of DLL_CONFIG register
2739 */
2740 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
2741 | CORE_DLL_RST),
2742 host->ioaddr + CORE_DLL_CONFIG);
2743
2744 /* Write 1 to DLL_PDN bit of DLL_CONFIG register */
2745 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
2746 | CORE_DLL_PDN),
2747 host->ioaddr + CORE_DLL_CONFIG);
2748 mb();
2749
2750 /*
2751 * The DLL needs to be restored and CDCLP533 recalibrated
2752 * when the clock frequency is set back to 400MHz.
2753 */
2754 msm_host->calibration_done = false;
2755 }
2756
2757 pr_debug("%s: %s-clock:%u uhs mode:%u ctrl_2:0x%x\n",
2758 mmc_hostname(host->mmc), __func__, host->clock, uhs, ctrl_2);
Sahitya Tummala14613432013-03-21 11:13:25 +05302759 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2760
2761}
2762
Venkat Gopalakrishnan34811972015-03-04 14:39:01 -08002763#define MAX_TEST_BUS 60
Sahitya Tummala67717bc2013-08-02 09:21:37 +05302764
2765void sdhci_msm_dump_vendor_regs(struct sdhci_host *host)
2766{
2767 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2768 struct sdhci_msm_host *msm_host = pltfm_host->priv;
2769 int tbsel, tbsel2;
2770 int i, index = 0;
2771 u32 test_bus_val = 0;
2772 u32 debug_reg[MAX_TEST_BUS] = {0};
2773
2774 pr_info("----------- VENDOR REGISTER DUMP -----------\n");
2775 pr_info("Data cnt: 0x%08x | Fifo cnt: 0x%08x | Int sts: 0x%08x\n",
2776 readl_relaxed(msm_host->core_mem + CORE_MCI_DATA_CNT),
2777 readl_relaxed(msm_host->core_mem + CORE_MCI_FIFO_CNT),
2778 readl_relaxed(msm_host->core_mem + CORE_MCI_STATUS));
2779 pr_info("DLL cfg: 0x%08x | DLL sts: 0x%08x | SDCC ver: 0x%08x\n",
2780 readl_relaxed(host->ioaddr + CORE_DLL_CONFIG),
2781 readl_relaxed(host->ioaddr + CORE_DLL_STATUS),
2782 readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION));
2783 pr_info("Vndr func: 0x%08x | Vndr adma err : addr0: 0x%08x addr1: 0x%08x\n",
2784 readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC),
2785 readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC_ADMA_ERR_ADDR0),
2786 readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC_ADMA_ERR_ADDR1));
2787
2788 /*
2789 * tbsel indicates [2:0] bits and tbsel2 indicates [7:4] bits
2790 * of CORE_TESTBUS_CONFIG register.
2791 *
2792 * To select test bus 0 to 7 use tbsel and to select any test bus
2793 * above 7 use (tbsel2 | tbsel) to get the test bus number. For eg,
2794 * to select test bus 14, write 0x1E to CORE_TESTBUS_CONFIG register
2795 * i.e., tbsel2[7:4] = 0001, tbsel[2:0] = 110.
2796 */
Venkat Gopalakrishnan34811972015-03-04 14:39:01 -08002797 for (tbsel2 = 0; tbsel2 < 7; tbsel2++) {
Sahitya Tummala67717bc2013-08-02 09:21:37 +05302798 for (tbsel = 0; tbsel < 8; tbsel++) {
2799 if (index >= MAX_TEST_BUS)
2800 break;
2801 test_bus_val = (tbsel2 << CORE_TESTBUS_SEL2_BIT) |
2802 tbsel | CORE_TESTBUS_ENA;
2803 writel_relaxed(test_bus_val,
2804 msm_host->core_mem + CORE_TESTBUS_CONFIG);
2805 debug_reg[index++] = readl_relaxed(msm_host->core_mem +
2806 CORE_SDCC_DEBUG_REG);
2807 }
2808 }
2809 for (i = 0; i < MAX_TEST_BUS; i = i + 4)
2810 pr_info(" Test bus[%d to %d]: 0x%08x 0x%08x 0x%08x 0x%08x\n",
2811 i, i + 3, debug_reg[i], debug_reg[i+1],
2812 debug_reg[i+2], debug_reg[i+3]);
Venkat Gopalakrishnan06f7f792015-05-29 17:56:59 -07002813}
2814
Ritesh Harjani4a5ffd12015-07-15 13:32:07 +05302815/*
2816 * sdhci_msm_enhanced_strobe_mask :-
2817 * Before running CMDQ transfers in HS400 Enhanced Strobe mode,
2818 * SW should write 3 to
2819 * HC_VENDOR_SPECIFIC_FUNC3.CMDEN_HS400_INPUT_MASK_CNT register.
2820 * The default reset value of this register is 2.
2821 */
2822static void sdhci_msm_enhanced_strobe_mask(struct sdhci_host *host, bool set)
2823{
2824 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2825 struct sdhci_msm_host *msm_host = pltfm_host->priv;
2826
2827 if (!msm_host->enhanced_strobe) {
2828 pr_debug("%s: host does not support hs400 enhanced strobe\n",
2829 mmc_hostname(host->mmc));
2830 return;
2831 }
2832
2833 if (set) {
2834 writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC3)
2835 | CORE_CMDEN_HS400_INPUT_MASK_CNT),
2836 host->ioaddr + CORE_VENDOR_SPEC3);
2837 } else {
2838 writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC3)
2839 & ~CORE_CMDEN_HS400_INPUT_MASK_CNT),
2840 host->ioaddr + CORE_VENDOR_SPEC3);
2841 }
2842}
2843
Venkat Gopalakrishnan06f7f792015-05-29 17:56:59 -07002844static void sdhci_msm_clear_set_dumpregs(struct sdhci_host *host, bool set)
2845{
2846 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2847 struct sdhci_msm_host *msm_host = pltfm_host->priv;
2848
2849 if (set) {
2850 writel_relaxed(CORE_TESTBUS_ENA,
2851 msm_host->core_mem + CORE_TESTBUS_CONFIG);
2852 } else {
2853 u32 value;
2854
2855 value = readl_relaxed(msm_host->core_mem + CORE_TESTBUS_CONFIG);
2856 value &= ~CORE_TESTBUS_ENA;
2857 writel_relaxed(value, msm_host->core_mem + CORE_TESTBUS_CONFIG);
2858 }
Sahitya Tummala67717bc2013-08-02 09:21:37 +05302859}
2860
Dov Levenglick9c575e22015-07-20 09:30:52 +03002861static void sdhci_msm_detect(struct sdhci_host *host, bool detected)
2862{
2863 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2864 struct sdhci_msm_host *msm_host = pltfm_host->priv;
2865 struct mmc_host *mmc = msm_host->mmc;
2866 struct mmc_card *card = mmc->card;
2867
2868 if (detected && mmc_card_sdio(card))
2869 mmc->pm_caps |= MMC_PM_KEEP_POWER;
2870 else
2871 mmc->pm_caps &= ~MMC_PM_KEEP_POWER;
2872}
2873
Asutosh Das0ef24812012-12-18 16:14:02 +05302874static struct sdhci_ops sdhci_msm_ops = {
Sahitya Tummala14613432013-03-21 11:13:25 +05302875 .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
Asutosh Das0ef24812012-12-18 16:14:02 +05302876 .check_power_status = sdhci_msm_check_power_status,
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -07002877 .platform_execute_tuning = sdhci_msm_execute_tuning,
Ritesh Harjaniea709662015-05-27 15:40:24 +05302878 .enhanced_strobe = sdhci_msm_enhanced_strobe,
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -07002879 .toggle_cdr = sdhci_msm_toggle_cdr,
Asutosh Das648f9d12013-01-10 21:11:04 +05302880 .get_max_segments = sdhci_msm_max_segs,
Sahitya Tummalaa7f3c572013-01-11 11:30:45 +05302881 .set_clock = sdhci_msm_set_clock,
Sahitya Tummala22dd3362013-02-28 19:50:51 +05302882 .get_min_clock = sdhci_msm_get_min_clock,
2883 .get_max_clock = sdhci_msm_get_max_clock,
Sahitya Tummala67717bc2013-08-02 09:21:37 +05302884 .dump_vendor_regs = sdhci_msm_dump_vendor_regs,
Asutosh Dase5e9ca62013-07-30 19:08:36 +05302885 .config_auto_tuning_cmd = sdhci_msm_config_auto_tuning_cmd,
Asutosh Das9d7ee2f2013-11-08 12:33:47 +05302886 .enable_controller_clock = sdhci_msm_enable_controller_clock,
Venkat Gopalakrishnanb8cb7072015-01-09 11:04:34 -08002887 .set_bus_width = sdhci_set_bus_width,
Venkat Gopalakrishnan411df072015-01-09 11:09:44 -08002888 .reset = sdhci_reset,
Venkat Gopalakrishnan06f7f792015-05-29 17:56:59 -07002889 .clear_set_dumpregs = sdhci_msm_clear_set_dumpregs,
Ritesh Harjani4a5ffd12015-07-15 13:32:07 +05302890 .enhanced_strobe_mask = sdhci_msm_enhanced_strobe_mask,
Dov Levenglick9c575e22015-07-20 09:30:52 +03002891 .detect = sdhci_msm_detect,
Asutosh Das0ef24812012-12-18 16:14:02 +05302892};
2893
Pratibhasagar Vd8acb7c2013-11-11 01:32:21 +05302894static void sdhci_set_default_hw_caps(struct sdhci_msm_host *msm_host,
2895 struct sdhci_host *host)
2896{
Krishna Konda46fd1432014-10-30 21:13:27 -07002897 u32 version, caps = 0;
Pratibhasagar Vd8acb7c2013-11-11 01:32:21 +05302898 u16 minor;
2899 u8 major;
2900
2901 version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION);
2902 major = (version & CORE_VERSION_MAJOR_MASK) >>
2903 CORE_VERSION_MAJOR_SHIFT;
2904 minor = version & CORE_VERSION_TARGET_MASK;
2905
Krishna Konda46fd1432014-10-30 21:13:27 -07002906 caps = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
2907
Pratibhasagar Vd8acb7c2013-11-11 01:32:21 +05302908 /*
2909 * Starting with SDCC 5 controller (core major version = 1)
Venkat Gopalakrishnan3ac8fd32014-08-28 18:15:45 -07002910 * controller won't advertise 3.0v, 1.8v and 8-bit features
2911 * except for some targets.
Pratibhasagar Vd8acb7c2013-11-11 01:32:21 +05302912 */
2913 if (major >= 1 && minor != 0x11 && minor != 0x12) {
Venkat Gopalakrishnan3ac8fd32014-08-28 18:15:45 -07002914 struct sdhci_msm_reg_data *vdd_io_reg;
Venkat Gopalakrishnan3ac8fd32014-08-28 18:15:45 -07002915 /*
2916 * Enable 1.8V support capability on controllers that
2917 * support dual voltage
2918 */
2919 vdd_io_reg = msm_host->pdata->vreg_data->vdd_io_data;
Krishna Konda46fd1432014-10-30 21:13:27 -07002920 if (vdd_io_reg && (vdd_io_reg->high_vol_level > 2700000))
2921 caps |= CORE_3_0V_SUPPORT;
2922 if (vdd_io_reg && (vdd_io_reg->low_vol_level < 1950000))
Venkat Gopalakrishnan3ac8fd32014-08-28 18:15:45 -07002923 caps |= CORE_1_8V_SUPPORT;
Pratibhasagar Vada47992013-12-09 20:42:32 +05302924 if (msm_host->pdata->mmc_bus_width == MMC_CAP_8_BIT_DATA)
2925 caps |= CORE_8_BIT_SUPPORT;
Pratibhasagar Vd8acb7c2013-11-11 01:32:21 +05302926 }
Krishna Konda2faa7bb2014-06-04 01:25:16 -07002927
2928 /*
2929 * SDCC 5 controller with major version 1, minor version 0x34 and later
2930 * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
2931 */
2932 if ((major == 1) && (minor < 0x34))
2933 msm_host->use_cdclp533 = true;
Gilad Broner2a10ca02014-10-02 17:20:35 +03002934
2935 /*
Venkat Gopalakrishnanc0a5c3a2015-02-03 16:10:07 -08002936 * SDCC 5 controller with major version 1, minor version 0x42 and later
2937 * will require additional steps when resetting DLL.
Ritesh Harjaniea709662015-05-27 15:40:24 +05302938 * It also supports HS400 enhanced strobe mode.
Venkat Gopalakrishnanc0a5c3a2015-02-03 16:10:07 -08002939 */
Ritesh Harjaniea709662015-05-27 15:40:24 +05302940 if ((major == 1) && (minor >= 0x42)) {
Venkat Gopalakrishnanc0a5c3a2015-02-03 16:10:07 -08002941 msm_host->use_updated_dll_reset = true;
Ritesh Harjaniea709662015-05-27 15:40:24 +05302942 msm_host->enhanced_strobe = true;
2943 }
Venkat Gopalakrishnanc0a5c3a2015-02-03 16:10:07 -08002944
2945 /*
Talel Shenhar9a25b882015-06-02 13:36:35 +03002946 * SDCC 5 controller with major version 1 and minor version 0x42,
2947 * 0x46 and 0x49 currently uses 14lpp tech DLL whose internal
2948 * gating cannot guarantee MCLK timing requirement i.e.
Ritesh Harjani764065e2015-05-13 14:14:45 +05302949 * when MCLK is gated OFF, it is not gated for less than 0.5us
2950 * and MCLK must be switched on for at-least 1us before DATA
2951 * starts coming.
2952 */
Talel Shenhar9a25b882015-06-02 13:36:35 +03002953 if ((major == 1) && ((minor == 0x42) || (minor == 0x46) ||
2954 (minor == 0x49)))
Ritesh Harjani764065e2015-05-13 14:14:45 +05302955 msm_host->use_14lpp_dll = true;
2956 /*
Gilad Broner2a10ca02014-10-02 17:20:35 +03002957 * Mask 64-bit support for controller with 32-bit address bus so that
2958 * smaller descriptor size will be used and improve memory consumption.
Gilad Broner2a10ca02014-10-02 17:20:35 +03002959 */
Venkat Gopalakrishnan9a62e042015-03-03 16:14:55 -08002960 if (!msm_host->pdata->largeaddressbus)
2961 caps &= ~CORE_SYS_BUS_SUPPORT_64_BIT;
2962
Gilad Broner2a10ca02014-10-02 17:20:35 +03002963 writel_relaxed(caps, host->ioaddr + CORE_VENDOR_SPEC_CAPABILITIES0);
Krishna Konda46fd1432014-10-30 21:13:27 -07002964 /* keep track of the value in SDHCI_CAPABILITIES */
2965 msm_host->caps_0 = caps;
Pratibhasagar Vd8acb7c2013-11-11 01:32:21 +05302966}
2967
Venkat Gopalakrishnand371f142015-05-29 17:49:46 -07002968#ifdef CONFIG_MMC_CQ_HCI
2969static void sdhci_msm_cmdq_init(struct sdhci_host *host,
2970 struct platform_device *pdev)
2971{
2972 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2973 struct sdhci_msm_host *msm_host = pltfm_host->priv;
2974
2975 host->cq_host = cmdq_pltfm_init(pdev);
2976 if (IS_ERR(host->cq_host))
2977 dev_dbg(&pdev->dev, "cmdq-pltfm init: failed: %ld\n",
2978 PTR_ERR(host->cq_host));
2979 else
2980 msm_host->mmc->caps2 |= MMC_CAP2_CMD_QUEUE;
2981}
2982#else
2983static void sdhci_msm_cmdq_init(struct sdhci_host *host,
2984 struct platform_device *pdev)
2985{
2986
2987}
2988#endif
2989
Subhash Jadavaniebcd00d2015-07-09 17:28:42 -07002990static bool sdhci_msm_is_bootdevice(struct device *dev)
2991{
2992 if (strnstr(saved_command_line, "androidboot.bootdevice=",
2993 strlen(saved_command_line))) {
2994 char search_string[50];
2995
2996 snprintf(search_string, ARRAY_SIZE(search_string),
2997 "androidboot.bootdevice=%s", dev_name(dev));
2998 if (strnstr(saved_command_line, search_string,
2999 strlen(saved_command_line)))
3000 return true;
3001 else
3002 return false;
3003 }
3004
3005 /*
3006 * "androidboot.bootdevice=" argument is not present then
3007 * return true as we don't know the boot device anyways.
3008 */
3009 return true;
3010}
3011
Asutosh Das0ef24812012-12-18 16:14:02 +05303012static int sdhci_msm_probe(struct platform_device *pdev)
3013{
3014 struct sdhci_host *host;
3015 struct sdhci_pltfm_host *pltfm_host;
3016 struct sdhci_msm_host *msm_host;
3017 struct resource *core_memres = NULL;
Konstantein Dorfmane0be02d2015-01-27 12:06:02 +02003018 int ret = 0, dead = 0;
Stephen Boyd8dce5c62013-04-24 14:19:46 -07003019 u16 host_version;
Venkat Gopalakrishnan17edb352015-06-24 14:46:49 -07003020 u32 irq_status, irq_ctl;
Asutosh Das0ef24812012-12-18 16:14:02 +05303021
3022 pr_debug("%s: Enter %s\n", dev_name(&pdev->dev), __func__);
3023 msm_host = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_msm_host),
3024 GFP_KERNEL);
3025 if (!msm_host) {
3026 ret = -ENOMEM;
3027 goto out;
3028 }
Asutosh Das0ef24812012-12-18 16:14:02 +05303029
3030 msm_host->sdhci_msm_pdata.ops = &sdhci_msm_ops;
3031 host = sdhci_pltfm_init(pdev, &msm_host->sdhci_msm_pdata, 0);
3032 if (IS_ERR(host)) {
3033 ret = PTR_ERR(host);
3034 goto out;
3035 }
3036
3037 pltfm_host = sdhci_priv(host);
3038 pltfm_host->priv = msm_host;
3039 msm_host->mmc = host->mmc;
Sahitya Tummala8a3e8182013-03-10 14:12:52 +05303040 msm_host->pdev = pdev;
Asutosh Das0ef24812012-12-18 16:14:02 +05303041
3042 /* Extract platform data */
3043 if (pdev->dev.of_node) {
Venkat Gopalakrishnan270580a2013-03-11 12:17:57 -07003044 ret = of_alias_get_id(pdev->dev.of_node, "sdhc");
3045 if (ret < 0) {
3046 dev_err(&pdev->dev, "Failed to get slot index %d\n",
3047 ret);
3048 goto pltfm_free;
3049 }
Subhash Jadavaniebcd00d2015-07-09 17:28:42 -07003050
3051 /* skip the probe if eMMC isn't a boot device */
3052 if ((ret == 1) && !sdhci_msm_is_bootdevice(&pdev->dev))
3053 goto pltfm_free;
3054
Venkat Gopalakrishnan270580a2013-03-11 12:17:57 -07003055 if (disable_slots & (1 << (ret - 1))) {
3056 dev_info(&pdev->dev, "%s: Slot %d disabled\n", __func__,
3057 ret);
3058 ret = -ENODEV;
3059 goto pltfm_free;
3060 }
3061
Dov Levenglickc9033ab2015-03-10 16:00:56 +02003062 msm_host->pdata = sdhci_msm_populate_pdata(&pdev->dev,
3063 msm_host);
Asutosh Das0ef24812012-12-18 16:14:02 +05303064 if (!msm_host->pdata) {
3065 dev_err(&pdev->dev, "DT parsing error\n");
3066 goto pltfm_free;
3067 }
3068 } else {
3069 dev_err(&pdev->dev, "No device tree node\n");
3070 goto pltfm_free;
3071 }
3072
3073 /* Setup Clocks */
3074
3075 /* Setup SDCC bus voter clock. */
3076 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
3077 if (!IS_ERR_OR_NULL(msm_host->bus_clk)) {
3078 /* Vote for max. clk rate for max. performance */
3079 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
3080 if (ret)
3081 goto pltfm_free;
3082 ret = clk_prepare_enable(msm_host->bus_clk);
3083 if (ret)
3084 goto pltfm_free;
3085 }
3086
3087 /* Setup main peripheral bus clock */
3088 msm_host->pclk = devm_clk_get(&pdev->dev, "iface_clk");
3089 if (!IS_ERR(msm_host->pclk)) {
3090 ret = clk_prepare_enable(msm_host->pclk);
3091 if (ret)
3092 goto bus_clk_disable;
3093 }
Asutosh Das9d7ee2f2013-11-08 12:33:47 +05303094 atomic_set(&msm_host->controller_clock, 1);
Asutosh Das0ef24812012-12-18 16:14:02 +05303095
3096 /* Setup SDC MMC clock */
3097 msm_host->clk = devm_clk_get(&pdev->dev, "core_clk");
3098 if (IS_ERR(msm_host->clk)) {
3099 ret = PTR_ERR(msm_host->clk);
3100 goto pclk_disable;
3101 }
3102
Sahitya Tummala22dd3362013-02-28 19:50:51 +05303103 /* Set to the minimum supported clock frequency */
3104 ret = clk_set_rate(msm_host->clk, sdhci_msm_get_min_clock(host));
3105 if (ret) {
3106 dev_err(&pdev->dev, "MClk rate set failed (%d)\n", ret);
Sahitya Tummala020ede0d2013-06-07 13:03:07 +05303107 goto pclk_disable;
Sahitya Tummala22dd3362013-02-28 19:50:51 +05303108 }
Sahitya Tummala020ede0d2013-06-07 13:03:07 +05303109 ret = clk_prepare_enable(msm_host->clk);
3110 if (ret)
3111 goto pclk_disable;
3112
Sahitya Tummala22dd3362013-02-28 19:50:51 +05303113 msm_host->clk_rate = sdhci_msm_get_min_clock(host);
Sahitya Tummalaa7f3c572013-01-11 11:30:45 +05303114 atomic_set(&msm_host->clks_on, 1);
Sahitya Tummala22dd3362013-02-28 19:50:51 +05303115
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -07003116 /* Setup CDC calibration fixed feedback clock */
3117 msm_host->ff_clk = devm_clk_get(&pdev->dev, "cal_clk");
3118 if (!IS_ERR(msm_host->ff_clk)) {
3119 ret = clk_prepare_enable(msm_host->ff_clk);
3120 if (ret)
3121 goto clk_disable;
3122 }
3123
3124 /* Setup CDC calibration sleep clock */
3125 msm_host->sleep_clk = devm_clk_get(&pdev->dev, "sleep_clk");
3126 if (!IS_ERR(msm_host->sleep_clk)) {
3127 ret = clk_prepare_enable(msm_host->sleep_clk);
3128 if (ret)
3129 goto ff_clk_disable;
3130 }
3131
Venkat Gopalakrishnan9e069632013-06-12 11:16:37 -07003132 msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
3133
Sahitya Tummala79edc6a2013-05-23 15:59:22 +05303134 ret = sdhci_msm_bus_register(msm_host, pdev);
3135 if (ret)
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -07003136 goto sleep_clk_disable;
Sahitya Tummala79edc6a2013-05-23 15:59:22 +05303137
3138 if (msm_host->msm_bus_vote.client_handle)
3139 INIT_DELAYED_WORK(&msm_host->msm_bus_vote.vote_work,
3140 sdhci_msm_bus_work);
3141 sdhci_msm_bus_voting(host, 1);
3142
Asutosh Das0ef24812012-12-18 16:14:02 +05303143 /* Setup regulators */
3144 ret = sdhci_msm_vreg_init(&pdev->dev, msm_host->pdata, true);
3145 if (ret) {
3146 dev_err(&pdev->dev, "Regulator setup failed (%d)\n", ret);
Sahitya Tummala79edc6a2013-05-23 15:59:22 +05303147 goto bus_unregister;
Asutosh Das0ef24812012-12-18 16:14:02 +05303148 }
3149
3150 /* Reset the core and Enable SDHC mode */
3151 core_memres = platform_get_resource_byname(pdev,
3152 IORESOURCE_MEM, "core_mem");
Asutosh Das890bdee2014-08-08 23:01:42 +05303153 if (!core_memres) {
3154 dev_err(&pdev->dev, "Failed to get iomem resource\n");
3155 goto vreg_deinit;
3156 }
Asutosh Das0ef24812012-12-18 16:14:02 +05303157 msm_host->core_mem = devm_ioremap(&pdev->dev, core_memres->start,
3158 resource_size(core_memres));
3159
3160 if (!msm_host->core_mem) {
3161 dev_err(&pdev->dev, "Failed to remap registers\n");
3162 ret = -ENOMEM;
3163 goto vreg_deinit;
3164 }
3165
Sahitya Tummala66b0fe32013-04-25 11:50:56 +05303166 /*
Venkat Gopalakrishnan17edb352015-06-24 14:46:49 -07003167 * Reset the vendor spec register to power on reset state.
Sahitya Tummala66b0fe32013-04-25 11:50:56 +05303168 */
Venkat Gopalakrishnan17edb352015-06-24 14:46:49 -07003169 writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
3170 host->ioaddr + CORE_VENDOR_SPEC);
Sahitya Tummala66b0fe32013-04-25 11:50:56 +05303171
Asutosh Das0ef24812012-12-18 16:14:02 +05303172 /* Set HC_MODE_EN bit in HC_MODE register */
3173 writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
3174
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -07003175 /* Set FF_CLK_SW_RST_DIS bit in HC_MODE register */
3176 writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_HC_MODE) |
3177 FF_CLK_SW_RST_DIS, msm_host->core_mem + CORE_HC_MODE);
3178
Pratibhasagar Vd8acb7c2013-11-11 01:32:21 +05303179 sdhci_set_default_hw_caps(msm_host, host);
Krishna Konda46fd1432014-10-30 21:13:27 -07003180
3181 /*
3182 * Set the PAD_PWR_SWTICH_EN bit so that the PAD_PWR_SWITCH bit can
3183 * be used as required later on.
3184 */
3185 writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
3186 CORE_IO_PAD_PWR_SWITCH_EN),
3187 host->ioaddr + CORE_VENDOR_SPEC);
Asutosh Das0ef24812012-12-18 16:14:02 +05303188 /*
Subhash Jadavani28137342013-05-14 17:46:43 +05303189 * CORE_SW_RST above may trigger power irq if previous status of PWRCTL
3190 * was either BUS_ON or IO_HIGH_V. So before we enable the power irq
3191 * interrupt in GIC (by registering the interrupt handler), we need to
3192 * ensure that any pending power irq interrupt status is acknowledged
3193 * otherwise power irq interrupt handler would be fired prematurely.
3194 */
3195 irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS);
3196 writel_relaxed(irq_status, (msm_host->core_mem + CORE_PWRCTL_CLEAR));
3197 irq_ctl = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_CTL);
3198 if (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF))
3199 irq_ctl |= CORE_PWRCTL_BUS_SUCCESS;
3200 if (irq_status & (CORE_PWRCTL_IO_HIGH | CORE_PWRCTL_IO_LOW))
3201 irq_ctl |= CORE_PWRCTL_IO_SUCCESS;
3202 writel_relaxed(irq_ctl, (msm_host->core_mem + CORE_PWRCTL_CTL));
Krishna Konda46fd1432014-10-30 21:13:27 -07003203
Subhash Jadavani28137342013-05-14 17:46:43 +05303204 /*
3205 * Ensure that above writes are propogated before interrupt enablement
3206 * in GIC.
3207 */
3208 mb();
3209
3210 /*
Asutosh Das0ef24812012-12-18 16:14:02 +05303211 * Following are the deviations from SDHC spec v3.0 -
3212 * 1. Card detection is handled using separate GPIO.
3213 * 2. Bus power control is handled by interacting with PMIC.
3214 */
3215 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
3216 host->quirks |= SDHCI_QUIRK_SINGLE_POWER_WRITE;
Sahitya Tummala22dd3362013-02-28 19:50:51 +05303217 host->quirks |= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
Talel Shenhar4661c2a2015-06-24 15:49:30 +03003218 host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
Sahitya Tummala22dd3362013-02-28 19:50:51 +05303219 host->quirks2 |= SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK;
Sahitya Tummala87d439442013-04-12 11:49:11 +05303220 host->quirks2 |= SDHCI_QUIRK2_IGNORE_DATATOUT_FOR_R1BCMD;
Sahitya Tummala314162c2013-04-12 12:11:20 +05303221 host->quirks2 |= SDHCI_QUIRK2_BROKEN_PRESET_VALUE;
Sahitya Tummala7c9780d2013-04-12 11:59:25 +05303222 host->quirks2 |= SDHCI_QUIRK2_USE_RESERVED_MAX_TIMEOUT;
Asutosh Das0ef24812012-12-18 16:14:02 +05303223
Sahitya Tummalaa5733ab52013-06-10 16:32:51 +05303224 if (host->quirks2 & SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK)
3225 host->quirks2 |= SDHCI_QUIRK2_DIVIDE_TOUT_BY_4;
3226
Stephen Boyd8dce5c62013-04-24 14:19:46 -07003227 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
Venkat Gopalakrishnana58f91f2012-09-17 16:00:15 -07003228 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
3229 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
3230 SDHCI_VENDOR_VER_SHIFT));
3231 if (((host_version & SDHCI_VENDOR_VER_MASK) >>
3232 SDHCI_VENDOR_VER_SHIFT) == SDHCI_VER_100) {
3233 /*
3234 * Add 40us delay in interrupt handler when
3235 * operating at initialization frequency(400KHz).
3236 */
3237 host->quirks2 |= SDHCI_QUIRK2_SLOW_INT_CLR;
3238 /*
3239 * Set Software Reset for DAT line in Software
3240 * Reset Register (Bit 2).
3241 */
3242 host->quirks2 |= SDHCI_QUIRK2_RDWR_TX_ACTIVE_EOT;
3243 }
3244
Asutosh Das214b9662013-06-13 14:27:42 +05303245 host->quirks2 |= SDHCI_QUIRK2_IGN_DATA_END_BIT_ERROR;
3246
Venkat Gopalakrishnana58f91f2012-09-17 16:00:15 -07003247 /* Setup PWRCTL irq */
Konstantein Dorfmane0be02d2015-01-27 12:06:02 +02003248 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
3249 if (msm_host->pwr_irq < 0) {
Asutosh Das0ef24812012-12-18 16:14:02 +05303250 dev_err(&pdev->dev, "Failed to get pwr_irq by name (%d)\n",
Konstantein Dorfmane0be02d2015-01-27 12:06:02 +02003251 msm_host->pwr_irq);
Asutosh Das0ef24812012-12-18 16:14:02 +05303252 goto vreg_deinit;
3253 }
Konstantein Dorfmane0be02d2015-01-27 12:06:02 +02003254 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
Asutosh Das0ef24812012-12-18 16:14:02 +05303255 sdhci_msm_pwr_irq, IRQF_ONESHOT,
Venkat Gopalakrishnan7944a372012-09-11 16:13:31 -07003256 dev_name(&pdev->dev), host);
Asutosh Das0ef24812012-12-18 16:14:02 +05303257 if (ret) {
3258 dev_err(&pdev->dev, "Request threaded irq(%d) failed (%d)\n",
Konstantein Dorfmane0be02d2015-01-27 12:06:02 +02003259 msm_host->pwr_irq, ret);
Asutosh Das0ef24812012-12-18 16:14:02 +05303260 goto vreg_deinit;
3261 }
3262
3263 /* Enable pwr irq interrupts */
3264 writel_relaxed(INT_MASK, (msm_host->core_mem + CORE_PWRCTL_MASK));
3265
Sahitya Tummalaa7f3c572013-01-11 11:30:45 +05303266#ifdef CONFIG_MMC_CLKGATE
3267 /* Set clock gating delay to be used when CONFIG_MMC_CLKGATE is set */
3268 msm_host->mmc->clkgate_delay = SDHCI_MSM_MMC_CLK_GATE_DELAY;
3269#endif
3270
Asutosh Das0ef24812012-12-18 16:14:02 +05303271 /* Set host capabilities */
3272 msm_host->mmc->caps |= msm_host->pdata->mmc_bus_width;
3273 msm_host->mmc->caps |= msm_host->pdata->caps;
Konstantin Dorfman98377d32015-02-25 10:09:41 +02003274 msm_host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM;
Asutosh Das0ef24812012-12-18 16:14:02 +05303275 msm_host->mmc->caps2 |= msm_host->pdata->caps2;
Venkat Gopalakrishnan97c16112014-12-16 18:26:25 -08003276 msm_host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
3277 msm_host->mmc->caps2 |= MMC_CAP2_FULL_PWR_CYCLE;
Subhash Jadavani6d472b22013-05-29 15:52:10 +05303278 msm_host->mmc->caps2 |= MMC_CAP2_ASYNC_SDIO_IRQ_4BIT_MODE;
Venkat Gopalakrishnan97c16112014-12-16 18:26:25 -08003279 msm_host->mmc->caps2 |= MMC_CAP2_HS400_POST_TUNING;
Talel Shenhar3d1dbf32015-05-13 14:08:39 +03003280 msm_host->mmc->caps2 |= MMC_CAP2_CLK_SCALE;
Asutosh Das0ef24812012-12-18 16:14:02 +05303281
3282 if (msm_host->pdata->nonremovable)
3283 msm_host->mmc->caps |= MMC_CAP_NONREMOVABLE;
3284
Guoping Yuf7c91332014-08-20 16:56:18 +08003285 if (msm_host->pdata->nonhotplug)
3286 msm_host->mmc->caps2 |= MMC_CAP2_NONHOTPLUG;
3287
Sahitya Tummalac6f48d42013-03-10 07:03:17 +05303288 host->cpu_dma_latency_us = msm_host->pdata->cpu_dma_latency_us;
Maya Erez994cf2f2014-10-21 20:22:04 +03003289 host->pm_qos_req_dma.type = msm_host->pdata->cpu_affinity_type;
Sahitya Tummalac6f48d42013-03-10 07:03:17 +05303290
Sahitya Tummala1f52eaa2013-03-20 19:24:01 +05303291 init_completion(&msm_host->pwr_irq_completion);
3292
Sahitya Tummala581df132013-03-12 14:57:46 +05303293 if (gpio_is_valid(msm_host->pdata->status_gpio)) {
Sahitya Tummala6ddabb42014-06-05 13:26:55 +05303294 /*
3295 * Set up the card detect GPIO in active configuration before
3296 * configuring it as an IRQ. Otherwise, it can be in some
3297 * weird/inconsistent state resulting in flood of interrupts.
3298 */
3299 sdhci_msm_setup_pins(msm_host->pdata, true);
3300
Sahitya Tummalaa3888f42015-02-05 14:05:27 +05303301 /*
3302 * This delay is needed for stabilizing the card detect GPIO
3303 * line after changing the pull configs.
3304 */
3305 usleep_range(10000, 10500);
Sahitya Tummala581df132013-03-12 14:57:46 +05303306 ret = mmc_gpio_request_cd(msm_host->mmc,
3307 msm_host->pdata->status_gpio, 0);
3308 if (ret) {
3309 dev_err(&pdev->dev, "%s: Failed to request card detection IRQ %d\n",
3310 __func__, ret);
Sahitya Tummala79edc6a2013-05-23 15:59:22 +05303311 goto vreg_deinit;
Sahitya Tummala581df132013-03-12 14:57:46 +05303312 }
3313 }
3314
Krishna Konda7feab352013-09-17 23:55:40 -07003315 if ((sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT) &&
3316 (dma_supported(mmc_dev(host->mmc), DMA_BIT_MASK(64)))) {
3317 host->dma_mask = DMA_BIT_MASK(64);
3318 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
Pavan Anamulaeeb3b142015-07-22 18:17:32 +05303319 mmc_dev(host->mmc)->coherent_dma_mask = host->dma_mask;
Krishna Konda7feab352013-09-17 23:55:40 -07003320 } else if (dma_supported(mmc_dev(host->mmc), DMA_BIT_MASK(32))) {
Sahitya Tummalaeaa21862013-03-20 19:34:59 +05303321 host->dma_mask = DMA_BIT_MASK(32);
3322 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
Pavan Anamulaeeb3b142015-07-22 18:17:32 +05303323 mmc_dev(host->mmc)->coherent_dma_mask = host->dma_mask;
Sahitya Tummalaeaa21862013-03-20 19:34:59 +05303324 } else {
3325 dev_err(&pdev->dev, "%s: Failed to set dma mask\n", __func__);
3326 }
3327
Venkat Gopalakrishnand371f142015-05-29 17:49:46 -07003328 sdhci_msm_cmdq_init(host, pdev);
Asutosh Das0ef24812012-12-18 16:14:02 +05303329 ret = sdhci_add_host(host);
3330 if (ret) {
3331 dev_err(&pdev->dev, "Add host failed (%d)\n", ret);
Sahitya Tummala581df132013-03-12 14:57:46 +05303332 goto vreg_deinit;
Asutosh Das0ef24812012-12-18 16:14:02 +05303333 }
3334
Konstantin Dorfman98377d32015-02-25 10:09:41 +02003335 pm_runtime_set_active(&pdev->dev);
3336 pm_runtime_enable(&pdev->dev);
3337 pm_runtime_set_autosuspend_delay(&pdev->dev, MSM_AUTOSUSPEND_DELAY_MS);
3338 pm_runtime_use_autosuspend(&pdev->dev);
3339
Sahitya Tummala8a3e8182013-03-10 14:12:52 +05303340 msm_host->msm_bus_vote.max_bus_bw.show = show_sdhci_max_bus_bw;
3341 msm_host->msm_bus_vote.max_bus_bw.store = store_sdhci_max_bus_bw;
3342 sysfs_attr_init(&msm_host->msm_bus_vote.max_bus_bw.attr);
3343 msm_host->msm_bus_vote.max_bus_bw.attr.name = "max_bus_bw";
3344 msm_host->msm_bus_vote.max_bus_bw.attr.mode = S_IRUGO | S_IWUSR;
3345 ret = device_create_file(&pdev->dev,
3346 &msm_host->msm_bus_vote.max_bus_bw);
3347 if (ret)
3348 goto remove_host;
3349
Sahitya Tummala5c55b932013-06-20 14:00:18 +05303350 if (!gpio_is_valid(msm_host->pdata->status_gpio)) {
3351 msm_host->polling.show = show_polling;
3352 msm_host->polling.store = store_polling;
3353 sysfs_attr_init(&msm_host->polling.attr);
3354 msm_host->polling.attr.name = "polling";
3355 msm_host->polling.attr.mode = S_IRUGO | S_IWUSR;
3356 ret = device_create_file(&pdev->dev, &msm_host->polling);
3357 if (ret)
3358 goto remove_max_bus_bw_file;
3359 }
Asutosh Dase5e9ca62013-07-30 19:08:36 +05303360
3361 msm_host->auto_cmd21_attr.show = show_auto_cmd21;
3362 msm_host->auto_cmd21_attr.store = store_auto_cmd21;
3363 sysfs_attr_init(&msm_host->auto_cmd21_attr.attr);
3364 msm_host->auto_cmd21_attr.attr.name = "enable_auto_cmd21";
3365 msm_host->auto_cmd21_attr.attr.mode = S_IRUGO | S_IWUSR;
3366 ret = device_create_file(&pdev->dev, &msm_host->auto_cmd21_attr);
3367 if (ret) {
3368 pr_err("%s: %s: failed creating auto-cmd21 attr: %d\n",
3369 mmc_hostname(host->mmc), __func__, ret);
3370 device_remove_file(&pdev->dev, &msm_host->auto_cmd21_attr);
3371 }
Asutosh Das0ef24812012-12-18 16:14:02 +05303372 /* Successful initialization */
3373 goto out;
3374
Sahitya Tummala5c55b932013-06-20 14:00:18 +05303375remove_max_bus_bw_file:
3376 device_remove_file(&pdev->dev, &msm_host->msm_bus_vote.max_bus_bw);
Asutosh Das0ef24812012-12-18 16:14:02 +05303377remove_host:
3378 dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
Konstantin Dorfman98377d32015-02-25 10:09:41 +02003379 pm_runtime_disable(&pdev->dev);
Asutosh Das0ef24812012-12-18 16:14:02 +05303380 sdhci_remove_host(host, dead);
3381vreg_deinit:
3382 sdhci_msm_vreg_init(&pdev->dev, msm_host->pdata, false);
Sahitya Tummala79edc6a2013-05-23 15:59:22 +05303383bus_unregister:
3384 if (msm_host->msm_bus_vote.client_handle)
3385 sdhci_msm_bus_cancel_work_and_set_vote(host, 0);
3386 sdhci_msm_bus_unregister(msm_host);
Venkat Gopalakrishnan7f691572013-06-23 17:36:46 -07003387sleep_clk_disable:
3388 if (!IS_ERR(msm_host->sleep_clk))
3389 clk_disable_unprepare(msm_host->sleep_clk);
3390ff_clk_disable:
3391 if (!IS_ERR(msm_host->ff_clk))
3392 clk_disable_unprepare(msm_host->ff_clk);
Asutosh Das0ef24812012-12-18 16:14:02 +05303393clk_disable:
3394 if (!IS_ERR(msm_host->clk))
3395 clk_disable_unprepare(msm_host->clk);
3396pclk_disable:
3397 if (!IS_ERR(msm_host->pclk))
3398 clk_disable_unprepare(msm_host->pclk);
3399bus_clk_disable:
3400 if (!IS_ERR_OR_NULL(msm_host->bus_clk))
3401 clk_disable_unprepare(msm_host->bus_clk);
3402pltfm_free:
3403 sdhci_pltfm_free(pdev);
3404out:
3405 pr_debug("%s: Exit %s\n", dev_name(&pdev->dev), __func__);
3406 return ret;
3407}
3408
3409static int sdhci_msm_remove(struct platform_device *pdev)
3410{
3411 struct sdhci_host *host = platform_get_drvdata(pdev);
3412 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
3413 struct sdhci_msm_host *msm_host = pltfm_host->priv;
3414 struct sdhci_msm_pltfm_data *pdata = msm_host->pdata;
3415 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
3416 0xffffffff);
3417
3418 pr_debug("%s: %s\n", dev_name(&pdev->dev), __func__);
Sahitya Tummala5c55b932013-06-20 14:00:18 +05303419 if (!gpio_is_valid(msm_host->pdata->status_gpio))
3420 device_remove_file(&pdev->dev, &msm_host->polling);
Sahitya Tummala8a3e8182013-03-10 14:12:52 +05303421 device_remove_file(&pdev->dev, &msm_host->msm_bus_vote.max_bus_bw);
Konstantin Dorfman98377d32015-02-25 10:09:41 +02003422 pm_runtime_disable(&pdev->dev);
Asutosh Das0ef24812012-12-18 16:14:02 +05303423 sdhci_remove_host(host, dead);
3424 sdhci_pltfm_free(pdev);
Sahitya Tummala581df132013-03-12 14:57:46 +05303425
Asutosh Das0ef24812012-12-18 16:14:02 +05303426 sdhci_msm_vreg_init(&pdev->dev, msm_host->pdata, false);
Sahitya Tummalaa7f3c572013-01-11 11:30:45 +05303427
Pratibhasagar V9acf2642013-11-21 21:07:21 +05303428 sdhci_msm_setup_pins(pdata, true);
3429 sdhci_msm_setup_pins(pdata, false);
Sahitya Tummala8a3e8182013-03-10 14:12:52 +05303430
3431 if (msm_host->msm_bus_vote.client_handle) {
3432 sdhci_msm_bus_cancel_work_and_set_vote(host, 0);
3433 sdhci_msm_bus_unregister(msm_host);
3434 }
Asutosh Das0ef24812012-12-18 16:14:02 +05303435 return 0;
3436}
3437
Konstantin Dorfman98377d32015-02-25 10:09:41 +02003438#ifdef CONFIG_PM
3439static int sdhci_msm_runtime_suspend(struct device *dev)
3440{
3441 struct sdhci_host *host = dev_get_drvdata(dev);
3442 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
3443 struct sdhci_msm_host *msm_host = pltfm_host->priv;
Konstantin Dorfmanddab0cc2015-02-25 16:23:50 +02003444 ktime_t start = ktime_get();
Konstantin Dorfman98377d32015-02-25 10:09:41 +02003445
3446 disable_irq(host->irq);
3447 disable_irq(msm_host->pwr_irq);
3448
3449 /*
3450 * Remove the vote immediately only if clocks are off in which
3451 * case we might have queued work to remove vote but it may not
3452 * be completed before runtime suspend or system suspend.
3453 */
3454 if (!atomic_read(&msm_host->clks_on)) {
3455 if (msm_host->msm_bus_vote.client_handle)
3456 sdhci_msm_bus_cancel_work_and_set_vote(host, 0);
3457 }
Konstantin Dorfmanddab0cc2015-02-25 16:23:50 +02003458 trace_sdhci_msm_runtime_suspend(mmc_hostname(host->mmc), 0,
3459 ktime_to_us(ktime_sub(ktime_get(), start)));
Konstantin Dorfman98377d32015-02-25 10:09:41 +02003460
3461 return 0;
3462}
3463
3464static int sdhci_msm_runtime_resume(struct device *dev)
3465{
3466 struct sdhci_host *host = dev_get_drvdata(dev);
3467 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
3468 struct sdhci_msm_host *msm_host = pltfm_host->priv;
Konstantin Dorfmanddab0cc2015-02-25 16:23:50 +02003469 ktime_t start = ktime_get();
Konstantin Dorfman98377d32015-02-25 10:09:41 +02003470
3471 enable_irq(msm_host->pwr_irq);
3472 enable_irq(host->irq);
3473
Konstantin Dorfmanddab0cc2015-02-25 16:23:50 +02003474 trace_sdhci_msm_runtime_resume(mmc_hostname(host->mmc), 0,
3475 ktime_to_us(ktime_sub(ktime_get(), start)));
Konstantin Dorfman98377d32015-02-25 10:09:41 +02003476 return 0;
3477}
3478
3479static int sdhci_msm_suspend(struct device *dev)
3480{
3481 struct sdhci_host *host = dev_get_drvdata(dev);
3482 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
3483 struct sdhci_msm_host *msm_host = pltfm_host->priv;
Konstantin Dorfmanddab0cc2015-02-25 16:23:50 +02003484 int ret = 0;
3485 ktime_t start = ktime_get();
Konstantin Dorfman98377d32015-02-25 10:09:41 +02003486
3487 if (gpio_is_valid(msm_host->pdata->status_gpio) &&
3488 (msm_host->mmc->slot.cd_irq >= 0))
3489 disable_irq(msm_host->mmc->slot.cd_irq);
3490
3491 if (pm_runtime_suspended(dev)) {
3492 pr_debug("%s: %s: already runtime suspended\n",
3493 mmc_hostname(host->mmc), __func__);
3494 goto out;
3495 }
Konstantin Dorfmanddab0cc2015-02-25 16:23:50 +02003496 ret = sdhci_msm_runtime_suspend(dev);
Konstantin Dorfman98377d32015-02-25 10:09:41 +02003497out:
Konstantin Dorfmanddab0cc2015-02-25 16:23:50 +02003498 trace_sdhci_msm_suspend(mmc_hostname(host->mmc), ret,
3499 ktime_to_us(ktime_sub(ktime_get(), start)));
3500 return ret;
Konstantin Dorfman98377d32015-02-25 10:09:41 +02003501}
3502
3503static int sdhci_msm_resume(struct device *dev)
3504{
3505 struct sdhci_host *host = dev_get_drvdata(dev);
3506 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
3507 struct sdhci_msm_host *msm_host = pltfm_host->priv;
3508 int ret = 0;
Konstantin Dorfmanddab0cc2015-02-25 16:23:50 +02003509 ktime_t start = ktime_get();
Konstantin Dorfman98377d32015-02-25 10:09:41 +02003510
3511 if (gpio_is_valid(msm_host->pdata->status_gpio) &&
3512 (msm_host->mmc->slot.cd_irq >= 0))
3513 enable_irq(msm_host->mmc->slot.cd_irq);
3514
3515 if (pm_runtime_suspended(dev)) {
3516 pr_debug("%s: %s: runtime suspended, defer system resume\n",
3517 mmc_hostname(host->mmc), __func__);
3518 goto out;
3519 }
3520
Konstantin Dorfmanddab0cc2015-02-25 16:23:50 +02003521 ret = sdhci_msm_runtime_resume(dev);
Konstantin Dorfman98377d32015-02-25 10:09:41 +02003522out:
Konstantin Dorfmanddab0cc2015-02-25 16:23:50 +02003523 trace_sdhci_msm_resume(mmc_hostname(host->mmc), ret,
3524 ktime_to_us(ktime_sub(ktime_get(), start)));
Konstantin Dorfman98377d32015-02-25 10:09:41 +02003525 return ret;
3526}
3527
3528static const struct dev_pm_ops sdhci_msm_pmops = {
3529 SET_SYSTEM_SLEEP_PM_OPS(sdhci_msm_suspend, sdhci_msm_resume)
3530 SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend, sdhci_msm_runtime_resume,
3531 NULL)
3532};
3533
3534#define SDHCI_MSM_PMOPS (&sdhci_msm_pmops)
3535
3536#else
3537#define SDHCI_MSM_PMOPS NULL
3538#endif
Asutosh Das0ef24812012-12-18 16:14:02 +05303539static const struct of_device_id sdhci_msm_dt_match[] = {
3540 {.compatible = "qcom,sdhci-msm"},
Venkat Gopalakrishnan272ba402015-06-25 12:00:02 -07003541 {},
Asutosh Das0ef24812012-12-18 16:14:02 +05303542};
3543MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
3544
3545static struct platform_driver sdhci_msm_driver = {
3546 .probe = sdhci_msm_probe,
3547 .remove = sdhci_msm_remove,
3548 .driver = {
3549 .name = "sdhci_msm",
3550 .owner = THIS_MODULE,
3551 .of_match_table = sdhci_msm_dt_match,
Konstantin Dorfman98377d32015-02-25 10:09:41 +02003552 .pm = SDHCI_MSM_PMOPS,
Asutosh Das0ef24812012-12-18 16:14:02 +05303553 },
3554};
3555
3556module_platform_driver(sdhci_msm_driver);
3557
3558MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Secure Digital Host Controller Interface driver");
3559MODULE_LICENSE("GPL v2");