blob: 9b234df810d008d6f44f22448fbeee44e86975d1 [file] [log] [blame]
Andrew Mortonc777ac52006-03-25 03:07:36 -08001
Christoph Hellwigd824e662006-04-10 22:54:04 -07002#include <linux/irq.h>
Andrew Mortonc777ac52006-03-25 03:07:36 -08003
4void set_pending_irq(unsigned int irq, cpumask_t mask)
5{
Ingo Molnar34ffdb72006-06-29 02:24:40 -07006 struct irq_desc *desc = irq_desc + irq;
Andrew Mortonc777ac52006-03-25 03:07:36 -08007 unsigned long flags;
8
9 spin_lock_irqsave(&desc->lock, flags);
Eric W. Biedermana24ceab2006-10-04 02:16:27 -070010 desc->status |= IRQ_MOVE_PENDING;
Ingo Molnarcd916d32006-06-29 02:24:42 -070011 irq_desc[irq].pending_mask = mask;
Andrew Mortonc777ac52006-03-25 03:07:36 -080012 spin_unlock_irqrestore(&desc->lock, flags);
13}
14
15void move_native_irq(int irq)
16{
Ingo Molnar34ffdb72006-06-29 02:24:40 -070017 struct irq_desc *desc = irq_desc + irq;
Andrew Mortonc777ac52006-03-25 03:07:36 -080018 cpumask_t tmp;
Andrew Mortonc777ac52006-03-25 03:07:36 -080019
Eric W. Biedermana24ceab2006-10-04 02:16:27 -070020 if (likely(!(desc->status & IRQ_MOVE_PENDING)))
Andrew Mortonc777ac52006-03-25 03:07:36 -080021 return;
22
Bryan Holty501f2492006-03-25 03:07:37 -080023 /*
24 * Paranoia: cpu-local interrupts shouldn't be calling in here anyway.
25 */
26 if (CHECK_IRQ_PER_CPU(desc->status)) {
27 WARN_ON(1);
28 return;
29 }
30
Eric W. Biedermana24ceab2006-10-04 02:16:27 -070031 desc->status &= ~IRQ_MOVE_PENDING;
Andrew Mortonc777ac52006-03-25 03:07:36 -080032
Ingo Molnarcd916d32006-06-29 02:24:42 -070033 if (unlikely(cpus_empty(irq_desc[irq].pending_mask)))
Andrew Mortonc777ac52006-03-25 03:07:36 -080034 return;
35
Ingo Molnard1bef4e2006-06-29 02:24:36 -070036 if (!desc->chip->set_affinity)
Andrew Mortonc777ac52006-03-25 03:07:36 -080037 return;
38
Bryan Holty501f2492006-03-25 03:07:37 -080039 assert_spin_locked(&desc->lock);
40
Ingo Molnarcd916d32006-06-29 02:24:42 -070041 cpus_and(tmp, irq_desc[irq].pending_mask, cpu_online_map);
Andrew Mortonc777ac52006-03-25 03:07:36 -080042
43 /*
44 * If there was a valid mask to work with, please
45 * do the disable, re-program, enable sequence.
46 * This is *not* particularly important for level triggered
47 * but in a edge trigger case, we might be setting rte
48 * when an active trigger is comming in. This could
49 * cause some ioapics to mal-function.
50 * Being paranoid i guess!
51 */
Daniel Walker89d0cf02006-06-23 02:05:29 -070052 if (likely(!cpus_empty(tmp))) {
Bryan Holty501f2492006-03-25 03:07:37 -080053 if (likely(!(desc->status & IRQ_DISABLED)))
Ingo Molnard1bef4e2006-06-29 02:24:36 -070054 desc->chip->disable(irq);
Bryan Holty501f2492006-03-25 03:07:37 -080055
Ingo Molnard1bef4e2006-06-29 02:24:36 -070056 desc->chip->set_affinity(irq,tmp);
Bryan Holty501f2492006-03-25 03:07:37 -080057
58 if (likely(!(desc->status & IRQ_DISABLED)))
Ingo Molnard1bef4e2006-06-29 02:24:36 -070059 desc->chip->enable(irq);
Andrew Mortonc777ac52006-03-25 03:07:36 -080060 }
Ingo Molnarcd916d32006-06-29 02:24:42 -070061 cpus_clear(irq_desc[irq].pending_mask);
Andrew Mortonc777ac52006-03-25 03:07:36 -080062}