tree 97c8d63dd247494999bda213da1b845de853cf69
parent 64ebda3acd6ea592e6f97dcd0682e87aa7cf8d61
parent 9b038bc58ad2658c76fd8b50bb333dfd4454573c
author Olof Johansson <olof@lixom.net> 1445838157 +0900
committer Olof Johansson <olof@lixom.net> 1445838157 +0900
mergetag object 9b038bc58ad2658c76fd8b50bb333dfd4454573c
 type commit
 tag sunxi-clocks-for-4.4
 tagger Maxime Ripard <maxime.ripard@free-electrons.com> 1445457233 +0200
 
 Allwinner clock additions for 4.4
 
   - Support for the Audio PLL and child clocks
   - Support for the A33 AHB gates
   - New clk-multiplier generic driver
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJWJ+3uAAoJEBx+YmzsjxAgx8UP/2QOntzRCUQYZGaI/aG2Pcag
 lWeoWRkHpEdjM288OxOgoqody6UU/5gecI2UgDLtziaXV5DfIFhP0Klq1gIYc7h0
 WDts2IlGht+fIObL87mD0Pm9StFNAtxFe5tKoHpU5oS6NP+lowSWAQlZSgUWdQky
 VEvXDcOtaEQ3UQgcuMsaqfzgRPJC9zz28MDF28EtPhnCeseb/LKdmvaGzxHHehSl
 016mQ4DvNC92PeLXUdy3LLOkcHTfYnH1OUBPrv7u8bFU09zPKSimymDyL87D7FFM
 vPGKtlD/cQb21z2OVK9GKNmd9dQ+8tnBn9Gbdem95LFHlhP/m+SJbW2P64dNVq0A
 QK5Ria2H6ccRMpfjNQ4zCHjIJQ6+z9xRzIlHXeAT7PcBf9XNwn1/N7qSBJTRy+y/
 uq9Wvgfuletk9lIiFstbJWT6Axu+w/QVWJwJSkOa63elkFSyz+9Dk88MDYd156or
 R79fc9EMQFcCg7k5IeiePLV8G1XVHc/3+ZoRON2ZJYk0L3z5uv/klizkCwtWN5cN
 55nzfQ8Mn69yG9vrR7DSbVY4eyXkr345Tqv0OFaDZlrpb9/oHjK6MNDWzmXY2Y+N
 ZcdNXwWu8DOqEf2iPWXETp0R0wV3kuEaKOvkS4KpvK2UjdQUeEvGUbpxm7Omo583
 5RN+z/gjJSZQx9AoGwBJ
 =WtVW
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-clocks-for-4.4' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt

Bringing in the sunxi clock branch since it introduces header file contents
that is needed by the DT branch. This is a stable tag shared with the clk tree.

Allwinner clock additions for 4.4

  - Support for the Audio PLL and child clocks
  - Support for the A33 AHB gates
  - New clk-multiplier generic driver

* tag 'sunxi-clocks-for-4.4' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
  clk: sunxi: mod1 clock support
  clk: sunxi: codec clock support
  clk: sunxi: pll2: Add A13 support
  clk: sunxi: Add a driver for the PLL2
  clk: Add a basic multiplier clock
  clk: sunxi: Add A33 gates support

Signed-off-by: Olof Johansson <olof@lixom.net>