| commit | e5f186c4f9812eccbc291da6dfe8b15da546f961 | [log] [tgz] |
|---|---|---|
| author | Ben Skeggs <bskeggs@redhat.com> | Thu Sep 27 08:55:53 2012 +1000 |
| committer | Ben Skeggs <bskeggs@redhat.com> | Wed Oct 03 13:13:17 2012 +1000 |
| tree | 84e667ebbe00bd91e10cff16defaad95b38d85a9 | |
| parent | 8a57d279d6e1bf19d2d2e54f51d4f40c46c7d1a8 [diff] |
drm/nv44/vm: fix and enable use of "real" pciegart Something seems to be missing in regards to flushing specific ranges of the TLB. For the moment, flushing the entire thing seems to make it work alright. Should give 39-bit DMA addressing on the relevant chipsets. v2: allocate contig 16KiB for dummy pages, reported by mwk on irc Signed-off-by: Ben Skeggs <bskeggs@redhat.com>