| commit | d78d27c0b427079fc7cf083394d0700cc05d354b | [log] [tgz] |
|---|---|---|
| author | Casey Piper <cpiper@codeaurora.org> | Wed Mar 11 18:25:03 2015 -0700 |
| committer | Narendra Muppalla <NarendraM@codeaurora.org> | Wed Jan 18 18:11:44 2017 -0800 |
| tree | 0b34cbe909e153304fb2de6ed17352ac18e1e07c | |
| parent | 0eb0ae0f5dcfc57369239534867edb53925df39e [diff] |
clk: mdss: write lane mode when powering on HDMI PHY To improve the timing margin, lane mode selection needs to be written during the HDMI PHY startup sequence. This prevents a timing failure when VDDCX or VCCA_CORE are applied rather than the nominal value. Change-Id: I2ed54f63903a473eca12fb4d8f3b542585397dae Signed-off-by: Casey Piper <cpiper@codeaurora.org>