Merge "dts: arm: DTSI changes for Camera probe"
diff --git a/Documentation/devicetree/bindings/arm/msm/sdx-ext-ipc.txt b/Documentation/devicetree/bindings/arm/msm/sdx-ext-ipc.txt
new file mode 100644
index 0000000..689c5b6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/sdx-ext-ipc.txt
@@ -0,0 +1,31 @@
+Modem chipset attached to Application processor
+
+Modem chipset can be connected to an external apss processor. The control
+channel between the two chipsets consists of gpios that can relay the
+state of one subsytem to another. Modem can indicate different events
+(bootup/crash etc.) to AP and can get the same information from AP.
+
+Required Properties:
+- compatible: "qcom,sdx-ext-ipc".
+
+Required named gpio properties:
+- qcom,mdm2ap-status-gpio: gpio for modem to indicate the boot status to APQ.
+
+- qcom,ap2mdm-status-gpio: gpio for APQ to indicate the boot status to modem.
+
+
+
+Optional named gpio properties:
+- qcom,mdm2ap-status2-gpio: gpio for modem to indicate to APQ that it is in
+ E911 call or doing firmware upgrade.
+
+- qcom,ap2mdm-status2-gpio: gpio for APQ to indicate graceful shutdown to modem.
+
+Example:
+ sdx_ext_ipc: qcom,sdx_ext_ipc {
+ compatible = "qcom,sdx-ext-ipc";
+ qcom,ap2mdm-status-gpio = <&tlmm 64 0x00>;
+ qcom,ap2mdm-status2-gpio = <&tlmm 65 0x00>;
+ qcom,mdm2ap-status-gpio = <&tlmm 63 0x00>;
+ qcom,mdm2ap-status2-gpio = <&tlmm 66 0x00>;
+ };
diff --git a/Documentation/devicetree/bindings/rtc/abracon,abx80x.txt b/Documentation/devicetree/bindings/rtc/abracon,abx80x.txt
index be78968..18b892d 100644
--- a/Documentation/devicetree/bindings/rtc/abracon,abx80x.txt
+++ b/Documentation/devicetree/bindings/rtc/abracon,abx80x.txt
@@ -27,4 +27,4 @@
- "abracon,tc-diode": should be "standard" (0.6V) or "schottky" (0.3V)
- "abracon,tc-resistor": should be <0>, <3>, <6> or <11>. 0 disables the output
- resistor, the other values are in ohm.
+ resistor, the other values are in kOhm.
diff --git a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
index b23d058..534ef89 100644
--- a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
+++ b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
@@ -674,6 +674,9 @@
msm_audio_apr_dummy {
compatible = "qcom,msm-audio-apr-dummy";
};
+ q6core {
+ compatible = "qcom,q6core-audio";
+ };
qcom,subsys-name = "apr_adsp";
};
@@ -2590,6 +2593,7 @@
"msm-dai-q6-dev.240", "msm-dai-q6-dev.32771",
"msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773",
"msm-dai-q6-auxpcm.2", "msm-dai-q6-dev.32774";
+ qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>;
};
* SDX ASoC Auto Machine driver
diff --git a/Documentation/devicetree/bindings/sound/tfa9897.txt b/Documentation/devicetree/bindings/sound/tfa9897.txt
new file mode 100644
index 0000000..6e5fedb
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/tfa9897.txt
@@ -0,0 +1,24 @@
+TFA9897 SmartpA
+
+Required properties:
+
+ - compatible : "nxp,tfa98xx"
+
+ - reg : I2C address of the device
+
+ - dvdd-supply : Power supply for PA's dvdd
+
+ - dvdd-voltage : Minimum and maximum voltage in uV to set for power supply
+
+ - dvdd-current : dvdd's max current in uA
+
+Examples:
+
+ i2c_smartpa@34 {
+ compatible = "nxp,tfa98xx";
+ reg = <0x34>;
+ reset-gpio = <&tlmm 68 0>;
+ dvdd-supply = <&pm660_l9>;
+ dvdd-voltage = <1800000 1800000>;
+ dvdd-current = <15000>;
+ };
diff --git a/LICENSE.txt b/LICENSE.txt
deleted file mode 100644
index 7a8348b..0000000
--- a/LICENSE.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-
-Copyright (C) 2018 NXP Semiconductors, All Rights Reserved.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License version 2 as
-published by the Free Software Foundation.
diff --git a/Makefile b/Makefile
index 3cad17b..ca11ec4 100644
--- a/Makefile
+++ b/Makefile
@@ -1,6 +1,6 @@
VERSION = 4
PATCHLEVEL = 9
-SUBLEVEL = 206
+SUBLEVEL = 208
EXTRAVERSION =
NAME = Roaring Lionus
@@ -1650,9 +1650,6 @@
# We are always building modules
KBUILD_MODULES := 1
-PHONY += crmodverdir
-crmodverdir:
- $(cmd_crmodverdir)
PHONY += $(objtree)/Module.symvers
$(objtree)/Module.symvers:
@@ -1664,7 +1661,7 @@
module-dirs := $(addprefix _module_,$(KBUILD_EXTMOD))
PHONY += $(module-dirs) modules
-$(module-dirs): crmodverdir $(objtree)/Module.symvers
+$(module-dirs): prepare $(objtree)/Module.symvers
$(Q)$(MAKE) $(build)=$(patsubst _module_%,%,$@)
modules: $(module-dirs)
@@ -1705,7 +1702,8 @@
# Dummies...
PHONY += prepare scripts
-prepare: ;
+prepare:
+ $(cmd_crmodverdir)
scripts: ;
endif # KBUILD_EXTMOD
@@ -1831,17 +1829,14 @@
# Modules
/: prepare scripts FORCE
- $(cmd_crmodverdir)
$(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \
$(build)=$(build-dir)
# Make sure the latest headers are built for Documentation
Documentation/ samples/: headers_install
%/: prepare scripts FORCE
- $(cmd_crmodverdir)
$(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \
$(build)=$(build-dir)
%.ko: prepare scripts FORCE
- $(cmd_crmodverdir)
$(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \
$(build)=$(build-dir) $(@:.ko=.o)
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 5499f95..cb8b76c 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -1002,14 +1002,21 @@
Say Y here if you want kernel low-level debugging support
on SOCFPGA(Cyclone 5 and Arria 5) based platforms.
- config DEBUG_SOCFPGA_UART1
+ config DEBUG_SOCFPGA_ARRIA10_UART1
depends on ARCH_SOCFPGA
- bool "Use SOCFPGA UART1 for low-level debug"
+ bool "Use SOCFPGA Arria10 UART1 for low-level debug"
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
on SOCFPGA(Arria 10) based platforms.
+ config DEBUG_SOCFPGA_CYCLONE5_UART1
+ depends on ARCH_SOCFPGA
+ bool "Use SOCFPGA Cyclone 5 UART1 for low-level debug"
+ select DEBUG_UART_8250
+ help
+ Say Y here if you want kernel low-level debugging support
+ on SOCFPGA(Cyclone 5 and Arria 5) based platforms.
config DEBUG_SUN9I_UART0
bool "Kernel low-level debugging messages via sun9i UART0"
@@ -1549,7 +1556,8 @@
default 0xfe800000 if ARCH_IOP32X
default 0xff690000 if DEBUG_RK32_UART2
default 0xffc02000 if DEBUG_SOCFPGA_UART0
- default 0xffc02100 if DEBUG_SOCFPGA_UART1
+ default 0xffc02100 if DEBUG_SOCFPGA_ARRIA10_UART1
+ default 0xffc03000 if DEBUG_SOCFPGA_CYCLONE5_UART1
default 0xffd82340 if ARCH_IOP13XX
default 0xffe40000 if DEBUG_RCAR_GEN1_SCIF0
default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2
@@ -1639,7 +1647,8 @@
default 0xfeb30c00 if DEBUG_KEYSTONE_UART0
default 0xfeb31000 if DEBUG_KEYSTONE_UART1
default 0xfec02000 if DEBUG_SOCFPGA_UART0
- default 0xfec02100 if DEBUG_SOCFPGA_UART1
+ default 0xfec02100 if DEBUG_SOCFPGA_ARRIA10_UART1
+ default 0xfec03000 if DEBUG_SOCFPGA_CYCLONE5_UART1
default 0xfec12000 if (DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE) && ARCH_MVEBU
default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE
default 0xfec10000 if DEBUG_SIRFATLAS7_UART0
@@ -1687,9 +1696,9 @@
depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
depends on DEBUG_UART_8250_SHIFT >= 2
default y if DEBUG_PICOXCELL_UART || \
- DEBUG_SOCFPGA_UART0 || DEBUG_SOCFPGA_UART1 || \
- DEBUG_KEYSTONE_UART0 || DEBUG_KEYSTONE_UART1 || \
- DEBUG_ALPINE_UART0 || \
+ DEBUG_SOCFPGA_UART0 || DEBUG_SOCFPGA_ARRIA10_UART1 || \
+ DEBUG_SOCFPGA_CYCLONE5_UART1 || DEBUG_KEYSTONE_UART0 || \
+ DEBUG_KEYSTONE_UART1 || DEBUG_ALPINE_UART0 || \
DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
DEBUG_DAVINCI_DA8XX_UART2 || \
DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2
diff --git a/arch/arm/boot/compressed/libfdt_env.h b/arch/arm/boot/compressed/libfdt_env.h
index 005bf4f..f3ddd4f 100644
--- a/arch/arm/boot/compressed/libfdt_env.h
+++ b/arch/arm/boot/compressed/libfdt_env.h
@@ -1,11 +1,13 @@
#ifndef _ARM_LIBFDT_ENV_H
#define _ARM_LIBFDT_ENV_H
+#include <linux/limits.h>
#include <linux/types.h>
#include <linux/string.h>
#include <asm/byteorder.h>
-#define INT_MAX ((int)(~0U>>1))
+#define INT32_MAX S32_MAX
+#define UINT32_MAX U32_MAX
typedef __be16 fdt16_t;
typedef __be32 fdt32_t;
diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts
index c1fd561..939c108 100644
--- a/arch/arm/boot/dts/arm-realview-pb1176.dts
+++ b/arch/arm/boot/dts/arm-realview-pb1176.dts
@@ -45,7 +45,7 @@
};
/* The voltage to the MMC card is hardwired at 3.3V */
- vmmc: fixedregulator@0 {
+ vmmc: regulator-vmmc {
compatible = "regulator-fixed";
regulator-name = "vmmc";
regulator-min-microvolt = <3300000>;
@@ -53,7 +53,7 @@
regulator-boot-on;
};
- veth: fixedregulator@0 {
+ veth: regulator-veth {
compatible = "regulator-fixed";
regulator-name = "veth";
regulator-min-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts
index e306f1c..95037c4 100644
--- a/arch/arm/boot/dts/arm-realview-pb11mp.dts
+++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts
@@ -145,7 +145,7 @@
};
/* The voltage to the MMC card is hardwired at 3.3V */
- vmmc: fixedregulator@0 {
+ vmmc: regulator-vmmc {
compatible = "regulator-fixed";
regulator-name = "vmmc";
regulator-min-microvolt = <3300000>;
@@ -153,7 +153,7 @@
regulator-boot-on;
};
- veth: fixedregulator@0 {
+ veth: regulator-veth {
compatible = "regulator-fixed";
regulator-name = "veth";
regulator-min-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi
index 2bf3958..0682932 100644
--- a/arch/arm/boot/dts/arm-realview-pbx.dtsi
+++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi
@@ -43,7 +43,7 @@
};
/* The voltage to the MMC card is hardwired at 3.3V */
- vmmc: fixedregulator@0 {
+ vmmc: regulator-vmmc {
compatible = "regulator-fixed";
regulator-name = "vmmc";
regulator-min-microvolt = <3300000>;
@@ -51,7 +51,7 @@
regulator-boot-on;
};
- veth: fixedregulator@0 {
+ veth: regulator-veth {
compatible = "regulator-fixed";
regulator-name = "veth";
regulator-min-microvolt = <3300000>;
@@ -539,4 +539,3 @@
};
};
};
-
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 51dbd8c..99b3d23 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -345,7 +345,7 @@
};
hsotg: hsotg@12480000 {
- compatible = "snps,dwc2";
+ compatible = "samsung,s3c6400-hsotg", "snps,dwc2";
reg = <0x12480000 0x20000>;
interrupts = <0 141 0>;
clocks = <&cmu CLK_USBOTG>;
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
index 47e5b63..e95deed 100644
--- a/arch/arm/boot/dts/mmp2.dtsi
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -180,7 +180,7 @@
clocks = <&soc_clocks MMP2_CLK_GPIO>;
resets = <&soc_clocks MMP2_CLK_GPIO>;
interrupt-controller;
- #interrupt-cells = <1>;
+ #interrupt-cells = <2>;
ranges;
gcb0: gpio@d4019000 {
diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi
index 53e007a..964240a 100644
--- a/arch/arm/boot/dts/omap3-pandora-common.dtsi
+++ b/arch/arm/boot/dts/omap3-pandora-common.dtsi
@@ -221,6 +221,17 @@
gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* GPIO_164 */
};
+ /* wl1251 wifi+bt module */
+ wlan_en: fixed-regulator-wg7210_en {
+ compatible = "regulator-fixed";
+ regulator-name = "vwlan";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ startup-delay-us = <50000>;
+ enable-active-high;
+ gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+ };
+
/* wg7210 (wifi+bt module) 32k clock buffer */
wg7210_32k: fixed-regulator-wg7210_32k {
compatible = "regulator-fixed";
@@ -514,9 +525,30 @@
/*wp-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;*/ /* GPIO_127 */
};
-/* mmc3 is probed using pdata-quirks to pass wl1251 card data */
&mmc3 {
- status = "disabled";
+ vmmc-supply = <&wlan_en>;
+
+ bus-width = <4>;
+ non-removable;
+ ti,non-removable;
+ cap-power-off-card;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wlan: wifi@1 {
+ compatible = "ti,wl1251";
+
+ reg = <1>;
+
+ interrupt-parent = <&gpio1>;
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_21 */
+
+ ti,wl1251-has-eeprom;
+ };
};
/* bluetooth*/
diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi
index dc80886b..e3dfba8 100644
--- a/arch/arm/boot/dts/omap3-tao3530.dtsi
+++ b/arch/arm/boot/dts/omap3-tao3530.dtsi
@@ -225,7 +225,7 @@
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&vmmc1>;
vmmc_aux-supply = <&vsim>;
- cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>;
+ cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
bus-width = <8>;
};
diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi
index 0e1320a..d629948 100644
--- a/arch/arm/boot/dts/pxa27x.dtsi
+++ b/arch/arm/boot/dts/pxa27x.dtsi
@@ -34,7 +34,7 @@
clocks = <&clks CLK_NONE>;
};
- pxa27x_ohci: usb@4c000000 {
+ usb0: usb@4c000000 {
compatible = "marvell,pxa-ohci";
reg = <0x4c000000 0x10000>;
interrupts = <3>;
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
index 3ff077c..5a6f4ed 100644
--- a/arch/arm/boot/dts/pxa2xx.dtsi
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -117,13 +117,6 @@
status = "disabled";
};
- usb0: ohci@4c000000 {
- compatible = "marvell,pxa-ohci";
- reg = <0x4c000000 0x10000>;
- interrupts = <3>;
- status = "disabled";
- };
-
mmc0: mmc@41100000 {
compatible = "marvell,pxa-mmc";
reg = <0x41100000 0x1000>;
diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi
index 9d6f3aa..4aee150 100644
--- a/arch/arm/boot/dts/pxa3xx.dtsi
+++ b/arch/arm/boot/dts/pxa3xx.dtsi
@@ -187,7 +187,7 @@
status = "disabled";
};
- pxa3xx_ohci: usb@4c000000 {
+ usb0: usb@4c000000 {
compatible = "marvell,pxa-ohci";
reg = <0x4c000000 0x10000>;
interrupts = <3>;
diff --git a/arch/arm/boot/dts/qcom/sdx-audio-lpass.dtsi b/arch/arm/boot/dts/qcom/sdx-audio-lpass.dtsi
index 8e358b6..a150e89 100644
--- a/arch/arm/boot/dts/qcom/sdx-audio-lpass.dtsi
+++ b/arch/arm/boot/dts/qcom/sdx-audio-lpass.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -72,6 +72,13 @@
audio_apr: qcom,msm-audio-apr {
compatible = "qcom,msm-audio-apr";
qcom,subsys-name = "apr_modem";
+ msm_audio_apr_dummy {
+ compatible = "qcom,msm-audio-apr-dummy";
+ };
+ };
+
+ q6core: qcom,q6core-audio {
+ compatible = "qcom,q6core-audio";
};
host_pcm: qcom,msm-voice-host-pcm {
diff --git a/arch/arm/boot/dts/qcom/sdxpoorwills-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/sdxpoorwills-audio-overlay.dtsi
index e51d54b..a140f1e 100644
--- a/arch/arm/boot/dts/qcom/sdxpoorwills-audio-overlay.dtsi
+++ b/arch/arm/boot/dts/qcom/sdxpoorwills-audio-overlay.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017, 2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -53,6 +53,8 @@
<&wsa881x_0213>, <&wsa881x_0214>;
qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",
"SpkrLeft", "SpkrRight";
+ qcom,msm_audio_ssr_devs = <&audio_apr>, <&wcd934x_cdc>,
+ <&q6core>;
};
&soc {
diff --git a/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi b/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi
index 7571661..e9c35d3 100644
--- a/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi
+++ b/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi
@@ -1,4 +1,4 @@
-/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -836,7 +836,7 @@
qcom,smem-id = <421>;
qcom,proxy-timeout-ms = <10000>;
qcom,sysmon-id = <0>;
- qcom,ssctl-instance-id = <0x12>;
+ qcom,ssctl-instance-id = <0x22>;
qcom,firmware-name = "modem";
memory-region = <&mss_mem>;
status = "ok";
@@ -846,6 +846,7 @@
qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>;
+ qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>;
/* GPIO output to mss */
qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
index bb1f01e..c1c5768 100644
--- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
@@ -63,7 +63,7 @@
vcc_flash: flash-regulator {
compatible = "regulator-fixed";
- regulator-name = "vcc_sys";
+ regulator-name = "vcc_flash";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
startup-delay-us = <150>;
diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts
index f4afda3..de04d87 100644
--- a/arch/arm/boot/dts/s3c6410-mini6410.dts
+++ b/arch/arm/boot/dts/s3c6410-mini6410.dts
@@ -167,6 +167,10 @@
};
};
+&clocks {
+ clocks = <&fin_pll>;
+};
+
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
diff --git a/arch/arm/boot/dts/s3c6410-smdk6410.dts b/arch/arm/boot/dts/s3c6410-smdk6410.dts
index ecf35ec..7ade1a0 100644
--- a/arch/arm/boot/dts/s3c6410-smdk6410.dts
+++ b/arch/arm/boot/dts/s3c6410-smdk6410.dts
@@ -71,6 +71,10 @@
};
};
+&clocks {
+ clocks = <&fin_pll>;
+};
+
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index ce19604..3bfa797 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -174,7 +174,7 @@
};
pmu {
- compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
+ compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 94cf5a1..db5d305 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -172,7 +172,7 @@
};
pmu {
- compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
+ compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
};
diff --git a/arch/arm/configs/msm8909-perf_defconfig b/arch/arm/configs/msm8909-perf_defconfig
index 9eecf62..23149f0 100755
--- a/arch/arm/configs/msm8909-perf_defconfig
+++ b/arch/arm/configs/msm8909-perf_defconfig
@@ -485,7 +485,6 @@
CONFIG_SECURITY_SELINUX=y
CONFIG_SECURITY_SMACK=y
CONFIG_SECURITY_APPARMOR=y
-CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_CRYPTO_XCBC=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_MD4=y
diff --git a/arch/arm/configs/msm8909_defconfig b/arch/arm/configs/msm8909_defconfig
index 90ed132..9ce2354 100644
--- a/arch/arm/configs/msm8909_defconfig
+++ b/arch/arm/configs/msm8909_defconfig
@@ -593,7 +593,6 @@
CONFIG_SECURITY_SELINUX=y
CONFIG_SECURITY_SMACK=y
CONFIG_SECURITY_APPARMOR=y
-CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_CRYPTO_XCBC=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_MD4=y
diff --git a/arch/arm/configs/sa415m-perf_defconfig b/arch/arm/configs/sa415m-perf_defconfig
index ce8c8b0..ab40fe1 100644
--- a/arch/arm/configs/sa415m-perf_defconfig
+++ b/arch/arm/configs/sa415m-perf_defconfig
@@ -369,6 +369,9 @@
CONFIG_IOMMU_DEBUG_TRACKING=y
CONFIG_IOMMU_TESTS=y
CONFIG_QCOM_SCM=y
+CONFIG_SETUP_SSR_NOTIF_TIMEOUTS=y
+CONFIG_SSR_SYSMON_NOTIF_TIMEOUT=20000
+CONFIG_SSR_SUBSYS_NOTIF_TIMEOUT=20000
CONFIG_MSM_BOOT_STATS=y
CONFIG_MSM_BOOT_TIME_MARKER=y
CONFIG_QCOM_WATCHDOG_V2=y
@@ -389,6 +392,7 @@
CONFIG_MSM_GLINK_PKT=y
CONFIG_MSM_SUBSYSTEM_RESTART=y
CONFIG_MSM_PIL=y
+CONFIG_MSM_SYSMON_GLINK_COMM=y
CONFIG_MSM_PIL_SSR_GENERIC=y
CONFIG_QCOM_COMMAND_DB=y
CONFIG_QCOM_SMCINVOKE=y
diff --git a/arch/arm/configs/sa415m_defconfig b/arch/arm/configs/sa415m_defconfig
index accaa86..f6be866 100644
--- a/arch/arm/configs/sa415m_defconfig
+++ b/arch/arm/configs/sa415m_defconfig
@@ -386,6 +386,9 @@
CONFIG_IOMMU_DEBUG_TRACKING=y
CONFIG_IOMMU_TESTS=y
CONFIG_QCOM_SCM=y
+CONFIG_SETUP_SSR_NOTIF_TIMEOUTS=y
+CONFIG_SSR_SYSMON_NOTIF_TIMEOUT=20000
+CONFIG_SSR_SUBSYS_NOTIF_TIMEOUT=20000
CONFIG_MSM_BOOT_STATS=y
CONFIG_MSM_BOOT_TIME_MARKER=y
CONFIG_QCOM_WATCHDOG_V2=y
@@ -406,6 +409,7 @@
CONFIG_MSM_GLINK_PKT=y
CONFIG_MSM_SUBSYSTEM_RESTART=y
CONFIG_MSM_PIL=y
+CONFIG_MSM_SYSMON_GLINK_COMM=y
CONFIG_MSM_PIL_SSR_GENERIC=y
CONFIG_QCOM_COMMAND_DB=y
CONFIG_QCOM_SMCINVOKE=y
diff --git a/arch/arm/configs/sdm429-bg-perf_defconfig b/arch/arm/configs/sdm429-bg-perf_defconfig
index 957a90f..3b6ff05 100644
--- a/arch/arm/configs/sdm429-bg-perf_defconfig
+++ b/arch/arm/configs/sdm429-bg-perf_defconfig
@@ -35,7 +35,6 @@
# CONFIG_RD_XZ is not set
# CONFIG_RD_LZO is not set
# CONFIG_RD_LZ4 is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_KALLSYMS_ALL=y
CONFIG_BPF_SYSCALL=y
# CONFIG_MEMBARRIER is not set
@@ -58,6 +57,7 @@
CONFIG_ARCH_MSM8937=y
CONFIG_ARCH_SDM429=y
# CONFIG_VDSO is not set
+# CONFIG_DEBUG_RODATA is not set
CONFIG_SMP=y
CONFIG_SCHED_MC=y
CONFIG_ARM_PSCI=y
@@ -208,6 +208,7 @@
CONFIG_BT=y
# CONFIG_BT_BREDR is not set
# CONFIG_BT_LE is not set
+# CONFIG_BT_DEBUGFS is not set
CONFIG_MSM_BT_POWER=y
CONFIG_CFG80211=y
CONFIG_CFG80211_INTERNAL_REGDB=y
@@ -351,9 +352,35 @@
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_MSM_CAMERA=y
+CONFIG_MSM_CAMERA_DEBUG=y
+CONFIG_MSMB_CAMERA=y
+CONFIG_MSMB_CAMERA_DEBUG=y
+CONFIG_MSM_CAMERA_SENSOR=y
+CONFIG_MSM_CPP=y
+CONFIG_MSM_CCI=y
+CONFIG_MSM_CSI20_HEADER=y
+CONFIG_MSM_CSI22_HEADER=y
+CONFIG_MSM_CSI30_HEADER=y
+CONFIG_MSM_CSI31_HEADER=y
+CONFIG_MSM_CSIPHY=y
+CONFIG_MSM_CSID=y
+CONFIG_MSM_EEPROM=y
+CONFIG_MSM_ISPIF_V2=y
+CONFIG_IMX134=y
+CONFIG_IMX132=y
+CONFIG_OV9724=y
+CONFIG_OV5648=y
+CONFIG_GC0339=y
+CONFIG_OV8825=y
+CONFIG_OV8865=y
+CONFIG_s5k4e1=y
+CONFIG_OV12830=y
+CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y
+CONFIG_MSMB_JPEG=y
+CONFIG_MSM_FD=y
CONFIG_MSM_VIDC_3X_V4L2=y
CONFIG_MSM_VIDC_3X_GOVERNORS=y
-CONFIG_ADSP_SHMEM=y
CONFIG_QCOM_KGSL=y
CONFIG_FB=y
CONFIG_FB_VIRTUAL=y
@@ -370,6 +397,7 @@
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_USB_AUDIO=y
CONFIG_SND_SOC=y
+CONFIG_SND_SOC_TFA98XX=y
CONFIG_UHID=y
CONFIG_USB=y
CONFIG_DUAL_ROLE_USB_INTF=y
@@ -407,8 +435,6 @@
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_MSM=y
CONFIG_MMC_SDHCI_MSM_ICE=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
CONFIG_LEDS_QPNP_HAPTICS=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
@@ -431,6 +457,7 @@
CONFIG_SPS_SUPPORT_NDP_BAM=y
CONFIG_QPNP_REVID=y
CONFIG_USB_BAM=y
+CONFIG_MSM_EXT_DISPLAY=y
CONFIG_MSM_RMNET_BAM=y
CONFIG_MSM_MDSS_PLL=y
CONFIG_REMOTE_SPINLOCK_MSM=y
@@ -489,6 +516,7 @@
CONFIG_IIO=y
CONFIG_QCOM_RRADC=y
CONFIG_PWM=y
+CONFIG_QCOM_SHOW_RESUME_IRQ=y
CONFIG_QTI_MPM=y
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
@@ -516,7 +544,6 @@
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_INFO=y
CONFIG_FRAME_WARN=2048
-CONFIG_DEBUG_FS=y
CONFIG_PANIC_TIMEOUT=5
# CONFIG_SCHED_DEBUG is not set
CONFIG_PANIC_ON_SCHED_BUG=y
@@ -524,7 +551,12 @@
CONFIG_SCHED_STACK_END_CHECK=y
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_FTRACE is not set
+CONFIG_FUNCTION_TRACER=y
+CONFIG_PREEMPTIRQ_EVENTS=y
+CONFIG_IRQSOFF_TRACER=y
+CONFIG_PREEMPT_TRACER=y
+CONFIG_FTRACE_SYSCALLS=y
+CONFIG_BLK_DEV_IO_TRACE=y
# CONFIG_ARM_UNWIND is not set
CONFIG_PFK=y
CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y
diff --git a/arch/arm/configs/sdm429-bg_defconfig b/arch/arm/configs/sdm429-bg_defconfig
index 3a0ee72..c76c09b 100644
--- a/arch/arm/configs/sdm429-bg_defconfig
+++ b/arch/arm/configs/sdm429-bg_defconfig
@@ -35,7 +35,6 @@
# CONFIG_RD_XZ is not set
# CONFIG_RD_LZO is not set
# CONFIG_RD_LZ4 is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_KALLSYMS_ALL=y
CONFIG_BPF_SYSCALL=y
# CONFIG_MEMBARRIER is not set
@@ -360,9 +359,35 @@
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_MSM_CAMERA=y
+CONFIG_MSM_CAMERA_DEBUG=y
+CONFIG_MSMB_CAMERA=y
+CONFIG_MSMB_CAMERA_DEBUG=y
+CONFIG_MSM_CAMERA_SENSOR=y
+CONFIG_MSM_CPP=y
+CONFIG_MSM_CCI=y
+CONFIG_MSM_CSI20_HEADER=y
+CONFIG_MSM_CSI22_HEADER=y
+CONFIG_MSM_CSI30_HEADER=y
+CONFIG_MSM_CSI31_HEADER=y
+CONFIG_MSM_CSIPHY=y
+CONFIG_MSM_CSID=y
+CONFIG_MSM_EEPROM=y
+CONFIG_MSM_ISPIF_V2=y
+CONFIG_IMX134=y
+CONFIG_IMX132=y
+CONFIG_OV9724=y
+CONFIG_OV5648=y
+CONFIG_GC0339=y
+CONFIG_OV8825=y
+CONFIG_OV8865=y
+CONFIG_s5k4e1=y
+CONFIG_OV12830=y
+CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y
+CONFIG_MSMB_JPEG=y
+CONFIG_MSM_FD=y
CONFIG_MSM_VIDC_3X_V4L2=y
CONFIG_MSM_VIDC_3X_GOVERNORS=y
-CONFIG_ADSP_SHMEM=y
CONFIG_QCOM_KGSL=y
CONFIG_FB=y
CONFIG_FB_VIRTUAL=y
@@ -379,6 +404,7 @@
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_USB_AUDIO=y
CONFIG_SND_SOC=y
+CONFIG_SND_SOC_TFA98XX=y
CONFIG_UHID=y
CONFIG_USB=y
CONFIG_DUAL_ROLE_USB_INTF=y
@@ -417,8 +443,6 @@
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_MSM=y
CONFIG_MMC_SDHCI_MSM_ICE=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
CONFIG_LEDS_QPNP_HAPTICS=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
@@ -441,6 +465,7 @@
CONFIG_SPS_SUPPORT_NDP_BAM=y
CONFIG_QPNP_REVID=y
CONFIG_USB_BAM=y
+CONFIG_MSM_EXT_DISPLAY=y
CONFIG_MSM_RMNET_BAM=y
CONFIG_MSM_MDSS_PLL=y
CONFIG_REMOTE_SPINLOCK_MSM=y
diff --git a/arch/arm/configs/vendor/sa415m-perf_defconfig b/arch/arm/configs/vendor/sa415m-perf_defconfig
new file mode 120000
index 0000000..7ecd325
--- /dev/null
+++ b/arch/arm/configs/vendor/sa415m-perf_defconfig
@@ -0,0 +1 @@
+../sa415m-perf_defconfig
\ No newline at end of file
diff --git a/arch/arm/configs/vendor/sa415m_defconfig b/arch/arm/configs/vendor/sa415m_defconfig
new file mode 120000
index 0000000..f2a512d
--- /dev/null
+++ b/arch/arm/configs/vendor/sa415m_defconfig
@@ -0,0 +1 @@
+../sa415m_defconfig
\ No newline at end of file
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 0f6c6b8..e05c31a 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -379,6 +379,13 @@ do { \
#define __get_user_asm_byte(x, addr, err) \
__get_user_asm(x, addr, err, ldrb)
+#if __LINUX_ARM_ARCH__ >= 6
+
+#define __get_user_asm_half(x, addr, err) \
+ __get_user_asm(x, addr, err, ldrh)
+
+#else
+
#ifndef __ARMEB__
#define __get_user_asm_half(x, __gu_addr, err) \
({ \
@@ -397,6 +404,8 @@ do { \
})
#endif
+#endif /* __LINUX_ARM_ARCH__ >= 6 */
+
#define __get_user_asm_word(x, addr, err) \
__get_user_asm(x, addr, err, ldr)
#endif
@@ -472,6 +481,13 @@ do { \
#define __put_user_asm_byte(x, __pu_addr, err) \
__put_user_asm(x, __pu_addr, err, strb)
+#if __LINUX_ARM_ARCH__ >= 6
+
+#define __put_user_asm_half(x, __pu_addr, err) \
+ __put_user_asm(x, __pu_addr, err, strh)
+
+#else
+
#ifndef __ARMEB__
#define __put_user_asm_half(x, __pu_addr, err) \
({ \
@@ -488,6 +504,8 @@ do { \
})
#endif
+#endif /* __LINUX_ARM_ARCH__ >= 6 */
+
#define __put_user_asm_word(x, __pu_addr, err) \
__put_user_asm(x, __pu_addr, err, str)
diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S
index 746e780..b2e4bc3a 100644
--- a/arch/arm/lib/getuser.S
+++ b/arch/arm/lib/getuser.S
@@ -42,6 +42,12 @@
ENTRY(__get_user_2)
check_uaccess r0, 2, r1, r2, __get_user_bad
+#if __LINUX_ARM_ARCH__ >= 6
+
+2: TUSER(ldrh) r2, [r0]
+
+#else
+
#ifdef CONFIG_CPU_USE_DOMAINS
rb .req ip
2: ldrbt r2, [r0], #1
@@ -56,6 +62,9 @@
#else
orr r2, rb, r2, lsl #8
#endif
+
+#endif /* __LINUX_ARM_ARCH__ >= 6 */
+
mov r0, #0
ret lr
ENDPROC(__get_user_2)
@@ -145,7 +154,9 @@
.pushsection __ex_table, "a"
.long 1b, __get_user_bad
.long 2b, __get_user_bad
+#if __LINUX_ARM_ARCH__ < 6
.long 3b, __get_user_bad
+#endif
.long 4b, __get_user_bad
.long 5b, __get_user_bad8
.long 6b, __get_user_bad8
diff --git a/arch/arm/lib/putuser.S b/arch/arm/lib/putuser.S
index 38d660d..515eeaa 100644
--- a/arch/arm/lib/putuser.S
+++ b/arch/arm/lib/putuser.S
@@ -41,16 +41,13 @@
ENTRY(__put_user_2)
check_uaccess r0, 2, r1, ip, __put_user_bad
- mov ip, r2, lsr #8
-#ifdef CONFIG_THUMB2_KERNEL
-#ifndef __ARMEB__
-2: TUSER(strb) r2, [r0]
-3: TUSER(strb) ip, [r0, #1]
+#if __LINUX_ARM_ARCH__ >= 6
+
+2: TUSER(strh) r2, [r0]
+
#else
-2: TUSER(strb) ip, [r0]
-3: TUSER(strb) r2, [r0, #1]
-#endif
-#else /* !CONFIG_THUMB2_KERNEL */
+
+ mov ip, r2, lsr #8
#ifndef __ARMEB__
2: TUSER(strb) r2, [r0], #1
3: TUSER(strb) ip, [r0]
@@ -58,7 +55,8 @@
2: TUSER(strb) ip, [r0], #1
3: TUSER(strb) r2, [r0]
#endif
-#endif /* CONFIG_THUMB2_KERNEL */
+
+#endif /* __LINUX_ARM_ARCH__ >= 6 */
mov r0, #0
ret lr
ENDPROC(__put_user_2)
@@ -91,7 +89,9 @@
.pushsection __ex_table, "a"
.long 1b, __put_user_bad
.long 2b, __put_user_bad
+#if __LINUX_ARM_ARCH__ < 6
.long 3b, __put_user_bad
+#endif
.long 4b, __put_user_bad
.long 5b, __put_user_bad
.long 6b, __put_user_bad
diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c
index 52de382..7e49dfd 100644
--- a/arch/arm/mach-omap1/id.c
+++ b/arch/arm/mach-omap1/id.c
@@ -200,10 +200,10 @@ void __init omap_check_revision(void)
printk(KERN_INFO "Unknown OMAP cpu type: 0x%02x\n", cpu_type);
}
- printk(KERN_INFO "OMAP%04x", omap_revision >> 16);
+ pr_info("OMAP%04x", omap_revision >> 16);
if ((omap_revision >> 8) & 0xff)
- printk(KERN_INFO "%x", (omap_revision >> 8) & 0xff);
- printk(KERN_INFO " revision %i handled as %02xxx id: %08x%08x\n",
+ pr_cont("%x", (omap_revision >> 8) & 0xff);
+ pr_cont(" revision %i handled as %02xxx id: %08x%08x\n",
die_rev, omap_revision & 0xff, system_serial_low,
system_serial_high);
}
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index cc6d9fa..9d942f0 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -199,8 +199,8 @@ void __init omap2xxx_check_revision(void)
pr_info("%s", soc_name);
if ((omap_rev() >> 8) & 0x0f)
- pr_info("%s", soc_rev);
- pr_info("\n");
+ pr_cont("%s", soc_rev);
+ pr_cont("\n");
}
#define OMAP3_SHOW_FEATURE(feat) \
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 88676fe..c3b3972 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -308,108 +308,15 @@ static void __init omap3_logicpd_torpedo_init(void)
}
/* omap3pandora legacy devices */
-#define PANDORA_WIFI_IRQ_GPIO 21
-#define PANDORA_WIFI_NRESET_GPIO 23
static struct platform_device pandora_backlight = {
.name = "pandora-backlight",
.id = -1,
};
-static struct regulator_consumer_supply pandora_vmmc3_supply[] = {
- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"),
-};
-
-static struct regulator_init_data pandora_vmmc3 = {
- .constraints = {
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(pandora_vmmc3_supply),
- .consumer_supplies = pandora_vmmc3_supply,
-};
-
-static struct fixed_voltage_config pandora_vwlan = {
- .supply_name = "vwlan",
- .microvolts = 1800000, /* 1.8V */
- .gpio = PANDORA_WIFI_NRESET_GPIO,
- .startup_delay = 50000, /* 50ms */
- .enable_high = 1,
- .init_data = &pandora_vmmc3,
-};
-
-static struct platform_device pandora_vwlan_device = {
- .name = "reg-fixed-voltage",
- .id = 1,
- .dev = {
- .platform_data = &pandora_vwlan,
- },
-};
-
-static void pandora_wl1251_init_card(struct mmc_card *card)
-{
- /*
- * We have TI wl1251 attached to MMC3. Pass this information to
- * SDIO core because it can't be probed by normal methods.
- */
- if (card->type == MMC_TYPE_SDIO || card->type == MMC_TYPE_SD_COMBO) {
- card->quirks |= MMC_QUIRK_NONSTD_SDIO;
- card->cccr.wide_bus = 1;
- card->cis.vendor = 0x104c;
- card->cis.device = 0x9066;
- card->cis.blksize = 512;
- card->cis.max_dtr = 24000000;
- card->ocr = 0x80;
- }
-}
-
-static struct omap2_hsmmc_info pandora_mmc3[] = {
- {
- .mmc = 3,
- .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
- .gpio_cd = -EINVAL,
- .gpio_wp = -EINVAL,
- .init_card = pandora_wl1251_init_card,
- },
- {} /* Terminator */
-};
-
-static void __init pandora_wl1251_init(void)
-{
- struct wl1251_platform_data pandora_wl1251_pdata;
- int ret;
-
- memset(&pandora_wl1251_pdata, 0, sizeof(pandora_wl1251_pdata));
-
- pandora_wl1251_pdata.power_gpio = -1;
-
- ret = gpio_request_one(PANDORA_WIFI_IRQ_GPIO, GPIOF_IN, "wl1251 irq");
- if (ret < 0)
- goto fail;
-
- pandora_wl1251_pdata.irq = gpio_to_irq(PANDORA_WIFI_IRQ_GPIO);
- if (pandora_wl1251_pdata.irq < 0)
- goto fail_irq;
-
- pandora_wl1251_pdata.use_eeprom = true;
- ret = wl1251_set_platform_data(&pandora_wl1251_pdata);
- if (ret < 0)
- goto fail_irq;
-
- return;
-
-fail_irq:
- gpio_free(PANDORA_WIFI_IRQ_GPIO);
-fail:
- pr_err("wl1251 board initialisation failed\n");
-}
-
static void __init omap3_pandora_legacy_init(void)
{
platform_device_register(&pandora_backlight);
- platform_device_register(&pandora_vwlan_device);
- omap_hsmmc_init(pandora_mmc3);
- omap_hsmmc_late_init(pandora_mmc3);
- pandora_wl1251_init();
}
#endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index e3070fd..3fe4ae6 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -56,16 +56,16 @@
cmp r6, #TEGRA20
beq 1f @ Yes
/* Clear the flow controller flags for this CPU. */
- cpu_to_csr_reg r1, r0
+ cpu_to_csr_reg r3, r0
mov32 r2, TEGRA_FLOW_CTRL_BASE
- ldr r1, [r2, r1]
+ ldr r1, [r2, r3]
/* Clear event & intr flag */
orr r1, r1, \
#FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
movw r0, #0x3FFD @ enable, cluster_switch, immed, bitmaps
@ & ext flags for CPU power mgnt
bic r1, r1, r0
- str r1, [r2]
+ str r1, [r2, r3]
1:
mov32 r9, 0xc09
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
index e5fc67b..a88afb6 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
@@ -1583,7 +1583,7 @@
regulator-name = "VDD_HDMI_5V0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- gpio = <&exp1 12 GPIO_ACTIVE_LOW>;
+ gpio = <&exp1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_5v0_sys>;
};
diff --git a/arch/arm64/boot/dts/qcom/msm8937-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/msm8937-pinctrl.dtsi
index 6de4900..b2d8749 100644
--- a/arch/arm64/boot/dts/qcom/msm8937-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8937-pinctrl.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2016, 2018-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2016, 2018-2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -350,6 +350,92 @@
};
};
+ spi6 {
+ spi6_default: spi6_default {
+ /* active state */
+ mux {
+ /* MOSI, MISO, CLK */
+ pins = "gpio20", "gpio21", "gpio23";
+ function = "blsp_spi6";
+ };
+
+ config {
+ pins = "gpio20", "gpio21", "gpio23";
+ drive-strength = <12>; /* 12 MA */
+ bias-disable = <0>; /* No PULL */
+ };
+ };
+
+ spi6_sleep: spi6_sleep {
+ /* suspended state */
+ mux {
+ /* MOSI, MISO, CLK */
+ pins = "gpio20", "gpio21", "gpio23";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio20", "gpio21", "gpio23";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-down; /* PULL Down */
+ };
+ };
+
+ spi6_cs0_active: cs0_active {
+ /* CS */
+ mux {
+ pins = "gpio22";
+ function = "blsp_spi6";
+ };
+
+ config {
+ pins = "gpio22";
+ drive-strength = <2>;
+ bias-disable = <0>;
+ };
+ };
+
+ spi6_cs0_sleep: cs0_sleep {
+ /* CS */
+ mux {
+ pins = "gpio22";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio22";
+ drive-strength = <2>;
+ bias-disable = <0>;
+ };
+ };
+ };
+
+ blsp2_uart2_active: blsp2_uart2_active {
+ mux {
+ pins = "gpio20", "gpio21", "gpio22", "gpio23";
+ function = "blsp_uart6";
+ };
+
+ config {
+ pins = "gpio20", "gpio21", "gpio22", "gpio23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ blsp2_uart2_sleep: blsp2_uart2_sleep {
+ mux {
+ pins = "gpio20", "gpio21", "gpio22", "gpio23";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio20", "gpio21", "gpio22", "gpio23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
spi7 {
spi7_default: spi7_default {
mux {
diff --git a/arch/arm64/boot/dts/qcom/msm8937.dtsi b/arch/arm64/boot/dts/qcom/msm8937.dtsi
index e8e7a63..18e75a0 100644
--- a/arch/arm64/boot/dts/qcom/msm8937.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8937.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -143,6 +143,7 @@
i2c2 = &i2c_2;
i2c5 = &i2c_5;
spi3 = &spi_3;
+ spi6 = &spi_6;
i2c3 = &i2c_3;
i2c4 = &i2c_4;
sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
@@ -667,6 +668,68 @@
status = "disabled";
};
+ spi_6: spi@7af6000 { /* BLSP2 QUP1 */
+ compatible = "qcom,spi-qup-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "spi_physical", "spi_bam_physical";
+ reg = <0x7af6000 0x600>,
+ <0x7ac4000 0x1f000>;
+ interrupt-names = "spi_irq", "spi_bam_irq";
+ interrupts = <0 300 0>, <0 239 0>;
+ spi-max-frequency = <19200000>;
+ pinctrl-names = "spi_default", "spi_sleep";
+ pinctrl-0 = <&spi6_default &spi6_cs0_active>;
+ pinctrl-1 = <&spi6_sleep &spi6_cs0_sleep>;
+ clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
+ <&clock_gcc clk_gcc_blsp2_qup1_spi_apps_clk>;
+ clock-names = "iface_clk", "core_clk";
+ qcom,infinite-mode = <0>;
+ qcom,use-bam;
+ qcom,use-pinctrl;
+ qcom,ver-reg-exists;
+ qcom,bam-consumer-pipe-index = <6>;
+ qcom,bam-producer-pipe-index = <7>;
+ qcom,master-id = <84>;
+ status = "disabled";
+ };
+
+ blsp2_uart2: uart@7af0000 { /* BLSP2 UART2 */
+ compatible = "qcom,msm-hsuart-v14";
+ reg = <0x7af0000 0x200>,
+ <0x7ac4000 0x1f000>;
+ reg-names = "core_mem", "bam_mem";
+ interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
+ #address-cells = <0>;
+ interrupt-parent = <&blsp2_uart2>;
+ interrupts = <0 1 2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xffffffff>;
+ interrupt-map = <0 &intc 0 307 0
+ 1 &intc 0 239 0
+ 2 &tlmm 21 0>;
+
+ qcom,inject-rx-on-wakeup;
+ qcom,rx-char-to-inject = <0xfd>;
+
+ qcom,bam-tx-ep-pipe-index = <2>;
+ qcom,bam-rx-ep-pipe-index = <3>;
+ qcom,master-id = <84>;
+ clock-names = "core_clk", "iface_clk";
+ clocks = <&clock_gcc clk_gcc_blsp2_uart2_apps_clk>,
+ <&clock_gcc clk_gcc_blsp2_ahb_clk>;
+ pinctrl-names = "sleep", "default";
+ pinctrl-0 = <&blsp2_uart2_sleep>;
+ pinctrl-1 = <&blsp2_uart2_active>;
+ qcom,msm-bus,name = "blsp2_uart2";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <84 512 0 0>,
+ <84 512 500 800>;
+ status = "disabled";
+ };
+
msm_cpufreq: qcom,msm-cpufreq {
compatible = "qcom,msm-cpufreq";
clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk",
diff --git a/arch/arm64/boot/dts/qcom/sda429-bg-wdp-overlay.dts b/arch/arm64/boot/dts/qcom/sda429-bg-wdp-overlay.dts
index 4058468..c34e945 100644
--- a/arch/arm64/boot/dts/qcom/sda429-bg-wdp-overlay.dts
+++ b/arch/arm64/boot/dts/qcom/sda429-bg-wdp-overlay.dts
@@ -72,6 +72,13 @@
qcom,glinkpkt-dev-name = "glink_pkt_bg_daemon";
};
+ qcom,glinkpkt-bg-daemon-ctrl {
+ qcom,glinkpkt-transport = "bgcom";
+ qcom,glinkpkt-edge = "bg";
+ qcom,glinkpkt-ch-name = "bg-daemon-ctl";
+ qcom,glinkpkt-dev-name = "glink_pkt_bg_daemon_ctrl";
+ };
+
qcom,glinkpkt-bg-display-ctrl {
qcom,glinkpkt-transport = "bgcom";
qcom,glinkpkt-edge = "bg";
diff --git a/arch/arm64/boot/dts/qcom/sda429-bg-wtp-overlay.dts b/arch/arm64/boot/dts/qcom/sda429-bg-wtp-overlay.dts
index 4a3bde0..d179b7b 100644
--- a/arch/arm64/boot/dts/qcom/sda429-bg-wtp-overlay.dts
+++ b/arch/arm64/boot/dts/qcom/sda429-bg-wtp-overlay.dts
@@ -72,6 +72,13 @@
qcom,glinkpkt-dev-name = "glink_pkt_bg_daemon";
};
+ qcom,glinkpkt-bg-daemon-ctrl {
+ qcom,glinkpkt-transport = "bgcom";
+ qcom,glinkpkt-edge = "bg";
+ qcom,glinkpkt-ch-name = "bg-daemon-ctl";
+ qcom,glinkpkt-dev-name = "glink_pkt_bg_daemon_ctrl";
+ };
+
qcom,glinkpkt-bg-display-ctrl {
qcom,glinkpkt-transport = "bgcom";
qcom,glinkpkt-edge = "bg";
diff --git a/arch/arm64/boot/dts/qcom/sdm429-bg-wdp-overlay.dts b/arch/arm64/boot/dts/qcom/sdm429-bg-wdp-overlay.dts
index 752ce07..37ff160 100644
--- a/arch/arm64/boot/dts/qcom/sdm429-bg-wdp-overlay.dts
+++ b/arch/arm64/boot/dts/qcom/sdm429-bg-wdp-overlay.dts
@@ -72,6 +72,13 @@
qcom,glinkpkt-dev-name = "glink_pkt_bg_daemon";
};
+ qcom,glinkpkt-bg-daemon-ctrl {
+ qcom,glinkpkt-transport = "bgcom";
+ qcom,glinkpkt-edge = "bg";
+ qcom,glinkpkt-ch-name = "bg-daemon-ctl";
+ qcom,glinkpkt-dev-name = "glink_pkt_bg_daemon_ctrl";
+ };
+
qcom,glinkpkt-bg-display-ctrl {
qcom,glinkpkt-transport = "bgcom";
qcom,glinkpkt-edge = "bg";
diff --git a/arch/arm64/boot/dts/qcom/sdm429-bg-wtp-overlay.dts b/arch/arm64/boot/dts/qcom/sdm429-bg-wtp-overlay.dts
index 89aba6f..32ae531 100644
--- a/arch/arm64/boot/dts/qcom/sdm429-bg-wtp-overlay.dts
+++ b/arch/arm64/boot/dts/qcom/sdm429-bg-wtp-overlay.dts
@@ -72,6 +72,13 @@
qcom,glinkpkt-dev-name = "glink_pkt_bg_daemon";
};
+ qcom,glinkpkt-bg-daemon-ctrl {
+ qcom,glinkpkt-transport = "bgcom";
+ qcom,glinkpkt-edge = "bg";
+ qcom,glinkpkt-ch-name = "bg-daemon-ctl";
+ qcom,glinkpkt-dev-name = "glink_pkt_bg_daemon_ctrl";
+ };
+
qcom,glinkpkt-bg-display-ctrl {
qcom,glinkpkt-transport = "bgcom";
qcom,glinkpkt-edge = "bg";
diff --git a/arch/arm64/configs/cuttlefish_defconfig b/arch/arm64/configs/cuttlefish_defconfig
index 897c986..3c5ed73 100644
--- a/arch/arm64/configs/cuttlefish_defconfig
+++ b/arch/arm64/configs/cuttlefish_defconfig
@@ -48,7 +48,6 @@
CONFIG_HZ_100=y
# CONFIG_SPARSEMEM_VMEMMAP is not set
CONFIG_KSM=y
-CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_ZSMALLOC=y
CONFIG_SECCOMP=y
CONFIG_PARAVIRT=y
diff --git a/arch/arm64/configs/sdm845-perf_defconfig b/arch/arm64/configs/sdm845-perf_defconfig
index 230ad65..269c0c7 100755
--- a/arch/arm64/configs/sdm845-perf_defconfig
+++ b/arch/arm64/configs/sdm845-perf_defconfig
@@ -301,6 +301,9 @@
CONFIG_WIL6210=m
# CONFIG_WIL6210_TRACING is not set
CONFIG_WCNSS_MEM_PRE_ALLOC=y
+CONFIG_CNSS=y
+CONFIG_CNSS_SDIO=y
+CONFIG_CLD_HL_SDIO_CORE=y
CONFIG_CLD_LL_CORE=y
CONFIG_CNSS_GENL=y
CONFIG_INPUT_EVDEV=y
@@ -575,6 +578,7 @@
CONFIG_QMP_DEBUGFS_CLIENT=y
CONFIG_MEM_SHARE_QMI_SERVICE=y
CONFIG_QSEE_IPC_IRQ_BRIDGE=y
+CONFIG_CNSS_CRYPTO=y
CONFIG_QCOM_BIMC_BWMON=y
CONFIG_ARM_MEMLAT_MON=y
CONFIG_QCOMCCI_HWMON=y
diff --git a/arch/arm64/kernel/psci.c b/arch/arm64/kernel/psci.c
old mode 100644
new mode 100755
index 716a5c2..35e0e64
--- a/arch/arm64/kernel/psci.c
+++ b/arch/arm64/kernel/psci.c
@@ -84,7 +84,8 @@ static void cpu_psci_cpu_die(unsigned int cpu)
static int cpu_psci_cpu_kill(unsigned int cpu)
{
- int err, i;
+ int err;
+ unsigned long start, end;
if (!psci_ops.affinity_info)
return 0;
@@ -94,16 +95,18 @@ static int cpu_psci_cpu_kill(unsigned int cpu)
* while it is dying. So, try again a few times.
*/
- for (i = 0; i < 10; i++) {
+ start = jiffies;
+ end = start + msecs_to_jiffies(100);
+ do {
err = psci_ops.affinity_info(cpu_logical_map(cpu), 0);
if (err == PSCI_0_2_AFFINITY_LEVEL_OFF) {
- pr_debug("CPU%d killed.\n", cpu);
+ pr_debug("CPU%d killed (polled %d ms)\n", cpu,
+ jiffies_to_msecs(jiffies - start));
return 0;
}
- msleep(10);
- pr_debug("Retrying again to check for CPU kill\n");
- }
+ usleep_range(100, 1000);
+ } while (time_before(jiffies, end));
pr_warn("CPU%d may not have shut down cleanly (AFFINITY_INFO reports %d)\n",
cpu, err);
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 92bcde0..f8a529c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -804,6 +804,7 @@
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
+ select ZONE_DMA32 if 64BIT
config SIBYTE_SENTOSA
bool "Sibyte BCM91250E-Sentosa"
diff --git a/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
index 8241fc6..3839feb 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
@@ -266,7 +266,7 @@ int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id)
} else {
union cvmx_pko_mem_debug8 debug8;
debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);
- return debug8.cn58xx.doorbell;
+ return debug8.cn50xx.doorbell;
}
case CVMX_CMD_QUEUE_ZIP:
case CVMX_CMD_QUEUE_DFA:
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index 1ba6bcf..2ecc8d1 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -502,7 +502,7 @@ static void __init octeon_fdt_set_phy(int eth, int phy_addr)
if (phy_addr >= 256 && alt_phy > 0) {
const struct fdt_property *phy_prop;
struct fdt_property *alt_prop;
- u32 phy_handle_name;
+ fdt32_t phy_handle_name;
/* Use the alt phy node instead.*/
phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL);
diff --git a/arch/mips/include/asm/octeon/cvmx-pko.h b/arch/mips/include/asm/octeon/cvmx-pko.h
index 5f47f76..20eb9c4 100644
--- a/arch/mips/include/asm/octeon/cvmx-pko.h
+++ b/arch/mips/include/asm/octeon/cvmx-pko.h
@@ -611,7 +611,7 @@ static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear,
pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);
- status->doorbell = debug8.cn58xx.doorbell;
+ status->doorbell = debug8.cn50xx.doorbell;
}
}
diff --git a/arch/powerpc/boot/libfdt_env.h b/arch/powerpc/boot/libfdt_env.h
index 0b3db63..5f2cb1c 100644
--- a/arch/powerpc/boot/libfdt_env.h
+++ b/arch/powerpc/boot/libfdt_env.h
@@ -5,6 +5,8 @@
#include <string.h>
#define INT_MAX ((int)(~0U>>1))
+#define UINT32_MAX ((u32)~0U)
+#define INT32_MAX ((s32)(UINT32_MAX >> 1))
#include "of.h"
diff --git a/arch/powerpc/include/asm/sfp-machine.h b/arch/powerpc/include/asm/sfp-machine.h
index d89beab..8b957aa 100644
--- a/arch/powerpc/include/asm/sfp-machine.h
+++ b/arch/powerpc/include/asm/sfp-machine.h
@@ -213,30 +213,18 @@
* respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
* (i.e. carry out) is not stored anywhere, and is lost.
*/
-#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
do { \
if (__builtin_constant_p (bh) && (bh) == 0) \
- __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
- : "%r" ((USItype)(ah)), \
- "%r" ((USItype)(al)), \
- "rI" ((USItype)(bl))); \
- else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
- __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
- : "%r" ((USItype)(ah)), \
- "%r" ((USItype)(al)), \
- "rI" ((USItype)(bl))); \
+ __asm__ ("add%I4c %1,%3,%4\n\taddze %0,%2" \
+ : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
+ else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
+ __asm__ ("add%I4c %1,%3,%4\n\taddme %0,%2" \
+ : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
else \
- __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
- : "%r" ((USItype)(ah)), \
- "r" ((USItype)(bh)), \
- "%r" ((USItype)(al)), \
- "rI" ((USItype)(bl))); \
+ __asm__ ("add%I5c %1,%4,%5\n\tadde %0,%2,%3" \
+ : "=r" (sh), "=&r" (sl) \
+ : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
} while (0)
/* sub_ddmmss is used in op-2.h and udivmodti4.c and should be equivalent to
@@ -248,44 +236,24 @@
* and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
* and is lost.
*/
-#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
do { \
if (__builtin_constant_p (ah) && (ah) == 0) \
- __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
- : "r" ((USItype)(bh)), \
- "rI" ((USItype)(al)), \
- "r" ((USItype)(bl))); \
- else if (__builtin_constant_p (ah) && (ah) ==~(USItype) 0) \
- __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
- : "r" ((USItype)(bh)), \
- "rI" ((USItype)(al)), \
- "r" ((USItype)(bl))); \
+ __asm__ ("subf%I3c %1,%4,%3\n\tsubfze %0,%2" \
+ : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
+ else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
+ __asm__ ("subf%I3c %1,%4,%3\n\tsubfme %0,%2" \
+ : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
else if (__builtin_constant_p (bh) && (bh) == 0) \
- __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
- : "r" ((USItype)(ah)), \
- "rI" ((USItype)(al)), \
- "r" ((USItype)(bl))); \
- else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
- __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
- : "r" ((USItype)(ah)), \
- "rI" ((USItype)(al)), \
- "r" ((USItype)(bl))); \
+ __asm__ ("subf%I3c %1,%4,%3\n\taddme %0,%2" \
+ : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
+ else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
+ __asm__ ("subf%I3c %1,%4,%3\n\taddze %0,%2" \
+ : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
else \
- __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
- : "=r" ((USItype)(sh)), \
- "=&r" ((USItype)(sl)) \
- : "r" ((USItype)(ah)), \
- "r" ((USItype)(bh)), \
- "rI" ((USItype)(al)), \
- "r" ((USItype)(bl))); \
+ __asm__ ("subf%I4c %1,%5,%4\n\tsubfe %0,%3,%2" \
+ : "=r" (sh), "=&r" (sl) \
+ : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
} while (0)
/* asm fragments for mul and div */
@@ -294,13 +262,10 @@
* UWtype integers MULTIPLER and MULTIPLICAND, and generates a two UWtype
* word product in HIGH_PROD and LOW_PROD.
*/
-#define umul_ppmm(ph, pl, m0, m1) \
+#define umul_ppmm(ph, pl, m0, m1) \
do { \
USItype __m0 = (m0), __m1 = (m1); \
- __asm__ ("mulhwu %0,%1,%2" \
- : "=r" ((USItype)(ph)) \
- : "%r" (__m0), \
- "r" (__m1)); \
+ __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
(pl) = __m0 * __m1; \
} while (0)
@@ -312,9 +277,10 @@
* significant bit of DENOMINATOR must be 1, then the pre-processor symbol
* UDIV_NEEDS_NORMALIZATION is defined to 1.
*/
-#define udiv_qrnnd(q, r, n1, n0, d) \
+#define udiv_qrnnd(q, r, n1, n0, d) \
do { \
- UWtype __d1, __d0, __q1, __q0, __r1, __r0, __m; \
+ UWtype __d1, __d0, __q1, __q0; \
+ UWtype __r1, __r0, __m; \
__d1 = __ll_highpart (d); \
__d0 = __ll_lowpart (d); \
\
@@ -325,7 +291,7 @@
if (__r1 < __m) \
{ \
__q1--, __r1 += (d); \
- if (__r1 >= (d)) /* we didn't get carry when adding to __r1 */ \
+ if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
if (__r1 < __m) \
__q1--, __r1 += (d); \
} \
diff --git a/arch/powerpc/include/asm/vdso_datapage.h b/arch/powerpc/include/asm/vdso_datapage.h
index 1afe90a..674c033 100644
--- a/arch/powerpc/include/asm/vdso_datapage.h
+++ b/arch/powerpc/include/asm/vdso_datapage.h
@@ -86,6 +86,7 @@ struct vdso_data {
__s32 wtom_clock_nsec;
struct timespec stamp_xtime; /* xtime as at tb_orig_stamp */
__u32 stamp_sec_fraction; /* fractional seconds of stamp_xtime */
+ __u32 hrtimer_res; /* hrtimer resolution */
__u32 syscall_map_64[SYSCALL_MAP_SIZE]; /* map of syscalls */
__u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
};
@@ -107,6 +108,7 @@ struct vdso_data {
__s32 wtom_clock_nsec;
struct timespec stamp_xtime; /* xtime as at tb_orig_stamp */
__u32 stamp_sec_fraction; /* fractional seconds of stamp_xtime */
+ __u32 hrtimer_res; /* hrtimer resolution */
__u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
__u32 dcache_block_size; /* L1 d-cache block size */
__u32 icache_block_size; /* L1 i-cache block size */
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 14fbbd9..dfcf28b 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -383,6 +383,7 @@ int main(void)
DEFINE(WTOM_CLOCK_NSEC, offsetof(struct vdso_data, wtom_clock_nsec));
DEFINE(STAMP_XTIME, offsetof(struct vdso_data, stamp_xtime));
DEFINE(STAMP_SEC_FRAC, offsetof(struct vdso_data, stamp_sec_fraction));
+ DEFINE(CLOCK_HRTIMER_RES, offsetof(struct vdso_data, hrtimer_res));
DEFINE(CFG_ICACHE_BLOCKSZ, offsetof(struct vdso_data, icache_block_size));
DEFINE(CFG_DCACHE_BLOCKSZ, offsetof(struct vdso_data, dcache_block_size));
DEFINE(CFG_ICACHE_LOGBLOCKSZ, offsetof(struct vdso_data, icache_log_block_size));
@@ -411,7 +412,6 @@ int main(void)
DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
DEFINE(NSEC_PER_SEC, NSEC_PER_SEC);
- DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
#ifdef CONFIG_BUG
DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index ad713f7..eff4a33 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -527,8 +527,6 @@ void __do_irq(struct pt_regs *regs)
trace_irq_entry(regs);
- check_stack_overflow();
-
/*
* Query the platform PIC for the interrupt & ack it.
*
@@ -560,6 +558,8 @@ void do_IRQ(struct pt_regs *regs)
irqtp = hardirq_ctx[raw_smp_processor_id()];
sirqtp = softirq_ctx[raw_smp_processor_id()];
+ check_stack_overflow();
+
/* Already there ? */
if (unlikely(curtp == irqtp || curtp == sirqtp)) {
__do_irq(regs);
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index 11fff96..ff85fc8 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -135,32 +135,33 @@ ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, cha
thread_priv = security_ftr_enabled(SEC_FTR_L1D_THREAD_PRIV);
- if (rfi_flush || thread_priv) {
+ if (rfi_flush) {
struct seq_buf s;
seq_buf_init(&s, buf, PAGE_SIZE - 1);
- seq_buf_printf(&s, "Mitigation: ");
-
- if (rfi_flush)
- seq_buf_printf(&s, "RFI Flush");
-
- if (rfi_flush && thread_priv)
- seq_buf_printf(&s, ", ");
-
+ seq_buf_printf(&s, "Mitigation: RFI Flush");
if (thread_priv)
- seq_buf_printf(&s, "L1D private per thread");
+ seq_buf_printf(&s, ", L1D private per thread");
seq_buf_printf(&s, "\n");
return s.len;
}
+ if (thread_priv)
+ return sprintf(buf, "Vulnerable: L1D private per thread\n");
+
if (!security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV) &&
!security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR))
return sprintf(buf, "Not affected\n");
return sprintf(buf, "Vulnerable\n");
}
+
+ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ return cpu_show_meltdown(dev, attr, buf);
+}
#endif
ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index ab7b661..71315b4 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -257,7 +257,7 @@ static u64 scan_dispatch_log(u64 stop_tb)
* Accumulate stolen time by scanning the dispatch trace log.
* Called on entry from user mode.
*/
-void accumulate_stolen_time(void)
+void notrace accumulate_stolen_time(void)
{
u64 sst, ust;
u8 save_soft_enabled = local_paca->soft_enabled;
@@ -862,6 +862,7 @@ void update_vsyscall_old(struct timespec *wall_time, struct timespec *wtm,
vdso_data->wtom_clock_nsec = wtm->tv_nsec;
vdso_data->stamp_xtime = *wall_time;
vdso_data->stamp_sec_fraction = frac_sec;
+ vdso_data->hrtimer_res = hrtimer_resolution;
smp_wmb();
++(vdso_data->tb_update_count);
}
diff --git a/arch/powerpc/kernel/vdso32/gettimeofday.S b/arch/powerpc/kernel/vdso32/gettimeofday.S
index 7b341b8..9b24466 100644
--- a/arch/powerpc/kernel/vdso32/gettimeofday.S
+++ b/arch/powerpc/kernel/vdso32/gettimeofday.S
@@ -160,12 +160,15 @@
cror cr0*4+eq,cr0*4+eq,cr1*4+eq
bne cr0,99f
+ mflr r12
+ .cfi_register lr,r12
+ bl __get_datapage@local /* get data page */
+ lwz r5, CLOCK_HRTIMER_RES(r3)
+ mtlr r12
li r3,0
cmpli cr0,r4,0
crclr cr0*4+so
beqlr
- lis r5,CLOCK_REALTIME_RES@h
- ori r5,r5,CLOCK_REALTIME_RES@l
stw r3,TSPC32_TV_SEC(r4)
stw r5,TSPC32_TV_NSEC(r4)
blr
diff --git a/arch/powerpc/kernel/vdso64/cacheflush.S b/arch/powerpc/kernel/vdso64/cacheflush.S
index 69c5af2..228a4a2 100644
--- a/arch/powerpc/kernel/vdso64/cacheflush.S
+++ b/arch/powerpc/kernel/vdso64/cacheflush.S
@@ -39,7 +39,7 @@
subf r8,r6,r4 /* compute length */
add r8,r8,r5 /* ensure we get enough */
lwz r9,CFG_DCACHE_LOGBLOCKSZ(r10)
- srw. r8,r8,r9 /* compute line count */
+ srd. r8,r8,r9 /* compute line count */
crclr cr0*4+so
beqlr /* nothing to do? */
mtctr r8
@@ -56,7 +56,7 @@
subf r8,r6,r4 /* compute length */
add r8,r8,r5
lwz r9,CFG_ICACHE_LOGBLOCKSZ(r10)
- srw. r8,r8,r9 /* compute line count */
+ srd. r8,r8,r9 /* compute line count */
crclr cr0*4+so
beqlr /* nothing to do? */
mtctr r8
diff --git a/arch/powerpc/kernel/vdso64/gettimeofday.S b/arch/powerpc/kernel/vdso64/gettimeofday.S
index 09b2a49..c973378 100644
--- a/arch/powerpc/kernel/vdso64/gettimeofday.S
+++ b/arch/powerpc/kernel/vdso64/gettimeofday.S
@@ -145,12 +145,15 @@
cror cr0*4+eq,cr0*4+eq,cr1*4+eq
bne cr0,99f
+ mflr r12
+ .cfi_register lr,r12
+ bl V_LOCAL_FUNC(__get_datapage)
+ lwz r5, CLOCK_HRTIMER_RES(r3)
+ mtlr r12
li r3,0
cmpldi cr0,r4,0
crclr cr0*4+so
beqlr
- lis r5,CLOCK_REALTIME_RES@h
- ori r5,r5,CLOCK_REALTIME_RES@l
std r3,TSPC64_TV_SEC(r4)
std r5,TSPC64_TV_NSEC(r4)
blr
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index bd66628..2dc1fc4 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -289,10 +289,18 @@ int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
HPTE_V_BOLTED, psize, psize,
ssize);
-
+ if (ret == -1) {
+ /* Try to remove a non bolted entry */
+ ret = mmu_hash_ops.hpte_remove(hpteg);
+ if (ret != -1)
+ ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
+ HPTE_V_BOLTED, psize, psize,
+ ssize);
+ }
if (ret < 0)
break;
+ cond_resched();
#ifdef CONFIG_DEBUG_PAGEALLOC
if (debug_pagealloc_enabled() &&
(paddr >> PAGE_SHIFT) < linear_map_hash_count)
diff --git a/arch/powerpc/platforms/pseries/cmm.c b/arch/powerpc/platforms/pseries/cmm.c
index 85018a1..316eded 100644
--- a/arch/powerpc/platforms/pseries/cmm.c
+++ b/arch/powerpc/platforms/pseries/cmm.c
@@ -391,6 +391,10 @@ static struct bus_type cmm_subsys = {
.dev_name = "cmm",
};
+static void cmm_release_device(struct device *dev)
+{
+}
+
/**
* cmm_sysfs_register - Register with sysfs
*
@@ -406,6 +410,7 @@ static int cmm_sysfs_register(struct device *dev)
dev->id = 0;
dev->bus = &cmm_subsys;
+ dev->release = cmm_release_device;
if ((rc = device_register(dev)))
goto subsys_unregister;
diff --git a/arch/s390/kernel/dis.c b/arch/s390/kernel/dis.c
index aaf9dab..f9dca1a 100644
--- a/arch/s390/kernel/dis.c
+++ b/arch/s390/kernel/dis.c
@@ -1930,10 +1930,11 @@ static int print_insn(char *buffer, unsigned char *code, unsigned long addr)
ptr += sprintf(ptr, "%%c%i", value);
else if (operand->flags & OPERAND_VR)
ptr += sprintf(ptr, "%%v%i", value);
- else if (operand->flags & OPERAND_PCREL)
- ptr += sprintf(ptr, "%lx", (signed int) value
- + addr);
- else if (operand->flags & OPERAND_SIGNED)
+ else if (operand->flags & OPERAND_PCREL) {
+ void *pcrel = (void *)((int)value + addr);
+
+ ptr += sprintf(ptr, "%px", pcrel);
+ } else if (operand->flags & OPERAND_SIGNED)
ptr += sprintf(ptr, "%i", value);
else
ptr += sprintf(ptr, "%u", value);
@@ -2005,7 +2006,7 @@ void show_code(struct pt_regs *regs)
else
*ptr++ = ' ';
addr = regs->psw.addr + start - 32;
- ptr += sprintf(ptr, "%016lx: ", addr);
+ ptr += sprintf(ptr, "%px: ", (void *)addr);
if (start + opsize >= end)
break;
for (i = 0; i < opsize; i++)
@@ -2033,7 +2034,7 @@ void print_fn_code(unsigned char *code, unsigned long len)
opsize = insn_length(*code);
if (opsize > len)
break;
- ptr += sprintf(ptr, "%p: ", code);
+ ptr += sprintf(ptr, "%px: ", code);
for (i = 0; i < opsize; i++)
ptr += sprintf(ptr, "%02x", code[i]);
*ptr++ = '\t';
diff --git a/arch/s390/kernel/perf_cpum_sf.c b/arch/s390/kernel/perf_cpum_sf.c
index f46e5c0..02476d2 100644
--- a/arch/s390/kernel/perf_cpum_sf.c
+++ b/arch/s390/kernel/perf_cpum_sf.c
@@ -185,7 +185,7 @@ static int realloc_sampling_buffer(struct sf_buffer *sfb,
unsigned long num_sdb, gfp_t gfp_flags)
{
int i, rc;
- unsigned long *new, *tail;
+ unsigned long *new, *tail, *tail_prev = NULL;
if (!sfb->sdbt || !sfb->tail)
return -EINVAL;
@@ -224,6 +224,7 @@ static int realloc_sampling_buffer(struct sf_buffer *sfb,
sfb->num_sdbt++;
/* Link current page to tail of chain */
*tail = (unsigned long)(void *) new + 1;
+ tail_prev = tail;
tail = new;
}
@@ -233,10 +234,22 @@ static int realloc_sampling_buffer(struct sf_buffer *sfb,
* issue, a new realloc call (if required) might succeed.
*/
rc = alloc_sample_data_block(tail, gfp_flags);
- if (rc)
+ if (rc) {
+ /* Undo last SDBT. An SDBT with no SDB at its first
+ * entry but with an SDBT entry instead can not be
+ * handled by the interrupt handler code.
+ * Avoid this situation.
+ */
+ if (tail_prev) {
+ sfb->num_sdbt--;
+ free_page((unsigned long) new);
+ tail = tail_prev;
+ }
break;
+ }
sfb->num_sdb++;
tail++;
+ tail_prev = new = NULL; /* Allocated at least one SBD */
}
/* Link sampling buffer to its origin */
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7734.h b/arch/sh/include/cpu-sh4/cpu/sh7734.h
index 2fb9a7b..a2667c9 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7734.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7734.h
@@ -133,7 +133,7 @@ enum {
GPIO_FN_EX_WAIT1, GPIO_FN_SD1_DAT0_A, GPIO_FN_DREQ2, GPIO_FN_CAN1_TX_C,
GPIO_FN_ET0_LINK_C, GPIO_FN_ET0_ETXD5_A,
GPIO_FN_EX_WAIT0, GPIO_FN_TCLK1_B,
- GPIO_FN_RD_WR, GPIO_FN_TCLK0,
+ GPIO_FN_RD_WR, GPIO_FN_TCLK0, GPIO_FN_CAN_CLK_B, GPIO_FN_ET0_ETXD4,
GPIO_FN_EX_CS5, GPIO_FN_SD1_CMD_A, GPIO_FN_ATADIR, GPIO_FN_QSSL_B,
GPIO_FN_ET0_ETXD3_A,
GPIO_FN_EX_CS4, GPIO_FN_SD1_WP_A, GPIO_FN_ATAWR, GPIO_FN_QMI_QIO1_B,
diff --git a/arch/x86/configs/x86_64_cuttlefish_defconfig b/arch/x86/configs/x86_64_cuttlefish_defconfig
index 7f1277f..dced28f 100644
--- a/arch/x86/configs/x86_64_cuttlefish_defconfig
+++ b/arch/x86/configs/x86_64_cuttlefish_defconfig
@@ -56,7 +56,6 @@
CONFIG_X86_CPUID=y
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
-CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_ZSMALLOC=y
# CONFIG_MTRR is not set
CONFIG_HZ_100=y
diff --git a/arch/x86/include/asm/crash.h b/arch/x86/include/asm/crash.h
index f498411..1b15304 100644
--- a/arch/x86/include/asm/crash.h
+++ b/arch/x86/include/asm/crash.h
@@ -1,6 +1,8 @@
#ifndef _ASM_X86_CRASH_H
#define _ASM_X86_CRASH_H
+struct kimage;
+
int crash_load_segments(struct kimage *image);
int crash_copy_backup_region(struct kimage *image);
int crash_setup_memmap_entries(struct kimage *image,
diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h
index 8554f96..61d6f2c 100644
--- a/arch/x86/include/asm/fixmap.h
+++ b/arch/x86/include/asm/fixmap.h
@@ -142,7 +142,7 @@ extern pte_t *kmap_pte;
extern pte_t *pkmap_page_table;
void __native_set_fixmap(enum fixed_addresses idx, pte_t pte);
-void native_set_fixmap(enum fixed_addresses idx,
+void native_set_fixmap(unsigned /* enum fixed_addresses */ idx,
phys_addr_t phys, pgprot_t flags);
#ifndef CONFIG_PARAVIRT
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 09dd95c..3401b28 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -1712,9 +1712,10 @@ static bool io_apic_level_ack_pending(struct mp_chip_data *data)
static inline bool ioapic_irqd_mask(struct irq_data *data)
{
- /* If we are moving the irq we need to mask it */
+ /* If we are moving the IRQ we need to mask it */
if (unlikely(irqd_is_setaffinity_pending(data))) {
- mask_ioapic_irq(data);
+ if (!irqd_irq_masked(data))
+ mask_ioapic_irq(data);
return true;
}
return false;
@@ -1751,7 +1752,9 @@ static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
*/
if (!io_apic_level_ack_pending(data->chip_data))
irq_move_masked_irq(data);
- unmask_ioapic_irq(data);
+ /* If the IRQ is masked in the core, leave it: */
+ if (!irqd_irq_masked(data))
+ unmask_ioapic_irq(data);
}
}
#else
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index e348bee..07188a0 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -782,8 +782,8 @@ static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
if (quirk_no_way_out)
quirk_no_way_out(i, m, regs);
+ m->bank = i;
if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) {
- m->bank = i;
mce_read_aux(m, i);
*msg = tmp;
return 1;
@@ -1648,36 +1648,6 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
if (c->x86 == 0x15 && c->x86_model <= 0xf)
mce_flags.overflow_recov = 1;
- /*
- * Turn off MC4_MISC thresholding banks on those models since
- * they're not supported there.
- */
- if (c->x86 == 0x15 &&
- (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) {
- int i;
- u64 hwcr;
- bool need_toggle;
- u32 msrs[] = {
- 0x00000413, /* MC4_MISC0 */
- 0xc0000408, /* MC4_MISC1 */
- };
-
- rdmsrl(MSR_K7_HWCR, hwcr);
-
- /* McStatusWrEn has to be set */
- need_toggle = !(hwcr & BIT(18));
-
- if (need_toggle)
- wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
-
- /* Clear CntP bit safely */
- for (i = 0; i < ARRAY_SIZE(msrs); i++)
- msr_clear_bit(msrs[i], 62);
-
- /* restore old settings */
- if (need_toggle)
- wrmsrl(MSR_K7_HWCR, hwcr);
- }
}
if (c->x86_vendor == X86_VENDOR_INTEL) {
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 39526e1..2a473cd 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -499,6 +499,40 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
return offset;
}
+/*
+ * Turn off MC4_MISC thresholding banks on all family 0x15 models since
+ * they're not supported there.
+ */
+void disable_err_thresholding(struct cpuinfo_x86 *c)
+{
+ int i;
+ u64 hwcr;
+ bool need_toggle;
+ u32 msrs[] = {
+ 0x00000413, /* MC4_MISC0 */
+ 0xc0000408, /* MC4_MISC1 */
+ };
+
+ if (c->x86 != 0x15)
+ return;
+
+ rdmsrl(MSR_K7_HWCR, hwcr);
+
+ /* McStatusWrEn has to be set */
+ need_toggle = !(hwcr & BIT(18));
+
+ if (need_toggle)
+ wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
+
+ /* Clear CntP bit safely */
+ for (i = 0; i < ARRAY_SIZE(msrs); i++)
+ msr_clear_bit(msrs[i], 62);
+
+ /* restore old settings */
+ if (need_toggle)
+ wrmsrl(MSR_K7_HWCR, hwcr);
+}
+
/* cpu init entry point, called from mce.c with preempt off */
void mce_amd_feature_init(struct cpuinfo_x86 *c)
{
@@ -506,6 +540,8 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
unsigned int bank, block, cpu = smp_processor_id();
int offset = -1;
+ disable_err_thresholding(c);
+
for (bank = 0; bank < mca_cfg.banks; ++bank) {
if (mce_flags.smca)
get_smca_bank_info(bank);
diff --git a/arch/x86/kernel/cpu/mcheck/therm_throt.c b/arch/x86/kernel/cpu/mcheck/therm_throt.c
index c460c91..be24395 100644
--- a/arch/x86/kernel/cpu/mcheck/therm_throt.c
+++ b/arch/x86/kernel/cpu/mcheck/therm_throt.c
@@ -190,7 +190,7 @@ static int therm_throt_process(bool new_event, int event, int level)
/* if we just entered the thermal event */
if (new_event) {
if (event == THERMAL_THROTTLING_EVENT)
- pr_crit("CPU%d: %s temperature above threshold, cpu clock throttled (total events = %lu)\n",
+ pr_warn("CPU%d: %s temperature above threshold, cpu clock throttled (total events = %lu)\n",
this_cpu,
level == CORE_LEVEL ? "Core" : "Package",
state->count);
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 18c5b49..242ad06 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -389,7 +389,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
r = -E2BIG;
- if (*nent >= maxnent)
+ if (WARN_ON(*nent >= maxnent))
goto out;
do_cpuid_1_ent(entry, function, index);
@@ -691,6 +691,9 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
static int do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 func,
u32 idx, int *nent, int maxnent, unsigned int type)
{
+ if (*nent >= maxnent)
+ return -E2BIG;
+
if (type == KVM_GET_EMULATED_CPUID)
return __do_cpuid_ent_emulated(entry, func, idx, nent, maxnent);
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 06cd710..c9c5333 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -273,13 +273,14 @@ int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
int err;
- if (((value ^ smsr->values[slot].curr) & mask) == 0)
+ value = (value & mask) | (smsr->values[slot].host & ~mask);
+ if (value == smsr->values[slot].curr)
return 0;
- smsr->values[slot].curr = value;
err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
if (err)
return 1;
+ smsr->values[slot].curr = value;
if (!smsr->registered) {
smsr->urn.on_user_return = kvm_on_user_return;
user_return_notifier_register(&smsr->urn);
@@ -1074,10 +1075,15 @@ u64 kvm_get_arch_capabilities(void)
* If TSX is disabled on the system, guests are also mitigated against
* TAA and clear CPU buffer mitigation is not required for guests.
*/
- if (boot_cpu_has_bug(X86_BUG_TAA) && boot_cpu_has(X86_FEATURE_RTM) &&
- (data & ARCH_CAP_TSX_CTRL_MSR))
+ if (!boot_cpu_has(X86_FEATURE_RTM))
+ data &= ~ARCH_CAP_TAA_NO;
+ else if (!boot_cpu_has_bug(X86_BUG_TAA))
+ data |= ARCH_CAP_TAA_NO;
+ else if (data & ARCH_CAP_TSX_CTRL_MSR)
data &= ~ARCH_CAP_MDS_NO;
+ /* KVM does not emulate MSR_IA32_TSX_CTRL. */
+ data &= ~ARCH_CAP_TSX_CTRL_MSR;
return data;
}
diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt
index 1754e09..0f7eb4f 100644
--- a/arch/x86/lib/x86-opcode-map.txt
+++ b/arch/x86/lib/x86-opcode-map.txt
@@ -333,7 +333,7 @@
06: CLTS
07: SYSRET (o64)
08: INVD
-09: WBINVD
+09: WBINVD | WBNOINVD (F3)
0a:
0b: UD2 (1B)
0c:
@@ -364,7 +364,7 @@
# a ModR/M byte.
1a: BNDCL Gv,Ev (F3) | BNDCU Gv,Ev (F2) | BNDMOV Gv,Ev (66) | BNDLDX Gv,Ev
1b: BNDCN Gv,Ev (F2) | BNDMOV Ev,Gv (66) | BNDMK Gv,Ev (F3) | BNDSTX Ev,Gv
-1c:
+1c: Grp20 (1A),(1C)
1d:
1e:
1f: NOP Ev
@@ -792,6 +792,8 @@
f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v)
f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v)
f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) | SHRX Gy,Ey,By (F2),(v)
+f8: MOVDIR64B Gv,Mdqq (66) | ENQCMD Gv,Mdqq (F2) | ENQCMDS Gv,Mdqq (F3)
+f9: MOVDIRI My,Gy
EndTable
Table: 3-byte opcode 2 (0x0f 0x3a)
@@ -943,9 +945,9 @@
EndTable
GrpTable: Grp7
-0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B)
-1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B)
-2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B)
+0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B) | PCONFIG (101),(11B) | ENCLV (000),(11B)
+1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B) | ENCLS (111),(11B)
+2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B) | ENCLU (111),(11B)
3: LIDT Ms
4: SMSW Mw/Rv
5: rdpkru (110),(11B) | wrpkru (111),(11B)
@@ -1011,7 +1013,7 @@
3: vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B)
4: XSAVE
5: XRSTOR | lfence (11B)
-6: XSAVEOPT | clwb (66) | mfence (11B)
+6: XSAVEOPT | clwb (66) | mfence (11B) | TPAUSE Rd (66),(11B) | UMONITOR Rv (F3),(11B) | UMWAIT Rd (F2),(11B)
7: clflush | clflushopt (66) | sfence (11B)
EndTable
@@ -1042,6 +1044,10 @@
6: vscatterpf1qps/d Wx (66),(ev)
EndTable
+GrpTable: Grp20
+0: cldemote Mb
+EndTable
+
# AMD's Prefetch Group
GrpTable: GrpP
0: PREFETCH
diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
index dff8ac2..08e0380 100644
--- a/arch/x86/mm/pgtable.c
+++ b/arch/x86/mm/pgtable.c
@@ -544,8 +544,8 @@ void __native_set_fixmap(enum fixed_addresses idx, pte_t pte)
fixmaps_set++;
}
-void native_set_fixmap(enum fixed_addresses idx, phys_addr_t phys,
- pgprot_t flags)
+void native_set_fixmap(unsigned /* enum fixed_addresses */ idx,
+ phys_addr_t phys, pgprot_t flags)
{
__native_set_fixmap(idx, pfn_pte(phys >> PAGE_SHIFT, flags));
}
diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
index 20fa7c8..62950ef 100644
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@ -573,6 +573,17 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fa0, pci_invalid_bar);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fc0, pci_invalid_bar);
/*
+ * Device [1022:7914]
+ * When in D0, PME# doesn't get asserted when plugging USB 2.0 device.
+ */
+static void pci_fixup_amd_fch_xhci_pme(struct pci_dev *dev)
+{
+ dev_info(&dev->dev, "PME# does not work under D0, disabling it\n");
+ dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7914, pci_fixup_amd_fch_xhci_pme);
+
+/*
* Apple MacBook Pro: Avoid [mem 0x7fa00000-0x7fbfffff]
*
* Using the [mem 0x7fa00000-0x7fbfffff] region, e.g., by assigning it to
diff --git a/arch/xtensa/mm/tlb.c b/arch/xtensa/mm/tlb.c
index 35c8222..3ce5ccd 100644
--- a/arch/xtensa/mm/tlb.c
+++ b/arch/xtensa/mm/tlb.c
@@ -218,6 +218,8 @@ static int check_tlb_entry(unsigned w, unsigned e, bool dtlb)
unsigned tlbidx = w | (e << PAGE_SHIFT);
unsigned r0 = dtlb ?
read_dtlb_virtual(tlbidx) : read_itlb_virtual(tlbidx);
+ unsigned r1 = dtlb ?
+ read_dtlb_translation(tlbidx) : read_itlb_translation(tlbidx);
unsigned vpn = (r0 & PAGE_MASK) | (e << PAGE_SHIFT);
unsigned pte = get_pte_for_vaddr(vpn);
unsigned mm_asid = (get_rasid_register() >> 8) & ASID_MASK;
@@ -233,8 +235,6 @@ static int check_tlb_entry(unsigned w, unsigned e, bool dtlb)
}
if (tlb_asid == mm_asid) {
- unsigned r1 = dtlb ? read_dtlb_translation(tlbidx) :
- read_itlb_translation(tlbidx);
if ((pte ^ r1) & PAGE_MASK) {
pr_err("%cTLB: way: %u, entry: %u, mapping: %08x->%08x, PTE: %08x\n",
dtlb ? 'D' : 'I', w, e, r0, r1, pte);
diff --git a/block/blk-mq-sysfs.c b/block/blk-mq-sysfs.c
index 8c0894e..5b64d9d 100644
--- a/block/blk-mq-sysfs.c
+++ b/block/blk-mq-sysfs.c
@@ -243,20 +243,25 @@ static ssize_t blk_mq_hw_sysfs_active_show(struct blk_mq_hw_ctx *hctx, char *pag
static ssize_t blk_mq_hw_sysfs_cpus_show(struct blk_mq_hw_ctx *hctx, char *page)
{
+ const size_t size = PAGE_SIZE - 1;
unsigned int i, first = 1;
- ssize_t ret = 0;
+ int ret = 0, pos = 0;
for_each_cpu(i, hctx->cpumask) {
if (first)
- ret += sprintf(ret + page, "%u", i);
+ ret = snprintf(pos + page, size - pos, "%u", i);
else
- ret += sprintf(ret + page, ", %u", i);
+ ret = snprintf(pos + page, size - pos, ", %u", i);
+
+ if (ret >= size - pos)
+ break;
first = 0;
+ pos += ret;
}
- ret += sprintf(ret + page, "\n");
- return ret;
+ ret = snprintf(pos + page, size + 1 - pos, "\n");
+ return pos + ret;
}
static struct blk_mq_ctx_sysfs_entry blk_mq_sysfs_dispatched = {
diff --git a/crypto/crypto_user.c b/crypto/crypto_user.c
index 60cf7d1..810be7a 100644
--- a/crypto/crypto_user.c
+++ b/crypto/crypto_user.c
@@ -269,8 +269,10 @@ static int crypto_report(struct sk_buff *in_skb, struct nlmsghdr *in_nlh,
drop_alg:
crypto_mod_put(alg);
- if (err)
+ if (err) {
+ kfree_skb(skb);
return err;
+ }
return nlmsg_unicast(crypto_nlsk, skb, NETLINK_CB(in_skb).portid);
}
diff --git a/crypto/ecc.c b/crypto/ecc.c
index 414c78a..7cf6c3e 100644
--- a/crypto/ecc.c
+++ b/crypto/ecc.c
@@ -897,10 +897,11 @@ static void ecc_point_mult(struct ecc_point *result,
static inline void ecc_swap_digits(const u64 *in, u64 *out,
unsigned int ndigits)
{
+ const __be64 *src = (__force __be64 *)in;
int i;
for (i = 0; i < ndigits; i++)
- out[i] = __swab64(in[ndigits - 1 - i]);
+ out[i] = be64_to_cpu(src[ndigits - 1 - i]);
}
int ecc_is_key_valid(unsigned int curve_id, unsigned int ndigits,
diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
index 0a3ca20..6b2c9d6 100644
--- a/drivers/acpi/bus.c
+++ b/drivers/acpi/bus.c
@@ -158,7 +158,7 @@ int acpi_bus_get_private_data(acpi_handle handle, void **data)
{
acpi_status status;
- if (!*data)
+ if (!data)
return -EINVAL;
status = acpi_get_data(handle, acpi_bus_private_data_handler, data);
diff --git a/drivers/acpi/device_pm.c b/drivers/acpi/device_pm.c
index 993fd31..c76e452 100644
--- a/drivers/acpi/device_pm.c
+++ b/drivers/acpi/device_pm.c
@@ -1096,9 +1096,19 @@ static void acpi_dev_pm_detach(struct device *dev, bool power_off)
*/
int acpi_dev_pm_attach(struct device *dev, bool power_on)
{
+ /*
+ * Skip devices whose ACPI companions match the device IDs below,
+ * because they require special power management handling incompatible
+ * with the generic ACPI PM domain.
+ */
+ static const struct acpi_device_id special_pm_ids[] = {
+ {"PNP0C0B", }, /* Generic ACPI fan */
+ {"INT3404", }, /* Fan */
+ {}
+ };
struct acpi_device *adev = ACPI_COMPANION(dev);
- if (!adev)
+ if (!adev || !acpi_match_device_ids(adev, special_pm_ids))
return -ENODEV;
if (dev->pm_domain)
diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c
index b9fade7..c6c7e42 100644
--- a/drivers/acpi/osl.c
+++ b/drivers/acpi/osl.c
@@ -375,19 +375,21 @@ void *__ref acpi_os_map_memory(acpi_physical_address phys, acpi_size size)
}
EXPORT_SYMBOL_GPL(acpi_os_map_memory);
-static void acpi_os_drop_map_ref(struct acpi_ioremap *map)
+/* Must be called with mutex_lock(&acpi_ioremap_lock) */
+static unsigned long acpi_os_drop_map_ref(struct acpi_ioremap *map)
{
- if (!--map->refcount)
+ unsigned long refcount = --map->refcount;
+
+ if (!refcount)
list_del_rcu(&map->list);
+ return refcount;
}
static void acpi_os_map_cleanup(struct acpi_ioremap *map)
{
- if (!map->refcount) {
- synchronize_rcu_expedited();
- acpi_unmap(map->phys, map->virt);
- kfree(map);
- }
+ synchronize_rcu_expedited();
+ acpi_unmap(map->phys, map->virt);
+ kfree(map);
}
/**
@@ -407,6 +409,7 @@ static void acpi_os_map_cleanup(struct acpi_ioremap *map)
void __ref acpi_os_unmap_iomem(void __iomem *virt, acpi_size size)
{
struct acpi_ioremap *map;
+ unsigned long refcount;
if (!acpi_gbl_permanent_mmap) {
__acpi_unmap_table(virt, size);
@@ -420,10 +423,11 @@ void __ref acpi_os_unmap_iomem(void __iomem *virt, acpi_size size)
WARN(true, PREFIX "%s: bad address %p\n", __func__, virt);
return;
}
- acpi_os_drop_map_ref(map);
+ refcount = acpi_os_drop_map_ref(map);
mutex_unlock(&acpi_ioremap_lock);
- acpi_os_map_cleanup(map);
+ if (!refcount)
+ acpi_os_map_cleanup(map);
}
EXPORT_SYMBOL_GPL(acpi_os_unmap_iomem);
@@ -464,6 +468,7 @@ void acpi_os_unmap_generic_address(struct acpi_generic_address *gas)
{
u64 addr;
struct acpi_ioremap *map;
+ unsigned long refcount;
if (gas->space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY)
return;
@@ -479,10 +484,11 @@ void acpi_os_unmap_generic_address(struct acpi_generic_address *gas)
mutex_unlock(&acpi_ioremap_lock);
return;
}
- acpi_os_drop_map_ref(map);
+ refcount = acpi_os_drop_map_ref(map);
mutex_unlock(&acpi_ioremap_lock);
- acpi_os_map_cleanup(map);
+ if (!refcount)
+ acpi_os_map_cleanup(map);
}
EXPORT_SYMBOL(acpi_os_unmap_generic_address);
diff --git a/drivers/android/binder.c b/drivers/android/binder.c
index 9ec9b05..f7f9a20 100644
--- a/drivers/android/binder.c
+++ b/drivers/android/binder.c
@@ -3436,7 +3436,7 @@ static void binder_transaction(struct binder_proc *proc,
binder_size_t parent_offset;
struct binder_fd_array_object *fda =
to_binder_fd_array_object(hdr);
- size_t num_valid = (buffer_offset - off_start_offset) *
+ size_t num_valid = (buffer_offset - off_start_offset) /
sizeof(binder_size_t);
struct binder_buffer_object *parent =
binder_validate_ptr(target_proc, t->buffer,
@@ -3510,7 +3510,7 @@ static void binder_transaction(struct binder_proc *proc,
t->buffer->user_data + sg_buf_offset;
sg_buf_offset += ALIGN(bp->length, sizeof(u64));
- num_valid = (buffer_offset - off_start_offset) *
+ num_valid = (buffer_offset - off_start_offset) /
sizeof(binder_size_t);
ret = binder_fixup_parent(t, thread, bp,
off_start_offset,
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index da1a987..b1582f1 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -6550,6 +6550,9 @@ void ata_host_detach(struct ata_host *host)
{
int i;
+ /* Ensure ata_port probe has completed */
+ async_synchronize_full();
+
for (i = 0; i < host->n_ports; i++)
ata_port_detach(host->ports[i]);
diff --git a/drivers/block/rsxx/core.c b/drivers/block/rsxx/core.c
index 34997df..6beafaa 100644
--- a/drivers/block/rsxx/core.c
+++ b/drivers/block/rsxx/core.c
@@ -1025,8 +1025,10 @@ static void rsxx_pci_remove(struct pci_dev *dev)
cancel_work_sync(&card->event_work);
+ destroy_workqueue(card->event_wq);
rsxx_destroy_dev(card);
rsxx_dma_destroy(card);
+ destroy_workqueue(card->creg_ctrl.creg_wq);
spin_lock_irqsave(&card->irq_lock, flags);
rsxx_disable_ier_and_isr(card, CR_INTR_ALL);
diff --git a/drivers/cdrom/cdrom.c b/drivers/cdrom/cdrom.c
index a46f188..782dbab 100644
--- a/drivers/cdrom/cdrom.c
+++ b/drivers/cdrom/cdrom.c
@@ -998,6 +998,12 @@ static void cdrom_count_tracks(struct cdrom_device_info *cdi, tracktype *tracks)
tracks->xa = 0;
tracks->error = 0;
cd_dbg(CD_COUNT_TRACKS, "entering cdrom_count_tracks\n");
+
+ if (!CDROM_CAN(CDC_PLAY_AUDIO)) {
+ tracks->error = CDS_NO_INFO;
+ return;
+ }
+
/* Grab the TOC header so we can see how many tracks there are */
ret = cdi->ops->audio_ioctl(cdi, CDROMREADTOCHDR, &header);
if (ret) {
@@ -1164,7 +1170,8 @@ int cdrom_open(struct cdrom_device_info *cdi, struct block_device *bdev,
ret = open_for_data(cdi);
if (ret)
goto err;
- cdrom_mmc3_profile(cdi);
+ if (CDROM_CAN(CDC_GENERIC_PACKET))
+ cdrom_mmc3_profile(cdi);
if (mode & FMODE_WRITE) {
ret = -EROFS;
if (cdrom_open_write(cdi))
@@ -2873,6 +2880,9 @@ int cdrom_get_last_written(struct cdrom_device_info *cdi, long *last_written)
it doesn't give enough information or fails. then we return
the toc contents. */
use_toc:
+ if (!CDROM_CAN(CDC_PLAY_AUDIO))
+ return -ENOSYS;
+
toc.cdte_format = CDROM_MSF;
toc.cdte_track = CDROM_LEADOUT;
if ((ret = cdi->ops->audio_ioctl(cdi, CDROMREADTOCENTRY, &toc)))
diff --git a/drivers/char/hw_random/omap3-rom-rng.c b/drivers/char/hw_random/omap3-rom-rng.c
index 37a58d7..3324a7f 100644
--- a/drivers/char/hw_random/omap3-rom-rng.c
+++ b/drivers/char/hw_random/omap3-rom-rng.c
@@ -114,7 +114,8 @@ static int omap3_rom_rng_remove(struct platform_device *pdev)
{
cancel_delayed_work_sync(&idle_work);
hwrng_unregister(&omap3_rom_rng_ops);
- clk_disable_unprepare(rng_clk);
+ if (!rng_idle)
+ clk_disable_unprepare(rng_clk);
return 0;
}
diff --git a/drivers/char/ppdev.c b/drivers/char/ppdev.c
index 336d02a..3648727 100644
--- a/drivers/char/ppdev.c
+++ b/drivers/char/ppdev.c
@@ -624,20 +624,27 @@ static int pp_do_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
if (copy_from_user(time32, argp, sizeof(time32)))
return -EFAULT;
+ if ((time32[0] < 0) || (time32[1] < 0))
+ return -EINVAL;
+
return pp_set_timeout(pp->pdev, time32[0], time32[1]);
case PPSETTIME64:
if (copy_from_user(time64, argp, sizeof(time64)))
return -EFAULT;
+ if ((time64[0] < 0) || (time64[1] < 0))
+ return -EINVAL;
+
+ if (IS_ENABLED(CONFIG_SPARC64) && !in_compat_syscall())
+ time64[1] >>= 32;
+
return pp_set_timeout(pp->pdev, time64[0], time64[1]);
case PPGETTIME32:
jiffies_to_timespec64(pp->pdev->timeout, &ts);
time32[0] = ts.tv_sec;
time32[1] = ts.tv_nsec / NSEC_PER_USEC;
- if ((time32[0] < 0) || (time32[1] < 0))
- return -EINVAL;
if (copy_to_user(argp, time32, sizeof(time32)))
return -EFAULT;
@@ -648,8 +655,9 @@ static int pp_do_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
jiffies_to_timespec64(pp->pdev->timeout, &ts);
time64[0] = ts.tv_sec;
time64[1] = ts.tv_nsec / NSEC_PER_USEC;
- if ((time64[0] < 0) || (time64[1] < 0))
- return -EINVAL;
+
+ if (IS_ENABLED(CONFIG_SPARC64) && !in_compat_syscall())
+ time64[1] <<= 32;
if (copy_to_user(argp, time64, sizeof(time64)))
return -EFAULT;
diff --git a/drivers/clk/pxa/clk-pxa27x.c b/drivers/clk/pxa/clk-pxa27x.c
index c40b180..bb556f9 100644
--- a/drivers/clk/pxa/clk-pxa27x.c
+++ b/drivers/clk/pxa/clk-pxa27x.c
@@ -362,6 +362,7 @@ struct dummy_clk {
};
static struct dummy_clk dummy_clks[] __initdata = {
DUMMY_CLK(NULL, "pxa27x-gpio", "osc_32_768khz"),
+ DUMMY_CLK(NULL, "pxa-rtc", "osc_32_768khz"),
DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
};
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index a4e0670..9d99f0c 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -308,6 +308,8 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw,
p = clk_hw_get_parent_by_index(hw, index);
if (clk_flags & CLK_SET_RATE_PARENT) {
if (f->pre_div) {
+ if (!rate)
+ rate = req->rate;
rate /= 2;
rate *= f->pre_div + 1;
}
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index 316ac39..e149eb6 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -42,6 +42,9 @@ struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
if (!f)
return NULL;
+ if (!f->freq)
+ return f;
+
for (; f->freq; f++)
if (rate <= f->freq)
return f;
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index 523378d..d62031e 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -361,8 +361,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
RK2928_CLKGATE_CON(2), 5, GFLAGS),
MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(21), 4, 1, MFLAGS),
- GATE(0, "sclk_mac_lbtest", "sclk_macref",
- RK2928_CLKGATE_CON(2), 12, 0, GFLAGS),
+ GATE(0, "sclk_mac_lbtest", "sclk_macref", 0,
+ RK2928_CLKGATE_CON(2), 12, GFLAGS),
COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
@@ -390,8 +390,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
* Clock-Architecture Diagram 4
*/
- GATE(SCLK_SMC, "sclk_smc", "hclk_peri",
- RK2928_CLKGATE_CON(2), 4, 0, GFLAGS),
+ GATE(SCLK_SMC, "sclk_smc", "hclk_peri", 0,
+ RK2928_CLKGATE_CON(2), 4, GFLAGS),
COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0,
RK2928_CLKSEL_CON(25), 0, 7, DFLAGS,
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index a26c8a1..9dd6daa 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -458,7 +458,7 @@ static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
0x134, 16, 4, 24, 3, BIT(31), 0);
-static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", "pll-periph0" };
+static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
0x134, 0, 5, 8, 3, BIT(15), 0);
diff --git a/drivers/clocksource/asm9260_timer.c b/drivers/clocksource/asm9260_timer.c
index 1ba871b..e571780 100644
--- a/drivers/clocksource/asm9260_timer.c
+++ b/drivers/clocksource/asm9260_timer.c
@@ -198,6 +198,10 @@ static int __init asm9260_timer_init(struct device_node *np)
}
clk = of_clk_get(np, 0);
+ if (IS_ERR(clk)) {
+ pr_err("Failed to get clk!\n");
+ return PTR_ERR(clk);
+ }
ret = clk_prepare_enable(clk);
if (ret) {
diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c
index 34355a9..1667bc0e 100644
--- a/drivers/cpufreq/cpufreq.c
+++ b/drivers/cpufreq/cpufreq.c
@@ -2595,6 +2595,13 @@ int cpufreq_register_driver(struct cpufreq_driver *driver_data)
if (cpufreq_disabled())
return -ENODEV;
+ /*
+ * The cpufreq core depends heavily on the availability of device
+ * structure, make sure they are available before proceeding further.
+ */
+ if (!get_cpu_device(0))
+ return -EPROBE_DEFER;
+
if (!driver_data || !driver_data->verify || !driver_data->init ||
!(driver_data->setpolicy || driver_data->target_index ||
driver_data->target) ||
diff --git a/drivers/cpuidle/driver.c b/drivers/cpuidle/driver.c
index ab264d3..3780e1a 100644
--- a/drivers/cpuidle/driver.c
+++ b/drivers/cpuidle/driver.c
@@ -61,25 +61,24 @@ static inline void __cpuidle_unset_driver(struct cpuidle_driver *drv)
* __cpuidle_set_driver - set per CPU driver variables for the given driver.
* @drv: a valid pointer to a struct cpuidle_driver
*
- * For each CPU in the driver's cpumask, unset the registered driver per CPU
- * to @drv.
- *
- * Returns 0 on success, -EBUSY if the CPUs have driver(s) already.
+ * Returns 0 on success, -EBUSY if any CPU in the cpumask have a driver
+ * different from drv already.
*/
static inline int __cpuidle_set_driver(struct cpuidle_driver *drv)
{
int cpu;
for_each_cpu(cpu, drv->cpumask) {
+ struct cpuidle_driver *old_drv;
- if (__cpuidle_get_cpu_driver(cpu)) {
- __cpuidle_unset_driver(drv);
+ old_drv = __cpuidle_get_cpu_driver(cpu);
+ if (old_drv && old_drv != drv)
return -EBUSY;
- }
-
- per_cpu(cpuidle_drivers, cpu) = drv;
}
+ for_each_cpu(cpu, drv->cpumask)
+ per_cpu(cpuidle_drivers, cpu) = drv;
+
return 0;
}
diff --git a/drivers/crypto/amcc/crypto4xx_core.c b/drivers/crypto/amcc/crypto4xx_core.c
index 7d066fa..e5e83c6 100644
--- a/drivers/crypto/amcc/crypto4xx_core.c
+++ b/drivers/crypto/amcc/crypto4xx_core.c
@@ -400,12 +400,8 @@ static u32 crypto4xx_build_sdr(struct crypto4xx_device *dev)
dma_alloc_coherent(dev->core_dev->device,
dev->scatter_buffer_size * PPC4XX_NUM_SD,
&dev->scatter_buffer_pa, GFP_ATOMIC);
- if (!dev->scatter_buffer_va) {
- dma_free_coherent(dev->core_dev->device,
- sizeof(struct ce_sd) * PPC4XX_NUM_SD,
- dev->sdr, dev->sdr_pa);
+ if (!dev->scatter_buffer_va)
return -ENOMEM;
- }
sd_array = dev->sdr;
diff --git a/drivers/crypto/ccp/ccp-dmaengine.c b/drivers/crypto/ccp/ccp-dmaengine.c
index 8d0eeb4..c458151 100644
--- a/drivers/crypto/ccp/ccp-dmaengine.c
+++ b/drivers/crypto/ccp/ccp-dmaengine.c
@@ -309,6 +309,7 @@ static struct ccp_dma_desc *ccp_alloc_dma_desc(struct ccp_dma_chan *chan,
desc->tx_desc.flags = flags;
desc->tx_desc.tx_submit = ccp_tx_submit;
desc->ccp = chan->ccp;
+ INIT_LIST_HEAD(&desc->entry);
INIT_LIST_HEAD(&desc->pending);
INIT_LIST_HEAD(&desc->active);
desc->status = DMA_IN_PROGRESS;
diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-hash.c b/drivers/crypto/sunxi-ss/sun4i-ss-hash.c
index ec16ec2e..b2e6837 100644
--- a/drivers/crypto/sunxi-ss/sun4i-ss-hash.c
+++ b/drivers/crypto/sunxi-ss/sun4i-ss-hash.c
@@ -286,8 +286,8 @@ static int sun4i_hash(struct ahash_request *areq)
*/
while (op->len < 64 && i < end) {
/* how many bytes we can read from current SG */
- in_r = min3(mi.length - in_i, end - i,
- 64 - op->len);
+ in_r = min(end - i, 64 - op->len);
+ in_r = min_t(size_t, mi.length - in_i, in_r);
memcpy(op->buf + op->len, mi.addr + in_i, in_r);
op->len += in_r;
i += in_r;
@@ -307,8 +307,8 @@ static int sun4i_hash(struct ahash_request *areq)
}
if (mi.length - in_i > 3 && i < end) {
/* how many bytes we can read from current SG */
- in_r = min3(mi.length - in_i, areq->nbytes - i,
- ((mi.length - in_i) / 4) * 4);
+ in_r = min_t(size_t, mi.length - in_i, areq->nbytes - i);
+ in_r = min_t(size_t, ((mi.length - in_i) / 4) * 4, in_r);
/* how many bytes we can write in the device*/
todo = min3((u32)(end - i) / 4, rx_cnt, (u32)in_r / 4);
writesl(ss->base + SS_RXFIFO, mi.addr + in_i, todo);
@@ -334,8 +334,8 @@ static int sun4i_hash(struct ahash_request *areq)
if ((areq->nbytes - i) < 64) {
while (i < areq->nbytes && in_i < mi.length && op->len < 64) {
/* how many bytes we can read from current SG */
- in_r = min3(mi.length - in_i, areq->nbytes - i,
- 64 - op->len);
+ in_r = min(areq->nbytes - i, 64 - op->len);
+ in_r = min_t(size_t, mi.length - in_i, in_r);
memcpy(op->buf + op->len, mi.addr + in_i, in_r);
op->len += in_r;
i += in_r;
diff --git a/drivers/crypto/vmx/Makefile b/drivers/crypto/vmx/Makefile
index de6e241..957377c 100644
--- a/drivers/crypto/vmx/Makefile
+++ b/drivers/crypto/vmx/Makefile
@@ -2,13 +2,13 @@
vmx-crypto-objs := vmx.o aesp8-ppc.o ghashp8-ppc.o aes.o aes_cbc.o aes_ctr.o aes_xts.o ghash.o
ifeq ($(CONFIG_CPU_LITTLE_ENDIAN),y)
-TARGET := linux-ppc64le
+override flavour := linux-ppc64le
else
-TARGET := linux-ppc64
+override flavour := linux-ppc64
endif
quiet_cmd_perl = PERL $@
- cmd_perl = $(PERL) $(<) $(TARGET) > $(@)
+ cmd_perl = $(PERL) $(<) $(flavour) > $(@)
$(src)/aesp8-ppc.S: $(src)/aesp8-ppc.pl
$(call cmd,perl)
diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index 2298de2..2760fe8 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -158,6 +158,7 @@ int devfreq_update_status(struct devfreq *devfreq, unsigned long freq)
int lev, prev_lev, ret = 0;
unsigned long cur_time;
+ lockdep_assert_held(&devfreq->lock);
cur_time = jiffies;
/* Immediately exit if previous_freq is not initialized yet. */
@@ -1222,12 +1223,17 @@ static ssize_t trans_stat_show(struct device *dev,
int i, j;
unsigned int max_state = devfreq->profile->max_state;
- if (!devfreq->stop_polling &&
- devfreq_update_status(devfreq, devfreq->previous_freq))
- return 0;
if (max_state == 0)
return sprintf(buf, "Not Supported.\n");
+ mutex_lock(&devfreq->lock);
+ if (!devfreq->stop_polling &&
+ devfreq_update_status(devfreq, devfreq->previous_freq)) {
+ mutex_unlock(&devfreq->lock);
+ return 0;
+ }
+ mutex_unlock(&devfreq->lock);
+
len = sprintf(buf, " From : To\n");
len += sprintf(buf + len, " :");
for (i = 0; i < max_state; i++)
diff --git a/drivers/dma-buf/sync_file.c b/drivers/dma-buf/sync_file.c
index 1936383..426a75d 100644
--- a/drivers/dma-buf/sync_file.c
+++ b/drivers/dma-buf/sync_file.c
@@ -210,7 +210,7 @@ static struct sync_file *sync_file_merge(const char *name, struct sync_file *a,
a_fences = get_fences(a, &a_num_fences);
b_fences = get_fences(b, &b_num_fences);
if (a_num_fences > INT_MAX - b_num_fences)
- return NULL;
+ goto err;
num_fences = a_num_fences + b_num_fences;
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index 74794c9..6d7d2d5 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -1797,13 +1797,10 @@ static struct dma_chan *coh901318_xlate(struct of_phandle_args *dma_spec,
static int coh901318_config(struct coh901318_chan *cohc,
struct coh901318_params *param)
{
- unsigned long flags;
const struct coh901318_params *p;
int channel = cohc->id;
void __iomem *virtbase = cohc->base->virtbase;
- spin_lock_irqsave(&cohc->lock, flags);
-
if (param)
p = param;
else
@@ -1823,8 +1820,6 @@ static int coh901318_config(struct coh901318_chan *cohc,
coh901318_set_conf(cohc, p->config);
coh901318_set_ctrl(cohc, p->ctrl_lli_last);
- spin_unlock_irqrestore(&cohc->lock, flags);
-
return 0;
}
diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c
index e3fa439..4ddbf66 100644
--- a/drivers/edac/ghes_edac.c
+++ b/drivers/edac/ghes_edac.c
@@ -189,6 +189,7 @@ void ghes_edac_report_mem_error(struct ghes *ghes, int sev,
/* Cleans the error report buffer */
memset(e, 0, sizeof (*e));
e->error_count = 1;
+ e->grain = 1;
strcpy(e->label, "unknown label");
e->msg = pvt->msg;
e->other_detail = pvt->other_detail;
@@ -284,7 +285,7 @@ void ghes_edac_report_mem_error(struct ghes *ghes, int sev,
/* Error grain */
if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
- e->grain = ~(mem_err->physical_addr_mask & ~PAGE_MASK);
+ e->grain = ~mem_err->physical_addr_mask + 1;
/* Memory error location, mapped on e->location */
p = e->location;
@@ -391,8 +392,13 @@ void ghes_edac_report_mem_error(struct ghes *ghes, int sev,
if (p > pvt->other_detail)
*(p - 1) = '\0';
+ /* Sanity-check driver-supplied grain value. */
+ if (WARN_ON_ONCE(!e->grain))
+ e->grain = 1;
+
+ grain_bits = fls_long(e->grain - 1);
+
/* Generate the trace event */
- grain_bits = fls_long(e->grain);
snprintf(pvt->detail_location, sizeof(pvt->detail_location),
"APEI location: %s %s", e->location, e->other_detail);
trace_mc_event(type, e->msg, e->label, e->error_count,
diff --git a/drivers/extcon/extcon-max8997.c b/drivers/extcon/extcon-max8997.c
index 4a0612f..b9b48d4 100644
--- a/drivers/extcon/extcon-max8997.c
+++ b/drivers/extcon/extcon-max8997.c
@@ -321,12 +321,10 @@ static int max8997_muic_handle_usb(struct max8997_muic_info *info,
{
int ret = 0;
- if (usb_type == MAX8997_USB_HOST) {
- ret = max8997_muic_set_path(info, info->path_usb, attached);
- if (ret < 0) {
- dev_err(info->dev, "failed to update muic register\n");
- return ret;
- }
+ ret = max8997_muic_set_path(info, info->path_usb, attached);
+ if (ret < 0) {
+ dev_err(info->dev, "failed to update muic register\n");
+ return ret;
}
switch (usb_type) {
diff --git a/drivers/extcon/extcon-sm5502.c b/drivers/extcon/extcon-sm5502.c
index b223256..9d2d8a6 100644
--- a/drivers/extcon/extcon-sm5502.c
+++ b/drivers/extcon/extcon-sm5502.c
@@ -69,6 +69,10 @@ struct sm5502_muic_info {
/* Default value of SM5502 register to bring up MUIC device. */
static struct reg_data sm5502_reg_data[] = {
{
+ .reg = SM5502_REG_RESET,
+ .val = SM5502_REG_RESET_MASK,
+ .invert = true,
+ }, {
.reg = SM5502_REG_CONTROL,
.val = SM5502_REG_CONTROL_MASK_INT_MASK,
.invert = false,
diff --git a/drivers/extcon/extcon-sm5502.h b/drivers/extcon/extcon-sm5502.h
index 974b532..12f8b01 100644
--- a/drivers/extcon/extcon-sm5502.h
+++ b/drivers/extcon/extcon-sm5502.h
@@ -241,6 +241,8 @@ enum sm5502_reg {
#define DM_DP_SWITCH_UART ((DM_DP_CON_SWITCH_UART <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \
| (DM_DP_CON_SWITCH_UART <<SM5502_REG_MANUAL_SW1_DM_SHIFT))
+#define SM5502_REG_RESET_MASK (0x1)
+
/* SM5502 Interrupts */
enum sm5502_irq {
/* INT1 */
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
index 1e2e519..7c31d27 100644
--- a/drivers/firmware/qcom_scm-64.c
+++ b/drivers/firmware/qcom_scm-64.c
@@ -158,7 +158,7 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
kfree(args_virt);
}
- if (res->a0 < 0)
+ if ((long)res->a0 < 0)
return qcom_scm_remap_error(res->a0);
return 0;
diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c
index 793518a..bd77768 100644
--- a/drivers/gpio/gpio-mpc8xxx.c
+++ b/drivers/gpio/gpio-mpc8xxx.c
@@ -337,7 +337,8 @@ static int mpc8xxx_probe(struct platform_device *pdev)
* It's assumed that only a single type of gpio controller is available
* on the current machine, so overwriting global data is fine.
*/
- mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
+ if (devtype->irq_set_type)
+ mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
if (devtype->gpio_dir_out)
gc->direction_output = devtype->gpio_dir_out;
diff --git a/drivers/gpu/drm/bridge/analogix-anx78xx.c b/drivers/gpu/drm/bridge/analogix-anx78xx.c
index a2a8236..eb97e88 100644
--- a/drivers/gpu/drm/bridge/analogix-anx78xx.c
+++ b/drivers/gpu/drm/bridge/analogix-anx78xx.c
@@ -725,7 +725,9 @@ static int anx78xx_init_pdata(struct anx78xx *anx78xx)
/* 1.0V digital core power regulator */
pdata->dvdd10 = devm_regulator_get(dev, "dvdd10");
if (IS_ERR(pdata->dvdd10)) {
- DRM_ERROR("DVDD10 regulator not found\n");
+ if (PTR_ERR(pdata->dvdd10) != -EPROBE_DEFER)
+ DRM_ERROR("DVDD10 regulator not found\n");
+
return PTR_ERR(pdata->dvdd10);
}
@@ -1344,7 +1346,9 @@ static int anx78xx_i2c_probe(struct i2c_client *client,
err = anx78xx_init_pdata(anx78xx);
if (err) {
- DRM_ERROR("Failed to initialize pdata: %d\n", err);
+ if (err != -EPROBE_DEFER)
+ DRM_ERROR("Failed to initialize pdata: %d\n", err);
+
return err;
}
diff --git a/drivers/gpu/drm/gma500/oaktrail_crtc.c b/drivers/gpu/drm/gma500/oaktrail_crtc.c
index da9fd34..caa6da0 100644
--- a/drivers/gpu/drm/gma500/oaktrail_crtc.c
+++ b/drivers/gpu/drm/gma500/oaktrail_crtc.c
@@ -139,6 +139,7 @@ static bool mrst_sdvo_find_best_pll(const struct gma_limit_t *limit,
s32 freq_error, min_error = 100000;
memset(best_clock, 0, sizeof(*best_clock));
+ memset(&clock, 0, sizeof(clock));
for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) {
for (clock.n = limit->n.min; clock.n <= limit->n.max;
@@ -195,6 +196,7 @@ static bool mrst_lvds_find_best_pll(const struct gma_limit_t *limit,
int err = target;
memset(best_clock, 0, sizeof(*best_clock));
+ memset(&clock, 0, sizeof(clock));
for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) {
for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max;
diff --git a/drivers/gpu/drm/i810/i810_dma.c b/drivers/gpu/drm/i810/i810_dma.c
index d918567..70de29f 100644
--- a/drivers/gpu/drm/i810/i810_dma.c
+++ b/drivers/gpu/drm/i810/i810_dma.c
@@ -723,7 +723,7 @@ static void i810_dma_dispatch_vertex(struct drm_device *dev,
if (nbox > I810_NR_SAREA_CLIPRECTS)
nbox = I810_NR_SAREA_CLIPRECTS;
- if (used > 4 * 1024)
+ if (used < 0 || used > 4 * 1024)
used = 0;
if (sarea_priv->dirty)
@@ -1043,7 +1043,7 @@ static void i810_dma_dispatch_mc(struct drm_device *dev, struct drm_buf *buf, in
if (u != I810_BUF_CLIENT)
DRM_DEBUG("MC found buffer that isn't mine!\n");
- if (used > 4 * 1024)
+ if (used < 0 || used > 4 * 1024)
used = 0;
sarea_priv->dirty = 0x7f;
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index f5e84f4..c99a976 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1824,8 +1824,8 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
track->textures[i].use_pitch = 1;
} else {
track->textures[i].use_pitch = 0;
- track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
- track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
+ track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT);
+ track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEIGHT_SHIFT);
}
if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
track->textures[i].tex_coord_type = 2;
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
index c70e6d5..8aa3772 100644
--- a/drivers/gpu/drm/radeon/r200.c
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -476,8 +476,8 @@ int r200_packet0_check(struct radeon_cs_parser *p,
track->textures[i].use_pitch = 1;
} else {
track->textures[i].use_pitch = 0;
- track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
- track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
+ track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT);
+ track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEIGHT_SHIFT);
}
if (idx_value & R200_TXFORMAT_LOOKUP_DISABLE)
track->textures[i].lookup_disable = true;
diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c
index acb0261..10d2a6b 100644
--- a/drivers/hid/hid-core.c
+++ b/drivers/hid/hid-core.c
@@ -761,6 +761,10 @@ static void hid_scan_feature_usage(struct hid_parser *parser, u32 usage)
if (usage == 0xff0000c5 && parser->global.report_count == 256 &&
parser->global.report_size == 8)
parser->scan_flags |= HID_SCAN_FLAG_MT_WIN_8;
+
+ if (usage == 0xff0000c6 && parser->global.report_count == 1 &&
+ parser->global.report_size == 8)
+ parser->scan_flags |= HID_SCAN_FLAG_MT_WIN_8;
}
static void hid_scan_collection(struct hid_parser *parser, unsigned type)
diff --git a/drivers/hid/hid-input.c b/drivers/hid/hid-input.c
index 9f7b1cf..e4aebe9 100644
--- a/drivers/hid/hid-input.c
+++ b/drivers/hid/hid-input.c
@@ -342,13 +342,45 @@ static unsigned find_battery_quirk(struct hid_device *hdev)
return quirks;
}
+static int hidinput_scale_battery_capacity(struct hid_device *dev,
+ int value)
+{
+ if (dev->battery_min < dev->battery_max &&
+ value >= dev->battery_min && value <= dev->battery_max)
+ value = ((value - dev->battery_min) * 100) /
+ (dev->battery_max - dev->battery_min);
+
+ return value;
+}
+
+static int hidinput_query_battery_capacity(struct hid_device *dev)
+{
+ u8 *buf;
+ int ret;
+
+ buf = kmalloc(2, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+
+ ret = hid_hw_raw_request(dev, dev->battery_report_id, buf, 2,
+ dev->battery_report_type, HID_REQ_GET_REPORT);
+ if (ret != 2) {
+ kfree(buf);
+ return -ENODATA;
+ }
+
+ ret = hidinput_scale_battery_capacity(dev, buf[1]);
+ kfree(buf);
+ return ret;
+}
+
static int hidinput_get_battery_property(struct power_supply *psy,
enum power_supply_property prop,
union power_supply_propval *val)
{
struct hid_device *dev = power_supply_get_drvdata(psy);
+ int value;
int ret = 0;
- __u8 *buf;
switch (prop) {
case POWER_SUPPLY_PROP_PRESENT:
@@ -357,29 +389,15 @@ static int hidinput_get_battery_property(struct power_supply *psy,
break;
case POWER_SUPPLY_PROP_CAPACITY:
-
- buf = kmalloc(2 * sizeof(__u8), GFP_KERNEL);
- if (!buf) {
- ret = -ENOMEM;
- break;
+ if (dev->battery_report_type == HID_FEATURE_REPORT) {
+ value = hidinput_query_battery_capacity(dev);
+ if (value < 0)
+ return value;
+ } else {
+ value = dev->battery_capacity;
}
- ret = hid_hw_raw_request(dev, dev->battery_report_id, buf, 2,
- dev->battery_report_type,
- HID_REQ_GET_REPORT);
- if (ret != 2) {
- ret = -ENODATA;
- kfree(buf);
- break;
- }
- ret = 0;
-
- if (dev->battery_min < dev->battery_max &&
- buf[1] >= dev->battery_min &&
- buf[1] <= dev->battery_max)
- val->intval = (100 * (buf[1] - dev->battery_min)) /
- (dev->battery_max - dev->battery_min);
- kfree(buf);
+ val->intval = value;
break;
case POWER_SUPPLY_PROP_MODEL_NAME:
@@ -387,7 +405,22 @@ static int hidinput_get_battery_property(struct power_supply *psy,
break;
case POWER_SUPPLY_PROP_STATUS:
- val->intval = POWER_SUPPLY_STATUS_DISCHARGING;
+ if (!dev->battery_reported &&
+ dev->battery_report_type == HID_FEATURE_REPORT) {
+ value = hidinput_query_battery_capacity(dev);
+ if (value < 0)
+ return value;
+
+ dev->battery_capacity = value;
+ dev->battery_reported = true;
+ }
+
+ if (!dev->battery_reported)
+ val->intval = POWER_SUPPLY_STATUS_UNKNOWN;
+ else if (dev->battery_capacity == 100)
+ val->intval = POWER_SUPPLY_STATUS_FULL;
+ else
+ val->intval = POWER_SUPPLY_STATUS_DISCHARGING;
break;
case POWER_SUPPLY_PROP_SCOPE:
@@ -402,18 +435,16 @@ static int hidinput_get_battery_property(struct power_supply *psy,
return ret;
}
-static bool hidinput_setup_battery(struct hid_device *dev, unsigned report_type, struct hid_field *field)
+static int hidinput_setup_battery(struct hid_device *dev, unsigned report_type, struct hid_field *field)
{
- struct power_supply_desc *psy_desc = NULL;
+ struct power_supply_desc *psy_desc;
struct power_supply_config psy_cfg = { .drv_data = dev, };
unsigned quirks;
s32 min, max;
+ int error;
- if (field->usage->hid != HID_DC_BATTERYSTRENGTH)
- return false; /* no match */
-
- if (dev->battery != NULL)
- goto out; /* already initialized? */
+ if (dev->battery)
+ return 0; /* already initialized? */
quirks = find_battery_quirk(dev);
@@ -421,16 +452,16 @@ static bool hidinput_setup_battery(struct hid_device *dev, unsigned report_type,
dev->bus, dev->vendor, dev->product, dev->version, quirks);
if (quirks & HID_BATTERY_QUIRK_IGNORE)
- goto out;
+ return 0;
psy_desc = kzalloc(sizeof(*psy_desc), GFP_KERNEL);
- if (psy_desc == NULL)
- goto out;
+ if (!psy_desc)
+ return -ENOMEM;
psy_desc->name = kasprintf(GFP_KERNEL, "hid-%s-battery", dev->uniq);
- if (psy_desc->name == NULL) {
- kfree(psy_desc);
- goto out;
+ if (!psy_desc->name) {
+ error = -ENOMEM;
+ goto err_free_mem;
}
psy_desc->type = POWER_SUPPLY_TYPE_BATTERY;
@@ -457,17 +488,20 @@ static bool hidinput_setup_battery(struct hid_device *dev, unsigned report_type,
dev->battery = power_supply_register(&dev->dev, psy_desc, &psy_cfg);
if (IS_ERR(dev->battery)) {
- hid_warn(dev, "can't register power supply: %ld\n",
- PTR_ERR(dev->battery));
- kfree(psy_desc->name);
- kfree(psy_desc);
- dev->battery = NULL;
- } else {
- power_supply_powers(dev->battery, &dev->dev);
+ error = PTR_ERR(dev->battery);
+ hid_warn(dev, "can't register power supply: %d\n", error);
+ goto err_free_name;
}
-out:
- return true;
+ power_supply_powers(dev->battery, &dev->dev);
+ return 0;
+
+err_free_name:
+ kfree(psy_desc->name);
+err_free_mem:
+ kfree(psy_desc);
+ dev->battery = NULL;
+ return error;
}
static void hidinput_cleanup_battery(struct hid_device *dev)
@@ -483,16 +517,33 @@ static void hidinput_cleanup_battery(struct hid_device *dev)
kfree(psy_desc);
dev->battery = NULL;
}
-#else /* !CONFIG_HID_BATTERY_STRENGTH */
-static bool hidinput_setup_battery(struct hid_device *dev, unsigned report_type,
- struct hid_field *field)
+
+static void hidinput_update_battery(struct hid_device *dev, int value)
{
- return false;
+ if (!dev->battery)
+ return;
+
+ if (value == 0 || value < dev->battery_min || value > dev->battery_max)
+ return;
+
+ dev->battery_capacity = hidinput_scale_battery_capacity(dev, value);
+ dev->battery_reported = true;
+ power_supply_changed(dev->battery);
+}
+#else /* !CONFIG_HID_BATTERY_STRENGTH */
+static int hidinput_setup_battery(struct hid_device *dev, unsigned report_type,
+ struct hid_field *field)
+{
+ return 0;
}
static void hidinput_cleanup_battery(struct hid_device *dev)
{
}
+
+static void hidinput_update_battery(struct hid_device *dev, int value)
+{
+}
#endif /* CONFIG_HID_BATTERY_STRENGTH */
static void hidinput_configure_usage(struct hid_input *hidinput, struct hid_field *field,
@@ -711,6 +762,11 @@ static void hidinput_configure_usage(struct hid_input *hidinput, struct hid_fiel
}
break;
+ case 0x3b: /* Battery Strength */
+ hidinput_setup_battery(device, HID_INPUT_REPORT, field);
+ usage->type = EV_PWR;
+ goto ignore;
+
case 0x3c: /* Invert */
map_key_clear(BTN_TOOL_RUBBER);
break;
@@ -951,11 +1007,13 @@ static void hidinput_configure_usage(struct hid_input *hidinput, struct hid_fiel
break;
case HID_UP_GENDEVCTRLS:
- if (hidinput_setup_battery(device, HID_INPUT_REPORT, field))
+ switch (usage->hid) {
+ case HID_DC_BATTERYSTRENGTH:
+ hidinput_setup_battery(device, HID_INPUT_REPORT, field);
+ usage->type = EV_PWR;
goto ignore;
- else
- goto unknown;
- break;
+ }
+ goto unknown;
case HID_UP_HPVENDOR: /* Reported on a Dutch layout HP5308 */
set_bit(EV_REP, input->evbit);
@@ -1038,7 +1096,6 @@ static void hidinput_configure_usage(struct hid_input *hidinput, struct hid_fiel
if (usage->code > max)
goto ignore;
-
if (usage->type == EV_ABS) {
int a = field->logical_minimum;
@@ -1097,14 +1154,19 @@ void hidinput_hid_event(struct hid_device *hid, struct hid_field *field, struct
struct input_dev *input;
unsigned *quirks = &hid->quirks;
+ if (!usage->type)
+ return;
+
+ if (usage->type == EV_PWR) {
+ hidinput_update_battery(hid, value);
+ return;
+ }
+
if (!field->hidinput)
return;
input = field->hidinput->input;
- if (!usage->type)
- return;
-
if (usage->hat_min < usage->hat_max || usage->hat_dir) {
int hat_dir = usage->hat_dir;
if (!hat_dir)
@@ -1381,6 +1443,7 @@ static void report_features(struct hid_device *hid)
struct hid_driver *drv = hid->driver;
struct hid_report_enum *rep_enum;
struct hid_report *rep;
+ struct hid_usage *usage;
int i, j;
rep_enum = &hid->report_enum[HID_FEATURE_REPORT];
@@ -1391,12 +1454,15 @@ static void report_features(struct hid_device *hid)
continue;
for (j = 0; j < rep->field[i]->maxusage; j++) {
+ usage = &rep->field[i]->usage[j];
+
/* Verify if Battery Strength feature is available */
- hidinput_setup_battery(hid, HID_FEATURE_REPORT, rep->field[i]);
+ if (usage->hid == HID_DC_BATTERYSTRENGTH)
+ hidinput_setup_battery(hid, HID_FEATURE_REPORT,
+ rep->field[i]);
if (drv->feature_mapping)
- drv->feature_mapping(hid, rep->field[i],
- rep->field[i]->usage + j);
+ drv->feature_mapping(hid, rep->field[i], usage);
}
}
}
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index 8f3b264..7412286 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -667,10 +667,13 @@ static ssize_t cyc_threshold_store(struct device *dev,
if (kstrtoul(buf, 16, &val))
return -EINVAL;
+
+ /* mask off max threshold before checking min value */
+ val &= ETM_CYC_THRESHOLD_MASK;
if (val < drvdata->ccitmin)
return -EINVAL;
- config->ccctlr = val & ETM_CYC_THRESHOLD_MASK;
+ config->ccctlr = val;
return size;
}
static DEVICE_ATTR_RW(cyc_threshold);
@@ -701,14 +704,16 @@ static ssize_t bb_ctrl_store(struct device *dev,
return -EINVAL;
if (!drvdata->nr_addr_cmp)
return -EINVAL;
+
/*
- * Bit[7:0] selects which address range comparator is used for
- * branch broadcast control.
+ * Bit[8] controls include(1) / exclude(0), bits[0-7] select
+ * individual range comparators. If include then at least 1
+ * range must be selected.
*/
- if (BMVAL(val, 0, 7) > drvdata->nr_addr_cmp)
+ if ((val & BIT(8)) && (BMVAL(val, 0, 7) == 0))
return -EINVAL;
- config->bb_ctrl = val;
+ config->bb_ctrl = val & GENMASK(8, 0);
return size;
}
static DEVICE_ATTR_RW(bb_ctrl);
@@ -1341,8 +1346,8 @@ static ssize_t seq_event_store(struct device *dev,
spin_lock(&drvdata->spinlock);
idx = config->seq_idx;
- /* RST, bits[7:0] */
- config->seq_ctrl[idx] = val & 0xFF;
+ /* Seq control has two masks B[15:8] F[7:0] */
+ config->seq_ctrl[idx] = val & 0xFFFF;
spin_unlock(&drvdata->spinlock);
return size;
}
@@ -1597,7 +1602,7 @@ static ssize_t res_ctrl_store(struct device *dev,
if (idx % 2 != 0)
/* PAIRINV, bit[21] */
val &= ~BIT(21);
- config->res_ctrl[idx] = val;
+ config->res_ctrl[idx] = val & GENMASK(21, 0);
spin_unlock(&drvdata->spinlock);
return size;
}
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index c418830..9c1be93 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -1088,7 +1088,8 @@ static int i2c_imx_probe(struct platform_device *pdev)
/* Get I2C clock */
i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(i2c_imx->clk)) {
- dev_err(&pdev->dev, "can't get I2C clock\n");
+ if (PTR_ERR(i2c_imx->clk) != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "can't get I2C clock\n");
return PTR_ERR(i2c_imx->clk);
}
diff --git a/drivers/iio/adc/max1027.c b/drivers/iio/adc/max1027.c
index 712fbd2..ec3f7bc 100644
--- a/drivers/iio/adc/max1027.c
+++ b/drivers/iio/adc/max1027.c
@@ -471,6 +471,14 @@ static int max1027_probe(struct spi_device *spi)
goto fail_dev_register;
}
+ /* Internal reset */
+ st->reg = MAX1027_RST_REG;
+ ret = spi_write(st->spi, &st->reg, 1);
+ if (ret < 0) {
+ dev_err(&indio_dev->dev, "Failed to reset the ADC\n");
+ return ret;
+ }
+
/* Disable averaging */
st->reg = MAX1027_AVG_REG;
ret = spi_write(st->spi, &st->reg, 1);
diff --git a/drivers/iio/humidity/hdc100x.c b/drivers/iio/humidity/hdc100x.c
index e0c9c70..c0e2e78 100644
--- a/drivers/iio/humidity/hdc100x.c
+++ b/drivers/iio/humidity/hdc100x.c
@@ -202,7 +202,7 @@ static int hdc100x_read_raw(struct iio_dev *indio_dev,
*val2 = 65536;
return IIO_VAL_FRACTIONAL;
} else {
- *val = 100;
+ *val = 100000;
*val2 = 65536;
return IIO_VAL_FRACTIONAL;
}
diff --git a/drivers/iio/imu/adis16480.c b/drivers/iio/imu/adis16480.c
index 6f975538..c950aa1 100644
--- a/drivers/iio/imu/adis16480.c
+++ b/drivers/iio/imu/adis16480.c
@@ -724,6 +724,7 @@ static const struct iio_info adis16480_info = {
.write_raw = &adis16480_write_raw,
.update_scan_mode = adis_update_scan_mode,
.driver_module = THIS_MODULE,
+ .debugfs_reg_access = adis_debugfs_reg_access,
};
static int adis16480_stop_device(struct iio_dev *indio_dev)
diff --git a/drivers/iio/light/bh1750.c b/drivers/iio/light/bh1750.c
index b059466..6d5bb11 100644
--- a/drivers/iio/light/bh1750.c
+++ b/drivers/iio/light/bh1750.c
@@ -62,9 +62,9 @@ struct bh1750_chip_info {
u16 int_time_low_mask;
u16 int_time_high_mask;
-}
+};
-static const bh1750_chip_info_tbl[] = {
+static const struct bh1750_chip_info bh1750_chip_info_tbl[] = {
[BH1710] = { 140, 1022, 300, 400, 250000000, 2, 0x001F, 0x03E0 },
[BH1721] = { 140, 1020, 300, 400, 250000000, 2, 0x0010, 0x03E0 },
[BH1750] = { 31, 254, 69, 1740, 57500000, 1, 0x001F, 0x00E0 },
diff --git a/drivers/infiniband/hw/hns/hns_roce_hem.h b/drivers/infiniband/hw/hns/hns_roce_hem.h
index 4357488..8e8917e 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hem.h
+++ b/drivers/infiniband/hw/hns/hns_roce_hem.h
@@ -52,7 +52,7 @@ enum {
#define HNS_ROCE_HEM_CHUNK_LEN \
((256 - sizeof(struct list_head) - 2 * sizeof(int)) / \
- (sizeof(struct scatterlist)))
+ (sizeof(struct scatterlist) + sizeof(void *)))
enum {
HNS_ROCE_HEM_PAGE_SHIFT = 12,
diff --git a/drivers/infiniband/hw/mlx4/sysfs.c b/drivers/infiniband/hw/mlx4/sysfs.c
index 69fb5ba..19caacd 100644
--- a/drivers/infiniband/hw/mlx4/sysfs.c
+++ b/drivers/infiniband/hw/mlx4/sysfs.c
@@ -352,16 +352,12 @@ static int add_port_entries(struct mlx4_ib_dev *device, int port_num)
static void get_name(struct mlx4_ib_dev *dev, char *name, int i, int max)
{
- char base_name[9];
-
- /* pci_name format is: bus:dev:func -> xxxx:yy:zz.n */
- strlcpy(name, pci_name(dev->dev->persist->pdev), max);
- strncpy(base_name, name, 8); /*till xxxx:yy:*/
- base_name[8] = '\0';
- /* with no ARI only 3 last bits are used so when the fn is higher than 8
+ /* pci_name format is: bus:dev:func -> xxxx:yy:zz.n
+ * with no ARI only 3 last bits are used so when the fn is higher than 8
* need to add it to the dev num, so count in the last number will be
* modulo 8 */
- sprintf(name, "%s%.2d.%d", base_name, (i/8), (i%8));
+ snprintf(name, max, "%.8s%.2d.%d", pci_name(dev->dev->persist->pdev),
+ i / 8, i % 8);
}
struct mlx4_port {
diff --git a/drivers/infiniband/hw/qib/qib_sysfs.c b/drivers/infiniband/hw/qib/qib_sysfs.c
index fe4cf5e..8ce0f6e 100644
--- a/drivers/infiniband/hw/qib/qib_sysfs.c
+++ b/drivers/infiniband/hw/qib/qib_sysfs.c
@@ -301,6 +301,9 @@ static ssize_t qib_portattr_show(struct kobject *kobj,
struct qib_pportdata *ppd =
container_of(kobj, struct qib_pportdata, pport_kobj);
+ if (!pattr->show)
+ return -EIO;
+
return pattr->show(ppd, buf);
}
@@ -312,6 +315,9 @@ static ssize_t qib_portattr_store(struct kobject *kobj,
struct qib_pportdata *ppd =
container_of(kobj, struct qib_pportdata, pport_kobj);
+ if (!pattr->store)
+ return -EIO;
+
return pattr->store(ppd, buf, len);
}
diff --git a/drivers/infiniband/ulp/iser/iscsi_iser.c b/drivers/infiniband/ulp/iser/iscsi_iser.c
index e46e2b0..fdf5179 100644
--- a/drivers/infiniband/ulp/iser/iscsi_iser.c
+++ b/drivers/infiniband/ulp/iser/iscsi_iser.c
@@ -649,6 +649,7 @@ iscsi_iser_session_create(struct iscsi_endpoint *ep,
if (ib_conn->pi_support) {
u32 sig_caps = ib_conn->device->ib_device->attrs.sig_prot_cap;
+ shost->sg_prot_tablesize = shost->sg_tablesize;
scsi_host_set_prot(shost, iser_dif_prot_caps(sig_caps));
scsi_host_set_guard(shost, SHOST_DIX_GUARD_IP |
SHOST_DIX_GUARD_CRC);
diff --git a/drivers/input/sensors/smi130/smi130_acc.c b/drivers/input/sensors/smi130/smi130_acc.c
index a6416e4..8564850 100644
--- a/drivers/input/sensors/smi130/smi130_acc.c
+++ b/drivers/input/sensors/smi130/smi130_acc.c
@@ -1529,7 +1529,7 @@ struct bosch_sensor_data {
};
#ifdef CONFIG_ENABLE_SMI_ACC_GYRO_BUFFERING
-#define SMI_ACC_MAXSAMPLE 4000
+#define SMI_ACC_MAXSAMPLE 5000
#define G_MAX 23920640
struct smi_acc_sample {
int xyz[3];
diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c b/drivers/input/touchscreen/atmel_mxt_ts.c
index c2fb023..8d871fc 100644
--- a/drivers/input/touchscreen/atmel_mxt_ts.c
+++ b/drivers/input/touchscreen/atmel_mxt_ts.c
@@ -3206,6 +3206,8 @@ static int __maybe_unused mxt_suspend(struct device *dev)
mutex_unlock(&input_dev->mutex);
+ disable_irq(data->irq);
+
return 0;
}
@@ -3218,6 +3220,8 @@ static int __maybe_unused mxt_resume(struct device *dev)
if (!input_dev)
return 0;
+ enable_irq(data->irq);
+
mutex_lock(&input_dev->mutex);
if (input_dev->users)
diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
index 44deca8..c1c29d7 100644
--- a/drivers/input/touchscreen/cyttsp4_core.c
+++ b/drivers/input/touchscreen/cyttsp4_core.c
@@ -1972,11 +1972,6 @@ static int cyttsp4_mt_probe(struct cyttsp4 *cd)
/* get sysinfo */
md->si = &cd->sysinfo;
- if (!md->si) {
- dev_err(dev, "%s: Fail get sysinfo pointer from core p=%p\n",
- __func__, md->si);
- goto error_get_sysinfo;
- }
rc = cyttsp4_setup_input_device(cd);
if (rc)
@@ -1986,8 +1981,6 @@ static int cyttsp4_mt_probe(struct cyttsp4 *cd)
error_init_input:
input_free_device(md->input);
-error_get_sysinfo:
- input_set_drvdata(md->input, NULL);
error_alloc_failed:
dev_err(dev, "%s failed.\n", __func__);
return rc;
diff --git a/drivers/input/touchscreen/goodix.c b/drivers/input/touchscreen/goodix.c
index c599b5a..6a02e73 100644
--- a/drivers/input/touchscreen/goodix.c
+++ b/drivers/input/touchscreen/goodix.c
@@ -90,6 +90,15 @@ static const unsigned long goodix_irq_flags[] = {
static const struct dmi_system_id rotated_screen[] = {
#if defined(CONFIG_DMI) && defined(CONFIG_X86)
{
+ .ident = "Teclast X89",
+ .matches = {
+ /* tPAD is too generic, also match on bios date */
+ DMI_MATCH(DMI_BOARD_VENDOR, "TECLAST"),
+ DMI_MATCH(DMI_BOARD_NAME, "tPAD"),
+ DMI_MATCH(DMI_BIOS_DATE, "12/19/2014"),
+ },
+ },
+ {
.ident = "WinBook TW100",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "WinBook"),
diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c
index c4eb293..04cec05 100644
--- a/drivers/iommu/tegra-smmu.c
+++ b/drivers/iommu/tegra-smmu.c
@@ -153,9 +153,9 @@ static bool smmu_dma_addr_valid(struct tegra_smmu *smmu, dma_addr_t addr)
return (addr & smmu->pfn_mask) == addr;
}
-static dma_addr_t smmu_pde_to_dma(u32 pde)
+static dma_addr_t smmu_pde_to_dma(struct tegra_smmu *smmu, u32 pde)
{
- return pde << 12;
+ return (dma_addr_t)(pde & smmu->pfn_mask) << 12;
}
static void smmu_flush_ptc_all(struct tegra_smmu *smmu)
@@ -540,6 +540,7 @@ static u32 *tegra_smmu_pte_lookup(struct tegra_smmu_as *as, unsigned long iova,
dma_addr_t *dmap)
{
unsigned int pd_index = iova_pd_index(iova);
+ struct tegra_smmu *smmu = as->smmu;
struct page *pt_page;
u32 *pd;
@@ -548,7 +549,7 @@ static u32 *tegra_smmu_pte_lookup(struct tegra_smmu_as *as, unsigned long iova,
return NULL;
pd = page_address(as->pd);
- *dmap = smmu_pde_to_dma(pd[pd_index]);
+ *dmap = smmu_pde_to_dma(smmu, pd[pd_index]);
return tegra_smmu_pte_offset(pt_page, iova);
}
@@ -590,7 +591,7 @@ static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova,
} else {
u32 *pd = page_address(as->pd);
- *dmap = smmu_pde_to_dma(pd[pde]);
+ *dmap = smmu_pde_to_dma(smmu, pd[pde]);
}
return tegra_smmu_pte_offset(as->pts[pde], iova);
@@ -615,7 +616,7 @@ static void tegra_smmu_pte_put_use(struct tegra_smmu_as *as, unsigned long iova)
if (--as->count[pde] == 0) {
struct tegra_smmu *smmu = as->smmu;
u32 *pd = page_address(as->pd);
- dma_addr_t pte_dma = smmu_pde_to_dma(pd[pde]);
+ dma_addr_t pte_dma = smmu_pde_to_dma(smmu, pd[pde]);
tegra_smmu_set_pde(as, iova, 0);
diff --git a/drivers/irqchip/irq-bcm7038-l1.c b/drivers/irqchip/irq-bcm7038-l1.c
index 6e24fac..a571d9c 100644
--- a/drivers/irqchip/irq-bcm7038-l1.c
+++ b/drivers/irqchip/irq-bcm7038-l1.c
@@ -282,6 +282,10 @@ static int __init bcm7038_l1_init_one(struct device_node *dn,
pr_err("failed to map parent interrupt %d\n", parent_irq);
return -EINVAL;
}
+
+ if (of_property_read_bool(dn, "brcm,irq-can-wake"))
+ enable_irq_wake(parent_irq);
+
irq_set_chained_handler_and_data(parent_irq, bcm7038_l1_irq_handle,
intc);
diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index fc5953d..b2e16dc 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -117,6 +117,14 @@ static int __init ingenic_intc_of_init(struct device_node *node,
goto out_unmap_irq;
}
+ domain = irq_domain_add_legacy(node, num_chips * 32,
+ JZ4740_IRQ_BASE, 0,
+ &irq_domain_simple_ops, NULL);
+ if (!domain) {
+ err = -ENOMEM;
+ goto out_unmap_base;
+ }
+
for (i = 0; i < num_chips; i++) {
/* Mask all irqs */
writel(0xffffffff, intc->base + (i * CHIP_SIZE) +
@@ -143,14 +151,11 @@ static int __init ingenic_intc_of_init(struct device_node *node,
IRQ_NOPROBE | IRQ_LEVEL);
}
- domain = irq_domain_add_legacy(node, num_chips * 32, JZ4740_IRQ_BASE, 0,
- &irq_domain_simple_ops, NULL);
- if (!domain)
- pr_warn("unable to register IRQ domain\n");
-
setup_irq(parent_irq, &intc_cascade_action);
return 0;
+out_unmap_base:
+ iounmap(intc->base);
out_unmap_irq:
irq_dispose_mapping(parent_irq);
out_free:
diff --git a/drivers/isdn/gigaset/usb-gigaset.c b/drivers/isdn/gigaset/usb-gigaset.c
index 5f306e2..aee4880 100644
--- a/drivers/isdn/gigaset/usb-gigaset.c
+++ b/drivers/isdn/gigaset/usb-gigaset.c
@@ -574,8 +574,7 @@ static int gigaset_initcshw(struct cardstate *cs)
{
struct usb_cardstate *ucs;
- cs->hw.usb = ucs =
- kmalloc(sizeof(struct usb_cardstate), GFP_KERNEL);
+ cs->hw.usb = ucs = kzalloc(sizeof(struct usb_cardstate), GFP_KERNEL);
if (!ucs) {
pr_err("out of memory\n");
return -ENOMEM;
@@ -587,9 +586,6 @@ static int gigaset_initcshw(struct cardstate *cs)
ucs->bchars[3] = 0;
ucs->bchars[4] = 0x11;
ucs->bchars[5] = 0x13;
- ucs->bulk_out_buffer = NULL;
- ucs->bulk_out_urb = NULL;
- ucs->read_urb = NULL;
tasklet_init(&cs->write_tasklet,
gigaset_modem_fill, (unsigned long) cs);
@@ -688,6 +684,11 @@ static int gigaset_probe(struct usb_interface *interface,
return -ENODEV;
}
+ if (hostif->desc.bNumEndpoints < 2) {
+ dev_err(&interface->dev, "missing endpoints\n");
+ return -ENODEV;
+ }
+
dev_info(&udev->dev, "%s: Device matched ... !\n", __func__);
/* allocate memory for our device state and initialize it */
@@ -707,6 +708,12 @@ static int gigaset_probe(struct usb_interface *interface,
endpoint = &hostif->endpoint[0].desc;
+ if (!usb_endpoint_is_bulk_out(endpoint)) {
+ dev_err(&interface->dev, "missing bulk-out endpoint\n");
+ retval = -ENODEV;
+ goto error;
+ }
+
buffer_size = le16_to_cpu(endpoint->wMaxPacketSize);
ucs->bulk_out_size = buffer_size;
ucs->bulk_out_epnum = usb_endpoint_num(endpoint);
@@ -726,6 +733,12 @@ static int gigaset_probe(struct usb_interface *interface,
endpoint = &hostif->endpoint[1].desc;
+ if (!usb_endpoint_is_int_in(endpoint)) {
+ dev_err(&interface->dev, "missing int-in endpoint\n");
+ retval = -ENODEV;
+ goto error;
+ }
+
ucs->busy = 0;
ucs->read_urb = usb_alloc_urb(0, GFP_KERNEL);
diff --git a/drivers/md/bcache/btree.c b/drivers/md/bcache/btree.c
index 4e34afb..c8c5e33 100644
--- a/drivers/md/bcache/btree.c
+++ b/drivers/md/bcache/btree.c
@@ -681,6 +681,8 @@ static unsigned long bch_mca_scan(struct shrinker *shrink,
* IO can always make forward progress:
*/
nr /= c->btree_pages;
+ if (nr == 0)
+ nr = 1;
nr = min_t(unsigned long, nr, mca_can_free(c));
i = 0;
diff --git a/drivers/md/persistent-data/dm-btree-remove.c b/drivers/md/persistent-data/dm-btree-remove.c
index 21ea537..eff04fa 100644
--- a/drivers/md/persistent-data/dm-btree-remove.c
+++ b/drivers/md/persistent-data/dm-btree-remove.c
@@ -203,7 +203,13 @@ static void __rebalance2(struct dm_btree_info *info, struct btree_node *parent,
struct btree_node *right = r->n;
uint32_t nr_left = le32_to_cpu(left->header.nr_entries);
uint32_t nr_right = le32_to_cpu(right->header.nr_entries);
- unsigned threshold = 2 * merge_threshold(left) + 1;
+ /*
+ * Ensure the number of entries in each child will be greater
+ * than or equal to (max_entries / 3 + 1), so no matter which
+ * child is used for removal, the number will still be not
+ * less than (max_entries / 3).
+ */
+ unsigned int threshold = 2 * (merge_threshold(left) + 1);
if (nr_left + nr_right < threshold) {
/*
diff --git a/drivers/media/i2c/ov2659.c b/drivers/media/i2c/ov2659.c
index 3554eea..ade3c48 100644
--- a/drivers/media/i2c/ov2659.c
+++ b/drivers/media/i2c/ov2659.c
@@ -419,10 +419,14 @@ static struct sensor_register ov2659_720p[] = {
{ REG_TIMING_YINC, 0x11 },
{ REG_TIMING_VERT_FORMAT, 0x80 },
{ REG_TIMING_HORIZ_FORMAT, 0x00 },
+ { 0x370a, 0x12 },
{ 0x3a03, 0xe8 },
{ 0x3a09, 0x6f },
{ 0x3a0b, 0x5d },
{ 0x3a15, 0x9a },
+ { REG_VFIFO_READ_START_H, 0x00 },
+ { REG_VFIFO_READ_START_L, 0x80 },
+ { REG_ISP_CTRL02, 0x00 },
{ REG_NULL, 0x00 },
};
@@ -1204,11 +1208,15 @@ static int ov2659_s_stream(struct v4l2_subdev *sd, int on)
goto unlock;
}
- ov2659_set_pixel_clock(ov2659);
- ov2659_set_frame_size(ov2659);
- ov2659_set_format(ov2659);
- ov2659_set_streaming(ov2659, 1);
- ov2659->streaming = on;
+ ret = ov2659_set_pixel_clock(ov2659);
+ if (!ret)
+ ret = ov2659_set_frame_size(ov2659);
+ if (!ret)
+ ret = ov2659_set_format(ov2659);
+ if (!ret) {
+ ov2659_set_streaming(ov2659, 1);
+ ov2659->streaming = on;
+ }
unlock:
mutex_unlock(&ov2659->lock);
diff --git a/drivers/media/i2c/soc_camera/ov6650.c b/drivers/media/i2c/soc_camera/ov6650.c
index fc187c5..7a11946 100644
--- a/drivers/media/i2c/soc_camera/ov6650.c
+++ b/drivers/media/i2c/soc_camera/ov6650.c
@@ -612,7 +612,6 @@ static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
dev_err(&client->dev, "Pixel format not handled: 0x%x\n", code);
return -EINVAL;
}
- priv->code = code;
if (code == MEDIA_BUS_FMT_Y8_1X8 ||
code == MEDIA_BUS_FMT_SBGGR8_1X8) {
@@ -638,7 +637,6 @@ static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
dev_dbg(&client->dev, "max resolution: CIF\n");
coma_mask |= COMA_QCIF;
}
- priv->half_scale = half_scale;
if (sense) {
if (sense->master_clock == 8000000) {
@@ -678,8 +676,13 @@ static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask);
if (!ret)
ret = ov6650_reg_write(client, REG_CLKRC, clkrc);
- if (!ret)
+ if (!ret) {
+ priv->half_scale = half_scale;
+
ret = ov6650_reg_rmw(client, REG_COML, coml_set, coml_mask);
+ }
+ if (!ret)
+ priv->code = code;
if (!ret) {
mf->colorspace = priv->colorspace;
diff --git a/drivers/media/platform/am437x/am437x-vpfe.c b/drivers/media/platform/am437x/am437x-vpfe.c
index 05489a4..bd500f1 100644
--- a/drivers/media/platform/am437x/am437x-vpfe.c
+++ b/drivers/media/platform/am437x/am437x-vpfe.c
@@ -1847,6 +1847,10 @@ static int vpfe_s_std(struct file *file, void *priv, v4l2_std_id std_id)
if (!(sdinfo->inputs[0].capabilities & V4L2_IN_CAP_STD))
return -ENODATA;
+ /* if trying to set the same std then nothing to do */
+ if (vpfe_standards[vpfe->std_index].std_id == std_id)
+ return 0;
+
/* If streaming is started, return error */
if (vb2_is_busy(&vpfe->buffer_queue)) {
vpfe_err(vpfe, "%s device busy\n", __func__);
diff --git a/drivers/media/platform/sti/bdisp/bdisp-v4l2.c b/drivers/media/platform/sti/bdisp/bdisp-v4l2.c
index 45f82b5..d88c9ba 100644
--- a/drivers/media/platform/sti/bdisp/bdisp-v4l2.c
+++ b/drivers/media/platform/sti/bdisp/bdisp-v4l2.c
@@ -651,8 +651,7 @@ static int bdisp_release(struct file *file)
dev_dbg(bdisp->dev, "%s\n", __func__);
- if (mutex_lock_interruptible(&bdisp->lock))
- return -ERESTARTSYS;
+ mutex_lock(&bdisp->lock);
v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
diff --git a/drivers/media/platform/ti-vpe/vpe.c b/drivers/media/platform/ti-vpe/vpe.c
index 0189f7f..dbb4829 100644
--- a/drivers/media/platform/ti-vpe/vpe.c
+++ b/drivers/media/platform/ti-vpe/vpe.c
@@ -330,20 +330,25 @@ enum {
};
/* find our format description corresponding to the passed v4l2_format */
-static struct vpe_fmt *find_format(struct v4l2_format *f)
+static struct vpe_fmt *__find_format(u32 fourcc)
{
struct vpe_fmt *fmt;
unsigned int k;
for (k = 0; k < ARRAY_SIZE(vpe_formats); k++) {
fmt = &vpe_formats[k];
- if (fmt->fourcc == f->fmt.pix.pixelformat)
+ if (fmt->fourcc == fourcc)
return fmt;
}
return NULL;
}
+static struct vpe_fmt *find_format(struct v4l2_format *f)
+{
+ return __find_format(f->fmt.pix.pixelformat);
+}
+
/*
* there is one vpe_dev structure in the driver, it is shared by
* all instances.
@@ -1293,6 +1298,7 @@ static irqreturn_t vpe_irq(int irq_vpe, void *data)
d_vb->timecode = s_vb->timecode;
d_vb->sequence = ctx->sequence;
+ s_vb->sequence = ctx->sequence;
d_q_data = &ctx->q_data[Q_DATA_DST];
if (d_q_data->flags & Q_DATA_INTERLACED) {
@@ -1433,9 +1439,9 @@ static int __vpe_try_fmt(struct vpe_ctx *ctx, struct v4l2_format *f,
int i, depth, depth_bytes;
if (!fmt || !(fmt->types & type)) {
- vpe_err(ctx->dev, "Fourcc format (0x%08x) invalid.\n",
+ vpe_dbg(ctx->dev, "Fourcc format (0x%08x) invalid.\n",
pix->pixelformat);
- return -EINVAL;
+ fmt = __find_format(V4L2_PIX_FMT_YUYV);
}
if (pix->field != V4L2_FIELD_NONE && pix->field != V4L2_FIELD_ALTERNATE)
@@ -1992,7 +1998,7 @@ static int vpe_open(struct file *file)
v4l2_ctrl_handler_setup(hdl);
s_q_data = &ctx->q_data[Q_DATA_SRC];
- s_q_data->fmt = &vpe_formats[2];
+ s_q_data->fmt = __find_format(V4L2_PIX_FMT_YUYV);
s_q_data->width = 1920;
s_q_data->height = 1080;
s_q_data->bytesperline[VPE_LUMA] = (s_q_data->width *
diff --git a/drivers/media/radio/radio-wl1273.c b/drivers/media/radio/radio-wl1273.c
index a93f681..6426b07 100644
--- a/drivers/media/radio/radio-wl1273.c
+++ b/drivers/media/radio/radio-wl1273.c
@@ -1149,8 +1149,7 @@ static int wl1273_fm_fops_release(struct file *file)
if (radio->rds_users > 0) {
radio->rds_users--;
if (radio->rds_users == 0) {
- if (mutex_lock_interruptible(&core->lock))
- return -EINTR;
+ mutex_lock(&core->lock);
radio->irq_flags &= ~WL1273_RDS_EVENT;
diff --git a/drivers/media/radio/si470x/radio-si470x-i2c.c b/drivers/media/radio/si470x/radio-si470x-i2c.c
index f218886..fb69534 100644
--- a/drivers/media/radio/si470x/radio-si470x-i2c.c
+++ b/drivers/media/radio/si470x/radio-si470x-i2c.c
@@ -460,6 +460,8 @@ static int si470x_i2c_remove(struct i2c_client *client)
video_unregister_device(&radio->videodev);
kfree(radio);
+ v4l2_ctrl_handler_free(&radio->hdl);
+ v4l2_device_unregister(&radio->v4l2_dev);
return 0;
}
diff --git a/drivers/media/usb/b2c2/flexcop-usb.c b/drivers/media/usb/b2c2/flexcop-usb.c
index 1fc3c8d..2594d6a 100644
--- a/drivers/media/usb/b2c2/flexcop-usb.c
+++ b/drivers/media/usb/b2c2/flexcop-usb.c
@@ -504,7 +504,13 @@ static int flexcop_usb_transfer_init(struct flexcop_usb *fc_usb)
static int flexcop_usb_init(struct flexcop_usb *fc_usb)
{
/* use the alternate setting with the larges buffer */
- usb_set_interface(fc_usb->udev,0,1);
+ int ret = usb_set_interface(fc_usb->udev, 0, 1);
+
+ if (ret) {
+ err("set interface failed.");
+ return ret;
+ }
+
switch (fc_usb->udev->speed) {
case USB_SPEED_LOW:
err("cannot handle USB speed because it is too slow.");
diff --git a/drivers/media/usb/pvrusb2/pvrusb2-v4l2.c b/drivers/media/usb/pvrusb2/pvrusb2-v4l2.c
index 2cc4d2b..d18ced2 100644
--- a/drivers/media/usb/pvrusb2/pvrusb2-v4l2.c
+++ b/drivers/media/usb/pvrusb2/pvrusb2-v4l2.c
@@ -919,8 +919,12 @@ static void pvr2_v4l2_internal_check(struct pvr2_channel *chp)
pvr2_v4l2_dev_disassociate_parent(vp->dev_video);
pvr2_v4l2_dev_disassociate_parent(vp->dev_radio);
if (!list_empty(&vp->dev_video->devbase.fh_list) ||
- !list_empty(&vp->dev_radio->devbase.fh_list))
+ (vp->dev_radio &&
+ !list_empty(&vp->dev_radio->devbase.fh_list))) {
+ pvr2_trace(PVR2_TRACE_STRUCT,
+ "pvr2_v4l2 internal_check exit-empty id=%p", vp);
return;
+ }
pvr2_v4l2_destroy_no_lock(vp);
}
@@ -994,7 +998,8 @@ static int pvr2_v4l2_release(struct file *file)
kfree(fhp);
if (vp->channel.mc_head->disconnect_flag &&
list_empty(&vp->dev_video->devbase.fh_list) &&
- list_empty(&vp->dev_radio->devbase.fh_list)) {
+ (!vp->dev_radio ||
+ list_empty(&vp->dev_radio->devbase.fh_list))) {
pvr2_v4l2_destroy_no_lock(vp);
}
return 0;
diff --git a/drivers/media/usb/stkwebcam/stk-webcam.c b/drivers/media/usb/stkwebcam/stk-webcam.c
index 7297fd2..f9844f8 100644
--- a/drivers/media/usb/stkwebcam/stk-webcam.c
+++ b/drivers/media/usb/stkwebcam/stk-webcam.c
@@ -166,7 +166,11 @@ int stk_camera_read_reg(struct stk_camera *dev, u16 index, u8 *value)
*value = *buf;
kfree(buf);
- return ret;
+
+ if (ret < 0)
+ return ret;
+ else
+ return 0;
}
static int stk_start_stream(struct stk_camera *dev)
diff --git a/drivers/misc/altera-stapl/altera.c b/drivers/misc/altera-stapl/altera.c
index f53e217..494e263 100644
--- a/drivers/misc/altera-stapl/altera.c
+++ b/drivers/misc/altera-stapl/altera.c
@@ -2176,8 +2176,7 @@ static int altera_get_note(u8 *p, s32 program_size,
key_ptr = &p[note_strings +
get_unaligned_be32(
&p[note_table + (8 * i)])];
- if ((strncasecmp(key, key_ptr, strlen(key_ptr)) == 0) &&
- (key != NULL)) {
+ if (key && !strncasecmp(key, key_ptr, strlen(key_ptr))) {
status = 0;
value_ptr = &p[note_strings +
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 009242b..65c0742 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -1700,6 +1700,36 @@ static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
if (mmc_pdata(host)->init_card)
mmc_pdata(host)->init_card(card);
+ else if (card->type == MMC_TYPE_SDIO ||
+ card->type == MMC_TYPE_SD_COMBO) {
+ struct device_node *np = mmc_dev(mmc)->of_node;
+
+ /*
+ * REVISIT: should be moved to sdio core and made more
+ * general e.g. by expanding the DT bindings of child nodes
+ * to provide a mechanism to provide this information:
+ * Documentation/devicetree/bindings/mmc/mmc-card.txt
+ */
+
+ np = of_get_compatible_child(np, "ti,wl1251");
+ if (np) {
+ /*
+ * We have TI wl1251 attached to MMC3. Pass this
+ * information to the SDIO core because it can't be
+ * probed by normal methods.
+ */
+
+ dev_info(host->dev, "found wl1251\n");
+ card->quirks |= MMC_QUIRK_NONSTD_SDIO;
+ card->cccr.wide_bus = 1;
+ card->cis.vendor = 0x104c;
+ card->cis.device = 0x9066;
+ card->cis.blksize = 512;
+ card->cis.max_dtr = 24000000;
+ card->ocr = 0x80;
+ of_node_put(np);
+ }
+ }
}
static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
index 6f11cd95..225ecab 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -637,8 +637,8 @@ static int sdhci_esdhc_probe(struct platform_device *pdev)
host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) {
- host->quirks2 |= SDHCI_QUIRK_RESET_AFTER_REQUEST;
- host->quirks2 |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
+ host->quirks |= SDHCI_QUIRK_RESET_AFTER_REQUEST;
+ host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
}
if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 50f6b00..6d8822b 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1929,9 +1929,7 @@ void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
else if (timing == MMC_TIMING_UHS_SDR12)
ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
- else if (timing == MMC_TIMING_SD_HS ||
- timing == MMC_TIMING_MMC_HS ||
- timing == MMC_TIMING_UHS_SDR25)
+ else if (timing == MMC_TIMING_UHS_SDR25)
ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
else if (timing == MMC_TIMING_UHS_SDR50)
ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
@@ -2580,7 +2578,7 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
spin_lock_irqsave(&host->lock, flags);
if (!host->tuning_done) {
- pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
+ pr_debug(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl &= ~SDHCI_CTRL_TUNED_CLK;
ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c
index 0fc1f73..3e02576 100644
--- a/drivers/mmc/host/tmio_mmc_pio.c
+++ b/drivers/mmc/host/tmio_mmc_pio.c
@@ -1076,7 +1076,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
tmio_mmc_ops.start_signal_voltage_switch = _host->start_signal_voltage_switch;
mmc->ops = &tmio_mmc_ops;
- mmc->caps |= MMC_CAP_4_BIT_DATA | pdata->capabilities;
+ mmc->caps |= MMC_CAP_ERASE | MMC_CAP_4_BIT_DATA | pdata->capabilities;
mmc->caps2 |= pdata->capabilities2;
mmc->max_segs = 32;
mmc->max_blk_size = 512;
diff --git a/drivers/mtd/devices/spear_smi.c b/drivers/mtd/devices/spear_smi.c
index dd50698..4a7da5f 100644
--- a/drivers/mtd/devices/spear_smi.c
+++ b/drivers/mtd/devices/spear_smi.c
@@ -595,6 +595,26 @@ static int spear_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
return 0;
}
+/*
+ * The purpose of this function is to ensure a memcpy_toio() with byte writes
+ * only. Its structure is inspired from the ARM implementation of _memcpy_toio()
+ * which also does single byte writes but cannot be used here as this is just an
+ * implementation detail and not part of the API. Not mentioning the comment
+ * stating that _memcpy_toio() should be optimized.
+ */
+static void spear_smi_memcpy_toio_b(volatile void __iomem *dest,
+ const void *src, size_t len)
+{
+ const unsigned char *from = src;
+
+ while (len) {
+ len--;
+ writeb(*from, dest);
+ from++;
+ dest++;
+ }
+}
+
static inline int spear_smi_cpy_toio(struct spear_smi *dev, u32 bank,
void __iomem *dest, const void *src, size_t len)
{
@@ -617,7 +637,23 @@ static inline int spear_smi_cpy_toio(struct spear_smi *dev, u32 bank,
ctrlreg1 = readl(dev->io_base + SMI_CR1);
writel((ctrlreg1 | WB_MODE) & ~SW_MODE, dev->io_base + SMI_CR1);
- memcpy_toio(dest, src, len);
+ /*
+ * In Write Burst mode (WB_MODE), the specs states that writes must be:
+ * - incremental
+ * - of the same size
+ * The ARM implementation of memcpy_toio() will optimize the number of
+ * I/O by using as much 4-byte writes as possible, surrounded by
+ * 2-byte/1-byte access if:
+ * - the destination is not 4-byte aligned
+ * - the length is not a multiple of 4-byte.
+ * Avoid this alternance of write access size by using our own 'byte
+ * access' helper if at least one of the two conditions above is true.
+ */
+ if (IS_ALIGNED(len, sizeof(u32)) &&
+ IS_ALIGNED((uintptr_t)dest, sizeof(u32)))
+ memcpy_toio(dest, src, len);
+ else
+ spear_smi_memcpy_toio_b(dest, src, len);
writel(ctrlreg1, dev->io_base + SMI_CR1);
diff --git a/drivers/net/can/slcan.c b/drivers/net/can/slcan.c
index a2c4048..0204379 100644
--- a/drivers/net/can/slcan.c
+++ b/drivers/net/can/slcan.c
@@ -613,6 +613,7 @@ static int slcan_open(struct tty_struct *tty)
sl->tty = NULL;
tty->disc_data = NULL;
clear_bit(SLF_INUSE, &sl->flags);
+ slc_free_netdev(sl->dev);
free_netdev(sl->dev);
err_exit:
diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c
index 0780900..961f31c8 100644
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.c
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c
@@ -1105,8 +1105,8 @@ static int ena_io_poll(struct napi_struct *napi, int budget)
struct ena_ring *tx_ring, *rx_ring;
struct ena_eth_io_intr_reg intr_reg;
- u32 tx_work_done;
- u32 rx_work_done;
+ int tx_work_done;
+ int rx_work_done = 0;
int tx_budget;
int napi_comp_call = 0;
int ret;
@@ -1122,7 +1122,11 @@ static int ena_io_poll(struct napi_struct *napi, int budget)
}
tx_work_done = ena_clean_tx_irq(tx_ring, tx_budget);
- rx_work_done = ena_clean_rx_irq(rx_ring, napi, budget);
+ /* On netpoll the budget is zero and the handler should only clean the
+ * tx completions.
+ */
+ if (likely(budget))
+ rx_work_done = ena_clean_rx_irq(rx_ring, napi, budget);
if ((budget > rx_work_done) && (tx_budget > tx_work_done)) {
napi_complete_done(napi, rx_work_done);
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c
index c6e0591..e8a09d0 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c
@@ -2376,15 +2376,21 @@ static int bnx2x_set_pf_tx_switching(struct bnx2x *bp, bool enable)
/* send the ramrod on all the queues of the PF */
for_each_eth_queue(bp, i) {
struct bnx2x_fastpath *fp = &bp->fp[i];
+ int tx_idx;
/* Set the appropriate Queue object */
q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
- /* Update the Queue state */
- rc = bnx2x_queue_state_change(bp, &q_params);
- if (rc) {
- BNX2X_ERR("Failed to configure Tx switching\n");
- return rc;
+ for (tx_idx = FIRST_TX_COS_INDEX;
+ tx_idx < fp->max_cos; tx_idx++) {
+ q_params.params.update.cid_index = tx_idx;
+
+ /* Update the Queue state */
+ rc = bnx2x_queue_state_change(bp, &q_params);
+ if (rc) {
+ BNX2X_ERR("Failed to configure Tx switching\n");
+ return rc;
+ }
}
}
diff --git a/drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c b/drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
index a37481c..9eb3071 100644
--- a/drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
@@ -718,6 +718,10 @@ static int adapter_up(struct adapter *adapter)
if (adapter->flags & USING_MSIX)
name_msix_vecs(adapter);
+
+ /* Initialize hash mac addr list*/
+ INIT_LIST_HEAD(&adapter->mac_hlist);
+
adapter->flags |= FULL_INIT_DONE;
}
@@ -743,8 +747,6 @@ static int adapter_up(struct adapter *adapter)
enable_rx(adapter);
t4vf_sge_start(adapter);
- /* Initialize hash mac addr list*/
- INIT_LIST_HEAD(&adapter->mac_hlist);
return 0;
}
diff --git a/drivers/net/ethernet/cirrus/ep93xx_eth.c b/drivers/net/ethernet/cirrus/ep93xx_eth.c
index 9a161e9..24f6903 100644
--- a/drivers/net/ethernet/cirrus/ep93xx_eth.c
+++ b/drivers/net/ethernet/cirrus/ep93xx_eth.c
@@ -780,6 +780,7 @@ static int ep93xx_eth_remove(struct platform_device *pdev)
{
struct net_device *dev;
struct ep93xx_priv *ep;
+ struct resource *mem;
dev = platform_get_drvdata(pdev);
if (dev == NULL)
@@ -795,8 +796,8 @@ static int ep93xx_eth_remove(struct platform_device *pdev)
iounmap(ep->base_addr);
if (ep->res != NULL) {
- release_resource(ep->res);
- kfree(ep->res);
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ release_mem_region(mem->start, resource_size(mem));
}
free_netdev(dev);
diff --git a/drivers/net/ethernet/hisilicon/hip04_eth.c b/drivers/net/ethernet/hisilicon/hip04_eth.c
index 4436a03..0b3aa83 100644
--- a/drivers/net/ethernet/hisilicon/hip04_eth.c
+++ b/drivers/net/ethernet/hisilicon/hip04_eth.c
@@ -455,9 +455,9 @@ static int hip04_mac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
skb_tx_timestamp(skb);
hip04_set_xmit_desc(priv, phys);
- priv->tx_head = TX_NEXT(tx_head);
count++;
netdev_sent_queue(ndev, skb->len);
+ priv->tx_head = TX_NEXT(tx_head);
stats->tx_bytes += skb->len;
stats->tx_packets++;
diff --git a/drivers/net/ethernet/intel/e100.c b/drivers/net/ethernet/intel/e100.c
index 068789e..93c2909 100644
--- a/drivers/net/ethernet/intel/e100.c
+++ b/drivers/net/ethernet/intel/e100.c
@@ -1370,8 +1370,8 @@ static inline int e100_load_ucode_wait(struct nic *nic)
fw = e100_request_firmware(nic);
/* If it's NULL, then no ucode is required */
- if (!fw || IS_ERR(fw))
- return PTR_ERR(fw);
+ if (IS_ERR_OR_NULL(fw))
+ return PTR_ERR_OR_ZERO(fw);
if ((err = e100_exec_cb(nic, (void *)fw, e100_setup_ucode)))
netif_err(nic, probe, nic->netdev,
diff --git a/drivers/net/ethernet/mellanox/mlx4/main.c b/drivers/net/ethernet/mellanox/mlx4/main.c
index cb7c3ef..781642d 100644
--- a/drivers/net/ethernet/mellanox/mlx4/main.c
+++ b/drivers/net/ethernet/mellanox/mlx4/main.c
@@ -198,7 +198,7 @@ int mlx4_check_port_params(struct mlx4_dev *dev,
for (i = 0; i < dev->caps.num_ports - 1; i++) {
if (port_type[i] != port_type[i + 1]) {
mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
- return -EINVAL;
+ return -EOPNOTSUPP;
}
}
}
@@ -207,7 +207,7 @@ int mlx4_check_port_params(struct mlx4_dev *dev,
if (!(port_type[i] & dev->caps.supported_type[i+1])) {
mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
i + 1);
- return -EINVAL;
+ return -EOPNOTSUPP;
}
}
return 0;
@@ -1122,8 +1122,7 @@ static int __set_port_type(struct mlx4_port_info *info,
mlx4_err(mdev,
"Requested port type for port %d is not supported on this HCA\n",
info->port);
- err = -EINVAL;
- goto err_sup;
+ return -EOPNOTSUPP;
}
mlx4_stop_sense(mdev);
@@ -1145,7 +1144,7 @@ static int __set_port_type(struct mlx4_port_info *info,
for (i = 1; i <= mdev->caps.num_ports; i++) {
if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
mdev->caps.possible_type[i] = mdev->caps.port_type[i];
- err = -EINVAL;
+ err = -EOPNOTSUPP;
}
}
}
@@ -1171,7 +1170,7 @@ static int __set_port_type(struct mlx4_port_info *info,
out:
mlx4_start_sense(mdev);
mutex_unlock(&priv->port_mutex);
-err_sup:
+
return err;
}
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
index e42ece2..e13a6cd 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
@@ -1368,7 +1368,7 @@ static int mlx5e_get_module_info(struct net_device *netdev,
break;
case MLX5_MODULE_ID_SFP:
modinfo->type = ETH_MODULE_SFF_8472;
- modinfo->eeprom_len = MLX5_EEPROM_PAGE_LENGTH;
+ modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
break;
default:
netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/qp.c b/drivers/net/ethernet/mellanox/mlx5/core/qp.c
index 9346f39..354338c 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/qp.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/qp.c
@@ -125,7 +125,7 @@ void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type)
if (!is_event_type_allowed((rsn >> MLX5_USER_INDEX_LEN), event_type)) {
mlx5_core_warn(dev, "event 0x%.2x is not allowed on resource 0x%.8x\n",
event_type, rsn);
- return;
+ goto out;
}
switch (common->res) {
@@ -139,7 +139,7 @@ void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type)
default:
mlx5_core_warn(dev, "invalid resource type for 0x%x\n", rsn);
}
-
+out:
mlx5_core_put_rsc(common);
}
diff --git a/drivers/net/ethernet/qlogic/qla3xxx.c b/drivers/net/ethernet/qlogic/qla3xxx.c
index c653b97..f2cb77c 100644
--- a/drivers/net/ethernet/qlogic/qla3xxx.c
+++ b/drivers/net/ethernet/qlogic/qla3xxx.c
@@ -2752,6 +2752,9 @@ static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
int err;
for (i = 0; i < qdev->num_large_buffers; i++) {
+ lrg_buf_cb = &qdev->lrg_buf[i];
+ memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
+
skb = netdev_alloc_skb(qdev->ndev,
qdev->lrg_buffer_len);
if (unlikely(!skb)) {
@@ -2762,11 +2765,7 @@ static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
ql_free_large_buffers(qdev);
return -ENOMEM;
} else {
-
- lrg_buf_cb = &qdev->lrg_buf[i];
- memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
lrg_buf_cb->index = i;
- lrg_buf_cb->skb = skb;
/*
* We save some space to copy the ethhdr from first
* buffer
@@ -2788,6 +2787,7 @@ static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
return -ENOMEM;
}
+ lrg_buf_cb->skb = skb;
dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
dma_unmap_len_set(lrg_buf_cb, maplen,
qdev->lrg_buffer_len -
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index 6d2de4e..e11920d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -354,7 +354,7 @@ struct dma_features {
struct stmmac_desc_ops {
/* DMA RX descriptor ring initialization */
void (*init_rx_desc) (struct dma_desc *p, int disable_rx_ic, int mode,
- int end);
+ int end, int bfsize);
/* DMA TX descriptor ring initialization */
void (*init_tx_desc) (struct dma_desc *p, int mode, int end);
diff --git a/drivers/net/ethernet/stmicro/stmmac/descs_com.h b/drivers/net/ethernet/stmicro/stmmac/descs_com.h
index 1d181e2..f9cbba2 100644
--- a/drivers/net/ethernet/stmicro/stmmac/descs_com.h
+++ b/drivers/net/ethernet/stmicro/stmmac/descs_com.h
@@ -33,11 +33,14 @@
/* Specific functions used for Ring mode */
/* Enhanced descriptors */
-static inline void ehn_desc_rx_set_on_ring(struct dma_desc *p, int end)
+static inline void ehn_desc_rx_set_on_ring(struct dma_desc *p, int end,
+ int bfsize)
{
- p->des1 |= cpu_to_le32(((BUF_SIZE_8KiB - 1)
- << ERDES1_BUFFER2_SIZE_SHIFT)
- & ERDES1_BUFFER2_SIZE_MASK);
+ if (bfsize == BUF_SIZE_16KiB)
+ p->des1 |= cpu_to_le32((BUF_SIZE_8KiB
+ << ERDES1_BUFFER2_SIZE_SHIFT)
+ & ERDES1_BUFFER2_SIZE_MASK);
+
if (end)
p->des1 |= cpu_to_le32(ERDES1_END_RING);
@@ -63,11 +66,15 @@ static inline void enh_set_tx_desc_len_on_ring(struct dma_desc *p, int len)
}
/* Normal descriptors */
-static inline void ndesc_rx_set_on_ring(struct dma_desc *p, int end)
+static inline void ndesc_rx_set_on_ring(struct dma_desc *p, int end, int bfsize)
{
- p->des1 |= cpu_to_le32(((BUF_SIZE_2KiB - 1)
- << RDES1_BUFFER2_SIZE_SHIFT)
- & RDES1_BUFFER2_SIZE_MASK);
+ if (bfsize >= BUF_SIZE_2KiB) {
+ int bfsize2;
+
+ bfsize2 = min(bfsize - BUF_SIZE_2KiB + 1, BUF_SIZE_2KiB - 1);
+ p->des1 |= cpu_to_le32((bfsize2 << RDES1_BUFFER2_SIZE_SHIFT)
+ & RDES1_BUFFER2_SIZE_MASK);
+ }
if (end)
p->des1 |= cpu_to_le32(RDES1_END_RING);
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
index 3f50568..a90b029 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
@@ -289,7 +289,7 @@ static int dwmac4_wrback_get_rx_timestamp_status(void *desc, u32 ats)
}
static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
- int mode, int end)
+ int mode, int end, int bfsize)
{
p->des3 = cpu_to_le32(RDES3_OWN | RDES3_BUFFER1_VALID_ADDR);
diff --git a/drivers/net/ethernet/stmicro/stmmac/enh_desc.c b/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
index 77dc584..47f4fe5 100644
--- a/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
+++ b/drivers/net/ethernet/stmicro/stmmac/enh_desc.c
@@ -269,15 +269,19 @@ static int enh_desc_get_rx_status(void *data, struct stmmac_extra_stats *x,
}
static void enh_desc_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
- int mode, int end)
+ int mode, int end, int bfsize)
{
+ int bfsize1;
+
p->des0 |= cpu_to_le32(RDES0_OWN);
- p->des1 |= cpu_to_le32((BUF_SIZE_8KiB - 1) & ERDES1_BUFFER1_SIZE_MASK);
+
+ bfsize1 = min(bfsize, BUF_SIZE_8KiB);
+ p->des1 |= cpu_to_le32(bfsize1 & ERDES1_BUFFER1_SIZE_MASK);
if (mode == STMMAC_CHAIN_MODE)
ehn_desc_rx_set_on_chain(p);
else
- ehn_desc_rx_set_on_ring(p, end);
+ ehn_desc_rx_set_on_ring(p, end, bfsize);
if (disable_rx_ic)
p->des1 |= cpu_to_le32(ERDES1_DISABLE_IC);
diff --git a/drivers/net/ethernet/stmicro/stmmac/norm_desc.c b/drivers/net/ethernet/stmicro/stmmac/norm_desc.c
index 01f8f2e..5a06a5a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/norm_desc.c
+++ b/drivers/net/ethernet/stmicro/stmmac/norm_desc.c
@@ -137,15 +137,19 @@ static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,
}
static void ndesc_init_rx_desc(struct dma_desc *p, int disable_rx_ic, int mode,
- int end)
+ int end, int bfsize)
{
+ int bfsize1;
+
p->des0 |= cpu_to_le32(RDES0_OWN);
- p->des1 |= cpu_to_le32((BUF_SIZE_2KiB - 1) & RDES1_BUFFER1_SIZE_MASK);
+
+ bfsize1 = min(bfsize, BUF_SIZE_2KiB - 1);
+ p->des1 |= cpu_to_le32(bfsize1 & RDES1_BUFFER1_SIZE_MASK);
if (mode == STMMAC_CHAIN_MODE)
ndesc_rx_set_on_chain(p, end);
else
- ndesc_rx_set_on_ring(p, end);
+ ndesc_rx_set_on_ring(p, end, bfsize);
if (disable_rx_ic)
p->des1 |= cpu_to_le32(RDES1_DISABLE_IC);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 2c04a07..5ac48a5 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -956,11 +956,11 @@ static void stmmac_clear_descriptors(struct stmmac_priv *priv)
if (priv->extend_desc)
priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
priv->use_riwt, priv->mode,
- (i == DMA_RX_SIZE - 1));
+ (i == DMA_RX_SIZE - 1), priv->dma_buf_sz);
else
priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
priv->use_riwt, priv->mode,
- (i == DMA_RX_SIZE - 1));
+ (i == DMA_RX_SIZE - 1), priv->dma_buf_sz);
for (i = 0; i < DMA_TX_SIZE; i++)
if (priv->extend_desc)
priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
@@ -2479,7 +2479,7 @@ static inline void stmmac_rx_refill(struct stmmac_priv *priv)
wmb();
if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
- priv->hw->desc->init_rx_desc(p, priv->use_riwt, 0, 0);
+ priv->hw->desc->init_rx_desc(p, priv->use_riwt, 0, 0, priv->dma_buf_sz);
else
priv->hw->desc->set_rx_owner(p);
@@ -2499,8 +2499,7 @@ static inline void stmmac_rx_refill(struct stmmac_priv *priv)
*/
static int stmmac_rx(struct stmmac_priv *priv, int limit)
{
- unsigned int entry = priv->cur_rx;
- unsigned int next_entry;
+ unsigned int next_entry = priv->cur_rx;
unsigned int count = 0;
int coe = priv->hw->rx_csum;
@@ -2516,10 +2515,12 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit)
priv->hw->desc->display_ring(rx_head, DMA_RX_SIZE, true);
}
while (count < limit) {
- int status;
+ int entry, status;
struct dma_desc *p;
struct dma_desc *np;
+ entry = next_entry;
+
if (priv->extend_desc)
p = (struct dma_desc *)(priv->dma_erx + entry);
else
@@ -2584,7 +2585,7 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit)
priv->dev->name, frame_len,
priv->dma_buf_sz);
priv->dev->stats.rx_length_errors++;
- break;
+ continue;
}
/* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
@@ -2615,7 +2616,7 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit)
dev_warn(priv->device,
"packet dropped\n");
priv->dev->stats.rx_dropped++;
- break;
+ continue;
}
dma_sync_single_for_cpu(priv->device,
@@ -2638,7 +2639,7 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit)
pr_err("%s: Inconsistent Rx chain\n",
priv->dev->name);
priv->dev->stats.rx_dropped++;
- break;
+ continue;
}
prefetch(skb->data - NET_IP_ALIGN);
priv->rx_skbuff[entry] = NULL;
@@ -2672,7 +2673,6 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit)
priv->dev->stats.rx_packets++;
priv->dev->stats.rx_bytes += frame_len;
}
- entry = next_entry;
}
stmmac_rx_refill(priv);
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 892b068..687f0c20 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -773,8 +773,8 @@ static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
{
struct cpsw_common *cpsw = dev_id;
- cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
writel(0, &cpsw->wr_regs->rx_en);
+ cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
if (cpsw->quirk_irq) {
disable_irq_nosync(cpsw->irqs_table[0]);
diff --git a/drivers/net/fjes/fjes_main.c b/drivers/net/fjes/fjes_main.c
index bbc983b..3511d40 100644
--- a/drivers/net/fjes/fjes_main.c
+++ b/drivers/net/fjes/fjes_main.c
@@ -148,6 +148,9 @@ static int fjes_acpi_add(struct acpi_device *device)
/* create platform_device */
plat_dev = platform_device_register_simple(DRV_NAME, 0, fjes_resource,
ARRAY_SIZE(fjes_resource));
+ if (IS_ERR(plat_dev))
+ return PTR_ERR(plat_dev);
+
device->driver_data = plat_dev;
return 0;
diff --git a/drivers/net/gtp.c b/drivers/net/gtp.c
index 7e1df40..c289871 100644
--- a/drivers/net/gtp.c
+++ b/drivers/net/gtp.c
@@ -42,7 +42,6 @@ struct pdp_ctx {
struct hlist_node hlist_addr;
union {
- u64 tid;
struct {
u64 tid;
u16 flow;
@@ -678,10 +677,13 @@ static int gtp_newlink(struct net *src_net, struct net_device *dev,
if (err < 0)
goto out_err;
- if (!data[IFLA_GTP_PDP_HASHSIZE])
+ if (!data[IFLA_GTP_PDP_HASHSIZE]) {
hashsize = 1024;
- else
+ } else {
hashsize = nla_get_u32(data[IFLA_GTP_PDP_HASHSIZE]);
+ if (!hashsize)
+ hashsize = 1024;
+ }
err = gtp_hashtable_new(gtp, hashsize);
if (err < 0)
@@ -1221,43 +1223,46 @@ static int gtp_genl_dump_pdp(struct sk_buff *skb,
struct netlink_callback *cb)
{
struct gtp_dev *last_gtp = (struct gtp_dev *)cb->args[2], *gtp;
+ int i, j, bucket = cb->args[0], skip = cb->args[1];
struct net *net = sock_net(skb->sk);
- struct gtp_net *gn = net_generic(net, gtp_net_id);
- unsigned long tid = cb->args[1];
- int i, k = cb->args[0], ret;
struct pdp_ctx *pctx;
+ struct gtp_net *gn;
+
+ gn = net_generic(net, gtp_net_id);
if (cb->args[4])
return 0;
+ rcu_read_lock();
list_for_each_entry_rcu(gtp, &gn->gtp_dev_list, list) {
if (last_gtp && last_gtp != gtp)
continue;
else
last_gtp = NULL;
- for (i = k; i < gtp->hash_size; i++) {
- hlist_for_each_entry_rcu(pctx, >p->tid_hash[i], hlist_tid) {
- if (tid && tid != pctx->u.tid)
- continue;
- else
- tid = 0;
-
- ret = gtp_genl_fill_info(skb,
- NETLINK_CB(cb->skb).portid,
- cb->nlh->nlmsg_seq,
- cb->nlh->nlmsg_type, pctx);
- if (ret < 0) {
+ for (i = bucket; i < gtp->hash_size; i++) {
+ j = 0;
+ hlist_for_each_entry_rcu(pctx, >p->tid_hash[i],
+ hlist_tid) {
+ if (j >= skip &&
+ gtp_genl_fill_info(skb,
+ NETLINK_CB(cb->skb).portid,
+ cb->nlh->nlmsg_seq,
+ cb->nlh->nlmsg_type, pctx)) {
cb->args[0] = i;
- cb->args[1] = pctx->u.tid;
+ cb->args[1] = j;
cb->args[2] = (unsigned long)gtp;
goto out;
}
+ j++;
}
+ skip = 0;
}
+ bucket = 0;
}
cb->args[4] = 1;
out:
+ rcu_read_unlock();
return skb->len;
}
diff --git a/drivers/net/hamradio/6pack.c b/drivers/net/hamradio/6pack.c
index 470b3dc..03c96a6 100644
--- a/drivers/net/hamradio/6pack.c
+++ b/drivers/net/hamradio/6pack.c
@@ -665,10 +665,10 @@ static void sixpack_close(struct tty_struct *tty)
{
struct sixpack *sp;
- write_lock_bh(&disc_data_lock);
+ write_lock_irq(&disc_data_lock);
sp = tty->disc_data;
tty->disc_data = NULL;
- write_unlock_bh(&disc_data_lock);
+ write_unlock_irq(&disc_data_lock);
if (!sp)
return;
diff --git a/drivers/net/hamradio/mkiss.c b/drivers/net/hamradio/mkiss.c
index e0a6b1a..088fe5d 100644
--- a/drivers/net/hamradio/mkiss.c
+++ b/drivers/net/hamradio/mkiss.c
@@ -783,10 +783,10 @@ static void mkiss_close(struct tty_struct *tty)
{
struct mkiss *ax;
- write_lock_bh(&disc_data_lock);
+ write_lock_irq(&disc_data_lock);
ax = tty->disc_data;
tty->disc_data = NULL;
- write_unlock_bh(&disc_data_lock);
+ write_unlock_irq(&disc_data_lock);
if (!ax)
return;
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index 5c2c72b..3289fd9 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -324,8 +324,8 @@ struct phy_device *phy_device_create(struct mii_bus *bus, int addr, int phy_id,
mdiodev->device_free = phy_mdio_device_free;
mdiodev->device_remove = phy_mdio_device_remove;
- dev->speed = 0;
- dev->duplex = -1;
+ dev->speed = SPEED_UNKNOWN;
+ dev->duplex = DUPLEX_UNKNOWN;
dev->pause = 0;
dev->asym_pause = 0;
dev->link = 1;
diff --git a/drivers/net/usb/lan78xx.c b/drivers/net/usb/lan78xx.c
index 32a2493..0eef6c9 100644
--- a/drivers/net/usb/lan78xx.c
+++ b/drivers/net/usb/lan78xx.c
@@ -1769,6 +1769,7 @@ static int lan78xx_mdio_init(struct lan78xx_net *dev)
dev->mdiobus->read = lan78xx_mdiobus_read;
dev->mdiobus->write = lan78xx_mdiobus_write;
dev->mdiobus->name = "lan78xx-mdiobus";
+ dev->mdiobus->parent = &dev->udev->dev;
snprintf(dev->mdiobus->id, MII_BUS_ID_SIZE, "usb-%03d:%03d",
dev->udev->bus->busnum, dev->udev->devnum);
diff --git a/drivers/net/wireless/ath/ar5523/ar5523.c b/drivers/net/wireless/ath/ar5523/ar5523.c
index 7a60d2e..e492c7f 100644
--- a/drivers/net/wireless/ath/ar5523/ar5523.c
+++ b/drivers/net/wireless/ath/ar5523/ar5523.c
@@ -255,7 +255,8 @@ static int ar5523_cmd(struct ar5523 *ar, u32 code, const void *idata,
if (flags & AR5523_CMD_FLAG_MAGIC)
hdr->magic = cpu_to_be32(1 << 24);
- memcpy(hdr + 1, idata, ilen);
+ if (ilen)
+ memcpy(hdr + 1, idata, ilen);
cmd->odata = odata;
cmd->olen = olen;
diff --git a/drivers/net/wireless/ath/ath10k/pci.c b/drivers/net/wireless/ath/ath10k/pci.c
index d84a362..d96e062 100644
--- a/drivers/net/wireless/ath/ath10k/pci.c
+++ b/drivers/net/wireless/ath/ath10k/pci.c
@@ -1765,6 +1765,11 @@ static void ath10k_pci_hif_stop(struct ath10k *ar)
ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
+ ath10k_pci_irq_disable(ar);
+ ath10k_pci_irq_sync(ar);
+ napi_synchronize(&ar->napi);
+ napi_disable(&ar->napi);
+
/* Most likely the device has HTT Rx ring configured. The only way to
* prevent the device from accessing (and possible corrupting) host
* memory is to reset the chip now.
@@ -1778,10 +1783,6 @@ static void ath10k_pci_hif_stop(struct ath10k *ar)
*/
ath10k_pci_safe_chip_reset(ar);
- ath10k_pci_irq_disable(ar);
- ath10k_pci_irq_sync(ar);
- napi_synchronize(&ar->napi);
- napi_disable(&ar->napi);
ath10k_pci_flush(ar);
spin_lock_irqsave(&ar_pci->ps_lock, flags);
diff --git a/drivers/net/wireless/ath/ath10k/txrx.c b/drivers/net/wireless/ath/ath10k/txrx.c
index 9852c5d..beeb6be 100644
--- a/drivers/net/wireless/ath/ath10k/txrx.c
+++ b/drivers/net/wireless/ath/ath10k/txrx.c
@@ -99,6 +99,8 @@ int ath10k_txrx_tx_unref(struct ath10k_htt *htt,
info = IEEE80211_SKB_CB(msdu);
memset(&info->status, 0, sizeof(info->status));
+ info->status.rates[0].idx = -1;
+
trace_ath10k_txrx_tx_unref(ar, tx_done->msdu_id);
if (tx_done->status == HTT_TX_COMPL_STATE_DISCARD) {
diff --git a/drivers/net/wireless/cnss2/pci.c b/drivers/net/wireless/cnss2/pci.c
index 86a6149..dc49be3 100644
--- a/drivers/net/wireless/cnss2/pci.c
+++ b/drivers/net/wireless/cnss2/pci.c
@@ -200,6 +200,17 @@ int cnss_resume_pci_link(struct cnss_pci_data *pci_priv)
return ret;
}
+int cnss_pci_prevent_l1(struct device *dev)
+{
+ return 0;
+}
+EXPORT_SYMBOL(cnss_pci_prevent_l1);
+
+void cnss_pci_allow_l1(struct device *dev)
+{
+}
+EXPORT_SYMBOL(cnss_pci_allow_l1);
+
int cnss_pci_link_down(struct device *dev)
{
unsigned long flags;
diff --git a/drivers/net/wireless/cnss_genl/cnss_nl.c b/drivers/net/wireless/cnss_genl/cnss_nl.c
index 29dd4c9..b399fc9 100644
--- a/drivers/net/wireless/cnss_genl/cnss_nl.c
+++ b/drivers/net/wireless/cnss_genl/cnss_nl.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -66,6 +66,8 @@ static const struct nla_policy cld80211_policy[CLD80211_ATTR_MAX + 1] = {
.len = CLD80211_MAX_NL_DATA },
[CLD80211_ATTR_META_DATA] = { .type = NLA_BINARY,
.len = CLD80211_MAX_NL_DATA },
+ [CLD80211_ATTR_CMD] = { .type = NLA_U32 },
+ [CLD80211_ATTR_CMD_TAG_DATA] = { .type = NLA_NESTED },
};
static int cld80211_pre_doit(const struct genl_ops *ops, struct sk_buff *skb,
diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/led.c b/drivers/net/wireless/intel/iwlwifi/dvm/led.c
index 1bbd17a..20e16c4 100644
--- a/drivers/net/wireless/intel/iwlwifi/dvm/led.c
+++ b/drivers/net/wireless/intel/iwlwifi/dvm/led.c
@@ -185,6 +185,9 @@ void iwl_leds_init(struct iwl_priv *priv)
priv->led.name = kasprintf(GFP_KERNEL, "%s-led",
wiphy_name(priv->hw->wiphy));
+ if (!priv->led.name)
+ return;
+
priv->led.brightness_set = iwl_led_brightness_set;
priv->led.blink_set = iwl_led_blink_set;
priv->led.max_brightness = 1;
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/led.c b/drivers/net/wireless/intel/iwlwifi/mvm/led.c
index 1e51fbe..73c351a 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/led.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/led.c
@@ -109,6 +109,9 @@ int iwl_mvm_leds_init(struct iwl_mvm *mvm)
mvm->led.name = kasprintf(GFP_KERNEL, "%s-led",
wiphy_name(mvm->hw->wiphy));
+ if (!mvm->led.name)
+ return -ENOMEM;
+
mvm->led.brightness_set = iwl_led_brightness_set;
mvm->led.max_brightness = 1;
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c
index 92557cd..d91ab2b 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c
@@ -805,6 +805,21 @@ static void iwl_mvm_mac_tx(struct ieee80211_hw *hw,
!ieee80211_is_action(hdr->frame_control)))
sta = NULL;
+ /* If there is no sta, and it's not offchannel - send through AP */
+ if (info->control.vif->type == NL80211_IFTYPE_STATION &&
+ info->hw_queue != IWL_MVM_OFFCHANNEL_QUEUE && !sta) {
+ struct iwl_mvm_vif *mvmvif =
+ iwl_mvm_vif_from_mac80211(info->control.vif);
+ u8 ap_sta_id = READ_ONCE(mvmvif->ap_sta_id);
+
+ if (ap_sta_id < IWL_MVM_STATION_COUNT) {
+ /* mac80211 holds rcu read lock */
+ sta = rcu_dereference(mvm->fw_id_to_mac_id[ap_sta_id]);
+ if (IS_ERR_OR_NULL(sta))
+ goto drop;
+ }
+ }
+
if (sta) {
if (iwl_mvm_defer_tx(mvm, sta, skb))
return;
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/rx.c b/drivers/net/wireless/intel/iwlwifi/mvm/rx.c
index b78e60e..d0aa4d0 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/rx.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/rx.c
@@ -62,6 +62,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
+#include <asm/unaligned.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include "iwl-trans.h"
@@ -289,7 +290,7 @@ void iwl_mvm_rx_rx_mpdu(struct iwl_mvm *mvm, struct napi_struct *napi,
rx_res = (struct iwl_rx_mpdu_res_start *)pkt->data;
hdr = (struct ieee80211_hdr *)(pkt->data + sizeof(*rx_res));
len = le16_to_cpu(rx_res->byte_count);
- rx_pkt_status = le32_to_cpup((__le32 *)
+ rx_pkt_status = get_unaligned_le32((__le32 *)
(pkt->data + sizeof(*rx_res) + len));
/* Dont use dev_alloc_skb(), we'll have enough headroom once
diff --git a/drivers/net/wireless/marvell/libertas/if_sdio.c b/drivers/net/wireless/marvell/libertas/if_sdio.c
index 06a57c7..44da911 100644
--- a/drivers/net/wireless/marvell/libertas/if_sdio.c
+++ b/drivers/net/wireless/marvell/libertas/if_sdio.c
@@ -1229,6 +1229,10 @@ static int if_sdio_probe(struct sdio_func *func,
spin_lock_init(&card->lock);
card->workqueue = alloc_workqueue("libertas_sdio", WQ_MEM_RECLAIM, 0);
+ if (unlikely(!card->workqueue)) {
+ ret = -ENOMEM;
+ goto err_queue;
+ }
INIT_WORK(&card->packet_worker, if_sdio_host_to_card_worker);
init_waitqueue_head(&card->pwron_waitq);
@@ -1282,6 +1286,7 @@ static int if_sdio_probe(struct sdio_func *func,
lbs_remove_card(priv);
free:
destroy_workqueue(card->workqueue);
+err_queue:
while (card->packets) {
packet = card->packets;
card->packets = card->packets->next;
diff --git a/drivers/net/wireless/marvell/mwifiex/pcie.c b/drivers/net/wireless/marvell/mwifiex/pcie.c
index cb681b2..38d45a7 100644
--- a/drivers/net/wireless/marvell/mwifiex/pcie.c
+++ b/drivers/net/wireless/marvell/mwifiex/pcie.c
@@ -632,8 +632,11 @@ static int mwifiex_pcie_init_evt_ring(struct mwifiex_adapter *adapter)
skb_put(skb, MAX_EVENT_SIZE);
if (mwifiex_map_pci_memory(adapter, skb, MAX_EVENT_SIZE,
- PCI_DMA_FROMDEVICE))
+ PCI_DMA_FROMDEVICE)) {
+ kfree_skb(skb);
+ kfree(card->evtbd_ring_vbase);
return -1;
+ }
buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h
index 08d587a..9143b17 100644
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h
@@ -1348,6 +1348,7 @@ struct rtl8xxxu_fileops {
u8 has_s0s1:1;
u8 has_tx_report:1;
u8 gen2_thermal_meter:1;
+ u8 needs_full_init:1;
u32 adda_1t_init;
u32 adda_1t_path_on;
u32 adda_2t_path_on_a;
diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c
index 02b8ddd..f51ee88 100644
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c
@@ -1673,6 +1673,7 @@ struct rtl8xxxu_fileops rtl8723bu_fops = {
.has_s0s1 = 1,
.has_tx_report = 1,
.gen2_thermal_meter = 1,
+ .needs_full_init = 1,
.adda_1t_init = 0x01c00014,
.adda_1t_path_on = 0x01c00014,
.adda_2t_path_on_a = 0x01c00014,
diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
index e78545d..6d34d44 100644
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
@@ -3905,6 +3905,9 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
else
macpower = true;
+ if (fops->needs_full_init)
+ macpower = false;
+
ret = fops->power_on(priv);
if (ret < 0) {
dev_warn(dev, "%s: Failed power on\n", __func__);
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c
index ae8f055..39a6bd3 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c
@@ -1576,6 +1576,8 @@ static bool usb_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb)
* This is maybe necessary:
* rtlpriv->cfg->ops->fill_tx_cmddesc(hw, buffer, 1, 1, skb);
*/
+ dev_kfree_skb(skb);
+
return true;
}
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c
index d91f8bb..2c23c9e 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c
@@ -1209,6 +1209,7 @@ void rtl92de_enable_interrupt(struct ieee80211_hw *hw)
rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
+ rtlpci->irq_enabled = true;
}
void rtl92de_disable_interrupt(struct ieee80211_hw *hw)
@@ -1218,7 +1219,7 @@ void rtl92de_disable_interrupt(struct ieee80211_hw *hw)
rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
- synchronize_irq(rtlpci->pdev->irq);
+ rtlpci->irq_enabled = false;
}
static void _rtl92de_poweroff_adapter(struct ieee80211_hw *hw)
@@ -1389,7 +1390,7 @@ void rtl92de_set_beacon_related_registers(struct ieee80211_hw *hw)
bcn_interval = mac->beacon_interval;
atim_window = 2;
- /*rtl92de_disable_interrupt(hw); */
+ rtl92de_disable_interrupt(hw);
rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
@@ -1409,9 +1410,9 @@ void rtl92de_set_beacon_interval(struct ieee80211_hw *hw)
RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
"beacon_interval:%d\n", bcn_interval);
- /* rtl92de_disable_interrupt(hw); */
+ rtl92de_disable_interrupt(hw);
rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
- /* rtl92de_enable_interrupt(hw); */
+ rtl92de_enable_interrupt(hw);
}
void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw,
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c
index 1ebfee1..63cad2f 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c
@@ -243,6 +243,7 @@ static struct rtl_hal_ops rtl8192de_hal_ops = {
.led_control = rtl92de_led_control,
.set_desc = rtl92de_set_desc,
.get_desc = rtl92de_get_desc,
+ .is_tx_desc_closed = rtl92de_is_tx_desc_closed,
.tx_polling = rtl92de_tx_polling,
.enable_hw_sec = rtl92de_enable_hw_security_config,
.set_key = rtl92de_set_key,
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c
index e998e98..bddf57c 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c
@@ -843,13 +843,15 @@ u32 rtl92de_get_desc(u8 *p_desc, bool istx, u8 desc_name)
break;
}
} else {
- struct rx_desc_92c *pdesc = (struct rx_desc_92c *)p_desc;
switch (desc_name) {
case HW_DESC_OWN:
- ret = GET_RX_DESC_OWN(pdesc);
+ ret = GET_RX_DESC_OWN(p_desc);
break;
case HW_DESC_RXPKT_LEN:
- ret = GET_RX_DESC_PKT_LEN(pdesc);
+ ret = GET_RX_DESC_PKT_LEN(p_desc);
+ break;
+ case HW_DESC_RXBUFF_ADDR:
+ ret = GET_RX_DESC_BUFF_ADDR(p_desc);
break;
default:
RT_ASSERT(false, "ERR rxdesc :%d not process\n",
@@ -860,6 +862,23 @@ u32 rtl92de_get_desc(u8 *p_desc, bool istx, u8 desc_name)
return ret;
}
+bool rtl92de_is_tx_desc_closed(struct ieee80211_hw *hw,
+ u8 hw_queue, u16 index)
+{
+ struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+ struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
+ u8 *entry = (u8 *)(&ring->desc[ring->idx]);
+ u8 own = (u8)rtl92de_get_desc(entry, true, HW_DESC_OWN);
+
+ /* a beacon packet will only use the first
+ * descriptor by defaut, and the own bit may not
+ * be cleared by the hardware
+ */
+ if (own)
+ return false;
+ return true;
+}
+
void rtl92de_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h
index 194d99f..d061f33 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h
@@ -740,6 +740,8 @@ bool rtl92de_rx_query_desc(struct ieee80211_hw *hw,
void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
u8 desc_name, u8 *val);
u32 rtl92de_get_desc(u8 *pdesc, bool istx, u8 desc_name);
+bool rtl92de_is_tx_desc_closed(struct ieee80211_hw *hw,
+ u8 hw_queue, u16 index);
void rtl92de_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
bool b_firstseg, bool b_lastseg,
diff --git a/drivers/net/wireless/realtek/rtlwifi/usb.c b/drivers/net/wireless/realtek/rtlwifi/usb.c
index ae0c48f..1f02461 100644
--- a/drivers/net/wireless/realtek/rtlwifi/usb.c
+++ b/drivers/net/wireless/realtek/rtlwifi/usb.c
@@ -1088,8 +1088,10 @@ int rtl_usb_probe(struct usb_interface *intf,
rtlpriv->hw = hw;
rtlpriv->usb_data = kzalloc(RTL_USB_MAX_RX_COUNT * sizeof(u32),
GFP_KERNEL);
- if (!rtlpriv->usb_data)
+ if (!rtlpriv->usb_data) {
+ ieee80211_free_hw(hw);
return -ENOMEM;
+ }
/* this spin lock must be initialized early */
spin_lock_init(&rtlpriv->locks.usb_lock);
@@ -1152,6 +1154,7 @@ int rtl_usb_probe(struct usb_interface *intf,
_rtl_usb_io_handler_release(hw);
usb_put_dev(udev);
complete(&rtlpriv->firmware_loading_complete);
+ kfree(rtlpriv->usb_data);
return -ENODEV;
}
EXPORT_SYMBOL(rtl_usb_probe);
diff --git a/drivers/nfc/nxp-nci/i2c.c b/drivers/nfc/nxp-nci/i2c.c
index 06a157c6..7eab975 100644
--- a/drivers/nfc/nxp-nci/i2c.c
+++ b/drivers/nfc/nxp-nci/i2c.c
@@ -238,8 +238,10 @@ static irqreturn_t nxp_nci_i2c_irq_thread_fn(int irq, void *phy_id)
if (r == -EREMOTEIO) {
phy->hard_fault = r;
- skb = NULL;
- } else if (r < 0) {
+ if (info->mode == NXP_NCI_MODE_FW)
+ nxp_nci_fw_recv_frame(phy->ndev, NULL);
+ }
+ if (r < 0) {
nfc_err(&client->dev, "Read failed with error %d\n", r);
goto exit_irq_handled;
}
diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c
index 8705bfe..9561a24 100644
--- a/drivers/nvme/host/core.c
+++ b/drivers/nvme/host/core.c
@@ -1043,7 +1043,7 @@ static int nvme_pr_reserve(struct block_device *bdev, u64 key,
static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
enum pr_type type, bool abort)
{
- u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1;
+ u32 cdw10 = nvme_pr_type(type) << 8 | (abort ? 2 : 1);
return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
}
@@ -1055,7 +1055,7 @@ static int nvme_pr_clear(struct block_device *bdev, u64 key)
static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
{
- u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0;
+ u32 cdw10 = nvme_pr_type(type) << 8 | (key ? 1 << 3 : 0);
return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
}
diff --git a/drivers/parport/share.c b/drivers/parport/share.c
index daa2eb3..a7ceed7 100644
--- a/drivers/parport/share.c
+++ b/drivers/parport/share.c
@@ -230,6 +230,18 @@ static int port_check(struct device *dev, void *dev_drv)
return 0;
}
+/*
+ * Iterates through all the devices connected to the bus and return 1
+ * if the device is a parallel port.
+ */
+
+static int port_detect(struct device *dev, void *dev_drv)
+{
+ if (is_parport(dev))
+ return 1;
+ return 0;
+}
+
/**
* parport_register_driver - register a parallel port device driver
* @drv: structure describing the driver
@@ -282,6 +294,15 @@ int __parport_register_driver(struct parport_driver *drv, struct module *owner,
if (ret)
return ret;
+ /*
+ * check if bus has any parallel port registered, if
+ * none is found then load the lowlevel driver.
+ */
+ ret = bus_for_each_dev(&parport_bus_type, NULL, NULL,
+ port_detect);
+ if (!ret)
+ get_lowlevel_driver();
+
mutex_lock(®istration_lock);
if (drv->match_port)
bus_for_each_dev(&parport_bus_type, NULL, drv,
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 37f393f..55ca14f 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -230,7 +230,7 @@ u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
return 0;
mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
- if (flag)
+ if (flag & PCI_MSIX_ENTRY_CTRL_MASKBIT)
mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
writel(mask_bits, pci_msix_desc_addr(desc) + PCI_MSIX_ENTRY_VECTOR_CTRL);
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index f474899..496296b 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -4446,7 +4446,7 @@ int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
#define INTEL_BSPR_REG_BPPD (1 << 9)
/* Upstream Peer Decode Configuration Register */
-#define INTEL_UPDCR_REG 0x1114
+#define INTEL_UPDCR_REG 0x1014
/* 5:0 Peer Decode Enable bits */
#define INTEL_UPDCR_REG_MASK 0x3f
diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c
index fc5b18d..f83a2a6 100644
--- a/drivers/pinctrl/intel/pinctrl-baytrail.c
+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c
@@ -204,7 +204,6 @@ struct byt_gpio {
struct platform_device *pdev;
struct pinctrl_dev *pctl_dev;
struct pinctrl_desc pctl_desc;
- raw_spinlock_t lock;
const struct byt_pinctrl_soc_data *soc_data;
struct byt_community *communities_copy;
struct byt_gpio_pin_context *saved_context;
@@ -715,6 +714,8 @@ static const struct byt_pinctrl_soc_data *byt_soc_data[] = {
NULL,
};
+static DEFINE_RAW_SPINLOCK(byt_lock);
+
static struct byt_community *byt_get_community(struct byt_gpio *vg,
unsigned int pin)
{
@@ -856,7 +857,7 @@ static void byt_set_group_simple_mux(struct byt_gpio *vg,
unsigned long flags;
int i;
- raw_spin_lock_irqsave(&vg->lock, flags);
+ raw_spin_lock_irqsave(&byt_lock, flags);
for (i = 0; i < group.npins; i++) {
void __iomem *padcfg0;
@@ -876,7 +877,7 @@ static void byt_set_group_simple_mux(struct byt_gpio *vg,
writel(value, padcfg0);
}
- raw_spin_unlock_irqrestore(&vg->lock, flags);
+ raw_spin_unlock_irqrestore(&byt_lock, flags);
}
static void byt_set_group_mixed_mux(struct byt_gpio *vg,
@@ -886,7 +887,7 @@ static void byt_set_group_mixed_mux(struct byt_gpio *vg,
unsigned long flags;
int i;
- raw_spin_lock_irqsave(&vg->lock, flags);
+ raw_spin_lock_irqsave(&byt_lock, flags);
for (i = 0; i < group.npins; i++) {
void __iomem *padcfg0;
@@ -906,7 +907,7 @@ static void byt_set_group_mixed_mux(struct byt_gpio *vg,
writel(value, padcfg0);
}
- raw_spin_unlock_irqrestore(&vg->lock, flags);
+ raw_spin_unlock_irqrestore(&byt_lock, flags);
}
static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
@@ -955,11 +956,11 @@ static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset)
unsigned long flags;
u32 value;
- raw_spin_lock_irqsave(&vg->lock, flags);
+ raw_spin_lock_irqsave(&byt_lock, flags);
value = readl(reg);
value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
writel(value, reg);
- raw_spin_unlock_irqrestore(&vg->lock, flags);
+ raw_spin_unlock_irqrestore(&byt_lock, flags);
}
static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
@@ -971,7 +972,7 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
u32 value, gpio_mux;
unsigned long flags;
- raw_spin_lock_irqsave(&vg->lock, flags);
+ raw_spin_lock_irqsave(&byt_lock, flags);
/*
* In most cases, func pin mux 000 means GPIO function.
@@ -993,7 +994,7 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
"pin %u forcibly re-configured as GPIO\n", offset);
}
- raw_spin_unlock_irqrestore(&vg->lock, flags);
+ raw_spin_unlock_irqrestore(&byt_lock, flags);
pm_runtime_get(&vg->pdev->dev);
@@ -1021,7 +1022,7 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
unsigned long flags;
u32 value;
- raw_spin_lock_irqsave(&vg->lock, flags);
+ raw_spin_lock_irqsave(&byt_lock, flags);
value = readl(val_reg);
value &= ~BYT_DIR_MASK;
@@ -1038,7 +1039,7 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
"Potential Error: Setting GPIO with direct_irq_en to output");
writel(value, val_reg);
- raw_spin_unlock_irqrestore(&vg->lock, flags);
+ raw_spin_unlock_irqrestore(&byt_lock, flags);
return 0;
}
@@ -1107,11 +1108,11 @@ static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
u32 conf, pull, val, debounce;
u16 arg = 0;
- raw_spin_lock_irqsave(&vg->lock, flags);
+ raw_spin_lock_irqsave(&byt_lock, flags);
conf = readl(conf_reg);
pull = conf & BYT_PULL_ASSIGN_MASK;
val = readl(val_reg);
- raw_spin_unlock_irqrestore(&vg->lock, flags);
+ raw_spin_unlock_irqrestore(&byt_lock, flags);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
@@ -1138,9 +1139,9 @@ static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
if (!(conf & BYT_DEBOUNCE_EN))
return -EINVAL;
- raw_spin_lock_irqsave(&vg->lock, flags);
+ raw_spin_lock_irqsave(&byt_lock, flags);
debounce = readl(db_reg);
- raw_spin_unlock_irqrestore(&vg->lock, flags);
+ raw_spin_unlock_irqrestore(&byt_lock, flags);
switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
case BYT_DEBOUNCE_PULSE_375US:
@@ -1192,7 +1193,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
u32 conf, val, debounce;
int i, ret = 0;
- raw_spin_lock_irqsave(&vg->lock, flags);
+ raw_spin_lock_irqsave(&byt_lock, flags);
conf = readl(conf_reg);
val = readl(val_reg);
@@ -1300,7 +1301,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
if (!ret)
writel(conf, conf_reg);
- raw_spin_unlock_irqrestore(&vg->lock, flags);
+ raw_spin_unlock_irqrestore(&byt_lock, flags);
return ret;
}
@@ -1325,9 +1326,9 @@ static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
unsigned long flags;
u32 val;
- raw_spin_lock_irqsave(&vg->lock, flags);
+ raw_spin_lock_irqsave(&byt_lock, flags);
val = readl(reg);
- raw_spin_unlock_irqrestore(&vg->lock, flags);
+ raw_spin_unlock_irqrestore(&byt_lock, flags);
return !!(val & BYT_LEVEL);
}
@@ -1342,13 +1343,13 @@ static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
if (!reg)
return;
- raw_spin_lock_irqsave(&vg->lock, flags);
+ raw_spin_lock_irqsave(&byt_lock, flags);
old_val = readl(reg);
if (value)
writel(old_val | BYT_LEVEL, reg);
else
writel(old_val & ~BYT_LEVEL, reg);
- raw_spin_unlock_irqrestore(&vg->lock, flags);
+ raw_spin_unlock_irqrestore(&byt_lock, flags);
}
static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
@@ -1361,9 +1362,9 @@ static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
if (!reg)
return -EINVAL;
- raw_spin_lock_irqsave(&vg->lock, flags);
+ raw_spin_lock_irqsave(&byt_lock, flags);
value = readl(reg);
- raw_spin_unlock_irqrestore(&vg->lock, flags);
+ raw_spin_unlock_irqrestore(&byt_lock, flags);
if (!(value & BYT_OUTPUT_EN))
return GPIOF_DIR_OUT;
@@ -1406,14 +1407,14 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
const char *label;
unsigned int pin;
- raw_spin_lock_irqsave(&vg->lock, flags);
+ raw_spin_lock_irqsave(&byt_lock, flags);
pin = vg->soc_data->pins[i].number;
reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
if (!reg) {
seq_printf(s,
"Could not retrieve pin %i conf0 reg\n",
pin);
- raw_spin_unlock_irqrestore(&vg->lock, flags);
+ raw_spin_unlock_irqrestore(&byt_lock, flags);
continue;
}
conf0 = readl(reg);
@@ -1422,11 +1423,11 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
if (!reg) {
seq_printf(s,
"Could not retrieve pin %i val reg\n", pin);
- raw_spin_unlock_irqrestore(&vg->lock, flags);
+ raw_spin_unlock_irqrestore(&byt_lock, flags);
continue;
}
val = readl(reg);
- raw_spin_unlock_irqrestore(&vg->lock, flags);
+ raw_spin_unlock_irqrestore(&byt_lock, flags);
comm = byt_get_community(vg, pin);
if (!comm) {
@@ -1510,9 +1511,9 @@ static void byt_irq_ack(struct irq_data *d)
if (!reg)
return;
- raw_spin_lock(&vg->lock);
+ raw_spin_lock(&byt_lock);
writel(BIT(offset % 32), reg);
- raw_spin_unlock(&vg->lock);
+ raw_spin_unlock(&byt_lock);
}
static void byt_irq_mask(struct irq_data *d)
@@ -1536,7 +1537,7 @@ static void byt_irq_unmask(struct irq_data *d)
if (!reg)
return;
- raw_spin_lock_irqsave(&vg->lock, flags);
+ raw_spin_lock_irqsave(&byt_lock, flags);
value = readl(reg);
switch (irqd_get_trigger_type(d)) {
@@ -1557,7 +1558,7 @@ static void byt_irq_unmask(struct irq_data *d)
writel(value, reg);
- raw_spin_unlock_irqrestore(&vg->lock, flags);
+ raw_spin_unlock_irqrestore(&byt_lock, flags);
}
static int byt_irq_type(struct irq_data *d, unsigned int type)
@@ -1571,7 +1572,7 @@ static int byt_irq_type(struct irq_data *d, unsigned int type)
if (!reg || offset >= vg->chip.ngpio)
return -EINVAL;
- raw_spin_lock_irqsave(&vg->lock, flags);
+ raw_spin_lock_irqsave(&byt_lock, flags);
value = readl(reg);
WARN(value & BYT_DIRECT_IRQ_EN,
@@ -1593,7 +1594,7 @@ static int byt_irq_type(struct irq_data *d, unsigned int type)
else if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_handler_locked(d, handle_level_irq);
- raw_spin_unlock_irqrestore(&vg->lock, flags);
+ raw_spin_unlock_irqrestore(&byt_lock, flags);
return 0;
}
@@ -1629,9 +1630,9 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
continue;
}
- raw_spin_lock(&vg->lock);
+ raw_spin_lock(&byt_lock);
pending = readl(reg);
- raw_spin_unlock(&vg->lock);
+ raw_spin_unlock(&byt_lock);
for_each_set_bit(pin, &pending, 32) {
virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
generic_handle_irq(virq);
@@ -1833,8 +1834,6 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
return PTR_ERR(vg->pctl_dev);
}
- raw_spin_lock_init(&vg->lock);
-
ret = byt_gpio_probe(vg);
if (ret) {
pinctrl_unregister(vg->pctl_dev);
@@ -1852,8 +1851,11 @@ static int byt_gpio_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct byt_gpio *vg = platform_get_drvdata(pdev);
+ unsigned long flags;
int i;
+ raw_spin_lock_irqsave(&byt_lock, flags);
+
for (i = 0; i < vg->soc_data->npins; i++) {
void __iomem *reg;
u32 value;
@@ -1874,6 +1876,7 @@ static int byt_gpio_suspend(struct device *dev)
vg->saved_context[i].val = value;
}
+ raw_spin_unlock_irqrestore(&byt_lock, flags);
return 0;
}
@@ -1881,8 +1884,11 @@ static int byt_gpio_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct byt_gpio *vg = platform_get_drvdata(pdev);
+ unsigned long flags;
int i;
+ raw_spin_lock_irqsave(&byt_lock, flags);
+
for (i = 0; i < vg->soc_data->npins; i++) {
void __iomem *reg;
u32 value;
@@ -1920,6 +1926,7 @@ static int byt_gpio_resume(struct device *dev)
}
}
+ raw_spin_unlock_irqrestore(&byt_lock, flags);
return 0;
}
#endif
diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
index db3fb23..906e044 100644
--- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
+++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
@@ -762,12 +762,23 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev)
return ret;
}
- ret = gpiochip_add_pin_range(&pctrl->chip,
- dev_name(pctrl->dev),
- 0, 0, pctrl->chip.ngpio);
- if (ret) {
- dev_err(pctrl->dev, "failed to add pin range\n");
- goto unregister_gpiochip;
+ /*
+ * For DeviceTree-supported systems, the gpio core checks the
+ * pinctrl's device node for the "gpio-ranges" property.
+ * If it is present, it takes care of adding the pin ranges
+ * for the driver. In this case the driver can skip ahead.
+ *
+ * In order to remain compatible with older, existing DeviceTree
+ * files which don't set the "gpio-ranges" property or systems that
+ * utilize ACPI the driver has to call gpiochip_add_pin_range().
+ */
+ if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
+ ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
+ 0, 0, pctrl->chip.ngpio);
+ if (ret) {
+ dev_err(pctrl->dev, "failed to add pin range\n");
+ goto unregister_gpiochip;
+ }
}
platform_set_drvdata(pdev, pctrl);
diff --git a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
index 3d92f82..0839b70a 100644
--- a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
+++ b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
@@ -495,8 +495,10 @@ static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d)
return -ENODEV;
eint_data = devm_kzalloc(dev, sizeof(*eint_data), GFP_KERNEL);
- if (!eint_data)
+ if (!eint_data) {
+ of_node_put(eint_np);
return -ENOMEM;
+ }
eint_data->drvdata = d;
@@ -508,12 +510,14 @@ static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d)
irq = irq_of_parse_and_map(eint_np, i);
if (!irq) {
dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i);
+ of_node_put(eint_np);
return -ENXIO;
}
eint_data->parents[i] = irq;
irq_set_chained_handler_and_data(irq, handlers[i], eint_data);
}
+ of_node_put(eint_np);
bank = d->pin_banks;
for (i = 0; i < d->nr_banks; ++i, ++bank) {
diff --git a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
index 43407ab..0cd9f3a 100644
--- a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
+++ b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
@@ -713,6 +713,7 @@ static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d)
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data) {
dev_err(dev, "could not allocate memory for wkup eint data\n");
+ of_node_put(eint0_np);
return -ENOMEM;
}
data->drvdata = d;
@@ -723,6 +724,7 @@ static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d)
irq = irq_of_parse_and_map(eint0_np, i);
if (!irq) {
dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i);
+ of_node_put(eint0_np);
return -ENXIO;
}
@@ -730,6 +732,7 @@ static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d)
s3c64xx_eint0_handlers[i],
data);
}
+ of_node_put(eint0_np);
bank = d->pin_banks;
for (i = 0; i < d->nr_banks; ++i, ++bank) {
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index 620727f..6b77a1b 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -281,6 +281,7 @@ static int samsung_dt_node_to_map(struct pinctrl_dev *pctldev,
&reserved_maps, num_maps);
if (ret < 0) {
samsung_dt_free_map(pctldev, *map, *num_maps);
+ of_node_put(np);
return ret;
}
}
@@ -770,8 +771,10 @@ static struct samsung_pmx_func *samsung_pinctrl_create_functions(
if (!of_get_child_count(cfg_np)) {
ret = samsung_pinctrl_create_function(dev, drvdata,
cfg_np, func);
- if (ret < 0)
+ if (ret < 0) {
+ of_node_put(cfg_np);
return ERR_PTR(ret);
+ }
if (ret > 0) {
++func;
++func_cnt;
@@ -782,8 +785,11 @@ static struct samsung_pmx_func *samsung_pinctrl_create_functions(
for_each_child_of_node(cfg_np, func_np) {
ret = samsung_pinctrl_create_function(dev, drvdata,
func_np, func);
- if (ret < 0)
+ if (ret < 0) {
+ of_node_put(func_np);
+ of_node_put(cfg_np);
return ERR_PTR(ret);
+ }
if (ret > 0) {
++func;
++func_cnt;
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
index 3323204..3eccc9b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
@@ -1453,7 +1453,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(ET0_ETXD2_A),
GPIO_FN(EX_CS5), GPIO_FN(SD1_CMD_A), GPIO_FN(ATADIR), GPIO_FN(QSSL_B),
GPIO_FN(ET0_ETXD3_A),
- GPIO_FN(RD_WR), GPIO_FN(TCLK1_B),
+ GPIO_FN(RD_WR), GPIO_FN(TCLK0), GPIO_FN(CAN_CLK_B), GPIO_FN(ET0_ETXD4),
GPIO_FN(EX_WAIT0), GPIO_FN(TCLK1_B),
GPIO_FN(EX_WAIT1), GPIO_FN(SD1_DAT0_A), GPIO_FN(DREQ2),
GPIO_FN(CAN1_TX_C), GPIO_FN(ET0_LINK_C), GPIO_FN(ET0_ETXD5_A),
@@ -1949,7 +1949,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP3_20 [1] */
FN_EX_WAIT0, FN_TCLK1_B,
/* IP3_19_18 [2] */
- FN_RD_WR, FN_TCLK1_B, 0, 0,
+ FN_RD_WR, FN_TCLK0, FN_CAN_CLK_B, FN_ET0_ETXD4,
/* IP3_17_15 [3] */
FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B,
FN_ET0_ETXD3_A, 0, 0, 0,
diff --git a/drivers/platform/msm/ipa/ipa_api.c b/drivers/platform/msm/ipa/ipa_api.c
index 1db9b04..ae75cbb 100644
--- a/drivers/platform/msm/ipa/ipa_api.c
+++ b/drivers/platform/msm/ipa/ipa_api.c
@@ -3428,6 +3428,21 @@ int ipa_tz_unlock_reg(struct ipa_tz_unlock_reg_info *reg_info, u16 num_regs)
return ret;
}
+void ipa_register_client_callback(int (*client_cb)(bool is_lock),
+ bool (*teth_port_state)(void),
+ enum ipa_client_type client)
+{
+ IPA_API_DISPATCH(ipa_register_client_callback,
+ client_cb, teth_port_state, client);
+}
+
+void ipa_deregister_client_callback(enum ipa_client_type client)
+{
+ IPA_API_DISPATCH(ipa_deregister_client_callback,
+ client);
+}
+
+
/**
* ipa_pm_is_used() - Returns if IPA PM framework is used
*/
diff --git a/drivers/platform/msm/ipa/ipa_api.h b/drivers/platform/msm/ipa/ipa_api.h
index 64ebf65..1c6df33a 100644
--- a/drivers/platform/msm/ipa/ipa_api.h
+++ b/drivers/platform/msm/ipa/ipa_api.h
@@ -435,6 +435,12 @@ struct ipa_api_controller {
bool (*ipa_pm_is_used)(void);
bool (*ipa_get_lan_rx_napi)(void);
+
+ void (*ipa_register_client_callback)(
+ int (*client_cb)(bool is_lock),
+ bool (*teth_port_state)(void), enum ipa_client_type client);
+
+ void (*ipa_deregister_client_callback)(enum ipa_client_type client);
};
#ifdef CONFIG_IPA
diff --git a/drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c b/drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c
index e211473..039e283 100644
--- a/drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c
+++ b/drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c
@@ -171,6 +171,7 @@ struct ipa_mhi_client_ctx {
};
static struct ipa_mhi_client_ctx *ipa_mhi_client_ctx;
+static DEFINE_MUTEX(mhi_client_general_mutex);
#ifdef CONFIG_DEBUG_FS
#define IPA_MHI_MAX_MSG_LEN 512
@@ -191,6 +192,18 @@ static char *ipa_mhi_channel_state_str[] = {
ipa_mhi_channel_state_str[(state)] : \
"INVALID")
+static int ipa_mhi_set_lock_unlock(bool is_lock)
+{
+ IPA_MHI_DBG("entry\n");
+ if (is_lock)
+ mutex_lock(&mhi_client_general_mutex);
+ else
+ mutex_unlock(&mhi_client_general_mutex);
+ IPA_MHI_DBG("exit\n");
+
+ return 0;
+}
+
static int ipa_mhi_read_write_host(enum ipa_mhi_dma_dir dir, void *dev_addr,
u64 host_addr, int size)
{
@@ -1586,6 +1599,7 @@ int ipa_mhi_connect_pipe(struct ipa_mhi_connect_params *in, u32 *clnt_hdl)
IPA_ACTIVE_CLIENTS_INC_EP(in->sys.client);
+ mutex_lock(&mhi_client_general_mutex);
if (ipa_get_transport_type() == IPA_TRANSPORT_TYPE_GSI) {
struct ipa_mhi_connect_params_internal internal;
@@ -1631,6 +1645,8 @@ int ipa_mhi_connect_pipe(struct ipa_mhi_connect_params *in, u32 *clnt_hdl)
sizeof(((struct ipa_mhi_ch_ctx *)0)->chstate));
if (res) {
IPA_MHI_ERR("ipa_mhi_read_write_host failed\n");
+ mutex_unlock(&mhi_client_general_mutex);
+ IPA_ACTIVE_CLIENTS_DEC_EP(in->sys.client);
return res;
}
@@ -1650,6 +1666,8 @@ int ipa_mhi_connect_pipe(struct ipa_mhi_connect_params *in, u32 *clnt_hdl)
channel->state = IPA_HW_MHI_CHANNEL_STATE_RUN;
}
+ mutex_unlock(&mhi_client_general_mutex);
+
if (!in->sys.keep_ipa_awake)
IPA_ACTIVE_CLIENTS_DEC_EP(in->sys.client);
@@ -1657,6 +1675,7 @@ int ipa_mhi_connect_pipe(struct ipa_mhi_connect_params *in, u32 *clnt_hdl)
return 0;
fail_connect_pipe:
+ mutex_unlock(&mhi_client_general_mutex);
ipa_mhi_reset_channel(channel);
fail_start_channel:
IPA_ACTIVE_CLIENTS_DEC_EP(in->sys.client);
@@ -1711,19 +1730,24 @@ int ipa_mhi_disconnect_pipe(u32 clnt_hdl)
goto fail_reset_channel;
}
+ mutex_lock(&mhi_client_general_mutex);
res = ipa_disconnect_mhi_pipe(clnt_hdl);
if (res) {
IPA_MHI_ERR(
"IPA core driver failed to disconnect the pipe hdl %d, res %d"
, clnt_hdl, res);
- return res;
+ goto fail_disconnect_pipe;
}
+ mutex_unlock(&mhi_client_general_mutex);
+
IPA_ACTIVE_CLIENTS_DEC_EP(ipa_get_client_mapping(clnt_hdl));
IPA_MHI_DBG("client (ep: %d) disconnected\n", clnt_hdl);
IPA_MHI_FUNC_EXIT();
return 0;
+fail_disconnect_pipe:
+ mutex_unlock(&mhi_client_general_mutex);
fail_reset_channel:
IPA_ACTIVE_CLIENTS_DEC_EP(ipa_get_client_mapping(clnt_hdl));
return res;
@@ -2560,6 +2584,8 @@ void ipa_mhi_destroy(void)
IPA_MHI_DBG("IPA MHI was not initialized, already destroyed\n");
return;
}
+
+ ipa_deregister_client_callback(IPA_CLIENT_MHI_PROD);
/* reset all UL and DL acc channels and its accociated event rings */
if (ipa_get_transport_type() == IPA_TRANSPORT_TYPE_GSI) {
res = ipa_mhi_destroy_all_channels();
@@ -2830,6 +2856,8 @@ int ipa_mhi_init(struct ipa_mhi_init_params *params)
/* Initialize debugfs */
ipa_mhi_debugfs_init();
+ ipa_register_client_callback(&ipa_mhi_set_lock_unlock, NULL,
+ IPA_CLIENT_MHI_PROD);
IPA_MHI_FUNC_EXIT();
return 0;
@@ -2907,6 +2935,5 @@ const char *ipa_mhi_get_state_str(int state)
return MHI_STATE_STR(state);
}
EXPORT_SYMBOL(ipa_mhi_get_state_str);
-
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("IPA MHI client driver");
diff --git a/drivers/platform/msm/ipa/ipa_clients/ipa_usb.c b/drivers/platform/msm/ipa/ipa_clients/ipa_usb.c
index eccdeab..153291a 100644
--- a/drivers/platform/msm/ipa/ipa_clients/ipa_usb.c
+++ b/drivers/platform/msm/ipa/ipa_clients/ipa_usb.c
@@ -299,6 +299,17 @@ static char *ipa3_usb_notify_event_to_string(enum ipa_usb_notify_event event)
return "UNSUPPORTED";
}
+static bool ipa3_usb_get_teth_port_state(void)
+{
+ if (ipa3_usb_ctx == NULL)
+ return false;
+ if (ipa3_usb_ctx->ttype_ctx[IPA_USB_TRANSPORT_TETH].state ==
+ IPA_USB_CONNECTED)
+ return true;
+ else
+ return false;
+}
+
static bool ipa3_usb_set_state(enum ipa3_usb_state new_state, bool err_permit,
enum ipa3_usb_transport_type ttype)
{
@@ -896,6 +907,18 @@ static int ipa3_usb_create_rm_resources(enum ipa3_usb_transport_type ttype)
return result;
}
+static int ipa_usb_set_lock_unlock(bool is_lock)
+{
+ IPA_USB_DBG("entry\n");
+ if (is_lock)
+ mutex_lock(&ipa3_usb_ctx->general_mutex);
+ else
+ mutex_unlock(&ipa3_usb_ctx->general_mutex);
+ IPA_USB_DBG("exit\n");
+
+ return 0;
+}
+
int ipa_usb_init_teth_prot(enum ipa_usb_teth_prot teth_prot,
struct ipa_usb_teth_params *teth_params,
int (*ipa_usb_notify_cb)(enum ipa_usb_notify_event,
@@ -1033,6 +1056,14 @@ int ipa_usb_init_teth_prot(enum ipa_usb_teth_prot teth_prot,
IPA_USB_DBG("initialized %s %s\n",
ipa3_usb_teth_prot_to_string(teth_prot),
ipa3_usb_teth_bridge_prot_to_string(teth_prot));
+ /*
+ * Register for xdci lock/unlock callback with ipa core driver.
+ * As per use case, only register for IPA_CONS end point now.
+ * If needed we can include the same for IPA_PROD ep.
+ * For IPA_USB_DIAG/DPL config there will not be any UL ep.
+ */
+ ipa3_register_client_callback(&ipa_usb_set_lock_unlock,
+ &ipa3_usb_get_teth_port_state, IPA_CLIENT_USB_PROD);
break;
case IPA_USB_RMNET_CV2X:
if (ipa3_usb_ctx->teth_prot_ctx[teth_prot].state !=
@@ -2353,20 +2384,6 @@ static void ipa_usb_debugfs_init(void){}
static void ipa_usb_debugfs_remove(void){}
#endif /* CONFIG_DEBUG_FS */
-static int ipa_usb_set_lock_unlock(bool is_lock)
-{
- IPA_USB_DBG("entry\n");
- if (is_lock)
- mutex_lock(&ipa3_usb_ctx->general_mutex);
- else
- mutex_unlock(&ipa3_usb_ctx->general_mutex);
- IPA_USB_DBG("exit\n");
-
- return 0;
-}
-
-
-
int ipa_usb_xdci_connect(struct ipa_usb_xdci_chan_params *ul_chan_params,
struct ipa_usb_xdci_chan_params *dl_chan_params,
struct ipa_req_chan_out_params *ul_out_params,
@@ -2428,16 +2445,6 @@ int ipa_usb_xdci_connect(struct ipa_usb_xdci_chan_params *ul_chan_params,
goto connect_fail;
}
- /*
- * Register for xdci lock/unlock callback with ipa core driver.
- * As per use case, only register for IPA_CONS end point for now.
- * If needed we can include the same for IPA_PROD ep.
- * For IPA_USB_DIAG/DPL config there will not be any UL ep.
- */
- if (connect_params->teth_prot != IPA_USB_DIAG)
- ipa3_register_lock_unlock_callback(&ipa_usb_set_lock_unlock,
- ul_out_params->clnt_hdl);
-
IPA_USB_DBG_LOW("exit\n");
mutex_unlock(&ipa3_usb_ctx->general_mutex);
return 0;
@@ -2515,15 +2522,6 @@ static int ipa_usb_xdci_dismiss_channels(u32 ul_clnt_hdl, u32 dl_clnt_hdl,
}
}
- /*
- * Deregister for xdci lock/unlock callback from ipa core driver.
- * As per use case, only deregister for IPA_CONS end point for now.
- * If needed we can include the same for IPA_PROD ep.
- * For IPA_USB_DIAG/DPL config there will not be any UL config.
- */
- if (!IPA3_USB_IS_TTYPE_DPL(ttype))
- ipa3_deregister_lock_unlock_callback(ul_clnt_hdl);
-
/* Change state to STOPPED */
if (!ipa3_usb_set_state(IPA_USB_STOPPED, false, ttype))
IPA_USB_ERR("failed to change state to stopped\n");
@@ -3234,6 +3232,15 @@ static int __init ipa3_usb_init(void)
static void ipa3_usb_exit(void)
{
IPA_USB_DBG_LOW("IPA_USB exit\n");
+
+ /*
+ * Deregister for xdci lock/unlock callback from ipa core driver.
+ * As per use case, only deregister for IPA_CONS end point for now.
+ * If needed we can include the same for IPA_PROD ep.
+ * For IPA_USB_DIAG/DPL config there will not be any UL config.
+ */
+ ipa3_deregister_client_callback(IPA_CLIENT_USB_PROD);
+
ipa_usb_debugfs_remove();
kfree(ipa3_usb_ctx);
}
diff --git a/drivers/platform/msm/ipa/ipa_common_i.h b/drivers/platform/msm/ipa/ipa_common_i.h
index 530aa54..3b40b41 100644
--- a/drivers/platform/msm/ipa/ipa_common_i.h
+++ b/drivers/platform/msm/ipa/ipa_common_i.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -445,4 +445,9 @@ int ipa_smmu_free_sgt(struct sg_table **out_sgt_ptr);
int ipa_ut_module_init(void);
void ipa_ut_module_exit(void);
+void ipa_register_client_callback(int (*client_cb)(bool is_lock),
+ bool (*teth_port_state)(void), u32 ipa_ep_idx);
+
+void ipa_deregister_client_callback(u32 ipa_ep_idx);
+
#endif /* _IPA_COMMON_I_H_ */
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c
index da6be7e..23e0bf7 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c
@@ -2881,16 +2881,6 @@ void ipa3_q6_pre_shutdown_cleanup(void)
ipa3_q6_pipe_delay(false);
ipa3_set_reset_client_prod_pipe_delay(true,
IPA_CLIENT_USB_PROD);
- if (ipa3_ctx->ipa_config_is_auto)
- ipa3_set_reset_client_prod_pipe_delay(true,
- IPA_CLIENT_USB2_PROD);
- if (ipa3_ctx->ipa_config_is_mhi) {
- ipa3_set_reset_client_prod_pipe_delay(true,
- IPA_CLIENT_MHI_PROD);
- if (ipa3_ctx->ipa_config_is_auto)
- ipa3_set_reset_client_prod_pipe_delay(true,
- IPA_CLIENT_MHI2_PROD);
- }
IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
IPADBG_LOW("Exit with success\n");
@@ -2950,6 +2940,34 @@ void ipa3_q6_post_shutdown_cleanup(void)
IPADBG_LOW("Exit with success\n");
}
+/**
+ * ipa3_q6_pre_powerup_cleanup() - A cleanup routine for pheripheral
+ * configuration in IPA HW. This is performed in case of SSR.
+ *
+ * This is a mandatory procedure, in case one of the steps fails, the
+ * AP needs to restart.
+ */
+void ipa3_q6_pre_powerup_cleanup(void)
+{
+ IPADBG_LOW("ENTER\n");
+
+ IPA_ACTIVE_CLIENTS_INC_SIMPLE();
+
+ if (ipa3_ctx->ipa_config_is_auto)
+ ipa3_set_reset_client_prod_pipe_delay(true,
+ IPA_CLIENT_USB2_PROD);
+ if (ipa3_ctx->ipa_config_is_mhi) {
+ ipa3_set_reset_client_prod_pipe_delay(true,
+ IPA_CLIENT_MHI_PROD);
+ if (ipa3_ctx->ipa_config_is_auto)
+ ipa3_set_reset_client_prod_pipe_delay(true,
+ IPA_CLIENT_MHI2_PROD);
+ }
+
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+ IPADBG_LOW("Exit with success\n");
+}
+
static inline void ipa3_sram_set_canary(u32 *sram_mmio, int offset)
{
/* Set 4 bytes of CANARY before the offset */
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_client.c b/drivers/platform/msm/ipa/ipa_v3/ipa_client.c
index b9a4283..a9c1899 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_client.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_client.c
@@ -644,66 +644,84 @@ int ipa3_smmu_map_peer_buff(u64 iova, u32 size, bool map, struct sg_table *sgt,
return 0;
}
-void ipa3_register_lock_unlock_callback(int (*client_cb)(bool is_lock),
- u32 ipa_ep_idx)
+static enum ipa_client_cb_type ipa_get_client_cb_type(
+ enum ipa_client_type client_type)
{
- struct ipa3_ep_context *ep;
+ enum ipa_client_cb_type client_cb;
+
+ if (client_type == IPA_CLIENT_USB_PROD ||
+ client_type == IPA_CLIENT_USB_CONS) {
+ IPADBG("USB Client registered\n");
+ client_cb = IPA_USB_CLNT;
+ } else if (client_type == IPA_CLIENT_MHI_PROD ||
+ client_type == IPA_CLIENT_MHI_CONS) {
+ IPADBG("MHI Client registered\n");
+ client_cb = IPA_MHI_CLNT;
+ } else {
+ IPAERR("Invalid IPA client\n");
+ client_cb = IPA_MAX_CLNT;
+ }
+
+ return client_cb;
+}
+void ipa3_register_client_callback(int (*client_cb)(bool is_lock),
+ bool (*teth_port_state)(void),
+ enum ipa_client_type client_type)
+{
+ enum ipa_client_cb_type client;
IPADBG("entry\n");
- ep = &ipa3_ctx->ep[ipa_ep_idx];
-
- if (!ep->valid) {
- IPAERR("Invalid EP\n");
+ client = ipa_get_client_cb_type(client_type);
+ if (client == IPA_MAX_CLNT)
return;
- }
if (client_cb == NULL) {
IPAERR("Bad Param");
return;
}
- ep->client_lock_unlock = client_cb;
+ if (!ipa3_ctx->client_lock_unlock[client])
+ ipa3_ctx->client_lock_unlock[client] = client_cb;
+
+ if (!ipa3_ctx->get_teth_port_state[client])
+ ipa3_ctx->get_teth_port_state[client] = teth_port_state;
IPADBG("exit\n");
}
-void ipa3_deregister_lock_unlock_callback(u32 ipa_ep_idx)
+void ipa3_deregister_client_callback(enum ipa_client_type client_type)
{
- struct ipa3_ep_context *ep;
+ enum ipa_client_cb_type client_cb;
IPADBG("entry\n");
- ep = &ipa3_ctx->ep[ipa_ep_idx];
-
- if (!ep->valid) {
- IPAERR("Invalid EP\n");
+ client_cb = ipa_get_client_cb_type(client_type);
+ if (client_cb == IPA_MAX_CLNT)
return;
- }
- if (ep->client_lock_unlock == NULL) {
+ if (ipa3_ctx->client_lock_unlock[client_cb] == NULL &&
+ ipa3_ctx->get_teth_port_state[client_cb] == NULL) {
IPAERR("client_lock_unlock is already NULL");
return;
}
- ep->client_lock_unlock = NULL;
+ ipa3_ctx->client_lock_unlock[client_cb] = NULL;
+ ipa3_ctx->get_teth_port_state[client_cb] = NULL;
IPADBG("exit\n");
}
-static void client_lock_unlock_cb(u32 ipa_ep_idx, bool is_lock)
+static void client_lock_unlock_cb(enum ipa_client_type client, bool is_lock)
{
- struct ipa3_ep_context *ep;
+ enum ipa_client_cb_type client_cb;
IPADBG("entry\n");
- ep = &ipa3_ctx->ep[ipa_ep_idx];
-
- if (!ep->valid) {
- IPAERR("Invalid EP\n");
+ client_cb = ipa_get_client_cb_type(client);
+ if (client_cb == IPA_MAX_CLNT)
return;
- }
- if (ep->client_lock_unlock)
- ep->client_lock_unlock(is_lock);
+ if (ipa3_ctx->client_lock_unlock[client_cb])
+ ipa3_ctx->client_lock_unlock[client_cb](is_lock);
IPADBG("exit\n");
}
@@ -780,6 +798,13 @@ int ipa3_request_gsi_channel(struct ipa_request_gsi_channel_params *params,
IPADBG("ep configuration successful\n");
} else {
IPADBG("Skipping endpoint configuration.\n");
+ if (IPA_CLIENT_IS_PROD(ipa3_ctx->ep[ipa_ep_idx].client) &&
+ ipa3_ctx->ep[ipa_ep_idx].client == IPA_CLIENT_USB_PROD)
+ if (ipa3_cfg_ep_seq(ipa_ep_idx,
+ ¶ms->ipa_ep_cfg.seq)) {
+ IPAERR("fail to configure USB pipe seq\n");
+ goto ipa_cfg_ep_fail;
+ }
}
out_params->clnt_hdl = ipa_ep_idx;
@@ -1366,7 +1391,7 @@ int ipa3_set_reset_client_prod_pipe_delay(bool set_reset,
ep = &ipa3_ctx->ep[pipe_idx];
/* Setting delay on USB_PROD with skip_ep_cfg */
- client_lock_unlock_cb(pipe_idx, true);
+ client_lock_unlock_cb(client, true);
if (ep->valid && ep->skip_ep_cfg) {
ep->ep_delay_set = ep_ctrl.ipa_ep_delay;
result = ipa3_cfg_ep_ctrl(pipe_idx, &ep_ctrl);
@@ -1376,7 +1401,7 @@ int ipa3_set_reset_client_prod_pipe_delay(bool set_reset,
else
IPADBG("client (ep: %d) success\n", pipe_idx);
}
- client_lock_unlock_cb(pipe_idx, false);
+ client_lock_unlock_cb(client, false);
return result;
}
@@ -1409,7 +1434,7 @@ int ipa3_set_reset_client_cons_pipe_sus_holb(bool set_reset,
ep = &ipa3_ctx->ep[pipe_idx];
/* Setting sus/holb on MHI_CONS with skip_ep_cfg */
- client_lock_unlock_cb(pipe_idx, true);
+ client_lock_unlock_cb(client, true);
if (ep->valid && ep->skip_ep_cfg) {
if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_0)
ipahal_write_reg_n_fields(
@@ -1428,7 +1453,7 @@ int ipa3_set_reset_client_cons_pipe_sus_holb(bool set_reset,
IPA_ENDP_INIT_HOL_BLOCK_EN_n,
pipe_idx, &ep_holb);
}
- client_lock_unlock_cb(pipe_idx, false);
+ client_lock_unlock_cb(client, false);
return 0;
}
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h
index 277b637..4c63959 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h
@@ -782,8 +782,6 @@ struct ipa3_ep_context {
u32 eot_in_poll_err;
bool ep_delay_set;
- int (*client_lock_unlock)(bool is_lock);
-
/* sys MUST be the last element of this struct */
struct ipa3_sys_context *sys;
};
@@ -1377,6 +1375,12 @@ enum ipa_smmu_cb_type {
IPA_SMMU_CB_MAX
};
+enum ipa_client_cb_type {
+ IPA_USB_CLNT,
+ IPA_MHI_CLNT,
+ IPA_MAX_CLNT
+};
+
/**
* struct ipa3_char_device_context - IPA character device
* @class: pointer to the struct class
@@ -1620,6 +1624,8 @@ struct ipa3_context {
bool vlan_mode_iface[IPA_VLAN_IF_MAX];
bool wdi_over_pcie;
bool fw_loaded;
+ int (*client_lock_unlock[IPA_MAX_CLNT])(bool is_lock);
+ bool (*get_teth_port_state[IPA_MAX_CLNT])(void);
};
struct ipa3_plat_drv_res {
@@ -1937,8 +1943,10 @@ int ipa3_xdci_connect(u32 clnt_hdl);
int ipa3_xdci_disconnect(u32 clnt_hdl, bool should_force_clear, u32 qmi_req_id);
void ipa3_xdci_ep_delay_rm(u32 clnt_hdl);
-void ipa3_register_lock_unlock_callback(int (*client_cb)(bool), u32 ipa_ep_idx);
-void ipa3_deregister_lock_unlock_callback(u32 ipa_ep_idx);
+void ipa3_register_client_callback(int (*client_cb)(bool),
+ bool (*teth_port_state)(void),
+ enum ipa_client_type client_type);
+void ipa3_deregister_client_callback(enum ipa_client_type client_type);
int ipa3_set_reset_client_prod_pipe_delay(bool set_reset,
enum ipa_client_type client);
int ipa3_set_reset_client_cons_pipe_sus_holb(bool set_reset,
@@ -1959,6 +1967,8 @@ int ipa3_clear_endpoint_delay(u32 clnt_hdl);
*/
int ipa3_cfg_ep(u32 clnt_hdl, const struct ipa_ep_cfg *ipa_ep_cfg);
+int ipa3_cfg_ep_seq(u32 clnt_hdl, const struct ipa_ep_cfg_seq *seq_cfg);
+
int ipa3_cfg_ep_nat(u32 clnt_hdl, const struct ipa_ep_cfg_nat *ipa_ep_cfg);
int ipa3_cfg_ep_conn_track(u32 clnt_hdl,
@@ -2290,6 +2300,7 @@ void ipa3_proxy_clk_unvote(void);
bool ipa3_is_client_handle_valid(u32 clnt_hdl);
enum ipa_client_type ipa3_get_client_mapping(int pipe_idx);
+enum ipa_client_type ipa3_get_client_by_pipe(int pipe_idx);
void ipa_init_ep_flt_bitmap(void);
@@ -2437,6 +2448,7 @@ int ipa3_tag_process(struct ipa3_desc *desc, int num_descs,
void ipa3_q6_pre_shutdown_cleanup(void);
void ipa3_q6_post_shutdown_cleanup(void);
+void ipa3_q6_pre_powerup_cleanup(void);
int ipa3_init_q6_smem(void);
int ipa3_mhi_handle_ipa_config_req(struct ipa_config_req_msg_v01 *config_req);
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
index 4166392..1ec3d7e 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
@@ -2888,7 +2888,7 @@ enum ipa_client_type ipa3_get_client_mapping(int pipe_idx)
*
* Return value: client type
*/
-static enum ipa_client_type ipa3_get_client_by_pipe(int pipe_idx)
+enum ipa_client_type ipa3_get_client_by_pipe(int pipe_idx)
{
int j = 0;
@@ -5134,7 +5134,10 @@ int ipa3_bind_api_controller(enum ipa_hw_type ipa_hw_type,
api_ctrl->ipa_is_vlan_mode = ipa3_is_vlan_mode;
api_ctrl->ipa_pm_is_used = ipa3_pm_is_used;
api_ctrl->ipa_get_lan_rx_napi = ipa3_get_lan_rx_napi;
-
+ api_ctrl->ipa_register_client_callback =
+ ipa3_register_client_callback;
+ api_ctrl->ipa_deregister_client_callback =
+ ipa3_deregister_client_callback;
return 0;
}
diff --git a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c
index 6a477f2..bc107d8 100644
--- a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c
+++ b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c
@@ -2730,9 +2730,11 @@ static int ipa3_ssr_notifier_cb(struct notifier_block *this,
break;
case SUBSYS_BEFORE_POWERUP:
IPAWANINFO("IPA received MPSS BEFORE_POWERUP\n");
- if (atomic_read(&rmnet_ipa3_ctx->is_ssr))
+ if (atomic_read(&rmnet_ipa3_ctx->is_ssr)) {
/* clean up cached QMI msg/handlers */
ipa3_qmi_service_exit();
+ ipa3_q6_pre_powerup_cleanup();
+ }
/*
* hold a proxy vote for the modem.
* for IPA 4.0 offline charge is not needed and proxy vote
diff --git a/drivers/platform/x86/hp-wmi.c b/drivers/platform/x86/hp-wmi.c
index 05dc16b..f065529 100644
--- a/drivers/platform/x86/hp-wmi.c
+++ b/drivers/platform/x86/hp-wmi.c
@@ -308,7 +308,7 @@ static int __init hp_wmi_bios_2008_later(void)
static int __init hp_wmi_bios_2009_later(void)
{
- int state = 0;
+ u8 state[128];
int ret = hp_wmi_perform_query(HPWMI_FEATURE2_QUERY, 0, &state,
sizeof(state), sizeof(state));
if (!ret)
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index c56a99f..0d81304 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -4859,7 +4859,7 @@ static int __init regulator_init(void)
/* init early to allow our consumers to complete system booting */
core_initcall(regulator_init);
-static int regulator_late_cleanup(struct device *dev, void *data)
+static int __init regulator_late_cleanup(struct device *dev, void *data)
{
struct regulator_dev *rdev = dev_to_rdev(dev);
const struct regulator_ops *ops = rdev->desc->ops;
@@ -4908,9 +4908,18 @@ static int regulator_late_cleanup(struct device *dev, void *data)
return 0;
}
-static void regulator_init_complete_work_function(struct work_struct *work)
+static int __init regulator_init_complete(void)
{
/*
+ * Since DT doesn't provide an idiomatic mechanism for
+ * enabling full constraints and since it's much more natural
+ * with DT to provide them just assume that a DT enabled
+ * system has full constraints.
+ */
+ if (of_have_populated_dt())
+ has_full_constraints = true;
+
+ /*
* Regulators may had failed to resolve their input supplies
* when were registered, either because the input supply was
* not registered yet or because its parent device was not
@@ -4927,35 +4936,6 @@ static void regulator_init_complete_work_function(struct work_struct *work)
*/
class_for_each_device(®ulator_class, NULL, NULL,
regulator_late_cleanup);
-}
-
-static DECLARE_DELAYED_WORK(regulator_init_complete_work,
- regulator_init_complete_work_function);
-
-static int __init regulator_init_complete(void)
-{
- /*
- * Since DT doesn't provide an idiomatic mechanism for
- * enabling full constraints and since it's much more natural
- * with DT to provide them just assume that a DT enabled
- * system has full constraints.
- */
- if (of_have_populated_dt())
- has_full_constraints = true;
-
- /*
- * We punt completion for an arbitrary amount of time since
- * systems like distros will load many drivers from userspace
- * so consumers might not always be ready yet, this is
- * particularly an issue with laptops where this might bounce
- * the display off then on. Ideally we'd get a notification
- * from userspace when this happens but we don't so just wait
- * a bit and hope we waited long enough. It'd be better if
- * we'd only do this on systems that need it, and a kernel
- * command line option might be useful.
- */
- schedule_delayed_work(®ulator_init_complete_work,
- msecs_to_jiffies(30000));
return 0;
}
diff --git a/drivers/regulator/max8907-regulator.c b/drivers/regulator/max8907-regulator.c
index 5e941db..c7e70cfb 100644
--- a/drivers/regulator/max8907-regulator.c
+++ b/drivers/regulator/max8907-regulator.c
@@ -299,7 +299,10 @@ static int max8907_regulator_probe(struct platform_device *pdev)
memcpy(pmic->desc, max8907_regulators, sizeof(pmic->desc));
/* Backwards compatibility with MAX8907B; SD1 uses different voltages */
- regmap_read(max8907->regmap_gen, MAX8907_REG_II2RR, &val);
+ ret = regmap_read(max8907->regmap_gen, MAX8907_REG_II2RR, &val);
+ if (ret)
+ return ret;
+
if ((val & MAX8907_II2RR_VERSION_MASK) ==
MAX8907_II2RR_VERSION_REV_B) {
pmic->desc[MAX8907_SD1].min_uV = 637500;
@@ -336,14 +339,20 @@ static int max8907_regulator_probe(struct platform_device *pdev)
}
if (pmic->desc[i].ops == &max8907_ldo_ops) {
- regmap_read(config.regmap, pmic->desc[i].enable_reg,
+ ret = regmap_read(config.regmap, pmic->desc[i].enable_reg,
&val);
+ if (ret)
+ return ret;
+
if ((val & MAX8907_MASK_LDO_SEQ) !=
MAX8907_MASK_LDO_SEQ)
pmic->desc[i].ops = &max8907_ldo_hwctl_ops;
} else if (pmic->desc[i].ops == &max8907_out5v_ops) {
- regmap_read(config.regmap, pmic->desc[i].enable_reg,
+ ret = regmap_read(config.regmap, pmic->desc[i].enable_reg,
&val);
+ if (ret)
+ return ret;
+
if ((val & (MAX8907_MASK_OUT5V_VINEN |
MAX8907_MASK_OUT5V_ENSRC)) !=
MAX8907_MASK_OUT5V_ENSRC)
diff --git a/drivers/rtc/rtc-max8997.c b/drivers/rtc/rtc-max8997.c
index db984d4..4cce5bd 100644
--- a/drivers/rtc/rtc-max8997.c
+++ b/drivers/rtc/rtc-max8997.c
@@ -221,7 +221,7 @@ static int max8997_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
out:
mutex_unlock(&info->lock);
- return 0;
+ return ret;
}
static int max8997_rtc_stop_alarm(struct max8997_rtc_info *info)
diff --git a/drivers/s390/scsi/zfcp_dbf.c b/drivers/s390/scsi/zfcp_dbf.c
index b6caad0..c53ea0a 100644
--- a/drivers/s390/scsi/zfcp_dbf.c
+++ b/drivers/s390/scsi/zfcp_dbf.c
@@ -93,11 +93,9 @@ void zfcp_dbf_hba_fsf_res(char *tag, int level, struct zfcp_fsf_req *req)
memcpy(rec->u.res.fsf_status_qual, &q_head->fsf_status_qual,
FSF_STATUS_QUALIFIER_SIZE);
- if (req->fsf_command != FSF_QTCB_FCP_CMND) {
- rec->pl_len = q_head->log_length;
- zfcp_dbf_pl_write(dbf, (char *)q_pref + q_head->log_start,
- rec->pl_len, "fsf_res", req->req_id);
- }
+ rec->pl_len = q_head->log_length;
+ zfcp_dbf_pl_write(dbf, (char *)q_pref + q_head->log_start,
+ rec->pl_len, "fsf_res", req->req_id);
debug_event(dbf->hba, level, rec, sizeof(*rec));
spin_unlock_irqrestore(&dbf->hba_lock, flags);
diff --git a/drivers/s390/scsi/zfcp_erp.c b/drivers/s390/scsi/zfcp_erp.c
index cc62d8c..d5214c4 100644
--- a/drivers/s390/scsi/zfcp_erp.c
+++ b/drivers/s390/scsi/zfcp_erp.c
@@ -178,9 +178,6 @@ static int zfcp_erp_handle_failed(int want, struct zfcp_adapter *adapter,
adapter, ZFCP_STATUS_COMMON_ERP_FAILED);
}
break;
- default:
- need = 0;
- break;
}
return need;
diff --git a/drivers/scsi/atari_scsi.c b/drivers/scsi/atari_scsi.c
index a59ad94..9dc4b68 100644
--- a/drivers/scsi/atari_scsi.c
+++ b/drivers/scsi/atari_scsi.c
@@ -753,7 +753,7 @@ static int __init atari_scsi_probe(struct platform_device *pdev)
atari_scsi_template.sg_tablesize = SG_ALL;
} else {
atari_scsi_template.can_queue = 1;
- atari_scsi_template.sg_tablesize = SG_NONE;
+ atari_scsi_template.sg_tablesize = 1;
}
if (setup_can_queue > 0)
@@ -762,8 +762,8 @@ static int __init atari_scsi_probe(struct platform_device *pdev)
if (setup_cmd_per_lun > 0)
atari_scsi_template.cmd_per_lun = setup_cmd_per_lun;
- /* Leave sg_tablesize at 0 on a Falcon! */
- if (ATARIHW_PRESENT(TT_SCSI) && setup_sg_tablesize >= 0)
+ /* Don't increase sg_tablesize on Falcon! */
+ if (ATARIHW_PRESENT(TT_SCSI) && setup_sg_tablesize > 0)
atari_scsi_template.sg_tablesize = setup_sg_tablesize;
if (setup_hostid >= 0) {
diff --git a/drivers/scsi/csiostor/csio_lnode.c b/drivers/scsi/csiostor/csio_lnode.c
index be5ee2d..957767d 100644
--- a/drivers/scsi/csiostor/csio_lnode.c
+++ b/drivers/scsi/csiostor/csio_lnode.c
@@ -301,6 +301,7 @@ csio_ln_fdmi_rhba_cbfn(struct csio_hw *hw, struct csio_ioreq *fdmi_req)
struct fc_fdmi_port_name *port_name;
uint8_t buf[64];
uint8_t *fc4_type;
+ unsigned long flags;
if (fdmi_req->wr_status != FW_SUCCESS) {
csio_ln_dbg(ln, "WR error:%x in processing fdmi rhba cmd\n",
@@ -377,13 +378,13 @@ csio_ln_fdmi_rhba_cbfn(struct csio_hw *hw, struct csio_ioreq *fdmi_req)
len = (uint32_t)(pld - (uint8_t *)cmd);
/* Submit FDMI RPA request */
- spin_lock_irq(&hw->lock);
+ spin_lock_irqsave(&hw->lock, flags);
if (csio_ln_mgmt_submit_req(fdmi_req, csio_ln_fdmi_done,
FCOE_CT, &fdmi_req->dma_buf, len)) {
CSIO_INC_STATS(ln, n_fdmi_err);
csio_ln_dbg(ln, "Failed to issue fdmi rpa req\n");
}
- spin_unlock_irq(&hw->lock);
+ spin_unlock_irqrestore(&hw->lock, flags);
}
/*
@@ -404,6 +405,7 @@ csio_ln_fdmi_dprt_cbfn(struct csio_hw *hw, struct csio_ioreq *fdmi_req)
struct fc_fdmi_rpl *reg_pl;
struct fs_fdmi_attrs *attrib_blk;
uint8_t buf[64];
+ unsigned long flags;
if (fdmi_req->wr_status != FW_SUCCESS) {
csio_ln_dbg(ln, "WR error:%x in processing fdmi dprt cmd\n",
@@ -483,13 +485,13 @@ csio_ln_fdmi_dprt_cbfn(struct csio_hw *hw, struct csio_ioreq *fdmi_req)
attrib_blk->numattrs = htonl(numattrs);
/* Submit FDMI RHBA request */
- spin_lock_irq(&hw->lock);
+ spin_lock_irqsave(&hw->lock, flags);
if (csio_ln_mgmt_submit_req(fdmi_req, csio_ln_fdmi_rhba_cbfn,
FCOE_CT, &fdmi_req->dma_buf, len)) {
CSIO_INC_STATS(ln, n_fdmi_err);
csio_ln_dbg(ln, "Failed to issue fdmi rhba req\n");
}
- spin_unlock_irq(&hw->lock);
+ spin_unlock_irqrestore(&hw->lock, flags);
}
/*
@@ -504,6 +506,7 @@ csio_ln_fdmi_dhba_cbfn(struct csio_hw *hw, struct csio_ioreq *fdmi_req)
void *cmd;
struct fc_fdmi_port_name *port_name;
uint32_t len;
+ unsigned long flags;
if (fdmi_req->wr_status != FW_SUCCESS) {
csio_ln_dbg(ln, "WR error:%x in processing fdmi dhba cmd\n",
@@ -534,13 +537,13 @@ csio_ln_fdmi_dhba_cbfn(struct csio_hw *hw, struct csio_ioreq *fdmi_req)
len += sizeof(*port_name);
/* Submit FDMI request */
- spin_lock_irq(&hw->lock);
+ spin_lock_irqsave(&hw->lock, flags);
if (csio_ln_mgmt_submit_req(fdmi_req, csio_ln_fdmi_dprt_cbfn,
FCOE_CT, &fdmi_req->dma_buf, len)) {
CSIO_INC_STATS(ln, n_fdmi_err);
csio_ln_dbg(ln, "Failed to issue fdmi dprt req\n");
}
- spin_unlock_irq(&hw->lock);
+ spin_unlock_irqrestore(&hw->lock, flags);
}
/**
diff --git a/drivers/scsi/libiscsi.c b/drivers/scsi/libiscsi.c
index 2ffe104..c4336b0 100644
--- a/drivers/scsi/libiscsi.c
+++ b/drivers/scsi/libiscsi.c
@@ -1982,7 +1982,7 @@ static enum blk_eh_timer_return iscsi_eh_cmd_timed_out(struct scsi_cmnd *sc)
ISCSI_DBG_EH(session, "scsi cmd %p timedout\n", sc);
- spin_lock(&session->frwd_lock);
+ spin_lock_bh(&session->frwd_lock);
task = (struct iscsi_task *)sc->SCp.ptr;
if (!task) {
/*
@@ -2109,7 +2109,7 @@ static enum blk_eh_timer_return iscsi_eh_cmd_timed_out(struct scsi_cmnd *sc)
done:
if (task)
task->last_timeout = jiffies;
- spin_unlock(&session->frwd_lock);
+ spin_unlock_bh(&session->frwd_lock);
ISCSI_DBG_EH(session, "return %s\n", rc == BLK_EH_RESET_TIMER ?
"timer reset" : "shutdown or nh");
return rc;
diff --git a/drivers/scsi/lpfc/lpfc.h b/drivers/scsi/lpfc/lpfc.h
index b484859..f0f6d71 100644
--- a/drivers/scsi/lpfc/lpfc.h
+++ b/drivers/scsi/lpfc/lpfc.h
@@ -878,7 +878,8 @@ struct lpfc_hba {
struct list_head port_list;
struct lpfc_vport *pport; /* physical lpfc_vport pointer */
uint16_t max_vpi; /* Maximum virtual nports */
-#define LPFC_MAX_VPI 0xFFFF /* Max number of VPI supported */
+#define LPFC_MAX_VPI 0xFF /* Max number VPI supported 0 - 0xff */
+#define LPFC_MAX_VPORTS 0x100 /* Max vports per port, with pport */
uint16_t max_vports; /*
* For IOV HBAs max_vpi can change
* after a reset. max_vports is max
diff --git a/drivers/scsi/lpfc/lpfc_attr.c b/drivers/scsi/lpfc/lpfc_attr.c
index cf15b97..aa0435b 100644
--- a/drivers/scsi/lpfc/lpfc_attr.c
+++ b/drivers/scsi/lpfc/lpfc_attr.c
@@ -1214,6 +1214,9 @@ lpfc_get_hba_info(struct lpfc_hba *phba,
max_vpi = (bf_get(lpfc_mbx_rd_conf_vpi_count, rd_config) > 0) ?
(bf_get(lpfc_mbx_rd_conf_vpi_count, rd_config) - 1) : 0;
+ /* Limit the max we support */
+ if (max_vpi > LPFC_MAX_VPI)
+ max_vpi = LPFC_MAX_VPI;
if (mvpi)
*mvpi = max_vpi;
if (avpi)
@@ -1229,8 +1232,13 @@ lpfc_get_hba_info(struct lpfc_hba *phba,
*axri = pmb->un.varRdConfig.avail_xri;
if (mvpi)
*mvpi = pmb->un.varRdConfig.max_vpi;
- if (avpi)
- *avpi = pmb->un.varRdConfig.avail_vpi;
+ if (avpi) {
+ /* avail_vpi is only valid if link is up and ready */
+ if (phba->link_state == LPFC_HBA_READY)
+ *avpi = pmb->un.varRdConfig.avail_vpi;
+ else
+ *avpi = pmb->un.varRdConfig.max_vpi;
+ }
}
mempool_free(pmboxq, phba->mbox_mem_pool);
diff --git a/drivers/scsi/lpfc/lpfc_els.c b/drivers/scsi/lpfc/lpfc_els.c
index 3702497..4901bf2 100644
--- a/drivers/scsi/lpfc/lpfc_els.c
+++ b/drivers/scsi/lpfc/lpfc_els.c
@@ -3863,7 +3863,7 @@ lpfc_cmpl_els_rsp(struct lpfc_hba *phba, struct lpfc_iocbq *cmdiocb,
mempool_free(mbox, phba->mbox_mem_pool);
}
out:
- if (ndlp && NLP_CHK_NODE_ACT(ndlp)) {
+ if (ndlp && NLP_CHK_NODE_ACT(ndlp) && shost) {
spin_lock_irq(shost->host_lock);
ndlp->nlp_flag &= ~(NLP_ACC_REGLOGIN | NLP_RM_DFLT_RPI);
spin_unlock_irq(shost->host_lock);
diff --git a/drivers/scsi/lpfc/lpfc_init.c b/drivers/scsi/lpfc/lpfc_init.c
index 2f80b2c..8c640bc 100644
--- a/drivers/scsi/lpfc/lpfc_init.c
+++ b/drivers/scsi/lpfc/lpfc_init.c
@@ -6973,6 +6973,9 @@ lpfc_sli4_read_config(struct lpfc_hba *phba)
bf_get(lpfc_mbx_rd_conf_xri_base, rd_config);
phba->sli4_hba.max_cfg_param.max_vpi =
bf_get(lpfc_mbx_rd_conf_vpi_count, rd_config);
+ /* Limit the max we support */
+ if (phba->sli4_hba.max_cfg_param.max_vpi > LPFC_MAX_VPORTS)
+ phba->sli4_hba.max_cfg_param.max_vpi = LPFC_MAX_VPORTS;
phba->sli4_hba.max_cfg_param.vpi_base =
bf_get(lpfc_mbx_rd_conf_vpi_base, rd_config);
phba->sli4_hba.max_cfg_param.max_rpi =
diff --git a/drivers/scsi/lpfc/lpfc_nportdisc.c b/drivers/scsi/lpfc/lpfc_nportdisc.c
index 21ec7b5..fefef28 100644
--- a/drivers/scsi/lpfc/lpfc_nportdisc.c
+++ b/drivers/scsi/lpfc/lpfc_nportdisc.c
@@ -454,8 +454,10 @@ lpfc_rcv_plogi(struct lpfc_vport *vport, struct lpfc_nodelist *ndlp,
* single discovery thread, this will cause a huge delay in
* discovery. Also this will cause multiple state machines
* running in parallel for this node.
+ * This only applies to a fabric environment.
*/
- if (ndlp->nlp_state == NLP_STE_PLOGI_ISSUE) {
+ if ((ndlp->nlp_state == NLP_STE_PLOGI_ISSUE) &&
+ (vport->fc_flag & FC_FABRIC)) {
/* software abort outstanding PLOGI */
lpfc_els_abort(phba, ndlp);
}
diff --git a/drivers/scsi/lpfc/lpfc_sli.c b/drivers/scsi/lpfc/lpfc_sli.c
index e1e0feb..cbe808e 100644
--- a/drivers/scsi/lpfc/lpfc_sli.c
+++ b/drivers/scsi/lpfc/lpfc_sli.c
@@ -11962,13 +11962,19 @@ lpfc_sli4_sp_handle_mbox_event(struct lpfc_hba *phba, struct lpfc_mcqe *mcqe)
phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
/* Setting active mailbox pointer need to be in sync to flag clear */
phba->sli.mbox_active = NULL;
+ if (bf_get(lpfc_trailer_consumed, mcqe))
+ lpfc_sli4_mq_release(phba->sli4_hba.mbx_wq);
spin_unlock_irqrestore(&phba->hbalock, iflags);
/* Wake up worker thread to post the next pending mailbox command */
lpfc_worker_wake_up(phba);
+ return workposted;
+
out_no_mqe_complete:
+ spin_lock_irqsave(&phba->hbalock, iflags);
if (bf_get(lpfc_trailer_consumed, mcqe))
lpfc_sli4_mq_release(phba->sli4_hba.mbx_wq);
- return workposted;
+ spin_unlock_irqrestore(&phba->hbalock, iflags);
+ return false;
}
/**
@@ -15989,6 +15995,13 @@ lpfc_sli4_alloc_rpi(struct lpfc_hba *phba)
static void
__lpfc_sli4_free_rpi(struct lpfc_hba *phba, int rpi)
{
+ /*
+ * if the rpi value indicates a prior unreg has already
+ * been done, skip the unreg.
+ */
+ if (rpi == LPFC_RPI_ALLOC_ERROR)
+ return;
+
if (test_and_clear_bit(rpi, phba->sli4_hba.rpi_bmask)) {
phba->sli4_hba.rpi_count--;
phba->sli4_hba.max_cfg_param.rpi_used--;
diff --git a/drivers/scsi/mac_scsi.c b/drivers/scsi/mac_scsi.c
index 5648d30..5aa60bb 100644
--- a/drivers/scsi/mac_scsi.c
+++ b/drivers/scsi/mac_scsi.c
@@ -378,7 +378,7 @@ static int __init mac_scsi_probe(struct platform_device *pdev)
mac_scsi_template.can_queue = setup_can_queue;
if (setup_cmd_per_lun > 0)
mac_scsi_template.cmd_per_lun = setup_cmd_per_lun;
- if (setup_sg_tablesize >= 0)
+ if (setup_sg_tablesize > 0)
mac_scsi_template.sg_tablesize = setup_sg_tablesize;
if (setup_hostid >= 0)
mac_scsi_template.this_id = setup_hostid & 7;
diff --git a/drivers/scsi/mpt3sas/mpt3sas_ctl.c b/drivers/scsi/mpt3sas/mpt3sas_ctl.c
index 26cdc12..90a87e5 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_ctl.c
+++ b/drivers/scsi/mpt3sas/mpt3sas_ctl.c
@@ -1465,7 +1465,8 @@ _ctl_diag_register_2(struct MPT3SAS_ADAPTER *ioc,
" for diag buffers, requested size(%d)\n",
ioc->name, __func__, request_data_sz);
mpt3sas_base_free_smid(ioc, smid);
- return -ENOMEM;
+ rc = -ENOMEM;
+ goto out;
}
ioc->diag_buffer[buffer_type] = request_data;
ioc->diag_buffer_sz[buffer_type] = request_data_sz;
diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c
index 9edd61c..df5f0bc 100644
--- a/drivers/scsi/pm8001/pm80xx_hwi.c
+++ b/drivers/scsi/pm8001/pm80xx_hwi.c
@@ -2368,6 +2368,8 @@ mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
pm8001_printk("task 0x%p done with io_status 0x%x"
" resp 0x%x stat 0x%x but aborted by upper layer!\n",
t, status, ts->resp, ts->stat));
+ if (t->slow_task)
+ complete(&t->slow_task->completion);
pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
} else {
spin_unlock_irqrestore(&t->task_state_lock, flags);
diff --git a/drivers/scsi/qla2xxx/qla_attr.c b/drivers/scsi/qla2xxx/qla_attr.c
index 5c3dfd9..33f4181 100644
--- a/drivers/scsi/qla2xxx/qla_attr.c
+++ b/drivers/scsi/qla2xxx/qla_attr.c
@@ -682,7 +682,8 @@ qla2x00_sysfs_write_reset(struct file *filp, struct kobject *kobj,
break;
} else {
/* Make sure FC side is not in reset */
- qla2x00_wait_for_hba_online(vha);
+ WARN_ON_ONCE(qla2x00_wait_for_hba_online(vha) !=
+ QLA_SUCCESS);
/* Issue MPI reset */
scsi_block_requests(vha->host);
diff --git a/drivers/scsi/qla2xxx/qla_bsg.c b/drivers/scsi/qla2xxx/qla_bsg.c
index 33e4dce..09f7a8c 100644
--- a/drivers/scsi/qla2xxx/qla_bsg.c
+++ b/drivers/scsi/qla2xxx/qla_bsg.c
@@ -336,6 +336,8 @@ qla2x00_process_els(struct fc_bsg_job *bsg_job)
dma_map_sg(&ha->pdev->dev, bsg_job->request_payload.sg_list,
bsg_job->request_payload.sg_cnt, DMA_TO_DEVICE);
if (!req_sg_cnt) {
+ dma_unmap_sg(&ha->pdev->dev, bsg_job->request_payload.sg_list,
+ bsg_job->request_payload.sg_cnt, DMA_TO_DEVICE);
rval = -ENOMEM;
goto done_free_fcport;
}
@@ -343,6 +345,8 @@ qla2x00_process_els(struct fc_bsg_job *bsg_job)
rsp_sg_cnt = dma_map_sg(&ha->pdev->dev, bsg_job->reply_payload.sg_list,
bsg_job->reply_payload.sg_cnt, DMA_FROM_DEVICE);
if (!rsp_sg_cnt) {
+ dma_unmap_sg(&ha->pdev->dev, bsg_job->reply_payload.sg_list,
+ bsg_job->reply_payload.sg_cnt, DMA_FROM_DEVICE);
rval = -ENOMEM;
goto done_free_fcport;
}
@@ -1740,8 +1744,8 @@ qla24xx_process_bidir_cmd(struct fc_bsg_job *bsg_job)
uint16_t nextlid = 0;
uint32_t tot_dsds;
srb_t *sp = NULL;
- uint32_t req_data_len = 0;
- uint32_t rsp_data_len = 0;
+ uint32_t req_data_len;
+ uint32_t rsp_data_len;
/* Check the type of the adapter */
if (!IS_BIDI_CAPABLE(ha)) {
@@ -1846,6 +1850,9 @@ qla24xx_process_bidir_cmd(struct fc_bsg_job *bsg_job)
goto done_unmap_sg;
}
+ req_data_len = bsg_job->request_payload.payload_len;
+ rsp_data_len = bsg_job->reply_payload.payload_len;
+
if (req_data_len != rsp_data_len) {
rval = EXT_STATUS_BUSY;
ql_log(ql_log_warn, vha, 0x70aa,
@@ -1853,10 +1860,6 @@ qla24xx_process_bidir_cmd(struct fc_bsg_job *bsg_job)
goto done_unmap_sg;
}
- req_data_len = bsg_job->request_payload.payload_len;
- rsp_data_len = bsg_job->reply_payload.payload_len;
-
-
/* Alloc SRB structure */
sp = qla2x00_get_sp(vha, &(vha->bidir_fcport), GFP_KERNEL);
if (!sp) {
diff --git a/drivers/scsi/qla2xxx/qla_target.c b/drivers/scsi/qla2xxx/qla_target.c
index d13e91e..b889caa 100644
--- a/drivers/scsi/qla2xxx/qla_target.c
+++ b/drivers/scsi/qla2xxx/qla_target.c
@@ -5893,7 +5893,6 @@ static void qlt_abort_work(struct qla_tgt *tgt,
struct qla_hw_data *ha = vha->hw;
struct qla_tgt_sess *sess = NULL;
unsigned long flags = 0, flags2 = 0;
- uint32_t be_s_id;
uint8_t s_id[3];
int rc;
@@ -5906,8 +5905,7 @@ static void qlt_abort_work(struct qla_tgt *tgt,
s_id[1] = prm->abts.fcp_hdr_le.s_id[1];
s_id[2] = prm->abts.fcp_hdr_le.s_id[0];
- sess = ha->tgt.tgt_ops->find_sess_by_s_id(vha,
- (unsigned char *)&be_s_id);
+ sess = ha->tgt.tgt_ops->find_sess_by_s_id(vha, s_id);
if (!sess) {
spin_unlock_irqrestore(&ha->tgt.sess_lock, flags2);
@@ -6343,7 +6341,8 @@ qlt_enable_vha(struct scsi_qla_host *vha)
set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
qla2xxx_wake_dpc(base_vha);
- qla2x00_wait_for_hba_online(base_vha);
+ WARN_ON_ONCE(qla2x00_wait_for_hba_online(base_vha) !=
+ QLA_SUCCESS);
}
}
EXPORT_SYMBOL(qlt_enable_vha);
@@ -6373,7 +6372,9 @@ static void qlt_disable_vha(struct scsi_qla_host *vha)
set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
qla2xxx_wake_dpc(vha);
- qla2x00_wait_for_hba_online(vha);
+ if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS)
+ ql_dbg(ql_dbg_tgt, vha, 0xe081,
+ "qla2x00_wait_for_hba_online() failed\n");
}
/*
diff --git a/drivers/scsi/scsi_debug.c b/drivers/scsi/scsi_debug.c
index 2b0e615..d7118d3 100644
--- a/drivers/scsi/scsi_debug.c
+++ b/drivers/scsi/scsi_debug.c
@@ -4953,6 +4953,11 @@ static int __init scsi_debug_init(void)
return -EINVAL;
}
+ if (sdebug_num_tgts < 0) {
+ pr_err("num_tgts must be >= 0\n");
+ return -EINVAL;
+ }
+
if (sdebug_guard > 1) {
pr_err("guard must be 0 or 1\n");
return -EINVAL;
diff --git a/drivers/scsi/scsi_trace.c b/drivers/scsi/scsi_trace.c
index 0ff083b..617a607 100644
--- a/drivers/scsi/scsi_trace.c
+++ b/drivers/scsi/scsi_trace.c
@@ -30,15 +30,18 @@ static const char *
scsi_trace_rw6(struct trace_seq *p, unsigned char *cdb, int len)
{
const char *ret = trace_seq_buffer_ptr(p);
- sector_t lba = 0, txlen = 0;
+ u32 lba = 0, txlen;
lba |= ((cdb[1] & 0x1F) << 16);
lba |= (cdb[2] << 8);
lba |= cdb[3];
- txlen = cdb[4];
+ /*
+ * From SBC-2: a TRANSFER LENGTH field set to zero specifies that 256
+ * logical blocks shall be read (READ(6)) or written (WRITE(6)).
+ */
+ txlen = cdb[4] ? cdb[4] : 256;
- trace_seq_printf(p, "lba=%llu txlen=%llu",
- (unsigned long long)lba, (unsigned long long)txlen);
+ trace_seq_printf(p, "lba=%u txlen=%u", lba, txlen);
trace_seq_putc(p, 0);
return ret;
diff --git a/drivers/scsi/sun3_scsi.c b/drivers/scsi/sun3_scsi.c
index 3c4c070..6f75693 100644
--- a/drivers/scsi/sun3_scsi.c
+++ b/drivers/scsi/sun3_scsi.c
@@ -419,7 +419,7 @@ static struct scsi_host_template sun3_scsi_template = {
.eh_bus_reset_handler = sun3scsi_bus_reset,
.can_queue = 16,
.this_id = 7,
- .sg_tablesize = SG_NONE,
+ .sg_tablesize = 1,
.cmd_per_lun = 2,
.use_clustering = DISABLE_CLUSTERING,
.cmd_size = NCR5380_CMD_SIZE,
@@ -440,7 +440,7 @@ static int __init sun3_scsi_probe(struct platform_device *pdev)
sun3_scsi_template.can_queue = setup_can_queue;
if (setup_cmd_per_lun > 0)
sun3_scsi_template.cmd_per_lun = setup_cmd_per_lun;
- if (setup_sg_tablesize >= 0)
+ if (setup_sg_tablesize > 0)
sun3_scsi_template.sg_tablesize = setup_sg_tablesize;
if (setup_hostid >= 0)
sun3_scsi_template.this_id = setup_hostid & 7;
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 080fbed..91403f0 100755
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -3792,10 +3792,10 @@ static int __ufshcd_query_descriptor(struct ufs_hba *hba,
goto out_unlock;
}
- hba->dev_cmd.query.descriptor = NULL;
*buf_len = be16_to_cpu(response->upiu_res.length);
out_unlock:
+ hba->dev_cmd.query.descriptor = NULL;
mutex_unlock(&hba->dev_cmd.lock);
if (has_read_lock)
up_read(&hba->lock);
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index cbf1734..6a6fc8c 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -274,6 +274,16 @@
If unsure, say N.
+config SDX_EXT_IPC
+ tristate "QCOM external ipc driver"
+ help
+ This enables the module to help modem communicate with external
+ Application processor connected to Qualcomm Technologies, Inc
+ modem chipset. The modem and APQ can understand each other's
+ state by reading ipc gpios.
+
+ If unsure, say N.
+
config PANIC_ON_GLADIATOR_ERROR
depends on MSM_GLADIATOR_ERP
bool "Panic on GLADIATOR error report"
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index 1dda5d1..c61594b 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -78,6 +78,7 @@
obj-$(CONFIG_MSM_BGCOM) += bgcom_spi.o
obj-$(CONFIG_MSM_PERFORMANCE) += msm_performance.o
+obj-$(CONFIG_SDX_EXT_IPC) += sdx_ext_ipc.o
ifdef CONFIG_MSM_SUBSYSTEM_RESTART
obj-y += subsystem_notif.o
diff --git a/drivers/soc/qcom/pil_bg_intf.h b/drivers/soc/qcom/pil_bg_intf.h
index 07e98f7..d0781d5 100644
--- a/drivers/soc/qcom/pil_bg_intf.h
+++ b/drivers/soc/qcom/pil_bg_intf.h
@@ -29,6 +29,7 @@ enum bg_tz_commands {
/* tzapp bg request.*/
struct tzapp_bg_req {
uint8_t tzapp_bg_cmd;
+ uint8_t padding[3];
phys_addr_t address_fw;
size_t size_fw;
} __attribute__ ((__packed__));
diff --git a/drivers/soc/qcom/sdx_ext_ipc.c b/drivers/soc/qcom/sdx_ext_ipc.c
new file mode 100644
index 0000000..2b18017
--- /dev/null
+++ b/drivers/soc/qcom/sdx_ext_ipc.c
@@ -0,0 +1,267 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+
+
+enum subsys_policies {
+ SUBSYS_PANIC = 0,
+ SUBSYS_NOP,
+};
+
+static const char * const policies[] = {
+ [SUBSYS_PANIC] = "PANIC",
+ [SUBSYS_NOP] = "NOP",
+};
+
+enum gpios {
+ AP2MDM_STATUS = 0,
+ MDM2AP_STATUS,
+ MDM2AP_STATUS2,
+ NUM_GPIOS,
+};
+
+static const char * const gpio_map[] = {
+ [AP2MDM_STATUS] = "qcom,ap2mdm-status-gpio",
+ [MDM2AP_STATUS] = "qcom,mdm2ap-status-gpio",
+ [MDM2AP_STATUS2] = "qcom,mdm2ap-status2-gpio",
+};
+
+struct gpio_cntrl {
+ unsigned int gpios[NUM_GPIOS];
+ int status_irq;
+ int policy;
+ struct device *dev;
+ struct mutex policy_lock;
+ struct notifier_block panic_blk;
+};
+
+static ssize_t policy_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ int ret;
+ struct gpio_cntrl *mdm = dev_get_drvdata(dev);
+
+ mutex_lock(&mdm->policy_lock);
+ ret = scnprintf(buf, strlen(policies[mdm->policy]) + 1,
+ policies[mdm->policy]);
+ mutex_unlock(&mdm->policy_lock);
+
+ return ret;
+}
+
+static ssize_t policy_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct gpio_cntrl *mdm = dev_get_drvdata(dev);
+ const char *p;
+ int i, orig_count = count;
+
+ p = memchr(buf, '\n', count);
+ if (p)
+ count = p - buf;
+
+ for (i = 0; i < ARRAY_SIZE(policies); i++)
+ if (!strncasecmp(buf, policies[i], count)) {
+ mutex_lock(&mdm->policy_lock);
+ mdm->policy = i;
+ mutex_unlock(&mdm->policy_lock);
+ return orig_count;
+ }
+ return -EPERM;
+}
+static DEVICE_ATTR_RW(policy);
+
+static irqreturn_t ap_status_change(int irq, void *dev_id)
+{
+ struct gpio_cntrl *mdm = dev_id;
+ int state;
+ struct gpio_desc *gp_status = gpio_to_desc(mdm->gpios[AP2MDM_STATUS]);
+ int active_low = 0;
+
+ if (gp_status)
+ active_low = gpiod_is_active_low(gp_status);
+
+ state = gpio_get_value(mdm->gpios[AP2MDM_STATUS]);
+ if ((!active_low && !state) || (active_low && state)) {
+ if (mdm->policy)
+ dev_info(mdm->dev, "Host undergoing SSR, leaving SDX as it is\n");
+ else
+ panic("Host undergoing SSR, panicking SDX\n");
+ } else
+ dev_info(mdm->dev, "HOST booted\n");
+
+ return IRQ_HANDLED;
+}
+
+static void remove_ipc(struct gpio_cntrl *mdm)
+{
+ int i;
+
+ for (i = 0; i < NUM_GPIOS; ++i) {
+ if (gpio_is_valid(mdm->gpios[i]))
+ gpio_free(mdm->gpios[i]);
+ }
+}
+
+static int setup_ipc(struct gpio_cntrl *mdm)
+{
+ int i, val, ret, irq;
+ struct device_node *node;
+
+ node = mdm->dev->of_node;
+ for (i = 0; i < ARRAY_SIZE(gpio_map); i++) {
+ val = of_get_named_gpio(node, gpio_map[i], 0);
+ if (val >= 0)
+ mdm->gpios[i] = val;
+ }
+
+ ret = gpio_request(mdm->gpios[AP2MDM_STATUS], "AP2MDM_STATUS");
+ if (ret) {
+ dev_err(mdm->dev, "Failed to configure AP2MDM_STATUS gpio\n");
+ return ret;
+ }
+ gpio_direction_input(mdm->gpios[AP2MDM_STATUS]);
+
+ ret = gpio_request(mdm->gpios[MDM2AP_STATUS], "MDM2AP_STATUS");
+ if (ret) {
+ dev_err(mdm->dev, "Failed to configure MDM2AP_STATUS gpio\n");
+ return ret;
+ }
+ gpio_direction_output(mdm->gpios[MDM2AP_STATUS], 1);
+
+ ret = gpio_request(mdm->gpios[MDM2AP_STATUS2], "MDM2AP_STATUS2");
+ if (ret) {
+ dev_err(mdm->dev, "Failed to configure MDM2AP_STATUS2 gpio\n");
+ return ret;
+ }
+ gpio_direction_output(mdm->gpios[MDM2AP_STATUS2], 0);
+
+ irq = gpio_to_irq(mdm->gpios[AP2MDM_STATUS]);
+ if (irq < 0) {
+ dev_err(mdm->dev, "bad AP2MDM_STATUS IRQ resource\n");
+ return irq;
+ }
+ mdm->status_irq = irq;
+
+ return 0;
+}
+
+static int sdx_ext_ipc_panic(struct notifier_block *this,
+ unsigned long event, void *ptr)
+{
+ struct gpio_cntrl *mdm = container_of(this,
+ struct gpio_cntrl, panic_blk);
+
+ gpio_set_value(mdm->gpios[MDM2AP_STATUS], 0);
+
+ return NOTIFY_DONE;
+}
+
+static int sdx_ext_ipc_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *node;
+ struct gpio_cntrl *mdm;
+
+ node = pdev->dev.of_node;
+ mdm = devm_kzalloc(&pdev->dev, sizeof(*mdm), GFP_KERNEL);
+ if (!mdm)
+ return -ENOMEM;
+
+ mdm->dev = &pdev->dev;
+ ret = setup_ipc(mdm);
+ if (ret) {
+ dev_err(mdm->dev, "Error setting up gpios\n");
+ devm_kfree(&pdev->dev, mdm);
+ return ret;
+ }
+
+ mdm->panic_blk.notifier_call = sdx_ext_ipc_panic;
+ atomic_notifier_chain_register(&panic_notifier_list, &mdm->panic_blk);
+
+ mutex_init(&mdm->policy_lock);
+ mdm->policy = SUBSYS_PANIC;
+
+ ret = device_create_file(mdm->dev, &dev_attr_policy);
+ if (ret) {
+ dev_err(mdm->dev, "cannot create sysfs attribute\n");
+ goto sys_fail;
+ }
+
+ platform_set_drvdata(pdev, mdm);
+
+ ret = devm_request_irq(mdm->dev, mdm->status_irq, ap_status_change,
+ IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
+ "ap status", mdm);
+ if (ret < 0) {
+ dev_err(mdm->dev, "%s: AP2MDM_STATUS IRQ#%d request failed,\n",
+ __func__, mdm->status_irq);
+ goto irq_fail;
+ }
+ irq_set_irq_wake(mdm->status_irq, 1);
+ return 0;
+
+irq_fail:
+ device_remove_file(mdm->dev, &dev_attr_policy);
+sys_fail:
+ atomic_notifier_chain_unregister(&panic_notifier_list, &mdm->panic_blk);
+ remove_ipc(mdm);
+ devm_kfree(&pdev->dev, mdm);
+ return ret;
+}
+
+static int sdx_ext_ipc_remove(struct platform_device *pdev)
+{
+ struct gpio_cntrl *mdm;
+
+ mdm = dev_get_drvdata(&pdev->dev);
+ disable_irq_wake(mdm->status_irq);
+ atomic_notifier_chain_unregister(&panic_notifier_list, &mdm->panic_blk);
+ remove_ipc(mdm);
+ device_remove_file(mdm->dev, &dev_attr_policy);
+ return 0;
+}
+
+static const struct of_device_id sdx_ext_ipc_of_match[] = {
+ { .compatible = "qcom,sdx-ext-ipc"},
+ {},
+};
+
+static struct platform_driver sdx_ext_ipc_driver = {
+ .probe = sdx_ext_ipc_probe,
+ .remove = sdx_ext_ipc_remove,
+ .driver = {
+ .name = "sdx-ext-ipc",
+ .owner = THIS_MODULE,
+ .of_match_table = sdx_ext_ipc_of_match,
+ },
+};
+
+static int __init sdx_ext_ipc_register(void)
+{
+ return platform_driver_register(&sdx_ext_ipc_driver);
+}
+subsys_initcall(sdx_ext_ipc_register);
+
+static void __exit sdx_ext_ipc_unregister(void)
+{
+ platform_driver_unregister(&sdx_ext_ipc_driver);
+}
+module_exit(sdx_ext_ipc_unregister);
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 44be6b5..691c04b 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -1209,10 +1209,8 @@ static int atmel_spi_setup(struct spi_device *spi)
as = spi_master_get_devdata(spi->master);
/* see notes above re chipselect */
- if (!atmel_spi_is_v2(as)
- && spi->chip_select == 0
- && (spi->mode & SPI_CS_HIGH)) {
- dev_dbg(&spi->dev, "setup: can't be active-high\n");
+ if (!as->use_cs_gpios && (spi->mode & SPI_CS_HIGH)) {
+ dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
return -EINVAL;
}
diff --git a/drivers/spi/spi-img-spfi.c b/drivers/spi/spi-img-spfi.c
index 7a37090..2e65b70 100644
--- a/drivers/spi/spi-img-spfi.c
+++ b/drivers/spi/spi-img-spfi.c
@@ -673,6 +673,8 @@ static int img_spfi_probe(struct platform_device *pdev)
dma_release_channel(spfi->tx_ch);
if (spfi->rx_ch)
dma_release_channel(spfi->rx_ch);
+ spfi->tx_ch = NULL;
+ spfi->rx_ch = NULL;
dev_warn(spfi->dev, "Failed to get DMA channels, falling back to PIO mode\n");
} else {
master->dma_tx = spfi->tx_ch;
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 6dd195b..2f84d76 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -1529,7 +1529,13 @@ pxa2xx_spi_init_pdata(struct platform_device *pdev)
}
ssp->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(ssp->clk))
+ return NULL;
+
ssp->irq = platform_get_irq(pdev, 0);
+ if (ssp->irq < 0)
+ return NULL;
+
ssp->type = type;
ssp->pdev = pdev;
ssp->port_id = pxa2xx_spi_get_port_id(adev);
diff --git a/drivers/spi/spi-st-ssc4.c b/drivers/spi/spi-st-ssc4.c
index e54b596..710adbc 100644
--- a/drivers/spi/spi-st-ssc4.c
+++ b/drivers/spi/spi-st-ssc4.c
@@ -385,6 +385,7 @@ static int spi_st_probe(struct platform_device *pdev)
return 0;
clk_disable:
+ pm_runtime_disable(&pdev->dev);
clk_disable_unprepare(spi_st->clk);
put_master:
spi_master_put(master);
@@ -396,6 +397,8 @@ static int spi_st_remove(struct platform_device *pdev)
struct spi_master *master = platform_get_drvdata(pdev);
struct spi_st *spi_st = spi_master_get_devdata(master);
+ pm_runtime_disable(&pdev->dev);
+
clk_disable_unprepare(spi_st->clk);
pinctrl_pm_select_sleep_state(&pdev->dev);
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
index af2880d..cf2a329 100644
--- a/drivers/spi/spi-tegra20-slink.c
+++ b/drivers/spi/spi-tegra20-slink.c
@@ -1078,7 +1078,7 @@ static int tegra_slink_probe(struct platform_device *pdev)
ret = clk_enable(tspi->clk);
if (ret < 0) {
dev_err(&pdev->dev, "Clock enable failed %d\n", ret);
- goto exit_free_master;
+ goto exit_clk_unprepare;
}
spi_irq = platform_get_irq(pdev, 0);
@@ -1151,6 +1151,8 @@ static int tegra_slink_probe(struct platform_device *pdev)
free_irq(spi_irq, tspi);
exit_clk_disable:
clk_disable(tspi->clk);
+exit_clk_unprepare:
+ clk_unprepare(tspi->clk);
exit_free_master:
spi_master_put(master);
return ret;
@@ -1164,6 +1166,7 @@ static int tegra_slink_remove(struct platform_device *pdev)
free_irq(tspi->irq, tspi);
clk_disable(tspi->clk);
+ clk_unprepare(tspi->clk);
if (tspi->tx_dma_chan)
tegra_slink_deinit_dma_param(tspi, false);
diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
index 0602366..4f1b6aa 100644
--- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c
@@ -663,6 +663,9 @@ static int spidev_release(struct inode *inode, struct file *filp)
if (dofree)
kfree(spidev);
}
+#ifdef CONFIG_SPI_SLAVE
+ spi_slave_abort(spidev->spi);
+#endif
mutex_unlock(&device_list_lock);
return 0;
diff --git a/drivers/staging/comedi/drivers/gsc_hpdi.c b/drivers/staging/comedi/drivers/gsc_hpdi.c
index e5b9484..a09631f 100644
--- a/drivers/staging/comedi/drivers/gsc_hpdi.c
+++ b/drivers/staging/comedi/drivers/gsc_hpdi.c
@@ -632,6 +632,11 @@ static int gsc_hpdi_auto_attach(struct comedi_device *dev,
dma_alloc_coherent(&pcidev->dev, DMA_BUFFER_SIZE,
&devpriv->dio_buffer_phys_addr[i],
GFP_KERNEL);
+ if (!devpriv->dio_buffer[i]) {
+ dev_warn(dev->class_dev,
+ "failed to allocate DMA buffer\n");
+ return -ENOMEM;
+ }
}
/* allocate dma descriptors */
devpriv->dma_desc = dma_alloc_coherent(&pcidev->dev,
@@ -639,6 +644,11 @@ static int gsc_hpdi_auto_attach(struct comedi_device *dev,
NUM_DMA_DESCRIPTORS,
&devpriv->dma_desc_phys_addr,
GFP_KERNEL);
+ if (!devpriv->dma_desc) {
+ dev_warn(dev->class_dev,
+ "failed to allocate DMA descriptors\n");
+ return -ENOMEM;
+ }
if (devpriv->dma_desc_phys_addr & 0xf) {
dev_warn(dev->class_dev,
" dma descriptors not quad-word aligned (bug)\n");
diff --git a/drivers/staging/fbtft/fbtft-core.c b/drivers/staging/fbtft/fbtft-core.c
index d9ba8c0..ece713d 100644
--- a/drivers/staging/fbtft/fbtft-core.c
+++ b/drivers/staging/fbtft/fbtft-core.c
@@ -766,7 +766,7 @@ struct fb_info *fbtft_framebuffer_alloc(struct fbtft_display *display,
fbdefio->deferred_io = fbtft_deferred_io;
fb_deferred_io_init(info);
- strncpy(info->fix.id, dev->driver->name, 16);
+ snprintf(info->fix.id, sizeof(info->fix.id), "%s", dev->driver->name);
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.visual = FB_VISUAL_TRUECOLOR;
info->fix.xpanstep = 0;
diff --git a/drivers/staging/iio/addac/adt7316-i2c.c b/drivers/staging/iio/addac/adt7316-i2c.c
index 0ccf192..5950225 100644
--- a/drivers/staging/iio/addac/adt7316-i2c.c
+++ b/drivers/staging/iio/addac/adt7316-i2c.c
@@ -35,6 +35,8 @@ static int adt7316_i2c_read(void *client, u8 reg, u8 *data)
return ret;
}
+ *data = ret;
+
return 0;
}
diff --git a/drivers/staging/media/pulse8-cec/pulse8-cec.c b/drivers/staging/media/pulse8-cec/pulse8-cec.c
index 1732c38..2785cc0 100644
--- a/drivers/staging/media/pulse8-cec/pulse8-cec.c
+++ b/drivers/staging/media/pulse8-cec/pulse8-cec.c
@@ -580,7 +580,7 @@ static int pulse8_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
else
pulse8->config_pending = true;
mutex_unlock(&pulse8->config_lock);
- return err;
+ return log_addr == CEC_LOG_ADDR_INVALID ? 0 : err;
}
static int pulse8_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
diff --git a/drivers/staging/rtl8188eu/core/rtw_xmit.c b/drivers/staging/rtl8188eu/core/rtw_xmit.c
index 0f8b8e0..dedc313 100644
--- a/drivers/staging/rtl8188eu/core/rtw_xmit.c
+++ b/drivers/staging/rtl8188eu/core/rtw_xmit.c
@@ -805,7 +805,7 @@ s32 rtw_make_wlanhdr(struct adapter *padapter, u8 *hdr, struct pkt_attrib *pattr
memcpy(pwlanhdr->addr2, get_bssid(pmlmepriv), ETH_ALEN);
memcpy(pwlanhdr->addr3, pattrib->src, ETH_ALEN);
- if (psta->qos_option)
+ if (psta && psta->qos_option)
qos_option = true;
} else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) ||
check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) {
@@ -813,7 +813,7 @@ s32 rtw_make_wlanhdr(struct adapter *padapter, u8 *hdr, struct pkt_attrib *pattr
memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);
- if (psta->qos_option)
+ if (psta && psta->qos_option)
qos_option = true;
} else {
RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("fw_state:%x is not allowed to xmit frame\n", get_fwstate(pmlmepriv)));
diff --git a/drivers/staging/rtl8188eu/os_dep/usb_intf.c b/drivers/staging/rtl8188eu/os_dep/usb_intf.c
index d4a7d74..bfcf9e5 100644
--- a/drivers/staging/rtl8188eu/os_dep/usb_intf.c
+++ b/drivers/staging/rtl8188eu/os_dep/usb_intf.c
@@ -78,7 +78,7 @@ static struct dvobj_priv *usb_dvobj_init(struct usb_interface *usb_intf)
phost_conf = pusbd->actconfig;
pconf_desc = &phost_conf->desc;
- phost_iface = &usb_intf->altsetting[0];
+ phost_iface = usb_intf->cur_altsetting;
piface_desc = &phost_iface->desc;
pdvobjpriv->NumInterfaces = pconf_desc->bNumInterfaces;
diff --git a/drivers/staging/rtl8192u/r8192U_core.c b/drivers/staging/rtl8192u/r8192U_core.c
index 5fe9593..6ec3790 100644
--- a/drivers/staging/rtl8192u/r8192U_core.c
+++ b/drivers/staging/rtl8192u/r8192U_core.c
@@ -1509,7 +1509,7 @@ short rtl8192_tx(struct net_device *dev, struct sk_buff *skb)
(tx_fwinfo_819x_usb *)(skb->data + USB_HWDESC_HEADER_LEN);
struct usb_device *udev = priv->udev;
int pend;
- int status;
+ int status, rt = -1;
struct urb *tx_urb = NULL, *tx_urb_zero = NULL;
unsigned int idx_pipe;
@@ -1653,8 +1653,10 @@ short rtl8192_tx(struct net_device *dev, struct sk_buff *skb)
}
if (bSend0Byte) {
tx_urb_zero = usb_alloc_urb(0, GFP_ATOMIC);
- if (!tx_urb_zero)
- return -ENOMEM;
+ if (!tx_urb_zero) {
+ rt = -ENOMEM;
+ goto error;
+ }
usb_fill_bulk_urb(tx_urb_zero, udev,
usb_sndbulkpipe(udev, idx_pipe),
&zero, 0, tx_zero_isr, dev);
@@ -1664,7 +1666,7 @@ short rtl8192_tx(struct net_device *dev, struct sk_buff *skb)
"Error TX URB for zero byte %d, error %d",
atomic_read(&priv->tx_pending[tcb_desc->queue_index]),
status);
- return -1;
+ goto error;
}
}
netif_trans_update(dev);
@@ -1675,7 +1677,12 @@ short rtl8192_tx(struct net_device *dev, struct sk_buff *skb)
RT_TRACE(COMP_ERR, "Error TX URB %d, error %d",
atomic_read(&priv->tx_pending[tcb_desc->queue_index]),
status);
- return -1;
+
+error:
+ dev_kfree_skb_any(skb);
+ usb_free_urb(tx_urb);
+ usb_free_urb(tx_urb_zero);
+ return rt;
}
static short rtl8192_usb_initendpoints(struct net_device *dev)
diff --git a/drivers/staging/rtl8712/usb_intf.c b/drivers/staging/rtl8712/usb_intf.c
index 897d462..d0ba42d 100644
--- a/drivers/staging/rtl8712/usb_intf.c
+++ b/drivers/staging/rtl8712/usb_intf.c
@@ -275,7 +275,7 @@ static uint r8712_usb_dvobj_init(struct _adapter *padapter)
pdvobjpriv->padapter = padapter;
padapter->EepromAddressSize = 6;
- phost_iface = &pintf->altsetting[0];
+ phost_iface = pintf->cur_altsetting;
piface_desc = &phost_iface->desc;
pdvobjpriv->nr_endpoint = piface_desc->bNumEndpoints;
if (pusbd->speed == USB_SPEED_HIGH) {
diff --git a/drivers/target/iscsi/iscsi_target.c b/drivers/target/iscsi/iscsi_target.c
index b6c4f55..e5674e5 100644
--- a/drivers/target/iscsi/iscsi_target.c
+++ b/drivers/target/iscsi/iscsi_target.c
@@ -1168,7 +1168,9 @@ int iscsit_setup_scsi_cmd(struct iscsi_conn *conn, struct iscsi_cmd *cmd,
hdr->cmdsn, be32_to_cpu(hdr->data_length), payload_length,
conn->cid);
- target_get_sess_cmd(&cmd->se_cmd, true);
+ if (target_get_sess_cmd(&cmd->se_cmd, true) < 0)
+ return iscsit_add_reject_cmd(cmd,
+ ISCSI_REASON_WAITING_FOR_LOGOUT, buf);
cmd->sense_reason = transport_lookup_cmd_lun(&cmd->se_cmd,
scsilun_to_int(&hdr->lun));
@@ -1986,7 +1988,9 @@ iscsit_handle_task_mgt_cmd(struct iscsi_conn *conn, struct iscsi_cmd *cmd,
conn->sess->se_sess, 0, DMA_NONE,
TCM_SIMPLE_TAG, cmd->sense_buffer + 2);
- target_get_sess_cmd(&cmd->se_cmd, true);
+ if (target_get_sess_cmd(&cmd->se_cmd, true) < 0)
+ return iscsit_add_reject_cmd(cmd,
+ ISCSI_REASON_WAITING_FOR_LOGOUT, buf);
/*
* TASK_REASSIGN for ERL=2 / connection stays inside of
@@ -4243,6 +4247,8 @@ int iscsit_close_connection(
* must wait until they have completed.
*/
iscsit_check_conn_usage_count(conn);
+ target_sess_cmd_list_set_waiting(sess->se_sess);
+ target_wait_for_sess_cmds(sess->se_sess);
ahash_request_free(conn->conn_tx_hash);
if (conn->conn_rx_hash) {
diff --git a/drivers/target/iscsi/iscsi_target_auth.c b/drivers/target/iscsi/iscsi_target_auth.c
index f0d9730..aa3f989 100644
--- a/drivers/target/iscsi/iscsi_target_auth.c
+++ b/drivers/target/iscsi/iscsi_target_auth.c
@@ -74,7 +74,7 @@ static int chap_check_algorithm(const char *a_str)
if (!token)
goto out;
- if (!strncmp(token, "5", 1)) {
+ if (!strcmp(token, "5")) {
pr_debug("Selected MD5 Algorithm\n");
kfree(orig);
return CHAP_DIGEST_MD5;
diff --git a/drivers/tty/n_hdlc.c b/drivers/tty/n_hdlc.c
index 8d625390..0c12dec 100644
--- a/drivers/tty/n_hdlc.c
+++ b/drivers/tty/n_hdlc.c
@@ -614,7 +614,7 @@ static ssize_t n_hdlc_tty_read(struct tty_struct *tty, struct file *file,
}
/* no data */
- if (file->f_flags & O_NONBLOCK) {
+ if (tty_io_nonblock(tty, file)) {
ret = -EAGAIN;
break;
}
@@ -681,7 +681,7 @@ static ssize_t n_hdlc_tty_write(struct tty_struct *tty, struct file *file,
if (tbuf)
break;
- if (file->f_flags & O_NONBLOCK) {
+ if (tty_io_nonblock(tty, file)) {
error = -EAGAIN;
break;
}
diff --git a/drivers/tty/n_r3964.c b/drivers/tty/n_r3964.c
index 3451114..ee0e07b 100644
--- a/drivers/tty/n_r3964.c
+++ b/drivers/tty/n_r3964.c
@@ -1080,7 +1080,7 @@ static ssize_t r3964_read(struct tty_struct *tty, struct file *file,
pMsg = remove_msg(pInfo, pClient);
if (pMsg == NULL) {
/* no messages available. */
- if (file->f_flags & O_NONBLOCK) {
+ if (tty_io_nonblock(tty, file)) {
ret = -EAGAIN;
goto unlock;
}
diff --git a/drivers/tty/n_tty.c b/drivers/tty/n_tty.c
index 86c0bc0..a75a6e1 100644
--- a/drivers/tty/n_tty.c
+++ b/drivers/tty/n_tty.c
@@ -1732,7 +1732,7 @@ n_tty_receive_buf_common(struct tty_struct *tty, const unsigned char *cp,
down_read(&tty->termios_rwsem);
- while (1) {
+ do {
/*
* When PARMRK is set, each input char may take up to 3 chars
* in the read buf; reduce the buffer space avail by 3x
@@ -1774,7 +1774,7 @@ n_tty_receive_buf_common(struct tty_struct *tty, const unsigned char *cp,
fp += n;
count -= n;
rcvd += n;
- }
+ } while (!test_bit(TTY_LDISC_CHANGING, &tty->flags));
tty->receive_room = room;
@@ -2241,7 +2241,7 @@ static ssize_t n_tty_read(struct tty_struct *tty, struct file *file,
break;
if (!timeout)
break;
- if (file->f_flags & O_NONBLOCK) {
+ if (tty_io_nonblock(tty, file)) {
retval = -EAGAIN;
break;
}
@@ -2395,7 +2395,7 @@ static ssize_t n_tty_write(struct tty_struct *tty, struct file *file,
}
if (!nr)
break;
- if (file->f_flags & O_NONBLOCK) {
+ if (tty_io_nonblock(tty, file)) {
retval = -EAGAIN;
break;
}
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 2d8089f..f6586a8 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -811,10 +811,8 @@ __acquires(&uap->port.lock)
if (!uap->using_tx_dma)
return;
- /* Avoid deadlock with the DMA engine callback */
- spin_unlock(&uap->port.lock);
- dmaengine_terminate_all(uap->dmatx.chan);
- spin_lock(&uap->port.lock);
+ dmaengine_terminate_async(uap->dmatx.chan);
+
if (uap->dmatx.queued) {
dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
DMA_TO_DEVICE);
diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index 5782422..325f9db 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -2200,27 +2200,6 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
mode |= ATMEL_US_USMODE_NORMAL;
}
- /* set the mode, clock divisor, parity, stop bits and data size */
- atmel_uart_writel(port, ATMEL_US_MR, mode);
-
- /*
- * when switching the mode, set the RTS line state according to the
- * new mode, otherwise keep the former state
- */
- if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
- unsigned int rts_state;
-
- if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
- /* let the hardware control the RTS line */
- rts_state = ATMEL_US_RTSDIS;
- } else {
- /* force RTS line to low level */
- rts_state = ATMEL_US_RTSEN;
- }
-
- atmel_uart_writel(port, ATMEL_US_CR, rts_state);
- }
-
/*
* Set the baud rate:
* Fractional baudrate allows to setup output frequency more
@@ -2247,6 +2226,28 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
quot = cd | fp << ATMEL_US_FP_OFFSET;
atmel_uart_writel(port, ATMEL_US_BRGR, quot);
+
+ /* set the mode, clock divisor, parity, stop bits and data size */
+ atmel_uart_writel(port, ATMEL_US_MR, mode);
+
+ /*
+ * when switching the mode, set the RTS line state according to the
+ * new mode, otherwise keep the former state
+ */
+ if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
+ unsigned int rts_state;
+
+ if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
+ /* let the hardware control the RTS line */
+ rts_state = ATMEL_US_RTSDIS;
+ } else {
+ /* force RTS line to low level */
+ rts_state = ATMEL_US_RTSEN;
+ }
+
+ atmel_uart_writel(port, ATMEL_US_CR, rts_state);
+ }
+
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
index 8009965..5b6093d 100644
--- a/drivers/tty/serial/fsl_lpuart.c
+++ b/drivers/tty/serial/fsl_lpuart.c
@@ -346,8 +346,8 @@ static void lpuart_dma_tx(struct lpuart_port *sport)
}
sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl,
- sport->dma_tx_nents,
- DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
+ ret, DMA_MEM_TO_DEV,
+ DMA_PREP_INTERRUPT);
if (!sport->dma_tx_desc) {
dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
dev_err(dev, "Cannot prepare TX slave DMA!\n");
diff --git a/drivers/tty/serial/ifx6x60.c b/drivers/tty/serial/ifx6x60.c
index 91d2ddd..180b773 100644
--- a/drivers/tty/serial/ifx6x60.c
+++ b/drivers/tty/serial/ifx6x60.c
@@ -1244,6 +1244,9 @@ static int ifx_spi_spi_remove(struct spi_device *spi)
struct ifx_spi_device *ifx_dev = spi_get_drvdata(spi);
/* stop activity */
tasklet_kill(&ifx_dev->io_work_tasklet);
+
+ pm_runtime_disable(&spi->dev);
+
/* free irq */
free_irq(gpio_to_irq(ifx_dev->gpio.reset_out), ifx_dev);
free_irq(gpio_to_irq(ifx_dev->gpio.srdy), ifx_dev);
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 0d82be1..6d596c6 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -1943,7 +1943,7 @@ imx_console_setup(struct console *co, char *options)
retval = clk_prepare(sport->clk_per);
if (retval)
- clk_disable_unprepare(sport->clk_ipg);
+ clk_unprepare(sport->clk_ipg);
error_console:
return retval;
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index 7700e8a..edf5569 100755
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -1006,6 +1006,7 @@ static unsigned int msm_get_mctrl(struct uart_port *port)
static void msm_reset(struct uart_port *port)
{
struct msm_port *msm_port = UART_TO_MSM(port);
+ unsigned int mr;
/* reset everything */
msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
@@ -1013,7 +1014,10 @@ static void msm_reset(struct uart_port *port)
msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
- msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
+ msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
+ mr = msm_read(port, UART_MR1);
+ mr &= ~UART_MR1_RX_RDY_CTL;
+ msm_write(port, mr, UART_MR1);
/* Disable DM modes */
if (msm_port->is_uartdm)
diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
index 48afdff..f4ab3e3 100644
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
@@ -1109,7 +1109,7 @@ static int uart_break_ctl(struct tty_struct *tty, int break_state)
if (!uport)
goto out;
- if (uport->type != PORT_UNKNOWN)
+ if (uport->type != PORT_UNKNOWN && uport->ops->break_ctl)
uport->ops->break_ctl(uport, break_state);
ret = 0;
out:
diff --git a/drivers/tty/tty_ldisc.c b/drivers/tty/tty_ldisc.c
index 3eb3f2a..706faca 100644
--- a/drivers/tty/tty_ldisc.c
+++ b/drivers/tty/tty_ldisc.c
@@ -348,6 +348,11 @@ int tty_ldisc_lock(struct tty_struct *tty, unsigned long timeout)
{
int ret;
+ /* Kindly asking blocked readers to release the read side */
+ set_bit(TTY_LDISC_CHANGING, &tty->flags);
+ wake_up_interruptible_all(&tty->read_wait);
+ wake_up_interruptible_all(&tty->write_wait);
+
ret = __tty_ldisc_lock(tty, timeout);
if (!ret)
return -EBUSY;
@@ -358,6 +363,8 @@ int tty_ldisc_lock(struct tty_struct *tty, unsigned long timeout)
void tty_ldisc_unlock(struct tty_struct *tty)
{
clear_bit(TTY_LDISC_HALTED, &tty->flags);
+ /* Can be cleared here - ldisc_unlock will wake up writers firstly */
+ clear_bit(TTY_LDISC_CHANGING, &tty->flags);
__tty_ldisc_unlock(tty);
}
diff --git a/drivers/tty/vt/keyboard.c b/drivers/tty/vt/keyboard.c
index e8a917a..b4e7a73 100644
--- a/drivers/tty/vt/keyboard.c
+++ b/drivers/tty/vt/keyboard.c
@@ -1460,7 +1460,7 @@ static void kbd_event(struct input_handle *handle, unsigned int event_type,
if (event_type == EV_MSC && event_code == MSC_RAW && HW_RAW(handle->dev))
kbd_rawcode(value);
- if (event_type == EV_KEY)
+ if (event_type == EV_KEY && event_code <= KEY_MAX)
kbd_keycode(event_code, value, HW_RAW(handle->dev));
spin_unlock(&kbd_event_lock);
diff --git a/drivers/usb/atm/ueagle-atm.c b/drivers/usb/atm/ueagle-atm.c
index df67815..127fcaf 100644
--- a/drivers/usb/atm/ueagle-atm.c
+++ b/drivers/usb/atm/ueagle-atm.c
@@ -2167,10 +2167,11 @@ static void uea_intr(struct urb *urb)
/*
* Start the modem : init the data and start kernel thread
*/
-static int uea_boot(struct uea_softc *sc)
+static int uea_boot(struct uea_softc *sc, struct usb_interface *intf)
{
- int ret, size;
struct intr_pkt *intr;
+ int ret = -ENOMEM;
+ int size;
uea_enters(INS_TO_USBDEV(sc));
@@ -2195,6 +2196,11 @@ static int uea_boot(struct uea_softc *sc)
if (UEA_CHIP_VERSION(sc) == ADI930)
load_XILINX_firmware(sc);
+ if (intf->cur_altsetting->desc.bNumEndpoints < 1) {
+ ret = -ENODEV;
+ goto err0;
+ }
+
intr = kmalloc(size, GFP_KERNEL);
if (!intr)
goto err0;
@@ -2206,8 +2212,7 @@ static int uea_boot(struct uea_softc *sc)
usb_fill_int_urb(sc->urb_int, sc->usb_dev,
usb_rcvintpipe(sc->usb_dev, UEA_INTR_PIPE),
intr, size, uea_intr, sc,
- sc->usb_dev->actconfig->interface[0]->altsetting[0].
- endpoint[0].desc.bInterval);
+ intf->cur_altsetting->endpoint[0].desc.bInterval);
ret = usb_submit_urb(sc->urb_int, GFP_KERNEL);
if (ret < 0) {
@@ -2222,6 +2227,7 @@ static int uea_boot(struct uea_softc *sc)
sc->kthread = kthread_create(uea_kthread, sc, "ueagle-atm");
if (IS_ERR(sc->kthread)) {
uea_err(INS_TO_USBDEV(sc), "failed to create thread\n");
+ ret = PTR_ERR(sc->kthread);
goto err2;
}
@@ -2236,7 +2242,7 @@ static int uea_boot(struct uea_softc *sc)
kfree(intr);
err0:
uea_leaves(INS_TO_USBDEV(sc));
- return -ENOMEM;
+ return ret;
}
/*
@@ -2597,7 +2603,7 @@ static int uea_bind(struct usbatm_data *usbatm, struct usb_interface *intf,
if (ret < 0)
goto error;
- ret = uea_boot(sc);
+ ret = uea_boot(sc, intf);
if (ret < 0)
goto error_rm_grp;
diff --git a/drivers/usb/core/devio.c b/drivers/usb/core/devio.c
index 06a8f64..059e71d 100644
--- a/drivers/usb/core/devio.c
+++ b/drivers/usb/core/devio.c
@@ -754,8 +754,15 @@ static int claimintf(struct usb_dev_state *ps, unsigned int ifnum)
intf = usb_ifnum_to_if(dev, ifnum);
if (!intf)
err = -ENOENT;
- else
+ else {
+ unsigned int old_suppress;
+
+ /* suppress uevents while claiming interface */
+ old_suppress = dev_get_uevent_suppress(&intf->dev);
+ dev_set_uevent_suppress(&intf->dev, 1);
err = usb_driver_claim_interface(&usbfs_driver, intf, ps);
+ dev_set_uevent_suppress(&intf->dev, old_suppress);
+ }
if (err == 0)
set_bit(ifnum, &ps->ifclaimed);
return err;
@@ -775,7 +782,13 @@ static int releaseintf(struct usb_dev_state *ps, unsigned int ifnum)
if (!intf)
err = -ENOENT;
else if (test_and_clear_bit(ifnum, &ps->ifclaimed)) {
+ unsigned int old_suppress;
+
+ /* suppress uevents while releasing interface */
+ old_suppress = dev_get_uevent_suppress(&intf->dev);
+ dev_set_uevent_suppress(&intf->dev, 1);
usb_driver_release_interface(&usbfs_driver, intf);
+ dev_set_uevent_suppress(&intf->dev, old_suppress);
err = 0;
}
return err;
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index 1b307de..ce389be 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -5655,7 +5655,7 @@ static int usb_reset_and_verify_device(struct usb_device *udev)
/**
* usb_reset_device - warn interface drivers and perform a USB port reset
- * @udev: device to reset (not in SUSPENDED or NOTATTACHED state)
+ * @udev: device to reset (not in NOTATTACHED state)
*
* Warns all drivers bound to registered interfaces (using their pre_reset
* method), performs the port reset, and then lets the drivers know that
@@ -5683,8 +5683,7 @@ int usb_reset_device(struct usb_device *udev)
struct usb_host_config *config = udev->actconfig;
struct usb_hub *hub = usb_hub_to_struct_hub(udev->parent);
- if (udev->state == USB_STATE_NOTATTACHED ||
- udev->state == USB_STATE_SUSPENDED) {
+ if (udev->state == USB_STATE_NOTATTACHED) {
dev_dbg(&udev->dev, "device reset not allowed in state %d\n",
udev->state);
return -EINVAL;
diff --git a/drivers/usb/core/urb.c b/drivers/usb/core/urb.c
index 5133ab9..7b81bcfa 100644
--- a/drivers/usb/core/urb.c
+++ b/drivers/usb/core/urb.c
@@ -40,6 +40,7 @@ void usb_init_urb(struct urb *urb)
if (urb) {
memset(urb, 0, sizeof(*urb));
kref_init(&urb->kref);
+ INIT_LIST_HEAD(&urb->urb_list);
INIT_LIST_HEAD(&urb->anchor_list);
}
}
diff --git a/drivers/usb/gadget/function/u_serial.c b/drivers/usb/gadget/function/u_serial.c
index 64909f3..d0d6611 100644
--- a/drivers/usb/gadget/function/u_serial.c
+++ b/drivers/usb/gadget/function/u_serial.c
@@ -1400,8 +1400,10 @@ int gserial_alloc_line(unsigned char *line_num)
__func__, port_num, PTR_ERR(tty_dev));
ret = PTR_ERR(tty_dev);
+ mutex_lock(&ports[port_num].lock);
port = ports[port_num].port;
ports[port_num].port = NULL;
+ mutex_unlock(&ports[port_num].lock);
gserial_free_port(port);
goto err;
}
diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c
index 484d9d7..3144fd9 100644
--- a/drivers/usb/host/ehci-q.c
+++ b/drivers/usb/host/ehci-q.c
@@ -40,6 +40,10 @@
/*-------------------------------------------------------------------------*/
+/* PID Codes that are used here, from EHCI specification, Table 3-16. */
+#define PID_CODE_IN 1
+#define PID_CODE_SETUP 2
+
/* fill a qtd, returning how much of the buffer we were able to queue up */
static int
@@ -203,7 +207,7 @@ static int qtd_copy_status (
int status = -EINPROGRESS;
/* count IN/OUT bytes, not SETUP (even short packets) */
- if (likely (QTD_PID (token) != 2))
+ if (likely(QTD_PID(token) != PID_CODE_SETUP))
urb->actual_length += length - QTD_LENGTH (token);
/* don't modify error codes */
@@ -219,6 +223,13 @@ static int qtd_copy_status (
if (token & QTD_STS_BABBLE) {
/* FIXME "must" disable babbling device's port too */
status = -EOVERFLOW;
+ /*
+ * When MMF is active and PID Code is IN, queue is halted.
+ * EHCI Specification, Table 4-13.
+ */
+ } else if ((token & QTD_STS_MMF) &&
+ (QTD_PID(token) == PID_CODE_IN)) {
+ status = -EPROTO;
/* CERR nonzero + halt --> stall */
} else if (QTD_CERR(token)) {
status = -EPIPE;
diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
index 8679875..a9a65ac 100644
--- a/drivers/usb/host/xhci-hub.c
+++ b/drivers/usb/host/xhci-hub.c
@@ -732,7 +732,7 @@ static u32 xhci_get_port_status(struct usb_hcd *hcd,
struct xhci_bus_state *bus_state,
__le32 __iomem **port_array,
u16 wIndex, u32 raw_port_status,
- unsigned long flags)
+ unsigned long *flags)
__releases(&xhci->lock)
__acquires(&xhci->lock)
{
@@ -764,6 +764,14 @@ static u32 xhci_get_port_status(struct usb_hcd *hcd,
status |= USB_PORT_STAT_C_BH_RESET << 16;
if ((raw_port_status & PORT_CEC))
status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
+
+ /* USB3 remote wake resume signaling completed */
+ if (bus_state->port_remote_wakeup & (1 << wIndex) &&
+ (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME &&
+ (raw_port_status & PORT_PLS_MASK) != XDEV_RECOVERY) {
+ bus_state->port_remote_wakeup &= ~(1 << wIndex);
+ usb_hcd_end_port_resume(&hcd->self, wIndex);
+ }
}
if (hcd->speed < HCD_USB3) {
@@ -814,12 +822,12 @@ static u32 xhci_get_port_status(struct usb_hcd *hcd,
xhci_set_link_state(xhci, port_array, wIndex,
XDEV_U0);
- spin_unlock_irqrestore(&xhci->lock, flags);
+ spin_unlock_irqrestore(&xhci->lock, *flags);
time_left = wait_for_completion_timeout(
&bus_state->rexit_done[wIndex],
msecs_to_jiffies(
XHCI_MAX_REXIT_TIMEOUT_MS));
- spin_lock_irqsave(&xhci->lock, flags);
+ spin_lock_irqsave(&xhci->lock, *flags);
if (time_left) {
slot_id = xhci_find_slot_id_by_port(hcd,
@@ -1112,7 +1120,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
break;
}
status = xhci_get_port_status(hcd, bus_state, port_array,
- wIndex, temp, flags);
+ wIndex, temp, &flags);
if (status == 0xffffffff)
goto error;
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 6b71b45..1ac64d7 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -2071,10 +2071,14 @@ void xhci_mem_cleanup(struct xhci_hcd *xhci)
kfree(xhci->port_array);
kfree(xhci->rh_bw);
kfree(xhci->ext_caps);
+ kfree(xhci->usb2_rhub.psi);
+ kfree(xhci->usb3_rhub.psi);
xhci->usb2_ports = NULL;
xhci->usb3_ports = NULL;
xhci->port_array = NULL;
+ xhci->usb2_rhub.psi = NULL;
+ xhci->usb3_rhub.psi = NULL;
xhci->rh_bw = NULL;
xhci->ext_caps = NULL;
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index 3e6c437..e10808c 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -470,6 +470,18 @@ static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
retval = xhci_resume(xhci, hibernated);
return retval;
}
+
+static void xhci_pci_shutdown(struct usb_hcd *hcd)
+{
+ struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+ struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
+
+ xhci_shutdown(hcd);
+
+ /* Yet another workaround for spurious wakeups at shutdown with HSW */
+ if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
+ pci_set_power_state(pdev, PCI_D3hot);
+}
#endif /* CONFIG_PM */
/*-------------------------------------------------------------------------*/
@@ -507,6 +519,7 @@ static int __init xhci_pci_init(void)
#ifdef CONFIG_PM
xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
+ xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
#endif
return pci_register_driver(&xhci_pci_driver);
}
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index fd2bcff..b5cf5bd 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -1599,9 +1599,6 @@ static void handle_port_status(struct xhci_hcd *xhci,
usb_hcd_resume_root_hub(hcd);
}
- if (hcd->speed >= HCD_USB3 && (temp & PORT_PLS_MASK) == XDEV_INACTIVE)
- bus_state->port_remote_wakeup &= ~(1 << faked_port_index);
-
if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
xhci_dbg(xhci, "port resume event for port %d\n", port_id);
@@ -1620,6 +1617,7 @@ static void handle_port_status(struct xhci_hcd *xhci,
bus_state->port_remote_wakeup |= 1 << faked_port_index;
xhci_test_and_clear_bit(xhci, port_array,
faked_port_index, PORT_PLC);
+ usb_hcd_start_port_resume(&hcd->self, faked_port_index);
xhci_set_link_state(xhci, port_array, faked_port_index,
XDEV_U0);
/* Need to wait until the next link state change
@@ -1657,8 +1655,6 @@ static void handle_port_status(struct xhci_hcd *xhci,
if (slot_id && xhci->devs[slot_id])
xhci_ring_device(xhci, slot_id);
if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
- bus_state->port_remote_wakeup &=
- ~(1 << faked_port_index);
xhci_test_and_clear_bit(xhci, port_array,
faked_port_index, PORT_PLC);
usb_wakeup_notification(hcd->self.root_hub,
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
old mode 100644
new mode 100755
index 919e0b8..0fcc23b
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -801,11 +801,8 @@ void xhci_shutdown(struct usb_hcd *hcd)
xhci_dbg_trace(xhci, trace_xhci_dbg_init,
"xhci_shutdown completed - status = %x",
readl(&xhci->op_regs->status));
-
- /* Yet another workaround for spurious wakeups at shutdown with HSW */
- if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
- pci_set_power_state(to_pci_dev(hcd->self.sysdev), PCI_D3hot);
}
+EXPORT_SYMBOL_GPL(xhci_shutdown);
#ifdef CONFIG_PM
static void xhci_save_registers(struct xhci_hcd *xhci)
@@ -976,7 +973,7 @@ static bool xhci_pending_portevent(struct xhci_hcd *xhci)
int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
{
int rc = 0;
- unsigned int delay = XHCI_MAX_HALT_USEC;
+ unsigned int delay = XHCI_MAX_HALT_USEC * 2;
struct usb_hcd *hcd = xhci_to_hcd(xhci);
u32 command;
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 016f7a1..6c0cfaa 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -316,6 +316,7 @@ struct xhci_op_regs {
#define XDEV_U3 (0x3 << 5)
#define XDEV_INACTIVE (0x6 << 5)
#define XDEV_POLLING (0x7 << 5)
+#define XDEV_RECOVERY (0x8 << 5)
#define XDEV_COMP_MODE (0xa << 5)
#define XDEV_RESUME (0xf << 5)
/* true: port has power (see HCC_PPC) */
@@ -1880,6 +1881,7 @@ int xhci_run(struct usb_hcd *hcd);
void xhci_stop(struct usb_hcd *hcd);
void xhci_shutdown(struct usb_hcd *hcd);
int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
+void xhci_shutdown(struct usb_hcd *hcd);
void xhci_init_driver(struct hc_driver *drv,
const struct xhci_driver_overrides *over);
diff --git a/drivers/usb/misc/adutux.c b/drivers/usb/misc/adutux.c
index f0c071d..7fb0590 100644
--- a/drivers/usb/misc/adutux.c
+++ b/drivers/usb/misc/adutux.c
@@ -685,7 +685,7 @@ static int adu_probe(struct usb_interface *interface,
init_waitqueue_head(&dev->read_wait);
init_waitqueue_head(&dev->write_wait);
- iface_desc = &interface->altsetting[0];
+ iface_desc = &interface->cur_altsetting[0];
/* set up the endpoint information */
for (i = 0; i < iface_desc->desc.bNumEndpoints; ++i) {
diff --git a/drivers/usb/misc/idmouse.c b/drivers/usb/misc/idmouse.c
index 9a67ae3..9cf8a9b 100644
--- a/drivers/usb/misc/idmouse.c
+++ b/drivers/usb/misc/idmouse.c
@@ -342,7 +342,7 @@ static int idmouse_probe(struct usb_interface *interface,
int result;
/* check if we have gotten the data or the hid interface */
- iface_desc = &interface->altsetting[0];
+ iface_desc = interface->cur_altsetting;
if (iface_desc->desc.bInterfaceClass != 0x0A)
return -ENODEV;
diff --git a/drivers/usb/mon/mon_bin.c b/drivers/usb/mon/mon_bin.c
index 80b37d2..bd1a8dc 100644
--- a/drivers/usb/mon/mon_bin.c
+++ b/drivers/usb/mon/mon_bin.c
@@ -1036,12 +1036,18 @@ static long mon_bin_ioctl(struct file *file, unsigned int cmd, unsigned long arg
mutex_lock(&rp->fetch_lock);
spin_lock_irqsave(&rp->b_lock, flags);
- mon_free_buff(rp->b_vec, rp->b_size/CHUNK_SIZE);
- kfree(rp->b_vec);
- rp->b_vec = vec;
- rp->b_size = size;
- rp->b_read = rp->b_in = rp->b_out = rp->b_cnt = 0;
- rp->cnt_lost = 0;
+ if (rp->mmap_active) {
+ mon_free_buff(vec, size/CHUNK_SIZE);
+ kfree(vec);
+ ret = -EBUSY;
+ } else {
+ mon_free_buff(rp->b_vec, rp->b_size/CHUNK_SIZE);
+ kfree(rp->b_vec);
+ rp->b_vec = vec;
+ rp->b_size = size;
+ rp->b_read = rp->b_in = rp->b_out = rp->b_cnt = 0;
+ rp->cnt_lost = 0;
+ }
spin_unlock_irqrestore(&rp->b_lock, flags);
mutex_unlock(&rp->fetch_lock);
}
@@ -1213,13 +1219,21 @@ mon_bin_poll(struct file *file, struct poll_table_struct *wait)
static void mon_bin_vma_open(struct vm_area_struct *vma)
{
struct mon_reader_bin *rp = vma->vm_private_data;
+ unsigned long flags;
+
+ spin_lock_irqsave(&rp->b_lock, flags);
rp->mmap_active++;
+ spin_unlock_irqrestore(&rp->b_lock, flags);
}
static void mon_bin_vma_close(struct vm_area_struct *vma)
{
+ unsigned long flags;
+
struct mon_reader_bin *rp = vma->vm_private_data;
+ spin_lock_irqsave(&rp->b_lock, flags);
rp->mmap_active--;
+ spin_unlock_irqrestore(&rp->b_lock, flags);
}
/*
@@ -1231,16 +1245,12 @@ static int mon_bin_vma_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
unsigned long offset, chunk_idx;
struct page *pageptr;
- mutex_lock(&rp->fetch_lock);
offset = vmf->pgoff << PAGE_SHIFT;
- if (offset >= rp->b_size) {
- mutex_unlock(&rp->fetch_lock);
+ if (offset >= rp->b_size)
return VM_FAULT_SIGBUS;
- }
chunk_idx = offset / CHUNK_SIZE;
pageptr = rp->b_vec[chunk_idx].pg;
get_page(pageptr);
- mutex_unlock(&rp->fetch_lock);
vmf->page = pageptr;
return 0;
}
diff --git a/drivers/usb/renesas_usbhs/common.h b/drivers/usb/renesas_usbhs/common.h
index b8620aa..8424c16 100644
--- a/drivers/usb/renesas_usbhs/common.h
+++ b/drivers/usb/renesas_usbhs/common.h
@@ -163,11 +163,12 @@ struct usbhs_priv;
#define VBSTS (1 << 7) /* VBUS_0 and VBUSIN_0 Input Status */
#define VALID (1 << 3) /* USB Request Receive */
-#define DVSQ_MASK (0x3 << 4) /* Device State */
+#define DVSQ_MASK (0x7 << 4) /* Device State */
#define POWER_STATE (0 << 4)
#define DEFAULT_STATE (1 << 4)
#define ADDRESS_STATE (2 << 4)
#define CONFIGURATION_STATE (3 << 4)
+#define SUSPENDED_STATE (4 << 4)
#define CTSQ_MASK (0x7) /* Control Transfer Stage */
#define IDLE_SETUP_STAGE 0 /* Idle stage or setup stage */
diff --git a/drivers/usb/renesas_usbhs/mod_gadget.c b/drivers/usb/renesas_usbhs/mod_gadget.c
index 6898ca1..b0397bc 100644
--- a/drivers/usb/renesas_usbhs/mod_gadget.c
+++ b/drivers/usb/renesas_usbhs/mod_gadget.c
@@ -465,12 +465,18 @@ static int usbhsg_irq_dev_state(struct usbhs_priv *priv,
{
struct usbhsg_gpriv *gpriv = usbhsg_priv_to_gpriv(priv);
struct device *dev = usbhsg_gpriv_to_dev(gpriv);
+ int state = usbhs_status_get_device_state(irq_state);
gpriv->gadget.speed = usbhs_bus_get_speed(priv);
- dev_dbg(dev, "state = %x : speed : %d\n",
- usbhs_status_get_device_state(irq_state),
- gpriv->gadget.speed);
+ dev_dbg(dev, "state = %x : speed : %d\n", state, gpriv->gadget.speed);
+
+ if (gpriv->gadget.speed != USB_SPEED_UNKNOWN &&
+ (state & SUSPENDED_STATE)) {
+ if (gpriv->driver && gpriv->driver->suspend)
+ gpriv->driver->suspend(&gpriv->gadget);
+ usb_gadget_set_state(&gpriv->gadget, USB_STATE_SUSPENDED);
+ }
return 0;
}
diff --git a/drivers/usb/serial/io_edgeport.c b/drivers/usb/serial/io_edgeport.c
index de61271..e5649ad 100644
--- a/drivers/usb/serial/io_edgeport.c
+++ b/drivers/usb/serial/io_edgeport.c
@@ -2852,16 +2852,18 @@ static int edge_startup(struct usb_serial *serial)
response = 0;
if (edge_serial->is_epic) {
+ struct usb_host_interface *alt;
+
+ alt = serial->interface->cur_altsetting;
+
/* EPIC thing, set up our interrupt polling now and our read
* urb, so that the device knows it really is connected. */
interrupt_in_found = bulk_in_found = bulk_out_found = false;
- for (i = 0; i < serial->interface->altsetting[0]
- .desc.bNumEndpoints; ++i) {
+ for (i = 0; i < alt->desc.bNumEndpoints; ++i) {
struct usb_endpoint_descriptor *endpoint;
int buffer_size;
- endpoint = &serial->interface->altsetting[0].
- endpoint[i].desc;
+ endpoint = &alt->endpoint[i].desc;
buffer_size = usb_endpoint_maxp(endpoint);
if (!interrupt_in_found &&
(usb_endpoint_is_int_in(endpoint))) {
diff --git a/drivers/usb/storage/uas.c b/drivers/usb/storage/uas.c
index 597bc55..a6999042 100644
--- a/drivers/usb/storage/uas.c
+++ b/drivers/usb/storage/uas.c
@@ -832,6 +832,10 @@ static int uas_slave_configure(struct scsi_device *sdev)
sdev->wce_default_on = 1;
}
+ /* Some disks cannot handle READ_CAPACITY_16 */
+ if (devinfo->flags & US_FL_NO_READ_CAPACITY_16)
+ sdev->no_read_capacity_16 = 1;
+
/*
* Some disks return the total number of blocks in response
* to READ CAPACITY rather than the highest block number.
@@ -841,6 +845,12 @@ static int uas_slave_configure(struct scsi_device *sdev)
sdev->fix_capacity = 1;
/*
+ * in some cases we have to guess
+ */
+ if (devinfo->flags & US_FL_CAPACITY_HEURISTICS)
+ sdev->guess_capacity = 1;
+
+ /*
* Some devices don't like MODE SENSE with page=0x3f,
* which is the command used for checking if a device
* is write-protected. Now that we tell the sd driver
diff --git a/drivers/usb/usbip/vhci_rx.c b/drivers/usb/usbip/vhci_rx.c
index 5943dee..a4f65aa 100644
--- a/drivers/usb/usbip/vhci_rx.c
+++ b/drivers/usb/usbip/vhci_rx.c
@@ -90,16 +90,21 @@ static void vhci_recv_ret_submit(struct vhci_device *vdev,
usbip_pack_pdu(pdu, urb, USBIP_RET_SUBMIT, 0);
/* recv transfer buffer */
- if (usbip_recv_xbuff(ud, urb) < 0)
- return;
+ if (usbip_recv_xbuff(ud, urb) < 0) {
+ urb->status = -EPROTO;
+ goto error;
+ }
/* recv iso_packet_descriptor */
- if (usbip_recv_iso(ud, urb) < 0)
- return;
+ if (usbip_recv_iso(ud, urb) < 0) {
+ urb->status = -EPROTO;
+ goto error;
+ }
/* restore the padding in iso packets */
usbip_pad_iso(ud, urb);
+error:
if (usbip_dbg_flag_vhci_rx)
usbip_dump_urb(urb);
diff --git a/drivers/vfio/pci/vfio_pci_intrs.c b/drivers/vfio/pci/vfio_pci_intrs.c
index 1c46045..94594dc 100644
--- a/drivers/vfio/pci/vfio_pci_intrs.c
+++ b/drivers/vfio/pci/vfio_pci_intrs.c
@@ -297,8 +297,8 @@ static int vfio_msi_set_vector_signal(struct vfio_pci_device *vdev,
irq = pci_irq_vector(pdev, vector);
if (vdev->ctx[vector].trigger) {
- free_irq(irq, vdev->ctx[vector].trigger);
irq_bypass_unregister_producer(&vdev->ctx[vector].producer);
+ free_irq(irq, vdev->ctx[vector].trigger);
kfree(vdev->ctx[vector].name);
eventfd_ctx_put(vdev->ctx[vector].trigger);
vdev->ctx[vector].trigger = NULL;
diff --git a/drivers/vhost/vsock.c b/drivers/vhost/vsock.c
index a775493..2e37097 100644
--- a/drivers/vhost/vsock.c
+++ b/drivers/vhost/vsock.c
@@ -399,7 +399,9 @@ static void vhost_vsock_handle_tx_kick(struct vhost_work *work)
len = pkt->len;
/* Only accept correctly addressed packets */
- if (le64_to_cpu(pkt->hdr.src_cid) == vsock->guest_cid)
+ if (le64_to_cpu(pkt->hdr.src_cid) == vsock->guest_cid &&
+ le64_to_cpu(pkt->hdr.dst_cid) ==
+ vhost_transport_get_local_cid())
virtio_transport_recv_pkt(pkt);
else
virtio_transport_free_pkt(pkt);
diff --git a/drivers/video/fbdev/msm/mdp3.h b/drivers/video/fbdev/msm/mdp3.h
index 3ab4652..e7294cb 100644
--- a/drivers/video/fbdev/msm/mdp3.h
+++ b/drivers/video/fbdev/msm/mdp3.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, 2016-2019, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, 2016-2020, The Linux Foundation. All rights reserved.
* Copyright (C) 2007 Google Incorporated
*
* This program is free software; you can redistribute it and/or modify
@@ -211,6 +211,8 @@ struct mdp3_hw_resource {
struct mutex reg_bus_lock;
int bklt_level;
int bklt_update;
+ bool secure_update_bl;
+ bool secure_reg_on;
bool twm_en;
u32 max_bw;
diff --git a/drivers/video/fbdev/msm/mdp3_ctrl.c b/drivers/video/fbdev/msm/mdp3_ctrl.c
index 09841d7..34869b8 100644
--- a/drivers/video/fbdev/msm/mdp3_ctrl.c
+++ b/drivers/video/fbdev/msm/mdp3_ctrl.c
@@ -948,6 +948,7 @@ static int mdp3_ctrl_on(struct msm_fb_data_type *mfd)
mutex_lock(&mdp3_session->lock);
MDSS_XLOG(XLOG_FUNC_ENTRY, __LINE__, mfd->panel_power_state);
+ mdp3_res->secure_update_bl = false;
panel = mdp3_session->panel;
/* make sure DSI host is initialized properly */
if (panel) {
@@ -1865,6 +1866,24 @@ static int mdp3_set_metadata(struct msm_fb_data_type *mfd,
return ret;
}
break;
+ case metadata_op_secure_bl_set:
+ if (mdss_panel_is_power_off(mfd->panel_power_state) &&
+ mfd->panel.type == SPI_PANEL) {
+ mfd->allow_secure_bl_update =
+ metadata_ptr->data.sec_bl_update_en;
+ mdp3_res->secure_update_bl =
+ mfd->allow_secure_bl_update;
+ }
+ pr_debug("Secure backlight = %d,panel power state = %d\n",
+ mfd->allow_secure_bl_update, mfd->panel_power_state);
+ break;
+ case metadata_op_secure_reg:
+ if (mfd->panel.type == SPI_PANEL) {
+ mdp3_res->secure_reg_on = metadata_ptr->data.sec_reg_on;
+ pr_debug("Secure regulator_on flag is %d\n",
+ mdp3_res->secure_reg_on);
+ }
+ break;
default:
pr_warn("Unsupported request to MDP SET META IOCTL.\n");
ret = -EINVAL;
@@ -2813,7 +2832,8 @@ static int mdp3_ctrl_ioctl_handler(struct msm_fb_data_type *mfd,
req = &mdp3_session->req_overlay;
if (!mdp3_session->status && cmd != MSMFB_METADATA_GET &&
- cmd != MSMFB_HISTOGRAM_STOP && cmd != MSMFB_HISTOGRAM) {
+ cmd != MSMFB_METADATA_SET && cmd != MSMFB_HISTOGRAM_STOP &&
+ cmd != MSMFB_HISTOGRAM) {
pr_err("mdp3_ctrl_ioctl_handler, display off!\n");
return -EPERM;
}
diff --git a/drivers/video/fbdev/msm/mdss_compat_utils.h b/drivers/video/fbdev/msm/mdss_compat_utils.h
index 819106b..10c5011 100644
--- a/drivers/video/fbdev/msm/mdss_compat_utils.h
+++ b/drivers/video/fbdev/msm/mdss_compat_utils.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2016, 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2016, 2018,2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -88,6 +88,8 @@ struct msmfb_metadata32 {
uint32_t video_info_code;
struct mdss_hw_caps caps;
uint8_t secure_en;
+ bool sec_bl_update_en;
+ bool sec_reg_on;
} data;
};
diff --git a/drivers/video/fbdev/msm/mdss_fb.c b/drivers/video/fbdev/msm/mdss_fb.c
index 3a5dd02..0c71e24 100644
--- a/drivers/video/fbdev/msm/mdss_fb.c
+++ b/drivers/video/fbdev/msm/mdss_fb.c
@@ -2,7 +2,7 @@
* Core MDSS framebuffer driver.
*
* Copyright (C) 2007 Google Incorporated
- * Copyright (c) 2008-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2008-2020, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -1716,13 +1716,14 @@ void mdss_fb_set_backlight(struct msm_fb_data_type *mfd, u32 bkl_lvl)
bool twm_en = false;
if ((((mdss_fb_is_power_off(mfd) && mfd->dcm_state != DCM_ENTER)
- || !mfd->allow_bl_update) && !IS_CALIB_MODE_BL(mfd)) ||
+ || !mfd->allow_bl_update) && !IS_CALIB_MODE_BL(mfd) &&
+ !mfd->allow_secure_bl_update) ||
mfd->panel_info->cont_splash_enabled) {
mfd->unset_bl_level = bkl_lvl;
return;
} else if (mdss_fb_is_power_on(mfd) && mfd->panel_info->panel_dead) {
mfd->unset_bl_level = mfd->bl_level;
- } else {
+ } else if (!mfd->allow_secure_bl_update) {
mfd->unset_bl_level = U32_MAX;
}
@@ -1734,6 +1735,9 @@ void mdss_fb_set_backlight(struct msm_fb_data_type *mfd, u32 bkl_lvl)
&ad_bl_notify_needed);
if (!IS_CALIB_MODE_BL(mfd))
mdss_fb_scale_bl(mfd, &temp);
+
+ if (!temp && !mfd->allow_secure_bl_update && mfd->bl_level)
+ mfd->unset_bl_level = mfd->bl_level;
/*
* Even though backlight has been scaled, want to show that
* backlight has been set to bkl_lvl to those that read from
@@ -1914,7 +1918,8 @@ static int mdss_fb_blank_blank(struct msm_fb_data_type *mfd,
mfd->allow_bl_update = true;
mdss_fb_set_backlight(mfd, 0);
mfd->allow_bl_update = false;
- mfd->unset_bl_level = current_bl;
+ if (current_bl)
+ mfd->unset_bl_level = current_bl;
mutex_unlock(&mfd->bl_lock);
}
mfd->panel_power_state = req_power_state;
@@ -1960,6 +1965,8 @@ static int mdss_fb_blank_unblank(struct msm_fb_data_type *mfd)
return 0;
}
+ mfd->allow_secure_bl_update = false;
+
if (mfd->mdp.on_fnc) {
struct mdss_panel_info *panel_info = mfd->panel_info;
struct fb_var_screeninfo *var = &mfd->fbi->var;
@@ -3326,6 +3333,7 @@ static int mdss_fb_pan_display_ex(struct fb_info *info,
mfd->msm_fb_backup.info = *info;
mfd->msm_fb_backup.disp_commit = *disp_commit;
+ atomic_inc(&mfd->mdp_sync_pt_data.commit_cnt);
atomic_inc(&mfd->commits_pending);
atomic_inc(&mfd->kickoff_pending);
wake_up_all(&mfd->commit_wait_q);
@@ -4429,7 +4437,7 @@ static int mdss_fb_handle_buf_sync_ioctl(struct msm_sync_pt_data *sync_pt_data,
if (IS_ERR_OR_NULL(retire_fence)) {
val += sync_pt_data->retire_threshold;
retire_fence = mdss_fb_sync_get_fence(
- sync_pt_data->timeline, "mdp-retire", val);
+ sync_pt_data->timeline_retire, "mdp-retire", val);
}
if (IS_ERR_OR_NULL(retire_fence)) {
diff --git a/drivers/video/fbdev/msm/mdss_fb.h b/drivers/video/fbdev/msm/mdss_fb.h
index 38cf5f7..4b39f9e 100644
--- a/drivers/video/fbdev/msm/mdss_fb.h
+++ b/drivers/video/fbdev/msm/mdss_fb.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2008-2018, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2008-2018,2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -322,6 +322,7 @@ struct msm_fb_data_type {
struct mutex bl_lock;
struct mutex mdss_sysfs_lock;
bool ipc_resume;
+ bool allow_secure_bl_update;
struct platform_device *pdev;
diff --git a/drivers/video/fbdev/msm/mdss_spi_panel.c b/drivers/video/fbdev/msm/mdss_spi_panel.c
index 86a1c1c..e95dcd5 100644
--- a/drivers/video/fbdev/msm/mdss_spi_panel.c
+++ b/drivers/video/fbdev/msm/mdss_spi_panel.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2017-2018,2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -163,12 +163,14 @@ static int mdss_spi_panel_power_on(struct mdss_panel_data *pdata)
ctrl_pdata = container_of(pdata, struct spi_panel_data,
panel_data);
- ret = msm_mdss_enable_vreg(
- ctrl_pdata->panel_power_data.vreg_config,
- ctrl_pdata->panel_power_data.num_vreg, 1);
- if (ret) {
- pr_err("%s: failed to enable vregs for %s\n",
- __func__, "PANEL_PM");
+ if (!mdp3_res->secure_reg_on) {
+ ret = msm_mdss_enable_vreg(
+ ctrl_pdata->panel_power_data.vreg_config,
+ ctrl_pdata->panel_power_data.num_vreg, 1);
+ if (ret) {
+ pr_err("%s: failed to enable vregs for %s\n",
+ __func__, "PANEL_PM");
+ }
}
/*
@@ -213,12 +215,14 @@ static int mdss_spi_panel_power_off(struct mdss_panel_data *pdata)
if (mdss_spi_panel_pinctrl_set_state(ctrl_pdata, false))
pr_warn("reset disable: pinctrl not enabled\n");
- ret = msm_mdss_enable_vreg(
- ctrl_pdata->panel_power_data.vreg_config,
- ctrl_pdata->panel_power_data.num_vreg, 0);
- if (ret)
- pr_err("%s: failed to disable vregs for %s\n",
- __func__, "PANEL_PM");
+ if (!mdp3_res->secure_reg_on) {
+ ret = msm_mdss_enable_vreg(
+ ctrl_pdata->panel_power_data.vreg_config,
+ ctrl_pdata->panel_power_data.num_vreg, 0);
+ if (ret)
+ pr_err("%s: failed to disable vregs for %s\n",
+ __func__, "PANEL_PM");
+ }
end:
return ret;
@@ -1167,7 +1171,8 @@ static void mdss_spi_panel_bklt_pwm(struct spi_panel_data *ctrl, int level)
static void mdss_spi_panel_bl_ctrl(struct mdss_panel_data *pdata,
u32 bl_level)
{
- if (bl_level) {
+ /* Allow panel backlight update if secure UI is enabled */
+ if (bl_level && !mdp3_res->secure_update_bl) {
mdp3_res->bklt_level = bl_level;
mdp3_res->bklt_update = true;
} else {
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 111a0ab..ce7c4a2 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -1036,12 +1036,12 @@ static int hdmi_avi_infoframe_unpack(struct hdmi_avi_infoframe *frame,
if (ptr[0] & 0x10)
frame->active_aspect = ptr[1] & 0xf;
if (ptr[0] & 0x8) {
- frame->top_bar = (ptr[5] << 8) + ptr[6];
- frame->bottom_bar = (ptr[7] << 8) + ptr[8];
+ frame->top_bar = (ptr[6] << 8) | ptr[5];
+ frame->bottom_bar = (ptr[8] << 8) | ptr[7];
}
if (ptr[0] & 0x4) {
- frame->left_bar = (ptr[9] << 8) + ptr[10];
- frame->right_bar = (ptr[11] << 8) + ptr[12];
+ frame->left_bar = (ptr[10] << 8) | ptr[9];
+ frame->right_bar = (ptr[12] << 8) | ptr[11];
}
frame->scan_mode = ptr[0] & 0x3;
diff --git a/drivers/virtio/virtio_balloon.c b/drivers/virtio/virtio_balloon.c
index 30076956..4e64a3b 100644
--- a/drivers/virtio/virtio_balloon.c
+++ b/drivers/virtio/virtio_balloon.c
@@ -482,6 +482,17 @@ static int virtballoon_migratepage(struct balloon_dev_info *vb_dev_info,
get_page(newpage); /* balloon reference */
+ /*
+ * When we migrate a page to a different zone and adjusted the
+ * managed page count when inflating, we have to fixup the count of
+ * both involved zones.
+ */
+ if (!virtio_has_feature(vb->vdev, VIRTIO_BALLOON_F_DEFLATE_ON_OOM) &&
+ page_zone(page) != page_zone(newpage)) {
+ adjust_managed_page_count(page, 1);
+ adjust_managed_page_count(newpage, -1);
+ }
+
/* balloon's page migration 1st step -- inflate "newpage" */
spin_lock_irqsave(&vb_dev_info->pages_lock, flags);
balloon_page_insert(vb_dev_info, newpage);
diff --git a/fs/autofs4/expire.c b/fs/autofs4/expire.c
index 2e1f50e..02f0d37 100644
--- a/fs/autofs4/expire.c
+++ b/fs/autofs4/expire.c
@@ -469,9 +469,10 @@ struct dentry *autofs4_expire_indirect(struct super_block *sb,
*/
flags &= ~AUTOFS_EXP_LEAVES;
found = should_expire(expired, mnt, timeout, how);
- if (!found || found != expired)
- /* Something has changed, continue */
+ if (found != expired) { // something has changed, continue
+ dput(found);
goto next;
+ }
if (expired != dentry)
dput(dentry);
diff --git a/fs/btrfs/async-thread.c b/fs/btrfs/async-thread.c
index ff0b0be..a3de11d 100644
--- a/fs/btrfs/async-thread.c
+++ b/fs/btrfs/async-thread.c
@@ -265,16 +265,17 @@ static inline void thresh_exec_hook(struct __btrfs_workqueue *wq)
}
}
-static void run_ordered_work(struct __btrfs_workqueue *wq)
+static void run_ordered_work(struct __btrfs_workqueue *wq,
+ struct btrfs_work *self)
{
struct list_head *list = &wq->ordered_list;
struct btrfs_work *work;
spinlock_t *lock = &wq->list_lock;
unsigned long flags;
+ void *wtag;
+ bool free_self = false;
while (1) {
- void *wtag;
-
spin_lock_irqsave(lock, flags);
if (list_empty(list))
break;
@@ -300,16 +301,47 @@ static void run_ordered_work(struct __btrfs_workqueue *wq)
list_del(&work->ordered_list);
spin_unlock_irqrestore(lock, flags);
- /*
- * We don't want to call the ordered free functions with the
- * lock held though. Save the work as tag for the trace event,
- * because the callback could free the structure.
- */
- wtag = work;
- work->ordered_free(work);
- trace_btrfs_all_work_done(wq->fs_info, wtag);
+ if (work == self) {
+ /*
+ * This is the work item that the worker is currently
+ * executing.
+ *
+ * The kernel workqueue code guarantees non-reentrancy
+ * of work items. I.e., if a work item with the same
+ * address and work function is queued twice, the second
+ * execution is blocked until the first one finishes. A
+ * work item may be freed and recycled with the same
+ * work function; the workqueue code assumes that the
+ * original work item cannot depend on the recycled work
+ * item in that case (see find_worker_executing_work()).
+ *
+ * Note that the work of one Btrfs filesystem may depend
+ * on the work of another Btrfs filesystem via, e.g., a
+ * loop device. Therefore, we must not allow the current
+ * work item to be recycled until we are really done,
+ * otherwise we break the above assumption and can
+ * deadlock.
+ */
+ free_self = true;
+ } else {
+ /*
+ * We don't want to call the ordered free functions with
+ * the lock held though. Save the work as tag for the
+ * trace event, because the callback could free the
+ * structure.
+ */
+ wtag = work;
+ work->ordered_free(work);
+ trace_btrfs_all_work_done(wq->fs_info, wtag);
+ }
}
spin_unlock_irqrestore(lock, flags);
+
+ if (free_self) {
+ wtag = self;
+ self->ordered_free(self);
+ trace_btrfs_all_work_done(wq->fs_info, wtag);
+ }
}
static void normal_work_helper(struct btrfs_work *work)
@@ -337,7 +369,7 @@ static void normal_work_helper(struct btrfs_work *work)
work->func(work);
if (need_order) {
set_bit(WORK_DONE_BIT, &work->flags);
- run_ordered_work(wq);
+ run_ordered_work(wq, work);
}
if (!need_order)
trace_btrfs_all_work_done(wq->fs_info, wtag);
diff --git a/fs/btrfs/ctree.c b/fs/btrfs/ctree.c
index 3faccbf..305deb6 100644
--- a/fs/btrfs/ctree.c
+++ b/fs/btrfs/ctree.c
@@ -424,7 +424,7 @@ void btrfs_put_tree_mod_seq(struct btrfs_fs_info *fs_info,
for (node = rb_first(tm_root); node; node = next) {
next = rb_next(node);
tm = container_of(node, struct tree_mod_elem, node);
- if (tm->seq > min_seq)
+ if (tm->seq >= min_seq)
continue;
rb_erase(node, tm_root);
kfree(tm);
diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c
index 8c4120b..bab3b84 100644
--- a/fs/btrfs/disk-io.c
+++ b/fs/btrfs/disk-io.c
@@ -1712,8 +1712,8 @@ static void end_workqueue_fn(struct btrfs_work *work)
bio->bi_error = end_io_wq->error;
bio->bi_private = end_io_wq->private;
bio->bi_end_io = end_io_wq->end_io;
- kmem_cache_free(btrfs_end_io_wq_cache, end_io_wq);
bio_endio(bio);
+ kmem_cache_free(btrfs_end_io_wq_cache, end_io_wq);
}
static int cleaner_kthread(void *arg)
diff --git a/fs/btrfs/extent_io.c b/fs/btrfs/extent_io.c
index 84051b2..36eabea 100644
--- a/fs/btrfs/extent_io.c
+++ b/fs/btrfs/extent_io.c
@@ -4983,12 +4983,14 @@ struct extent_buffer *alloc_test_extent_buffer(struct btrfs_fs_info *fs_info,
return eb;
eb = alloc_dummy_extent_buffer(fs_info, start, nodesize);
if (!eb)
- return NULL;
+ return ERR_PTR(-ENOMEM);
eb->fs_info = fs_info;
again:
ret = radix_tree_preload(GFP_NOFS);
- if (ret)
+ if (ret) {
+ exists = ERR_PTR(ret);
goto free_eb;
+ }
spin_lock(&fs_info->buffer_lock);
ret = radix_tree_insert(&fs_info->buffer_radix,
start >> PAGE_SHIFT, eb);
diff --git a/fs/btrfs/file.c b/fs/btrfs/file.c
index 6cdf273..03661b7 100644
--- a/fs/btrfs/file.c
+++ b/fs/btrfs/file.c
@@ -1555,6 +1555,7 @@ static noinline ssize_t __btrfs_buffered_write(struct file *file,
break;
}
+ only_release_metadata = false;
sector_offset = pos & (root->sectorsize - 1);
reserve_bytes = round_up(write_bytes + sector_offset,
root->sectorsize);
@@ -1704,7 +1705,6 @@ static noinline ssize_t __btrfs_buffered_write(struct file *file,
set_extent_bit(&BTRFS_I(inode)->io_tree, lockstart,
lockend, EXTENT_NORESERVE, NULL,
NULL, GFP_NOFS);
- only_release_metadata = false;
}
btrfs_drop_pages(pages, num_pages);
diff --git a/fs/btrfs/free-space-cache.c b/fs/btrfs/free-space-cache.c
index 69a3c11..a84a1ce 100644
--- a/fs/btrfs/free-space-cache.c
+++ b/fs/btrfs/free-space-cache.c
@@ -391,6 +391,12 @@ static int io_ctl_prepare_pages(struct btrfs_io_ctl *io_ctl, struct inode *inode
if (uptodate && !PageUptodate(page)) {
btrfs_readpage(NULL, page);
lock_page(page);
+ if (page->mapping != inode->i_mapping) {
+ btrfs_err(BTRFS_I(inode)->root->fs_info,
+ "free space cache page truncated");
+ io_ctl_drop_pages(io_ctl);
+ return -EIO;
+ }
if (!PageUptodate(page)) {
btrfs_err(BTRFS_I(inode)->root->fs_info,
"error reading free space cache");
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index 1b1a9e3..250c840 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -5576,7 +5576,6 @@ static void inode_tree_del(struct inode *inode)
spin_unlock(&root->inode_lock);
if (empty && btrfs_root_refs(&root->root_item) == 0) {
- synchronize_srcu(&root->fs_info->subvol_srcu);
spin_lock(&root->inode_lock);
empty = RB_EMPTY_ROOT(&root->inode_tree);
spin_unlock(&root->inode_lock);
@@ -9597,9 +9596,8 @@ static int btrfs_rename_exchange(struct inode *old_dir,
return -EXDEV;
/* close the race window with snapshot create/destroy ioctl */
- if (old_ino == BTRFS_FIRST_FREE_OBJECTID)
- down_read(&root->fs_info->subvol_sem);
- if (new_ino == BTRFS_FIRST_FREE_OBJECTID)
+ if (old_ino == BTRFS_FIRST_FREE_OBJECTID ||
+ new_ino == BTRFS_FIRST_FREE_OBJECTID)
down_read(&dest->fs_info->subvol_sem);
/*
@@ -9616,6 +9614,9 @@ static int btrfs_rename_exchange(struct inode *old_dir,
goto out_notrans;
}
+ if (dest != root)
+ btrfs_record_root_in_trans(trans, dest);
+
/*
* We need to find a free sequence number both in the source and
* in the destination directory for the exchange.
@@ -9782,9 +9783,8 @@ static int btrfs_rename_exchange(struct inode *old_dir,
ret2 = btrfs_end_transaction(trans, root);
ret = ret ? ret : ret2;
out_notrans:
- if (new_ino == BTRFS_FIRST_FREE_OBJECTID)
- up_read(&dest->fs_info->subvol_sem);
- if (old_ino == BTRFS_FIRST_FREE_OBJECTID)
+ if (new_ino == BTRFS_FIRST_FREE_OBJECTID ||
+ old_ino == BTRFS_FIRST_FREE_OBJECTID)
up_read(&root->fs_info->subvol_sem);
return ret;
diff --git a/fs/btrfs/ioctl.c b/fs/btrfs/ioctl.c
index a67143c..eefe103 100644
--- a/fs/btrfs/ioctl.c
+++ b/fs/btrfs/ioctl.c
@@ -610,12 +610,18 @@ static noinline int create_subvol(struct inode *dir,
btrfs_i_size_write(dir, dir->i_size + namelen * 2);
ret = btrfs_update_inode(trans, root, dir);
- BUG_ON(ret);
+ if (ret) {
+ btrfs_abort_transaction(trans, ret);
+ goto fail;
+ }
ret = btrfs_add_root_ref(trans, root->fs_info->tree_root,
objectid, root->root_key.objectid,
btrfs_ino(dir), index, name, namelen);
- BUG_ON(ret);
+ if (ret) {
+ btrfs_abort_transaction(trans, ret);
+ goto fail;
+ }
ret = btrfs_uuid_tree_add(trans, root->fs_info->uuid_root,
root_item->uuid, BTRFS_UUID_KEY_SUBVOL,
diff --git a/fs/btrfs/reada.c b/fs/btrfs/reada.c
index 94441fd..0d1565d 100644
--- a/fs/btrfs/reada.c
+++ b/fs/btrfs/reada.c
@@ -734,21 +734,19 @@ static int reada_start_machine_dev(struct btrfs_fs_info *fs_info,
static void reada_start_machine_worker(struct btrfs_work *work)
{
struct reada_machine_work *rmw;
- struct btrfs_fs_info *fs_info;
int old_ioprio;
rmw = container_of(work, struct reada_machine_work, work);
- fs_info = rmw->fs_info;
-
- kfree(rmw);
old_ioprio = IOPRIO_PRIO_VALUE(task_nice_ioclass(current),
task_nice_ioprio(current));
set_task_ioprio(current, BTRFS_IOPRIO_READA);
- __reada_start_machine(fs_info);
+ __reada_start_machine(rmw->fs_info);
set_task_ioprio(current, old_ioprio);
- atomic_dec(&fs_info->reada_works_cnt);
+ atomic_dec(&rmw->fs_info->reada_works_cnt);
+
+ kfree(rmw);
}
static void __reada_start_machine(struct btrfs_fs_info *fs_info)
diff --git a/fs/btrfs/relocation.c b/fs/btrfs/relocation.c
index b0c3a6a..b106d36 100644
--- a/fs/btrfs/relocation.c
+++ b/fs/btrfs/relocation.c
@@ -4587,6 +4587,7 @@ int btrfs_recover_relocation(struct btrfs_root *root)
reloc_root->root_key.offset);
if (IS_ERR(fs_root)) {
err = PTR_ERR(fs_root);
+ list_add_tail(&reloc_root->root_list, &reloc_roots);
goto out_free;
}
diff --git a/fs/btrfs/send.c b/fs/btrfs/send.c
index d9e4970..edfc7ba 100644
--- a/fs/btrfs/send.c
+++ b/fs/btrfs/send.c
@@ -37,6 +37,14 @@
#include "compression.h"
/*
+ * Maximum number of references an extent can have in order for us to attempt to
+ * issue clone operations instead of write operations. This currently exists to
+ * avoid hitting limitations of the backreference walking code (taking a lot of
+ * time and using too much memory for extents with large number of references).
+ */
+#define SEND_MAX_EXTENT_REFS 64
+
+/*
* A fs_path is a helper to dynamically build path names with unknown size.
* It reallocates the internal buffer on demand.
* It allows fast adding of path elements on the right side (normal path) and
@@ -1327,6 +1335,7 @@ static int find_extent_clone(struct send_ctx *sctx,
struct clone_root *cur_clone_root;
struct btrfs_key found_key;
struct btrfs_path *tmp_path;
+ struct btrfs_extent_item *ei;
int compressed;
u32 i;
@@ -1376,7 +1385,6 @@ static int find_extent_clone(struct send_ctx *sctx,
ret = extent_from_logical(fs_info, disk_byte, tmp_path,
&found_key, &flags);
up_read(&fs_info->commit_root_sem);
- btrfs_release_path(tmp_path);
if (ret < 0)
goto out;
@@ -1385,6 +1393,21 @@ static int find_extent_clone(struct send_ctx *sctx,
goto out;
}
+ ei = btrfs_item_ptr(tmp_path->nodes[0], tmp_path->slots[0],
+ struct btrfs_extent_item);
+ /*
+ * Backreference walking (iterate_extent_inodes() below) is currently
+ * too expensive when an extent has a large number of references, both
+ * in time spent and used memory. So for now just fallback to write
+ * operations instead of clone operations when an extent has more than
+ * a certain amount of references.
+ */
+ if (btrfs_extent_refs(tmp_path->nodes[0], ei) > SEND_MAX_EXTENT_REFS) {
+ ret = -ENOENT;
+ goto out;
+ }
+ btrfs_release_path(tmp_path);
+
/*
* Setup the clone roots.
*/
diff --git a/fs/btrfs/tests/free-space-tree-tests.c b/fs/btrfs/tests/free-space-tree-tests.c
index a724d9a..5e3b875 100644
--- a/fs/btrfs/tests/free-space-tree-tests.c
+++ b/fs/btrfs/tests/free-space-tree-tests.c
@@ -476,9 +476,9 @@ static int run_test(test_func_t test_func, int bitmaps, u32 sectorsize,
root->node = alloc_test_extent_buffer(root->fs_info,
nodesize, nodesize);
- if (!root->node) {
- test_msg("Couldn't allocate dummy buffer\n");
- ret = -ENOMEM;
+ if (IS_ERR(root->node)) {
+ test_msg("couldn't allocate dummy buffer\n");
+ ret = PTR_ERR(root->node);
goto out;
}
btrfs_set_header_level(root->node, 0);
diff --git a/fs/btrfs/tests/qgroup-tests.c b/fs/btrfs/tests/qgroup-tests.c
index 9c66666..e0aa6b9 100644
--- a/fs/btrfs/tests/qgroup-tests.c
+++ b/fs/btrfs/tests/qgroup-tests.c
@@ -488,9 +488,9 @@ int btrfs_test_qgroups(u32 sectorsize, u32 nodesize)
*/
root->node = alloc_test_extent_buffer(root->fs_info, nodesize,
nodesize);
- if (!root->node) {
+ if (IS_ERR(root->node)) {
test_msg("Couldn't allocate dummy buffer\n");
- ret = -ENOMEM;
+ ret = PTR_ERR(root->node);
goto out;
}
btrfs_set_header_level(root->node, 0);
diff --git a/fs/btrfs/tree-log.c b/fs/btrfs/tree-log.c
index 65e1eaa..7ee573c 100644
--- a/fs/btrfs/tree-log.c
+++ b/fs/btrfs/tree-log.c
@@ -5702,9 +5702,28 @@ int btrfs_recover_log_trees(struct btrfs_root *log_root_tree)
wc.replay_dest = btrfs_read_fs_root_no_name(fs_info, &tmp_key);
if (IS_ERR(wc.replay_dest)) {
ret = PTR_ERR(wc.replay_dest);
+
+ /*
+ * We didn't find the subvol, likely because it was
+ * deleted. This is ok, simply skip this log and go to
+ * the next one.
+ *
+ * We need to exclude the root because we can't have
+ * other log replays overwriting this log as we'll read
+ * it back in a few more times. This will keep our
+ * block from being modified, and we'll just bail for
+ * each subsequent pass.
+ */
+ if (ret == -ENOENT)
+ ret = btrfs_pin_extent_for_log_replay(fs_info->extent_root,
+ log->node->start,
+ log->node->len);
free_extent_buffer(log->node);
free_extent_buffer(log->commit_root);
kfree(log);
+
+ if (!ret)
+ goto next;
btrfs_handle_fs_error(fs_info, ret,
"Couldn't read target root for tree log recovery.");
goto error;
@@ -5736,7 +5755,6 @@ int btrfs_recover_log_trees(struct btrfs_root *log_root_tree)
&root->highest_objectid);
}
- key.offset = found_key.offset - 1;
wc.replay_dest->log_root = NULL;
free_extent_buffer(log->node);
free_extent_buffer(log->commit_root);
@@ -5744,9 +5762,10 @@ int btrfs_recover_log_trees(struct btrfs_root *log_root_tree)
if (ret)
goto error;
-
+next:
if (found_key.offset == 0)
break;
+ key.offset = found_key.offset - 1;
}
btrfs_release_path(path);
diff --git a/fs/btrfs/uuid-tree.c b/fs/btrfs/uuid-tree.c
index 83bb2f2..ee1c76c 100644
--- a/fs/btrfs/uuid-tree.c
+++ b/fs/btrfs/uuid-tree.c
@@ -335,6 +335,8 @@ int btrfs_uuid_tree_iterate(struct btrfs_fs_info *fs_info,
}
if (ret < 0 && ret != -ENOENT)
goto out;
+ key.offset++;
+ goto again_search_slot;
}
item_size -= sizeof(subid_le);
offset += sizeof(subid_le);
diff --git a/fs/btrfs/volumes.h b/fs/btrfs/volumes.h
index 663d668..96c1b84 100644
--- a/fs/btrfs/volumes.h
+++ b/fs/btrfs/volumes.h
@@ -312,7 +312,6 @@ struct btrfs_bio {
u64 map_type; /* get from map_lookup->type */
bio_end_io_t *end_io;
struct bio *orig_bio;
- unsigned long flags;
void *private;
atomic_t error;
int max_errors;
diff --git a/fs/cifs/file.c b/fs/cifs/file.c
index 1c3f262..09d8327 100644
--- a/fs/cifs/file.c
+++ b/fs/cifs/file.c
@@ -312,9 +312,6 @@ cifs_new_fileinfo(struct cifs_fid *fid, struct file *file,
INIT_LIST_HEAD(&fdlocks->locks);
fdlocks->cfile = cfile;
cfile->llist = fdlocks;
- cifs_down_write(&cinode->lock_sem);
- list_add(&fdlocks->llist, &cinode->llist);
- up_write(&cinode->lock_sem);
cfile->count = 1;
cfile->pid = current->tgid;
@@ -338,6 +335,10 @@ cifs_new_fileinfo(struct cifs_fid *fid, struct file *file,
oplock = 0;
}
+ cifs_down_write(&cinode->lock_sem);
+ list_add(&fdlocks->llist, &cinode->llist);
+ up_write(&cinode->lock_sem);
+
spin_lock(&tcon->open_file_lock);
if (fid->pending_open->oplock != CIFS_OPLOCK_NO_CHANGE && oplock)
oplock = fid->pending_open->oplock;
@@ -721,6 +722,13 @@ cifs_reopen_file(struct cifsFileInfo *cfile, bool can_flush)
if (backup_cred(cifs_sb))
create_options |= CREATE_OPEN_BACKUP_INTENT;
+ /* O_SYNC also has bit for O_DSYNC so following check picks up either */
+ if (cfile->f_flags & O_SYNC)
+ create_options |= CREATE_WRITE_THROUGH;
+
+ if (cfile->f_flags & O_DIRECT)
+ create_options |= CREATE_NO_BUFFER;
+
if (server->ops->get_lease_key)
server->ops->get_lease_key(inode, &cfile->fid);
diff --git a/fs/cifs/smb2misc.c b/fs/cifs/smb2misc.c
index 9994d15..7b7b47e 100644
--- a/fs/cifs/smb2misc.c
+++ b/fs/cifs/smb2misc.c
@@ -617,10 +617,10 @@ smb2_is_valid_oplock_break(char *buffer, struct TCP_Server_Info *server)
spin_lock(&cifs_tcp_ses_lock);
list_for_each(tmp, &server->smb_ses_list) {
ses = list_entry(tmp, struct cifs_ses, smb_ses_list);
+
list_for_each(tmp1, &ses->tcon_list) {
tcon = list_entry(tmp1, struct cifs_tcon, tcon_list);
- cifs_stats_inc(&tcon->stats.cifs_stats.num_oplock_brks);
spin_lock(&tcon->open_file_lock);
list_for_each(tmp2, &tcon->openFileList) {
cfile = list_entry(tmp2, struct cifsFileInfo,
@@ -632,6 +632,8 @@ smb2_is_valid_oplock_break(char *buffer, struct TCP_Server_Info *server)
continue;
cifs_dbg(FYI, "file id match, oplock break\n");
+ cifs_stats_inc(
+ &tcon->stats.cifs_stats.num_oplock_brks);
cinode = CIFS_I(d_inode(cfile->dentry));
spin_lock(&cfile->file_info_lock);
if (!CIFS_CACHE_WRITE(cinode) &&
@@ -664,9 +666,6 @@ smb2_is_valid_oplock_break(char *buffer, struct TCP_Server_Info *server)
return true;
}
spin_unlock(&tcon->open_file_lock);
- spin_unlock(&cifs_tcp_ses_lock);
- cifs_dbg(FYI, "No matching file for oplock break\n");
- return true;
}
}
spin_unlock(&cifs_tcp_ses_lock);
diff --git a/fs/dlm/lockspace.c b/fs/dlm/lockspace.c
index 30e4e01..b14bb2c 100644
--- a/fs/dlm/lockspace.c
+++ b/fs/dlm/lockspace.c
@@ -800,6 +800,7 @@ static int release_lockspace(struct dlm_ls *ls, int force)
dlm_delete_debug_file(ls);
+ idr_destroy(&ls->ls_recover_idr);
kfree(ls->ls_recover_buf);
/*
diff --git a/fs/dlm/memory.c b/fs/dlm/memory.c
index 7cd24bc..37be29f 100644
--- a/fs/dlm/memory.c
+++ b/fs/dlm/memory.c
@@ -38,10 +38,8 @@ int __init dlm_memory_init(void)
void dlm_memory_exit(void)
{
- if (lkb_cache)
- kmem_cache_destroy(lkb_cache);
- if (rsb_cache)
- kmem_cache_destroy(rsb_cache);
+ kmem_cache_destroy(lkb_cache);
+ kmem_cache_destroy(rsb_cache);
}
char *dlm_allocate_lvb(struct dlm_ls *ls)
@@ -86,8 +84,7 @@ void dlm_free_lkb(struct dlm_lkb *lkb)
struct dlm_user_args *ua;
ua = lkb->lkb_ua;
if (ua) {
- if (ua->lksb.sb_lvbptr)
- kfree(ua->lksb.sb_lvbptr);
+ kfree(ua->lksb.sb_lvbptr);
kfree(ua);
}
}
diff --git a/fs/dlm/user.c b/fs/dlm/user.c
index 57f2aac..bb0d307 100644
--- a/fs/dlm/user.c
+++ b/fs/dlm/user.c
@@ -25,6 +25,7 @@
#include "lvb_table.h"
#include "user.h"
#include "ast.h"
+#include "config.h"
static const char name_prefix[] = "dlm";
static const struct file_operations device_fops;
@@ -402,7 +403,7 @@ static int device_create_lockspace(struct dlm_lspace_params *params)
if (!capable(CAP_SYS_ADMIN))
return -EPERM;
- error = dlm_new_lockspace(params->name, NULL, params->flags,
+ error = dlm_new_lockspace(params->name, dlm_config.ci_cluster_name, params->flags,
DLM_USER_LVB_LEN, NULL, NULL, NULL,
&lockspace);
if (error)
diff --git a/fs/exportfs/expfs.c b/fs/exportfs/expfs.c
index 7a7bba7..3706939 100644
--- a/fs/exportfs/expfs.c
+++ b/fs/exportfs/expfs.c
@@ -506,26 +506,33 @@ struct dentry *exportfs_decode_fh(struct vfsmount *mnt, struct fid *fid,
* inode is actually connected to the parent.
*/
err = exportfs_get_name(mnt, target_dir, nbuf, result);
- if (!err) {
- inode_lock(target_dir->d_inode);
- nresult = lookup_one_len(nbuf, target_dir,
- strlen(nbuf));
- inode_unlock(target_dir->d_inode);
- if (!IS_ERR(nresult)) {
- if (nresult->d_inode) {
- dput(result);
- result = nresult;
- } else
- dput(nresult);
- }
+ if (err) {
+ dput(target_dir);
+ goto err_result;
}
+ inode_lock(target_dir->d_inode);
+ nresult = lookup_one_len(nbuf, target_dir, strlen(nbuf));
+ if (!IS_ERR(nresult)) {
+ if (unlikely(nresult->d_inode != result->d_inode)) {
+ dput(nresult);
+ nresult = ERR_PTR(-ESTALE);
+ }
+ }
+ inode_unlock(target_dir->d_inode);
/*
* At this point we are done with the parent, but it's pinned
* by the child dentry anyway.
*/
dput(target_dir);
+ if (IS_ERR(nresult)) {
+ err = PTR_ERR(nresult);
+ goto err_result;
+ }
+ dput(result);
+ result = nresult;
+
/*
* And finally make sure the dentry is actually acceptable
* to NFSD.
diff --git a/fs/ext2/inode.c b/fs/ext2/inode.c
index 85449a6..fe66494 100644
--- a/fs/ext2/inode.c
+++ b/fs/ext2/inode.c
@@ -697,10 +697,13 @@ static int ext2_get_blocks(struct inode *inode,
if (!partial) {
count++;
mutex_unlock(&ei->truncate_mutex);
- if (err)
- goto cleanup;
goto got_it;
}
+
+ if (err) {
+ mutex_unlock(&ei->truncate_mutex);
+ goto cleanup;
+ }
}
/*
diff --git a/fs/ext4/dir.c b/fs/ext4/dir.c
index 9aa4a18..3c89ced 100644
--- a/fs/ext4/dir.c
+++ b/fs/ext4/dir.c
@@ -75,6 +75,11 @@ int __ext4_check_dir_entry(const char *function, unsigned int line,
error_msg = "rec_len is too small for name_len";
else if (unlikely(((char *) de - buf) + rlen > size))
error_msg = "directory entry overrun";
+ else if (unlikely(((char *) de - buf) + rlen >
+ size - EXT4_DIR_REC_LEN(1) &&
+ ((char *) de - buf) + rlen != size)) {
+ error_msg = "directory entry too close to block end";
+ }
else if (unlikely(le32_to_cpu(de->inode) >
le32_to_cpu(EXT4_SB(dir->i_sb)->s_es->s_inodes_count)))
error_msg = "inode out of bounds";
diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c
index c7b5865..ff6ddc8 100644
--- a/fs/ext4/inode.c
+++ b/fs/ext4/inode.c
@@ -5146,11 +5146,15 @@ static void ext4_wait_for_tail_page_commit(struct inode *inode)
offset = inode->i_size & (PAGE_SIZE - 1);
/*
- * All buffers in the last page remain valid? Then there's nothing to
- * do. We do the check mainly to optimize the common PAGE_SIZE ==
- * blocksize case
+ * If the page is fully truncated, we don't need to wait for any commit
+ * (and we even should not as __ext4_journalled_invalidatepage() may
+ * strip all buffers from the page but keep the page dirty which can then
+ * confuse e.g. concurrent ext4_writepage() seeing dirty page without
+ * buffers). Also we don't need to wait for any commit if all buffers in
+ * the page remain valid. This is most beneficial for the common case of
+ * blocksize == PAGESIZE.
*/
- if (offset > PAGE_SIZE - i_blocksize(inode))
+ if (!offset || offset > (PAGE_SIZE - i_blocksize(inode)))
return;
while (1) {
page = find_lock_page(inode->i_mapping,
diff --git a/fs/ext4/namei.c b/fs/ext4/namei.c
index 50e12c9..9485f40 100644
--- a/fs/ext4/namei.c
+++ b/fs/ext4/namei.c
@@ -2681,7 +2681,7 @@ bool ext4_empty_dir(struct inode *inode)
{
unsigned int offset;
struct buffer_head *bh;
- struct ext4_dir_entry_2 *de, *de1;
+ struct ext4_dir_entry_2 *de;
struct super_block *sb;
if (ext4_has_inline_data(inode)) {
@@ -2706,19 +2706,25 @@ bool ext4_empty_dir(struct inode *inode)
return true;
de = (struct ext4_dir_entry_2 *) bh->b_data;
- de1 = ext4_next_entry(de, sb->s_blocksize);
- if (le32_to_cpu(de->inode) != inode->i_ino ||
- le32_to_cpu(de1->inode) == 0 ||
- strcmp(".", de->name) || strcmp("..", de1->name)) {
- ext4_warning_inode(inode, "directory missing '.' and/or '..'");
+ if (ext4_check_dir_entry(inode, NULL, de, bh, bh->b_data, bh->b_size,
+ 0) ||
+ le32_to_cpu(de->inode) != inode->i_ino || strcmp(".", de->name)) {
+ ext4_warning_inode(inode, "directory missing '.'");
brelse(bh);
return true;
}
- offset = ext4_rec_len_from_disk(de->rec_len, sb->s_blocksize) +
- ext4_rec_len_from_disk(de1->rec_len, sb->s_blocksize);
- de = ext4_next_entry(de1, sb->s_blocksize);
+ offset = ext4_rec_len_from_disk(de->rec_len, sb->s_blocksize);
+ de = ext4_next_entry(de, sb->s_blocksize);
+ if (ext4_check_dir_entry(inode, NULL, de, bh, bh->b_data, bh->b_size,
+ offset) ||
+ le32_to_cpu(de->inode) == 0 || strcmp("..", de->name)) {
+ ext4_warning_inode(inode, "directory missing '..'");
+ brelse(bh);
+ return true;
+ }
+ offset += ext4_rec_len_from_disk(de->rec_len, sb->s_blocksize);
while (offset < inode->i_size) {
- if ((void *) de >= (void *) (bh->b_data+sb->s_blocksize)) {
+ if (!(offset & (sb->s_blocksize - 1))) {
unsigned int lblock;
brelse(bh);
lblock = offset >> EXT4_BLOCK_SIZE_BITS(sb);
@@ -2729,12 +2735,11 @@ bool ext4_empty_dir(struct inode *inode)
}
if (IS_ERR(bh))
return true;
- de = (struct ext4_dir_entry_2 *) bh->b_data;
}
+ de = (struct ext4_dir_entry_2 *) (bh->b_data +
+ (offset & (sb->s_blocksize - 1)));
if (ext4_check_dir_entry(inode, NULL, de, bh,
bh->b_data, bh->b_size, offset)) {
- de = (struct ext4_dir_entry_2 *)(bh->b_data +
- sb->s_blocksize);
offset = (offset | (sb->s_blocksize - 1)) + 1;
continue;
}
@@ -2743,7 +2748,6 @@ bool ext4_empty_dir(struct inode *inode)
return false;
}
offset += ext4_rec_len_from_disk(de->rec_len, sb->s_blocksize);
- de = ext4_next_entry(de, sb->s_blocksize);
}
brelse(bh);
return true;
@@ -3038,18 +3042,17 @@ static int ext4_unlink(struct inode *dir, struct dentry *dentry)
if (IS_DIRSYNC(dir))
ext4_handle_sync(handle);
- if (inode->i_nlink == 0) {
- ext4_warning_inode(inode, "Deleting file '%.*s' with no links",
- dentry->d_name.len, dentry->d_name.name);
- set_nlink(inode, 1);
- }
retval = ext4_delete_entry(handle, dir, de, bh);
if (retval)
goto end_unlink;
dir->i_ctime = dir->i_mtime = ext4_current_time(dir);
ext4_update_dx_flag(dir);
ext4_mark_inode_dirty(handle, dir);
- drop_nlink(inode);
+ if (inode->i_nlink == 0)
+ ext4_warning_inode(inode, "Deleting file '%.*s' with no links",
+ dentry->d_name.len, dentry->d_name.name);
+ else
+ drop_nlink(inode);
if (!inode->i_nlink)
ext4_orphan_add(handle, inode);
inode->i_ctime = ext4_current_time(inode);
diff --git a/fs/fuse/dir.c b/fs/fuse/dir.c
index 108329e..a24f5a9 100644
--- a/fs/fuse/dir.c
+++ b/fs/fuse/dir.c
@@ -234,7 +234,8 @@ static int fuse_dentry_revalidate(struct dentry *entry, unsigned int flags)
kfree(forget);
if (ret == -ENOMEM)
goto out;
- if (ret || (outarg.attr.mode ^ inode->i_mode) & S_IFMT)
+ if (ret || fuse_invalid_attr(&outarg.attr) ||
+ (outarg.attr.mode ^ inode->i_mode) & S_IFMT)
goto invalid;
forget_all_cached_acls(inode);
@@ -343,6 +344,12 @@ int fuse_valid_type(int m)
S_ISBLK(m) || S_ISFIFO(m) || S_ISSOCK(m);
}
+bool fuse_invalid_attr(struct fuse_attr *attr)
+{
+ return !fuse_valid_type(attr->mode) ||
+ attr->size > LLONG_MAX;
+}
+
int fuse_lookup_name(struct super_block *sb, u64 nodeid, const struct qstr *name,
struct fuse_entry_out *outarg, struct inode **inode)
{
@@ -374,7 +381,7 @@ int fuse_lookup_name(struct super_block *sb, u64 nodeid, const struct qstr *name
err = -EIO;
if (!outarg->nodeid)
goto out_put_forget;
- if (!fuse_valid_type(outarg->attr.mode))
+ if (fuse_invalid_attr(&outarg->attr))
goto out_put_forget;
*inode = fuse_iget(sb, outarg->nodeid, outarg->generation,
@@ -498,7 +505,8 @@ static int fuse_create_open(struct inode *dir, struct dentry *entry,
goto out_free_ff;
err = -EIO;
- if (!S_ISREG(outentry.attr.mode) || invalid_nodeid(outentry.nodeid))
+ if (!S_ISREG(outentry.attr.mode) || invalid_nodeid(outentry.nodeid) ||
+ fuse_invalid_attr(&outentry.attr))
goto out_free_ff;
ff->fh = outopen.fh;
@@ -606,7 +614,7 @@ static int create_new_entry(struct fuse_conn *fc, struct fuse_args *args,
goto out_put_forget_req;
err = -EIO;
- if (invalid_nodeid(outarg.nodeid))
+ if (invalid_nodeid(outarg.nodeid) || fuse_invalid_attr(&outarg.attr))
goto out_put_forget_req;
if ((outarg.attr.mode ^ mode) & S_IFMT)
@@ -879,7 +887,8 @@ static int fuse_link(struct dentry *entry, struct inode *newdir,
spin_lock(&fc->lock);
fi->attr_version = ++fc->attr_version;
- inc_nlink(inode);
+ if (likely(inode->i_nlink < UINT_MAX))
+ inc_nlink(inode);
spin_unlock(&fc->lock);
fuse_invalidate_attr(inode);
fuse_update_ctime(inode);
@@ -959,7 +968,8 @@ static int fuse_do_getattr(struct inode *inode, struct kstat *stat,
args.out.args[0].value = &outarg;
err = fuse_simple_request(fc, &args);
if (!err) {
- if ((inode->i_mode ^ outarg.attr.mode) & S_IFMT) {
+ if (fuse_invalid_attr(&outarg.attr) ||
+ (inode->i_mode ^ outarg.attr.mode) & S_IFMT) {
make_bad_inode(inode);
err = -EIO;
} else {
@@ -1267,7 +1277,7 @@ static int fuse_direntplus_link(struct file *file,
if (invalid_nodeid(o->nodeid))
return -EIO;
- if (!fuse_valid_type(o->attr.mode))
+ if (fuse_invalid_attr(&o->attr))
return -EIO;
fc = get_fuse_conn(dir);
@@ -1744,7 +1754,8 @@ int fuse_do_setattr(struct dentry *dentry, struct iattr *attr,
goto error;
}
- if ((inode->i_mode ^ outarg.attr.mode) & S_IFMT) {
+ if (fuse_invalid_attr(&outarg.attr) ||
+ (inode->i_mode ^ outarg.attr.mode) & S_IFMT) {
make_bad_inode(inode);
err = -EIO;
goto error;
diff --git a/fs/fuse/fuse_i.h b/fs/fuse/fuse_i.h
index 2c1e88c..c8d9c66 100644
--- a/fs/fuse/fuse_i.h
+++ b/fs/fuse/fuse_i.h
@@ -912,6 +912,8 @@ void fuse_ctl_remove_conn(struct fuse_conn *fc);
*/
int fuse_valid_type(int m);
+bool fuse_invalid_attr(struct fuse_attr *attr);
+
/**
* Is current process allowed to perform filesystem operation?
*/
diff --git a/fs/jbd2/commit.c b/fs/jbd2/commit.c
index 10ec276..d002b2b 100644
--- a/fs/jbd2/commit.c
+++ b/fs/jbd2/commit.c
@@ -722,7 +722,6 @@ void jbd2_journal_commit_transaction(journal_t *journal)
submit_bh(REQ_OP_WRITE, WRITE_SYNC, bh);
}
cond_resched();
- stats.run.rs_blocks_logged += bufs;
/* Force a new descriptor to be generated next
time round the loop. */
@@ -809,6 +808,7 @@ void jbd2_journal_commit_transaction(journal_t *journal)
if (unlikely(!buffer_uptodate(bh)))
err = -EIO;
jbd2_unfile_log_bh(bh);
+ stats.run.rs_blocks_logged++;
/*
* The list contains temporary buffer heads created by
@@ -854,6 +854,7 @@ void jbd2_journal_commit_transaction(journal_t *journal)
BUFFER_TRACE(bh, "ph5: control buffer writeout done: unfile");
clear_buffer_jwrite(bh);
jbd2_unfile_log_bh(bh);
+ stats.run.rs_blocks_logged++;
__brelse(bh); /* One for getblk */
/* AKPM: bforget here */
}
@@ -875,6 +876,7 @@ void jbd2_journal_commit_transaction(journal_t *journal)
}
if (cbh)
err = journal_wait_on_commit_record(journal, cbh);
+ stats.run.rs_blocks_logged++;
if (jbd2_has_feature_async_commit(journal) &&
journal->j_flags & JBD2_BARRIER) {
blkdev_issue_flush(journal->j_dev, GFP_NOFS, NULL);
diff --git a/fs/nfsd/nfs4recover.c b/fs/nfsd/nfs4recover.c
index 66eaeb1..dc9586f 100644
--- a/fs/nfsd/nfs4recover.c
+++ b/fs/nfsd/nfs4recover.c
@@ -661,7 +661,7 @@ struct cld_net {
struct cld_upcall {
struct list_head cu_list;
struct cld_net *cu_net;
- struct task_struct *cu_task;
+ struct completion cu_done;
struct cld_msg cu_msg;
};
@@ -670,23 +670,18 @@ __cld_pipe_upcall(struct rpc_pipe *pipe, struct cld_msg *cmsg)
{
int ret;
struct rpc_pipe_msg msg;
+ struct cld_upcall *cup = container_of(cmsg, struct cld_upcall, cu_msg);
memset(&msg, 0, sizeof(msg));
msg.data = cmsg;
msg.len = sizeof(*cmsg);
- /*
- * Set task state before we queue the upcall. That prevents
- * wake_up_process in the downcall from racing with schedule.
- */
- set_current_state(TASK_UNINTERRUPTIBLE);
ret = rpc_queue_upcall(pipe, &msg);
if (ret < 0) {
- set_current_state(TASK_RUNNING);
goto out;
}
- schedule();
+ wait_for_completion(&cup->cu_done);
if (msg.errno < 0)
ret = msg.errno;
@@ -753,7 +748,7 @@ cld_pipe_downcall(struct file *filp, const char __user *src, size_t mlen)
if (copy_from_user(&cup->cu_msg, src, mlen) != 0)
return -EFAULT;
- wake_up_process(cup->cu_task);
+ complete(&cup->cu_done);
return mlen;
}
@@ -768,7 +763,7 @@ cld_pipe_destroy_msg(struct rpc_pipe_msg *msg)
if (msg->errno >= 0)
return;
- wake_up_process(cup->cu_task);
+ complete(&cup->cu_done);
}
static const struct rpc_pipe_ops cld_upcall_ops = {
@@ -899,7 +894,7 @@ alloc_cld_upcall(struct cld_net *cn)
goto restart_search;
}
}
- new->cu_task = current;
+ init_completion(&new->cu_done);
new->cu_msg.cm_vers = CLD_UPCALL_VERSION;
put_unaligned(cn->cn_xid++, &new->cu_msg.cm_xid);
new->cu_net = cn;
diff --git a/fs/nfsd/vfs.c b/fs/nfsd/vfs.c
index 8f0b19a..b8cd100 100644
--- a/fs/nfsd/vfs.c
+++ b/fs/nfsd/vfs.c
@@ -395,10 +395,23 @@ nfsd_setattr(struct svc_rqst *rqstp, struct svc_fh *fhp, struct iattr *iap,
bool get_write_count;
bool size_change = (iap->ia_valid & ATTR_SIZE);
- if (iap->ia_valid & (ATTR_ATIME | ATTR_MTIME | ATTR_SIZE))
+ if (iap->ia_valid & ATTR_SIZE) {
accmode |= NFSD_MAY_WRITE|NFSD_MAY_OWNER_OVERRIDE;
- if (iap->ia_valid & ATTR_SIZE)
ftype = S_IFREG;
+ }
+
+ /*
+ * If utimes(2) and friends are called with times not NULL, we should
+ * not set NFSD_MAY_WRITE bit. Otherwise fh_verify->nfsd_permission
+ * will return EACCESS, when the caller's effective UID does not match
+ * the owner of the file, and the caller is not privileged. In this
+ * situation, we should return EPERM(notify_change will return this).
+ */
+ if (iap->ia_valid & (ATTR_ATIME | ATTR_MTIME)) {
+ accmode |= NFSD_MAY_OWNER_OVERRIDE;
+ if (!(iap->ia_valid & (ATTR_ATIME_SET | ATTR_MTIME_SET)))
+ accmode |= NFSD_MAY_WRITE;
+ }
/* Callers that do fh_verify should do the fh_want_write: */
get_write_count = !fhp->fh_dentry;
diff --git a/fs/ocfs2/acl.c b/fs/ocfs2/acl.c
index ee8dbba..6dc714a 100644
--- a/fs/ocfs2/acl.c
+++ b/fs/ocfs2/acl.c
@@ -338,8 +338,8 @@ int ocfs2_acl_chmod(struct inode *inode, struct buffer_head *bh)
down_read(&OCFS2_I(inode)->ip_xattr_sem);
acl = ocfs2_get_acl_nolock(inode, ACL_TYPE_ACCESS, bh);
up_read(&OCFS2_I(inode)->ip_xattr_sem);
- if (IS_ERR(acl) || !acl)
- return PTR_ERR(acl);
+ if (IS_ERR_OR_NULL(acl))
+ return PTR_ERR_OR_ZERO(acl);
ret = __posix_acl_chmod(&acl, GFP_KERNEL, inode->i_mode);
if (ret)
return ret;
diff --git a/fs/ocfs2/quota_global.c b/fs/ocfs2/quota_global.c
index 87e577a..542fa21 100644
--- a/fs/ocfs2/quota_global.c
+++ b/fs/ocfs2/quota_global.c
@@ -714,7 +714,7 @@ static int ocfs2_release_dquot(struct dquot *dquot)
mutex_lock(&dquot->dq_lock);
/* Check whether we are not racing with some other dqget() */
- if (atomic_read(&dquot->dq_count) > 1)
+ if (dquot_is_busy(dquot))
goto out;
/* Running from downconvert thread? Postpone quota processing to wq */
if (current == osb->dc_task) {
diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c
index f9246ac..82a5ecb 100644
--- a/fs/quota/dquot.c
+++ b/fs/quota/dquot.c
@@ -479,7 +479,7 @@ int dquot_release(struct dquot *dquot)
mutex_lock(&dquot->dq_lock);
/* Check whether we are not racing with some other dqget() */
- if (atomic_read(&dquot->dq_count) > 1)
+ if (dquot_is_busy(dquot))
goto out_dqlock;
mutex_lock(&dqopt->dqio_mutex);
if (dqopt->ops[dquot->dq_id.type]->release_dqblk) {
@@ -611,7 +611,7 @@ EXPORT_SYMBOL(dquot_scan_active);
/* Write all dquot structures to quota files */
int dquot_writeback_dquots(struct super_block *sb, int type)
{
- struct list_head *dirty;
+ struct list_head dirty;
struct dquot *dquot;
struct quota_info *dqopt = sb_dqopt(sb);
int cnt;
@@ -624,9 +624,10 @@ int dquot_writeback_dquots(struct super_block *sb, int type)
if (!sb_has_quota_active(sb, cnt))
continue;
spin_lock(&dq_list_lock);
- dirty = &dqopt->info[cnt].dqi_dirty_list;
- while (!list_empty(dirty)) {
- dquot = list_first_entry(dirty, struct dquot,
+ /* Move list away to avoid livelock. */
+ list_replace_init(&dqopt->info[cnt].dqi_dirty_list, &dirty);
+ while (!list_empty(&dirty)) {
+ dquot = list_first_entry(&dirty, struct dquot,
dq_dirty);
/* Dirty and inactive can be only bad dquot... */
if (!test_bit(DQ_ACTIVE_B, &dquot->dq_flags)) {
@@ -2848,68 +2849,73 @@ EXPORT_SYMBOL(dquot_quotactl_sysfile_ops);
static int do_proc_dqstats(struct ctl_table *table, int write,
void __user *buffer, size_t *lenp, loff_t *ppos)
{
- unsigned int type = (int *)table->data - dqstats.stat;
+ unsigned int type = (unsigned long *)table->data - dqstats.stat;
+ s64 value = percpu_counter_sum(&dqstats.counter[type]);
+
+ /* Filter negative values for non-monotonic counters */
+ if (value < 0 && (type == DQST_ALLOC_DQUOTS ||
+ type == DQST_FREE_DQUOTS))
+ value = 0;
/* Update global table */
- dqstats.stat[type] =
- percpu_counter_sum_positive(&dqstats.counter[type]);
- return proc_dointvec(table, write, buffer, lenp, ppos);
+ dqstats.stat[type] = value;
+ return proc_doulongvec_minmax(table, write, buffer, lenp, ppos);
}
static struct ctl_table fs_dqstats_table[] = {
{
.procname = "lookups",
.data = &dqstats.stat[DQST_LOOKUPS],
- .maxlen = sizeof(int),
+ .maxlen = sizeof(unsigned long),
.mode = 0444,
.proc_handler = do_proc_dqstats,
},
{
.procname = "drops",
.data = &dqstats.stat[DQST_DROPS],
- .maxlen = sizeof(int),
+ .maxlen = sizeof(unsigned long),
.mode = 0444,
.proc_handler = do_proc_dqstats,
},
{
.procname = "reads",
.data = &dqstats.stat[DQST_READS],
- .maxlen = sizeof(int),
+ .maxlen = sizeof(unsigned long),
.mode = 0444,
.proc_handler = do_proc_dqstats,
},
{
.procname = "writes",
.data = &dqstats.stat[DQST_WRITES],
- .maxlen = sizeof(int),
+ .maxlen = sizeof(unsigned long),
.mode = 0444,
.proc_handler = do_proc_dqstats,
},
{
.procname = "cache_hits",
.data = &dqstats.stat[DQST_CACHE_HITS],
- .maxlen = sizeof(int),
+ .maxlen = sizeof(unsigned long),
.mode = 0444,
.proc_handler = do_proc_dqstats,
},
{
.procname = "allocated_dquots",
.data = &dqstats.stat[DQST_ALLOC_DQUOTS],
- .maxlen = sizeof(int),
+ .maxlen = sizeof(unsigned long),
.mode = 0444,
.proc_handler = do_proc_dqstats,
},
{
.procname = "free_dquots",
.data = &dqstats.stat[DQST_FREE_DQUOTS],
- .maxlen = sizeof(int),
+ .maxlen = sizeof(unsigned long),
.mode = 0444,
.proc_handler = do_proc_dqstats,
},
{
.procname = "syncs",
.data = &dqstats.stat[DQST_SYNCS],
- .maxlen = sizeof(int),
+ .maxlen = sizeof(unsigned long),
.mode = 0444,
.proc_handler = do_proc_dqstats,
},
diff --git a/fs/readdir.c b/fs/readdir.c
index 9d0212c..1059f2a 100644
--- a/fs/readdir.c
+++ b/fs/readdir.c
@@ -64,6 +64,40 @@ int iterate_dir(struct file *file, struct dir_context *ctx)
EXPORT_SYMBOL(iterate_dir);
/*
+ * POSIX says that a dirent name cannot contain NULL or a '/'.
+ *
+ * It's not 100% clear what we should really do in this case.
+ * The filesystem is clearly corrupted, but returning a hard
+ * error means that you now don't see any of the other names
+ * either, so that isn't a perfect alternative.
+ *
+ * And if you return an error, what error do you use? Several
+ * filesystems seem to have decided on EUCLEAN being the error
+ * code for EFSCORRUPTED, and that may be the error to use. Or
+ * just EIO, which is perhaps more obvious to users.
+ *
+ * In order to see the other file names in the directory, the
+ * caller might want to make this a "soft" error: skip the
+ * entry, and return the error at the end instead.
+ *
+ * Note that this should likely do a "memchr(name, 0, len)"
+ * check too, since that would be filesystem corruption as
+ * well. However, that case can't actually confuse user space,
+ * which has to do a strlen() on the name anyway to find the
+ * filename length, and the above "soft error" worry means
+ * that it's probably better left alone until we have that
+ * issue clarified.
+ */
+static int verify_dirent_name(const char *name, int len)
+{
+ if (!len)
+ return -EIO;
+ if (memchr(name, '/', len))
+ return -EIO;
+ return 0;
+}
+
+/*
* Traditional linux readdir() handling..
*
* "count=1" is a special case, meaning that the buffer is one
@@ -172,6 +206,9 @@ static int filldir(struct dir_context *ctx, const char *name, int namlen,
int reclen = ALIGN(offsetof(struct linux_dirent, d_name) + namlen + 2,
sizeof(long));
+ buf->error = verify_dirent_name(name, namlen);
+ if (unlikely(buf->error))
+ return buf->error;
buf->error = -EINVAL; /* only used if we fail.. */
if (reclen > buf->count)
return -EINVAL;
@@ -258,6 +295,9 @@ static int filldir64(struct dir_context *ctx, const char *name, int namlen,
int reclen = ALIGN(offsetof(struct linux_dirent64, d_name) + namlen + 1,
sizeof(u64));
+ buf->error = verify_dirent_name(name, namlen);
+ if (unlikely(buf->error))
+ return buf->error;
buf->error = -EINVAL; /* only used if we fail.. */
if (reclen > buf->count)
return -EINVAL;
diff --git a/fs/reiserfs/inode.c b/fs/reiserfs/inode.c
index bd4c727..9531b6c 100644
--- a/fs/reiserfs/inode.c
+++ b/fs/reiserfs/inode.c
@@ -2102,6 +2102,15 @@ int reiserfs_new_inode(struct reiserfs_transaction_handle *th,
goto out_inserted_sd;
}
+ /*
+ * Mark it private if we're creating the privroot
+ * or something under it.
+ */
+ if (IS_PRIVATE(dir) || dentry == REISERFS_SB(sb)->priv_root) {
+ inode->i_flags |= S_PRIVATE;
+ inode->i_opflags &= ~IOP_XATTR;
+ }
+
if (reiserfs_posixacl(inode->i_sb)) {
reiserfs_write_unlock(inode->i_sb);
retval = reiserfs_inherit_default_acl(th, dir, dentry, inode);
@@ -2116,8 +2125,7 @@ int reiserfs_new_inode(struct reiserfs_transaction_handle *th,
reiserfs_warning(inode->i_sb, "jdm-13090",
"ACLs aren't enabled in the fs, "
"but vfs thinks they are!");
- } else if (IS_PRIVATE(dir))
- inode->i_flags |= S_PRIVATE;
+ }
if (security->name) {
reiserfs_write_unlock(inode->i_sb);
diff --git a/fs/reiserfs/namei.c b/fs/reiserfs/namei.c
index 1ec728c..1c900f3 100644
--- a/fs/reiserfs/namei.c
+++ b/fs/reiserfs/namei.c
@@ -377,10 +377,13 @@ static struct dentry *reiserfs_lookup(struct inode *dir, struct dentry *dentry,
/*
* Propagate the private flag so we know we're
- * in the priv tree
+ * in the priv tree. Also clear IOP_XATTR
+ * since we don't have xattrs on xattr files.
*/
- if (IS_PRIVATE(dir))
+ if (IS_PRIVATE(dir)) {
inode->i_flags |= S_PRIVATE;
+ inode->i_opflags &= ~IOP_XATTR;
+ }
}
reiserfs_write_unlock(dir->i_sb);
if (retval == IO_ERROR) {
diff --git a/fs/reiserfs/reiserfs.h b/fs/reiserfs/reiserfs.h
index d920a64..3e78a39 100644
--- a/fs/reiserfs/reiserfs.h
+++ b/fs/reiserfs/reiserfs.h
@@ -1167,6 +1167,8 @@ static inline int bmap_would_wrap(unsigned bmap_nr)
return bmap_nr > ((1LL << 16) - 1);
}
+extern const struct xattr_handler *reiserfs_xattr_handlers[];
+
/*
* this says about version of key of all items (but stat data) the
* object consists of
diff --git a/fs/reiserfs/super.c b/fs/reiserfs/super.c
index dec6c93..cd2d555 100644
--- a/fs/reiserfs/super.c
+++ b/fs/reiserfs/super.c
@@ -2026,6 +2026,8 @@ static int reiserfs_fill_super(struct super_block *s, void *data, int silent)
if (replay_only(s))
goto error_unlocked;
+ s->s_xattr = reiserfs_xattr_handlers;
+
if (bdev_read_only(s->s_bdev) && !(s->s_flags & MS_RDONLY)) {
SWARN(silent, s, "clm-7000",
"Detected readonly device, marking FS readonly");
diff --git a/fs/reiserfs/xattr.c b/fs/reiserfs/xattr.c
index 9e313fc..dbc2ada 100644
--- a/fs/reiserfs/xattr.c
+++ b/fs/reiserfs/xattr.c
@@ -121,13 +121,13 @@ static struct dentry *open_xa_root(struct super_block *sb, int flags)
struct dentry *xaroot;
if (d_really_is_negative(privroot))
- return ERR_PTR(-ENODATA);
+ return ERR_PTR(-EOPNOTSUPP);
inode_lock_nested(d_inode(privroot), I_MUTEX_XATTR);
xaroot = dget(REISERFS_SB(sb)->xattr_root);
if (!xaroot)
- xaroot = ERR_PTR(-ENODATA);
+ xaroot = ERR_PTR(-EOPNOTSUPP);
else if (d_really_is_negative(xaroot)) {
int err = -ENODATA;
@@ -609,6 +609,10 @@ int reiserfs_xattr_set(struct inode *inode, const char *name,
int error, error2;
size_t jbegin_count = reiserfs_xattr_nblocks(inode, buffer_size);
+ /* Check before we start a transaction and then do nothing. */
+ if (!d_really_is_positive(REISERFS_SB(inode->i_sb)->priv_root))
+ return -EOPNOTSUPP;
+
if (!(flags & XATTR_REPLACE))
jbegin_count += reiserfs_xattr_jcreate_nblocks(inode);
@@ -831,8 +835,7 @@ ssize_t reiserfs_listxattr(struct dentry * dentry, char *buffer, size_t size)
if (d_really_is_negative(dentry))
return -EINVAL;
- if (!dentry->d_sb->s_xattr ||
- get_inode_sd_version(d_inode(dentry)) == STAT_DATA_V1)
+ if (get_inode_sd_version(d_inode(dentry)) == STAT_DATA_V1)
return -EOPNOTSUPP;
dir = open_xa_dir(d_inode(dentry), XATTR_REPLACE);
@@ -872,6 +875,7 @@ static int create_privroot(struct dentry *dentry)
}
d_inode(dentry)->i_flags |= S_PRIVATE;
+ d_inode(dentry)->i_opflags &= ~IOP_XATTR;
reiserfs_info(dentry->d_sb, "Created %s - reserved for xattr "
"storage.\n", PRIVROOT_NAME);
@@ -885,7 +889,7 @@ static int create_privroot(struct dentry *dentry) { return 0; }
#endif
/* Actual operations that are exported to VFS-land */
-static const struct xattr_handler *reiserfs_xattr_handlers[] = {
+const struct xattr_handler *reiserfs_xattr_handlers[] = {
#ifdef CONFIG_REISERFS_FS_XATTR
&reiserfs_xattr_user_handler,
&reiserfs_xattr_trusted_handler,
@@ -956,8 +960,10 @@ int reiserfs_lookup_privroot(struct super_block *s)
if (!IS_ERR(dentry)) {
REISERFS_SB(s)->priv_root = dentry;
d_set_d_op(dentry, &xattr_lookup_poison_ops);
- if (d_really_is_positive(dentry))
+ if (d_really_is_positive(dentry)) {
d_inode(dentry)->i_flags |= S_PRIVATE;
+ d_inode(dentry)->i_opflags &= ~IOP_XATTR;
+ }
} else
err = PTR_ERR(dentry);
inode_unlock(d_inode(s->s_root));
@@ -986,7 +992,6 @@ int reiserfs_xattr_init(struct super_block *s, int mount_flags)
}
if (d_really_is_positive(privroot)) {
- s->s_xattr = reiserfs_xattr_handlers;
inode_lock(d_inode(privroot));
if (!REISERFS_SB(s)->xattr_root) {
struct dentry *dentry;
diff --git a/fs/reiserfs/xattr_acl.c b/fs/reiserfs/xattr_acl.c
index d92a1dc..1f1fdfd 100644
--- a/fs/reiserfs/xattr_acl.c
+++ b/fs/reiserfs/xattr_acl.c
@@ -316,10 +316,8 @@ reiserfs_inherit_default_acl(struct reiserfs_transaction_handle *th,
* would be useless since permissions are ignored, and a pain because
* it introduces locking cycles
*/
- if (IS_PRIVATE(dir)) {
- inode->i_flags |= S_PRIVATE;
+ if (IS_PRIVATE(inode))
goto apply_umask;
- }
err = posix_acl_create(dir, &inode->i_mode, &default_acl, &acl);
if (err)
diff --git a/inc/dbgprint.h b/inc/dbgprint.h
deleted file mode 100644
index 4555452..0000000
--- a/inc/dbgprint.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _DBGPRINT_H
-# define _DBGPRINT_H
-
-/* Debugging macro's. */
-# ifndef DEBUG
-# define DEBUG
-# endif
-
-# ifndef ASSERT
-//#define ASSERT
-# endif
- //TODO wwwim
-# ifndef _ASSERT
- #define _ASSERT(e)
-# endif
-
-# ifndef PREFIX
-# define PREFIX "tfa98xx: "
-# define DRIVER_NAME "tfa98xx"
-# endif
-
-#ifdef __KERNEL__
-
-# ifdef DEBUG
-# define _DEBUG(level,fmt,va...) do {\
- if (unlikely(debug >= (level))) \
- printk(KERN_INFO PREFIX "%s:%d: "fmt,__func__,__LINE__,##va); \
- } while (0)
-
-# else
-# define _DEBUG(level,fmt,va...) do {} while(0)
-# endif
-
-# define MSG(fmt,va...) printk(KERN_INFO PREFIX "%s:%d: "fmt,__func__,__LINE__,##va)
-# define _ERRORMSG(fmt,va...) printk(KERN_ERR PREFIX "ERROR %s:%d: "fmt,__func__,__LINE__, ##va)
-
-
-# define DEBUG0(x...) MSG(x)
-# define DEBUG1(x...) _DEBUG(1,x)
-# define DEBUG2(x...) _DEBUG(2,x)
-# define DEBUG3(x...) _DEBUG(3,x)
-# define ERRORMSG(x...) _ERRORMSG(x)
-# define PRINT(x...) printk(x)
-# define PRINT_ERROR(x...) printk(KERN_INFO PREFIX " **ERROR** " x)
-# define PRINT_ASSERT(e)if ((e)) printk(KERN_ERR "PrintAssert:%s (%s:%d) error code:%d\n",__FUNCTION__,__FILE__,__LINE__, e)
-
-# define PRINT_ENTRY DEBUG2("+[%s]\n", __func__)
-# define PRINT_EXIT DEBUG2("-[%s]\n", __func__)
-
-# ifdef ASSERT
-# define assert(cond,action) do { if (unlikely(!(cond))) { DEBUG0("Assert: %s\n",#cond); action; }} while(0)
-# else
-# define assert(cond,action) do { } while (0)
-# endif
-
-#else /* __KERNEL__ */
-#if defined(WIN32) || defined(_X64)
-#include <stdio.h>
-/* user mode */
-# ifdef DEBUG
-# define _DEBUGMSG(level,fmt,...) printf(PREFIX "%s:%d: "fmt,__FUNCTION__,__LINE__,__VA_ARGS__);
-# else
-# define _DEBUGMSG(level,fmt,...) do {} while(0)
-# endif
-
-# define _ERRORMSG(fmt,...) printf(PREFIX "%s:%s:%d: "fmt,__FILE__,__FUNCTION__,__LINE__,__VA_ARGS__)
-
-# define DEBUG0(...) MSG(__VA_ARGS__)
-# define DEBUG1(...) _DEBUGMSG(1,__VA_ARGS__)
-# define DEBUG2(...) _DEBUGMSG(2,__VA_ARGS__)
-# define DEBUG3(...) _DEBUGMSG(3,__VA_ARGS__)
-# define ERRORMSG(fmt,...) _ERRORMSG(fmt,__VA_ARGS__)
-# define PRINT(...) printf(__VA_ARGS__)
-/*
-# define PRINT(...) { FILE *stream; \
- if((stream = freopen("nxp_tfa.txt", "ab+", stdout)) == NULL) exit(-1); \
- printf(__VA_ARGS__); \
- freopen( "CON", "ab+", stdout ); \
- }
-*/
-# define PRINT_ERROR(...) fprintf(stderr,__VA_ARGS__)
-# define PRINT_FILE(file,...) fprintf(file,__VA_ARGS__)
-# define PRINT_ASSERT(e)if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) error code:%d\n",__FUNCTION__,__FILE__,__LINE__, e)
-//# define PRINT_ASSERT(e) if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) %s\n",__FUNCTION__,__FILE__,__LINE__, Tfa98xx_GetErrorString(e))
-
-#elif defined(__CODE_RED)
-#include "app_global.h"
-# ifdef DEBUG
-# define _DEBUG(level,fmt,va...) TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,va))
-//printf(PREFIX "%s:%d: "fmt,__func__,__LINE__,##va);
-# else
-# define _DEBUG(level,fmt,va...) do {} while(0)
-# endif
-
-# define MSG(fmt,...) TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,__VA_ARGS__))
-//printf(PREFIX "%s:%s:%d: "fmt,__FILE__,__func__,__LINE__,##va)
-//TB_TRACE_INF(TbTracePfx2(APP_PFX,TB_FUNC,"path=%s, chan=%u, muted=%s, vol=%d\n",
-// path->isRecording ? "recording" : "playback",
-// i,
-// channelVol.currentMuteValue ? "YES" : "NO",
-// channelVol.currentVolumeValue
-// ));
-//# define _ERRORMSG(fmt,va...) TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,va))
-# define ERRORMSG(...) TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,__VA_ARGS__))
-//fprintf(stderr, PREFIX "ERROR %s:%s:%d: "fmt,__FILE__,__func__,__LINE__, ##va)
-
-# define DEBUG0(x...) MSG(x)
-# define DEBUG1(x...) _DEBUG(1,x)
-# define DEBUG2(x...) _DEBUG(2,x)
-# define DEBUG3(x...) _DEBUG(3,x)
-//# define ERRORMSG(x...) _ERRORMSG(x)
-# define PRINT(x...) TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,x))
-//printf(x)
-# define PRINT_ERROR(x...) TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,x))
-//fprintf(stderr,__VA_ARGS__)
-# define PRINT_FILE(file,x...) TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,x))
-//fprintf(file,__VA_ARGS__)
-# define PRINT_ASSERT(e)
-//TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,Tfa98xx_GetErrorString(e)))
-//if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) %s\n",__FUNCTION__,__FILE__,__LINE__, Tfa98xx_GetErrorString(e))
-#else
-#include <stdio.h>
-/* user mode */
-# ifdef DEBUG
-# define _DEBUG(level,fmt,va...) printf(PREFIX "%s:%d: "fmt,__func__,__LINE__,##va);
-# else
-# define _DEBUG(level,fmt,va...) do {} while(0)
-# endif
-
-# define MSG(fmt,va...) printf(PREFIX "%s:%s:%d: "fmt,__FILE__,__func__,__LINE__,##va)
-# define _ERRORMSG(fmt,va...) fprintf(stderr, PREFIX "ERROR %s:%s:%d: "fmt,__FILE__,__func__,__LINE__, ##va)
-
-# define DEBUG0(x...) MSG(x)
-# define DEBUG1(x...) _DEBUG(1,x)
-# define DEBUG2(x...) _DEBUG(2,x)
-# define DEBUG3(x...) _DEBUG(3,x)
-# define ERRORMSG(x...) _ERRORMSG(x)
-# define PRINT(x...) printf(x)
-# define PRINT_ERROR(...) fprintf(stderr,__VA_ARGS__)
-# define PRINT_FILE(file,...) fprintf(file,__VA_ARGS__)
-# define PRINT_ASSERT(e)if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) error code:%d\n",__FUNCTION__,__FILE__,__LINE__, e)
-//# define PRINT_ASSERT(e) if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) %s\n",__FUNCTION__,__FILE__,__LINE__, Tfa98xx_GetErrorString(e))
-
-
-#endif /* WIN32 */
-
-#endif /* user */
-
-#endif /* _DBGPRINT_H --------------- */
diff --git a/inc/tfa.h b/inc/tfa.h
deleted file mode 100644
index 7711769..0000000
--- a/inc/tfa.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef TFA_H_
-#define TFA_H_
-
-/* set the limit for the container file length */
-#define TFA_MAX_CNT_LENGTH (256*1024)
-
-extern struct tfa_device **devs;
-
-/**
- * tfa error return codes
- */
-enum tfa_error {
- tfa_error_ok, /**< no error */
- tfa_error_device, /**< no response from device */
- tfa_error_bad_param,/**< parameter no accepted */
- tfa_error_noclock, /**< required clock not present */
- tfa_error_timeout, /**< a timeout occurred */
- tfa_error_dsp, /**< a DSP error was returned */
- tfa_error_container,/**< no or wrong container file */
- tfa_error_max /**< impossible value, max enum */
-};
-
-enum Tfa98xx_Error tfa_write_filters(struct tfa_device *tfa, int prof_idx);
-
-struct tfa_device ** tfa_devs_create(int count);
-void tfa_devs_destroy(int count);
-
-struct tfa_device ** tfa_get_device_struct(void);
-
-int tfa_plop_noise_interrupt(struct tfa_device *tfa, int profile, int vstep);
-void tfa_lp_mode_interrupt(struct tfa_device *tfa);
-
-#endif /* TFA_H_ */
diff --git a/inc/tfa1_tfafieldnames.h b/inc/tfa1_tfafieldnames.h
deleted file mode 100644
index 138b212..0000000
--- a/inc/tfa1_tfafieldnames.h
+++ /dev/null
@@ -1,904 +0,0 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#define TFA9897_I2CVERSION 34
-typedef enum nxpTfa1BfEnumList {
- TFA1_BF_VDDS = 0x0000, /*!< Power-on-reset flag */
- TFA1_BF_PLLS = 0x0010, /*!< PLL lock */
- TFA1_BF_OTDS = 0x0020, /*!< Over Temperature Protection alarm */
- TFA1_BF_OVDS = 0x0030, /*!< Over Voltage Protection alarm */
- TFA1_BF_UVDS = 0x0040, /*!< Under Voltage Protection alarm */
- TFA1_BF_OCDS = 0x0050, /*!< Over Current Protection alarm */
- TFA1_BF_CLKS = 0x0060, /*!< Clocks stable flag */
- TFA1_BF_CLIPS = 0x0070, /*!< Amplifier clipping */
- TFA1_BF_MTPB = 0x0080, /*!< MTP busy */
- TFA1_BF_NOCLK = 0x0090, /*!< Flag lost clock from clock generation unit */
- TFA1_BF_SPKS = 0x00a0, /*!< Speaker error flag */
- TFA1_BF_ACS = 0x00b0, /*!< Cold Start flag */
- TFA1_BF_SWS = 0x00c0, /*!< Flag Engage */
- TFA1_BF_WDS = 0x00d0, /*!< Flag watchdog reset */
- TFA1_BF_AMPS = 0x00e0, /*!< Amplifier is enabled by manager */
- TFA1_BF_AREFS = 0x00f0, /*!< References are enabled by manager */
- TFA1_BF_BATS = 0x0109, /*!< Battery voltage readout; 0 .. 5.5 [V] */
- TFA1_BF_TEMPS = 0x0208, /*!< Temperature readout from the temperature sensor */
- TFA1_BF_REV = 0x030b, /*!< Device type number is B97 */
- TFA1_BF_RCV = 0x0420, /*!< Enable Receiver Mode */
- TFA1_BF_CHS12 = 0x0431, /*!< Channel Selection TDM input for Coolflux */
- TFA1_BF_INPLVL= 0x0450, /*!< Input level selection control */
- TFA1_BF_CHSA = 0x0461, /*!< Input selection for amplifier */
- TFA1_BF_I2SDOE= 0x04b0, /*!< Enable data output */
- TFA1_BF_AUDFS = 0x04c3, /*!< Audio sample rate setting */
- TFA1_BF_BSSCR = 0x0501, /*!< Protection Attack Time */
- TFA1_BF_BSST = 0x0523, /*!< ProtectionThreshold */
- TFA1_BF_BSSRL = 0x0561, /*!< Protection Maximum Reduction */
- TFA1_BF_BSSRR = 0x0582, /*!< Battery Protection Release Time */
- TFA1_BF_BSSHY = 0x05b1, /*!< Battery Protection Hysteresis */
- TFA1_BF_BSSR = 0x05e0, /*!< battery voltage for I2C read out only */
- TFA1_BF_BSSBY = 0x05f0, /*!< bypass clipper battery protection */
- TFA1_BF_DPSA = 0x0600, /*!< Enable dynamic powerstage activation */
- TFA1_BF_CFSM = 0x0650, /*!< Soft mute in CoolFlux */
- TFA1_BF_BSSS = 0x0670, /*!< BatSenseSteepness */
- TFA1_BF_VOL = 0x0687, /*!< volume control (in CoolFlux) */
- TFA1_BF_DCVO = 0x0702, /*!< Boost Voltage */
- TFA1_BF_DCMCC = 0x0733, /*!< Max boost coil current - step of 175 mA */
- TFA1_BF_DCIE = 0x07a0, /*!< Adaptive boost mode */
- TFA1_BF_DCSR = 0x07b0, /*!< Soft RampUp/Down mode for DCDC controller */
- TFA1_BF_DCPAVG= 0x07c0, /*!< ctrl_peak2avg for analog part of DCDC */
- TFA1_BF_TROS = 0x0800, /*!< Select external temperature also the ext_temp will be put on the temp read out */
- TFA1_BF_EXTTS = 0x0818, /*!< external temperature setting to be given by host */
- TFA1_BF_PWDN = 0x0900, /*!< Device Mode */
- TFA1_BF_I2CR = 0x0910, /*!< I2C Reset */
- TFA1_BF_CFE = 0x0920, /*!< Enable CoolFlux */
- TFA1_BF_AMPE = 0x0930, /*!< Enable Amplifier */
- TFA1_BF_DCA = 0x0940, /*!< EnableBoost */
- TFA1_BF_SBSL = 0x0950, /*!< Coolflux configured */
- TFA1_BF_AMPC = 0x0960, /*!< Selection on how Amplifier is enabled */
- TFA1_BF_DCDIS = 0x0970, /*!< DCDC not connected */
- TFA1_BF_PSDR = 0x0980, /*!< IDDQ test amplifier */
- TFA1_BF_DCCV = 0x0991, /*!< Coil Value */
- TFA1_BF_CCFD = 0x09b0, /*!< Selection CoolFlux Clock */
- TFA1_BF_INTPAD= 0x09c1, /*!< INT pad configuration control */
- TFA1_BF_IPLL = 0x09e0, /*!< PLL input reference clock selection */
- TFA1_BF_MTPK = 0x0b07, /*!< 5Ah, 90d To access KEY1_Protected registers (Default for engineering) */
- TFA1_BF_CVFDLY= 0x0c25, /*!< Fractional delay adjustment between current and voltage sense */
- TFA1_BF_TDMPRF= 0x1011, /*!< TDM_usecase */
- TFA1_BF_TDMEN = 0x1030, /*!< TDM interface control */
- TFA1_BF_TDMCKINV= 0x1040, /*!< TDM clock inversion */
- TFA1_BF_TDMFSLN= 0x1053, /*!< TDM FS length */
- TFA1_BF_TDMFSPOL= 0x1090, /*!< TDM FS polarity */
- TFA1_BF_TDMSAMSZ= 0x10a4, /*!< TDM Sample Size for all tdm sinks/sources */
- TFA1_BF_TDMSLOTS= 0x1103, /*!< Number of slots */
- TFA1_BF_TDMSLLN= 0x1144, /*!< Slot length */
- TFA1_BF_TDMBRMG= 0x1194, /*!< Bits remaining */
- TFA1_BF_TDMDDEL= 0x11e0, /*!< Data delay */
- TFA1_BF_TDMDADJ= 0x11f0, /*!< Data adjustment */
- TFA1_BF_TDMTXFRM= 0x1201, /*!< TXDATA format */
- TFA1_BF_TDMUUS0= 0x1221, /*!< TXDATA format unused slot sd0 */
- TFA1_BF_TDMUUS1= 0x1241, /*!< TXDATA format unused slot sd1 */
- TFA1_BF_TDMSI0EN= 0x1270, /*!< TDM sink0 enable */
- TFA1_BF_TDMSI1EN= 0x1280, /*!< TDM sink1 enable */
- TFA1_BF_TDMSI2EN= 0x1290, /*!< TDM sink2 enable */
- TFA1_BF_TDMSO0EN= 0x12a0, /*!< TDM source0 enable */
- TFA1_BF_TDMSO1EN= 0x12b0, /*!< TDM source1 enable */
- TFA1_BF_TDMSO2EN= 0x12c0, /*!< TDM source2 enable */
- TFA1_BF_TDMSI0IO= 0x12d0, /*!< tdm_sink0_io */
- TFA1_BF_TDMSI1IO= 0x12e0, /*!< tdm_sink1_io */
- TFA1_BF_TDMSI2IO= 0x12f0, /*!< tdm_sink2_io */
- TFA1_BF_TDMSO0IO= 0x1300, /*!< tdm_source0_io */
- TFA1_BF_TDMSO1IO= 0x1310, /*!< tdm_source1_io */
- TFA1_BF_TDMSO2IO= 0x1320, /*!< tdm_source2_io */
- TFA1_BF_TDMSI0SL= 0x1333, /*!< sink0_slot [GAIN IN] */
- TFA1_BF_TDMSI1SL= 0x1373, /*!< sink1_slot [CH1 IN] */
- TFA1_BF_TDMSI2SL= 0x13b3, /*!< sink2_slot [CH2 IN] */
- TFA1_BF_TDMSO0SL= 0x1403, /*!< source0_slot [GAIN OUT] */
- TFA1_BF_TDMSO1SL= 0x1443, /*!< source1_slot [Voltage Sense] */
- TFA1_BF_TDMSO2SL= 0x1483, /*!< source2_slot [Current Sense] */
- TFA1_BF_NBCK = 0x14c3, /*!< NBCK */
- TFA1_BF_INTOVDDS= 0x2000, /*!< flag_por_int_out */
- TFA1_BF_INTOPLLS= 0x2010, /*!< flag_pll_lock_int_out */
- TFA1_BF_INTOOTDS= 0x2020, /*!< flag_otpok_int_out */
- TFA1_BF_INTOOVDS= 0x2030, /*!< flag_ovpok_int_out */
- TFA1_BF_INTOUVDS= 0x2040, /*!< flag_uvpok_int_out */
- TFA1_BF_INTOOCDS= 0x2050, /*!< flag_ocp_alarm_int_out */
- TFA1_BF_INTOCLKS= 0x2060, /*!< flag_clocks_stable_int_out */
- TFA1_BF_INTOCLIPS= 0x2070, /*!< flag_clip_int_out */
- TFA1_BF_INTOMTPB= 0x2080, /*!< mtp_busy_int_out */
- TFA1_BF_INTONOCLK= 0x2090, /*!< flag_lost_clk_int_out */
- TFA1_BF_INTOSPKS= 0x20a0, /*!< flag_cf_speakererror_int_out */
- TFA1_BF_INTOACS= 0x20b0, /*!< flag_cold_started_int_out */
- TFA1_BF_INTOSWS= 0x20c0, /*!< flag_engage_int_out */
- TFA1_BF_INTOWDS= 0x20d0, /*!< flag_watchdog_reset_int_out */
- TFA1_BF_INTOAMPS= 0x20e0, /*!< flag_enbl_amp_int_out */
- TFA1_BF_INTOAREFS= 0x20f0, /*!< flag_enbl_ref_int_out */
- TFA1_BF_INTOACK= 0x2201, /*!< Interrupt status register output - Corresponding flag */
- TFA1_BF_INTIVDDS= 0x2300, /*!< flag_por_int_in */
- TFA1_BF_INTIPLLS= 0x2310, /*!< flag_pll_lock_int_in */
- TFA1_BF_INTIOTDS= 0x2320, /*!< flag_otpok_int_in */
- TFA1_BF_INTIOVDS= 0x2330, /*!< flag_ovpok_int_in */
- TFA1_BF_INTIUVDS= 0x2340, /*!< flag_uvpok_int_in */
- TFA1_BF_INTIOCDS= 0x2350, /*!< flag_ocp_alarm_int_in */
- TFA1_BF_INTICLKS= 0x2360, /*!< flag_clocks_stable_int_in */
- TFA1_BF_INTICLIPS= 0x2370, /*!< flag_clip_int_in */
- TFA1_BF_INTIMTPB= 0x2380, /*!< mtp_busy_int_in */
- TFA1_BF_INTINOCLK= 0x2390, /*!< flag_lost_clk_int_in */
- TFA1_BF_INTISPKS= 0x23a0, /*!< flag_cf_speakererror_int_in */
- TFA1_BF_INTIACS= 0x23b0, /*!< flag_cold_started_int_in */
- TFA1_BF_INTISWS= 0x23c0, /*!< flag_engage_int_in */
- TFA1_BF_INTIWDS= 0x23d0, /*!< flag_watchdog_reset_int_in */
- TFA1_BF_INTIAMPS= 0x23e0, /*!< flag_enbl_amp_int_in */
- TFA1_BF_INTIAREFS= 0x23f0, /*!< flag_enbl_ref_int_in */
- TFA1_BF_INTIACK= 0x2501, /*!< Interrupt register input */
- TFA1_BF_INTENVDDS= 0x2600, /*!< flag_por_int_enable */
- TFA1_BF_INTENPLLS= 0x2610, /*!< flag_pll_lock_int_enable */
- TFA1_BF_INTENOTDS= 0x2620, /*!< flag_otpok_int_enable */
- TFA1_BF_INTENOVDS= 0x2630, /*!< flag_ovpok_int_enable */
- TFA1_BF_INTENUVDS= 0x2640, /*!< flag_uvpok_int_enable */
- TFA1_BF_INTENOCDS= 0x2650, /*!< flag_ocp_alarm_int_enable */
- TFA1_BF_INTENCLKS= 0x2660, /*!< flag_clocks_stable_int_enable */
- TFA1_BF_INTENCLIPS= 0x2670, /*!< flag_clip_int_enable */
- TFA1_BF_INTENMTPB= 0x2680, /*!< mtp_busy_int_enable */
- TFA1_BF_INTENNOCLK= 0x2690, /*!< flag_lost_clk_int_enable */
- TFA1_BF_INTENSPKS= 0x26a0, /*!< flag_cf_speakererror_int_enable */
- TFA1_BF_INTENACS= 0x26b0, /*!< flag_cold_started_int_enable */
- TFA1_BF_INTENSWS= 0x26c0, /*!< flag_engage_int_enable */
- TFA1_BF_INTENWDS= 0x26d0, /*!< flag_watchdog_reset_int_enable */
- TFA1_BF_INTENAMPS= 0x26e0, /*!< flag_enbl_amp_int_enable */
- TFA1_BF_INTENAREFS= 0x26f0, /*!< flag_enbl_ref_int_enable */
- TFA1_BF_INTENACK= 0x2801, /*!< Interrupt enable register */
- TFA1_BF_INTPOLVDDS= 0x2900, /*!< flag_por_int_pol */
- TFA1_BF_INTPOLPLLS= 0x2910, /*!< flag_pll_lock_int_pol */
- TFA1_BF_INTPOLOTDS= 0x2920, /*!< flag_otpok_int_pol */
- TFA1_BF_INTPOLOVDS= 0x2930, /*!< flag_ovpok_int_pol */
- TFA1_BF_INTPOLUVDS= 0x2940, /*!< flag_uvpok_int_pol */
- TFA1_BF_INTPOLOCDS= 0x2950, /*!< flag_ocp_alarm_int_pol */
- TFA1_BF_INTPOLCLKS= 0x2960, /*!< flag_clocks_stable_int_pol */
- TFA1_BF_INTPOLCLIPS= 0x2970, /*!< flag_clip_int_pol */
- TFA1_BF_INTPOLMTPB= 0x2980, /*!< mtp_busy_int_pol */
- TFA1_BF_INTPOLNOCLK= 0x2990, /*!< flag_lost_clk_int_pol */
- TFA1_BF_INTPOLSPKS= 0x29a0, /*!< flag_cf_speakererror_int_pol */
- TFA1_BF_INTPOLACS= 0x29b0, /*!< flag_cold_started_int_pol */
- TFA1_BF_INTPOLSWS= 0x29c0, /*!< flag_engage_int_pol */
- TFA1_BF_INTPOLWDS= 0x29d0, /*!< flag_watchdog_reset_int_pol */
- TFA1_BF_INTPOLAMPS= 0x29e0, /*!< flag_enbl_amp_int_pol */
- TFA1_BF_INTPOLAREFS= 0x29f0, /*!< flag_enbl_ref_int_pol */
- TFA1_BF_INTPOLACK= 0x2b01, /*!< Interrupt status flags polarity register */
- TFA1_BF_CLIP = 0x4900, /*!< Bypass clip control */
- TFA1_BF_CIMTP = 0x62b0, /*!< start copying all the data from i2cregs_mtp to mtp [Key 2 protected] */
- TFA1_BF_RST = 0x7000, /*!< Reset CoolFlux DSP */
- TFA1_BF_DMEM = 0x7011, /*!< Target memory for access */
- TFA1_BF_AIF = 0x7030, /*!< Autoincrement-flag for memory-address */
- TFA1_BF_CFINT = 0x7040, /*!< Interrupt CoolFlux DSP */
- TFA1_BF_REQ = 0x7087, /*!< request for access (8 channels) */
- TFA1_BF_REQCMD= 0x7080, /*!< Firmware event request rpc command */
- TFA1_BF_REQRST= 0x7090, /*!< Firmware event request reset restart */
- TFA1_BF_REQMIPS= 0x70a0, /*!< Firmware event request short on mips */
- TFA1_BF_REQMUTED= 0x70b0, /*!< Firmware event request mute sequence ready */
- TFA1_BF_REQVOL= 0x70c0, /*!< Firmware event request volume ready */
- TFA1_BF_REQDMG= 0x70d0, /*!< Firmware event request speaker damage detected */
- TFA1_BF_REQCAL= 0x70e0, /*!< Firmware event request calibration completed */
- TFA1_BF_REQRSV= 0x70f0, /*!< Firmware event request reserved */
- TFA1_BF_MADD = 0x710f, /*!< memory-address to be accessed */
- TFA1_BF_MEMA = 0x720f, /*!< activate memory access (24- or 32-bits data is written/read to/from memory */
- TFA1_BF_ERR = 0x7307, /*!< Coolflux error flags */
- TFA1_BF_ACK = 0x7387, /*!< acknowledge of requests (8 channels) */
- TFA1_BF_MTPOTC= 0x8000, /*!< Calibration schedule (key2 protected) */
- TFA1_BF_MTPEX = 0x8010, /*!< (key2 protected) */
-} nxpTfa1BfEnumList_t;
-#define TFA1_NAMETABLE static tfaBfName_t Tfa1DatasheetNames[]= {\
- { 0x0, "VDDS"}, /* Power-on-reset flag , */\
- { 0x10, "PLLS"}, /* PLL lock , */\
- { 0x20, "OTDS"}, /* Over Temperature Protection alarm , */\
- { 0x30, "OVDS"}, /* Over Voltage Protection alarm , */\
- { 0x40, "UVDS"}, /* Under Voltage Protection alarm , */\
- { 0x50, "OCDS"}, /* Over Current Protection alarm , */\
- { 0x60, "CLKS"}, /* Clocks stable flag , */\
- { 0x70, "CLIPS"}, /* Amplifier clipping , */\
- { 0x80, "MTPB"}, /* MTP busy , */\
- { 0x90, "NOCLK"}, /* Flag lost clock from clock generation unit , */\
- { 0xa0, "SPKS"}, /* Speaker error flag , */\
- { 0xb0, "ACS"}, /* Cold Start flag , */\
- { 0xc0, "SWS"}, /* Flag Engage , */\
- { 0xd0, "WDS"}, /* Flag watchdog reset , */\
- { 0xe0, "AMPS"}, /* Amplifier is enabled by manager , */\
- { 0xf0, "AREFS"}, /* References are enabled by manager , */\
- { 0x109, "BATS"}, /* Battery voltage readout; 0 .. 5.5 [V] , */\
- { 0x208, "TEMPS"}, /* Temperature readout from the temperature sensor , */\
- { 0x30b, "REV"}, /* Device type number is B97 , */\
- { 0x420, "RCV"}, /* Enable Receiver Mode , */\
- { 0x431, "CHS12"}, /* Channel Selection TDM input for Coolflux , */\
- { 0x450, "INPLVL"}, /* Input level selection control , */\
- { 0x461, "CHSA"}, /* Input selection for amplifier , */\
- { 0x4b0, "I2SDOE"}, /* Enable data output , */\
- { 0x4c3, "AUDFS"}, /* Audio sample rate setting , */\
- { 0x501, "SSCR"}, /* Protection Attack Time , */\
- { 0x523, "SST"}, /* ProtectionThreshold , */\
- { 0x561, "SSRL"}, /* Protection Maximum Reduction , */\
- { 0x582, "SSRR"}, /* Battery Protection Release Time , */\
- { 0x5b1, "SSHY"}, /* Battery Protection Hysteresis , */\
- { 0x5e0, "SSR"}, /* battery voltage for I2C read out only , */\
- { 0x5f0, "SSBY"}, /* bypass clipper battery protection , */\
- { 0x600, "DPSA"}, /* Enable dynamic powerstage activation , */\
- { 0x650, "CFSM"}, /* Soft mute in CoolFlux , */\
- { 0x670, "SSS"}, /* BatSenseSteepness , */\
- { 0x687, "VOL"}, /* volume control (in CoolFlux) , */\
- { 0x702, "DCVO"}, /* Boost Voltage , */\
- { 0x733, "DCMCC"}, /* Max boost coil current - step of 175 mA , */\
- { 0x7a0, "DCIE"}, /* Adaptive boost mode , */\
- { 0x7b0, "DCSR"}, /* Soft RampUp/Down mode for DCDC controller , */\
- { 0x7c0, "DCPAVG"}, /* ctrl_peak2avg for analog part of DCDC , */\
- { 0x800, "TROS"}, /* Select external temperature also the ext_temp will be put on the temp read out , */\
- { 0x818, "EXTTS"}, /* external temperature setting to be given by host , */\
- { 0x900, "PWDN"}, /* Device Mode , */\
- { 0x910, "I2CR"}, /* I2C Reset , */\
- { 0x920, "CFE"}, /* Enable CoolFlux , */\
- { 0x930, "AMPE"}, /* Enable Amplifier , */\
- { 0x940, "DCA"}, /* EnableBoost , */\
- { 0x950, "SBSL"}, /* Coolflux configured , */\
- { 0x960, "AMPC"}, /* Selection on how Amplifier is enabled , */\
- { 0x970, "DCDIS"}, /* DCDC not connected , */\
- { 0x980, "PSDR"}, /* IDDQ test amplifier , */\
- { 0x991, "DCCV"}, /* Coil Value , */\
- { 0x9b0, "CCFD"}, /* Selection CoolFlux Clock , */\
- { 0x9c1, "INTPAD"}, /* INT pad configuration control , */\
- { 0x9e0, "IPLL"}, /* PLL input reference clock selection , */\
- { 0xb07, "MTPK"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
- { 0xc25, "CVFDLY"}, /* Fractional delay adjustment between current and voltage sense, */\
- { 0x1011, "TDMPRF"}, /* TDM_usecase , */\
- { 0x1030, "TDMEN"}, /* TDM interface control , */\
- { 0x1040, "TDMCKINV"}, /* TDM clock inversion , */\
- { 0x1053, "TDMFSLN"}, /* TDM FS length , */\
- { 0x1090, "TDMFSPOL"}, /* TDM FS polarity , */\
- { 0x10a4, "TDMSAMSZ"}, /* TDM Sample Size for all tdm sinks/sources , */\
- { 0x1103, "TDMSLOTS"}, /* Number of slots , */\
- { 0x1144, "TDMSLLN"}, /* Slot length , */\
- { 0x1194, "TDMBRMG"}, /* Bits remaining , */\
- { 0x11e0, "TDMDDEL"}, /* Data delay , */\
- { 0x11f0, "TDMDADJ"}, /* Data adjustment , */\
- { 0x1201, "TDMTXFRM"}, /* TXDATA format , */\
- { 0x1221, "TDMUUS0"}, /* TXDATA format unused slot sd0 , */\
- { 0x1241, "TDMUUS1"}, /* TXDATA format unused slot sd1 , */\
- { 0x1270, "TDMSI0EN"}, /* TDM sink0 enable , */\
- { 0x1280, "TDMSI1EN"}, /* TDM sink1 enable , */\
- { 0x1290, "TDMSI2EN"}, /* TDM sink2 enable , */\
- { 0x12a0, "TDMSO0EN"}, /* TDM source0 enable , */\
- { 0x12b0, "TDMSO1EN"}, /* TDM source1 enable , */\
- { 0x12c0, "TDMSO2EN"}, /* TDM source2 enable , */\
- { 0x12d0, "TDMSI0IO"}, /* tdm_sink0_io , */\
- { 0x12e0, "TDMSI1IO"}, /* tdm_sink1_io , */\
- { 0x12f0, "TDMSI2IO"}, /* tdm_sink2_io , */\
- { 0x1300, "TDMSO0IO"}, /* tdm_source0_io , */\
- { 0x1310, "TDMSO1IO"}, /* tdm_source1_io , */\
- { 0x1320, "TDMSO2IO"}, /* tdm_source2_io , */\
- { 0x1333, "TDMSI0SL"}, /* sink0_slot [GAIN IN] , */\
- { 0x1373, "TDMSI1SL"}, /* sink1_slot [CH1 IN] , */\
- { 0x13b3, "TDMSI2SL"}, /* sink2_slot [CH2 IN] , */\
- { 0x1403, "TDMSO0SL"}, /* source0_slot [GAIN OUT] , */\
- { 0x1443, "TDMSO1SL"}, /* source1_slot [Voltage Sense] , */\
- { 0x1483, "TDMSO2SL"}, /* source2_slot [Current Sense] , */\
- { 0x14c3, "NBCK"}, /* NBCK , */\
- { 0x2000, "INTOVDDS"}, /* flag_por_int_out , */\
- { 0x2010, "INTOPLLS"}, /* flag_pll_lock_int_out , */\
- { 0x2020, "INTOOTDS"}, /* flag_otpok_int_out , */\
- { 0x2030, "INTOOVDS"}, /* flag_ovpok_int_out , */\
- { 0x2040, "INTOUVDS"}, /* flag_uvpok_int_out , */\
- { 0x2050, "INTOOCDS"}, /* flag_ocp_alarm_int_out , */\
- { 0x2060, "INTOCLKS"}, /* flag_clocks_stable_int_out , */\
- { 0x2070, "INTOCLIPS"}, /* flag_clip_int_out , */\
- { 0x2080, "INTOMTPB"}, /* mtp_busy_int_out , */\
- { 0x2090, "INTONOCLK"}, /* flag_lost_clk_int_out , */\
- { 0x20a0, "INTOSPKS"}, /* flag_cf_speakererror_int_out , */\
- { 0x20b0, "INTOACS"}, /* flag_cold_started_int_out , */\
- { 0x20c0, "INTOSWS"}, /* flag_engage_int_out , */\
- { 0x20d0, "INTOWDS"}, /* flag_watchdog_reset_int_out , */\
- { 0x20e0, "INTOAMPS"}, /* flag_enbl_amp_int_out , */\
- { 0x20f0, "INTOAREFS"}, /* flag_enbl_ref_int_out , */\
- { 0x2201, "INTOACK"}, /* Interrupt status register output - Corresponding flag, */\
- { 0x2300, "INTIVDDS"}, /* flag_por_int_in , */\
- { 0x2310, "INTIPLLS"}, /* flag_pll_lock_int_in , */\
- { 0x2320, "INTIOTDS"}, /* flag_otpok_int_in , */\
- { 0x2330, "INTIOVDS"}, /* flag_ovpok_int_in , */\
- { 0x2340, "INTIUVDS"}, /* flag_uvpok_int_in , */\
- { 0x2350, "INTIOCDS"}, /* flag_ocp_alarm_int_in , */\
- { 0x2360, "INTICLKS"}, /* flag_clocks_stable_int_in , */\
- { 0x2370, "INTICLIPS"}, /* flag_clip_int_in , */\
- { 0x2380, "INTIMTPB"}, /* mtp_busy_int_in , */\
- { 0x2390, "INTINOCLK"}, /* flag_lost_clk_int_in , */\
- { 0x23a0, "INTISPKS"}, /* flag_cf_speakererror_int_in , */\
- { 0x23b0, "INTIACS"}, /* flag_cold_started_int_in , */\
- { 0x23c0, "INTISWS"}, /* flag_engage_int_in , */\
- { 0x23d0, "INTIWDS"}, /* flag_watchdog_reset_int_in , */\
- { 0x23e0, "INTIAMPS"}, /* flag_enbl_amp_int_in , */\
- { 0x23f0, "INTIAREFS"}, /* flag_enbl_ref_int_in , */\
- { 0x2501, "INTIACK"}, /* Interrupt register input , */\
- { 0x2600, "INTENVDDS"}, /* flag_por_int_enable , */\
- { 0x2610, "INTENPLLS"}, /* flag_pll_lock_int_enable , */\
- { 0x2620, "INTENOTDS"}, /* flag_otpok_int_enable , */\
- { 0x2630, "INTENOVDS"}, /* flag_ovpok_int_enable , */\
- { 0x2640, "INTENUVDS"}, /* flag_uvpok_int_enable , */\
- { 0x2650, "INTENOCDS"}, /* flag_ocp_alarm_int_enable , */\
- { 0x2660, "INTENCLKS"}, /* flag_clocks_stable_int_enable , */\
- { 0x2670, "INTENCLIPS"}, /* flag_clip_int_enable , */\
- { 0x2680, "INTENMTPB"}, /* mtp_busy_int_enable , */\
- { 0x2690, "INTENNOCLK"}, /* flag_lost_clk_int_enable , */\
- { 0x26a0, "INTENSPKS"}, /* flag_cf_speakererror_int_enable , */\
- { 0x26b0, "INTENACS"}, /* flag_cold_started_int_enable , */\
- { 0x26c0, "INTENSWS"}, /* flag_engage_int_enable , */\
- { 0x26d0, "INTENWDS"}, /* flag_watchdog_reset_int_enable , */\
- { 0x26e0, "INTENAMPS"}, /* flag_enbl_amp_int_enable , */\
- { 0x26f0, "INTENAREFS"}, /* flag_enbl_ref_int_enable , */\
- { 0x2801, "INTENACK"}, /* Interrupt enable register , */\
- { 0x2900, "INTPOLVDDS"}, /* flag_por_int_pol , */\
- { 0x2910, "INTPOLPLLS"}, /* flag_pll_lock_int_pol , */\
- { 0x2920, "INTPOLOTDS"}, /* flag_otpok_int_pol , */\
- { 0x2930, "INTPOLOVDS"}, /* flag_ovpok_int_pol , */\
- { 0x2940, "INTPOLUVDS"}, /* flag_uvpok_int_pol , */\
- { 0x2950, "INTPOLOCDS"}, /* flag_ocp_alarm_int_pol , */\
- { 0x2960, "INTPOLCLKS"}, /* flag_clocks_stable_int_pol , */\
- { 0x2970, "INTPOLCLIPS"}, /* flag_clip_int_pol , */\
- { 0x2980, "INTPOLMTPB"}, /* mtp_busy_int_pol , */\
- { 0x2990, "INTPOLNOCLK"}, /* flag_lost_clk_int_pol , */\
- { 0x29a0, "INTPOLSPKS"}, /* flag_cf_speakererror_int_pol , */\
- { 0x29b0, "INTPOLACS"}, /* flag_cold_started_int_pol , */\
- { 0x29c0, "INTPOLSWS"}, /* flag_engage_int_pol , */\
- { 0x29d0, "INTPOLWDS"}, /* flag_watchdog_reset_int_pol , */\
- { 0x29e0, "INTPOLAMPS"}, /* flag_enbl_amp_int_pol , */\
- { 0x29f0, "INTPOLAREFS"}, /* flag_enbl_ref_int_pol , */\
- { 0x2b01, "INTPOLACK"}, /* Interrupt status flags polarity register , */\
- { 0x4900, "CLIP"}, /* Bypass clip control , */\
- { 0x62b0, "CIMTP"}, /* start copying all the data from i2cregs_mtp to mtp [Key 2 protected], */\
- { 0x7000, "RST"}, /* Reset CoolFlux DSP , */\
- { 0x7011, "DMEM"}, /* Target memory for access , */\
- { 0x7030, "AIF"}, /* Autoincrement-flag for memory-address , */\
- { 0x7040, "CFINT"}, /* Interrupt CoolFlux DSP , */\
- { 0x7087, "REQ"}, /* request for access (8 channels) , */\
- { 0x7080, "REQCMD"}, /* Firmware event request rpc command , */\
- { 0x7090, "REQRST"}, /* Firmware event request reset restart , */\
- { 0x70a0, "REQMIPS"}, /* Firmware event request short on mips , */\
- { 0x70b0, "REQMUTED"}, /* Firmware event request mute sequence ready , */\
- { 0x70c0, "REQVOL"}, /* Firmware event request volume ready , */\
- { 0x70d0, "REQDMG"}, /* Firmware event request speaker damage detected , */\
- { 0x70e0, "REQCAL"}, /* Firmware event request calibration completed , */\
- { 0x70f0, "REQRSV"}, /* Firmware event request reserved , */\
- { 0x710f, "MADD"}, /* memory-address to be accessed , */\
- { 0x720f, "MEMA"}, /* activate memory access (24- or 32-bits data is written/read to/from memory, */\
- { 0x7307, "ERR"}, /* Coolflux error flags , */\
- { 0x7387, "ACK"}, /* acknowledge of requests (8 channels) , */\
- { 0x7380, "ACKCMD"}, /* Firmware event acknowledge rpc command , */\
- { 0x7390, "ACKRST"}, /* Firmware event acknowledge reset restart , */\
- { 0x73a0, "ACKMIPS"}, /* Firmware event acknowledge short on mips , */\
- { 0x73b0, "ACKMUTED"}, /* Firmware event acknowledge mute sequence ready , */\
- { 0x73c0, "ACKVOL"}, /* Firmware event acknowledge volume ready , */\
- { 0x73d0, "ACKDMG"}, /* Firmware event acknowledge speaker damage detected, */\
- { 0x73e0, "ACKCAL"}, /* Firmware event acknowledge calibration completed , */\
- { 0x73f0, "ACKRSV"}, /* Firmware event acknowledge reserved , */\
- { 0x8000, "MTPOTC"}, /* Calibration schedule (key2 protected) , */\
- { 0x8010, "MTPEX"}, /* (key2 protected) , */\
- { 0x8045, "SWPROFIL" },\
- { 0x80a5, "SWVSTEP" },\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-
-#define TFA1_BITNAMETABLE static tfaBfName_t Tfa1BitNames[]= {\
- { 0x0, "flag_por"}, /* Power-on-reset flag , */\
- { 0x10, "flag_pll_lock"}, /* PLL lock , */\
- { 0x20, "flag_otpok"}, /* Over Temperature Protection alarm , */\
- { 0x30, "flag_ovpok"}, /* Over Voltage Protection alarm , */\
- { 0x40, "flag_uvpok"}, /* Under Voltage Protection alarm , */\
- { 0x50, "flag_ocp_alarm"}, /* Over Current Protection alarm , */\
- { 0x60, "flag_clocks_stable"}, /* Clocks stable flag , */\
- { 0x70, "flag_clip"}, /* Amplifier clipping , */\
- { 0x80, "mtp_busy"}, /* MTP busy , */\
- { 0x90, "flag_lost_clk"}, /* Flag lost clock from clock generation unit , */\
- { 0xa0, "flag_cf_speakererror"}, /* Speaker error flag , */\
- { 0xb0, "flag_cold_started"}, /* Cold Start flag , */\
- { 0xc0, "flag_engage"}, /* Flag Engage , */\
- { 0xd0, "flag_watchdog_reset"}, /* Flag watchdog reset , */\
- { 0xe0, "flag_enbl_amp"}, /* Amplifier is enabled by manager , */\
- { 0xf0, "flag_enbl_ref"}, /* References are enabled by manager , */\
- { 0x109, "bat_adc"}, /* Battery voltage readout; 0 .. 5.5 [V] , */\
- { 0x208, "temp_adc"}, /* Temperature readout from the temperature sensor , */\
- { 0x30b, "rev_reg"}, /* Device type number is B97 , */\
- { 0x420, "ctrl_rcv"}, /* Enable Receiver Mode , */\
- { 0x431, "chan_sel"}, /* Channel Selection TDM input for Coolflux , */\
- { 0x450, "input_level"}, /* Input level selection control , */\
- { 0x461, "vamp_sel"}, /* Input selection for amplifier , */\
- { 0x4c3, "audio_fs"}, /* Audio sample rate setting , */\
- { 0x501, "vbat_prot_attacktime"}, /* Protection Attack Time , */\
- { 0x523, "vbat_prot_thlevel"}, /* ProtectionThreshold , */\
- { 0x561, "vbat_prot_max_reduct"}, /* Protection Maximum Reduction , */\
- { 0x582, "vbat_prot_release_t"}, /* Battery Protection Release Time , */\
- { 0x5b1, "vbat_prot_hysterese"}, /* Battery Protection Hysteresis , */\
- { 0x5d0, "reset_min_vbat"}, /* reset clipper , */\
- { 0x5e0, "sel_vbat"}, /* battery voltage for I2C read out only , */\
- { 0x5f0, "bypass_clipper"}, /* bypass clipper battery protection , */\
- { 0x600, "dpsa"}, /* Enable dynamic powerstage activation , */\
- { 0x650, "cf_mute"}, /* Soft mute in CoolFlux , */\
- { 0x670, "batsense_steepness"}, /* BatSenseSteepness , */\
- { 0x687, "vol"}, /* volume control (in CoolFlux) , */\
- { 0x702, "boost_volt"}, /* Boost Voltage , */\
- { 0x733, "boost_cur"}, /* Max boost coil current - step of 175 mA , */\
- { 0x7a0, "boost_intel"}, /* Adaptive boost mode , */\
- { 0x7b0, "boost_speed"}, /* Soft RampUp/Down mode for DCDC controller , */\
- { 0x7c0, "boost_peak2avg"}, /* ctrl_peak2avg for analog part of DCDC , */\
- { 0x800, "ext_temp_sel"}, /* Select external temperature also the ext_temp will be put on the temp read out , */\
- { 0x818, "ext_temp"}, /* external temperature setting to be given by host , */\
- { 0x8b2, "dcdc_synchronisation"}, /* DCDC synchronisation off + 7 positions , */\
- { 0x900, "powerdown"}, /* Device Mode , */\
- { 0x910, "reset"}, /* I2C Reset , */\
- { 0x920, "enbl_coolflux"}, /* Enable CoolFlux , */\
- { 0x930, "enbl_amplifier"}, /* Enable Amplifier , */\
- { 0x940, "enbl_boost"}, /* EnableBoost , */\
- { 0x950, "coolflux_configured"}, /* Coolflux configured , */\
- { 0x960, "sel_enbl_amplifier"}, /* Selection on how Amplifier is enabled , */\
- { 0x970, "dcdcoff_mode"}, /* DCDC not connected , */\
- { 0x980, "iddqtest"}, /* IDDQ test amplifier , */\
- { 0x991, "coil_value"}, /* Coil Value , */\
- { 0x9b0, "sel_cf_clock"}, /* Selection CoolFlux Clock , */\
- { 0x9c1, "int_pad_io"}, /* INT pad configuration control , */\
- { 0x9e0, "sel_fs_bck"}, /* PLL input reference clock selection , */\
- { 0x9f0, "sel_scl_cf_clock"}, /* Coolflux sub-system clock , */\
- { 0xb07, "mtpkey2"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
- { 0xc00, "enbl_volt_sense"}, /* Voltage sense enabling control bit , */\
- { 0xc10, "vsense_pwm_sel"}, /* Voltage sense PWM source selection control , */\
- { 0xc25, "vi_frac_delay"}, /* Fractional delay adjustment between current and voltage sense, */\
- { 0xc80, "sel_voltsense_out"}, /* TDM output data selection control , */\
- { 0xc90, "vsense_bypass_avg"}, /* Voltage Sense Average Block Bypass , */\
- { 0xd05, "cf_frac_delay"}, /* Fractional delay adjustment between current and voltage sense by firmware, */\
- { 0xe00, "bypass_dcdc_curr_prot"}, /* Control to switch off dcdc current reduction with bat protection, */\
- { 0xe80, "disable_clock_sh_prot"}, /* disable clock_sh protection , */\
- { 0xe96, "reserve_reg_1_15_9"}, /* , */\
- { 0x1011, "tdm_usecase"}, /* TDM_usecase , */\
- { 0x1030, "tdm_enable"}, /* TDM interface control , */\
- { 0x1040, "tdm_clk_inversion"}, /* TDM clock inversion , */\
- { 0x1053, "tdm_fs_ws_length"}, /* TDM FS length , */\
- { 0x1090, "tdm_fs_ws_polarity"}, /* TDM FS polarity , */\
- { 0x10a4, "tdm_sample_size"}, /* TDM Sample Size for all tdm sinks/sources , */\
- { 0x1103, "tdm_nb_of_slots"}, /* Number of slots , */\
- { 0x1144, "tdm_slot_length"}, /* Slot length , */\
- { 0x1194, "tdm_bits_remaining"}, /* Bits remaining , */\
- { 0x11e0, "tdm_data_delay"}, /* Data delay , */\
- { 0x11f0, "tdm_data_adjustment"}, /* Data adjustment , */\
- { 0x1201, "tdm_txdata_format"}, /* TXDATA format , */\
- { 0x1221, "tdm_txdata_format_unused_slot_sd0"}, /* TXDATA format unused slot sd0 , */\
- { 0x1241, "tdm_txdata_format_unused_slot_sd1"}, /* TXDATA format unused slot sd1 , */\
- { 0x1270, "tdm_sink0_enable"}, /* TDM sink0 enable , */\
- { 0x1280, "tdm_sink1_enable"}, /* TDM sink1 enable , */\
- { 0x1290, "tdm_sink2_enable"}, /* TDM sink2 enable , */\
- { 0x12a0, "tdm_source0_enable"}, /* TDM source0 enable , */\
- { 0x12b0, "tdm_source1_enable"}, /* TDM source1 enable , */\
- { 0x12c0, "tdm_source2_enable"}, /* TDM source2 enable , */\
- { 0x12d0, "tdm_sink0_io"}, /* tdm_sink0_io , */\
- { 0x12e0, "tdm_sink1_io"}, /* tdm_sink1_io , */\
- { 0x12f0, "tdm_sink2_io"}, /* tdm_sink2_io , */\
- { 0x1300, "tdm_source0_io"}, /* tdm_source0_io , */\
- { 0x1310, "tdm_source1_io"}, /* tdm_source1_io , */\
- { 0x1320, "tdm_source2_io"}, /* tdm_source2_io , */\
- { 0x1333, "tdm_sink0_slot"}, /* sink0_slot [GAIN IN] , */\
- { 0x1373, "tdm_sink1_slot"}, /* sink1_slot [CH1 IN] , */\
- { 0x13b3, "tdm_sink2_slot"}, /* sink2_slot [CH2 IN] , */\
- { 0x1403, "tdm_source0_slot"}, /* source0_slot [GAIN OUT] , */\
- { 0x1443, "tdm_source1_slot"}, /* source1_slot [Voltage Sense] , */\
- { 0x1483, "tdm_source2_slot"}, /* source2_slot [Current Sense] , */\
- { 0x14c3, "tdm_nbck"}, /* NBCK , */\
- { 0x1500, "flag_tdm_lut_error"}, /* TDM LUT error flag , */\
- { 0x1512, "flag_tdm_status"}, /* TDM interface status bits , */\
- { 0x1540, "flag_tdm_error"}, /* TDM interface error indicator , */\
- { 0x2000, "flag_por_int_out"}, /* flag_por_int_out , */\
- { 0x2010, "flag_pll_lock_int_out"}, /* flag_pll_lock_int_out , */\
- { 0x2020, "flag_otpok_int_out"}, /* flag_otpok_int_out , */\
- { 0x2030, "flag_ovpok_int_out"}, /* flag_ovpok_int_out , */\
- { 0x2040, "flag_uvpok_int_out"}, /* flag_uvpok_int_out , */\
- { 0x2050, "flag_ocp_alarm_int_out"}, /* flag_ocp_alarm_int_out , */\
- { 0x2060, "flag_clocks_stable_int_out"}, /* flag_clocks_stable_int_out , */\
- { 0x2070, "flag_clip_int_out"}, /* flag_clip_int_out , */\
- { 0x2080, "mtp_busy_int_out"}, /* mtp_busy_int_out , */\
- { 0x2090, "flag_lost_clk_int_out"}, /* flag_lost_clk_int_out , */\
- { 0x20a0, "flag_cf_speakererror_int_out"}, /* flag_cf_speakererror_int_out , */\
- { 0x20b0, "flag_cold_started_int_out"}, /* flag_cold_started_int_out , */\
- { 0x20c0, "flag_engage_int_out"}, /* flag_engage_int_out , */\
- { 0x20d0, "flag_watchdog_reset_int_out"}, /* flag_watchdog_reset_int_out , */\
- { 0x20e0, "flag_enbl_amp_int_out"}, /* flag_enbl_amp_int_out , */\
- { 0x20f0, "flag_enbl_ref_int_out"}, /* flag_enbl_ref_int_out , */\
- { 0x2100, "flag_voutcomp_int_out"}, /* flag_voutcomp_int_out , */\
- { 0x2110, "flag_voutcomp93_int_out"}, /* flag_voutcomp93_int_out , */\
- { 0x2120, "flag_voutcomp86_int_out"}, /* flag_voutcomp86_int_out , */\
- { 0x2130, "flag_hiz_int_out"}, /* flag_hiz_int_out , */\
- { 0x2140, "flag_ocpokbst_int_out"}, /* flag_ocpokbst_int_out , */\
- { 0x2150, "flag_peakcur_int_out"}, /* flag_peakcur_int_out , */\
- { 0x2160, "flag_ocpokap_int_out"}, /* flag_ocpokap_int_out , */\
- { 0x2170, "flag_ocpokan_int_out"}, /* flag_ocpokan_int_out , */\
- { 0x2180, "flag_ocpokbp_int_out"}, /* flag_ocpokbp_int_out , */\
- { 0x2190, "flag_ocpokbn_int_out"}, /* flag_ocpokbn_int_out , */\
- { 0x21a0, "flag_adc10_ready_int_out"}, /* flag_adc10_ready_int_out , */\
- { 0x21b0, "flag_clipa_high_int_out"}, /* flag_clipa_high_int_out , */\
- { 0x21c0, "flag_clipa_low_int_out"}, /* flag_clipa_low_int_out , */\
- { 0x21d0, "flag_clipb_high_int_out"}, /* flag_clipb_high_int_out , */\
- { 0x21e0, "flag_clipb_low_int_out"}, /* flag_clipb_low_int_out , */\
- { 0x21f0, "flag_tdm_error_int_out"}, /* flag_tdm_error_int_out , */\
- { 0x2201, "interrupt_out3"}, /* Interrupt status register output - Corresponding flag, */\
- { 0x2300, "flag_por_int_in"}, /* flag_por_int_in , */\
- { 0x2310, "flag_pll_lock_int_in"}, /* flag_pll_lock_int_in , */\
- { 0x2320, "flag_otpok_int_in"}, /* flag_otpok_int_in , */\
- { 0x2330, "flag_ovpok_int_in"}, /* flag_ovpok_int_in , */\
- { 0x2340, "flag_uvpok_int_in"}, /* flag_uvpok_int_in , */\
- { 0x2350, "flag_ocp_alarm_int_in"}, /* flag_ocp_alarm_int_in , */\
- { 0x2360, "flag_clocks_stable_int_in"}, /* flag_clocks_stable_int_in , */\
- { 0x2370, "flag_clip_int_in"}, /* flag_clip_int_in , */\
- { 0x2380, "mtp_busy_int_in"}, /* mtp_busy_int_in , */\
- { 0x2390, "flag_lost_clk_int_in"}, /* flag_lost_clk_int_in , */\
- { 0x23a0, "flag_cf_speakererror_int_in"}, /* flag_cf_speakererror_int_in , */\
- { 0x23b0, "flag_cold_started_int_in"}, /* flag_cold_started_int_in , */\
- { 0x23c0, "flag_engage_int_in"}, /* flag_engage_int_in , */\
- { 0x23d0, "flag_watchdog_reset_int_in"}, /* flag_watchdog_reset_int_in , */\
- { 0x23e0, "flag_enbl_amp_int_in"}, /* flag_enbl_amp_int_in , */\
- { 0x23f0, "flag_enbl_ref_int_in"}, /* flag_enbl_ref_int_in , */\
- { 0x2400, "flag_voutcomp_int_in"}, /* flag_voutcomp_int_in , */\
- { 0x2410, "flag_voutcomp93_int_in"}, /* flag_voutcomp93_int_in , */\
- { 0x2420, "flag_voutcomp86_int_in"}, /* flag_voutcomp86_int_in , */\
- { 0x2430, "flag_hiz_int_in"}, /* flag_hiz_int_in , */\
- { 0x2440, "flag_ocpokbst_int_in"}, /* flag_ocpokbst_int_in , */\
- { 0x2450, "flag_peakcur_int_in"}, /* flag_peakcur_int_in , */\
- { 0x2460, "flag_ocpokap_int_in"}, /* flag_ocpokap_int_in , */\
- { 0x2470, "flag_ocpokan_int_in"}, /* flag_ocpokan_int_in , */\
- { 0x2480, "flag_ocpokbp_int_in"}, /* flag_ocpokbp_int_in , */\
- { 0x2490, "flag_ocpokbn_int_in"}, /* flag_ocpokbn_int_in , */\
- { 0x24a0, "flag_adc10_ready_int_in"}, /* flag_adc10_ready_int_in , */\
- { 0x24b0, "flag_clipa_high_int_in"}, /* flag_clipa_high_int_in , */\
- { 0x24c0, "flag_clipa_low_int_in"}, /* flag_clipa_low_int_in , */\
- { 0x24d0, "flag_clipb_high_int_in"}, /* flag_clipb_high_int_in , */\
- { 0x24e0, "flag_clipb_low_int_in"}, /* flag_clipb_low_int_in , */\
- { 0x24f0, "flag_tdm_error_int_in"}, /* flag_tdm_error_int_in , */\
- { 0x2501, "interrupt_in3"}, /* Interrupt register input , */\
- { 0x2600, "flag_por_int_enable"}, /* flag_por_int_enable , */\
- { 0x2610, "flag_pll_lock_int_enable"}, /* flag_pll_lock_int_enable , */\
- { 0x2620, "flag_otpok_int_enable"}, /* flag_otpok_int_enable , */\
- { 0x2630, "flag_ovpok_int_enable"}, /* flag_ovpok_int_enable , */\
- { 0x2640, "flag_uvpok_int_enable"}, /* flag_uvpok_int_enable , */\
- { 0x2650, "flag_ocp_alarm_int_enable"}, /* flag_ocp_alarm_int_enable , */\
- { 0x2660, "flag_clocks_stable_int_enable"}, /* flag_clocks_stable_int_enable , */\
- { 0x2670, "flag_clip_int_enable"}, /* flag_clip_int_enable , */\
- { 0x2680, "mtp_busy_int_enable"}, /* mtp_busy_int_enable , */\
- { 0x2690, "flag_lost_clk_int_enable"}, /* flag_lost_clk_int_enable , */\
- { 0x26a0, "flag_cf_speakererror_int_enable"}, /* flag_cf_speakererror_int_enable , */\
- { 0x26b0, "flag_cold_started_int_enable"}, /* flag_cold_started_int_enable , */\
- { 0x26c0, "flag_engage_int_enable"}, /* flag_engage_int_enable , */\
- { 0x26d0, "flag_watchdog_reset_int_enable"}, /* flag_watchdog_reset_int_enable , */\
- { 0x26e0, "flag_enbl_amp_int_enable"}, /* flag_enbl_amp_int_enable , */\
- { 0x26f0, "flag_enbl_ref_int_enable"}, /* flag_enbl_ref_int_enable , */\
- { 0x2700, "flag_voutcomp_int_enable"}, /* flag_voutcomp_int_enable , */\
- { 0x2710, "flag_voutcomp93_int_enable"}, /* flag_voutcomp93_int_enable , */\
- { 0x2720, "flag_voutcomp86_int_enable"}, /* flag_voutcomp86_int_enable , */\
- { 0x2730, "flag_hiz_int_enable"}, /* flag_hiz_int_enable , */\
- { 0x2740, "flag_ocpokbst_int_enable"}, /* flag_ocpokbst_int_enable , */\
- { 0x2750, "flag_peakcur_int_enable"}, /* flag_peakcur_int_enable , */\
- { 0x2760, "flag_ocpokap_int_enable"}, /* flag_ocpokap_int_enable , */\
- { 0x2770, "flag_ocpokan_int_enable"}, /* flag_ocpokan_int_enable , */\
- { 0x2780, "flag_ocpokbp_int_enable"}, /* flag_ocpokbp_int_enable , */\
- { 0x2790, "flag_ocpokbn_int_enable"}, /* flag_ocpokbn_int_enable , */\
- { 0x27a0, "flag_adc10_ready_int_enable"}, /* flag_adc10_ready_int_enable , */\
- { 0x27b0, "flag_clipa_high_int_enable"}, /* flag_clipa_high_int_enable , */\
- { 0x27c0, "flag_clipa_low_int_enable"}, /* flag_clipa_low_int_enable , */\
- { 0x27d0, "flag_clipb_high_int_enable"}, /* flag_clipb_high_int_enable , */\
- { 0x27e0, "flag_clipb_low_int_enable"}, /* flag_clipb_low_int_enable , */\
- { 0x27f0, "flag_tdm_error_int_enable"}, /* flag_tdm_error_int_enable , */\
- { 0x2801, "interrupt_enable3"}, /* Interrupt enable register , */\
- { 0x2900, "flag_por_int_pol"}, /* flag_por_int_pol , */\
- { 0x2910, "flag_pll_lock_int_pol"}, /* flag_pll_lock_int_pol , */\
- { 0x2920, "flag_otpok_int_pol"}, /* flag_otpok_int_pol , */\
- { 0x2930, "flag_ovpok_int_pol"}, /* flag_ovpok_int_pol , */\
- { 0x2940, "flag_uvpok_int_pol"}, /* flag_uvpok_int_pol , */\
- { 0x2950, "flag_ocp_alarm_int_pol"}, /* flag_ocp_alarm_int_pol , */\
- { 0x2960, "flag_clocks_stable_int_pol"}, /* flag_clocks_stable_int_pol , */\
- { 0x2970, "flag_clip_int_pol"}, /* flag_clip_int_pol , */\
- { 0x2980, "mtp_busy_int_pol"}, /* mtp_busy_int_pol , */\
- { 0x2990, "flag_lost_clk_int_pol"}, /* flag_lost_clk_int_pol , */\
- { 0x29a0, "flag_cf_speakererror_int_pol"}, /* flag_cf_speakererror_int_pol , */\
- { 0x29b0, "flag_cold_started_int_pol"}, /* flag_cold_started_int_pol , */\
- { 0x29c0, "flag_engage_int_pol"}, /* flag_engage_int_pol , */\
- { 0x29d0, "flag_watchdog_reset_int_pol"}, /* flag_watchdog_reset_int_pol , */\
- { 0x29e0, "flag_enbl_amp_int_pol"}, /* flag_enbl_amp_int_pol , */\
- { 0x29f0, "flag_enbl_ref_int_pol"}, /* flag_enbl_ref_int_pol , */\
- { 0x2a00, "flag_voutcomp_int_pol"}, /* flag_voutcomp_int_pol , */\
- { 0x2a10, "flag_voutcomp93_int_pol"}, /* flag_voutcomp93_int_pol , */\
- { 0x2a20, "flag_voutcomp86_int_pol"}, /* flag_voutcomp86_int_pol , */\
- { 0x2a30, "flag_hiz_int_pol"}, /* flag_hiz_int_pol , */\
- { 0x2a40, "flag_ocpokbst_int_pol"}, /* flag_ocpokbst_int_pol , */\
- { 0x2a50, "flag_peakcur_int_pol"}, /* flag_peakcur_int_pol , */\
- { 0x2a60, "flag_ocpokap_int_pol"}, /* flag_ocpokap_int_pol , */\
- { 0x2a70, "flag_ocpokan_int_pol"}, /* flag_ocpokan_int_pol , */\
- { 0x2a80, "flag_ocpokbp_int_pol"}, /* flag_ocpokbp_int_pol , */\
- { 0x2a90, "flag_ocpokbn_int_pol"}, /* flag_ocpokbn_int_pol , */\
- { 0x2aa0, "flag_adc10_ready_int_pol"}, /* flag_adc10_ready_int_pol , */\
- { 0x2ab0, "flag_clipa_high_int_pol"}, /* flag_clipa_high_int_pol , */\
- { 0x2ac0, "flag_clipa_low_int_pol"}, /* flag_clipa_low_int_pol , */\
- { 0x2ad0, "flag_clipb_high_int_pol"}, /* flag_clipb_high_int_pol , */\
- { 0x2ae0, "flag_clipb_low_int_pol"}, /* flag_clipb_low_int_pol , */\
- { 0x2af0, "flag_tdm_error_int_pol"}, /* flag_tdm_error_int_pol , */\
- { 0x2b01, "status_polarity3"}, /* Interrupt status flags polarity register , */\
- { 0x3000, "flag_voutcomp"}, /* flag_voutcomp, indication Vset is larger than Vbat, */\
- { 0x3010, "flag_voutcomp93"}, /* flag_voutcomp93, indication Vset is larger than 1.07* Vbat, */\
- { 0x3020, "flag_voutcomp86"}, /* flag_voutcomp86, indication Vset is larger than 1.14* Vbat, */\
- { 0x3030, "flag_hiz"}, /* flag_hiz, indication Vbst is larger than Vbat , */\
- { 0x3040, "flag_ocpokbst"}, /* flag_ocpokbst, indication no over current in boost converter pmos switch, */\
- { 0x3050, "flag_peakcur"}, /* flag_peakcur, indication current is max in dcdc converter, */\
- { 0x3060, "flag_ocpokap"}, /* flag_ocpokap, indication no over current in amplifier "a" pmos output stage, */\
- { 0x3070, "flag_ocpokan"}, /* flag_ocpokan, indication no over current in amplifier "a" nmos output stage, */\
- { 0x3080, "flag_ocpokbp"}, /* flag_ocpokbp, indication no over current in amplifier "b" pmos output stage, */\
- { 0x3090, "flag_ocpokbn"}, /* flag_ocpokbn, indication no over current in amplifier"b" nmos output stage, */\
- { 0x30a0, "flag_adc10_ready"}, /* flag_adc10_ready, indication adc10 is ready , */\
- { 0x30b0, "flag_clipa_high"}, /* flag_clipa_high, indication pmos amplifier "a" is clipping, */\
- { 0x30c0, "flag_clipa_low"}, /* flag_clipa_low, indication nmos amplifier "a" is clipping, */\
- { 0x30d0, "flag_clipb_high"}, /* flag_clipb_high, indication pmos amplifier "b" is clipping, */\
- { 0x30e0, "flag_clipb_low"}, /* flag_clipb_low, indication nmos amplifier "b" is clipping, */\
- { 0x310f, "mtp_man_data_out"}, /* single word read from MTP (manual copy) , */\
- { 0x3200, "key01_locked"}, /* key01_locked, indication key 1 is locked , */\
- { 0x3210, "key02_locked"}, /* key02_locked, indication key 2 is locked , */\
- { 0x3225, "mtp_ecc_tcout"}, /* mtp_ecc_tcout , */\
- { 0x3280, "mtpctrl_valid_test_rd"}, /* mtp test readout for read , */\
- { 0x3290, "mtpctrl_valid_test_wr"}, /* mtp test readout for write , */\
- { 0x32a0, "flag_in_alarm_state"}, /* Alarm state , */\
- { 0x32b0, "mtp_ecc_err2"}, /* two or more bit errors detected in MTP, can not reconstruct value, */\
- { 0x32c0, "mtp_ecc_err1"}, /* one bit error detected in MTP, reconstructed value, */\
- { 0x32d0, "mtp_mtp_hvf"}, /* high voltage ready flag for MTP , */\
- { 0x32f0, "mtp_zero_check_fail"}, /* zero check failed (tbd) for MTP , */\
- { 0x3309, "data_adc10_tempbat"}, /* data_adc10_tempbat[9;0], adc 10 data output for testing, */\
- { 0x400f, "hid_code"}, /* 5A6Bh, 23147d to access registers (Default for engineering), */\
- { 0x4100, "bypass_hp"}, /* Bypass_High Pass Filter , */\
- { 0x4110, "hard_mute"}, /* Hard Mute , */\
- { 0x4120, "soft_mute"}, /* Soft Mute , */\
- { 0x4134, "pwm_delay"}, /* PWM DelayBits to set the delay , */\
- { 0x4180, "pwm_shape"}, /* PWM Shape , */\
- { 0x4190, "pwm_bitlength"}, /* PWM Bitlength in noise shaper , */\
- { 0x4203, "drive"}, /* Drive bits to select amount of power stage amplifier, */\
- { 0x4240, "reclock_pwm"}, /* , */\
- { 0x4250, "reclock_voltsense"}, /* , */\
- { 0x4281, "dpsalevel"}, /* DPSA Threshold level , */\
- { 0x42a1, "dpsa_release"}, /* DPSA Release time , */\
- { 0x42c0, "coincidence"}, /* Prevent simultaneously switching of output stage , */\
- { 0x42d0, "kickback"}, /* Prevent double pulses of output stage , */\
- { 0x4306, "drivebst"}, /* Drive bits to select the powertransistor sections boost converter, */\
- { 0x43a0, "ocptestbst"}, /* Boost OCP. For old ocp (ctrl_reversebst is 0);For new ocp (ctrl_reversebst is 1);, */\
- { 0x43d0, "test_abistfft_enbl"}, /* FFT coolflux , */\
- { 0x43f0, "test_bcontrol"}, /* test _bcontrol , */\
- { 0x4400, "reversebst"}, /* OverCurrent Protection selection of power stage boost converter, */\
- { 0x4410, "sensetest"}, /* Test option for the sense NMOS in booster for current mode control., */\
- { 0x4420, "enbl_engagebst"}, /* Enable power stage dcdc controller , */\
- { 0x4470, "enbl_slopecur"}, /* Enable bit of max-current dac , */\
- { 0x4480, "enbl_voutcomp"}, /* Enable vout comparators , */\
- { 0x4490, "enbl_voutcomp93"}, /* Enable vout-93 comparators , */\
- { 0x44a0, "enbl_voutcomp86"}, /* Enable vout-86 comparators , */\
- { 0x44b0, "enbl_hizcom"}, /* Enable hiz comparator , */\
- { 0x44c0, "enbl_peakcur"}, /* Enable peak current , */\
- { 0x44d0, "bypass_ovpglitch"}, /* Bypass OVP Glitch Filter , */\
- { 0x44e0, "enbl_windac"}, /* Enable window dac , */\
- { 0x44f0, "enbl_powerbst"}, /* Enable line of the powerstage , */\
- { 0x4507, "ocp_thr"}, /* ocp_thr threshold level for OCP , */\
- { 0x4580, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
- { 0x4590, "bypass_ovp"}, /* Bypass OVP , */\
- { 0x45a0, "bypass_uvp"}, /* Bypass UVP , */\
- { 0x45b0, "bypass_otp"}, /* Bypass OTP , */\
- { 0x45c0, "bypass_ocp"}, /* Bypass OCP , */\
- { 0x45d0, "bypass_ocpcounter"}, /* BypassOCPCounter , */\
- { 0x45e0, "bypass_lost_clk"}, /* Bypasslost_clk detector , */\
- { 0x45f0, "vpalarm"}, /* vpalarm (uvp ovp handling) , */\
- { 0x4600, "bypass_gc"}, /* bypass_gc, bypasses the CS gain correction , */\
- { 0x4610, "cs_gain_control"}, /* gain control by means of MTP or i2c; 0 is MTP , */\
- { 0x4627, "cs_gain"}, /* + / - 128 steps in steps of 1/4 percent 2's compliment, */\
- { 0x46a0, "bypass_lp"}, /* bypass Low-Pass filter in temperature sensor , */\
- { 0x46b0, "bypass_pwmcounter"}, /* bypass_pwmcounter , */\
- { 0x46c0, "cs_negfixed"}, /* does not switch to neg , */\
- { 0x46d2, "cs_neghyst"}, /* switches to neg depending on level , */\
- { 0x4700, "switch_fb"}, /* switch_fb , */\
- { 0x4713, "se_hyst"}, /* se_hyst , */\
- { 0x4754, "se_level"}, /* se_level , */\
- { 0x47a5, "ktemp"}, /* temperature compensation trimming , */\
- { 0x4800, "cs_negin"}, /* negin , */\
- { 0x4810, "cs_sein"}, /* cs_sein , */\
- { 0x4820, "cs_coincidence"}, /* Coincidence current sense , */\
- { 0x4830, "iddqtestbst"}, /* for iddq testing in powerstage of boost convertor , */\
- { 0x4840, "coincidencebst"}, /* Switch protection on to prevent simultaneously switching power stages bst and amp, */\
- { 0x4876, "delay_se_neg"}, /* delay of se and neg , */\
- { 0x48e1, "cs_ttrack"}, /* sample & hold track time , */\
- { 0x4900, "bypass_clip"}, /* Bypass clip control , */\
- { 0x4920, "cf_cgate_off"}, /* to disable clock gating in the coolflux , */\
- { 0x4940, "clipfast"}, /* clock switch for battery protection clipper, it switches back to old frequency, */\
- { 0x4950, "cs_8ohm"}, /* 8 ohm mode for current sense (gain mode) , */\
- { 0x4974, "delay_clock_sh"}, /* delay_sh, tunes S7H delay , */\
- { 0x49c0, "inv_clksh"}, /* Invert the sample/hold clock for current sense ADC, */\
- { 0x49d0, "inv_neg"}, /* Invert neg signal , */\
- { 0x49e0, "inv_se"}, /* Invert se signal , */\
- { 0x49f0, "setse"}, /* switches between Single Ende and differential mode; 1 is single ended, */\
- { 0x4a12, "adc10_sel"}, /* select the input to convert the 10b ADC , */\
- { 0x4a60, "adc10_reset"}, /* Global asynchronous reset (active HIGH) 10 bit ADC, */\
- { 0x4a81, "adc10_test"}, /* Test mode selection signal 10 bit ADC , */\
- { 0x4aa0, "bypass_lp_vbat"}, /* lp filter in batt sensor , */\
- { 0x4ae0, "dc_offset"}, /* switch offset control on/off, is decimator offset control, */\
- { 0x4af0, "tsense_hibias"}, /* bit to set the biasing in temp sensor to high , */\
- { 0x4b00, "adc13_iset"}, /* Micadc Setting of current consumption. Debug use only, */\
- { 0x4b14, "adc13_gain"}, /* Micadc gain setting (2-compl) , */\
- { 0x4b61, "adc13_slowdel"}, /* Micadc Delay setting for internal clock. Debug use only, */\
- { 0x4b83, "adc13_offset"}, /* Micadc ADC offset setting , */\
- { 0x4bc0, "adc13_bsoinv"}, /* Micadc bit stream output invert mode for test , */\
- { 0x4bd0, "adc13_resonator_enable"}, /* Micadc Give extra SNR with less stability. Debug use only, */\
- { 0x4be0, "testmicadc"}, /* Mux at input of MICADC for test purpose , */\
- { 0x4c0f, "abist_offset"}, /* offset control for ABIST testing , */\
- { 0x4d05, "windac"}, /* for testing direct control windac , */\
- { 0x4dc3, "pwm_dcc_cnt"}, /* control pwm duty cycle when enbl_pwm_dcc is 1 , */\
- { 0x4e04, "slopecur"}, /* for testing direct control slopecur , */\
- { 0x4e50, "ctrl_dem"}, /* dyn element matching control, rest of codes are optional, */\
- { 0x4ed0, "enbl_pwm_dcc"}, /* to enable direct control of pwm duty cycle , */\
- { 0x5007, "gain"}, /* Gain setting of the gain multiplier , */\
- { 0x5081, "sourceb"}, /* Set OUTB to , */\
- { 0x50a1, "sourcea"}, /* Set OUTA to , */\
- { 0x50c1, "sourcebst"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
- { 0x50e0, "tdm_enable_loopback"}, /* TDM loopback test , */\
- { 0x5104, "pulselengthbst"}, /* pulse length setting test input for boost converter, */\
- { 0x5150, "bypasslatchbst"}, /* bypass_latch in boost converter , */\
- { 0x5160, "invertbst"}, /* invert pwmbst test signal , */\
- { 0x5174, "pulselength"}, /* pulse length setting test input for amplifier , */\
- { 0x51c0, "bypasslatch"}, /* bypass_latch in PWM source selection module , */\
- { 0x51d0, "invertb"}, /* invert pwmb test signal , */\
- { 0x51e0, "inverta"}, /* invert pwma test signal , */\
- { 0x51f0, "bypass_ctrlloop"}, /* bypass_ctrlloop bypasses the control loop of the amplifier, */\
- { 0x5210, "test_rdsona"}, /* tbd for rdson testing , */\
- { 0x5220, "test_rdsonb"}, /* tbd for rdson testing , */\
- { 0x5230, "test_rdsonbst"}, /* tbd for rdson testing , */\
- { 0x5240, "test_cvia"}, /* tbd for rdson testing , */\
- { 0x5250, "test_cvib"}, /* tbd for rdson testing , */\
- { 0x5260, "test_cvibst"}, /* tbd for rdson testing , */\
- { 0x5306, "digimuxa_sel"}, /* DigimuxA input selection control (see Digimux list for details), */\
- { 0x5376, "digimuxb_sel"}, /* DigimuxB input selection control (see Digimux list for details), */\
- { 0x5400, "hs_mode"}, /* hs_mode, high speed mode I2C bus , */\
- { 0x5412, "test_parametric_io"}, /* test_parametric_io for testing pads , */\
- { 0x5440, "enbl_ringo"}, /* enbl_ringo, for test purpose to check with ringo , */\
- { 0x5456, "digimuxc_sel"}, /* DigimuxC input selection control (see Digimux list for details), */\
- { 0x54c0, "dio_ehs"}, /* Slew control for DIO in output mode , */\
- { 0x54d0, "gainio_ehs"}, /* Slew control for GAINIO in output mode , */\
- { 0x550d, "enbl_amp"}, /* enbl_amp for testing to enable all analoge blocks in amplifier, */\
- { 0x5600, "use_direct_ctrls"}, /* use_direct_ctrls, to overrule several functions direct for testing, */\
- { 0x5610, "rst_datapath"}, /* rst_datapath, datapath reset , */\
- { 0x5620, "rst_cgu"}, /* rst_cgu, cgu reset , */\
- { 0x5637, "enbl_ref"}, /* for testing to enable all analoge blocks in references, */\
- { 0x56b0, "enbl_engage"}, /* Enable output stage amplifier , */\
- { 0x56c0, "use_direct_clk_ctrl"}, /* use_direct_clk_ctrl, to overrule several functions direct for testing, */\
- { 0x56d0, "use_direct_pll_ctrl"}, /* use_direct_pll_ctrl, to overrule several functions direct for testing, */\
- { 0x56e0, "use_direct_ctrls_2"}, /* use_direct_sourseamp_ctrls, to overrule several functions direct for testing, */\
- { 0x5707, "anamux"}, /* Anamux control , */\
- { 0x57c0, "ocptest"}, /* ctrl_ocptest, deactivates the over current protection in the power stages of the amplifier. The ocp flag signals stay active., */\
- { 0x57e0, "otptest"}, /* otptest, test mode otp amplifier , */\
- { 0x57f0, "reverse"}, /* 1: Normal mode, slope is controlled , */\
- { 0x5813, "pll_selr"}, /* pll_selr , */\
- { 0x5854, "pll_selp"}, /* pll_selp , */\
- { 0x58a5, "pll_seli"}, /* pll_seli , */\
- { 0x5950, "pll_mdec_msb"}, /* most significant bits of pll_mdec[16] , */\
- { 0x5960, "pll_ndec_msb"}, /* most significant bits of pll_ndec[9] , */\
- { 0x5970, "pll_frm"}, /* pll_frm , */\
- { 0x5980, "pll_directi"}, /* pll_directi , */\
- { 0x5990, "pll_directo"}, /* pll_directo , */\
- { 0x59a0, "enbl_pll"}, /* enbl_pll , */\
- { 0x59f0, "pll_bypass"}, /* pll_bypass , */\
- { 0x5a0f, "tsig_freq"}, /* tsig_freq, internal sinus test generator, frequency control, */\
- { 0x5b02, "tsig_freq_msb"}, /* select internal sinus test generator, frequency control msb bits, */\
- { 0x5b30, "inject_tsig"}, /* inject_tsig, control bit to switch to internal sinus test generator, */\
- { 0x5b44, "adc10_prog_sample"}, /* control ADC10 , */\
- { 0x5c0f, "pll_mdec"}, /* bits 15..0 of pll_mdec[16;0] , */\
- { 0x5d06, "pll_pdec"}, /* pll_pdec , */\
- { 0x5d78, "pll_ndec"}, /* bits 8..0 of pll_ndec[9;0] , */\
- { 0x6007, "mtpkey1"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
- { 0x6185, "mtp_ecc_tcin"}, /* Mtp_ecc_tcin , */\
- { 0x6203, "mtp_man_address_in"}, /* address from I2C regs for writing one word single mtp, */\
- { 0x6260, "mtp_ecc_eeb"}, /* enable code bit generation (active low!) , */\
- { 0x6270, "mtp_ecc_ecb"}, /* enable correction signal (active low!) , */\
- { 0x6280, "man_copy_mtp_to_iic"}, /* start copying single word from mtp to i2cregs_mtp , */\
- { 0x6290, "man_copy_iic_to_mtp"}, /* start copying single word from i2cregs_mtp to mtp [Key 1 protected], */\
- { 0x62a0, "auto_copy_mtp_to_iic"}, /* start copying all the data from mtp to i2cregs_mtp, */\
- { 0x62b0, "auto_copy_iic_to_mtp"}, /* start copying all the data from i2cregs_mtp to mtp [Key 2 protected], */\
- { 0x62d2, "mtp_speed_mode"}, /* Speed mode , */\
- { 0x6340, "mtp_direct_enable"}, /* mtp_direct_enable (key1 protected) , */\
- { 0x6350, "mtp_direct_wr"}, /* mtp_direct_wr (key1 protected) , */\
- { 0x6360, "mtp_direct_rd"}, /* mtp_direct_rd (key1 protected) , */\
- { 0x6370, "mtp_direct_rst"}, /* mtp_direct_rst (key1 protected) , */\
- { 0x6380, "mtp_direct_ers"}, /* mtp_direct_ers (key1 protected) , */\
- { 0x6390, "mtp_direct_prg"}, /* mtp_direct_prg (key1 protected) , */\
- { 0x63a0, "mtp_direct_epp"}, /* mtp_direct_epp (key1 protected) , */\
- { 0x63b4, "mtp_direct_test"}, /* mtp_direct_test (key1 protected) , */\
- { 0x640f, "mtp_man_data_in"}, /* single word to be written to MTP (manual copy) , */\
- { 0x7000, "cf_rst_dsp"}, /* Reset CoolFlux DSP , */\
- { 0x7011, "cf_dmem"}, /* Target memory for access , */\
- { 0x7030, "cf_aif"}, /* Autoincrement-flag for memory-address , */\
- { 0x7040, "cf_int"}, /* Interrupt CoolFlux DSP , */\
- { 0x7087, "cf_req"}, /* request for access (8 channels) , */\
- { 0x710f, "cf_madd"}, /* memory-address to be accessed , */\
- { 0x720f, "cf_mema"}, /* activate memory access (24- or 32-bits data is written/read to/from memory, */\
- { 0x7307, "cf_err"}, /* Coolflux error flags , */\
- { 0x7387, "cf_ack"}, /* acknowledge of requests (8 channels) , */\
- { 0x8000, "calibration_onetime"}, /* Calibration schedule (key2 protected) , */\
- { 0x8010, "calibr_ron_done"}, /* (key2 protected) , */\
- { 0x8105, "calibr_vout_offset"}, /* calibr_vout_offset (DCDCoffset) 2's compliment (key1 protected), */\
- { 0x8163, "calibr_delta_gain"}, /* delta gain for vamp (alpha) 2's compliment (key1 protected), */\
- { 0x81a5, "calibr_offs_amp"}, /* offset for vamp (Ampoffset) 2's compliment (key1 protected), */\
- { 0x8207, "calibr_gain_cs"}, /* gain current sense (Imeasalpha) 2's compliment (key1 protected), */\
- { 0x8284, "calibr_temp_offset"}, /* temperature offset 2's compliment (key1 protected), */\
- { 0x82d2, "calibr_temp_gain"}, /* temperature gain 2's compliment (key1 protected) , */\
- { 0x830f, "calibr_ron"}, /* Ron resistance of coil (key1 protected) , */\
- { 0x8505, "type_bits_HW"}, /* Key1_Protected_MTP5 , */\
- { 0x8601, "type_bits_1_0_SW"}, /* MTP-control SW , */\
- { 0x8681, "type_bits_8_9_SW"}, /* MTP-control SW , */\
- { 0x870f, "type_bits2_SW"}, /* MTP-control SW2 , */\
- { 0x8806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
- { 0x8870, "htol_iic_addr_en"}, /* HTOL_I2C_Address_Enable , */\
- { 0x8881, "ctrl_ovp_response"}, /* OVP response control , */\
- { 0x88a0, "disable_ovp_alarm_state"}, /* OVP alarm state control , */\
- { 0x88b0, "enbl_stretch_ovp"}, /* OVP alram strech control , */\
- { 0x88c0, "cf_debug_mode"}, /* Coolflux debug mode , */\
- { 0x8a0f, "production_data1"}, /* (key1 protected) , */\
- { 0x8b0f, "production_data2"}, /* (key1 protected) , */\
- { 0x8c0f, "production_data3"}, /* (key1 protected) , */\
- { 0x8d0f, "production_data4"}, /* (key1 protected) , */\
- { 0x8e0f, "production_data5"}, /* (key1 protected) , */\
- { 0x8f0f, "production_data6"}, /* (key1 protected) , */\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-
-enum tfa1_irq {
- tfa1_irq_vdds = 0,
- tfa1_irq_plls = 1,
- tfa1_irq_ds = 2,
- tfa1_irq_vds = 3,
- tfa1_irq_uvds = 4,
- tfa1_irq_cds = 5,
- tfa1_irq_clks = 6,
- tfa1_irq_clips = 7,
- tfa1_irq_mtpb = 8,
- tfa1_irq_clk = 9,
- tfa1_irq_spks = 10,
- tfa1_irq_acs = 11,
- tfa1_irq_sws = 12,
- tfa1_irq_wds = 13,
- tfa1_irq_amps = 14,
- tfa1_irq_arefs = 15,
- tfa1_irq_ack = 32,
- tfa1_irq_max = 33,
- tfa1_irq_all = -1 /* all irqs */};
-
-#define TFA1_IRQ_NAMETABLE static tfaIrqName_t Tfa1IrqNames[]= {\
- { 0, "VDDS"},\
- { 1, "PLLS"},\
- { 2, "DS"},\
- { 3, "VDS"},\
- { 4, "UVDS"},\
- { 5, "CDS"},\
- { 6, "CLKS"},\
- { 7, "CLIPS"},\
- { 8, "MTPB"},\
- { 9, "CLK"},\
- { 10, "SPKS"},\
- { 11, "ACS"},\
- { 12, "SWS"},\
- { 13, "WDS"},\
- { 14, "AMPS"},\
- { 15, "AREFS"},\
- { 16, "16"},\
- { 17, "17"},\
- { 18, "18"},\
- { 19, "19"},\
- { 20, "20"},\
- { 21, "21"},\
- { 22, "22"},\
- { 23, "23"},\
- { 24, "24"},\
- { 25, "25"},\
- { 26, "26"},\
- { 27, "27"},\
- { 28, "28"},\
- { 29, "29"},\
- { 30, "30"},\
- { 31, "31"},\
- { 32, "ACK"},\
- { 33, "33"},\
-};
diff --git a/inc/tfa9872_device_genregs_POR.h b/inc/tfa9872_device_genregs_POR.h
deleted file mode 100644
index 4bf88dd..0000000
--- a/inc/tfa9872_device_genregs_POR.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _TFA9872_DEVICE_GENREGS_H
-#define _TFA9872_DEVICE_GENREGS_H
-
-
-#define TFA9872_SYS_CONTROL0 0x00
-#define TFA9872_SYS_CONTROL1 0x01
-#define TFA9872_SYS_CONTROL2 0x02
-#define TFA9872_DEVICE_REVISION 0x03
-#define TFA9872_CLOCK_CONTROL 0x04
-#define TFA9872_CLOCK_GATING_CONTROL 0x05
-#define TFA9872_SIDE_TONE_CONFIG 0x0d
-#define TFA9872_STATUS_FLAGS0 0x10
-#define TFA9872_STATUS_FLAGS1 0x11
-#define TFA9872_STATUS_FLAGS3 0x13
-#define TFA9872_STATUS_FLAGS4 0x14
-#define TFA9872_BATTERY_VOLTAGE 0x15
-#define TFA9872_TEMPERATURE 0x16
-#define TFA9872_VDDP_VOLTAGE 0x17
-#define TFA9872_TDM_CONFIG0 0x20
-#define TFA9872_TDM_CONFIG1 0x21
-#define TFA9872_TDM_CONFIG2 0x22
-#define TFA9872_TDM_CONFIG3 0x23
-#define TFA9872_TDM_CONFIG6 0x26
-#define TFA9872_TDM_CONFIG7 0x27
-#define TFA9872_PDM_CONFIG0 0x31
-#define TFA9872_INTERRUPT_OUT_REG1 0x40
-#define TFA9872_INTERRUPT_OUT_REG2 0x41
-#define TFA9872_INTERRUPT_OUT_REG3 0x42
-#define TFA9872_INTERRUPT_IN_REG1 0x44
-#define TFA9872_INTERRUPT_IN_REG2 0x45
-#define TFA9872_INTERRUPT_IN_REG3 0x46
-#define TFA9872_INTERRUPT_ENABLE_REG1 0x48
-#define TFA9872_INTERRUPT_ENABLE_REG2 0x49
-#define TFA9872_INTERRUPT_ENABLE_REG3 0x4a
-#define TFA9872_STATUS_POLARITY_REG1 0x4c
-#define TFA9872_STATUS_POLARITY_REG2 0x4d
-#define TFA9872_STATUS_POLARITY_REG3 0x4e
-#define TFA9872_BAT_PROT_CONFIG 0x50
-#define TFA9872_AUDIO_CONTROL 0x51
-#define TFA9872_AMPLIFIER_CONFIG 0x52
-#define TFA9872_PGA_CONTROL0 0x60
-#define TFA9872_GAIN_ATT 0x61
-#define TFA9872_TDM_SOURCE_CTRL 0x68
-#define TFA9872_SAM_CTRL 0x69
-#define TFA9872_STATUS_FLAGS5 0x6e
-#define TFA9872_CURSENSE_COMP 0x6f
-#define TFA9872_DCDC_CONTROL0 0x70
-#define TFA9872_DCDC_CONTROL4 0x74
-#define TFA9872_DCDC_CONTROL5 0x75
-#define TFA9872_MTPKEY2_REG 0xa1
-#define TFA9872_MTP_STATUS 0xa2
-#define TFA9872_KEY_PROTECTED_MTP_CONTROL 0xa3
-#define TFA9872_MTP_DATA_OUT_MSB 0xa5
-#define TFA9872_MTP_DATA_OUT_LSB 0xa6
-#define TFA9872_TEMP_SENSOR_CONFIG 0xb1
-#define TFA9872_SOFTWARE_PROFILE 0xee
-#define TFA9872_SOFTWARE_VSTEP 0xef
-#define TFA9872_KEY2_PROTECTED_MTP0 0xf0
-#define TFA9872_KEY2_PROTECTED_MTP5 0xf5
-#define TFA9872_SYS_CONTROL0_POR 0x0001
-#define TFA9872_SYS_CONTROL1_POR 0x0000
-#define TFA9872_SYS_CONTROL2_POR 0x2828
-#define TFA9872_DEVICE_REVISION_POR 0x3b72
-#define TFA9872_CLOCK_CONTROL_POR 0x0000
-#define TFA9872_CLOCK_GATING_CONTROL_POR 0x1f6a
-#define TFA9872_SIDE_TONE_CONFIG_POR 0x0ebe
-#define TFA9872_STATUS_FLAGS0_POR 0x001d
-#define TFA9872_STATUS_FLAGS1_POR 0x0004
-#define TFA9872_STATUS_FLAGS3_POR 0x000f
-#define TFA9872_STATUS_FLAGS4_POR 0x0000
-#define TFA9872_BATTERY_VOLTAGE_POR 0x03ff
-#define TFA9872_TEMPERATURE_POR 0x0100
-#define TFA9872_VDDP_VOLTAGE_POR 0x0000
-#define TFA9872_TDM_CONFIG0_POR 0x2890
-#define TFA9872_TDM_CONFIG1_POR 0xc1f1
-#define TFA9872_TDM_CONFIG2_POR 0x045c
-#define TFA9872_TDM_CONFIG3_POR 0x0003
-#define TFA9872_TDM_CONFIG6_POR 0x0010
-#define TFA9872_TDM_CONFIG7_POR 0x0001
-#define TFA9872_PDM_CONFIG0_POR 0x0000
-#define TFA9872_INTERRUPT_OUT_REG1_POR 0x0081
-#define TFA9872_INTERRUPT_OUT_REG2_POR 0x0000
-#define TFA9872_INTERRUPT_OUT_REG3_POR 0x0000
-#define TFA9872_INTERRUPT_IN_REG1_POR 0x0000
-#define TFA9872_INTERRUPT_IN_REG2_POR 0x0000
-#define TFA9872_INTERRUPT_IN_REG3_POR 0x0000
-#define TFA9872_INTERRUPT_ENABLE_REG1_POR 0x0001
-#define TFA9872_INTERRUPT_ENABLE_REG2_POR 0x0000
-#define TFA9872_INTERRUPT_ENABLE_REG3_POR 0x0000
-#define TFA9872_STATUS_POLARITY_REG1_POR 0x74e3
-#define TFA9872_STATUS_POLARITY_REG2_POR 0x967b
-#define TFA9872_STATUS_POLARITY_REG3_POR 0x0085
-#define TFA9872_BAT_PROT_CONFIG_POR 0x8091
-#define TFA9872_AUDIO_CONTROL_POR 0x0080
-#define TFA9872_AMPLIFIER_CONFIG_POR 0x7a08
-#define TFA9872_PGA_CONTROL0_POR 0x0000
-#define TFA9872_GAIN_ATT_POR 0x0000
-#define TFA9872_TDM_SOURCE_CTRL_POR 0x0400
-#define TFA9872_SAM_CTRL_POR 0x0000
-#define TFA9872_STATUS_FLAGS5_POR 0x0007
-#define TFA9872_CURSENSE_COMP_POR 0x02e4
-#define TFA9872_DCDC_CONTROL0_POR 0x06e6
-#define TFA9872_DCDC_CONTROL4_POR 0xd913
-#define TFA9872_DCDC_CONTROL5_POR 0x118a
-#define TFA9872_MTPKEY2_REG_POR 0x0000
-#define TFA9872_MTP_STATUS_POR 0x0003
-#define TFA9872_KEY_PROTECTED_MTP_CONTROL_POR 0x0000
-#define TFA9872_MTP_DATA_OUT_MSB_POR 0x0000
-#define TFA9872_MTP_DATA_OUT_LSB_POR 0x0000
-#define TFA9872_TEMP_SENSOR_CONFIG_POR 0x0000
-#define TFA9872_SOFTWARE_PROFILE_POR 0x0000
-#define TFA9872_SOFTWARE_VSTEP_POR 0x0000
-#define TFA9872_KEY2_PROTECTED_MTP0_POR 0x0000
-#define TFA9872_KEY2_PROTECTED_MTP5_POR 0x0000
-
-#endif /* _TFA9872_DEVICE_GENREGS_H */
diff --git a/inc/tfa9872_tfafieldnames.h b/inc/tfa9872_tfafieldnames.h
deleted file mode 100644
index 8e943e5..0000000
--- a/inc/tfa9872_tfafieldnames.h
+++ /dev/null
@@ -1,1221 +0,0 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _TFA9872_TFAFIELDNAMES_H
-#define _TFA9872_TFAFIELDNAMES_H
-
-#define TFA9872_I2CVERSION_N1A 26
-#define TFA9872_I2CVERSION_N1B 29
-#define TFA9872_I2CVERSION_N1B2 25
-
-typedef enum nxpTfa9872BfEnumList {
- TFA9872_BF_PWDN = 0x0000, /*!< Powerdown selection */
- TFA9872_BF_I2CR = 0x0010, /*!< I2C Reset - Auto clear */
- TFA9872_BF_AMPE = 0x0030, /*!< Activate Amplifier */
- TFA9872_BF_DCA = 0x0040, /*!< Activate DC-to-DC converter */
- TFA9872_BF_INTP = 0x0071, /*!< Interrupt config */
- TFA9872_BF_BYPOCP= 0x00b0, /*!< Bypass OCP */
- TFA9872_BF_TSTOCP= 0x00c0, /*!< OCP testing control */
- TFA9872_BF_MANSCONF= 0x0120, /*!< I2C configured */
- TFA9872_BF_MANAOOSC= 0x0140, /*!< Internal osc off at PWDN */
- TFA9872_BF_MUTETO= 0x01d0, /*!< Time out SB mute sequence */
- TFA9872_BF_RCVNS = 0x01e0, /*!< Noise shaper selection */
- TFA9872_BF_AUDFS = 0x0203, /*!< Sample rate (fs) */
- TFA9872_BF_INPLEV= 0x0240, /*!< TDM output attenuation */
- TFA9872_BF_FRACTDEL= 0x0255, /*!< V/I Fractional delay */
- TFA9872_BF_BYPHVBF= 0x02b0, /*!< Bypass HVBAT filter */
- TFA9872_BF_REV = 0x030f, /*!< Revision info */
- TFA9872_BF_REFCKEXT= 0x0401, /*!< PLL external ref clock */
- TFA9872_BF_REFCKSEL= 0x0420, /*!< PLL internal ref clock */
- TFA9872_BF_SSE = 0x0510, /*!< Enable speaker path */
- TFA9872_BF_VSE = 0x0530, /*!< Voltage sense */
- TFA9872_BF_CSE = 0x0550, /*!< Current sense */
- TFA9872_BF_SSPDME= 0x0560, /*!< Sub-system PDM */
- TFA9872_BF_PGAE = 0x0580, /*!< Enable PGA chop clock */
- TFA9872_BF_SSTDME= 0x0590, /*!< Sub-system TDM */
- TFA9872_BF_SSPBSTE= 0x05a0, /*!< Sub-system boost */
- TFA9872_BF_SSADCE= 0x05b0, /*!< Sub-system ADC */
- TFA9872_BF_SSFAIME= 0x05c0, /*!< Sub-system FAIM */
- TFA9872_BF_STGAIN= 0x0d18, /*!< Side tone gain */
- TFA9872_BF_STSMUTE= 0x0da0, /*!< Side tone soft mute */
- TFA9872_BF_ST1C = 0x0db0, /*!< side tone one s complement */
- TFA9872_BF_VDDS = 0x1000, /*!< POR */
- TFA9872_BF_PLLS = 0x1010, /*!< PLL lock */
- TFA9872_BF_OTDS = 0x1020, /*!< OTP alarm */
- TFA9872_BF_OVDS = 0x1030, /*!< OVP alarm */
- TFA9872_BF_UVDS = 0x1040, /*!< UVP alarm */
- TFA9872_BF_CLKS = 0x1050, /*!< Clocks stable */
- TFA9872_BF_MTPB = 0x1060, /*!< MTP busy */
- TFA9872_BF_NOCLK = 0x1070, /*!< Lost clock */
- TFA9872_BF_SWS = 0x10a0, /*!< Amplifier engage */
- TFA9872_BF_AMPS = 0x10c0, /*!< Amplifier enable */
- TFA9872_BF_AREFS = 0x10d0, /*!< References enable */
- TFA9872_BF_ADCCR = 0x10e0, /*!< Control ADC */
- TFA9872_BF_DCIL = 0x1100, /*!< DCDC current limiting */
- TFA9872_BF_DCDCA = 0x1110, /*!< DCDC active */
- TFA9872_BF_DCOCPOK= 0x1120, /*!< DCDC OCP nmos */
- TFA9872_BF_DCHVBAT= 0x1140, /*!< DCDC level 1x */
- TFA9872_BF_DCH114= 0x1150, /*!< DCDC level 1.14x */
- TFA9872_BF_DCH107= 0x1160, /*!< DCDC level 1.07x */
- TFA9872_BF_STMUTEB= 0x1170, /*!< side tone (un)mute busy */
- TFA9872_BF_STMUTE= 0x1180, /*!< side tone mute state */
- TFA9872_BF_TDMLUTER= 0x1190, /*!< TDM LUT error */
- TFA9872_BF_TDMSTAT= 0x11a2, /*!< TDM status bits */
- TFA9872_BF_TDMERR= 0x11d0, /*!< TDM error */
- TFA9872_BF_OCPOAP= 0x1300, /*!< OCPOK pmos A */
- TFA9872_BF_OCPOAN= 0x1310, /*!< OCPOK nmos A */
- TFA9872_BF_OCPOBP= 0x1320, /*!< OCPOK pmos B */
- TFA9872_BF_OCPOBN= 0x1330, /*!< OCPOK nmos B */
- TFA9872_BF_CLIPAH= 0x1340, /*!< Clipping A to Vddp */
- TFA9872_BF_CLIPAL= 0x1350, /*!< Clipping A to gnd */
- TFA9872_BF_CLIPBH= 0x1360, /*!< Clipping B to Vddp */
- TFA9872_BF_CLIPBL= 0x1370, /*!< Clipping B to gnd */
- TFA9872_BF_OCDS = 0x1380, /*!< OCP amplifier */
- TFA9872_BF_CLIPS = 0x1390, /*!< Amplifier clipping */
- TFA9872_BF_OCPOKMC= 0x13a0, /*!< OCPOK MICVDD */
- TFA9872_BF_MANALARM= 0x13b0, /*!< Alarm state */
- TFA9872_BF_MANWAIT1= 0x13c0, /*!< Wait HW I2C settings */
- TFA9872_BF_MANMUTE= 0x13e0, /*!< Audio mute sequence */
- TFA9872_BF_MANOPER= 0x13f0, /*!< Operating state */
- TFA9872_BF_CLKOOR= 0x1420, /*!< External clock status */
- TFA9872_BF_MANSTATE= 0x1433, /*!< Device manager status */
- TFA9872_BF_DCMODE= 0x1471, /*!< DCDC mode status bits */
- TFA9872_BF_BATS = 0x1509, /*!< Battery voltage (V) */
- TFA9872_BF_TEMPS = 0x1608, /*!< IC Temperature (C) */
- TFA9872_BF_VDDPS = 0x1709, /*!< IC VDDP voltage ( 1023*VDDP/9.5 V) */
- TFA9872_BF_TDME = 0x2040, /*!< Enable interface */
- TFA9872_BF_TDMMODE= 0x2050, /*!< Slave/master */
- TFA9872_BF_TDMCLINV= 0x2060, /*!< Reception data to BCK clock */
- TFA9872_BF_TDMFSLN= 0x2073, /*!< FS length (master mode only) */
- TFA9872_BF_TDMFSPOL= 0x20b0, /*!< FS polarity */
- TFA9872_BF_TDMNBCK= 0x20c3, /*!< N-BCK's in FS */
- TFA9872_BF_TDMSLOTS= 0x2103, /*!< N-slots in Frame */
- TFA9872_BF_TDMSLLN= 0x2144, /*!< N-bits in slot */
- TFA9872_BF_TDMBRMG= 0x2194, /*!< N-bits remaining */
- TFA9872_BF_TDMDEL= 0x21e0, /*!< data delay to FS */
- TFA9872_BF_TDMADJ= 0x21f0, /*!< data adjustment */
- TFA9872_BF_TDMOOMP= 0x2201, /*!< Received audio compression */
- TFA9872_BF_TDMSSIZE= 0x2224, /*!< Sample size per slot */
- TFA9872_BF_TDMTXDFO= 0x2271, /*!< Format unused bits */
- TFA9872_BF_TDMTXUS0= 0x2291, /*!< Format unused slots DATAO */
- TFA9872_BF_TDMSPKE= 0x2300, /*!< Control audio tdm channel in 0 (spkr + dcdc) */
- TFA9872_BF_TDMDCE= 0x2310, /*!< Control audio tdm channel in 1 (dcdc) */
- TFA9872_BF_TDMCSE= 0x2330, /*!< current sense vbat temperature and vddp feedback */
- TFA9872_BF_TDMVSE= 0x2340, /*!< Voltage sense vbat temperature and vddp feedback */
- TFA9872_BF_TDMSPKS= 0x2603, /*!< tdm slot for sink 0 (speaker + dcdc) */
- TFA9872_BF_TDMDCS= 0x2643, /*!< tdm slot for sink 1 (dcdc) */
- TFA9872_BF_TDMCSS= 0x26c3, /*!< Slot Position of current sense vbat temperature and vddp feedback */
- TFA9872_BF_TDMVSS= 0x2703, /*!< Slot Position of Voltage sense vbat temperature and vddp feedback */
- TFA9872_BF_PDMSTSEL= 0x3111, /*!< Side tone input */
- TFA9872_BF_ISTVDDS= 0x4000, /*!< Status POR */
- TFA9872_BF_ISTPLLS= 0x4010, /*!< Status PLL lock */
- TFA9872_BF_ISTOTDS= 0x4020, /*!< Status OTP alarm */
- TFA9872_BF_ISTOVDS= 0x4030, /*!< Status OVP alarm */
- TFA9872_BF_ISTUVDS= 0x4040, /*!< Status UVP alarm */
- TFA9872_BF_ISTCLKS= 0x4050, /*!< Status clocks stable */
- TFA9872_BF_ISTMTPB= 0x4060, /*!< Status MTP busy */
- TFA9872_BF_ISTNOCLK= 0x4070, /*!< Status lost clock */
- TFA9872_BF_ISTSWS= 0x40a0, /*!< Status amplifier engage */
- TFA9872_BF_ISTAMPS= 0x40c0, /*!< Status amplifier enable */
- TFA9872_BF_ISTAREFS= 0x40d0, /*!< Status Ref enable */
- TFA9872_BF_ISTADCCR= 0x40e0, /*!< Status Control ADC */
- TFA9872_BF_ISTBSTCU= 0x4100, /*!< Status DCDC current limiting */
- TFA9872_BF_ISTBSTHI= 0x4110, /*!< Status DCDC active */
- TFA9872_BF_ISTBSTOC= 0x4120, /*!< Status DCDC OCP */
- TFA9872_BF_ISTBSTPKCUR= 0x4130, /*!< Status bst peakcur */
- TFA9872_BF_ISTBSTVC= 0x4140, /*!< Status DCDC level 1x */
- TFA9872_BF_ISTBST86= 0x4150, /*!< Status DCDC level 1.14x */
- TFA9872_BF_ISTBST93= 0x4160, /*!< Status DCDC level 1.07x */
- TFA9872_BF_ISTOCPR= 0x4190, /*!< Status ocp alarm */
- TFA9872_BF_ISTMWSRC= 0x41a0, /*!< Status Waits HW I2C settings */
- TFA9872_BF_ISTMWSMU= 0x41c0, /*!< Status Audio mute sequence */
- TFA9872_BF_ISTCLKOOR= 0x41f0, /*!< Status flag_clk_out_of_range */
- TFA9872_BF_ISTTDMER= 0x4200, /*!< Status tdm error */
- TFA9872_BF_ISTCLPR= 0x4220, /*!< Status clip */
- TFA9872_BF_ISTLP0= 0x4240, /*!< Status low power mode0 */
- TFA9872_BF_ISTLP1= 0x4250, /*!< Status low power mode1 */
- TFA9872_BF_ISTLA = 0x4260, /*!< Status low noise detection */
- TFA9872_BF_ISTVDDPH= 0x4270, /*!< Status VDDP greater than VBAT */
- TFA9872_BF_ICLVDDS= 0x4400, /*!< Clear POR */
- TFA9872_BF_ICLPLLS= 0x4410, /*!< Clear PLL lock */
- TFA9872_BF_ICLOTDS= 0x4420, /*!< Clear OTP alarm */
- TFA9872_BF_ICLOVDS= 0x4430, /*!< Clear OVP alarm */
- TFA9872_BF_ICLUVDS= 0x4440, /*!< Clear UVP alarm */
- TFA9872_BF_ICLCLKS= 0x4450, /*!< Clear clocks stable */
- TFA9872_BF_ICLMTPB= 0x4460, /*!< Clear mtp busy */
- TFA9872_BF_ICLNOCLK= 0x4470, /*!< Clear lost clk */
- TFA9872_BF_ICLSWS= 0x44a0, /*!< Clear amplifier engage */
- TFA9872_BF_ICLAMPS= 0x44c0, /*!< Clear enbl amp */
- TFA9872_BF_ICLAREFS= 0x44d0, /*!< Clear ref enable */
- TFA9872_BF_ICLADCCR= 0x44e0, /*!< Clear control ADC */
- TFA9872_BF_ICLBSTCU= 0x4500, /*!< Clear DCDC current limiting */
- TFA9872_BF_ICLBSTHI= 0x4510, /*!< Clear DCDC active */
- TFA9872_BF_ICLBSTOC= 0x4520, /*!< Clear DCDC OCP */
- TFA9872_BF_ICLBSTPC= 0x4530, /*!< Clear bst peakcur */
- TFA9872_BF_ICLBSTVC= 0x4540, /*!< Clear DCDC level 1x */
- TFA9872_BF_ICLBST86= 0x4550, /*!< Clear DCDC level 1.14x */
- TFA9872_BF_ICLBST93= 0x4560, /*!< Clear DCDC level 1.07x */
- TFA9872_BF_ICLOCPR= 0x4590, /*!< Clear ocp alarm */
- TFA9872_BF_ICLMWSRC= 0x45a0, /*!< Clear wait HW I2C settings */
- TFA9872_BF_ICLMWSMU= 0x45c0, /*!< Clear audio mute sequence */
- TFA9872_BF_ICLCLKOOR= 0x45f0, /*!< Clear flag_clk_out_of_range */
- TFA9872_BF_ICLTDMER= 0x4600, /*!< Clear tdm error */
- TFA9872_BF_ICLCLPR= 0x4620, /*!< Clear clip */
- TFA9872_BF_ICLLP0= 0x4640, /*!< Clear low power mode0 */
- TFA9872_BF_ICLLP1= 0x4650, /*!< Clear low power mode1 */
- TFA9872_BF_ICLLA = 0x4660, /*!< Clear low noise detection */
- TFA9872_BF_ICLVDDPH= 0x4670, /*!< Clear VDDP greater then VBAT */
- TFA9872_BF_IEVDDS= 0x4800, /*!< Enable por */
- TFA9872_BF_IEPLLS= 0x4810, /*!< Enable pll lock */
- TFA9872_BF_IEOTDS= 0x4820, /*!< Enable OTP alarm */
- TFA9872_BF_IEOVDS= 0x4830, /*!< Enable OVP alarm */
- TFA9872_BF_IEUVDS= 0x4840, /*!< Enable UVP alarm */
- TFA9872_BF_IECLKS= 0x4850, /*!< Enable clocks stable */
- TFA9872_BF_IEMTPB= 0x4860, /*!< Enable mtp busy */
- TFA9872_BF_IENOCLK= 0x4870, /*!< Enable lost clk */
- TFA9872_BF_IESWS = 0x48a0, /*!< Enable amplifier engage */
- TFA9872_BF_IEAMPS= 0x48c0, /*!< Enable enbl amp */
- TFA9872_BF_IEAREFS= 0x48d0, /*!< Enable ref enable */
- TFA9872_BF_IEADCCR= 0x48e0, /*!< Enable Control ADC */
- TFA9872_BF_IEBSTCU= 0x4900, /*!< Enable DCDC current limiting */
- TFA9872_BF_IEBSTHI= 0x4910, /*!< Enable DCDC active */
- TFA9872_BF_IEBSTOC= 0x4920, /*!< Enable DCDC OCP */
- TFA9872_BF_IEBSTPC= 0x4930, /*!< Enable bst peakcur */
- TFA9872_BF_IEBSTVC= 0x4940, /*!< Enable DCDC level 1x */
- TFA9872_BF_IEBST86= 0x4950, /*!< Enable DCDC level 1.14x */
- TFA9872_BF_IEBST93= 0x4960, /*!< Enable DCDC level 1.07x */
- TFA9872_BF_IEOCPR= 0x4990, /*!< Enable ocp alarm */
- TFA9872_BF_IEMWSRC= 0x49a0, /*!< Enable waits HW I2C settings */
- TFA9872_BF_IEMWSMU= 0x49c0, /*!< Enable man Audio mute sequence */
- TFA9872_BF_IECLKOOR= 0x49f0, /*!< Enable flag_clk_out_of_range */
- TFA9872_BF_IETDMER= 0x4a00, /*!< Enable tdm error */
- TFA9872_BF_IECLPR= 0x4a20, /*!< Enable clip */
- TFA9872_BF_IELP0 = 0x4a40, /*!< Enable low power mode0 */
- TFA9872_BF_IELP1 = 0x4a50, /*!< Enable low power mode1 */
- TFA9872_BF_IELA = 0x4a60, /*!< Enable low noise detection */
- TFA9872_BF_IEVDDPH= 0x4a70, /*!< Enable VDDP greater tehn VBAT */
- TFA9872_BF_IPOVDDS= 0x4c00, /*!< Polarity por */
- TFA9872_BF_IPOPLLS= 0x4c10, /*!< Polarity pll lock */
- TFA9872_BF_IPOOTDS= 0x4c20, /*!< Polarity OTP alarm */
- TFA9872_BF_IPOOVDS= 0x4c30, /*!< Polarity OVP alarm */
- TFA9872_BF_IPOUVDS= 0x4c40, /*!< Polarity UVP alarm */
- TFA9872_BF_IPOCLKS= 0x4c50, /*!< Polarity clocks stable */
- TFA9872_BF_IPOMTPB= 0x4c60, /*!< Polarity mtp busy */
- TFA9872_BF_IPONOCLK= 0x4c70, /*!< Polarity lost clk */
- TFA9872_BF_IPOSWS= 0x4ca0, /*!< Polarity amplifier engage */
- TFA9872_BF_IPOAMPS= 0x4cc0, /*!< Polarity enbl amp */
- TFA9872_BF_IPOAREFS= 0x4cd0, /*!< Polarity ref enable */
- TFA9872_BF_IPOADCCR= 0x4ce0, /*!< Polarity Control ADC */
- TFA9872_BF_IPOBSTCU= 0x4d00, /*!< Polarity DCDC current limiting */
- TFA9872_BF_IPOBSTHI= 0x4d10, /*!< Polarity DCDC active */
- TFA9872_BF_IPOBSTOC= 0x4d20, /*!< Polarity DCDC OCP */
- TFA9872_BF_IPOBSTPC= 0x4d30, /*!< Polarity bst peakcur */
- TFA9872_BF_IPOBSTVC= 0x4d40, /*!< Polarity DCDC level 1x */
- TFA9872_BF_IPOBST86= 0x4d50, /*!< Polarity DCDC level 1.14x */
- TFA9872_BF_IPOBST93= 0x4d60, /*!< Polarity DCDC level 1.07x */
- TFA9872_BF_IPOOCPR= 0x4d90, /*!< Polarity ocp alarm */
- TFA9872_BF_IPOMWSRC= 0x4da0, /*!< Polarity waits HW I2C settings */
- TFA9872_BF_IPOMWSMU= 0x4dc0, /*!< Polarity man audio mute sequence */
- TFA9872_BF_IPCLKOOR= 0x4df0, /*!< Polarity flag_clk_out_of_range */
- TFA9872_BF_IPOTDMER= 0x4e00, /*!< Polarity tdm error */
- TFA9872_BF_IPOCLPR= 0x4e20, /*!< Polarity clip right */
- TFA9872_BF_IPOLP0= 0x4e40, /*!< Polarity low power mode0 */
- TFA9872_BF_IPOLP1= 0x4e50, /*!< Polarity low power mode1 */
- TFA9872_BF_IPOLA = 0x4e60, /*!< Polarity low noise mode */
- TFA9872_BF_IPOVDDPH= 0x4e70, /*!< Polarity VDDP greater than VBAT */
- TFA9872_BF_BSSCR = 0x5001, /*!< Battery Safeguard attack time */
- TFA9872_BF_BSST = 0x5023, /*!< Battery Safeguard threshold voltage level */
- TFA9872_BF_BSSRL = 0x5061, /*!< Battery Safeguard maximum reduction */
- TFA9872_BF_BSSR = 0x50e0, /*!< Battery voltage read out */
- TFA9872_BF_BSSBY = 0x50f0, /*!< Bypass battery safeguard */
- TFA9872_BF_BSSS = 0x5100, /*!< Vbat prot steepness */
- TFA9872_BF_INTSMUTE= 0x5110, /*!< Soft mute HW */
- TFA9872_BF_HPFBYP= 0x5150, /*!< Bypass HPF */
- TFA9872_BF_DPSA = 0x5170, /*!< Enable DPSA */
- TFA9872_BF_CLIPCTRL= 0x5222, /*!< Clip control setting */
- TFA9872_BF_AMPGAIN= 0x5257, /*!< Amplifier gain */
- TFA9872_BF_SLOPEE= 0x52d0, /*!< Enables slope control */
- TFA9872_BF_SLOPESET= 0x52e0, /*!< Slope speed setting (bin. coded) */
- TFA9872_BF_PGAGAIN= 0x6081, /*!< PGA gain selection */
- TFA9872_BF_PGALPE= 0x60b0, /*!< Lowpass enable */
- TFA9872_BF_LPM0BYP= 0x6110, /*!< bypass low power idle mode */
- TFA9872_BF_TDMDCG= 0x6123, /*!< Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE) */
- TFA9872_BF_TDMSPKG= 0x6163, /*!< Total gain depending on INPLEV setting (channel 0) */
- TFA9872_BF_STIDLEEN= 0x61b0, /*!< enable idle feature for channel 1 */
- TFA9872_BF_LNMODE= 0x62e1, /*!< ctrl select mode */
- TFA9872_BF_LPM1MODE= 0x64e1, /*!< low power mode control */
- TFA9872_BF_LPM1DIS= 0x65c0, /*!< low power mode1 detector control */
- TFA9872_BF_TDMSRCMAP= 0x6801, /*!< tdm source mapping */
- TFA9872_BF_TDMSRCAS= 0x6821, /*!< Sensed value A */
- TFA9872_BF_TDMSRCBS= 0x6841, /*!< Sensed value B */
- TFA9872_BF_ANCSEL= 0x6881, /*!< anc input */
- TFA9872_BF_ANC1C = 0x68a0, /*!< ANC one s complement */
- TFA9872_BF_SAMMODE= 0x6901, /*!< sam enable */
- TFA9872_BF_SAMSEL= 0x6920, /*!< sam source */
- TFA9872_BF_PDMOSELH= 0x6931, /*!< pdm out value when pdm_clk is higth */
- TFA9872_BF_PDMOSELL= 0x6951, /*!< pdm out value when pdm_clk is low */
- TFA9872_BF_SAMOSEL= 0x6970, /*!< ram output on mode sam and audio */
- TFA9872_BF_LP0 = 0x6e00, /*!< low power mode 0 detection */
- TFA9872_BF_LP1 = 0x6e10, /*!< low power mode 1 detection */
- TFA9872_BF_LA = 0x6e20, /*!< low amplitude detection */
- TFA9872_BF_VDDPH = 0x6e30, /*!< vddp greater than vbat */
- TFA9872_BF_DELCURCOMP= 0x6f02, /*!< delay to allign compensation signal with current sense signal */
- TFA9872_BF_SIGCURCOMP= 0x6f40, /*!< polarity of compensation for current sense */
- TFA9872_BF_ENCURCOMP= 0x6f50, /*!< enable current sense compensation */
- TFA9872_BF_SELCLPPWM= 0x6f60, /*!< Select pwm clip flag */
- TFA9872_BF_LVLCLPPWM= 0x6f72, /*!< set the amount of pwm pulse that may be skipped before clip-flag is triggered */
- TFA9872_BF_DCVOS = 0x7002, /*!< Second boost voltage level */
- TFA9872_BF_DCMCC = 0x7033, /*!< Max coil current */
- TFA9872_BF_DCCV = 0x7071, /*!< Slope compensation current, represents LxF (inductance x frequency) value */
- TFA9872_BF_DCIE = 0x7090, /*!< Adaptive boost mode */
- TFA9872_BF_DCSR = 0x70a0, /*!< Soft ramp up/down */
- TFA9872_BF_DCDIS = 0x70e0, /*!< DCDC on/off */
- TFA9872_BF_DCPWM = 0x70f0, /*!< DCDC PWM only mode */
- TFA9872_BF_DCVOF = 0x7402, /*!< 1st boost voltage level */
- TFA9872_BF_DCTRACK= 0x7430, /*!< Boost algorithm selection, effective only when boost_intelligent is set to 1 */
- TFA9872_BF_DCTRIP= 0x7444, /*!< 1st Adaptive boost trip levels, effective only when DCIE is set to 1 */
- TFA9872_BF_DCHOLD= 0x7494, /*!< Hold time for DCDC booster, effective only when boost_intelligent is set to 1 */
- TFA9872_BF_DCTRIP2= 0x7534, /*!< 2nd Adaptive boost trip levels, effective only when DCIE is set to 1 */
- TFA9872_BF_DCTRIPT= 0x7584, /*!< Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1 */
- TFA9872_BF_MTPK = 0xa107, /*!< MTP KEY2 register */
- TFA9872_BF_KEY1LOCKED= 0xa200, /*!< Indicates KEY1 is locked */
- TFA9872_BF_KEY2LOCKED= 0xa210, /*!< Indicates KEY2 is locked */
- TFA9872_BF_CMTPI = 0xa350, /*!< Start copying all the data from mtp to I2C mtp registers */
- TFA9872_BF_CIMTP = 0xa360, /*!< Start copying data from I2C mtp registers to mtp */
- TFA9872_BF_MTPRDMSB= 0xa50f, /*!< MSB word of MTP manual read data */
- TFA9872_BF_MTPRDLSB= 0xa60f, /*!< LSB word of MTP manual read data */
- TFA9872_BF_EXTTS = 0xb108, /*!< External temperature (C) */
- TFA9872_BF_TROS = 0xb190, /*!< Select temp Speaker calibration */
- TFA9872_BF_SWPROFIL= 0xee0f, /*!< Software profile data */
- TFA9872_BF_SWVSTEP= 0xef0f, /*!< Software vstep information */
- TFA9872_BF_MTPOTC= 0xf000, /*!< Calibration schedule */
- TFA9872_BF_MTPEX = 0xf010, /*!< Calibration Ron executed */
- TFA9872_BF_DCMCCAPI= 0xf020, /*!< Calibration current limit DCDC */
- TFA9872_BF_DCMCCSB= 0xf030, /*!< Sign bit for delta calibration current limit DCDC */
- TFA9872_BF_USERDEF= 0xf042, /*!< Calibration delta current limit DCDC */
- TFA9872_BF_CUSTINFO= 0xf078, /*!< Reserved space for allowing customer to store speaker information */
- TFA9872_BF_R25C = 0xf50f, /*!< Ron resistance of speaker coil */
-} nxpTfa9872BfEnumList_t;
-#define TFA9872_NAMETABLE static tfaBfName_t Tfa9872DatasheetNames[]= {\
- { 0x0, "PWDN"}, /* Powerdown selection , */\
- { 0x10, "I2CR"}, /* I2C Reset - Auto clear , */\
- { 0x30, "AMPE"}, /* Activate Amplifier , */\
- { 0x40, "DCA"}, /* Activate DC-to-DC converter , */\
- { 0x71, "INTP"}, /* Interrupt config , */\
- { 0xb0, "BYPOCP"}, /* Bypass OCP , */\
- { 0xc0, "TSTOCP"}, /* OCP testing control , */\
- { 0x120, "MANSCONF"}, /* I2C configured , */\
- { 0x140, "MANAOOSC"}, /* Internal osc off at PWDN , */\
- { 0x1d0, "MUTETO"}, /* Time out SB mute sequence , */\
- { 0x1e0, "RCVNS"}, /* Noise shaper selection , */\
- { 0x203, "AUDFS"}, /* Sample rate (fs) , */\
- { 0x240, "INPLEV"}, /* TDM output attenuation , */\
- { 0x255, "FRACTDEL"}, /* V/I Fractional delay , */\
- { 0x2b0, "BYPHVBF"}, /* Bypass HVBAT filter , */\
- { 0x30f, "REV"}, /* Revision info , */\
- { 0x401, "REFCKEXT"}, /* PLL external ref clock , */\
- { 0x420, "REFCKSEL"}, /* PLL internal ref clock , */\
- { 0x510, "SSE"}, /* Enable speaker path , */\
- { 0x530, "VSE"}, /* Voltage sense , */\
- { 0x550, "CSE"}, /* Current sense , */\
- { 0x560, "SSPDME"}, /* Sub-system PDM , */\
- { 0x580, "PGAE"}, /* Enable PGA chop clock , */\
- { 0x590, "SSTDME"}, /* Sub-system TDM , */\
- { 0x5a0, "SSPBSTE"}, /* Sub-system boost , */\
- { 0x5b0, "SSADCE"}, /* Sub-system ADC , */\
- { 0x5c0, "SSFAIME"}, /* Sub-system FAIM , */\
- { 0xd18, "STGAIN"}, /* Side tone gain , */\
- { 0xda0, "STSMUTE"}, /* Side tone soft mute , */\
- { 0xdb0, "ST1C"}, /* side tone one s complement , */\
- { 0x1000, "VDDS"}, /* POR , */\
- { 0x1010, "PLLS"}, /* PLL lock , */\
- { 0x1020, "OTDS"}, /* OTP alarm , */\
- { 0x1030, "OVDS"}, /* OVP alarm , */\
- { 0x1040, "UVDS"}, /* UVP alarm , */\
- { 0x1050, "CLKS"}, /* Clocks stable , */\
- { 0x1060, "MTPB"}, /* MTP busy , */\
- { 0x1070, "NOCLK"}, /* Lost clock , */\
- { 0x10a0, "SWS"}, /* Amplifier engage , */\
- { 0x10c0, "AMPS"}, /* Amplifier enable , */\
- { 0x10d0, "AREFS"}, /* References enable , */\
- { 0x10e0, "ADCCR"}, /* Control ADC , */\
- { 0x1100, "DCIL"}, /* DCDC current limiting , */\
- { 0x1110, "DCDCA"}, /* DCDC active , */\
- { 0x1120, "DCOCPOK"}, /* DCDC OCP nmos , */\
- { 0x1140, "DCHVBAT"}, /* DCDC level 1x , */\
- { 0x1150, "DCH114"}, /* DCDC level 1.14x , */\
- { 0x1160, "DCH107"}, /* DCDC level 1.07x , */\
- { 0x1170, "STMUTEB"}, /* side tone (un)mute busy , */\
- { 0x1180, "STMUTE"}, /* side tone mute state , */\
- { 0x1190, "TDMLUTER"}, /* TDM LUT error , */\
- { 0x11a2, "TDMSTAT"}, /* TDM status bits , */\
- { 0x11d0, "TDMERR"}, /* TDM error , */\
- { 0x1300, "OCPOAP"}, /* OCPOK pmos A , */\
- { 0x1310, "OCPOAN"}, /* OCPOK nmos A , */\
- { 0x1320, "OCPOBP"}, /* OCPOK pmos B , */\
- { 0x1330, "OCPOBN"}, /* OCPOK nmos B , */\
- { 0x1340, "CLIPAH"}, /* Clipping A to Vddp , */\
- { 0x1350, "CLIPAL"}, /* Clipping A to gnd , */\
- { 0x1360, "CLIPBH"}, /* Clipping B to Vddp , */\
- { 0x1370, "CLIPBL"}, /* Clipping B to gnd , */\
- { 0x1380, "OCDS"}, /* OCP amplifier , */\
- { 0x1390, "CLIPS"}, /* Amplifier clipping , */\
- { 0x13a0, "OCPOKMC"}, /* OCPOK MICVDD , */\
- { 0x13b0, "MANALARM"}, /* Alarm state , */\
- { 0x13c0, "MANWAIT1"}, /* Wait HW I2C settings , */\
- { 0x13e0, "MANMUTE"}, /* Audio mute sequence , */\
- { 0x13f0, "MANOPER"}, /* Operating state , */\
- { 0x1420, "CLKOOR"}, /* External clock status , */\
- { 0x1433, "MANSTATE"}, /* Device manager status , */\
- { 0x1471, "DCMODE"}, /* DCDC mode status bits , */\
- { 0x1509, "BATS"}, /* Battery voltage (V) , */\
- { 0x1608, "TEMPS"}, /* IC Temperature (C) , */\
- { 0x1709, "VDDPS"}, /* IC VDDP voltage ( 1023*VDDP/9.5 V) , */\
- { 0x2040, "TDME"}, /* Enable interface , */\
- { 0x2050, "TDMMODE"}, /* Slave/master , */\
- { 0x2060, "TDMCLINV"}, /* Reception data to BCK clock , */\
- { 0x2073, "TDMFSLN"}, /* FS length (master mode only) , */\
- { 0x20b0, "TDMFSPOL"}, /* FS polarity , */\
- { 0x20c3, "TDMNBCK"}, /* N-BCK's in FS , */\
- { 0x2103, "TDMSLOTS"}, /* N-slots in Frame , */\
- { 0x2144, "TDMSLLN"}, /* N-bits in slot , */\
- { 0x2194, "TDMBRMG"}, /* N-bits remaining , */\
- { 0x21e0, "TDMDEL"}, /* data delay to FS , */\
- { 0x21f0, "TDMADJ"}, /* data adjustment , */\
- { 0x2201, "TDMOOMP"}, /* Received audio compression , */\
- { 0x2224, "TDMSSIZE"}, /* Sample size per slot , */\
- { 0x2271, "TDMTXDFO"}, /* Format unused bits , */\
- { 0x2291, "TDMTXUS0"}, /* Format unused slots DATAO , */\
- { 0x2300, "TDMSPKE"}, /* Control audio tdm channel in 0 (spkr + dcdc) , */\
- { 0x2310, "TDMDCE"}, /* Control audio tdm channel in 1 (dcdc) , */\
- { 0x2330, "TDMCSE"}, /* current sense vbat temperature and vddp feedback , */\
- { 0x2340, "TDMVSE"}, /* Voltage sense vbat temperature and vddp feedback , */\
- { 0x2603, "TDMSPKS"}, /* tdm slot for sink 0 (speaker + dcdc) , */\
- { 0x2643, "TDMDCS"}, /* tdm slot for sink 1 (dcdc) , */\
- { 0x26c3, "TDMCSS"}, /* Slot Position of current sense vbat temperature and vddp feedback, */\
- { 0x2703, "TDMVSS"}, /* Slot Position of Voltage sense vbat temperature and vddp feedback, */\
- { 0x3111, "PDMSTSEL"}, /* Side tone input , */\
- { 0x4000, "ISTVDDS"}, /* Status POR , */\
- { 0x4010, "ISTPLLS"}, /* Status PLL lock , */\
- { 0x4020, "ISTOTDS"}, /* Status OTP alarm , */\
- { 0x4030, "ISTOVDS"}, /* Status OVP alarm , */\
- { 0x4040, "ISTUVDS"}, /* Status UVP alarm , */\
- { 0x4050, "ISTCLKS"}, /* Status clocks stable , */\
- { 0x4060, "ISTMTPB"}, /* Status MTP busy , */\
- { 0x4070, "ISTNOCLK"}, /* Status lost clock , */\
- { 0x40a0, "ISTSWS"}, /* Status amplifier engage , */\
- { 0x40c0, "ISTAMPS"}, /* Status amplifier enable , */\
- { 0x40d0, "ISTAREFS"}, /* Status Ref enable , */\
- { 0x40e0, "ISTADCCR"}, /* Status Control ADC , */\
- { 0x4100, "ISTBSTCU"}, /* Status DCDC current limiting , */\
- { 0x4110, "ISTBSTHI"}, /* Status DCDC active , */\
- { 0x4120, "ISTBSTOC"}, /* Status DCDC OCP , */\
- { 0x4130, "ISTBSTPKCUR"}, /* Status bst peakcur , */\
- { 0x4140, "ISTBSTVC"}, /* Status DCDC level 1x , */\
- { 0x4150, "ISTBST86"}, /* Status DCDC level 1.14x , */\
- { 0x4160, "ISTBST93"}, /* Status DCDC level 1.07x , */\
- { 0x4190, "ISTOCPR"}, /* Status ocp alarm , */\
- { 0x41a0, "ISTMWSRC"}, /* Status Waits HW I2C settings , */\
- { 0x41c0, "ISTMWSMU"}, /* Status Audio mute sequence , */\
- { 0x41f0, "ISTCLKOOR"}, /* Status flag_clk_out_of_range , */\
- { 0x4200, "ISTTDMER"}, /* Status tdm error , */\
- { 0x4220, "ISTCLPR"}, /* Status clip , */\
- { 0x4240, "ISTLP0"}, /* Status low power mode0 , */\
- { 0x4250, "ISTLP1"}, /* Status low power mode1 , */\
- { 0x4260, "ISTLA"}, /* Status low noise detection , */\
- { 0x4270, "ISTVDDPH"}, /* Status VDDP greater than VBAT , */\
- { 0x4400, "ICLVDDS"}, /* Clear POR , */\
- { 0x4410, "ICLPLLS"}, /* Clear PLL lock , */\
- { 0x4420, "ICLOTDS"}, /* Clear OTP alarm , */\
- { 0x4430, "ICLOVDS"}, /* Clear OVP alarm , */\
- { 0x4440, "ICLUVDS"}, /* Clear UVP alarm , */\
- { 0x4450, "ICLCLKS"}, /* Clear clocks stable , */\
- { 0x4460, "ICLMTPB"}, /* Clear mtp busy , */\
- { 0x4470, "ICLNOCLK"}, /* Clear lost clk , */\
- { 0x44a0, "ICLSWS"}, /* Clear amplifier engage , */\
- { 0x44c0, "ICLAMPS"}, /* Clear enbl amp , */\
- { 0x44d0, "ICLAREFS"}, /* Clear ref enable , */\
- { 0x44e0, "ICLADCCR"}, /* Clear control ADC , */\
- { 0x4500, "ICLBSTCU"}, /* Clear DCDC current limiting , */\
- { 0x4510, "ICLBSTHI"}, /* Clear DCDC active , */\
- { 0x4520, "ICLBSTOC"}, /* Clear DCDC OCP , */\
- { 0x4530, "ICLBSTPC"}, /* Clear bst peakcur , */\
- { 0x4540, "ICLBSTVC"}, /* Clear DCDC level 1x , */\
- { 0x4550, "ICLBST86"}, /* Clear DCDC level 1.14x , */\
- { 0x4560, "ICLBST93"}, /* Clear DCDC level 1.07x , */\
- { 0x4590, "ICLOCPR"}, /* Clear ocp alarm , */\
- { 0x45a0, "ICLMWSRC"}, /* Clear wait HW I2C settings , */\
- { 0x45c0, "ICLMWSMU"}, /* Clear audio mute sequence , */\
- { 0x45f0, "ICLCLKOOR"}, /* Clear flag_clk_out_of_range , */\
- { 0x4600, "ICLTDMER"}, /* Clear tdm error , */\
- { 0x4620, "ICLCLPR"}, /* Clear clip , */\
- { 0x4640, "ICLLP0"}, /* Clear low power mode0 , */\
- { 0x4650, "ICLLP1"}, /* Clear low power mode1 , */\
- { 0x4660, "ICLLA"}, /* Clear low noise detection , */\
- { 0x4670, "ICLVDDPH"}, /* Clear VDDP greater then VBAT , */\
- { 0x4800, "IEVDDS"}, /* Enable por , */\
- { 0x4810, "IEPLLS"}, /* Enable pll lock , */\
- { 0x4820, "IEOTDS"}, /* Enable OTP alarm , */\
- { 0x4830, "IEOVDS"}, /* Enable OVP alarm , */\
- { 0x4840, "IEUVDS"}, /* Enable UVP alarm , */\
- { 0x4850, "IECLKS"}, /* Enable clocks stable , */\
- { 0x4860, "IEMTPB"}, /* Enable mtp busy , */\
- { 0x4870, "IENOCLK"}, /* Enable lost clk , */\
- { 0x48a0, "IESWS"}, /* Enable amplifier engage , */\
- { 0x48c0, "IEAMPS"}, /* Enable enbl amp , */\
- { 0x48d0, "IEAREFS"}, /* Enable ref enable , */\
- { 0x48e0, "IEADCCR"}, /* Enable Control ADC , */\
- { 0x4900, "IEBSTCU"}, /* Enable DCDC current limiting , */\
- { 0x4910, "IEBSTHI"}, /* Enable DCDC active , */\
- { 0x4920, "IEBSTOC"}, /* Enable DCDC OCP , */\
- { 0x4930, "IEBSTPC"}, /* Enable bst peakcur , */\
- { 0x4940, "IEBSTVC"}, /* Enable DCDC level 1x , */\
- { 0x4950, "IEBST86"}, /* Enable DCDC level 1.14x , */\
- { 0x4960, "IEBST93"}, /* Enable DCDC level 1.07x , */\
- { 0x4990, "IEOCPR"}, /* Enable ocp alarm , */\
- { 0x49a0, "IEMWSRC"}, /* Enable waits HW I2C settings , */\
- { 0x49c0, "IEMWSMU"}, /* Enable man Audio mute sequence , */\
- { 0x49f0, "IECLKOOR"}, /* Enable flag_clk_out_of_range , */\
- { 0x4a00, "IETDMER"}, /* Enable tdm error , */\
- { 0x4a20, "IECLPR"}, /* Enable clip , */\
- { 0x4a40, "IELP0"}, /* Enable low power mode0 , */\
- { 0x4a50, "IELP1"}, /* Enable low power mode1 , */\
- { 0x4a60, "IELA"}, /* Enable low noise detection , */\
- { 0x4a70, "IEVDDPH"}, /* Enable VDDP greater tehn VBAT , */\
- { 0x4c00, "IPOVDDS"}, /* Polarity por , */\
- { 0x4c10, "IPOPLLS"}, /* Polarity pll lock , */\
- { 0x4c20, "IPOOTDS"}, /* Polarity OTP alarm , */\
- { 0x4c30, "IPOOVDS"}, /* Polarity OVP alarm , */\
- { 0x4c40, "IPOUVDS"}, /* Polarity UVP alarm , */\
- { 0x4c50, "IPOCLKS"}, /* Polarity clocks stable , */\
- { 0x4c60, "IPOMTPB"}, /* Polarity mtp busy , */\
- { 0x4c70, "IPONOCLK"}, /* Polarity lost clk , */\
- { 0x4ca0, "IPOSWS"}, /* Polarity amplifier engage , */\
- { 0x4cc0, "IPOAMPS"}, /* Polarity enbl amp , */\
- { 0x4cd0, "IPOAREFS"}, /* Polarity ref enable , */\
- { 0x4ce0, "IPOADCCR"}, /* Polarity Control ADC , */\
- { 0x4d00, "IPOBSTCU"}, /* Polarity DCDC current limiting , */\
- { 0x4d10, "IPOBSTHI"}, /* Polarity DCDC active , */\
- { 0x4d20, "IPOBSTOC"}, /* Polarity DCDC OCP , */\
- { 0x4d30, "IPOBSTPC"}, /* Polarity bst peakcur , */\
- { 0x4d40, "IPOBSTVC"}, /* Polarity DCDC level 1x , */\
- { 0x4d50, "IPOBST86"}, /* Polarity DCDC level 1.14x , */\
- { 0x4d60, "IPOBST93"}, /* Polarity DCDC level 1.07x , */\
- { 0x4d90, "IPOOCPR"}, /* Polarity ocp alarm , */\
- { 0x4da0, "IPOMWSRC"}, /* Polarity waits HW I2C settings , */\
- { 0x4dc0, "IPOMWSMU"}, /* Polarity man audio mute sequence , */\
- { 0x4df0, "IPCLKOOR"}, /* Polarity flag_clk_out_of_range , */\
- { 0x4e00, "IPOTDMER"}, /* Polarity tdm error , */\
- { 0x4e20, "IPOCLPR"}, /* Polarity clip right , */\
- { 0x4e40, "IPOLP0"}, /* Polarity low power mode0 , */\
- { 0x4e50, "IPOLP1"}, /* Polarity low power mode1 , */\
- { 0x4e60, "IPOLA"}, /* Polarity low noise mode , */\
- { 0x4e70, "IPOVDDPH"}, /* Polarity VDDP greater than VBAT , */\
- { 0x5001, "BSSCR"}, /* Battery Safeguard attack time , */\
- { 0x5023, "BSST"}, /* Battery Safeguard threshold voltage level , */\
- { 0x5061, "BSSRL"}, /* Battery Safeguard maximum reduction , */\
- { 0x50e0, "BSSR"}, /* Battery voltage read out , */\
- { 0x50f0, "BSSBY"}, /* Bypass battery safeguard , */\
- { 0x5100, "BSSS"}, /* Vbat prot steepness , */\
- { 0x5110, "INTSMUTE"}, /* Soft mute HW , */\
- { 0x5150, "HPFBYP"}, /* Bypass HPF , */\
- { 0x5170, "DPSA"}, /* Enable DPSA , */\
- { 0x5222, "CLIPCTRL"}, /* Clip control setting , */\
- { 0x5257, "AMPGAIN"}, /* Amplifier gain , */\
- { 0x52d0, "SLOPEE"}, /* Enables slope control , */\
- { 0x52e0, "SLOPESET"}, /* Slope speed setting (bin. coded) , */\
- { 0x6081, "PGAGAIN"}, /* PGA gain selection , */\
- { 0x60b0, "PGALPE"}, /* Lowpass enable , */\
- { 0x6110, "LPM0BYP"}, /* bypass low power idle mode , */\
- { 0x6123, "TDMDCG"}, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */\
- { 0x6163, "TDMSPKG"}, /* Total gain depending on INPLEV setting (channel 0), */\
- { 0x61b0, "STIDLEEN"}, /* enable idle feature for channel 1 , */\
- { 0x62e1, "LNMODE"}, /* ctrl select mode , */\
- { 0x64e1, "LPM1MODE"}, /* low power mode control , */\
- { 0x65c0, "LPM1DIS"}, /* low power mode1 detector control , */\
- { 0x6801, "TDMSRCMAP"}, /* tdm source mapping , */\
- { 0x6821, "TDMSRCAS"}, /* Sensed value A , */\
- { 0x6841, "TDMSRCBS"}, /* Sensed value B , */\
- { 0x6881, "ANCSEL"}, /* anc input , */\
- { 0x68a0, "ANC1C"}, /* ANC one s complement , */\
- { 0x6901, "SAMMODE"}, /* sam enable , */\
- { 0x6920, "SAMSEL"}, /* sam source , */\
- { 0x6931, "PDMOSELH"}, /* pdm out value when pdm_clk is higth , */\
- { 0x6951, "PDMOSELL"}, /* pdm out value when pdm_clk is low , */\
- { 0x6970, "SAMOSEL"}, /* ram output on mode sam and audio , */\
- { 0x6e00, "LP0"}, /* low power mode 0 detection , */\
- { 0x6e10, "LP1"}, /* low power mode 1 detection , */\
- { 0x6e20, "LA"}, /* low amplitude detection , */\
- { 0x6e30, "VDDPH"}, /* vddp greater than vbat , */\
- { 0x6f02, "DELCURCOMP"}, /* delay to allign compensation signal with current sense signal, */\
- { 0x6f40, "SIGCURCOMP"}, /* polarity of compensation for current sense , */\
- { 0x6f50, "ENCURCOMP"}, /* enable current sense compensation , */\
- { 0x6f60, "SELCLPPWM"}, /* Select pwm clip flag , */\
- { 0x6f72, "LVLCLPPWM"}, /* set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
- { 0x7002, "DCVOS"}, /* Second boost voltage level , */\
- { 0x7033, "DCMCC"}, /* Max coil current , */\
- { 0x7071, "DCCV"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
- { 0x7090, "DCIE"}, /* Adaptive boost mode , */\
- { 0x70a0, "DCSR"}, /* Soft ramp up/down , */\
- { 0x70e0, "DCDIS"}, /* DCDC on/off , */\
- { 0x70f0, "DCPWM"}, /* DCDC PWM only mode , */\
- { 0x7402, "DCVOF"}, /* 1st boost voltage level , */\
- { 0x7430, "DCTRACK"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
- { 0x7444, "DCTRIP"}, /* 1st Adaptive boost trip levels, effective only when DCIE is set to 1, */\
- { 0x7494, "DCHOLD"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
- { 0x7534, "DCTRIP2"}, /* 2nd Adaptive boost trip levels, effective only when DCIE is set to 1, */\
- { 0x7584, "DCTRIPT"}, /* Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
- { 0xa107, "MTPK"}, /* MTP KEY2 register , */\
- { 0xa200, "KEY1LOCKED"}, /* Indicates KEY1 is locked , */\
- { 0xa210, "KEY2LOCKED"}, /* Indicates KEY2 is locked , */\
- { 0xa350, "CMTPI"}, /* Start copying all the data from mtp to I2C mtp registers, */\
- { 0xa360, "CIMTP"}, /* Start copying data from I2C mtp registers to mtp , */\
- { 0xa50f, "MTPRDMSB"}, /* MSB word of MTP manual read data , */\
- { 0xa60f, "MTPRDLSB"}, /* LSB word of MTP manual read data , */\
- { 0xb108, "EXTTS"}, /* External temperature (C) , */\
- { 0xb190, "TROS"}, /* Select temp Speaker calibration , */\
- { 0xee0f, "SWPROFIL"}, /* Software profile data , */\
- { 0xef0f, "SWVSTEP"}, /* Software vstep information , */\
- { 0xf000, "MTPOTC"}, /* Calibration schedule , */\
- { 0xf010, "MTPEX"}, /* Calibration Ron executed , */\
- { 0xf020, "DCMCCAPI"}, /* Calibration current limit DCDC , */\
- { 0xf030, "DCMCCSB"}, /* Sign bit for delta calibration current limit DCDC , */\
- { 0xf042, "USERDEF"}, /* Calibration delta current limit DCDC , */\
- { 0xf078, "CUSTINFO"}, /* Reserved space for allowing customer to store speaker information, */\
- { 0xf50f, "R25C"}, /* Ron resistance of speaker coil , */\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-
-#define TFA9872_BITNAMETABLE static tfaBfName_t Tfa9872BitNames[]= {\
- { 0x0, "powerdown"}, /* Powerdown selection , */\
- { 0x10, "reset"}, /* I2C Reset - Auto clear , */\
- { 0x30, "enbl_amplifier"}, /* Activate Amplifier , */\
- { 0x40, "enbl_boost"}, /* Activate DC-to-DC converter , */\
- { 0x71, "int_pad_io"}, /* Interrupt config , */\
- { 0xb0, "bypass_ocp"}, /* Bypass OCP , */\
- { 0xc0, "test_ocp"}, /* OCP testing control , */\
- { 0x120, "src_set_configured"}, /* I2C configured , */\
- { 0x140, "enbl_osc1m_auto_off"}, /* Internal osc off at PWDN , */\
- { 0x1d0, "disable_mute_time_out"}, /* Time out SB mute sequence , */\
- { 0x203, "audio_fs"}, /* Sample rate (fs) , */\
- { 0x240, "input_level"}, /* TDM output attenuation , */\
- { 0x255, "cs_frac_delay"}, /* V/I Fractional delay , */\
- { 0x2b0, "bypass_hvbat_filter"}, /* Bypass HVBAT filter , */\
- { 0x2d0, "sel_hysteresis"}, /* Select hysteresis for clock range detector , */\
- { 0x30f, "device_rev"}, /* Revision info , */\
- { 0x401, "pll_clkin_sel"}, /* PLL external ref clock , */\
- { 0x420, "pll_clkin_sel_osc"}, /* PLL internal ref clock , */\
- { 0x510, "enbl_spkr_ss"}, /* Enable speaker path , */\
- { 0x530, "enbl_volsense"}, /* Voltage sense , */\
- { 0x550, "enbl_cursense"}, /* Current sense , */\
- { 0x560, "enbl_pdm_ss"}, /* Sub-system PDM , */\
- { 0x580, "enbl_pga_chop"}, /* Enable PGA chop clock , */\
- { 0x590, "enbl_tdm_ss"}, /* Sub-system TDM , */\
- { 0x5a0, "enbl_bst_ss"}, /* Sub-system boost , */\
- { 0x5b0, "enbl_adc_ss"}, /* Sub-system ADC , */\
- { 0x5c0, "enbl_faim_ss"}, /* Sub-system FAIM , */\
- { 0xd18, "side_tone_gain"}, /* Side tone gain , */\
- { 0xda0, "mute_side_tone"}, /* Side tone soft mute , */\
- { 0xdb0, "side_tone_1scomplement"}, /* side tone one s complement , */\
- { 0xe07, "ctrl_digtoana"}, /* Spare control from digital to analog , */\
- { 0xf0f, "hidden_code"}, /* 5A6Bh, 23147d to access registers (default for engineering), */\
- { 0x1000, "flag_por"}, /* POR , */\
- { 0x1010, "flag_pll_lock"}, /* PLL lock , */\
- { 0x1020, "flag_otpok"}, /* OTP alarm , */\
- { 0x1030, "flag_ovpok"}, /* OVP alarm , */\
- { 0x1040, "flag_uvpok"}, /* UVP alarm , */\
- { 0x1050, "flag_clocks_stable"}, /* Clocks stable , */\
- { 0x1060, "flag_mtp_busy"}, /* MTP busy , */\
- { 0x1070, "flag_lost_clk"}, /* Lost clock , */\
- { 0x10a0, "flag_engage"}, /* Amplifier engage , */\
- { 0x10c0, "flag_enbl_amp"}, /* Amplifier enable , */\
- { 0x10d0, "flag_enbl_ref"}, /* References enable , */\
- { 0x10e0, "flag_adc10_ready"}, /* Control ADC , */\
- { 0x1100, "flag_bst_bstcur"}, /* DCDC current limiting , */\
- { 0x1110, "flag_bst_hiz"}, /* DCDC active , */\
- { 0x1120, "flag_bst_ocpok"}, /* DCDC OCP nmos , */\
- { 0x1130, "flag_bst_peakcur"}, /* Indicates current is max in DC-to-DC converter , */\
- { 0x1140, "flag_bst_voutcomp"}, /* DCDC level 1x , */\
- { 0x1150, "flag_bst_voutcomp86"}, /* DCDC level 1.14x , */\
- { 0x1160, "flag_bst_voutcomp93"}, /* DCDC level 1.07x , */\
- { 0x1170, "flag_soft_mute_busy"}, /* side tone (un)mute busy , */\
- { 0x1180, "flag_soft_mute_state"}, /* side tone mute state , */\
- { 0x1190, "flag_tdm_lut_error"}, /* TDM LUT error , */\
- { 0x11a2, "flag_tdm_status"}, /* TDM status bits , */\
- { 0x11d0, "flag_tdm_error"}, /* TDM error , */\
- { 0x1300, "flag_ocpokap"}, /* OCPOK pmos A , */\
- { 0x1310, "flag_ocpokan"}, /* OCPOK nmos A , */\
- { 0x1320, "flag_ocpokbp"}, /* OCPOK pmos B , */\
- { 0x1330, "flag_ocpokbn"}, /* OCPOK nmos B , */\
- { 0x1340, "flag_clipa_high"}, /* Clipping A to Vddp , */\
- { 0x1350, "flag_clipa_low"}, /* Clipping A to gnd , */\
- { 0x1360, "flag_clipb_high"}, /* Clipping B to Vddp , */\
- { 0x1370, "flag_clipb_low"}, /* Clipping B to gnd , */\
- { 0x1380, "flag_ocp_alarm"}, /* OCP amplifier , */\
- { 0x1390, "flag_clip"}, /* Amplifier clipping , */\
- { 0x13b0, "flag_man_alarm_state"}, /* Alarm state , */\
- { 0x13c0, "flag_man_wait_src_settings"}, /* Wait HW I2C settings , */\
- { 0x13e0, "flag_man_start_mute_audio"}, /* Audio mute sequence , */\
- { 0x13f0, "flag_man_operating_state"}, /* Operating state , */\
- { 0x1420, "flag_clk_out_of_range"}, /* External clock status , */\
- { 0x1433, "man_state"}, /* Device manager status , */\
- { 0x1471, "status_bst_mode"}, /* DCDC mode status bits , */\
- { 0x1509, "bat_adc"}, /* Battery voltage (V) , */\
- { 0x1608, "temp_adc"}, /* IC Temperature (C) , */\
- { 0x1709, "vddp_adc"}, /* IC VDDP voltage ( 1023*VDDP/9.5 V) , */\
- { 0x2040, "tdm_enable"}, /* Enable interface , */\
- { 0x2050, "tdm_mode"}, /* Slave/master , */\
- { 0x2060, "tdm_clk_inversion"}, /* Reception data to BCK clock , */\
- { 0x2073, "tdm_fs_ws_length"}, /* FS length (master mode only) , */\
- { 0x20b0, "tdm_fs_ws_polarity"}, /* FS polarity , */\
- { 0x20c3, "tdm_nbck"}, /* N-BCK's in FS , */\
- { 0x2103, "tdm_nb_of_slots"}, /* N-slots in Frame , */\
- { 0x2144, "tdm_slot_length"}, /* N-bits in slot , */\
- { 0x2194, "tdm_bits_remaining"}, /* N-bits remaining , */\
- { 0x21e0, "tdm_data_delay"}, /* data delay to FS , */\
- { 0x21f0, "tdm_data_adjustment"}, /* data adjustment , */\
- { 0x2201, "tdm_audio_sample_compression"}, /* Received audio compression , */\
- { 0x2224, "tdm_sample_size"}, /* Sample size per slot , */\
- { 0x2271, "tdm_txdata_format"}, /* Format unused bits , */\
- { 0x2291, "tdm_txdata_format_unused_slot_sd0"}, /* Format unused slots DATAO , */\
- { 0x2300, "tdm_sink0_enable"}, /* Control audio tdm channel in 0 (spkr + dcdc) , */\
- { 0x2310, "tdm_sink1_enable"}, /* Control audio tdm channel in 1 (dcdc) , */\
- { 0x2330, "tdm_source0_enable"}, /* current sense vbat temperature and vddp feedback , */\
- { 0x2340, "tdm_source1_enable"}, /* Voltage sense vbat temperature and vddp feedback , */\
- { 0x2603, "tdm_sink0_slot"}, /* tdm slot for sink 0 (speaker + dcdc) , */\
- { 0x2643, "tdm_sink1_slot"}, /* tdm slot for sink 1 (dcdc) , */\
- { 0x26c3, "tdm_source0_slot"}, /* Slot Position of current sense vbat temperature and vddp feedback, */\
- { 0x2703, "tdm_source1_slot"}, /* Slot Position of Voltage sense vbat temperature and vddp feedback, */\
- { 0x3111, "pdm_side_tone_sel"}, /* Side tone input , */\
- { 0x3201, "pdm_nbck"}, /* PDM BCK/Fs ratio , */\
- { 0x4000, "int_out_flag_por"}, /* Status POR , */\
- { 0x4010, "int_out_flag_pll_lock"}, /* Status PLL lock , */\
- { 0x4020, "int_out_flag_otpok"}, /* Status OTP alarm , */\
- { 0x4030, "int_out_flag_ovpok"}, /* Status OVP alarm , */\
- { 0x4040, "int_out_flag_uvpok"}, /* Status UVP alarm , */\
- { 0x4050, "int_out_flag_clocks_stable"}, /* Status clocks stable , */\
- { 0x4060, "int_out_flag_mtp_busy"}, /* Status MTP busy , */\
- { 0x4070, "int_out_flag_lost_clk"}, /* Status lost clock , */\
- { 0x40a0, "int_out_flag_engage"}, /* Status amplifier engage , */\
- { 0x40c0, "int_out_flag_enbl_amp"}, /* Status amplifier enable , */\
- { 0x40d0, "int_out_flag_enbl_ref"}, /* Status Ref enable , */\
- { 0x40e0, "int_out_flag_adc10_ready"}, /* Status Control ADC , */\
- { 0x4100, "int_out_flag_bst_bstcur"}, /* Status DCDC current limiting , */\
- { 0x4110, "int_out_flag_bst_hiz"}, /* Status DCDC active , */\
- { 0x4120, "int_out_flag_bst_ocpok"}, /* Status DCDC OCP , */\
- { 0x4130, "int_out_flag_bst_peakcur"}, /* Status bst peakcur , */\
- { 0x4140, "int_out_flag_bst_voutcomp"}, /* Status DCDC level 1x , */\
- { 0x4150, "int_out_flag_bst_voutcomp86"}, /* Status DCDC level 1.14x , */\
- { 0x4160, "int_out_flag_bst_voutcomp93"}, /* Status DCDC level 1.07x , */\
- { 0x4190, "int_out_flag_ocp_alarm"}, /* Status ocp alarm , */\
- { 0x41a0, "int_out_flag_man_wait_src_settings"}, /* Status Waits HW I2C settings , */\
- { 0x41c0, "int_out_flag_man_start_mute_audio"}, /* Status Audio mute sequence , */\
- { 0x41f0, "int_out_flag_clk_out_of_range"}, /* Status flag_clk_out_of_range , */\
- { 0x4200, "int_out_flag_tdm_error"}, /* Status tdm error , */\
- { 0x4220, "int_out_flag_clip"}, /* Status clip , */\
- { 0x4240, "int_out_flag_lp_detect_mode0"}, /* Status low power mode0 , */\
- { 0x4250, "int_out_flag_lp_detect_mode1"}, /* Status low power mode1 , */\
- { 0x4260, "int_out_flag_low_amplitude"}, /* Status low noise detection , */\
- { 0x4270, "int_out_flag_vddp_gt_vbat"}, /* Status VDDP greater than VBAT , */\
- { 0x4400, "int_in_flag_por"}, /* Clear POR , */\
- { 0x4410, "int_in_flag_pll_lock"}, /* Clear PLL lock , */\
- { 0x4420, "int_in_flag_otpok"}, /* Clear OTP alarm , */\
- { 0x4430, "int_in_flag_ovpok"}, /* Clear OVP alarm , */\
- { 0x4440, "int_in_flag_uvpok"}, /* Clear UVP alarm , */\
- { 0x4450, "int_in_flag_clocks_stable"}, /* Clear clocks stable , */\
- { 0x4460, "int_in_flag_mtp_busy"}, /* Clear mtp busy , */\
- { 0x4470, "int_in_flag_lost_clk"}, /* Clear lost clk , */\
- { 0x44a0, "int_in_flag_engage"}, /* Clear amplifier engage , */\
- { 0x44c0, "int_in_flag_enbl_amp"}, /* Clear enbl amp , */\
- { 0x44d0, "int_in_flag_enbl_ref"}, /* Clear ref enable , */\
- { 0x44e0, "int_in_flag_adc10_ready"}, /* Clear control ADC , */\
- { 0x4500, "int_in_flag_bst_bstcur"}, /* Clear DCDC current limiting , */\
- { 0x4510, "int_in_flag_bst_hiz"}, /* Clear DCDC active , */\
- { 0x4520, "int_in_flag_bst_ocpok"}, /* Clear DCDC OCP , */\
- { 0x4530, "int_in_flag_bst_peakcur"}, /* Clear bst peakcur , */\
- { 0x4540, "int_in_flag_bst_voutcomp"}, /* Clear DCDC level 1x , */\
- { 0x4550, "int_in_flag_bst_voutcomp86"}, /* Clear DCDC level 1.14x , */\
- { 0x4560, "int_in_flag_bst_voutcomp93"}, /* Clear DCDC level 1.07x , */\
- { 0x4590, "int_in_flag_ocp_alarm"}, /* Clear ocp alarm , */\
- { 0x45a0, "int_in_flag_man_wait_src_settings"}, /* Clear wait HW I2C settings , */\
- { 0x45c0, "int_in_flag_man_start_mute_audio"}, /* Clear audio mute sequence , */\
- { 0x45f0, "int_in_flag_clk_out_of_range"}, /* Clear flag_clk_out_of_range , */\
- { 0x4600, "int_in_flag_tdm_error"}, /* Clear tdm error , */\
- { 0x4620, "int_in_flag_clip"}, /* Clear clip , */\
- { 0x4640, "int_in_flag_lp_detect_mode0"}, /* Clear low power mode0 , */\
- { 0x4650, "int_in_flag_lp_detect_mode1"}, /* Clear low power mode1 , */\
- { 0x4660, "int_in_flag_low_amplitude"}, /* Clear low noise detection , */\
- { 0x4670, "int_in_flag_vddp_gt_vbat"}, /* Clear VDDP greater then VBAT , */\
- { 0x4800, "int_enable_flag_por"}, /* Enable por , */\
- { 0x4810, "int_enable_flag_pll_lock"}, /* Enable pll lock , */\
- { 0x4820, "int_enable_flag_otpok"}, /* Enable OTP alarm , */\
- { 0x4830, "int_enable_flag_ovpok"}, /* Enable OVP alarm , */\
- { 0x4840, "int_enable_flag_uvpok"}, /* Enable UVP alarm , */\
- { 0x4850, "int_enable_flag_clocks_stable"}, /* Enable clocks stable , */\
- { 0x4860, "int_enable_flag_mtp_busy"}, /* Enable mtp busy , */\
- { 0x4870, "int_enable_flag_lost_clk"}, /* Enable lost clk , */\
- { 0x48a0, "int_enable_flag_engage"}, /* Enable amplifier engage , */\
- { 0x48c0, "int_enable_flag_enbl_amp"}, /* Enable enbl amp , */\
- { 0x48d0, "int_enable_flag_enbl_ref"}, /* Enable ref enable , */\
- { 0x48e0, "int_enable_flag_adc10_ready"}, /* Enable Control ADC , */\
- { 0x4900, "int_enable_flag_bst_bstcur"}, /* Enable DCDC current limiting , */\
- { 0x4910, "int_enable_flag_bst_hiz"}, /* Enable DCDC active , */\
- { 0x4920, "int_enable_flag_bst_ocpok"}, /* Enable DCDC OCP , */\
- { 0x4930, "int_enable_flag_bst_peakcur"}, /* Enable bst peakcur , */\
- { 0x4940, "int_enable_flag_bst_voutcomp"}, /* Enable DCDC level 1x , */\
- { 0x4950, "int_enable_flag_bst_voutcomp86"}, /* Enable DCDC level 1.14x , */\
- { 0x4960, "int_enable_flag_bst_voutcomp93"}, /* Enable DCDC level 1.07x , */\
- { 0x4990, "int_enable_flag_ocp_alarm"}, /* Enable ocp alarm , */\
- { 0x49a0, "int_enable_flag_man_wait_src_settings"}, /* Enable waits HW I2C settings , */\
- { 0x49c0, "int_enable_flag_man_start_mute_audio"}, /* Enable man Audio mute sequence , */\
- { 0x49f0, "int_enable_flag_clk_out_of_range"}, /* Enable flag_clk_out_of_range , */\
- { 0x4a00, "int_enable_flag_tdm_error"}, /* Enable tdm error , */\
- { 0x4a20, "int_enable_flag_clip"}, /* Enable clip , */\
- { 0x4a40, "int_enable_flag_lp_detect_mode0"}, /* Enable low power mode0 , */\
- { 0x4a50, "int_enable_flag_lp_detect_mode1"}, /* Enable low power mode1 , */\
- { 0x4a60, "int_enable_flag_low_amplitude"}, /* Enable low noise detection , */\
- { 0x4a70, "int_enable_flag_vddp_gt_vbat"}, /* Enable VDDP greater tehn VBAT , */\
- { 0x4c00, "int_polarity_flag_por"}, /* Polarity por , */\
- { 0x4c10, "int_polarity_flag_pll_lock"}, /* Polarity pll lock , */\
- { 0x4c20, "int_polarity_flag_otpok"}, /* Polarity OTP alarm , */\
- { 0x4c30, "int_polarity_flag_ovpok"}, /* Polarity OVP alarm , */\
- { 0x4c40, "int_polarity_flag_uvpok"}, /* Polarity UVP alarm , */\
- { 0x4c50, "int_polarity_flag_clocks_stable"}, /* Polarity clocks stable , */\
- { 0x4c60, "int_polarity_flag_mtp_busy"}, /* Polarity mtp busy , */\
- { 0x4c70, "int_polarity_flag_lost_clk"}, /* Polarity lost clk , */\
- { 0x4ca0, "int_polarity_flag_engage"}, /* Polarity amplifier engage , */\
- { 0x4cc0, "int_polarity_flag_enbl_amp"}, /* Polarity enbl amp , */\
- { 0x4cd0, "int_polarity_flag_enbl_ref"}, /* Polarity ref enable , */\
- { 0x4ce0, "int_polarity_flag_adc10_ready"}, /* Polarity Control ADC , */\
- { 0x4d00, "int_polarity_flag_bst_bstcur"}, /* Polarity DCDC current limiting , */\
- { 0x4d10, "int_polarity_flag_bst_hiz"}, /* Polarity DCDC active , */\
- { 0x4d20, "int_polarity_flag_bst_ocpok"}, /* Polarity DCDC OCP , */\
- { 0x4d30, "int_polarity_flag_bst_peakcur"}, /* Polarity bst peakcur , */\
- { 0x4d40, "int_polarity_flag_bst_voutcomp"}, /* Polarity DCDC level 1x , */\
- { 0x4d50, "int_polarity_flag_bst_voutcomp86"}, /* Polarity DCDC level 1.14x , */\
- { 0x4d60, "int_polarity_flag_bst_voutcomp93"}, /* Polarity DCDC level 1.07x , */\
- { 0x4d90, "int_polarity_flag_ocp_alarm"}, /* Polarity ocp alarm , */\
- { 0x4da0, "int_polarity_flag_man_wait_src_settings"}, /* Polarity waits HW I2C settings , */\
- { 0x4dc0, "int_polarity_flag_man_start_mute_audio"}, /* Polarity man audio mute sequence , */\
- { 0x4df0, "int_polarity_flag_clk_out_of_range"}, /* Polarity flag_clk_out_of_range , */\
- { 0x4e00, "int_polarity_flag_tdm_error"}, /* Polarity tdm error , */\
- { 0x4e20, "int_polarity_flag_clip"}, /* Polarity clip right , */\
- { 0x4e40, "int_polarity_flag_lp_detect_mode0"}, /* Polarity low power mode0 , */\
- { 0x4e50, "int_polarity_flag_lp_detect_mode1"}, /* Polarity low power mode1 , */\
- { 0x4e60, "int_polarity_flag_low_amplitude"}, /* Polarity low noise mode , */\
- { 0x4e70, "int_polarity_flag_vddp_gt_vbat"}, /* Polarity VDDP greater than VBAT , */\
- { 0x5001, "vbat_prot_attack_time"}, /* Battery Safeguard attack time , */\
- { 0x5023, "vbat_prot_thlevel"}, /* Battery Safeguard threshold voltage level , */\
- { 0x5061, "vbat_prot_max_reduct"}, /* Battery Safeguard maximum reduction , */\
- { 0x50d0, "rst_min_vbat"}, /* Reset clipper - Auto clear , */\
- { 0x50e0, "sel_vbat"}, /* Battery voltage read out , */\
- { 0x50f0, "bypass_clipper"}, /* Bypass battery safeguard , */\
- { 0x5100, "batsense_steepness"}, /* Vbat prot steepness , */\
- { 0x5110, "soft_mute"}, /* Soft mute HW , */\
- { 0x5150, "bypass_hp"}, /* Bypass HPF , */\
- { 0x5170, "enbl_dpsa"}, /* Enable DPSA , */\
- { 0x5222, "ctrl_cc"}, /* Clip control setting , */\
- { 0x5257, "gain"}, /* Amplifier gain , */\
- { 0x52d0, "ctrl_slopectrl"}, /* Enables slope control , */\
- { 0x52e0, "ctrl_slope"}, /* Slope speed setting (bin. coded) , */\
- { 0x5301, "dpsa_level"}, /* DPSA threshold levels , */\
- { 0x5321, "dpsa_release"}, /* DPSA Release time , */\
- { 0x5340, "clipfast"}, /* Clock selection for HW clipper for Battery Safeguard, */\
- { 0x5350, "bypass_lp"}, /* Bypass the low power filter inside temperature sensor, */\
- { 0x5400, "first_order_mode"}, /* Overrule to 1st order mode of control stage when clipping, */\
- { 0x5410, "bypass_ctrlloop"}, /* Switch amplifier into open loop configuration , */\
- { 0x5420, "fb_hz"}, /* Feedback resistor set to high ohmic , */\
- { 0x5430, "icomp_engage"}, /* Engage of icomp , */\
- { 0x5440, "ctrl_kickback"}, /* Prevent double pulses of output stage , */\
- { 0x5450, "icomp_engage_overrule"}, /* To overrule the functional icomp_engage signal during validation, */\
- { 0x5503, "ctrl_dem"}, /* Enable DEM icomp and DEM one bit dac , */\
- { 0x5543, "ctrl_dem_mismatch"}, /* Enable DEM icomp mismatch for testing , */\
- { 0x5582, "dpsa_drive"}, /* Drive setting (bin. coded) , */\
- { 0x570a, "enbl_amp"}, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually, */\
- { 0x57b0, "enbl_engage"}, /* Enables/engage power stage and control loop , */\
- { 0x57c0, "enbl_engage_pst"}, /* Enables/engage power stage and control loop , */\
- { 0x5810, "hard_mute"}, /* Hard mute - PWM , */\
- { 0x5820, "pwm_shape"}, /* PWM shape , */\
- { 0x5844, "pwm_delay"}, /* PWM delay bits to set the delay, clockd is 1/(k*2048*fs), */\
- { 0x5890, "reclock_pwm"}, /* Reclock the pwm signal inside analog , */\
- { 0x58a0, "reclock_voltsense"}, /* Reclock the voltage sense pwm signal , */\
- { 0x58c0, "enbl_pwm_phase_shift"}, /* Control for pwm phase shift , */\
- { 0x6081, "pga_gain_set"}, /* PGA gain selection , */\
- { 0x60b0, "pga_lowpass_enable"}, /* Lowpass enable , */\
- { 0x60c0, "pga_pwr_enable"}, /* Power enable, directcontrol mode only , */\
- { 0x60d0, "pga_switch_enable"}, /* Switch enable, directcontrol mode only , */\
- { 0x60e0, "pga_switch_aux_enable"}, /* Switch enable aux, directcontrol mode only , */\
- { 0x6100, "force_idle"}, /* force low power in idle mode , */\
- { 0x6110, "bypass_idle"}, /* bypass low power idle mode , */\
- { 0x6123, "ctrl_attl"}, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */\
- { 0x6163, "ctrl_attr"}, /* Total gain depending on INPLEV setting (channel 0), */\
- { 0x61a0, "idle_cnt"}, /* idle counter , */\
- { 0x61b0, "enbl_idle_ch1"}, /* enable idle feature for channel 1 , */\
- { 0x6265, "zero_lvl"}, /* low noise gain switch zero trigger level , */\
- { 0x62c1, "ctrl_fb_classd"}, /* class D gain ctrl_fb_50k ctrl_fb_100k , */\
- { 0x62e1, "lownoisegain_mode"}, /* ctrl select mode , */\
- { 0x6305, "threshold_lvl"}, /* low noise gain switch trigger level , */\
- { 0x6365, "hold_time"}, /* ctrl hold time before low audio is reckoned to be low audio, */\
- { 0x6405, "lpm1_cal_offset"}, /* low power mode1 detector ctrl cal_offset from gain module , */\
- { 0x6465, "lpm1_zero_lvl"}, /* low power mode1 zero crossing detection level , */\
- { 0x64e1, "lpm1_mode"}, /* low power mode control , */\
- { 0x6505, "lpm1_threshold_lvl"}, /* low power mode1 amplitude trigger level , */\
- { 0x6565, "lpm1_hold_time"}, /* low power mode1 detector ctrl hold time before low audio is reckoned to be low audio, */\
- { 0x65c0, "disable_low_power_mode"}, /* low power mode1 detector control , */\
- { 0x6600, "dcdc_pfm20khz_limit"}, /* DCDC in PFM mode pwm mode is activated each 50us to force a pwm pulse, */\
- { 0x6611, "dcdc_ctrl_maxzercnt"}, /* DCDC. Number of zero current flags to count before going to pfm mode, */\
- { 0x6656, "dcdc_vbat_delta_detect"}, /* Threshold before booster is reacting on a delta Vbat (in PFM mode) by temporarily switching to PWM mode, */\
- { 0x66c0, "dcdc_ignore_vbat"}, /* Ignore an increase on Vbat , */\
- { 0x6700, "enbl_minion"}, /* Enables minion (small) power stage , */\
- { 0x6713, "vth_vddpvbat"}, /* select vddp-vbat thres signal , */\
- { 0x6750, "lpen_vddpvbat"}, /* select vddp-vbat filtred vs unfiltered compare , */\
- { 0x6801, "tdm_source_mapping"}, /* tdm source mapping , */\
- { 0x6821, "tdm_sourcea_frame_sel"}, /* Sensed value A , */\
- { 0x6841, "tdm_sourceb_frame_sel"}, /* Sensed value B , */\
- { 0x6881, "pdm_anc_sel"}, /* anc input , */\
- { 0x68a0, "anc_1scomplement"}, /* ANC one s complement , */\
- { 0x6901, "sam_mode"}, /* sam enable , */\
- { 0x6920, "sam_src"}, /* sam source , */\
- { 0x6931, "pdmdat_h_sel"}, /* pdm out value when pdm_clk is higth , */\
- { 0x6951, "pdmdat_l_sel"}, /* pdm out value when pdm_clk is low , */\
- { 0x6970, "sam_spkr_sel"}, /* ram output on mode sam and audio , */\
- { 0x6a02, "rst_min_vbat_delay"}, /* rst_min_vbat delay (nb fs) , */\
- { 0x6b00, "disable_auto_engage"}, /* disable auto engange , */\
- { 0x6b10, "sel_tdm_data_valid"}, /* select tdm valid for speaker subsystem , */\
- { 0x6c02, "ns_hp2ln_criterion"}, /* 0..7 zeroes at ns as threshold to swap from high_power to low_noise, */\
- { 0x6c32, "ns_ln2hp_criterion"}, /* 0..7 zeroes at ns as threshold to swap from low_noise to high_power, */\
- { 0x6c69, "spare_out"}, /* spare_out , */\
- { 0x6d0f, "spare_in"}, /* spare_in , */\
- { 0x6e00, "flag_lp_detect_mode0"}, /* low power mode 0 detection , */\
- { 0x6e10, "flag_lp_detect_mode1"}, /* low power mode 1 detection , */\
- { 0x6e20, "flag_low_amplitude"}, /* low amplitude detection , */\
- { 0x6e30, "flag_vddp_gt_vbat"}, /* vddp greater than vbat , */\
- { 0x6f02, "cursense_comp_delay"}, /* delay to allign compensation signal with current sense signal, */\
- { 0x6f40, "cursense_comp_sign"}, /* polarity of compensation for current sense , */\
- { 0x6f50, "enbl_cursense_comp"}, /* enable current sense compensation , */\
- { 0x6f60, "sel_clip_pwms"}, /* Select pwm clip flag , */\
- { 0x6f72, "pwms_clip_lvl"}, /* set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
- { 0x7002, "scnd_boost_voltage"}, /* Second boost voltage level , */\
- { 0x7033, "boost_cur"}, /* Max coil current , */\
- { 0x7071, "bst_slpcmplvl"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
- { 0x7090, "boost_intel"}, /* Adaptive boost mode , */\
- { 0x70a0, "boost_speed"}, /* Soft ramp up/down , */\
- { 0x70e0, "dcdcoff_mode"}, /* DCDC on/off , */\
- { 0x70f0, "dcdc_pwmonly"}, /* DCDC PWM only mode , */\
- { 0x7104, "bst_drive"}, /* Binary coded drive setting for boost converter power stage, */\
- { 0x7151, "bst_scalecur"}, /* For testing direct control scale current , */\
- { 0x7174, "bst_slopecur"}, /* For testing direct control slope current , */\
- { 0x71c1, "bst_slope"}, /* Boost slope speed , */\
- { 0x71e0, "bst_bypass_bstcur"}, /* Bypass control for boost current settings , */\
- { 0x71f0, "bst_bypass_bstfoldback"}, /* Bypass control for boost foldback , */\
- { 0x7200, "enbl_bst_engage"}, /* Enable power stage dcdc controller , */\
- { 0x7210, "enbl_bst_hizcom"}, /* Enable hiz comparator , */\
- { 0x7220, "enbl_bst_peak2avg"}, /* Enable boost peak2avg functionality , */\
- { 0x7230, "enbl_bst_peakcur"}, /* Enable peak current , */\
- { 0x7240, "enbl_bst_power"}, /* Enable line of the powerstage , */\
- { 0x7250, "enbl_bst_slopecur"}, /* Enable bit of max-current dac , */\
- { 0x7260, "enbl_bst_voutcomp"}, /* Enable vout comparators , */\
- { 0x7270, "enbl_bst_voutcomp86"}, /* Enable vout-86 comparators , */\
- { 0x7280, "enbl_bst_voutcomp93"}, /* Enable vout-93 comparators , */\
- { 0x7290, "enbl_bst_windac"}, /* Enable window dac , */\
- { 0x72a5, "bst_windac"}, /* for testing direct control windac , */\
- { 0x7300, "boost_alg"}, /* Control for boost adaptive loop gain , */\
- { 0x7311, "boost_loopgain"}, /* DCDC boost loopgain setting , */\
- { 0x7331, "bst_freq"}, /* DCDC boost frequency control , */\
- { 0x7402, "frst_boost_voltage"}, /* 1st boost voltage level , */\
- { 0x7430, "boost_track"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
- { 0x7444, "boost_trip_lvl_1st"}, /* 1st Adaptive boost trip levels, effective only when DCIE is set to 1, */\
- { 0x7494, "boost_hold_time"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
- { 0x74e0, "sel_dcdc_envelope_8fs"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
- { 0x74f0, "ignore_flag_voutcomp86"}, /* Ignore flag_voutcomp86 , */\
- { 0x7502, "track_decay"}, /* DCDC Boost decay speed after a peak value, effective only when boost_track is set to 1, */\
- { 0x7534, "boost_trip_lvl_2nd"}, /* 2nd Adaptive boost trip levels, effective only when DCIE is set to 1, */\
- { 0x7584, "boost_trip_lvl_track"}, /* Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
- { 0x7620, "pga_test_ldo_bypass"}, /* bypass internal PGA LDO , */\
- { 0x8001, "sel_clk_cs"}, /* Current sense clock duty cycle control , */\
- { 0x8021, "micadc_speed"}, /* Current sense clock for MiCADC selection - 32/44.1/48 KHz Fs band only, */\
- { 0x8050, "cs_gain_control"}, /* Current sense gain control , */\
- { 0x8060, "cs_bypass_gc"}, /* Bypasses the CS gain correction , */\
- { 0x8087, "cs_gain"}, /* Current sense gain , */\
- { 0x8200, "enbl_cmfb"}, /* Current sense common mode feedback control , */\
- { 0x8210, "invertpwm"}, /* Current sense common mode feedback pwm invert control, */\
- { 0x8222, "cmfb_gain"}, /* Current sense common mode feedback control gain , */\
- { 0x8254, "cmfb_offset"}, /* Current sense common mode feedback control offset , */\
- { 0x82a0, "cs_sam_set"}, /* Enable SAM input for current sense , */\
- { 0x8305, "cs_ktemp"}, /* Current sense temperature compensation trimming (1 - VALUE*TEMP)*signal, */\
- { 0x8400, "cs_adc_bsoinv"}, /* Bitstream inversion for current sense ADC , */\
- { 0x8421, "cs_adc_hifreq"}, /* Frequency mode current sense ADC , */\
- { 0x8440, "cs_adc_nortz"}, /* Return to zero for current sense ADC , */\
- { 0x8453, "cs_adc_offset"}, /* Micadc ADC offset setting , */\
- { 0x8490, "cs_adc_slowdel"}, /* Select delay for current sense ADC (internal decision circuitry), */\
- { 0x84a4, "cs_adc_gain"}, /* Gain setting for current sense ADC (two's complement), */\
- { 0x8500, "cs_resonator_enable"}, /* Enable for resonator to improve SRN , */\
- { 0x8510, "cs_classd_tran_skip"}, /* Skip current sense connection during a classD amplifier transition, */\
- { 0x8530, "cs_inn_short"}, /* Short current sense negative to common mode , */\
- { 0x8540, "cs_inp_short"}, /* Short current sense positive to common mode , */\
- { 0x8550, "cs_ldo_bypass"}, /* Bypass current sense LDO , */\
- { 0x8560, "cs_ldo_pulldown"}, /* Pull down current sense LDO, only valid if left_enbl_cs_ldo is high, */\
- { 0x8574, "cs_ldo_voset"}, /* Current sense LDO voltage level setting (two's complement), */\
- { 0x8700, "enbl_cs_adc"}, /* Enable current sense ADC , */\
- { 0x8710, "enbl_cs_inn1"}, /* Enable connection of current sense negative1 , */\
- { 0x8720, "enbl_cs_inn2"}, /* Enable connection of current sense negative2 , */\
- { 0x8730, "enbl_cs_inp1"}, /* Enable connection of current sense positive1 , */\
- { 0x8740, "enbl_cs_inp2"}, /* Enable connection of current sense positive2 , */\
- { 0x8750, "enbl_cs_ldo"}, /* Enable current sense LDO , */\
- { 0x8760, "enbl_cs_nofloating_n"}, /* Connect current sense negative to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */\
- { 0x8770, "enbl_cs_nofloating_p"}, /* Connect current sense positive to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */\
- { 0x8780, "enbl_cs_vbatldo"}, /* Enable of current sense LDO , */\
- { 0x8800, "volsense_pwm_sel"}, /* Voltage sense PWM source selection control , */\
- { 0x8810, "vol_cur_sense_dc_offset"}, /* voltage and current sense decimator offset control, */\
- { 0xa007, "mtpkey1"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
- { 0xa107, "mtpkey2"}, /* MTP KEY2 register , */\
- { 0xa200, "key01_locked"}, /* Indicates KEY1 is locked , */\
- { 0xa210, "key02_locked"}, /* Indicates KEY2 is locked , */\
- { 0xa302, "mtp_man_address_in"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
- { 0xa330, "man_copy_mtp_to_iic"}, /* Start copying single word from mtp to I2C mtp register, */\
- { 0xa340, "man_copy_iic_to_mtp"}, /* Start copying single word from I2C mtp register to mtp, */\
- { 0xa350, "auto_copy_mtp_to_iic"}, /* Start copying all the data from mtp to I2C mtp registers, */\
- { 0xa360, "auto_copy_iic_to_mtp"}, /* Start copying data from I2C mtp registers to mtp , */\
- { 0xa400, "faim_set_clkws"}, /* Sets the faim controller clock wait state register, */\
- { 0xa410, "faim_sel_evenrows"}, /* All even rows of the faim are selected, active high, */\
- { 0xa420, "faim_sel_oddrows"}, /* All odd rows of the faim are selected, all rows in combination with sel_evenrows, */\
- { 0xa430, "faim_program_only"}, /* Skip the erase access at wr_faim command (write-program-marginread), */\
- { 0xa440, "faim_erase_only"}, /* Skip the program access at wr_faim command (write-erase-marginread), */\
- { 0xa50f, "mtp_man_data_out_msb"}, /* MSB word of MTP manual read data , */\
- { 0xa60f, "mtp_man_data_out_lsb"}, /* LSB word of MTP manual read data , */\
- { 0xa70f, "mtp_man_data_in_msb"}, /* MSB word of write data for MTP manual write , */\
- { 0xa80f, "mtp_man_data_in_lsb"}, /* LSB word of write data for MTP manual write , */\
- { 0xb010, "bypass_ocpcounter"}, /* Bypass OCP Counter , */\
- { 0xb020, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
- { 0xb030, "bypass_ovp"}, /* Bypass OVP , */\
- { 0xb040, "bypass_uvp"}, /* Bypass UVP , */\
- { 0xb050, "bypass_otp"}, /* Bypass OTP , */\
- { 0xb060, "bypass_lost_clk"}, /* Bypass lost clock detector , */\
- { 0xb070, "ctrl_vpalarm"}, /* vpalarm (uvp ovp handling) , */\
- { 0xb087, "ocp_threshold"}, /* OCP threshold level , */\
- { 0xb108, "ext_temp"}, /* External temperature (C) , */\
- { 0xb190, "ext_temp_sel"}, /* Select temp Speaker calibration , */\
- { 0xc000, "use_direct_ctrls"}, /* Direct control to overrule several functions for testing, */\
- { 0xc010, "rst_datapath"}, /* Direct control for datapath reset , */\
- { 0xc020, "rst_cgu"}, /* Direct control for cgu reset , */\
- { 0xc038, "enbl_ref"}, /* Switch on the analog references, each part of the references can be switched on/off individually, */\
- { 0xc0d0, "enbl_ringo"}, /* Enable the ring oscillator for test purpose , */\
- { 0xc0e0, "use_direct_clk_ctrl"}, /* Direct clock control to overrule several functions for testing, */\
- { 0xc0f0, "use_direct_pll_ctrl"}, /* Direct PLL control to overrule several functions for testing, */\
- { 0xc100, "enbl_tsense"}, /* Temperature sensor enable control - I2C direct mode, */\
- { 0xc110, "tsense_hibias"}, /* Bit to set the biasing in temp sensor to high , */\
- { 0xc120, "enbl_flag_vbg"}, /* Enable flagging of bandgap out of control , */\
- { 0xc20f, "abist_offset"}, /* Offset control for ABIST testing (two's complement), */\
- { 0xc300, "bypasslatch"}, /* Bypass latch , */\
- { 0xc311, "sourcea"}, /* Set OUTA to , */\
- { 0xc331, "sourceb"}, /* Set OUTB to , */\
- { 0xc350, "inverta"}, /* Invert pwma test signal , */\
- { 0xc360, "invertb"}, /* Invert pwmb test signal , */\
- { 0xc374, "pulselength"}, /* Pulse length setting test input for amplifier (clock d - k*2048*fs), */\
- { 0xc3c0, "tdm_enable_loopback"}, /* TDM loopback test , */\
- { 0xc400, "bst_bypasslatch"}, /* Bypass latch in boost converter , */\
- { 0xc411, "bst_source"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
- { 0xc430, "bst_invertb"}, /* Invert pwmbst test signal , */\
- { 0xc444, "bst_pulselength"}, /* Pulse length setting test input for boost converter , */\
- { 0xc490, "test_bst_ctrlsthv"}, /* Test mode for boost control stage , */\
- { 0xc4a0, "test_bst_iddq"}, /* IDDQ testing in power stage of boost converter , */\
- { 0xc4b0, "test_bst_rdson"}, /* RDSON testing - boost power stage , */\
- { 0xc4c0, "test_bst_cvi"}, /* CVI testing - boost power stage , */\
- { 0xc4d0, "test_bst_ocp"}, /* Boost OCP. For old ocp (ctrl_reversebst is 0), For new ocp (ctrl_reversebst is 1), */\
- { 0xc4e0, "test_bst_sense"}, /* Test option for the sense NMOS in booster for current mode control., */\
- { 0xc500, "test_cvi"}, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */\
- { 0xc510, "test_discrete"}, /* Test function noise measurement , */\
- { 0xc520, "test_iddq"}, /* Set the power stages in iddq mode for gate stress., */\
- { 0xc540, "test_rdson"}, /* Analog BIST, switch to enable Rdson measurement , */\
- { 0xc550, "test_sdelta"}, /* Analog BIST, noise test , */\
- { 0xc570, "test_enbl_cs"}, /* Enable for digimux mode of current sense , */\
- { 0xc5b0, "pga_test_enable"}, /* Enable PGA test mode , */\
- { 0xc5c0, "pga_test_offset_enable"}, /* Enable PGA test offset , */\
- { 0xc5d0, "pga_test_shortinput_enable"}, /* Enable PGA test shortinput , */\
- { 0xc600, "enbl_pwm_dcc"}, /* Enables direct control of pwm duty cycle for DCDC power stage, */\
- { 0xc613, "pwm_dcc_cnt"}, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */\
- { 0xc650, "enbl_ldo_stress"}, /* Enable stress of internal supply voltages powerstages, */\
- { 0xc707, "digimuxa_sel"}, /* DigimuxA input selection control routed to DATAO (see Digimux list for details), */\
- { 0xc787, "digimuxb_sel"}, /* DigimuxB input selection control routed to INT (see Digimux list for details), */\
- { 0xc807, "digimuxc_sel"}, /* DigimuxC input selection control routed to PDMDAT (see Digimux list for details), */\
- { 0xc981, "int_ehs"}, /* Speed/load setting for INT IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
- { 0xc9c0, "hs_mode"}, /* I2C high speed mode control , */\
- { 0xca00, "enbl_anamux1"}, /* Enable anamux1 , */\
- { 0xca10, "enbl_anamux2"}, /* Enable anamux2 , */\
- { 0xca20, "enbl_anamux3"}, /* Enable anamux3 , */\
- { 0xca30, "enbl_anamux4"}, /* Enable anamux4 , */\
- { 0xca74, "anamux1"}, /* Anamux selection control - anamux on TEST1 , */\
- { 0xcb04, "anamux2"}, /* Anamux selection control - anamux on TEST2 , */\
- { 0xcb54, "anamux3"}, /* Anamux selection control - anamux on TEST3 , */\
- { 0xcba4, "anamux4"}, /* Anamux selection control - anamux on TEST4 , */\
- { 0xcd05, "pll_seli"}, /* PLL SELI - I2C direct PLL control mode only , */\
- { 0xcd64, "pll_selp"}, /* PLL SELP - I2C direct PLL control mode only , */\
- { 0xcdb3, "pll_selr"}, /* PLL SELR - I2C direct PLL control mode only , */\
- { 0xcdf0, "pll_frm"}, /* PLL free running mode control; 1 in TCB direct control mode, else this control bit, */\
- { 0xce09, "pll_ndec"}, /* PLL NDEC - I2C direct PLL control mode only , */\
- { 0xcea0, "pll_mdec_msb"}, /* MSB of pll_mdec - I2C direct PLL control mode only, */\
- { 0xceb0, "enbl_pll"}, /* Enables PLL in I2C direct PLL control mode only , */\
- { 0xcec0, "enbl_osc"}, /* Enables OSC1M in I2C direct control mode only , */\
- { 0xced0, "pll_bypass"}, /* PLL bypass control in I2C direct PLL control mode only, */\
- { 0xcee0, "pll_directi"}, /* PLL directi control in I2C direct PLL control mode only, */\
- { 0xcef0, "pll_directo"}, /* PLL directo control in I2C direct PLL control mode only, */\
- { 0xcf0f, "pll_mdec_lsb"}, /* Bits 15..0 of PLL MDEC are I2C direct PLL control mode only, */\
- { 0xd006, "pll_pdec"}, /* PLL PDEC - I2C direct PLL control mode only , */\
- { 0xd10f, "tsig_freq_lsb"}, /* Internal sinus test generator frequency control , */\
- { 0xd202, "tsig_freq_msb"}, /* Select internal sinus test generator, frequency control msb bits, */\
- { 0xd230, "inject_tsig"}, /* Control bit to switch to internal sinus test generator, */\
- { 0xd283, "tsig_gain"}, /* Test signal gain , */\
- { 0xd300, "adc10_reset"}, /* Reset for ADC10 - I2C direct control mode , */\
- { 0xd311, "adc10_test"}, /* Test mode selection signal for ADC10 - I2C direct control mode, */\
- { 0xd332, "adc10_sel"}, /* Select the input to convert for ADC10 - I2C direct control mode, */\
- { 0xd364, "adc10_prog_sample"}, /* ADC10 program sample setting - I2C direct control mode, */\
- { 0xd3b0, "adc10_enbl"}, /* Enable ADC10 - I2C direct control mode , */\
- { 0xd3c0, "bypass_lp_vbat"}, /* Bypass control for Low pass filter in batt sensor , */\
- { 0xd409, "data_adc10_tempbat"}, /* ADC 10 data output data for testing , */\
- { 0xd507, "ctrl_digtoana_hidden"}, /* Spare digital to analog control bits - Hidden , */\
- { 0xd580, "enbl_clk_out_of_range"}, /* Clock out of range , */\
- { 0xd621, "clkdiv_audio_sel"}, /* Audio clock divider selection in direct clock control mode, */\
- { 0xd641, "clkdiv_muxa_sel"}, /* DCDC MUXA clock divider selection in direct clock control mode, */\
- { 0xd661, "clkdiv_muxb_sel"}, /* DCDC MUXB clock divider selection in direct clock control mode, */\
- { 0xd701, "pdmdat_ehs"}, /* Speed/load setting for PDMDAT IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
- { 0xd721, "datao_ehs"}, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
- { 0xd740, "bck_ehs"}, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
- { 0xd750, "datai_ehs"}, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
- { 0xd760, "pdmclk_ehs"}, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
- { 0xd800, "source_in_testmode"}, /* tdm source in test mode (return only current and voltage sense), */\
- { 0xd810, "gainatt_feedback"}, /* gainatt feedback to tdm , */\
- { 0xd822, "test_parametric_io"}, /* test io parametric , */\
- { 0xd850, "ctrl_bst_clk_lp1"}, /* boost clock control in low power mode1 , */\
- { 0xd861, "test_spare_out1"}, /* test spare out 1 , */\
- { 0xd880, "bst_dcmbst"}, /* dcm boost , */\
- { 0xd890, "pdm_loopback"}, /* pdm loop back to tdm , */\
- { 0xd8a1, "force_pga_clock"}, /* force pga clock , */\
- { 0xd8c3, "test_spare_out2"}, /* test spare out 1 , */\
- { 0xee0f, "sw_profile"}, /* Software profile data , */\
- { 0xef0f, "sw_vstep"}, /* Software vstep information , */\
- { 0xf000, "calibration_onetime"}, /* Calibration schedule , */\
- { 0xf010, "calibr_ron_done"}, /* Calibration Ron executed , */\
- { 0xf020, "calibr_dcdc_api_calibrate"}, /* Calibration current limit DCDC , */\
- { 0xf030, "calibr_dcdc_delta_sign"}, /* Sign bit for delta calibration current limit DCDC , */\
- { 0xf042, "calibr_dcdc_delta"}, /* Calibration delta current limit DCDC , */\
- { 0xf078, "calibr_speaker_info"}, /* Reserved space for allowing customer to store speaker information, */\
- { 0xf105, "calibr_vout_offset"}, /* DCDC offset calibration 2's complement (key1 protected), */\
- { 0xf163, "spare_mpt1_9_6"}, /* HW gain module - left channel (2's complement) , */\
- { 0xf1a5, "spare_mpt1_15_10"}, /* Offset for amplifier, HW gain module - left channel (2's complement), */\
- { 0xf203, "calibr_gain"}, /* HW gain module (2's complement) , */\
- { 0xf245, "calibr_offset"}, /* Offset for amplifier, HW gain module (2's complement), */\
- { 0xf2a3, "spare_mpt2_13_10"}, /* Trimming of LDO (2.7V) , */\
- { 0xf307, "spare_mpt3_7_0"}, /* SPARE , */\
- { 0xf387, "calibr_gain_cs"}, /* Current sense gain (signed two's complement format), */\
- { 0xf40f, "spare_mtp4_15_0"}, /* SPARE , */\
- { 0xf50f, "calibr_R25C_R"}, /* Ron resistance of speaker coil , */\
- { 0xf606, "spare_mpt6_6_0"}, /* SPARE , */\
- { 0xf686, "spare_mpt6_14_8"}, /* Offset of left amplifier level shifter B , */\
- { 0xf706, "ctrl_offset_a"}, /* Offset of level shifter A , */\
- { 0xf786, "ctrl_offset_b"}, /* Offset of amplifier level shifter B , */\
- { 0xf806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
- { 0xf870, "htol_iic_addr_en"}, /* HTOL I2C address enable control , */\
- { 0xf884, "calibr_temp_offset"}, /* Temperature offset 2's compliment (key1 protected), */\
- { 0xf8d2, "calibr_temp_gain"}, /* Temperature gain 2's compliment (key1 protected) , */\
- { 0xf900, "mtp_lock_dcdcoff_mode"}, /* Disable function dcdcoff_mode , */\
- { 0xf910, "disable_sam_mode"}, /* Disable same mode , */\
- { 0xf920, "mtp_lock_bypass_clipper"}, /* Disable function bypass_clipper , */\
- { 0xf930, "mtp_lock_max_dcdc_voltage"}, /* Disable programming of max dcdc boost voltage , */\
- { 0xf943, "calibr_vbg_trim"}, /* Bandgap trimming control , */\
- { 0xf980, "mtp_enbl_amp_in_state_alarm"}, /* Enbl_amp in alarm state , */\
- { 0xf990, "mtp_enbl_pwm_delay_clock_gating"}, /* pwm delay clock auto gating , */\
- { 0xf9a0, "mtp_enbl_ocp_clock_gating"}, /* ocpclock auto gating , */\
- { 0xf9b0, "mtp_gate_cgu_clock_for_test"}, /* cgu test clock control , */\
- { 0xf9c3, "spare_mtp9_15_12"}, /* MTP-control FW - See Firmware I2C API document for details, */\
- { 0xfa0f, "mtpdataA"}, /* MTPdataA (key1 protected) , */\
- { 0xfb0f, "mtpdataB"}, /* MTPdataB (key1 protected) , */\
- { 0xfc0f, "mtpdataC"}, /* MTPdataC (key1 protected) , */\
- { 0xfd0f, "mtpdataD"}, /* MTPdataD (key1 protected) , */\
- { 0xfe0f, "mtpdataE"}, /* MTPdataE (key1 protected) , */\
- { 0xff07, "calibr_osc_delta_ndiv"}, /* Calibration data for OSC1M, signed number representation, */\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-
-enum tfa9872_irq {
- tfa9872_irq_stvdds = 0,
- tfa9872_irq_stplls = 1,
- tfa9872_irq_stotds = 2,
- tfa9872_irq_stovds = 3,
- tfa9872_irq_stuvds = 4,
- tfa9872_irq_stclks = 5,
- tfa9872_irq_stmtpb = 6,
- tfa9872_irq_stnoclk = 7,
- tfa9872_irq_stsws = 10,
- tfa9872_irq_stamps = 12,
- tfa9872_irq_starefs = 13,
- tfa9872_irq_stadccr = 14,
- tfa9872_irq_stbstcu = 16,
- tfa9872_irq_stbsthi = 17,
- tfa9872_irq_stbstoc = 18,
- tfa9872_irq_stbstpkcur = 19,
- tfa9872_irq_stbstvc = 20,
- tfa9872_irq_stbst86 = 21,
- tfa9872_irq_stbst93 = 22,
- tfa9872_irq_stocpr = 25,
- tfa9872_irq_stmwsrc = 26,
- tfa9872_irq_stmwsmu = 28,
- tfa9872_irq_stclkoor = 31,
- tfa9872_irq_sttdmer = 32,
- tfa9872_irq_stclpr = 34,
- tfa9872_irq_stlp0 = 36,
- tfa9872_irq_stlp1 = 37,
- tfa9872_irq_stla = 38,
- tfa9872_irq_stvddph = 39,
- tfa9872_irq_max = 40,
- tfa9872_irq_all = -1 /* all irqs */};
-
-#define TFA9872_IRQ_NAMETABLE static tfaIrqName_t Tfa9872IrqNames[]= {\
- { 0, "STVDDS"},\
- { 1, "STPLLS"},\
- { 2, "STOTDS"},\
- { 3, "STOVDS"},\
- { 4, "STUVDS"},\
- { 5, "STCLKS"},\
- { 6, "STMTPB"},\
- { 7, "STNOCLK"},\
- { 8, "8"},\
- { 9, "9"},\
- { 10, "STSWS"},\
- { 11, "11"},\
- { 12, "STAMPS"},\
- { 13, "STAREFS"},\
- { 14, "STADCCR"},\
- { 15, "15"},\
- { 16, "STBSTCU"},\
- { 17, "STBSTHI"},\
- { 18, "STBSTOC"},\
- { 19, "STBSTPKCUR"},\
- { 20, "STBSTVC"},\
- { 21, "STBST86"},\
- { 22, "STBST93"},\
- { 23, "23"},\
- { 24, "24"},\
- { 25, "STOCPR"},\
- { 26, "STMWSRC"},\
- { 27, "27"},\
- { 28, "STMWSMU"},\
- { 29, "29"},\
- { 30, "30"},\
- { 31, "STCLKOOR"},\
- { 32, "STTDMER"},\
- { 33, "33"},\
- { 34, "STCLPR"},\
- { 35, "35"},\
- { 36, "STLP0"},\
- { 37, "STLP1"},\
- { 38, "STLA"},\
- { 39, "STVDDPH"},\
- { 40, "40"},\
-};
-#endif /* _TFA9872_TFAFIELDNAMES_H */
diff --git a/inc/tfa9874_tfafieldnames.h b/inc/tfa9874_tfafieldnames.h
deleted file mode 100644
index ca7f320..0000000
--- a/inc/tfa9874_tfafieldnames.h
+++ /dev/null
@@ -1,836 +0,0 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _TFA9874_TFAFIELDNAMES_H
-#define _TFA9874_TFAFIELDNAMES_H
-
-
-#define TFA9874_I2CVERSION 1.16
-
-typedef enum nxpTfa9874BfEnumList {
- TFA9874_BF_PWDN = 0x0000, /*!< Powerdown selection */
- TFA9874_BF_I2CR = 0x0010, /*!< I2C Reset - Auto clear */
- TFA9874_BF_AMPE = 0x0030, /*!< Activate Amplifier */
- TFA9874_BF_DCA = 0x0040, /*!< Activate DC-to-DC converter */
- TFA9874_BF_INTP = 0x0071, /*!< Interrupt config */
- TFA9874_BF_BYPOCP= 0x00b0, /*!< Bypass OCP */
- TFA9874_BF_TSTOCP= 0x00c0, /*!< OCP testing control */
- TFA9874_BF_MANSCONF= 0x0120, /*!< I2C configured */
- TFA9874_BF_MANAOOSC= 0x0140, /*!< Internal osc off at PWDN */
- TFA9874_BF_MUTETO= 0x01d0, /*!< Time out SB mute sequence */
- TFA9874_BF_OPENMTP= 0x01e0, /*!< Control for FAIM protection */
- TFA9874_BF_AUDFS = 0x0203, /*!< Sample rate (fs) */
- TFA9874_BF_INPLEV= 0x0240, /*!< TDM output attenuation */
- TFA9874_BF_FRACTDEL= 0x0255, /*!< V/I Fractional delay */
- TFA9874_BF_REV = 0x030f, /*!< Revision info */
- TFA9874_BF_REFCKEXT= 0x0401, /*!< PLL external ref clock */
- TFA9874_BF_REFCKSEL= 0x0420, /*!< PLL internal ref clock */
- TFA9874_BF_SSFAIME= 0x05c0, /*!< Sub-system FAIM */
- TFA9874_BF_AMPOCRT= 0x0802, /*!< Amplifier on-off criteria for shutdown */
- TFA9874_BF_VDDS = 0x1000, /*!< POR */
- TFA9874_BF_DCOCPOK= 0x1010, /*!< DCDC OCP nmos (sticky register , clear on read) */
- TFA9874_BF_OTDS = 0x1020, /*!< OTP alarm (sticky register , clear on read) */
- TFA9874_BF_OCDS = 0x1030, /*!< OCP amplifier (sticky register , clear on read) */
- TFA9874_BF_UVDS = 0x1040, /*!< UVP alarm (sticky register , clear on read) */
- TFA9874_BF_MANALARM= 0x1050, /*!< Alarm state */
- TFA9874_BF_TDMERR= 0x1060, /*!< TDM error */
- TFA9874_BF_NOCLK = 0x1070, /*!< Lost clock (sticky register , clear on read) */
- TFA9874_BF_DCIL = 0x1100, /*!< DCDC current limiting */
- TFA9874_BF_DCDCA = 0x1110, /*!< DCDC active (sticky register , clear on read) */
- TFA9874_BF_DCHVBAT= 0x1130, /*!< DCDC level 1x */
- TFA9874_BF_DCH114= 0x1140, /*!< DCDC level 1.14x */
- TFA9874_BF_DCH107= 0x1150, /*!< DCDC level 1.07x */
- TFA9874_BF_PLLS = 0x1160, /*!< PLL lock */
- TFA9874_BF_CLKS = 0x1170, /*!< Clocks stable */
- TFA9874_BF_TDMLUTER= 0x1180, /*!< TDM LUT error */
- TFA9874_BF_TDMSTAT= 0x1192, /*!< TDM status bits */
- TFA9874_BF_MTPB = 0x11c0, /*!< MTP busy */
- TFA9874_BF_SWS = 0x11d0, /*!< Amplifier engage */
- TFA9874_BF_AMPS = 0x11e0, /*!< Amplifier enable */
- TFA9874_BF_AREFS = 0x11f0, /*!< References enable */
- TFA9874_BF_OCPOAP= 0x1300, /*!< OCPOK pmos A */
- TFA9874_BF_OCPOAN= 0x1310, /*!< OCPOK nmos A */
- TFA9874_BF_OCPOBP= 0x1320, /*!< OCPOK pmos B */
- TFA9874_BF_OCPOBN= 0x1330, /*!< OCPOK nmos B */
- TFA9874_BF_OVDS = 0x1380, /*!< OVP alarm */
- TFA9874_BF_CLIPS = 0x1390, /*!< Amplifier clipping */
- TFA9874_BF_ADCCR = 0x13a0, /*!< Control ADC */
- TFA9874_BF_MANWAIT1= 0x13c0, /*!< Wait HW I2C settings */
- TFA9874_BF_MANMUTE= 0x13e0, /*!< Audio mute sequence */
- TFA9874_BF_MANOPER= 0x13f0, /*!< Operating state */
- TFA9874_BF_CLKOOR= 0x1420, /*!< External clock status */
- TFA9874_BF_MANSTATE= 0x1433, /*!< Device manager status */
- TFA9874_BF_DCMODE= 0x1471, /*!< DCDC mode status bits */
- TFA9874_BF_BATS = 0x1509, /*!< Battery voltage (V) */
- TFA9874_BF_TEMPS = 0x1608, /*!< IC Temperature (C) */
- TFA9874_BF_VDDPS = 0x1709, /*!< IC VDDP voltage ( 1023*VDDP/13 V) */
- TFA9874_BF_TDME = 0x2040, /*!< Enable interface */
- TFA9874_BF_TDMMODE= 0x2050, /*!< Slave/master */
- TFA9874_BF_TDMCLINV= 0x2060, /*!< Reception data to BCK clock */
- TFA9874_BF_TDMFSLN= 0x2073, /*!< FS length (master mode only) */
- TFA9874_BF_TDMFSPOL= 0x20b0, /*!< FS polarity */
- TFA9874_BF_TDMNBCK= 0x20c3, /*!< N-BCK's in FS */
- TFA9874_BF_TDMSLOTS= 0x2103, /*!< N-slots in Frame */
- TFA9874_BF_TDMSLLN= 0x2144, /*!< N-bits in slot */
- TFA9874_BF_TDMBRMG= 0x2194, /*!< N-bits remaining */
- TFA9874_BF_TDMDEL= 0x21e0, /*!< data delay to FS */
- TFA9874_BF_TDMADJ= 0x21f0, /*!< data adjustment */
- TFA9874_BF_TDMOOMP= 0x2201, /*!< Received audio compression */
- TFA9874_BF_TDMSSIZE= 0x2224, /*!< Sample size per slot */
- TFA9874_BF_TDMTXDFO= 0x2271, /*!< Format unused bits */
- TFA9874_BF_TDMTXUS0= 0x2291, /*!< Format unused slots DATAO */
- TFA9874_BF_TDMSPKE= 0x2300, /*!< Control audio tdm channel in 0 (spkr + dcdc) */
- TFA9874_BF_TDMDCE= 0x2310, /*!< Control audio tdm channel in 1 (dcdc) */
- TFA9874_BF_TDMCSE= 0x2330, /*!< current sense vbat temperature and vddp feedback */
- TFA9874_BF_TDMVSE= 0x2340, /*!< Voltage sense vbat temperature and vddp feedback */
- TFA9874_BF_TDMSPKS= 0x2603, /*!< tdm slot for sink 0 (speaker + dcdc) */
- TFA9874_BF_TDMDCS= 0x2643, /*!< tdm slot for sink 1 (dcdc) */
- TFA9874_BF_TDMCSS= 0x26c3, /*!< Slot Position of current sense vbat temperature and vddp feedback */
- TFA9874_BF_TDMVSS= 0x2703, /*!< Slot Position of Voltage sense vbat temperature and vddp feedback */
- TFA9874_BF_ISTVDDS= 0x4000, /*!< Status POR */
- TFA9874_BF_ISTBSTOC= 0x4010, /*!< Status DCDC OCP */
- TFA9874_BF_ISTOTDS= 0x4020, /*!< Status OTP alarm */
- TFA9874_BF_ISTOCPR= 0x4030, /*!< Status ocp alarm */
- TFA9874_BF_ISTUVDS= 0x4040, /*!< Status UVP alarm */
- TFA9874_BF_ISTMANALARM= 0x4050, /*!< Status nanager Alarm state */
- TFA9874_BF_ISTTDMER= 0x4060, /*!< Status tdm error */
- TFA9874_BF_ISTNOCLK= 0x4070, /*!< Status lost clock */
- TFA9874_BF_ICLVDDS= 0x4400, /*!< Clear POR */
- TFA9874_BF_ICLBSTOC= 0x4410, /*!< Clear DCDC OCP */
- TFA9874_BF_ICLOTDS= 0x4420, /*!< Clear OTP alarm */
- TFA9874_BF_ICLOCPR= 0x4430, /*!< Clear ocp alarm */
- TFA9874_BF_ICLUVDS= 0x4440, /*!< Clear UVP alarm */
- TFA9874_BF_ICLMANALARM= 0x4450, /*!< clear nanager Alarm state */
- TFA9874_BF_ICLTDMER= 0x4460, /*!< Clear tdm error */
- TFA9874_BF_ICLNOCLK= 0x4470, /*!< Clear lost clk */
- TFA9874_BF_IEVDDS= 0x4800, /*!< Enable por */
- TFA9874_BF_IEBSTOC= 0x4810, /*!< Enable DCDC OCP */
- TFA9874_BF_IEOTDS= 0x4820, /*!< Enable OTP alarm */
- TFA9874_BF_IEOCPR= 0x4830, /*!< Enable ocp alarm */
- TFA9874_BF_IEUVDS= 0x4840, /*!< Enable UVP alarm */
- TFA9874_BF_IEMANALARM= 0x4850, /*!< Enable nanager Alarm state */
- TFA9874_BF_IETDMER= 0x4860, /*!< Enable tdm error */
- TFA9874_BF_IENOCLK= 0x4870, /*!< Enable lost clk */
- TFA9874_BF_IPOVDDS= 0x4c00, /*!< Polarity por */
- TFA9874_BF_IPOBSTOC= 0x4c10, /*!< Polarity DCDC OCP */
- TFA9874_BF_IPOOTDS= 0x4c20, /*!< Polarity OTP alarm */
- TFA9874_BF_IPOOCPR= 0x4c30, /*!< Polarity ocp alarm */
- TFA9874_BF_IPOUVDS= 0x4c40, /*!< Polarity UVP alarm */
- TFA9874_BF_IPOMANALARM= 0x4c50, /*!< Polarity nanager Alarm state */
- TFA9874_BF_IPOTDMER= 0x4c60, /*!< Polarity tdm error */
- TFA9874_BF_IPONOCLK= 0x4c70, /*!< Polarity lost clk */
- TFA9874_BF_BSSCR = 0x5001, /*!< Battery Safeguard attack time */
- TFA9874_BF_BSST = 0x5023, /*!< Battery Safeguard threshold voltage level */
- TFA9874_BF_BSSRL = 0x5061, /*!< Battery Safeguard maximum reduction */
- TFA9874_BF_VBATFLTL= 0x5080, /*!< vbat filter limit */
- TFA9874_BF_BSSR = 0x50e0, /*!< Battery voltage read out */
- TFA9874_BF_BSSBY = 0x50f0, /*!< Bypass battery safeguard */
- TFA9874_BF_BSSS = 0x5100, /*!< Vbat prot steepness */
- TFA9874_BF_HPFBYP= 0x5150, /*!< Bypass HPF */
- TFA9874_BF_DPSA = 0x5170, /*!< Enable DPSA */
- TFA9874_BF_CLIPCTRL= 0x5222, /*!< Clip control setting */
- TFA9874_BF_AMPGAIN= 0x5257, /*!< Amplifier gain */
- TFA9874_BF_SLOPEE= 0x52d0, /*!< Enables slope control */
- TFA9874_BF_SLOPESET= 0x52e0, /*!< Slope speed setting (bin. coded) */
- TFA9874_BF_TDMDCG= 0x6123, /*!< Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE) */
- TFA9874_BF_TDMSPKG= 0x6163, /*!< Total gain depending on INPLEV setting (channel 0) */
- TFA9874_BF_LNMODE= 0x62e1, /*!< ctrl select mode */
- TFA9874_BF_LPM1MODE= 0x64e1, /*!< low power mode control */
- TFA9874_BF_TDMSRCMAP= 0x6802, /*!< tdm source mapping */
- TFA9874_BF_TDMSRCAS= 0x6831, /*!< Sensed value A */
- TFA9874_BF_TDMSRCBS= 0x6851, /*!< Sensed value B */
- TFA9874_BF_TDMSRCACLIP= 0x6871, /*!< clip information (analog /digital) for source0 */
- TFA9874_BF_TDMSRCBCLIP= 0x6891, /*!< clip information (analog /digital) for source1 */
- TFA9874_BF_LP1 = 0x6e10, /*!< low power mode 1 detection */
- TFA9874_BF_LA = 0x6e20, /*!< low amplitude detection */
- TFA9874_BF_VDDPH = 0x6e30, /*!< vddp greater than vbat */
- TFA9874_BF_DELCURCOMP= 0x6f02, /*!< delay to allign compensation signal with current sense signal */
- TFA9874_BF_SIGCURCOMP= 0x6f40, /*!< polarity of compensation for current sense */
- TFA9874_BF_ENCURCOMP= 0x6f50, /*!< enable current sense compensation */
- TFA9874_BF_LVLCLPPWM= 0x6f72, /*!< set the amount of pwm pulse that may be skipped before clip-flag is triggered */
- TFA9874_BF_DCMCC = 0x7033, /*!< Max coil current */
- TFA9874_BF_DCCV = 0x7071, /*!< Slope compensation current, represents LxF (inductance x frequency) value */
- TFA9874_BF_DCIE = 0x7090, /*!< Adaptive boost mode */
- TFA9874_BF_DCSR = 0x70a0, /*!< Soft ramp up/down */
- TFA9874_BF_DCDIS = 0x70e0, /*!< DCDC on/off */
- TFA9874_BF_DCPWM = 0x70f0, /*!< DCDC PWM only mode */
- TFA9874_BF_DCTRACK= 0x7430, /*!< Boost algorithm selection, effective only when boost_intelligent is set to 1 */
- TFA9874_BF_DCTRIP= 0x7444, /*!< 1st Adaptive boost trip levels, effective only when DCIE is set to 1 */
- TFA9874_BF_DCHOLD= 0x7494, /*!< Hold time for DCDC booster, effective only when boost_intelligent is set to 1 */
- TFA9874_BF_DCINT = 0x74e0, /*!< Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1 */
- TFA9874_BF_DCTRIP2= 0x7534, /*!< 2nd Adaptive boost trip levels, effective only when DCIE is set to 1 */
- TFA9874_BF_DCTRIPT= 0x7584, /*!< Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1 */
- TFA9874_BF_DCTRIPHYSTE= 0x75f0, /*!< Enable hysteresis on booster trip levels */
- TFA9874_BF_DCVOF = 0x7635, /*!< First boost voltage level */
- TFA9874_BF_DCVOS = 0x7695, /*!< Second boost voltage level */
- TFA9874_BF_MTPK = 0xa107, /*!< MTP KEY2 register */
- TFA9874_BF_KEY1LOCKED= 0xa200, /*!< Indicates KEY1 is locked */
- TFA9874_BF_KEY2LOCKED= 0xa210, /*!< Indicates KEY2 is locked */
- TFA9874_BF_CIMTP = 0xa360, /*!< Start copying data from I2C mtp registers to mtp */
- TFA9874_BF_MTPRDMSB= 0xa50f, /*!< MSB word of MTP manual read data */
- TFA9874_BF_MTPRDLSB= 0xa60f, /*!< LSB word of MTP manual read data */
- TFA9874_BF_EXTTS = 0xb108, /*!< External temperature (C) */
- TFA9874_BF_TROS = 0xb190, /*!< Select temp Speaker calibration */
- TFA9874_BF_SWPROFIL= 0xee0f, /*!< Software profile data */
- TFA9874_BF_SWVSTEP= 0xef0f, /*!< Software vstep information */
- TFA9874_BF_MTPOTC= 0xf000, /*!< Calibration schedule */
- TFA9874_BF_MTPEX = 0xf010, /*!< Calibration Ron executed */
- TFA9874_BF_DCMCCAPI= 0xf020, /*!< Calibration current limit DCDC */
- TFA9874_BF_DCMCCSB= 0xf030, /*!< Sign bit for delta calibration current limit DCDC */
- TFA9874_BF_USERDEF= 0xf042, /*!< Calibration delta current limit DCDC */
- TFA9874_BF_CUSTINFO= 0xf078, /*!< Reserved space for allowing customer to store speaker information */
- TFA9874_BF_R25C = 0xf50f, /*!< Ron resistance of speaker coil */
-} nxpTfa9874BfEnumList_t;
-#define TFA9874_NAMETABLE static tfaBfName_t Tfa9874DatasheetNames[]= {\
- { 0x0, "PWDN"}, /* Powerdown selection , */\
- { 0x10, "I2CR"}, /* I2C Reset - Auto clear , */\
- { 0x30, "AMPE"}, /* Activate Amplifier , */\
- { 0x40, "DCA"}, /* Activate DC-to-DC converter , */\
- { 0x71, "INTP"}, /* Interrupt config , */\
- { 0xb0, "BYPOCP"}, /* Bypass OCP , */\
- { 0xc0, "TSTOCP"}, /* OCP testing control , */\
- { 0x120, "MANSCONF"}, /* I2C configured , */\
- { 0x140, "MANAOOSC"}, /* Internal osc off at PWDN , */\
- { 0x1d0, "MUTETO"}, /* Time out SB mute sequence , */\
- { 0x1e0, "OPENMTP"}, /* Control for FAIM protection , */\
- { 0x203, "AUDFS"}, /* Sample rate (fs) , */\
- { 0x240, "INPLEV"}, /* TDM output attenuation , */\
- { 0x255, "FRACTDEL"}, /* V/I Fractional delay , */\
- { 0x30f, "REV"}, /* Revision info , */\
- { 0x401, "REFCKEXT"}, /* PLL external ref clock , */\
- { 0x420, "REFCKSEL"}, /* PLL internal ref clock , */\
- { 0x5c0, "SSFAIME"}, /* Sub-system FAIM , */\
- { 0x802, "AMPOCRT"}, /* Amplifier on-off criteria for shutdown , */\
- { 0x1000, "VDDS"}, /* POR , */\
- { 0x1010, "DCOCPOK"}, /* DCDC OCP nmos (sticky register , clear on read) , */\
- { 0x1020, "OTDS"}, /* OTP alarm (sticky register , clear on read) , */\
- { 0x1030, "OCDS"}, /* OCP amplifier (sticky register , clear on read), */\
- { 0x1040, "UVDS"}, /* UVP alarm (sticky register , clear on read) , */\
- { 0x1050, "MANALARM"}, /* Alarm state , */\
- { 0x1060, "TDMERR"}, /* TDM error , */\
- { 0x1070, "NOCLK"}, /* Lost clock (sticky register , clear on read) , */\
- { 0x1100, "DCIL"}, /* DCDC current limiting , */\
- { 0x1110, "DCDCA"}, /* DCDC active (sticky register , clear on read) , */\
- { 0x1130, "DCHVBAT"}, /* DCDC level 1x , */\
- { 0x1140, "DCH114"}, /* DCDC level 1.14x , */\
- { 0x1150, "DCH107"}, /* DCDC level 1.07x , */\
- { 0x1160, "PLLS"}, /* PLL lock , */\
- { 0x1170, "CLKS"}, /* Clocks stable , */\
- { 0x1180, "TDMLUTER"}, /* TDM LUT error , */\
- { 0x1192, "TDMSTAT"}, /* TDM status bits , */\
- { 0x11c0, "MTPB"}, /* MTP busy , */\
- { 0x11d0, "SWS"}, /* Amplifier engage , */\
- { 0x11e0, "AMPS"}, /* Amplifier enable , */\
- { 0x11f0, "AREFS"}, /* References enable , */\
- { 0x1300, "OCPOAP"}, /* OCPOK pmos A , */\
- { 0x1310, "OCPOAN"}, /* OCPOK nmos A , */\
- { 0x1320, "OCPOBP"}, /* OCPOK pmos B , */\
- { 0x1330, "OCPOBN"}, /* OCPOK nmos B , */\
- { 0x1380, "OVDS"}, /* OVP alarm , */\
- { 0x1390, "CLIPS"}, /* Amplifier clipping , */\
- { 0x13a0, "ADCCR"}, /* Control ADC , */\
- { 0x13c0, "MANWAIT1"}, /* Wait HW I2C settings , */\
- { 0x13e0, "MANMUTE"}, /* Audio mute sequence , */\
- { 0x13f0, "MANOPER"}, /* Operating state , */\
- { 0x1420, "CLKOOR"}, /* External clock status , */\
- { 0x1433, "MANSTATE"}, /* Device manager status , */\
- { 0x1471, "DCMODE"}, /* DCDC mode status bits , */\
- { 0x1509, "BATS"}, /* Battery voltage (V) , */\
- { 0x1608, "TEMPS"}, /* IC Temperature (C) , */\
- { 0x1709, "VDDPS"}, /* IC VDDP voltage ( 1023*VDDP/13 V) , */\
- { 0x2040, "TDME"}, /* Enable interface , */\
- { 0x2050, "TDMMODE"}, /* Slave/master , */\
- { 0x2060, "TDMCLINV"}, /* Reception data to BCK clock , */\
- { 0x2073, "TDMFSLN"}, /* FS length (master mode only) , */\
- { 0x20b0, "TDMFSPOL"}, /* FS polarity , */\
- { 0x20c3, "TDMNBCK"}, /* N-BCK's in FS , */\
- { 0x2103, "TDMSLOTS"}, /* N-slots in Frame , */\
- { 0x2144, "TDMSLLN"}, /* N-bits in slot , */\
- { 0x2194, "TDMBRMG"}, /* N-bits remaining , */\
- { 0x21e0, "TDMDEL"}, /* data delay to FS , */\
- { 0x21f0, "TDMADJ"}, /* data adjustment , */\
- { 0x2201, "TDMOOMP"}, /* Received audio compression , */\
- { 0x2224, "TDMSSIZE"}, /* Sample size per slot , */\
- { 0x2271, "TDMTXDFO"}, /* Format unused bits , */\
- { 0x2291, "TDMTXUS0"}, /* Format unused slots DATAO , */\
- { 0x2300, "TDMSPKE"}, /* Control audio tdm channel in 0 (spkr + dcdc) , */\
- { 0x2310, "TDMDCE"}, /* Control audio tdm channel in 1 (dcdc) , */\
- { 0x2330, "TDMCSE"}, /* current sense vbat temperature and vddp feedback , */\
- { 0x2340, "TDMVSE"}, /* Voltage sense vbat temperature and vddp feedback , */\
- { 0x2603, "TDMSPKS"}, /* tdm slot for sink 0 (speaker + dcdc) , */\
- { 0x2643, "TDMDCS"}, /* tdm slot for sink 1 (dcdc) , */\
- { 0x26c3, "TDMCSS"}, /* Slot Position of current sense vbat temperature and vddp feedback, */\
- { 0x2703, "TDMVSS"}, /* Slot Position of Voltage sense vbat temperature and vddp feedback, */\
- { 0x4000, "ISTVDDS"}, /* Status POR , */\
- { 0x4010, "ISTBSTOC"}, /* Status DCDC OCP , */\
- { 0x4020, "ISTOTDS"}, /* Status OTP alarm , */\
- { 0x4030, "ISTOCPR"}, /* Status ocp alarm , */\
- { 0x4040, "ISTUVDS"}, /* Status UVP alarm , */\
- { 0x4050, "ISTMANALARM"}, /* Status nanager Alarm state , */\
- { 0x4060, "ISTTDMER"}, /* Status tdm error , */\
- { 0x4070, "ISTNOCLK"}, /* Status lost clock , */\
- { 0x4400, "ICLVDDS"}, /* Clear POR , */\
- { 0x4410, "ICLBSTOC"}, /* Clear DCDC OCP , */\
- { 0x4420, "ICLOTDS"}, /* Clear OTP alarm , */\
- { 0x4430, "ICLOCPR"}, /* Clear ocp alarm , */\
- { 0x4440, "ICLUVDS"}, /* Clear UVP alarm , */\
- { 0x4450, "ICLMANALARM"}, /* clear nanager Alarm state , */\
- { 0x4460, "ICLTDMER"}, /* Clear tdm error , */\
- { 0x4470, "ICLNOCLK"}, /* Clear lost clk , */\
- { 0x4800, "IEVDDS"}, /* Enable por , */\
- { 0x4810, "IEBSTOC"}, /* Enable DCDC OCP , */\
- { 0x4820, "IEOTDS"}, /* Enable OTP alarm , */\
- { 0x4830, "IEOCPR"}, /* Enable ocp alarm , */\
- { 0x4840, "IEUVDS"}, /* Enable UVP alarm , */\
- { 0x4850, "IEMANALARM"}, /* Enable nanager Alarm state , */\
- { 0x4860, "IETDMER"}, /* Enable tdm error , */\
- { 0x4870, "IENOCLK"}, /* Enable lost clk , */\
- { 0x4c00, "IPOVDDS"}, /* Polarity por , */\
- { 0x4c10, "IPOBSTOC"}, /* Polarity DCDC OCP , */\
- { 0x4c20, "IPOOTDS"}, /* Polarity OTP alarm , */\
- { 0x4c30, "IPOOCPR"}, /* Polarity ocp alarm , */\
- { 0x4c40, "IPOUVDS"}, /* Polarity UVP alarm , */\
- { 0x4c50, "IPOMANALARM"}, /* Polarity nanager Alarm state , */\
- { 0x4c60, "IPOTDMER"}, /* Polarity tdm error , */\
- { 0x4c70, "IPONOCLK"}, /* Polarity lost clk , */\
- { 0x5001, "BSSCR"}, /* Battery Safeguard attack time , */\
- { 0x5023, "BSST"}, /* Battery Safeguard threshold voltage level , */\
- { 0x5061, "BSSRL"}, /* Battery Safeguard maximum reduction , */\
- { 0x5080, "VBATFLTL"}, /* vbat filter limit , */\
- { 0x50e0, "BSSR"}, /* Battery voltage read out , */\
- { 0x50f0, "BSSBY"}, /* Bypass battery safeguard , */\
- { 0x5100, "BSSS"}, /* Vbat prot steepness , */\
- { 0x5150, "HPFBYP"}, /* Bypass HPF , */\
- { 0x5170, "DPSA"}, /* Enable DPSA , */\
- { 0x5222, "CLIPCTRL"}, /* Clip control setting , */\
- { 0x5257, "AMPGAIN"}, /* Amplifier gain , */\
- { 0x52d0, "SLOPEE"}, /* Enables slope control , */\
- { 0x52e0, "SLOPESET"}, /* Slope speed setting (bin. coded) , */\
- { 0x6123, "TDMDCG"}, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */\
- { 0x6163, "TDMSPKG"}, /* Total gain depending on INPLEV setting (channel 0), */\
- { 0x62e1, "LNMODE"}, /* ctrl select mode , */\
- { 0x64e1, "LPM1MODE"}, /* low power mode control , */\
- { 0x6802, "TDMSRCMAP"}, /* tdm source mapping , */\
- { 0x6831, "TDMSRCAS"}, /* Sensed value A , */\
- { 0x6851, "TDMSRCBS"}, /* Sensed value B , */\
- { 0x6871, "TDMSRCACLIP"}, /* clip information (analog /digital) for source0 , */\
- { 0x6891, "TDMSRCBCLIP"}, /* clip information (analog /digital) for source1 , */\
- { 0x6e10, "LP1"}, /* low power mode 1 detection , */\
- { 0x6e20, "LA"}, /* low amplitude detection , */\
- { 0x6e30, "VDDPH"}, /* vddp greater than vbat , */\
- { 0x6f02, "DELCURCOMP"}, /* delay to allign compensation signal with current sense signal, */\
- { 0x6f40, "SIGCURCOMP"}, /* polarity of compensation for current sense , */\
- { 0x6f50, "ENCURCOMP"}, /* enable current sense compensation , */\
- { 0x6f72, "LVLCLPPWM"}, /* set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
- { 0x7033, "DCMCC"}, /* Max coil current , */\
- { 0x7071, "DCCV"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
- { 0x7090, "DCIE"}, /* Adaptive boost mode , */\
- { 0x70a0, "DCSR"}, /* Soft ramp up/down , */\
- { 0x70e0, "DCDIS"}, /* DCDC on/off , */\
- { 0x70f0, "DCPWM"}, /* DCDC PWM only mode , */\
- { 0x7430, "DCTRACK"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
- { 0x7444, "DCTRIP"}, /* 1st Adaptive boost trip levels, effective only when DCIE is set to 1, */\
- { 0x7494, "DCHOLD"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
- { 0x74e0, "DCINT"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
- { 0x7534, "DCTRIP2"}, /* 2nd Adaptive boost trip levels, effective only when DCIE is set to 1, */\
- { 0x7584, "DCTRIPT"}, /* Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
- { 0x75f0, "DCTRIPHYSTE"}, /* Enable hysteresis on booster trip levels , */\
- { 0x7635, "DCVOF"}, /* First boost voltage level , */\
- { 0x7695, "DCVOS"}, /* Second boost voltage level , */\
- { 0xa107, "MTPK"}, /* MTP KEY2 register , */\
- { 0xa200, "KEY1LOCKED"}, /* Indicates KEY1 is locked , */\
- { 0xa210, "KEY2LOCKED"}, /* Indicates KEY2 is locked , */\
- { 0xa360, "CIMTP"}, /* Start copying data from I2C mtp registers to mtp , */\
- { 0xa50f, "MTPRDMSB"}, /* MSB word of MTP manual read data , */\
- { 0xa60f, "MTPRDLSB"}, /* LSB word of MTP manual read data , */\
- { 0xb108, "EXTTS"}, /* External temperature (C) , */\
- { 0xb190, "TROS"}, /* Select temp Speaker calibration , */\
- { 0xee0f, "SWPROFIL"}, /* Software profile data , */\
- { 0xef0f, "SWVSTEP"}, /* Software vstep information , */\
- { 0xf000, "MTPOTC"}, /* Calibration schedule , */\
- { 0xf010, "MTPEX"}, /* Calibration Ron executed , */\
- { 0xf020, "DCMCCAPI"}, /* Calibration current limit DCDC , */\
- { 0xf030, "DCMCCSB"}, /* Sign bit for delta calibration current limit DCDC , */\
- { 0xf042, "USERDEF"}, /* Calibration delta current limit DCDC , */\
- { 0xf078, "CUSTINFO"}, /* Reserved space for allowing customer to store speaker information, */\
- { 0xf50f, "R25C"}, /* Ron resistance of speaker coil , */\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-
-#define TFA9874_BITNAMETABLE static tfaBfName_t Tfa9874BitNames[]= {\
- { 0x0, "powerdown"}, /* Powerdown selection , */\
- { 0x10, "reset"}, /* I2C Reset - Auto clear , */\
- { 0x30, "enbl_amplifier"}, /* Activate Amplifier , */\
- { 0x40, "enbl_boost"}, /* Activate DC-to-DC converter , */\
- { 0x71, "int_pad_io"}, /* Interrupt config , */\
- { 0xb0, "bypass_ocp"}, /* Bypass OCP , */\
- { 0xc0, "test_ocp"}, /* OCP testing control , */\
- { 0x120, "src_set_configured"}, /* I2C configured , */\
- { 0x140, "enbl_osc1m_auto_off"}, /* Internal osc off at PWDN , */\
- { 0x1d0, "disable_mute_time_out"}, /* Time out SB mute sequence , */\
- { 0x1e0, "unprotect_faim"}, /* Control for FAIM protection , */\
- { 0x203, "audio_fs"}, /* Sample rate (fs) , */\
- { 0x240, "input_level"}, /* TDM output attenuation , */\
- { 0x255, "cs_frac_delay"}, /* V/I Fractional delay , */\
- { 0x2d0, "sel_hysteresis"}, /* Select hysteresis for clock range detector , */\
- { 0x30f, "device_rev"}, /* Revision info , */\
- { 0x401, "pll_clkin_sel"}, /* PLL external ref clock , */\
- { 0x420, "pll_clkin_sel_osc"}, /* PLL internal ref clock , */\
- { 0x5c0, "enbl_faim_ss"}, /* Sub-system FAIM , */\
- { 0x802, "ctrl_on2off_criterion"}, /* Amplifier on-off criteria for shutdown , */\
- { 0xe07, "ctrl_digtoana"}, /* Spare control from digital to analog , */\
- { 0xf0f, "hidden_code"}, /* 5A6Bh, 23147d to access registers (default for engineering), */\
- { 0x1000, "flag_por"}, /* POR , */\
- { 0x1010, "flag_bst_ocpok"}, /* DCDC OCP nmos (sticky register , clear on read) , */\
- { 0x1020, "flag_otpok"}, /* OTP alarm (sticky register , clear on read) , */\
- { 0x1030, "flag_ocp_alarm"}, /* OCP amplifier (sticky register , clear on read), */\
- { 0x1040, "flag_uvpok"}, /* UVP alarm (sticky register , clear on read) , */\
- { 0x1050, "flag_man_alarm_state"}, /* Alarm state , */\
- { 0x1060, "flag_tdm_error"}, /* TDM error , */\
- { 0x1070, "flag_lost_clk"}, /* Lost clock (sticky register , clear on read) , */\
- { 0x1100, "flag_bst_bstcur"}, /* DCDC current limiting , */\
- { 0x1110, "flag_bst_hiz"}, /* DCDC active (sticky register , clear on read) , */\
- { 0x1120, "flag_bst_peakcur"}, /* Indicates current is max in DC-to-DC converter , */\
- { 0x1130, "flag_bst_voutcomp"}, /* DCDC level 1x , */\
- { 0x1140, "flag_bst_voutcomp86"}, /* DCDC level 1.14x , */\
- { 0x1150, "flag_bst_voutcomp93"}, /* DCDC level 1.07x , */\
- { 0x1160, "flag_pll_lock"}, /* PLL lock , */\
- { 0x1170, "flag_clocks_stable"}, /* Clocks stable , */\
- { 0x1180, "flag_tdm_lut_error"}, /* TDM LUT error , */\
- { 0x1192, "flag_tdm_status"}, /* TDM status bits , */\
- { 0x11c0, "flag_mtp_busy"}, /* MTP busy , */\
- { 0x11d0, "flag_engage"}, /* Amplifier engage , */\
- { 0x11e0, "flag_enbl_amp"}, /* Amplifier enable , */\
- { 0x11f0, "flag_enbl_ref"}, /* References enable , */\
- { 0x1300, "flag_ocpokap"}, /* OCPOK pmos A , */\
- { 0x1310, "flag_ocpokan"}, /* OCPOK nmos A , */\
- { 0x1320, "flag_ocpokbp"}, /* OCPOK pmos B , */\
- { 0x1330, "flag_ocpokbn"}, /* OCPOK nmos B , */\
- { 0x1380, "flag_ovpok"}, /* OVP alarm , */\
- { 0x1390, "flag_clip"}, /* Amplifier clipping , */\
- { 0x13a0, "flag_adc10_ready"}, /* Control ADC , */\
- { 0x13c0, "flag_man_wait_src_settings"}, /* Wait HW I2C settings , */\
- { 0x13e0, "flag_man_start_mute_audio"}, /* Audio mute sequence , */\
- { 0x13f0, "flag_man_operating_state"}, /* Operating state , */\
- { 0x1420, "flag_clk_out_of_range"}, /* External clock status , */\
- { 0x1433, "man_state"}, /* Device manager status , */\
- { 0x1471, "status_bst_mode"}, /* DCDC mode status bits , */\
- { 0x1509, "bat_adc"}, /* Battery voltage (V) , */\
- { 0x1608, "temp_adc"}, /* IC Temperature (C) , */\
- { 0x1709, "vddp_adc"}, /* IC VDDP voltage ( 1023*VDDP/13 V) , */\
- { 0x2040, "tdm_enable"}, /* Enable interface , */\
- { 0x2050, "tdm_mode"}, /* Slave/master , */\
- { 0x2060, "tdm_clk_inversion"}, /* Reception data to BCK clock , */\
- { 0x2073, "tdm_fs_ws_length"}, /* FS length (master mode only) , */\
- { 0x20b0, "tdm_fs_ws_polarity"}, /* FS polarity , */\
- { 0x20c3, "tdm_nbck"}, /* N-BCK's in FS , */\
- { 0x2103, "tdm_nb_of_slots"}, /* N-slots in Frame , */\
- { 0x2144, "tdm_slot_length"}, /* N-bits in slot , */\
- { 0x2194, "tdm_bits_remaining"}, /* N-bits remaining , */\
- { 0x21e0, "tdm_data_delay"}, /* data delay to FS , */\
- { 0x21f0, "tdm_data_adjustment"}, /* data adjustment , */\
- { 0x2201, "tdm_audio_sample_compression"}, /* Received audio compression , */\
- { 0x2224, "tdm_sample_size"}, /* Sample size per slot , */\
- { 0x2271, "tdm_txdata_format"}, /* Format unused bits , */\
- { 0x2291, "tdm_txdata_format_unused_slot_sd0"}, /* Format unused slots DATAO , */\
- { 0x2300, "tdm_sink0_enable"}, /* Control audio tdm channel in 0 (spkr + dcdc) , */\
- { 0x2310, "tdm_sink1_enable"}, /* Control audio tdm channel in 1 (dcdc) , */\
- { 0x2330, "tdm_source0_enable"}, /* current sense vbat temperature and vddp feedback , */\
- { 0x2340, "tdm_source1_enable"}, /* Voltage sense vbat temperature and vddp feedback , */\
- { 0x2603, "tdm_sink0_slot"}, /* tdm slot for sink 0 (speaker + dcdc) , */\
- { 0x2643, "tdm_sink1_slot"}, /* tdm slot for sink 1 (dcdc) , */\
- { 0x26c3, "tdm_source0_slot"}, /* Slot Position of current sense vbat temperature and vddp feedback, */\
- { 0x2703, "tdm_source1_slot"}, /* Slot Position of Voltage sense vbat temperature and vddp feedback, */\
- { 0x4000, "int_out_flag_por"}, /* Status POR , */\
- { 0x4010, "int_out_flag_bst_ocpok"}, /* Status DCDC OCP , */\
- { 0x4020, "int_out_flag_otpok"}, /* Status OTP alarm , */\
- { 0x4030, "int_out_flag_ocp_alarm"}, /* Status ocp alarm , */\
- { 0x4040, "int_out_flag_uvpok"}, /* Status UVP alarm , */\
- { 0x4050, "int_out_flag_man_alarm_state"}, /* Status nanager Alarm state , */\
- { 0x4060, "int_out_flag_tdm_error"}, /* Status tdm error , */\
- { 0x4070, "int_out_flag_lost_clk"}, /* Status lost clock , */\
- { 0x4400, "int_in_flag_por"}, /* Clear POR , */\
- { 0x4410, "int_in_flag_bst_ocpok"}, /* Clear DCDC OCP , */\
- { 0x4420, "int_in_flag_otpok"}, /* Clear OTP alarm , */\
- { 0x4430, "int_in_flag_ocp_alarm"}, /* Clear ocp alarm , */\
- { 0x4440, "int_in_flag_uvpok"}, /* Clear UVP alarm , */\
- { 0x4450, "int_in_flag_man_alarm_state"}, /* clear nanager Alarm state , */\
- { 0x4460, "int_in_flag_tdm_error"}, /* Clear tdm error , */\
- { 0x4470, "int_in_flag_lost_clk"}, /* Clear lost clk , */\
- { 0x4800, "int_enable_flag_por"}, /* Enable por , */\
- { 0x4810, "int_enable_flag_bst_ocpok"}, /* Enable DCDC OCP , */\
- { 0x4820, "int_enable_flag_otpok"}, /* Enable OTP alarm , */\
- { 0x4830, "int_enable_flag_ocp_alarm"}, /* Enable ocp alarm , */\
- { 0x4840, "int_enable_flag_uvpok"}, /* Enable UVP alarm , */\
- { 0x4850, "int_enable_flag_man_alarm_state"}, /* Enable nanager Alarm state , */\
- { 0x4860, "int_enable_flag_tdm_error"}, /* Enable tdm error , */\
- { 0x4870, "int_enable_flag_lost_clk"}, /* Enable lost clk , */\
- { 0x4c00, "int_polarity_flag_por"}, /* Polarity por , */\
- { 0x4c10, "int_polarity_flag_bst_ocpok"}, /* Polarity DCDC OCP , */\
- { 0x4c20, "int_polarity_flag_otpok"}, /* Polarity OTP alarm , */\
- { 0x4c30, "int_polarity_flag_ocp_alarm"}, /* Polarity ocp alarm , */\
- { 0x4c40, "int_polarity_flag_uvpok"}, /* Polarity UVP alarm , */\
- { 0x4c50, "int_polarity_flag_man_alarm_state"}, /* Polarity nanager Alarm state , */\
- { 0x4c60, "int_polarity_flag_tdm_error"}, /* Polarity tdm error , */\
- { 0x4c70, "int_polarity_flag_lost_clk"}, /* Polarity lost clk , */\
- { 0x5001, "vbat_prot_attack_time"}, /* Battery Safeguard attack time , */\
- { 0x5023, "vbat_prot_thlevel"}, /* Battery Safeguard threshold voltage level , */\
- { 0x5061, "vbat_prot_max_reduct"}, /* Battery Safeguard maximum reduction , */\
- { 0x5080, "vbat_flt_limit"}, /* vbat filter limit , */\
- { 0x50d0, "rst_min_vbat"}, /* Reset clipper - Auto clear , */\
- { 0x50e0, "sel_vbat"}, /* Battery voltage read out , */\
- { 0x50f0, "bypass_clipper"}, /* Bypass battery safeguard , */\
- { 0x5100, "batsense_steepness"}, /* Vbat prot steepness , */\
- { 0x5150, "bypass_hp"}, /* Bypass HPF , */\
- { 0x5170, "enbl_dpsa"}, /* Enable DPSA , */\
- { 0x5222, "ctrl_cc"}, /* Clip control setting , */\
- { 0x5257, "gain"}, /* Amplifier gain , */\
- { 0x52d0, "ctrl_slopectrl"}, /* Enables slope control , */\
- { 0x52e0, "ctrl_slope"}, /* Slope speed setting (bin. coded) , */\
- { 0x5301, "dpsa_level"}, /* DPSA threshold levels , */\
- { 0x5321, "dpsa_release"}, /* DPSA Release time , */\
- { 0x5340, "clipfast"}, /* Clock selection for HW clipper for Battery Safeguard, */\
- { 0x5350, "bypass_lp"}, /* Bypass the low power filter inside temperature sensor, */\
- { 0x5400, "first_order_mode"}, /* Overrule to 1st order mode of control stage when clipping, */\
- { 0x5410, "bypass_ctrlloop"}, /* Switch amplifier into open loop configuration , */\
- { 0x5430, "icomp_engage"}, /* Engage of icomp , */\
- { 0x5440, "ctrl_kickback"}, /* Prevent double pulses of output stage , */\
- { 0x5450, "icomp_engage_overrule"}, /* To overrule the functional icomp_engage signal during validation, */\
- { 0x5503, "ctrl_dem"}, /* Enable DEM icomp and DEM one bit dac , */\
- { 0x5543, "ctrl_dem_mismatch"}, /* Enable DEM icomp mismatch for testing , */\
- { 0x5582, "dpsa_drive"}, /* Drive setting (bin. coded) , */\
- { 0x5690, "sel_pwm_delay_src"}, /* Control for selection for PWM delay line source , */\
- { 0x56a1, "enbl_odd_up_even_down"}, /* Control for PWM reference sawtooth generartion , */\
- { 0x570a, "enbl_amp"}, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually, */\
- { 0x57b0, "enbl_engage"}, /* Enables/engage power stage and control loop , */\
- { 0x57c0, "enbl_engage_pst"}, /* Enables/engage power stage and control loop , */\
- { 0x5810, "hard_mute"}, /* Hard mute - PWM , */\
- { 0x5820, "pwm_shape"}, /* PWM shape , */\
- { 0x5844, "pwm_delay"}, /* PWM delay bits to set the delay, clockd is 1/(k*2048*fs), */\
- { 0x5890, "reclock_pwm"}, /* Reclock the pwm signal inside analog , */\
- { 0x58a0, "reclock_voltsense"}, /* Reclock the voltage sense pwm signal , */\
- { 0x58c0, "enbl_pwm_phase_shift"}, /* Control for pwm phase shift , */\
- { 0x6123, "ctrl_attl"}, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */\
- { 0x6163, "ctrl_attr"}, /* Total gain depending on INPLEV setting (channel 0), */\
- { 0x6265, "zero_lvl"}, /* low noise gain switch zero trigger level , */\
- { 0x62c1, "ctrl_fb_resistor"}, /* Select amplifier feedback resistor connection , */\
- { 0x62e1, "lownoisegain_mode"}, /* ctrl select mode , */\
- { 0x6305, "threshold_lvl"}, /* low noise gain switch trigger level , */\
- { 0x6365, "hold_time"}, /* ctrl hold time before low audio is reckoned to be low audio, */\
- { 0x6405, "lpm1_cal_offset"}, /* low power mode1 detector ctrl cal_offset from gain module , */\
- { 0x6465, "lpm1_zero_lvl"}, /* low power mode1 zero crossing detection level , */\
- { 0x64e1, "lpm1_mode"}, /* low power mode control , */\
- { 0x6505, "lpm1_threshold_lvl"}, /* low power mode1 amplitude trigger level , */\
- { 0x6565, "lpm1_hold_time"}, /* low power mode1 detector ctrl hold time before low audio is reckoned to be low audio, */\
- { 0x65c0, "disable_low_power_mode"}, /* low power mode1 detector control , */\
- { 0x6600, "dcdc_pfm20khz_limit"}, /* DCDC in PFM mode pwm mode is activated each 50us to force a pwm pulse, */\
- { 0x6611, "dcdc_ctrl_maxzercnt"}, /* DCDC. Number of zero current flags to count before going to pfm mode, */\
- { 0x6656, "dcdc_vbat_delta_detect"}, /* Threshold before booster is reacting on a delta Vbat (in PFM mode) by temporarily switching to PWM mode, */\
- { 0x66c0, "dcdc_ignore_vbat"}, /* Ignore an increase on Vbat , */\
- { 0x6700, "enbl_minion"}, /* Enables minion (small) power stage , */\
- { 0x6713, "vth_vddpvbat"}, /* select vddp-vbat thres signal , */\
- { 0x6750, "lpen_vddpvbat"}, /* select vddp-vbat filtred vs unfiltered compare , */\
- { 0x6761, "ctrl_rfb"}, /* Feedback resistor selection - I2C direct mode , */\
- { 0x6802, "tdm_source_mapping"}, /* tdm source mapping , */\
- { 0x6831, "tdm_sourcea_frame_sel"}, /* Sensed value A , */\
- { 0x6851, "tdm_sourceb_frame_sel"}, /* Sensed value B , */\
- { 0x6871, "tdm_source0_clip_sel"}, /* clip information (analog /digital) for source0 , */\
- { 0x6891, "tdm_source1_clip_sel"}, /* clip information (analog /digital) for source1 , */\
- { 0x6a02, "rst_min_vbat_delay"}, /* rst_min_vbat delay (nb fs) , */\
- { 0x6b00, "disable_auto_engage"}, /* disable auto engange , */\
- { 0x6b10, "disable_engage"}, /* disable engange , */\
- { 0x6c02, "ns_hp2ln_criterion"}, /* 0..7 zeroes at ns as threshold to swap from high_power to low_noise, */\
- { 0x6c32, "ns_ln2hp_criterion"}, /* 0..7 zeroes at ns as threshold to swap from low_noise to high_power, */\
- { 0x6c69, "spare_out"}, /* spare_out , */\
- { 0x6d0f, "spare_in"}, /* spare_in , */\
- { 0x6e10, "flag_lp_detect_mode1"}, /* low power mode 1 detection , */\
- { 0x6e20, "flag_low_amplitude"}, /* low amplitude detection , */\
- { 0x6e30, "flag_vddp_gt_vbat"}, /* vddp greater than vbat , */\
- { 0x6f02, "cursense_comp_delay"}, /* delay to allign compensation signal with current sense signal, */\
- { 0x6f40, "cursense_comp_sign"}, /* polarity of compensation for current sense , */\
- { 0x6f50, "enbl_cursense_comp"}, /* enable current sense compensation , */\
- { 0x6f72, "pwms_clip_lvl"}, /* set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
- { 0x7033, "boost_cur"}, /* Max coil current , */\
- { 0x7071, "bst_slpcmplvl"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
- { 0x7090, "boost_intel"}, /* Adaptive boost mode , */\
- { 0x70a0, "boost_speed"}, /* Soft ramp up/down , */\
- { 0x70e0, "dcdcoff_mode"}, /* DCDC on/off , */\
- { 0x70f0, "dcdc_pwmonly"}, /* DCDC PWM only mode , */\
- { 0x7104, "bst_drive"}, /* Binary coded drive setting for boost converter power stage, */\
- { 0x7151, "bst_scalecur"}, /* For testing direct control scale current , */\
- { 0x7174, "bst_slopecur"}, /* For testing direct control slope current , */\
- { 0x71c1, "bst_slope"}, /* Boost slope speed , */\
- { 0x71e0, "bst_bypass_bstcur"}, /* Bypass control for boost current settings , */\
- { 0x71f0, "bst_bypass_bstfoldback"}, /* Bypass control for boost foldback , */\
- { 0x7200, "enbl_bst_engage"}, /* Enable power stage dcdc controller , */\
- { 0x7210, "enbl_bst_hizcom"}, /* Enable hiz comparator , */\
- { 0x7220, "enbl_bst_peak2avg"}, /* Enable boost peak2avg functionality , */\
- { 0x7230, "enbl_bst_peakcur"}, /* Enable peak current , */\
- { 0x7240, "enbl_bst_power"}, /* Enable line of the powerstage , */\
- { 0x7250, "enbl_bst_slopecur"}, /* Enable bit of max-current dac , */\
- { 0x7260, "enbl_bst_voutcomp"}, /* Enable vout comparators , */\
- { 0x7270, "enbl_bst_voutcomp86"}, /* Enable vout-86 comparators , */\
- { 0x7280, "enbl_bst_voutcomp93"}, /* Enable vout-93 comparators , */\
- { 0x7290, "enbl_bst_windac"}, /* Enable window dac , */\
- { 0x72a5, "bst_windac"}, /* for testing direct control windac , */\
- { 0x7300, "boost_alg"}, /* Control for boost adaptive loop gain , */\
- { 0x7311, "boost_loopgain"}, /* DCDC boost loopgain setting , */\
- { 0x7331, "bst_freq"}, /* DCDC boost frequency control , */\
- { 0x7360, "bst_use_new_zercur_detect"}, /* Enable new zero current detection for boost control, */\
- { 0x7430, "boost_track"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
- { 0x7444, "boost_trip_lvl_1st"}, /* 1st Adaptive boost trip levels, effective only when DCIE is set to 1, */\
- { 0x7494, "boost_hold_time"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
- { 0x74e0, "sel_dcdc_envelope_8fs"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
- { 0x74f0, "ignore_flag_voutcomp86"}, /* Determines the maximum PWM frequency be the most efficient in relation to the Booster inductor value, */\
- { 0x7534, "boost_trip_lvl_2nd"}, /* 2nd Adaptive boost trip levels, effective only when DCIE is set to 1, */\
- { 0x7584, "boost_trip_lvl_track"}, /* Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
- { 0x75f0, "enbl_trip_hyst"}, /* Enable hysteresis on booster trip levels , */\
- { 0x7635, "frst_boost_voltage"}, /* First boost voltage level , */\
- { 0x7695, "scnd_boost_voltage"}, /* Second boost voltage level , */\
- { 0x8001, "sel_clk_cs"}, /* Current sense clock duty cycle control , */\
- { 0x8021, "micadc_speed"}, /* Current sense clock for MiCADC selection - 32/44.1/48 KHz Fs band only, */\
- { 0x8050, "cs_gain_control"}, /* Current sense gain control , */\
- { 0x8060, "cs_bypass_gc"}, /* Bypasses the CS gain correction , */\
- { 0x8087, "cs_gain"}, /* Current sense gain , */\
- { 0x8210, "invertpwm"}, /* Current sense common mode feedback pwm invert control, */\
- { 0x8305, "cs_ktemp"}, /* Current sense temperature compensation trimming (1 - VALUE*TEMP)*signal, */\
- { 0x8364, "cs_ktemp2"}, /* Second order temperature compensation coefficient , */\
- { 0x8400, "cs_adc_bsoinv"}, /* Bitstream inversion for current sense ADC , */\
- { 0x8421, "cs_adc_hifreq"}, /* Frequency mode current sense ADC , */\
- { 0x8440, "cs_adc_nortz"}, /* Return to zero for current sense ADC , */\
- { 0x8453, "cs_adc_offset"}, /* Micadc ADC offset setting , */\
- { 0x8490, "cs_adc_slowdel"}, /* Select delay for current sense ADC (internal decision circuitry), */\
- { 0x84a4, "cs_adc_gain"}, /* Gain setting for current sense ADC (two's complement), */\
- { 0x8500, "cs_resonator_enable"}, /* Enable for resonator to improve SRN , */\
- { 0x8510, "cs_classd_tran_skip"}, /* Skip current sense connection during a classD amplifier transition, */\
- { 0x8530, "cs_inn_short"}, /* Short current sense negative to common mode , */\
- { 0x8540, "cs_inp_short"}, /* Short current sense positive to common mode , */\
- { 0x8550, "cs_ldo_bypass"}, /* Bypass current sense LDO , */\
- { 0x8560, "cs_ldo_pulldown"}, /* Pull down current sense LDO, only valid if left_enbl_cs_ldo is high, */\
- { 0x8574, "cs_ldo_voset"}, /* Current sense LDO voltage level setting (two's complement), */\
- { 0x8700, "enbl_cs_adc"}, /* Enable current sense ADC , */\
- { 0x8710, "enbl_cs_inn1"}, /* Enable connection of current sense negative1 , */\
- { 0x8720, "enbl_cs_inn2"}, /* Enable connection of current sense negative2 , */\
- { 0x8730, "enbl_cs_inp1"}, /* Enable connection of current sense positive1 , */\
- { 0x8740, "enbl_cs_inp2"}, /* Enable connection of current sense positive2 , */\
- { 0x8750, "enbl_cs_ldo"}, /* Enable current sense LDO , */\
- { 0x8780, "enbl_cs_vbatldo"}, /* Enable of current sense LDO , */\
- { 0x8790, "enbl_dc_filter"}, /* Control for enabling the DC blocking filter for voltage and current sense, */\
- { 0x8801, "volsense_pwm_sel"}, /* Voltage sense source selection control , */\
- { 0x8850, "vs_gain_control"}, /* Voltage sense gain control , */\
- { 0x8860, "vs_bypass_gc"}, /* Bypasses the VS gain correction , */\
- { 0x8870, "vs_igen_supply"}, /* Switch internal supply of current generator , */\
- { 0x8887, "vs_gain"}, /* voltage sense gain , */\
- { 0x8c00, "vs_adc_bsoinv"}, /* Bitstream inversion for voltage sense ADC , */\
- { 0x8c40, "vs_adc_nortz"}, /* Return to zero for voltage sense ADC , */\
- { 0x8c90, "vs_adc_slowdel"}, /* Select delay for voltage sense ADC (internal decision circuitry), */\
- { 0x8d10, "vs_classd_tran_skip"}, /* Skip voltage sense connection during a classD amplifier transition, */\
- { 0x8d30, "vs_inn_short"}, /* Short voltage sense negative to common mode , */\
- { 0x8d40, "vs_inp_short"}, /* Short voltage sense positive to common mode , */\
- { 0x8d50, "vs_ldo_bypass"}, /* Bypass voltage sense LDO , */\
- { 0x8d60, "vs_ldo_pulldown"}, /* Pull down voltage sense LDO, only valid if left_enbl_cs_ldo is high, */\
- { 0x8d74, "vs_ldo_voset"}, /* Voltage sense LDO voltage level setting (two's complement), */\
- { 0x8f00, "enbl_vs_adc"}, /* Enable voltage sense ADC (Direct Control only only others done by manager), */\
- { 0x8f10, "enbl_vs_inn1"}, /* Enable connection of voltage sense negative1 , */\
- { 0x8f20, "enbl_vs_inn2"}, /* Enable connection of voltage sense negative2 , */\
- { 0x8f30, "enbl_vs_inp1"}, /* Enable connection of voltage sense positive1 , */\
- { 0x8f40, "enbl_vs_inp2"}, /* Enable connection of voltage sense positive2 , */\
- { 0x8f50, "enbl_vs_ldo"}, /* Enable voltage sense LDO (Direct Control only only others done by manager), */\
- { 0x8f80, "enbl_vs_vbatldo"}, /* Enable of voltage sense LDO (Direct Control only others done by manager), */\
- { 0xa007, "mtpkey1"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
- { 0xa107, "mtpkey2"}, /* MTP KEY2 register , */\
- { 0xa200, "key01_locked"}, /* Indicates KEY1 is locked , */\
- { 0xa210, "key02_locked"}, /* Indicates KEY2 is locked , */\
- { 0xa302, "mtp_man_address_in"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
- { 0xa330, "man_copy_mtp_to_iic"}, /* Start copying single word from mtp to I2C mtp register, */\
- { 0xa340, "man_copy_iic_to_mtp"}, /* Start copying single word from I2C mtp register to mtp, */\
- { 0xa350, "auto_copy_mtp_to_iic"}, /* Start copying all the data from mtp to I2C mtp registers, */\
- { 0xa360, "auto_copy_iic_to_mtp"}, /* Start copying data from I2C mtp registers to mtp , */\
- { 0xa400, "faim_set_clkws"}, /* Sets the faim controller clock wait state register, */\
- { 0xa410, "faim_sel_evenrows"}, /* All even rows of the faim are selected, active high, */\
- { 0xa420, "faim_sel_oddrows"}, /* All odd rows of the faim are selected, all rows in combination with sel_evenrows, */\
- { 0xa430, "faim_program_only"}, /* Skip the erase access at wr_faim command (write-program-marginread), */\
- { 0xa440, "faim_erase_only"}, /* Skip the program access at wr_faim command (write-erase-marginread), */\
- { 0xa50f, "mtp_man_data_out_msb"}, /* MSB word of MTP manual read data , */\
- { 0xa60f, "mtp_man_data_out_lsb"}, /* LSB word of MTP manual read data , */\
- { 0xa70f, "mtp_man_data_in_msb"}, /* MSB word of write data for MTP manual write , */\
- { 0xa80f, "mtp_man_data_in_lsb"}, /* LSB word of write data for MTP manual write , */\
- { 0xb010, "bypass_ocpcounter"}, /* Bypass OCP Counter , */\
- { 0xb020, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
- { 0xb030, "bypass_ovp"}, /* Bypass OVP , */\
- { 0xb040, "bypass_uvp"}, /* Bypass UVP , */\
- { 0xb050, "bypass_otp"}, /* Bypass OTP , */\
- { 0xb060, "bypass_lost_clk"}, /* Bypass lost clock detector , */\
- { 0xb070, "ctrl_vpalarm"}, /* vpalarm (uvp ovp handling) , */\
- { 0xb087, "ocp_threshold"}, /* OCP threshold level , */\
- { 0xb108, "ext_temp"}, /* External temperature (C) , */\
- { 0xb190, "ext_temp_sel"}, /* Select temp Speaker calibration , */\
- { 0xc000, "use_direct_ctrls"}, /* Direct control to overrule several functions for testing, */\
- { 0xc010, "rst_datapath"}, /* Direct control for datapath reset , */\
- { 0xc020, "rst_cgu"}, /* Direct control for cgu reset , */\
- { 0xc038, "enbl_ref"}, /* Switch on the analog references, each part of the references can be switched on/off individually, */\
- { 0xc0c0, "use_direct_vs_ctrls"}, /* voltage sense Direct control to overrule several functions for testing, */\
- { 0xc0d0, "enbl_ringo"}, /* Enable the ring oscillator for test purpose , */\
- { 0xc0e0, "use_direct_clk_ctrl"}, /* Direct clock control to overrule several functions for testing, */\
- { 0xc0f0, "use_direct_pll_ctrl"}, /* Direct PLL control to overrule several functions for testing, */\
- { 0xc100, "enbl_tsense"}, /* Temperature sensor enable control - I2C direct mode, */\
- { 0xc110, "tsense_hibias"}, /* Bit to set the biasing in temp sensor to high , */\
- { 0xc120, "enbl_flag_vbg"}, /* Enable flagging of bandgap out of control , */\
- { 0xc20f, "abist_offset"}, /* Offset control for ABIST testing (two's complement), */\
- { 0xc300, "bypasslatch"}, /* Bypass latch , */\
- { 0xc311, "sourcea"}, /* Set OUTA to , */\
- { 0xc331, "sourceb"}, /* Set OUTB to , */\
- { 0xc350, "inverta"}, /* Invert pwma test signal , */\
- { 0xc360, "invertb"}, /* Invert pwmb test signal , */\
- { 0xc374, "pulselength"}, /* Pulse length setting test input for amplifier (clock d - k*2048*fs), */\
- { 0xc3c0, "tdm_enable_loopback"}, /* TDM loopback test , */\
- { 0xc400, "bst_bypasslatch"}, /* Bypass latch in boost converter , */\
- { 0xc411, "bst_source"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
- { 0xc430, "bst_invertb"}, /* Invert pwmbst test signal , */\
- { 0xc444, "bst_pulselength"}, /* Pulse length setting test input for boost converter , */\
- { 0xc490, "test_bst_ctrlsthv"}, /* Test mode for boost control stage , */\
- { 0xc4a0, "test_bst_iddq"}, /* IDDQ testing in power stage of boost converter , */\
- { 0xc4b0, "test_bst_rdson"}, /* RDSON testing - boost power stage , */\
- { 0xc4c0, "test_bst_cvi"}, /* CVI testing - boost power stage , */\
- { 0xc4d0, "test_bst_ocp"}, /* Boost OCP. For old ocp (ctrl_reversebst is 0), For new ocp (ctrl_reversebst is 1), */\
- { 0xc4e0, "test_bst_sense"}, /* Test option for the sense NMOS in booster for current mode control., */\
- { 0xc500, "test_cvi"}, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */\
- { 0xc510, "test_discrete"}, /* Test function noise measurement , */\
- { 0xc520, "test_iddq"}, /* Set the power stages in iddq mode for gate stress., */\
- { 0xc540, "test_rdson"}, /* Analog BIST, switch to enable Rdson measurement , */\
- { 0xc550, "test_sdelta"}, /* Analog BIST, noise test , */\
- { 0xc570, "test_enbl_cs"}, /* Enable for digimux mode of current sense , */\
- { 0xc580, "test_enbl_vs"}, /* Enable for digimux mode of voltage sense , */\
- { 0xc600, "enbl_pwm_dcc"}, /* Enables direct control of pwm duty cycle for DCDC power stage, */\
- { 0xc613, "pwm_dcc_cnt"}, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */\
- { 0xc650, "enbl_ldo_stress"}, /* Enable stress of internal supply voltages powerstages, */\
- { 0xc707, "digimuxa_sel"}, /* DigimuxA input selection control routed to DATAO (see Digimux list for details), */\
- { 0xc787, "digimuxb_sel"}, /* DigimuxB input selection control routed to INT (see Digimux list for details), */\
- { 0xc807, "digimuxc_sel"}, /* DigimuxC input selection control routed to PDMDAT (see Digimux list for details), */\
- { 0xc981, "int_ehs"}, /* Speed/load setting for INT IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
- { 0xc9c0, "hs_mode"}, /* I2C high speed mode control , */\
- { 0xca00, "enbl_anamux1"}, /* Enable anamux1 , */\
- { 0xca10, "enbl_anamux2"}, /* Enable anamux2 , */\
- { 0xca20, "enbl_anamux3"}, /* Enable anamux3 , */\
- { 0xca30, "enbl_anamux4"}, /* Enable anamux4 , */\
- { 0xca74, "anamux1"}, /* Anamux selection control - anamux on TEST1 , */\
- { 0xcb04, "anamux2"}, /* Anamux selection control - anamux on TEST2 , */\
- { 0xcb53, "anamux3"}, /* Anamux selection control - anamux on TEST3 , */\
- { 0xcba3, "anamux4"}, /* Anamux selection control - anamux on TEST4 , */\
- { 0xcd05, "pll_seli"}, /* PLL SELI - I2C direct PLL control mode only , */\
- { 0xcd64, "pll_selp"}, /* PLL SELP - I2C direct PLL control mode only , */\
- { 0xcdb3, "pll_selr"}, /* PLL SELR - I2C direct PLL control mode only , */\
- { 0xcdf0, "pll_frm"}, /* PLL free running mode control; 1 in TCB direct control mode, else this control bit, */\
- { 0xce09, "pll_ndec"}, /* PLL NDEC - I2C direct PLL control mode only , */\
- { 0xcea0, "pll_mdec_msb"}, /* MSB of pll_mdec - I2C direct PLL control mode only, */\
- { 0xceb0, "enbl_pll"}, /* Enables PLL in I2C direct PLL control mode only , */\
- { 0xcec0, "enbl_osc"}, /* Enables OSC1M in I2C direct control mode only , */\
- { 0xced0, "pll_bypass"}, /* PLL bypass control in I2C direct PLL control mode only, */\
- { 0xcee0, "pll_directi"}, /* PLL directi control in I2C direct PLL control mode only, */\
- { 0xcef0, "pll_directo"}, /* PLL directo control in I2C direct PLL control mode only, */\
- { 0xcf0f, "pll_mdec_lsb"}, /* Bits 15..0 of PLL MDEC are I2C direct PLL control mode only, */\
- { 0xd006, "pll_pdec"}, /* PLL PDEC - I2C direct PLL control mode only , */\
- { 0xd10f, "tsig_freq_lsb"}, /* Internal sinus test generator frequency control , */\
- { 0xd202, "tsig_freq_msb"}, /* Select internal sinus test generator, frequency control msb bits, */\
- { 0xd230, "inject_tsig"}, /* Control bit to switch to internal sinus test generator, */\
- { 0xd283, "tsig_gain"}, /* Test signal gain , */\
- { 0xd300, "adc10_reset"}, /* Reset for ADC10 - I2C direct control mode , */\
- { 0xd311, "adc10_test"}, /* Test mode selection signal for ADC10 - I2C direct control mode, */\
- { 0xd332, "adc10_sel"}, /* Select the input to convert for ADC10 - I2C direct control mode, */\
- { 0xd364, "adc10_prog_sample"}, /* ADC10 program sample setting - I2C direct control mode, */\
- { 0xd3b0, "adc10_enbl"}, /* Enable ADC10 - I2C direct control mode , */\
- { 0xd3c0, "bypass_lp_vbat"}, /* Bypass control for Low pass filter in batt sensor , */\
- { 0xd409, "data_adc10_tempbat"}, /* ADC 10 data output data for testing , */\
- { 0xd507, "ctrl_digtoana_hidden"}, /* Spare digital to analog control bits - Hidden , */\
- { 0xd580, "enbl_clk_out_of_range"}, /* Clock out of range , */\
- { 0xd621, "clkdiv_audio_sel"}, /* Audio clock divider selection in direct clock control mode, */\
- { 0xd641, "clkdiv_muxa_sel"}, /* DCDC MUXA clock divider selection in direct clock control mode, */\
- { 0xd661, "clkdiv_muxb_sel"}, /* DCDC MUXB clock divider selection in direct clock control mode, */\
- { 0xd721, "datao_ehs"}, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
- { 0xd740, "bck_ehs"}, /* High-speed and standard/fast mode selection for BCK IO cell (see IIC3V3 IO cell datasheet), */\
- { 0xd750, "datai_ehs"}, /* High-speed and standard/fast mode selection for DATAI IO cell (see IIC3V3 IO cell datasheet), */\
- { 0xd800, "source_in_testmode"}, /* tdm source in test mode (return only current and voltage sense), */\
- { 0xd810, "gainatt_feedback"}, /* gainatt feedback to tdm , */\
- { 0xd822, "test_parametric_io"}, /* test io parametric , */\
- { 0xd850, "ctrl_bst_clk_lp1"}, /* boost clock control in low power mode1 , */\
- { 0xd861, "test_spare_out1"}, /* test spare out 1 , */\
- { 0xd880, "bst_dcmbst"}, /* dcm boost , */\
- { 0xd8c3, "test_spare_out2"}, /* test spare out 1 , */\
- { 0xee0f, "sw_profile"}, /* Software profile data , */\
- { 0xef0f, "sw_vstep"}, /* Software vstep information , */\
- { 0xf000, "calibration_onetime"}, /* Calibration schedule , */\
- { 0xf010, "calibr_ron_done"}, /* Calibration Ron executed , */\
- { 0xf020, "calibr_dcdc_api_calibrate"}, /* Calibration current limit DCDC , */\
- { 0xf030, "calibr_dcdc_delta_sign"}, /* Sign bit for delta calibration current limit DCDC , */\
- { 0xf042, "calibr_dcdc_delta"}, /* Calibration delta current limit DCDC , */\
- { 0xf078, "calibr_speaker_info"}, /* Reserved space for allowing customer to store speaker information, */\
- { 0xf105, "calibr_vout_offset"}, /* DCDC offset calibration 2's complement (key1 protected), */\
- { 0xf169, "spare_mpt1_15_6"}, /* SPARE , */\
- { 0xf203, "calibr_gain"}, /* HW gain module (2's complement) , */\
- { 0xf245, "calibr_offset"}, /* Offset for amplifier, HW gain module (2's complement), */\
- { 0xf2a5, "spare_mtp2_15_10"}, /* SPARE , */\
- { 0xf307, "calibr_gain_vs"}, /* Voltage sense gain , */\
- { 0xf387, "calibr_gain_cs"}, /* Current sense gain (signed two's complement format), */\
- { 0xf407, "spare_mtp4_15_0"}, /* SPARE , */\
- { 0xf487, "vs_trim"}, /* VS Trimming , */\
- { 0xf50f, "calibr_R25C_R"}, /* Ron resistance of speaker coil , */\
- { 0xf60f, "spare_mpt6_6_0"}, /* SPARE , */\
- { 0xf706, "ctrl_offset_a"}, /* Offset of level shifter A , */\
- { 0xf770, "spare_mtp7_07"}, /* SPARE , */\
- { 0xf786, "ctrl_offset_b"}, /* Offset of amplifier level shifter B , */\
- { 0xf7f0, "spare_mtp7_15"}, /* SPARE , */\
- { 0xf806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
- { 0xf870, "htol_iic_addr_en"}, /* HTOL I2C address enable control , */\
- { 0xf884, "calibr_temp_offset"}, /* Temperature offset 2's compliment (key1 protected), */\
- { 0xf8d2, "calibr_temp_gain"}, /* Temperature gain 2's compliment (key1 protected) , */\
- { 0xf900, "mtp_lock_dcdcoff_mode"}, /* Disable function dcdcoff_mode , */\
- { 0xf910, "spare_mtp9_1"}, /* SPARE , */\
- { 0xf920, "mtp_lock_bypass_clipper"}, /* Disable function bypass_clipper , */\
- { 0xf930, "mtp_lock_max_dcdc_voltage"}, /* Force Boost in follower mode , */\
- { 0xf943, "calibr_vbg_trim"}, /* Bandgap trimming control , */\
- { 0xf980, "spare_mtp9_8"}, /* SPARE , */\
- { 0xf990, "mtp_enbl_pwm_delay_clock_gating"}, /* pwm delay clock auto gating , */\
- { 0xf9a0, "mtp_enbl_ocp_clock_gating"}, /* ocpclock auto gating , */\
- { 0xf9b0, "mtp_gate_cgu_clock_for_test"}, /* cgu test clock control , */\
- { 0xf9c0, "mtp_tdm_pad_sel"}, /* tdm pad selection , */\
- { 0xf9d2, "spare_mtp9_15_12"}, /* MTP-control FW - See Firmware I2C API document for details, */\
- { 0xfa0f, "mtpdataA"}, /* MTPdataA (key1 protected) , */\
- { 0xfb0f, "mtpdataB"}, /* MTPdataB (key1 protected) , */\
- { 0xfc0f, "mtpdataC"}, /* MTPdataC (key1 protected) , */\
- { 0xfd0f, "mtpdataD"}, /* MTPdataD (key1 protected) , */\
- { 0xfe0f, "mtpdataE"}, /* MTPdataE (key1 protected) , */\
- { 0xff07, "calibr_osc_delta_ndiv"}, /* Calibration data for OSC1M, signed number representation, */\
- { 0xff87, "spare_mtp7_15_08"}, /* SPARE , */\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-
-enum tfa9874_irq {
- tfa9874_irq_stvdds = 0,
- tfa9874_irq_stbstoc = 1,
- tfa9874_irq_stotds = 2,
- tfa9874_irq_stocpr = 3,
- tfa9874_irq_stuvds = 4,
- tfa9874_irq_stmanalarm = 5,
- tfa9874_irq_sttdmer = 6,
- tfa9874_irq_stnoclk = 7,
- tfa9874_irq_max = 8,
- tfa9874_irq_all = -1 /* all irqs */};
-
-#define TFA9874_IRQ_NAMETABLE static tfaIrqName_t Tfa9874IrqNames[]= {\
- { 0, "STVDDS"},\
- { 1, "STBSTOC"},\
- { 2, "STOTDS"},\
- { 3, "STOCPR"},\
- { 4, "STUVDS"},\
- { 5, "STMANALARM"},\
- { 6, "STTDMER"},\
- { 7, "STNOCLK"},\
- { 8, "8"},\
-};
-#endif /* _TFA9874_TFAFIELDNAMES_H */
diff --git a/inc/tfa9891_genregs.h b/inc/tfa9891_genregs.h
deleted file mode 100644
index 8071895..0000000
--- a/inc/tfa9891_genregs.h
+++ /dev/null
@@ -1,1129 +0,0 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef TFA9891_GENREGS_H
-#define TFA9891_GENREGS_H
-
-
-#define TFA98XX_STATUSREG 0x00
-#define TFA98XX_BATTERYVOLTAGE 0x01
-#define TFA9891_TEMPERATURE 0x02
-#define TFA98XX_REVISIONNUMBER 0x03
-#define TFA98XX_I2SREG 0x04
-#define TFA98XX_BAT_PROT 0x05
-#define TFA98XX_AUDIO_CTR 0x06
-#define TFA98XX_DCDCBOOST 0x07
-#define TFA98XX_SPKR_CALIBRATION 0x08
-#define TFA98XX_SYS_CTRL 0x09
-#define TFA98XX_I2S_SEL_REG 0x0a
-#define TFA98XX_HIDDEN_MTP_KEY2 0x0b
-#define TFA98XX_INTERRUPT_REG 0x0f
-#define TFA98XX_PDM_CTRL 0x10
-#define TFA98XX_PDM_OUT_CTRL 0x11
-#define TFA98XX_PDM_DS4_R 0x12
-#define TFA98XX_PDM_DS4_L 0x13
-#define TFA98XX_CTRL_SAAM_PGA 0x22
-#define TFA98XX_MISC_CTRL 0x25
-#define TFA98XX_CURRENTSENSE1 0x46
-#define TFA98XX_CURRENTSENSE4 0x49
-#define TFA98XX_HIDDEN_MTP_CTRL_REG3 0x62
-#define TFA9891_CF_CONTROLS 0x70
-#define TFA9891_CF_MAD 0x71
-#define TFA9891_CF_MEM 0x72
-#define TFA9891_CF_STATUS 0x73
-#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP 0x80
-
-/*
- * (0x00)-StatusReg
- */
-
-/*
- * POR
- */
-#define TFA98XX_STATUSREG_VDDS (0x1<<0)
-#define TFA98XX_STATUSREG_VDDS_POS 0
-#define TFA98XX_STATUSREG_VDDS_LEN 1
-#define TFA98XX_STATUSREG_VDDS_MAX 1
-#define TFA98XX_STATUSREG_VDDS_MSK 0x1
-
-/*
- * PLL_LOCK
- */
-#define TFA98XX_STATUSREG_PLLS (0x1<<1)
-#define TFA98XX_STATUSREG_PLLS_POS 1
-#define TFA98XX_STATUSREG_PLLS_LEN 1
-#define TFA98XX_STATUSREG_PLLS_MAX 1
-#define TFA98XX_STATUSREG_PLLS_MSK 0x2
-
-/*
- * flag_otpok
- */
-#define TFA98XX_STATUSREG_OTDS (0x1<<2)
-#define TFA98XX_STATUSREG_OTDS_POS 2
-#define TFA98XX_STATUSREG_OTDS_LEN 1
-#define TFA98XX_STATUSREG_OTDS_MAX 1
-#define TFA98XX_STATUSREG_OTDS_MSK 0x4
-
-/*
- * flag_ovpok
- */
-#define TFA98XX_STATUSREG_OVDS (0x1<<3)
-#define TFA98XX_STATUSREG_OVDS_POS 3
-#define TFA98XX_STATUSREG_OVDS_LEN 1
-#define TFA98XX_STATUSREG_OVDS_MAX 1
-#define TFA98XX_STATUSREG_OVDS_MSK 0x8
-
-/*
- * flag_uvpok
- */
-#define TFA98XX_STATUSREG_UVDS (0x1<<4)
-#define TFA98XX_STATUSREG_UVDS_POS 4
-#define TFA98XX_STATUSREG_UVDS_LEN 1
-#define TFA98XX_STATUSREG_UVDS_MAX 1
-#define TFA98XX_STATUSREG_UVDS_MSK 0x10
-
-/*
- * flag_OCP_alarm
- */
-#define TFA98XX_STATUSREG_OCDS (0x1<<5)
-#define TFA98XX_STATUSREG_OCDS_POS 5
-#define TFA98XX_STATUSREG_OCDS_LEN 1
-#define TFA98XX_STATUSREG_OCDS_MAX 1
-#define TFA98XX_STATUSREG_OCDS_MSK 0x20
-
-/*
- * flag_clocks_stable
- */
-#define TFA98XX_STATUSREG_CLKS (0x1<<6)
-#define TFA98XX_STATUSREG_CLKS_POS 6
-#define TFA98XX_STATUSREG_CLKS_LEN 1
-#define TFA98XX_STATUSREG_CLKS_MAX 1
-#define TFA98XX_STATUSREG_CLKS_MSK 0x40
-
-/*
- * CLIP
- */
-#define TFA98XX_STATUSREG_CLIPS (0x1<<7)
-#define TFA98XX_STATUSREG_CLIPS_POS 7
-#define TFA98XX_STATUSREG_CLIPS_LEN 1
-#define TFA98XX_STATUSREG_CLIPS_MAX 1
-#define TFA98XX_STATUSREG_CLIPS_MSK 0x80
-
-/*
- * mtp_busy
- */
-#define TFA98XX_STATUSREG_MTPB (0x1<<8)
-#define TFA98XX_STATUSREG_MTPB_POS 8
-#define TFA98XX_STATUSREG_MTPB_LEN 1
-#define TFA98XX_STATUSREG_MTPB_MAX 1
-#define TFA98XX_STATUSREG_MTPB_MSK 0x100
-
-/*
- * flag_pwrokbst
- */
-#define TFA98XX_STATUSREG_DCCS (0x1<<9)
-#define TFA98XX_STATUSREG_DCCS_POS 9
-#define TFA98XX_STATUSREG_DCCS_LEN 1
-#define TFA98XX_STATUSREG_DCCS_MAX 1
-#define TFA98XX_STATUSREG_DCCS_MSK 0x200
-
-/*
- * flag_cf_speakererror
- */
-#define TFA98XX_STATUSREG_SPKS (0x1<<10)
-#define TFA98XX_STATUSREG_SPKS_POS 10
-#define TFA98XX_STATUSREG_SPKS_LEN 1
-#define TFA98XX_STATUSREG_SPKS_MAX 1
-#define TFA98XX_STATUSREG_SPKS_MSK 0x400
-
-/*
- * flag_cold_started
- */
-#define TFA98XX_STATUSREG_ACS (0x1<<11)
-#define TFA98XX_STATUSREG_ACS_POS 11
-#define TFA98XX_STATUSREG_ACS_LEN 1
-#define TFA98XX_STATUSREG_ACS_MAX 1
-#define TFA98XX_STATUSREG_ACS_MSK 0x800
-
-/*
- * flag_engage
- */
-#define TFA98XX_STATUSREG_SWS (0x1<<12)
-#define TFA98XX_STATUSREG_SWS_POS 12
-#define TFA98XX_STATUSREG_SWS_LEN 1
-#define TFA98XX_STATUSREG_SWS_MAX 1
-#define TFA98XX_STATUSREG_SWS_MSK 0x1000
-
-/*
- * flag_watchdog_reset
- */
-#define TFA98XX_STATUSREG_WDS (0x1<<13)
-#define TFA98XX_STATUSREG_WDS_POS 13
-#define TFA98XX_STATUSREG_WDS_LEN 1
-#define TFA98XX_STATUSREG_WDS_MAX 1
-#define TFA98XX_STATUSREG_WDS_MSK 0x2000
-
-/*
- * flag_enbl_amp
- */
-#define TFA98XX_STATUSREG_AMPS (0x1<<14)
-#define TFA98XX_STATUSREG_AMPS_POS 14
-#define TFA98XX_STATUSREG_AMPS_LEN 1
-#define TFA98XX_STATUSREG_AMPS_MAX 1
-#define TFA98XX_STATUSREG_AMPS_MSK 0x4000
-
-/*
- * flag_enbl_ref
- */
-#define TFA98XX_STATUSREG_AREFS (0x1<<15)
-#define TFA98XX_STATUSREG_AREFS_POS 15
-#define TFA98XX_STATUSREG_AREFS_LEN 1
-#define TFA98XX_STATUSREG_AREFS_MAX 1
-#define TFA98XX_STATUSREG_AREFS_MSK 0x8000
-
-/*
- * (0x01)-BatteryVoltage
- */
-
-/*
- * bat_adc
- */
-#define TFA98XX_BATTERYVOLTAGE_BATS (0x3ff<<0)
-#define TFA98XX_BATTERYVOLTAGE_BATS_POS 0
-#define TFA98XX_BATTERYVOLTAGE_BATS_LEN 10
-#define TFA98XX_BATTERYVOLTAGE_BATS_MAX 1023
-#define TFA98XX_BATTERYVOLTAGE_BATS_MSK 0x3ff
-
-
-/*
- * (0x02)-Temperature
- */
-
-/*
- * temp_adc
- */
-#define TFA9891_TEMPERATURE_TEMPS (0x1ff<<0)
-#define TFA9891_TEMPERATURE_TEMPS_POS 0
-#define TFA9891_TEMPERATURE_TEMPS_LEN 9
-#define TFA9891_TEMPERATURE_TEMPS_MAX 511
-#define TFA9891_TEMPERATURE_TEMPS_MSK 0x1ff
-
-
-/*
- * (0x03)-RevisionNumber
- */
-
-/*
- * rev_reg
- */
-#define TFA98XX_REVISIONNUMBER_REV (0xff<<0)
-#define TFA98XX_REVISIONNUMBER_REV_POS 0
-#define TFA98XX_REVISIONNUMBER_REV_LEN 8
-#define TFA98XX_REVISIONNUMBER_REV_MAX 255
-#define TFA98XX_REVISIONNUMBER_REV_MSK 0xff
-
-
-/*
- * (0x04)-I2SReg
- */
-
-/*
- * i2s_seti
- */
-#define TFA98XX_I2SREG_I2SF (0x7<<0)
-#define TFA98XX_I2SREG_I2SF_POS 0
-#define TFA98XX_I2SREG_I2SF_LEN 3
-#define TFA98XX_I2SREG_I2SF_MAX 7
-#define TFA98XX_I2SREG_I2SF_MSK 0x7
-
-/*
- * chan_sel1
- */
-#define TFA98XX_I2SREG_CHS12 (0x3<<3)
-#define TFA98XX_I2SREG_CHS12_POS 3
-#define TFA98XX_I2SREG_CHS12_LEN 2
-#define TFA98XX_I2SREG_CHS12_MAX 3
-#define TFA98XX_I2SREG_CHS12_MSK 0x18
-
-/*
- * lr_sw_i2si2
- */
-#define TFA98XX_I2SREG_CHS3 (0x1<<5)
-#define TFA98XX_I2SREG_CHS3_POS 5
-#define TFA98XX_I2SREG_CHS3_LEN 1
-#define TFA98XX_I2SREG_CHS3_MAX 1
-#define TFA98XX_I2SREG_CHS3_MSK 0x20
-
-/*
- * input_sel
- */
-#define TFA98XX_I2SREG_CHSA (0x3<<6)
-#define TFA98XX_I2SREG_CHSA_POS 6
-#define TFA98XX_I2SREG_CHSA_LEN 2
-#define TFA98XX_I2SREG_CHSA_MAX 3
-#define TFA98XX_I2SREG_CHSA_MSK 0xc0
-
-/*
- * datao_sel
- */
-#define TFA98XX_I2SREG_I2SDOC (0x3<<8)
-#define TFA98XX_I2SREG_I2SDOC_POS 8
-#define TFA98XX_I2SREG_I2SDOC_LEN 2
-#define TFA98XX_I2SREG_I2SDOC_MAX 3
-#define TFA98XX_I2SREG_I2SDOC_MSK 0x300
-
-/*
- * disable_idp
- */
-#define TFA98XX_I2SREG_DISP (0x1<<10)
-#define TFA98XX_I2SREG_DISP_POS 10
-#define TFA98XX_I2SREG_DISP_LEN 1
-#define TFA98XX_I2SREG_DISP_MAX 1
-#define TFA98XX_I2SREG_DISP_MSK 0x400
-
-/*
- * enbl_datao
- */
-#define TFA98XX_I2SREG_I2SDOE (0x1<<11)
-#define TFA98XX_I2SREG_I2SDOE_POS 11
-#define TFA98XX_I2SREG_I2SDOE_LEN 1
-#define TFA98XX_I2SREG_I2SDOE_MAX 1
-#define TFA98XX_I2SREG_I2SDOE_MSK 0x800
-
-/*
- * i2s_fs
- */
-#define TFA98XX_I2SREG_I2SSR (0xf<<12)
-#define TFA98XX_I2SREG_I2SSR_POS 12
-#define TFA98XX_I2SREG_I2SSR_LEN 4
-#define TFA98XX_I2SREG_I2SSR_MAX 15
-#define TFA98XX_I2SREG_I2SSR_MSK 0xf000
-
-
-/*
- * (0x05)-bat_prot
- */
-
-/*
- * vbat_prot_attacktime
- */
-#define TFA98XX_BAT_PROT_BSSCR (0x3<<0)
-#define TFA98XX_BAT_PROT_BSSCR_POS 0
-#define TFA98XX_BAT_PROT_BSSCR_LEN 2
-#define TFA98XX_BAT_PROT_BSSCR_MAX 3
-#define TFA98XX_BAT_PROT_BSSCR_MSK 0x3
-
-/*
- * vbat_prot_thlevel
- */
-#define TFA98XX_BAT_PROT_BSST (0xf<<2)
-#define TFA98XX_BAT_PROT_BSST_POS 2
-#define TFA98XX_BAT_PROT_BSST_LEN 4
-#define TFA98XX_BAT_PROT_BSST_MAX 15
-#define TFA98XX_BAT_PROT_BSST_MSK 0x3c
-
-/*
- * vbat_prot_max_reduct
- */
-#define TFA98XX_BAT_PROT_BSSRL (0x3<<6)
-#define TFA98XX_BAT_PROT_BSSRL_POS 6
-#define TFA98XX_BAT_PROT_BSSRL_LEN 2
-#define TFA98XX_BAT_PROT_BSSRL_MAX 3
-#define TFA98XX_BAT_PROT_BSSRL_MSK 0xc0
-
-/*
- * vbat_prot_release_t
- */
-#define TFA98XX_BAT_PROT_BSSRR (0x7<<8)
-#define TFA98XX_BAT_PROT_BSSRR_POS 8
-#define TFA98XX_BAT_PROT_BSSRR_LEN 3
-#define TFA98XX_BAT_PROT_BSSRR_MAX 7
-#define TFA98XX_BAT_PROT_BSSRR_MSK 0x700
-
-/*
- * vbat_prot_hysterese
- */
-#define TFA98XX_BAT_PROT_BSSHY (0x3<<11)
-#define TFA98XX_BAT_PROT_BSSHY_POS 11
-#define TFA98XX_BAT_PROT_BSSHY_LEN 2
-#define TFA98XX_BAT_PROT_BSSHY_MAX 3
-#define TFA98XX_BAT_PROT_BSSHY_MSK 0x1800
-
-/*
- * sel_vbat
- */
-#define TFA98XX_BAT_PROT_BSSR (0x1<<14)
-#define TFA98XX_BAT_PROT_BSSR_POS 14
-#define TFA98XX_BAT_PROT_BSSR_LEN 1
-#define TFA98XX_BAT_PROT_BSSR_MAX 1
-#define TFA98XX_BAT_PROT_BSSR_MSK 0x4000
-
-/*
- * bypass_clipper
- */
-#define TFA98XX_BAT_PROT_BSSBY (0x1<<15)
-#define TFA98XX_BAT_PROT_BSSBY_POS 15
-#define TFA98XX_BAT_PROT_BSSBY_LEN 1
-#define TFA98XX_BAT_PROT_BSSBY_MAX 1
-#define TFA98XX_BAT_PROT_BSSBY_MSK 0x8000
-
-
-/*
- * (0x06)-audio_ctr
- */
-
-/*
- * dpsa
- */
-#define TFA98XX_AUDIO_CTR_DPSA (0x1<<0)
-#define TFA98XX_AUDIO_CTR_DPSA_POS 0
-#define TFA98XX_AUDIO_CTR_DPSA_LEN 1
-#define TFA98XX_AUDIO_CTR_DPSA_MAX 1
-#define TFA98XX_AUDIO_CTR_DPSA_MSK 0x1
-
-/*
- * ctrl_slope
- */
-#define TFA98XX_AUDIO_CTR_AMPSL (0xf<<1)
-#define TFA98XX_AUDIO_CTR_AMPSL_POS 1
-#define TFA98XX_AUDIO_CTR_AMPSL_LEN 4
-#define TFA98XX_AUDIO_CTR_AMPSL_MAX 15
-#define TFA98XX_AUDIO_CTR_AMPSL_MSK 0x1e
-
-/*
- * cf_mute
- */
-#define TFA98XX_AUDIO_CTR_CFSM (0x1<<5)
-#define TFA98XX_AUDIO_CTR_CFSM_POS 5
-#define TFA98XX_AUDIO_CTR_CFSM_LEN 1
-#define TFA98XX_AUDIO_CTR_CFSM_MAX 1
-#define TFA98XX_AUDIO_CTR_CFSM_MSK 0x20
-
-/*
- * ctrl_batsensesteepness
- */
-#define TFA98XX_AUDIO_CTR_BSSS (0x1<<7)
-#define TFA98XX_AUDIO_CTR_BSSS_POS 7
-#define TFA98XX_AUDIO_CTR_BSSS_LEN 1
-#define TFA98XX_AUDIO_CTR_BSSS_MAX 1
-#define TFA98XX_AUDIO_CTR_BSSS_MSK 0x80
-
-/*
- * vol
- */
-#define TFA98XX_AUDIO_CTR_VOL (0xff<<8)
-#define TFA98XX_AUDIO_CTR_VOL_POS 8
-#define TFA98XX_AUDIO_CTR_VOL_LEN 8
-#define TFA98XX_AUDIO_CTR_VOL_MAX 255
-#define TFA98XX_AUDIO_CTR_VOL_MSK 0xff00
-
-
-/*
- * (0x07)-DCDCboost
- */
-
-/*
- * ctrl_bstvolt
- */
-#define TFA98XX_DCDCBOOST_DCVO (0x7<<0)
-#define TFA98XX_DCDCBOOST_DCVO_POS 0
-#define TFA98XX_DCDCBOOST_DCVO_LEN 3
-#define TFA98XX_DCDCBOOST_DCVO_MAX 7
-#define TFA98XX_DCDCBOOST_DCVO_MSK 0x7
-
-/*
- * ctrl_bstcur
- */
-#define TFA98XX_DCDCBOOST_DCMCC (0x7<<3)
-#define TFA98XX_DCDCBOOST_DCMCC_POS 3
-#define TFA98XX_DCDCBOOST_DCMCC_LEN 3
-#define TFA98XX_DCDCBOOST_DCMCC_MAX 7
-#define TFA98XX_DCDCBOOST_DCMCC_MSK 0x38
-
-/*
- * boost_intel
- */
-#define TFA98XX_DCDCBOOST_DCIE (0x1<<10)
-#define TFA98XX_DCDCBOOST_DCIE_POS 10
-#define TFA98XX_DCDCBOOST_DCIE_LEN 1
-#define TFA98XX_DCDCBOOST_DCIE_MAX 1
-#define TFA98XX_DCDCBOOST_DCIE_MSK 0x400
-
-/*
- * boost_speed
- */
-#define TFA98XX_DCDCBOOST_DCSR (0x1<<11)
-#define TFA98XX_DCDCBOOST_DCSR_POS 11
-#define TFA98XX_DCDCBOOST_DCSR_LEN 1
-#define TFA98XX_DCDCBOOST_DCSR_MAX 1
-#define TFA98XX_DCDCBOOST_DCSR_MSK 0x800
-
-
-/*
- * (0x08)-spkr_calibration
- */
-
-/*
- * ext_temp_sel
- */
-#define TFA98XX_SPKR_CALIBRATION_TROS (0x1<<0)
-#define TFA98XX_SPKR_CALIBRATION_TROS_POS 0
-#define TFA98XX_SPKR_CALIBRATION_TROS_LEN 1
-#define TFA98XX_SPKR_CALIBRATION_TROS_MAX 1
-#define TFA98XX_SPKR_CALIBRATION_TROS_MSK 0x1
-
-/*
- * ext_temp
- */
-#define TFA98XX_SPKR_CALIBRATION_EXTTS (0x1ff<<1)
-#define TFA98XX_SPKR_CALIBRATION_EXTTS_POS 1
-#define TFA98XX_SPKR_CALIBRATION_EXTTS_LEN 9
-#define TFA98XX_SPKR_CALIBRATION_EXTTS_MAX 511
-#define TFA98XX_SPKR_CALIBRATION_EXTTS_MSK 0x3fe
-
-
-/*
- * (0x09)-sys_ctrl
- */
-
-/*
- * PowerDown
- */
-#define TFA98XX_SYS_CTRL_PWDN (0x1<<0)
-#define TFA98XX_SYS_CTRL_PWDN_POS 0
-#define TFA98XX_SYS_CTRL_PWDN_LEN 1
-#define TFA98XX_SYS_CTRL_PWDN_MAX 1
-#define TFA98XX_SYS_CTRL_PWDN_MSK 0x1
-
-/*
- * reset
- */
-#define TFA98XX_SYS_CTRL_I2CR (0x1<<1)
-#define TFA98XX_SYS_CTRL_I2CR_POS 1
-#define TFA98XX_SYS_CTRL_I2CR_LEN 1
-#define TFA98XX_SYS_CTRL_I2CR_MAX 1
-#define TFA98XX_SYS_CTRL_I2CR_MSK 0x2
-
-/*
- * enbl_coolflux
- */
-#define TFA98XX_SYS_CTRL_CFE (0x1<<2)
-#define TFA98XX_SYS_CTRL_CFE_POS 2
-#define TFA98XX_SYS_CTRL_CFE_LEN 1
-#define TFA98XX_SYS_CTRL_CFE_MAX 1
-#define TFA98XX_SYS_CTRL_CFE_MSK 0x4
-
-/*
- * enbl_amplifier
- */
-#define TFA98XX_SYS_CTRL_AMPE (0x1<<3)
-#define TFA98XX_SYS_CTRL_AMPE_POS 3
-#define TFA98XX_SYS_CTRL_AMPE_LEN 1
-#define TFA98XX_SYS_CTRL_AMPE_MAX 1
-#define TFA98XX_SYS_CTRL_AMPE_MSK 0x8
-
-/*
- * enbl_boost
- */
-#define TFA98XX_SYS_CTRL_DCA (0x1<<4)
-#define TFA98XX_SYS_CTRL_DCA_POS 4
-#define TFA98XX_SYS_CTRL_DCA_LEN 1
-#define TFA98XX_SYS_CTRL_DCA_MAX 1
-#define TFA98XX_SYS_CTRL_DCA_MSK 0x10
-
-/*
- * cf_configured
- */
-#define TFA98XX_SYS_CTRL_SBSL (0x1<<5)
-#define TFA98XX_SYS_CTRL_SBSL_POS 5
-#define TFA98XX_SYS_CTRL_SBSL_LEN 1
-#define TFA98XX_SYS_CTRL_SBSL_MAX 1
-#define TFA98XX_SYS_CTRL_SBSL_MSK 0x20
-
-/*
- * sel_enbl_amplifier
- */
-#define TFA98XX_SYS_CTRL_AMPC (0x1<<6)
-#define TFA98XX_SYS_CTRL_AMPC_POS 6
-#define TFA98XX_SYS_CTRL_AMPC_LEN 1
-#define TFA98XX_SYS_CTRL_AMPC_MAX 1
-#define TFA98XX_SYS_CTRL_AMPC_MSK 0x40
-
-/*
- * dcdcoff_mode
- */
-#define TFA98XX_SYS_CTRL_DCDIS (0x1<<7)
-#define TFA98XX_SYS_CTRL_DCDIS_POS 7
-#define TFA98XX_SYS_CTRL_DCDIS_LEN 1
-#define TFA98XX_SYS_CTRL_DCDIS_MAX 1
-#define TFA98XX_SYS_CTRL_DCDIS_MSK 0x80
-
-/*
- * cttr_iddqtest
- */
-#define TFA98XX_SYS_CTRL_PSDR (0x1<<8)
-#define TFA98XX_SYS_CTRL_PSDR_POS 8
-#define TFA98XX_SYS_CTRL_PSDR_LEN 1
-#define TFA98XX_SYS_CTRL_PSDR_MAX 1
-#define TFA98XX_SYS_CTRL_PSDR_MSK 0x100
-
-/*
- * ctrl_coil_value
- */
-#define TFA98XX_SYS_CTRL_DCCV (0x3<<9)
-#define TFA98XX_SYS_CTRL_DCCV_POS 9
-#define TFA98XX_SYS_CTRL_DCCV_LEN 2
-#define TFA98XX_SYS_CTRL_DCCV_MAX 3
-#define TFA98XX_SYS_CTRL_DCCV_MSK 0x600
-
-/*
- * ctrl_sel_cf_clock
- */
-#define TFA98XX_SYS_CTRL_CCFD (0x3<<11)
-#define TFA98XX_SYS_CTRL_CCFD_POS 11
-#define TFA98XX_SYS_CTRL_CCFD_LEN 2
-#define TFA98XX_SYS_CTRL_CCFD_MAX 3
-#define TFA98XX_SYS_CTRL_CCFD_MSK 0x1800
-
-/*
- * intf_sel
- */
-#define TFA98XX_SYS_CTRL_ISEL (0x1<<13)
-#define TFA98XX_SYS_CTRL_ISEL_POS 13
-#define TFA98XX_SYS_CTRL_ISEL_LEN 1
-#define TFA98XX_SYS_CTRL_ISEL_MAX 1
-#define TFA98XX_SYS_CTRL_ISEL_MSK 0x2000
-
-/*
- * sel_ws_bck
- */
-#define TFA98XX_SYS_CTRL_IPLL (0x1<<14)
-#define TFA98XX_SYS_CTRL_IPLL_POS 14
-#define TFA98XX_SYS_CTRL_IPLL_LEN 1
-#define TFA98XX_SYS_CTRL_IPLL_MAX 1
-#define TFA98XX_SYS_CTRL_IPLL_MSK 0x4000
-
-
-/*
- * (0x0a)-I2S_sel_reg
- */
-
-/*
- * sel_i2so_l
- */
-#define TFA98XX_I2S_SEL_REG_DOLS (0x7<<0)
-#define TFA98XX_I2S_SEL_REG_DOLS_POS 0
-#define TFA98XX_I2S_SEL_REG_DOLS_LEN 3
-#define TFA98XX_I2S_SEL_REG_DOLS_MAX 7
-#define TFA98XX_I2S_SEL_REG_DOLS_MSK 0x7
-
-/*
- * sel_i2so_r
- */
-#define TFA98XX_I2S_SEL_REG_DORS (0x7<<3)
-#define TFA98XX_I2S_SEL_REG_DORS_POS 3
-#define TFA98XX_I2S_SEL_REG_DORS_LEN 3
-#define TFA98XX_I2S_SEL_REG_DORS_MAX 7
-#define TFA98XX_I2S_SEL_REG_DORS_MSK 0x38
-
-/*
- * ctrl_spkr_coil
- */
-#define TFA98XX_I2S_SEL_REG_SPKL (0x7<<6)
-#define TFA98XX_I2S_SEL_REG_SPKL_POS 6
-#define TFA98XX_I2S_SEL_REG_SPKL_LEN 3
-#define TFA98XX_I2S_SEL_REG_SPKL_MAX 7
-#define TFA98XX_I2S_SEL_REG_SPKL_MSK 0x1c0
-
-/*
- * ctrl_spr_res
- */
-#define TFA98XX_I2S_SEL_REG_SPKR (0x3<<9)
-#define TFA98XX_I2S_SEL_REG_SPKR_POS 9
-#define TFA98XX_I2S_SEL_REG_SPKR_LEN 2
-#define TFA98XX_I2S_SEL_REG_SPKR_MAX 3
-#define TFA98XX_I2S_SEL_REG_SPKR_MSK 0x600
-
-/*
- * ctrl_dcdc_spkr_i_comp_gain
- */
-#define TFA98XX_I2S_SEL_REG_DCFG (0xf<<11)
-#define TFA98XX_I2S_SEL_REG_DCFG_POS 11
-#define TFA98XX_I2S_SEL_REG_DCFG_LEN 4
-#define TFA98XX_I2S_SEL_REG_DCFG_MAX 15
-#define TFA98XX_I2S_SEL_REG_DCFG_MSK 0x7800
-
-
-/*
- * (0x0b)-Hidden_mtp_key2
- */
-
-/*
- * MTP_key2
- */
-#define TFA98XX_HIDDEN_MTP_KEY2_MTPK (0xff<<0)
-#define TFA98XX_HIDDEN_MTP_KEY2_MTPK_POS 0
-#define TFA98XX_HIDDEN_MTP_KEY2_MTPK_LEN 8
-#define TFA98XX_HIDDEN_MTP_KEY2_MTPK_MAX 255
-#define TFA98XX_HIDDEN_MTP_KEY2_MTPK_MSK 0xff
-
-
-/*
- * (0x0f)-interrupt_reg
- */
-
-/*
- * flag_por_mask
- */
-#define TFA98XX_INTERRUPT_REG_VDDD (0x1<<0)
-#define TFA98XX_INTERRUPT_REG_VDDD_POS 0
-#define TFA98XX_INTERRUPT_REG_VDDD_LEN 1
-#define TFA98XX_INTERRUPT_REG_VDDD_MAX 1
-#define TFA98XX_INTERRUPT_REG_VDDD_MSK 0x1
-
-/*
- * flag_otpok_mask
- */
-#define TFA98XX_INTERRUPT_REG_OTDD (0x1<<1)
-#define TFA98XX_INTERRUPT_REG_OTDD_POS 1
-#define TFA98XX_INTERRUPT_REG_OTDD_LEN 1
-#define TFA98XX_INTERRUPT_REG_OTDD_MAX 1
-#define TFA98XX_INTERRUPT_REG_OTDD_MSK 0x2
-
-/*
- * flag_ovpok_mask
- */
-#define TFA98XX_INTERRUPT_REG_OVDD (0x1<<2)
-#define TFA98XX_INTERRUPT_REG_OVDD_POS 2
-#define TFA98XX_INTERRUPT_REG_OVDD_LEN 1
-#define TFA98XX_INTERRUPT_REG_OVDD_MAX 1
-#define TFA98XX_INTERRUPT_REG_OVDD_MSK 0x4
-
-/*
- * flag_uvpok_mask
- */
-#define TFA98XX_INTERRUPT_REG_UVDD (0x1<<3)
-#define TFA98XX_INTERRUPT_REG_UVDD_POS 3
-#define TFA98XX_INTERRUPT_REG_UVDD_LEN 1
-#define TFA98XX_INTERRUPT_REG_UVDD_MAX 1
-#define TFA98XX_INTERRUPT_REG_UVDD_MSK 0x8
-
-/*
- * flag_ocp_alarm_mask
- */
-#define TFA98XX_INTERRUPT_REG_OCDD (0x1<<4)
-#define TFA98XX_INTERRUPT_REG_OCDD_POS 4
-#define TFA98XX_INTERRUPT_REG_OCDD_LEN 1
-#define TFA98XX_INTERRUPT_REG_OCDD_MAX 1
-#define TFA98XX_INTERRUPT_REG_OCDD_MSK 0x10
-
-/*
- * flag_clocks_stable_mask
- */
-#define TFA98XX_INTERRUPT_REG_CLKD (0x1<<5)
-#define TFA98XX_INTERRUPT_REG_CLKD_POS 5
-#define TFA98XX_INTERRUPT_REG_CLKD_LEN 1
-#define TFA98XX_INTERRUPT_REG_CLKD_MAX 1
-#define TFA98XX_INTERRUPT_REG_CLKD_MSK 0x20
-
-/*
- * flag_pwrokbst_mask
- */
-#define TFA98XX_INTERRUPT_REG_DCCD (0x1<<6)
-#define TFA98XX_INTERRUPT_REG_DCCD_POS 6
-#define TFA98XX_INTERRUPT_REG_DCCD_LEN 1
-#define TFA98XX_INTERRUPT_REG_DCCD_MAX 1
-#define TFA98XX_INTERRUPT_REG_DCCD_MSK 0x40
-
-/*
- * flag_cf_speakererror_mask
- */
-#define TFA98XX_INTERRUPT_REG_SPKD (0x1<<7)
-#define TFA98XX_INTERRUPT_REG_SPKD_POS 7
-#define TFA98XX_INTERRUPT_REG_SPKD_LEN 1
-#define TFA98XX_INTERRUPT_REG_SPKD_MAX 1
-#define TFA98XX_INTERRUPT_REG_SPKD_MSK 0x80
-
-/*
- * flag_watchdog_reset_mask
- */
-#define TFA98XX_INTERRUPT_REG_WDD (0x1<<8)
-#define TFA98XX_INTERRUPT_REG_WDD_POS 8
-#define TFA98XX_INTERRUPT_REG_WDD_LEN 1
-#define TFA98XX_INTERRUPT_REG_WDD_MAX 1
-#define TFA98XX_INTERRUPT_REG_WDD_MSK 0x100
-
-/*
- * enable_interrupt
- */
-#define TFA98XX_INTERRUPT_REG_INT (0x1<<14)
-#define TFA98XX_INTERRUPT_REG_INT_POS 14
-#define TFA98XX_INTERRUPT_REG_INT_LEN 1
-#define TFA98XX_INTERRUPT_REG_INT_MAX 1
-#define TFA98XX_INTERRUPT_REG_INT_MSK 0x4000
-
-/*
- * invert_int_polarity
- */
-#define TFA98XX_INTERRUPT_REG_INTP (0x1<<15)
-#define TFA98XX_INTERRUPT_REG_INTP_POS 15
-#define TFA98XX_INTERRUPT_REG_INTP_LEN 1
-#define TFA98XX_INTERRUPT_REG_INTP_MAX 1
-#define TFA98XX_INTERRUPT_REG_INTP_MSK 0x8000
-
-
-/*
- * (0x10)-pdm_ctrl
- */
-
-/*
- * pdm_i2s_input
- */
-#define TFA98XX_PDM_CTRL_PDMSEL (0x1<<0)
-#define TFA98XX_PDM_CTRL_PDMSEL_POS 0
-#define TFA98XX_PDM_CTRL_PDMSEL_LEN 1
-#define TFA98XX_PDM_CTRL_PDMSEL_MAX 1
-#define TFA98XX_PDM_CTRL_PDMSEL_MSK 0x1
-
-/*
- * I2S_master_ena
- */
-#define TFA98XX_PDM_CTRL_I2SMOUTEN (0x1<<1)
-#define TFA98XX_PDM_CTRL_I2SMOUTEN_POS 1
-#define TFA98XX_PDM_CTRL_I2SMOUTEN_LEN 1
-#define TFA98XX_PDM_CTRL_I2SMOUTEN_MAX 1
-#define TFA98XX_PDM_CTRL_I2SMOUTEN_MSK 0x2
-
-/*
- * pdm_out_sel_r
- */
-#define TFA98XX_PDM_CTRL_PDMORSEL (0x3<<2)
-#define TFA98XX_PDM_CTRL_PDMORSEL_POS 2
-#define TFA98XX_PDM_CTRL_PDMORSEL_LEN 2
-#define TFA98XX_PDM_CTRL_PDMORSEL_MAX 3
-#define TFA98XX_PDM_CTRL_PDMORSEL_MSK 0xc
-
-/*
- * pdm_out_sel_l
- */
-#define TFA98XX_PDM_CTRL_PDMOLSEL (0x3<<4)
-#define TFA98XX_PDM_CTRL_PDMOLSEL_POS 4
-#define TFA98XX_PDM_CTRL_PDMOLSEL_LEN 2
-#define TFA98XX_PDM_CTRL_PDMOLSEL_MAX 3
-#define TFA98XX_PDM_CTRL_PDMOLSEL_MSK 0x30
-
-/*
- * micdat_out_sel
- */
-#define TFA98XX_PDM_CTRL_PADSEL (0x3<<6)
-#define TFA98XX_PDM_CTRL_PADSEL_POS 6
-#define TFA98XX_PDM_CTRL_PADSEL_LEN 2
-#define TFA98XX_PDM_CTRL_PADSEL_MAX 3
-#define TFA98XX_PDM_CTRL_PADSEL_MSK 0xc0
-
-
-/*
- * (0x11)-pdm_out_ctrl
- */
-
-/*
- * secure_dly
- */
-#define TFA98XX_PDM_OUT_CTRL_PDMOSDEN (0x1<<0)
-#define TFA98XX_PDM_OUT_CTRL_PDMOSDEN_POS 0
-#define TFA98XX_PDM_OUT_CTRL_PDMOSDEN_LEN 1
-#define TFA98XX_PDM_OUT_CTRL_PDMOSDEN_MAX 1
-#define TFA98XX_PDM_OUT_CTRL_PDMOSDEN_MSK 0x1
-
-/*
- * d_out_valid_rf_mux
- */
-#define TFA98XX_PDM_OUT_CTRL_PDMOSDCF (0x1<<1)
-#define TFA98XX_PDM_OUT_CTRL_PDMOSDCF_POS 1
-#define TFA98XX_PDM_OUT_CTRL_PDMOSDCF_LEN 1
-#define TFA98XX_PDM_OUT_CTRL_PDMOSDCF_MAX 1
-#define TFA98XX_PDM_OUT_CTRL_PDMOSDCF_MSK 0x2
-
-/*
- * Speak_As_Mic_en
- */
-#define TFA98XX_PDM_OUT_CTRL_SAAMEN (0x1<<4)
-#define TFA98XX_PDM_OUT_CTRL_SAAMEN_POS 4
-#define TFA98XX_PDM_OUT_CTRL_SAAMEN_LEN 1
-#define TFA98XX_PDM_OUT_CTRL_SAAMEN_MAX 1
-#define TFA98XX_PDM_OUT_CTRL_SAAMEN_MSK 0x10
-
-/*
- * speak_as_mic_lp_mode
- */
-#define TFA98XX_PDM_OUT_CTRL_SAAMLPEN (0x1<<5)
-#define TFA98XX_PDM_OUT_CTRL_SAAMLPEN_POS 5
-#define TFA98XX_PDM_OUT_CTRL_SAAMLPEN_LEN 1
-#define TFA98XX_PDM_OUT_CTRL_SAAMLPEN_MAX 1
-#define TFA98XX_PDM_OUT_CTRL_SAAMLPEN_MSK 0x20
-
-/*
- * pdm_out_rate
- */
-#define TFA98XX_PDM_OUT_CTRL_PDMOINTEN (0x1<<6)
-#define TFA98XX_PDM_OUT_CTRL_PDMOINTEN_POS 6
-#define TFA98XX_PDM_OUT_CTRL_PDMOINTEN_LEN 1
-#define TFA98XX_PDM_OUT_CTRL_PDMOINTEN_MAX 1
-#define TFA98XX_PDM_OUT_CTRL_PDMOINTEN_MSK 0x40
-
-
-/*
- * (0x12)-pdm_ds4_r
- */
-
-/*
- * ds4_g1_r
- */
-#define TFA98XX_PDM_DS4_R_PDMORG1 (0xf<<0)
-#define TFA98XX_PDM_DS4_R_PDMORG1_POS 0
-#define TFA98XX_PDM_DS4_R_PDMORG1_LEN 4
-#define TFA98XX_PDM_DS4_R_PDMORG1_MAX 15
-#define TFA98XX_PDM_DS4_R_PDMORG1_MSK 0xf
-
-/*
- * ds4_g2_r
- */
-#define TFA98XX_PDM_DS4_R_PDMORG2 (0xf<<4)
-#define TFA98XX_PDM_DS4_R_PDMORG2_POS 4
-#define TFA98XX_PDM_DS4_R_PDMORG2_LEN 4
-#define TFA98XX_PDM_DS4_R_PDMORG2_MAX 15
-#define TFA98XX_PDM_DS4_R_PDMORG2_MSK 0xf0
-
-
-/*
- * (0x13)-pdm_ds4_l
- */
-
-/*
- * ds4_g1_l
- */
-#define TFA98XX_PDM_DS4_L_PDMOLG1 (0xf<<0)
-#define TFA98XX_PDM_DS4_L_PDMOLG1_POS 0
-#define TFA98XX_PDM_DS4_L_PDMOLG1_LEN 4
-#define TFA98XX_PDM_DS4_L_PDMOLG1_MAX 15
-#define TFA98XX_PDM_DS4_L_PDMOLG1_MSK 0xf
-
-/*
- * ds4_g2_l
- */
-#define TFA98XX_PDM_DS4_L_PDMOLG2 (0xf<<4)
-#define TFA98XX_PDM_DS4_L_PDMOLG2_POS 4
-#define TFA98XX_PDM_DS4_L_PDMOLG2_LEN 4
-#define TFA98XX_PDM_DS4_L_PDMOLG2_MAX 15
-#define TFA98XX_PDM_DS4_L_PDMOLG2_MSK 0xf0
-
-
-/*
- * (0x22)-ctrl_saam_pga
- */
-
-/*
- * Ctrl_saam_pga_gain
- */
-#define TFA98XX_CTRL_SAAM_PGA_SAAMGAIN (0x7<<0)
-#define TFA98XX_CTRL_SAAM_PGA_SAAMGAIN_POS 0
-#define TFA98XX_CTRL_SAAM_PGA_SAAMGAIN_LEN 3
-#define TFA98XX_CTRL_SAAM_PGA_SAAMGAIN_MAX 7
-#define TFA98XX_CTRL_SAAM_PGA_SAAMGAIN_MSK 0x7
-
-/*
- * ctrl_saam_pga_src
- */
-#define TFA98XX_CTRL_SAAM_PGA_SAAMPGACTRL (0x1<<5)
-#define TFA98XX_CTRL_SAAM_PGA_SAAMPGACTRL_POS 5
-#define TFA98XX_CTRL_SAAM_PGA_SAAMPGACTRL_LEN 1
-#define TFA98XX_CTRL_SAAM_PGA_SAAMPGACTRL_MAX 1
-#define TFA98XX_CTRL_SAAM_PGA_SAAMPGACTRL_MSK 0x20
-
-
-/*
- * (0x25)-misc_ctrl
- */
-
-/*
- * pll_fcco
- */
-#define TFA98XX_MISC_CTRL_PLLCCOSEL (0x1<<0)
-#define TFA98XX_MISC_CTRL_PLLCCOSEL_POS 0
-#define TFA98XX_MISC_CTRL_PLLCCOSEL_LEN 1
-#define TFA98XX_MISC_CTRL_PLLCCOSEL_MAX 1
-#define TFA98XX_MISC_CTRL_PLLCCOSEL_MSK 0x1
-
-
-/*
- * (0x46)-CurrentSense1
- */
-
-/*
- * bypass_gc
- */
-#define TFA98XX_CURRENTSENSE1_CSBYPGC (0x1<<0)
-#define TFA98XX_CURRENTSENSE1_CSBYPGC_POS 0
-#define TFA98XX_CURRENTSENSE1_CSBYPGC_LEN 1
-#define TFA98XX_CURRENTSENSE1_CSBYPGC_MAX 1
-#define TFA98XX_CURRENTSENSE1_CSBYPGC_MSK 0x1
-
-
-/*
- * (0x49)-CurrentSense4
- */
-
-/*
- * ctrl_bypassclip
- */
-#define TFA98XX_CURRENTSENSE4_CLIP (0x1<<0)
-#define TFA98XX_CURRENTSENSE4_CLIP_POS 0
-#define TFA98XX_CURRENTSENSE4_CLIP_LEN 1
-#define TFA98XX_CURRENTSENSE4_CLIP_MAX 1
-#define TFA98XX_CURRENTSENSE4_CLIP_MSK 0x1
-
-/*
- * ctrl_bypassclip2
- */
-#define TFA98XX_CURRENTSENSE4_CLIP2 (0x1<<1)
-#define TFA98XX_CURRENTSENSE4_CLIP2_POS 1
-#define TFA98XX_CURRENTSENSE4_CLIP2_LEN 1
-#define TFA98XX_CURRENTSENSE4_CLIP2_MAX 1
-#define TFA98XX_CURRENTSENSE4_CLIP2_MSK 0x2
-
-
-/*
- * (0x62)-Hidden_mtp_ctrl_reg3
- */
-
-
-/*
- * (0x70)-cf_controls
- */
-
-/*
- * cf_rst_dsp
- */
-#define TFA98XX_CF_CONTROLS_RST (0x1<<0)
-#define TFA98XX_CF_CONTROLS_RST_POS 0
-#define TFA98XX_CF_CONTROLS_RST_LEN 1
-#define TFA98XX_CF_CONTROLS_RST_MAX 1
-#define TFA98XX_CF_CONTROLS_RST_MSK 0x1
-
-/*
- * cf_dmem
- */
-#define TFA98XX_CF_CONTROLS_DMEM (0x3<<1)
-#define TFA98XX_CF_CONTROLS_DMEM_POS 1
-#define TFA98XX_CF_CONTROLS_DMEM_LEN 2
-#define TFA98XX_CF_CONTROLS_DMEM_MAX 3
-#define TFA98XX_CF_CONTROLS_DMEM_MSK 0x6
-
-/*
- * cf_aif
- */
-#define TFA98XX_CF_CONTROLS_AIF (0x1<<3)
-#define TFA98XX_CF_CONTROLS_AIF_POS 3
-#define TFA98XX_CF_CONTROLS_AIF_LEN 1
-#define TFA98XX_CF_CONTROLS_AIF_MAX 1
-#define TFA98XX_CF_CONTROLS_AIF_MSK 0x8
-
-/*
- * cf_int
- */
-#define TFA98XX_CF_CONTROLS_CFINT (0x1<<4)
-#define TFA98XX_CF_CONTROLS_CFINT_POS 4
-#define TFA98XX_CF_CONTROLS_CFINT_LEN 1
-#define TFA98XX_CF_CONTROLS_CFINT_MAX 1
-#define TFA98XX_CF_CONTROLS_CFINT_MSK 0x10
-
-/*
- * cf_req
- */
-#define TFA98XX_CF_CONTROLS_REQ (0xff<<8)
-#define TFA98XX_CF_CONTROLS_REQ_POS 8
-#define TFA98XX_CF_CONTROLS_REQ_LEN 8
-#define TFA98XX_CF_CONTROLS_REQ_MAX 255
-#define TFA98XX_CF_CONTROLS_REQ_MSK 0xff00
-
-
-/*
- * (0x71)-cf_mad
- */
-
-/*
- * cf_madd
- */
-#define TFA9891_CF_MAD_MADD (0xffff<<0)
-#define TFA9891_CF_MAD_MADD_POS 0
-#define TFA9891_CF_MAD_MADD_LEN 16
-#define TFA9891_CF_MAD_MADD_MAX 65535
-#define TFA9891_CF_MAD_MADD_MSK 0xffff
-
-
-/*
- * (0x72)-cf_mem
- */
-
-/*
- * cf_mema
- */
-#define TFA9891_CF_MEM_MEMA (0xffff<<0)
-#define TFA9891_CF_MEM_MEMA_POS 0
-#define TFA9891_CF_MEM_MEMA_LEN 16
-#define TFA9891_CF_MEM_MEMA_MAX 65535
-#define TFA9891_CF_MEM_MEMA_MSK 0xffff
-
-
-/*
- * (0x73)-cf_status
- */
-
-/*
- * cf_err
- */
-#define TFA9891_CF_STATUS_ERR (0xff<<0)
-#define TFA9891_CF_STATUS_ERR_POS 0
-#define TFA9891_CF_STATUS_ERR_LEN 8
-#define TFA9891_CF_STATUS_ERR_MAX 255
-#define TFA9891_CF_STATUS_ERR_MSK 0xff
-
-/*
- * cf_ack
- */
-#define TFA9891_CF_STATUS_ACK (0xff<<8)
-#define TFA9891_CF_STATUS_ACK_POS 8
-#define TFA9891_CF_STATUS_ACK_LEN 8
-#define TFA9891_CF_STATUS_ACK_MAX 255
-#define TFA9891_CF_STATUS_ACK_MSK 0xff00
-
-
-/*
- * (0x80)-Key2Protected_spkr_cal_mtp
- */
-
-/*
- * calibration_onetime
- */
-#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP_MTPOTC (0x1<<0)
-#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP_MTPOTC_POS 0
-#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP_MTPOTC_LEN 1
-#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP_MTPOTC_MAX 1
-#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP_MTPOTC_MSK 0x1
-
-/*
- * calibr_ron_done
- */
-#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP_MTPEX (0x1<<1)
-#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP_MTPEX_POS 1
-#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP_MTPEX_LEN 1
-#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP_MTPEX_MAX 1
-#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP_MTPEX_MSK 0x2
-
-#endif /* TFA9891_GENREGS_H */
diff --git a/inc/tfa9912_device_genregs.h b/inc/tfa9912_device_genregs.h
deleted file mode 100644
index 698c79f..0000000
--- a/inc/tfa9912_device_genregs.h
+++ /dev/null
@@ -1,259 +0,0 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _TFA9912_DEVICE_GENREGS_H
-#define _TFA9912_DEVICE_GENREGS_H
-
-
-#define TFA99XX_SYS_CONTROL0 0x00
-#define TFA99XX_SYS_CONTROL1 0x01
-#define TFA99XX_SYS_CONTROL2 0x02
-#define TFA99XX_DEVICE_REVISION 0x03
-#define TFA99XX_CLOCK_CONTROL 0x04
-#define TFA99XX_CLOCK_GATING_CONTROL 0x05
-#define TFA99XX_HW_PATH_CFG 0x06
-#define TFA99XX_CLKCHK_TH 0x07
-#define TFA99XX_AMP_CTRL 0x08
-#define TFA99XX_SIDE_TONE_CONFIG 0x0d
-#define TFA99XX_CTRL_DIGTOANA_REG 0x0e
-#define TFA99XX_STATUS_FLAGS0 0x10
-#define TFA99XX_STATUS_FLAGS1 0x11
-#define TFA99XX_STATUS_FLAGS3 0x13
-#define TFA99XX_STATUS_FLAGS4 0x14
-#define TFA99XX_BATTERY_VOLTAGE 0x15
-#define TFA99XX_TEMPERATURE 0x16
-#define TFA99XX_VDDP_VOLTAGE 0x17
-#define TFA99XX_TDM_CONFIG0 0x20
-#define TFA99XX_TDM_CONFIG1 0x21
-#define TFA99XX_TDM_CONFIG2 0x22
-#define TFA99XX_TDM_CONFIG3 0x23
-#define TFA99XX_TDM_CONFIG4 0x24
-#define TFA99XX_TDM_CONFIG5 0x25
-#define TFA99XX_TDM_CONFIG6 0x26
-#define TFA99XX_TDM_CONFIG7 0x27
-#define TFA99XX_TDM_CONFIG8 0x28
-#define TFA99XX_TDM_CONFIG9 0x29
-#define TFA99XX_PDM_CONFIG0 0x31
-#define TFA99XX_PDM_CONFIG1 0x32
-#define TFA99XX_INTERRUPT_OUT_REG1 0x40
-#define TFA99XX_INTERRUPT_OUT_REG2 0x41
-#define TFA99XX_INTERRUPT_OUT_REG3 0x42
-#define TFA99XX_INTERRUPT_IN_REG1 0x44
-#define TFA99XX_INTERRUPT_IN_REG2 0x45
-#define TFA99XX_INTERRUPT_IN_REG3 0x46
-#define TFA99XX_INTERRUPT_ENABLE_REG1 0x48
-#define TFA99XX_INTERRUPT_ENABLE_REG2 0x49
-#define TFA99XX_INTERRUPT_ENABLE_REG3 0x4a
-#define TFA99XX_STATUS_POLARITY_REG1 0x4c
-#define TFA99XX_STATUS_POLARITY_REG2 0x4d
-#define TFA99XX_STATUS_POLARITY_REG3 0x4e
-#define TFA99XX_BAT_PROT_CONFIG 0x50
-#define TFA99XX_AUDIO_CONTROL 0x51
-#define TFA99XX_AMPLIFIER_CONFIG 0x52
-#define TFA99XX_KEY1_PROTECTED_AMPLIFIER_CONTROL0 0x53
-#define TFA99XX_KEY1_PROTECTED_AMPLIFIER_CONTROL1 0x54
-#define TFA99XX_KEY1_PROTECTED_AMPLIFIER_CONTROL2 0x55
-#define TFA99XX_KEY1_PROTECTED_AMPLIFIER_CONTROL4 0x57
-#define TFA99XX_KEY1_PROTECTED_PWM_CONFIG 0x58
-#define TFA99XX_CF_TAP_STATUS_0 0x5c
-#define TFA99XX_CF_TAP_STATUS_1 0x5d
-#define TFA99XX_TAP_CONTROL 0x5f
-#define TFA99XX_PGA_CONTROL0 0x60
-#define TFA99XX_GAIN_ATT 0x61
-#define TFA99XX_LOW_NOISE_GAIN1 0x62
-#define TFA99XX_LOW_NOISE_GAIN2 0x63
-#define TFA99XX_MODE1_DETECTOR1 0x64
-#define TFA99XX_MODE1_DETECTOR2 0x65
-#define TFA99XX_BST_PFM_CTRL 0x66
-#define TFA99XX_LOW_POWER_CTRL 0x67
-#define TFA99XX_TDM_SOURCE_CTRL 0x68
-#define TFA99XX_SAM_CTRL 0x69
-#define TFA99XX_RST_MIN_VBAT_CTRL 0x6a
-#define TFA99XX_SYS_CONTROL3 0x6b
-#define TFA99XX_STATUS_FLAGS5 0x6e
-#define TFA99XX_DCDC_CONTROL0 0x70
-#define TFA99XX_KEY1_PROTECTED_DCDC_CONTROL3 0x73
-#define TFA99XX_DCDC_CONTROL4 0x74
-#define TFA99XX_DCDC_CONTROL5 0x75
-#define TFA99XX_DCDC_CONTROL6 0x76
-#define TFA99XX_KEY2_PROTECTED_DCDC_CONTROL7 0x77
-#define TFA99XX_KEY2_PROTECTED_CURSENSE_CONFIG0 0x80
-#define TFA99XX_KEY2_PROTECTED_CURSENSE_CONFIG2 0x82
-#define TFA99XX_KEY2_PROTECTED_CURSENSE_CONFIG3 0x83
-#define TFA99XX_KEY2_PROTECTED_CURSENSE_CONFIG4 0x84
-#define TFA99XX_KEY2_PROTECTED_CURSENSE_CONFIG5 0x85
-#define TFA99XX_KEY2_PROTECTED_CURSENSE_CONFIG7 0x87
-#define TFA99XX_KEY2_PROTECTED_VOLSENSE_CONFIG 0x88
-#define TFA99XX_CURSENSE_CONFIG 0x89
-#define TFA99XX_CF_CONTROLS 0x90
-#define TFA99XX_CF_MAD 0x91
-#define TFA99XX_CF_MEM 0x92
-#define TFA99XX_CF_STATUS 0x93
-#define TFA99XX_MTPKEY1_REG 0xa0
-#define TFA99XX_MTPKEY2_REG 0xa1
-#define TFA99XX_MTP_STATUS 0xa2
-#define TFA99XX_KEY_PROTECTED_MTP_CONTROL 0xa3
-#define TFA99XX_KEY1_PROTECTED_FAIM_CONTROL 0xa4
-#define TFA99XX_MTP_DATA_OUT_MSB 0xa5
-#define TFA99XX_MTP_DATA_OUT_LSB 0xa6
-#define TFA99XX_KEY1_PROTECTED_PROTECTION_CONFIG 0xb0
-#define TFA99XX_TEMP_SENSOR_CONFIG 0xb1
-#define TFA99XX_KEY1_PROTECTED_DIRECT_CONTROL0 0xc0
-#define TFA99XX_KEY1_PROTECTED_DIRECT_CONTROL1 0xc1
-#define TFA99XX_KEY1_PROTECTED_TEST_CONFIG0 0xc3
-#define TFA99XX_KEY1_PROTECTED_TEST_CONFIG1 0xc4
-#define TFA99XX_KEY1_PROTECTED_TEST_CONFIG2 0xc5
-#define TFA99XX_KEY1_PROTECTED_TEST_CONFIG3 0xc6
-#define TFA99XX_KEY1_PROTECTED_DIGIMUX_CONTROL1 0xc8
-#define TFA99XX_KEY1_PROTECTED_ANAMUX_CONTROL0 0xca
-#define TFA99XX_KEY1_PROTECTED_ANAMUX_CONTROL1 0xcb
-#define TFA99XX_KEY1_PROTECTED_PLL_TEST0 0xcd
-#define TFA99XX_KEY1_PROTECTED_PLL_TEST3 0xd0
-#define TFA99XX_KEY1_PROTECTED_TSIG_CONTROL1 0xd2
-#define TFA99XX_KEY1_PROTECTED_ADC10_CONTROL 0xd3
-#define TFA99XX_KEY1_PROTECTED_ADC10_DATA 0xd4
-#define TFA99XX_KEY2_PROTECTED_CTRL_DIGTOANA 0xd5
-#define TFA99XX_KEY1_PROTECTED_CLKDIV_CONTROL 0xd6
-#define TFA99XX_KEY1_PROTECTED_IO_CONFIG2 0xd7
-#define TFA99XX_KEY1_PROTECTED_TEST_CTRL1 0xd8
-#define TFA99XX_KEY1_PROTECTED_MODE_OVERRULE 0xd9
-#define TFA99XX_KEY1_PROTECTED_FRO8_CALIB_CTRL 0xed
-#define TFA99XX_SOFTWARE_PROFILE 0xee
-#define TFA99XX_SOFTWARE_VSTEP 0xef
-#define TFA99XX_KEY2_PROTECTED_MTP0 0xf0
-#define TFA99XX_KEY1_PROTECTED_MTP2 0xf2
-#define TFA99XX_KEY2_PROTECTED_MTP4 0xf4
-#define TFA99XX_KEY1_PROTECTED_MTP6 0xf6
-#define TFA99XX_KEY1_PROTECTED_MTP7 0xf7
-#define TFA99XX_KEY1_PROTECTED_MTP9 0xf9
-#define TFA99XX_KEY1_PROTECTED_MTPF 0xff
-#define TFA99XX_SYS_CONTROL0_POR
-#define TFA99XX_SYS_CONTROL1_POR
-#define TFA99XX_SYS_CONTROL2_POR
-#define TFA99XX_DEVICE_REVISION_POR
-#define TFA99XX_CLOCK_CONTROL_POR
-#define TFA99XX_CLOCK_GATING_CONTROL_POR
-#define TFA99XX_HW_PATH_CFG_POR
-#define TFA99XX_CLKCHK_TH_POR
-#define TFA99XX_AMP_CTRL_POR
-#define TFA99XX_SIDE_TONE_CONFIG_POR
-#define TFA99XX_CTRL_DIGTOANA_REG_POR
-#define TFA99XX_STATUS_FLAGS0_POR
-#define TFA99XX_STATUS_FLAGS1_POR
-#define TFA99XX_STATUS_FLAGS3_POR
-#define TFA99XX_STATUS_FLAGS4_POR
-#define TFA99XX_BATTERY_VOLTAGE_POR
-#define TFA99XX_TEMPERATURE_POR
-#define TFA99XX_VDDP_VOLTAGE_POR
-#define TFA99XX_TDM_CONFIG0_POR
-#define TFA99XX_TDM_CONFIG1_POR
-#define TFA99XX_TDM_CONFIG2_POR
-#define TFA99XX_TDM_CONFIG3_POR
-#define TFA99XX_TDM_CONFIG4_POR
-#define TFA99XX_TDM_CONFIG5_POR
-#define TFA99XX_TDM_CONFIG6_POR
-#define TFA99XX_TDM_CONFIG7_POR
-#define TFA99XX_TDM_CONFIG8_POR
-#define TFA99XX_TDM_CONFIG9_POR
-#define TFA99XX_PDM_CONFIG0_POR
-#define TFA99XX_PDM_CONFIG1_POR
-#define TFA99XX_INTERRUPT_OUT_REG1_POR
-#define TFA99XX_INTERRUPT_OUT_REG2_POR
-#define TFA99XX_INTERRUPT_OUT_REG3_POR
-#define TFA99XX_INTERRUPT_IN_REG1_POR
-#define TFA99XX_INTERRUPT_IN_REG2_POR
-#define TFA99XX_INTERRUPT_IN_REG3_POR
-#define TFA99XX_INTERRUPT_ENABLE_REG1_POR
-#define TFA99XX_INTERRUPT_ENABLE_REG2_POR
-#define TFA99XX_INTERRUPT_ENABLE_REG3_POR
-#define TFA99XX_STATUS_POLARITY_REG1_POR
-#define TFA99XX_STATUS_POLARITY_REG2_POR
-#define TFA99XX_STATUS_POLARITY_REG3_POR
-#define TFA99XX_BAT_PROT_CONFIG_POR
-#define TFA99XX_AUDIO_CONTROL_POR
-#define TFA99XX_AMPLIFIER_CONFIG_POR
-#define TFA99XX_KEY1_PROTECTED_AMPLIFIER_CONTROL0_POR
-#define TFA99XX_KEY1_PROTECTED_AMPLIFIER_CONTROL1_POR
-#define TFA99XX_KEY1_PROTECTED_AMPLIFIER_CONTROL2_POR
-#define TFA99XX_KEY1_PROTECTED_AMPLIFIER_CONTROL4_POR
-#define TFA99XX_KEY1_PROTECTED_PWM_CONFIG_POR
-#define TFA99XX_CF_TAP_STATUS_0_POR
-#define TFA99XX_CF_TAP_STATUS_1_POR
-#define TFA99XX_TAP_CONTROL_POR
-#define TFA99XX_PGA_CONTROL0_POR
-#define TFA99XX_GAIN_ATT_POR
-#define TFA99XX_LOW_NOISE_GAIN1_POR
-#define TFA99XX_LOW_NOISE_GAIN2_POR
-#define TFA99XX_MODE1_DETECTOR1_POR
-#define TFA99XX_MODE1_DETECTOR2_POR
-#define TFA99XX_BST_PFM_CTRL_POR
-#define TFA99XX_LOW_POWER_CTRL_POR
-#define TFA99XX_TDM_SOURCE_CTRL_POR
-#define TFA99XX_SAM_CTRL_POR
-#define TFA99XX_RST_MIN_VBAT_CTRL_POR
-#define TFA99XX_SYS_CONTROL3_POR
-#define TFA99XX_STATUS_FLAGS5_POR
-#define TFA99XX_DCDC_CONTROL0_POR
-#define TFA99XX_KEY1_PROTECTED_DCDC_CONTROL3_POR
-#define TFA99XX_DCDC_CONTROL4_POR
-#define TFA99XX_DCDC_CONTROL5_POR
-#define TFA99XX_DCDC_CONTROL6_POR
-#define TFA99XX_KEY2_PROTECTED_DCDC_CONTROL7_POR
-#define TFA99XX_KEY2_PROTECTED_CURSENSE_CONFIG0_POR
-#define TFA99XX_KEY2_PROTECTED_CURSENSE_CONFIG2_POR
-#define TFA99XX_KEY2_PROTECTED_CURSENSE_CONFIG3_POR
-#define TFA99XX_KEY2_PROTECTED_CURSENSE_CONFIG4_POR
-#define TFA99XX_KEY2_PROTECTED_CURSENSE_CONFIG5_POR
-#define TFA99XX_KEY2_PROTECTED_CURSENSE_CONFIG7_POR
-#define TFA99XX_KEY2_PROTECTED_VOLSENSE_CONFIG_POR
-#define TFA99XX_CURSENSE_CONFIG_POR
-#define TFA99XX_CF_CONTROLS_POR
-#define TFA99XX_CF_MAD_POR
-#define TFA99XX_CF_MEM_POR
-#define TFA99XX_CF_STATUS_POR
-#define TFA99XX_MTPKEY1_REG_POR
-#define TFA99XX_MTPKEY2_REG_POR
-#define TFA99XX_MTP_STATUS_POR
-#define TFA99XX_KEY_PROTECTED_MTP_CONTROL_POR
-#define TFA99XX_KEY1_PROTECTED_FAIM_CONTROL_POR
-#define TFA99XX_MTP_DATA_OUT_MSB_POR
-#define TFA99XX_MTP_DATA_OUT_LSB_POR
-#define TFA99XX_KEY1_PROTECTED_PROTECTION_CONFIG_POR
-#define TFA99XX_TEMP_SENSOR_CONFIG_POR
-#define TFA99XX_KEY1_PROTECTED_DIRECT_CONTROL0_POR
-#define TFA99XX_KEY1_PROTECTED_DIRECT_CONTROL1_POR
-#define TFA99XX_KEY1_PROTECTED_TEST_CONFIG0_POR
-#define TFA99XX_KEY1_PROTECTED_TEST_CONFIG1_POR
-#define TFA99XX_KEY1_PROTECTED_TEST_CONFIG2_POR
-#define TFA99XX_KEY1_PROTECTED_TEST_CONFIG3_POR
-#define TFA99XX_KEY1_PROTECTED_DIGIMUX_CONTROL1_POR
-#define TFA99XX_KEY1_PROTECTED_ANAMUX_CONTROL0_POR
-#define TFA99XX_KEY1_PROTECTED_ANAMUX_CONTROL1_POR
-#define TFA99XX_KEY1_PROTECTED_PLL_TEST0_POR
-#define TFA99XX_KEY1_PROTECTED_PLL_TEST3_POR
-#define TFA99XX_KEY1_PROTECTED_TSIG_CONTROL1_POR
-#define TFA99XX_KEY1_PROTECTED_ADC10_CONTROL_POR
-#define TFA99XX_KEY1_PROTECTED_ADC10_DATA_POR
-#define TFA99XX_KEY2_PROTECTED_CTRL_DIGTOANA_POR
-#define TFA99XX_KEY1_PROTECTED_CLKDIV_CONTROL_POR
-#define TFA99XX_KEY1_PROTECTED_IO_CONFIG2_POR
-#define TFA99XX_KEY1_PROTECTED_TEST_CTRL1_POR
-#define TFA99XX_KEY1_PROTECTED_MODE_OVERRULE_POR
-#define TFA99XX_KEY1_PROTECTED_FRO8_CALIB_CTRL_POR
-#define TFA99XX_SOFTWARE_PROFILE_POR
-#define TFA99XX_SOFTWARE_VSTEP_POR
-#define TFA99XX_KEY2_PROTECTED_MTP0_POR
-#define TFA99XX_KEY1_PROTECTED_MTP2_POR
-#define TFA99XX_KEY2_PROTECTED_MTP4_POR
-#define TFA99XX_KEY1_PROTECTED_MTP6_POR
-#define TFA99XX_KEY1_PROTECTED_MTP7_POR
-#define TFA99XX_KEY1_PROTECTED_MTP9_POR
-#define TFA99XX_KEY1_PROTECTED_MTPF_POR
-
-#endif /* _TFA9912_DEVICE_GENREGS_H */
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index 0032076..c0542de 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -312,7 +312,7 @@ struct drm_dp_resource_status_notify {
struct drm_dp_query_payload_ack_reply {
u8 port_number;
- u8 allocated_pbn;
+ u16 allocated_pbn;
};
struct drm_dp_sideband_msg_req_body {
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 719eb97..5670bb9 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -77,7 +77,7 @@ static inline bool has_acpi_companion(struct device *dev)
static inline void acpi_preset_companion(struct device *dev,
struct acpi_device *parent, u64 addr)
{
- ACPI_COMPANION_SET(dev, acpi_find_child_device(parent, addr, NULL));
+ ACPI_COMPANION_SET(dev, acpi_find_child_device(parent, addr, false));
}
static inline const char *acpi_dev_name(struct acpi_device *adev)
diff --git a/include/linux/atalk.h b/include/linux/atalk.h
index af43ed4..4be0e14 100644
--- a/include/linux/atalk.h
+++ b/include/linux/atalk.h
@@ -107,7 +107,7 @@ static __inline__ struct elapaarp *aarp_hdr(struct sk_buff *skb)
#define AARP_RESOLVE_TIME (10 * HZ)
extern struct datalink_proto *ddp_dl, *aarp_dl;
-extern void aarp_proto_init(void);
+extern int aarp_proto_init(void);
/* Inter module exports */
diff --git a/include/linux/bpf-cgroup.h b/include/linux/bpf-cgroup.h
index ace92fc..ed3bb3d 100644
--- a/include/linux/bpf-cgroup.h
+++ b/include/linux/bpf-cgroup.h
@@ -13,27 +13,42 @@ struct sk_buff;
extern struct static_key_false cgroup_bpf_enabled_key;
#define cgroup_bpf_enabled static_branch_unlikely(&cgroup_bpf_enabled_key)
+struct bpf_prog_list {
+ struct list_head node;
+ struct bpf_prog *prog;
+};
+
+struct bpf_prog_array;
+
struct cgroup_bpf {
- /*
- * Store two sets of bpf_prog pointers, one for programs that are
- * pinned directly to this cgroup, and one for those that are effective
- * when this cgroup is accessed.
+ /* array of effective progs in this cgroup */
+ struct bpf_prog_array __rcu *effective[MAX_BPF_ATTACH_TYPE];
+
+ /* attached progs to this cgroup and attach flags
+ * when flags == 0 or BPF_F_ALLOW_OVERRIDE the progs list will
+ * have either zero or one element
+ * when BPF_F_ALLOW_MULTI the list can have up to BPF_CGROUP_MAX_PROGS
*/
- struct bpf_prog *prog[MAX_BPF_ATTACH_TYPE];
- struct bpf_prog *effective[MAX_BPF_ATTACH_TYPE];
- bool disallow_override[MAX_BPF_ATTACH_TYPE];
+ struct list_head progs[MAX_BPF_ATTACH_TYPE];
+ u32 flags[MAX_BPF_ATTACH_TYPE];
+
+ /* temp storage for effective prog array used by prog_attach/detach */
+ struct bpf_prog_array __rcu *inactive;
};
void cgroup_bpf_put(struct cgroup *cgrp);
-void cgroup_bpf_inherit(struct cgroup *cgrp, struct cgroup *parent);
+int cgroup_bpf_inherit(struct cgroup *cgrp);
-int __cgroup_bpf_update(struct cgroup *cgrp, struct cgroup *parent,
- struct bpf_prog *prog, enum bpf_attach_type type,
- bool overridable);
+int __cgroup_bpf_attach(struct cgroup *cgrp, struct bpf_prog *prog,
+ enum bpf_attach_type type, u32 flags);
+int __cgroup_bpf_detach(struct cgroup *cgrp, struct bpf_prog *prog,
+ enum bpf_attach_type type, u32 flags);
-/* Wrapper for __cgroup_bpf_update() protected by cgroup_mutex */
-int cgroup_bpf_update(struct cgroup *cgrp, struct bpf_prog *prog,
- enum bpf_attach_type type, bool overridable);
+/* Wrapper for __cgroup_bpf_*() protected by cgroup_mutex */
+int cgroup_bpf_attach(struct cgroup *cgrp, struct bpf_prog *prog,
+ enum bpf_attach_type type, u32 flags);
+int cgroup_bpf_detach(struct cgroup *cgrp, struct bpf_prog *prog,
+ enum bpf_attach_type type, u32 flags);
int __cgroup_bpf_run_filter(struct sock *sk,
struct sk_buff *skb,
@@ -66,8 +81,7 @@ int __cgroup_bpf_run_filter(struct sock *sk,
struct cgroup_bpf {};
static inline void cgroup_bpf_put(struct cgroup *cgrp) {}
-static inline void cgroup_bpf_inherit(struct cgroup *cgrp,
- struct cgroup *parent) {}
+static inline int cgroup_bpf_inherit(struct cgroup *cgrp) { return 0; }
#define BPF_CGROUP_RUN_PROG_INET_INGRESS(sk,skb) ({ 0; })
#define BPF_CGROUP_RUN_PROG_INET_EGRESS(sk,skb) ({ 0; })
diff --git a/include/linux/bpf.h b/include/linux/bpf.h
index cd6aaf0..30b808f 100644
--- a/include/linux/bpf.h
+++ b/include/linux/bpf.h
@@ -241,6 +241,58 @@ typedef unsigned long (*bpf_ctx_copy_t)(void *dst, const void *src,
u64 bpf_event_output(struct bpf_map *map, u64 flags, void *meta, u64 meta_size,
void *ctx, u64 ctx_size, bpf_ctx_copy_t ctx_copy);
+/* an array of programs to be executed under rcu_lock.
+ *
+ * Typical usage:
+ * ret = BPF_PROG_RUN_ARRAY(&bpf_prog_array, ctx, BPF_PROG_RUN);
+ *
+ * the structure returned by bpf_prog_array_alloc() should be populated
+ * with program pointers and the last pointer must be NULL.
+ * The user has to keep refcnt on the program and make sure the program
+ * is removed from the array before bpf_prog_put().
+ * The 'struct bpf_prog_array *' should only be replaced with xchg()
+ * since other cpus are walking the array of pointers in parallel.
+ */
+struct bpf_prog_array {
+ struct rcu_head rcu;
+ struct bpf_prog *progs[0];
+};
+
+struct bpf_prog_array __rcu *bpf_prog_array_alloc(u32 prog_cnt, gfp_t flags);
+void bpf_prog_array_free(struct bpf_prog_array __rcu *progs);
+
+void bpf_prog_array_delete_safe(struct bpf_prog_array __rcu *progs,
+ struct bpf_prog *old_prog);
+int bpf_prog_array_copy(struct bpf_prog_array __rcu *old_array,
+ struct bpf_prog *exclude_prog,
+ struct bpf_prog *include_prog,
+ struct bpf_prog_array **new_array);
+
+#define __BPF_PROG_RUN_ARRAY(array, ctx, func, check_non_null) \
+ ({ \
+ struct bpf_prog **_prog, *__prog; \
+ struct bpf_prog_array *_array; \
+ u32 _ret = 1; \
+ rcu_read_lock(); \
+ _array = rcu_dereference(array); \
+ if (unlikely(check_non_null && !_array))\
+ goto _out; \
+ _prog = _array->progs; \
+ while ((__prog = READ_ONCE(*_prog))) { \
+ _ret &= func(__prog, ctx); \
+ _prog++; \
+ } \
+_out: \
+ rcu_read_unlock(); \
+ _ret; \
+ })
+
+#define BPF_PROG_RUN_ARRAY(array, ctx, func) \
+ __BPF_PROG_RUN_ARRAY(array, ctx, func, false)
+
+#define BPF_PROG_RUN_ARRAY_CHECK(array, ctx, func) \
+ __BPF_PROG_RUN_ARRAY(array, ctx, func, true)
+
#ifdef CONFIG_BPF_SYSCALL
DECLARE_PER_CPU(int, bpf_prog_active);
diff --git a/include/linux/cec-funcs.h b/include/linux/cec-funcs.h
index 138bbf7..a844749 100644
--- a/include/linux/cec-funcs.h
+++ b/include/linux/cec-funcs.h
@@ -956,7 +956,8 @@ static inline void cec_msg_give_deck_status(struct cec_msg *msg,
msg->len = 3;
msg->msg[1] = CEC_MSG_GIVE_DECK_STATUS;
msg->msg[2] = status_req;
- msg->reply = reply ? CEC_MSG_DECK_STATUS : 0;
+ msg->reply = (reply && status_req != CEC_OP_STATUS_REQ_OFF) ?
+ CEC_MSG_DECK_STATUS : 0;
}
static inline void cec_ops_give_deck_status(const struct cec_msg *msg,
@@ -1060,7 +1061,8 @@ static inline void cec_msg_give_tuner_device_status(struct cec_msg *msg,
msg->len = 3;
msg->msg[1] = CEC_MSG_GIVE_TUNER_DEVICE_STATUS;
msg->msg[2] = status_req;
- msg->reply = reply ? CEC_MSG_TUNER_DEVICE_STATUS : 0;
+ msg->reply = (reply && status_req != CEC_OP_STATUS_REQ_OFF) ?
+ CEC_MSG_TUNER_DEVICE_STATUS : 0;
}
static inline void cec_ops_give_tuner_device_status(const struct cec_msg *msg,
diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index 69935e66..c336f93 100644
--- a/include/linux/dma-mapping.h
+++ b/include/linux/dma-mapping.h
@@ -689,8 +689,7 @@ static inline unsigned int dma_get_max_seg_size(struct device *dev)
return SZ_64K;
}
-static inline unsigned int dma_set_max_seg_size(struct device *dev,
- unsigned int size)
+static inline int dma_set_max_seg_size(struct device *dev, unsigned int size)
{
if (dev->dma_parms) {
dev->dma_parms->max_segment_size = size;
diff --git a/include/linux/filter.h b/include/linux/filter.h
index 0837d90..69e8e19 100644
--- a/include/linux/filter.h
+++ b/include/linux/filter.h
@@ -423,7 +423,7 @@ struct sk_filter {
struct bpf_prog *prog;
};
-#define BPF_PROG_RUN(filter, ctx) (*filter->bpf_func)(ctx, filter->insnsi)
+#define BPF_PROG_RUN(filter, ctx) (*(filter)->bpf_func)(ctx, (filter)->insnsi)
#define BPF_SKB_CB_LEN QDISC_CB_PRIV_LEN
diff --git a/include/linux/hid.h b/include/linux/hid.h
index c43f58e..09a2a13 100644
--- a/include/linux/hid.h
+++ b/include/linux/hid.h
@@ -524,10 +524,12 @@ struct hid_device { /* device report descriptor */
* battery is non-NULL.
*/
struct power_supply *battery;
+ __s32 battery_capacity;
__s32 battery_min;
__s32 battery_max;
__s32 battery_report_type;
__s32 battery_report_id;
+ bool battery_reported;
#endif
unsigned int status; /* see STAT flags above */
diff --git a/include/linux/hrtimer.h b/include/linux/hrtimer.h
index 9523c60..2869fb1 100644
--- a/include/linux/hrtimer.h
+++ b/include/linux/hrtimer.h
@@ -419,12 +419,18 @@ extern u64 hrtimer_get_next_event(void);
extern bool hrtimer_active(const struct hrtimer *timer);
-/*
- * Helper function to check, whether the timer is on one of the queues
+/**
+ * hrtimer_is_queued = check, whether the timer is on one of the queues
+ * @timer: Timer to check
+ *
+ * Returns: True if the timer is queued, false otherwise
+ *
+ * The function can be used lockless, but it gives only a current snapshot.
*/
-static inline int hrtimer_is_queued(struct hrtimer *timer)
+static inline bool hrtimer_is_queued(struct hrtimer *timer)
{
- return timer->state & HRTIMER_STATE_ENQUEUED;
+ /* The READ_ONCE pairs with the update functions of timer->state */
+ return !!(READ_ONCE(timer->state) & HRTIMER_STATE_ENQUEUED);
}
/*
diff --git a/include/linux/jbd2.h b/include/linux/jbd2.h
index d073470..344eb87 100644
--- a/include/linux/jbd2.h
+++ b/include/linux/jbd2.h
@@ -1560,7 +1560,7 @@ static inline int jbd2_space_needed(journal_t *journal)
static inline unsigned long jbd2_log_space_left(journal_t *journal)
{
/* Allow for rounding errors */
- unsigned long free = journal->j_free - 32;
+ long free = journal->j_free - 32;
if (journal->j_committing_transaction) {
unsigned long committing = atomic_read(&journal->
@@ -1569,7 +1569,7 @@ static inline unsigned long jbd2_log_space_left(journal_t *journal)
/* Transaction + control blocks */
free -= committing + (committing >> JBD2_CONTROL_BLOCKS_SHIFT);
}
- return free;
+ return max_t(long, free, 0);
}
/*
diff --git a/include/linux/libfdt_env.h b/include/linux/libfdt_env.h
index 8850e24..bd0a558 100644
--- a/include/linux/libfdt_env.h
+++ b/include/linux/libfdt_env.h
@@ -6,6 +6,9 @@
#include <asm/byteorder.h>
+#define INT32_MAX S32_MAX
+#define UINT32_MAX U32_MAX
+
typedef __be16 fdt16_t;
typedef __be32 fdt32_t;
typedef __be64 fdt64_t;
diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
index 85a43db..6b54319 100644
--- a/include/linux/mod_devicetable.h
+++ b/include/linux/mod_devicetable.h
@@ -520,9 +520,9 @@ struct platform_device_id {
#define MDIO_MODULE_PREFIX "mdio:"
-#define MDIO_ID_FMT "%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d"
+#define MDIO_ID_FMT "%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u%u"
#define MDIO_ID_ARGS(_id) \
- (_id)>>31, ((_id)>>30) & 1, ((_id)>>29) & 1, ((_id)>>28) & 1, \
+ ((_id)>>31) & 1, ((_id)>>30) & 1, ((_id)>>29) & 1, ((_id)>>28) & 1, \
((_id)>>27) & 1, ((_id)>>26) & 1, ((_id)>>25) & 1, ((_id)>>24) & 1, \
((_id)>>23) & 1, ((_id)>>22) & 1, ((_id)>>21) & 1, ((_id)>>20) & 1, \
((_id)>>19) & 1, ((_id)>>18) & 1, ((_id)>>17) & 1, ((_id)>>16) & 1, \
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 13f8052..13ddba5 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -392,7 +392,7 @@ static inline struct device_node *mtd_get_of_node(struct mtd_info *mtd)
return mtd->dev.of_node;
}
-static inline int mtd_oobavail(struct mtd_info *mtd, struct mtd_oob_ops *ops)
+static inline u32 mtd_oobavail(struct mtd_info *mtd, struct mtd_oob_ops *ops)
{
return ops->mode == MTD_OPS_AUTO_OOB ? mtd->oobavail : mtd->oobsize;
}
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index c2bc0da..a79980a 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -1730,6 +1730,11 @@ struct net_device {
unsigned char if_port;
unsigned char dma;
+ /* Note : dev->mtu is often read without holding a lock.
+ * Writers usually hold RTNL.
+ * It is recommended to use READ_ONCE() to annotate the reads,
+ * and to use WRITE_ONCE() to annotate the writes.
+ */
unsigned int mtu;
unsigned short type;
unsigned short hard_header_len;
diff --git a/include/linux/quota.h b/include/linux/quota.h
index 55107a8..23eb8ea 100644
--- a/include/linux/quota.h
+++ b/include/linux/quota.h
@@ -263,7 +263,7 @@ enum {
};
struct dqstats {
- int stat[_DQST_DQSTAT_LAST];
+ unsigned long stat[_DQST_DQSTAT_LAST];
struct percpu_counter counter[_DQST_DQSTAT_LAST];
};
diff --git a/include/linux/quotaops.h b/include/linux/quotaops.h
index 8773334..0a60fe3 100644
--- a/include/linux/quotaops.h
+++ b/include/linux/quotaops.h
@@ -54,6 +54,16 @@ static inline struct dquot *dqgrab(struct dquot *dquot)
atomic_inc(&dquot->dq_count);
return dquot;
}
+
+static inline bool dquot_is_busy(struct dquot *dquot)
+{
+ if (test_bit(DQ_MOD_B, &dquot->dq_flags))
+ return true;
+ if (atomic_read(&dquot->dq_count) > 1)
+ return true;
+ return false;
+}
+
void dqput(struct dquot *dquot);
int dquot_scan_active(struct super_block *sb,
int (*fn)(struct dquot *dquot, unsigned long priv),
diff --git a/include/linux/rculist_nulls.h b/include/linux/rculist_nulls.h
index 2720b2f..106f4e0 100644
--- a/include/linux/rculist_nulls.h
+++ b/include/linux/rculist_nulls.h
@@ -100,6 +100,43 @@ static inline void hlist_nulls_add_head_rcu(struct hlist_nulls_node *n,
}
/**
+ * hlist_nulls_add_tail_rcu
+ * @n: the element to add to the hash list.
+ * @h: the list to add to.
+ *
+ * Description:
+ * Adds the specified element to the specified hlist_nulls,
+ * while permitting racing traversals.
+ *
+ * The caller must take whatever precautions are necessary
+ * (such as holding appropriate locks) to avoid racing
+ * with another list-mutation primitive, such as hlist_nulls_add_head_rcu()
+ * or hlist_nulls_del_rcu(), running on this same list.
+ * However, it is perfectly legal to run concurrently with
+ * the _rcu list-traversal primitives, such as
+ * hlist_nulls_for_each_entry_rcu(), used to prevent memory-consistency
+ * problems on Alpha CPUs. Regardless of the type of CPU, the
+ * list-traversal primitive must be guarded by rcu_read_lock().
+ */
+static inline void hlist_nulls_add_tail_rcu(struct hlist_nulls_node *n,
+ struct hlist_nulls_head *h)
+{
+ struct hlist_nulls_node *i, *last = NULL;
+
+ /* Note: write side code, so rcu accessors are not needed. */
+ for (i = h->first; !is_a_nulls(i); i = i->next)
+ last = i;
+
+ if (last) {
+ n->next = last->next;
+ n->pprev = &last->next;
+ rcu_assign_pointer(hlist_next_rcu(last), n);
+ } else {
+ hlist_nulls_add_head_rcu(n, h);
+ }
+}
+
+/**
* hlist_nulls_for_each_entry_rcu - iterate over rcu list of given type
* @tpos: the type * to use as a loop cursor.
* @pos: the &struct hlist_nulls_node to use as a loop cursor.
diff --git a/include/linux/regulator/consumer.h b/include/linux/regulator/consumer.h
index a40c4c9..c7bafc7 100644
--- a/include/linux/regulator/consumer.h
+++ b/include/linux/regulator/consumer.h
@@ -482,7 +482,7 @@ static inline unsigned int regulator_get_mode(struct regulator *regulator)
static inline int regulator_set_load(struct regulator *regulator, int load_uA)
{
- return REGULATOR_MODE_NORMAL;
+ return 0;
}
static inline int regulator_allow_bypass(struct regulator *regulator,
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index c7dff69..695bb36 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -162,6 +162,7 @@ struct uart_port {
struct console *cons; /* struct console, if any */
#if defined(CONFIG_SERIAL_CORE_CONSOLE) || defined(SUPPORT_SYSRQ)
unsigned long sysrq; /* sysrq timeout */
+ unsigned int sysrq_ch; /* char for sysrq */
#endif
/* flags must be updated while holding port mutex */
@@ -471,8 +472,42 @@ uart_handle_sysrq_char(struct uart_port *port, unsigned int ch)
}
return 0;
}
+static inline int
+uart_prepare_sysrq_char(struct uart_port *port, unsigned int ch)
+{
+ if (port->sysrq) {
+ if (ch && time_before(jiffies, port->sysrq)) {
+ port->sysrq_ch = ch;
+ port->sysrq = 0;
+ return 1;
+ }
+ port->sysrq = 0;
+ }
+ return 0;
+}
+static inline void
+uart_unlock_and_check_sysrq(struct uart_port *port, unsigned long irqflags)
+{
+ int sysrq_ch;
+
+ sysrq_ch = port->sysrq_ch;
+ port->sysrq_ch = 0;
+
+ spin_unlock_irqrestore(&port->lock, irqflags);
+
+ if (sysrq_ch)
+ handle_sysrq(sysrq_ch);
+}
#else
-#define uart_handle_sysrq_char(port,ch) ({ (void)port; 0; })
+static inline int
+uart_handle_sysrq_char(struct uart_port *port, unsigned int ch) { return 0; }
+static inline int
+uart_prepare_sysrq_char(struct uart_port *port, unsigned int ch) { return 0; }
+static inline void
+uart_unlock_and_check_sysrq(struct uart_port *port, unsigned long irqflags)
+{
+ spin_unlock_irqrestore(&port->lock, irqflags);
+}
#endif
/*
diff --git a/include/linux/time.h b/include/linux/time.h
index 4cea09d..60fd505 100644
--- a/include/linux/time.h
+++ b/include/linux/time.h
@@ -275,4 +275,16 @@ static __always_inline void timespec_add_ns(struct timespec *a, u64 ns)
a->tv_nsec = ns;
}
+/**
+ * time_between32 - check if a 32-bit timestamp is within a given time range
+ * @t: the time which may be within [l,h]
+ * @l: the lower bound of the range
+ * @h: the higher bound of the range
+ *
+ * time_before32(t, l, h) returns true if @l <= @t <= @h. All operands are
+ * treated as 32-bit integers.
+ *
+ * Equivalent to !(time_before32(@t, @l) || time_after32(@t, @h)).
+ */
+#define time_between32(t, l, h) ((u32)(h) - (u32)(l) >= (u32)(t) - (u32)(l))
#endif
diff --git a/include/linux/trace_events.h b/include/linux/trace_events.h
index 751a510..25b777b 100644
--- a/include/linux/trace_events.h
+++ b/include/linux/trace_events.h
@@ -274,14 +274,37 @@ struct trace_event_call {
#ifdef CONFIG_PERF_EVENTS
int perf_refcount;
struct hlist_head __percpu *perf_events;
- struct bpf_prog *prog;
- struct perf_event *bpf_prog_owner;
+ struct bpf_prog_array __rcu *prog_array;
int (*perf_perm)(struct trace_event_call *,
struct perf_event *);
#endif
};
+#ifdef CONFIG_PERF_EVENTS
+static inline bool bpf_prog_array_valid(struct trace_event_call *call)
+{
+ /*
+ * This inline function checks whether call->prog_array
+ * is valid or not. The function is called in various places,
+ * outside rcu_read_lock/unlock, as a heuristic to speed up execution.
+ *
+ * If this function returns true, and later call->prog_array
+ * becomes false inside rcu_read_lock/unlock region,
+ * we bail out then. If this function return false,
+ * there is a risk that we might miss a few events if the checking
+ * were delayed until inside rcu_read_lock/unlock region and
+ * call->prog_array happened to become non-NULL then.
+ *
+ * Here, READ_ONCE() is used instead of rcu_access_pointer().
+ * rcu_access_pointer() requires the actual definition of
+ * "struct bpf_prog_array" while READ_ONCE() only needs
+ * a declaration of the same type.
+ */
+ return !!READ_ONCE(call->prog_array);
+}
+#endif
+
static inline const char *
trace_event_name(struct trace_event_call *call)
{
@@ -432,12 +455,23 @@ trace_trigger_soft_disabled(struct trace_event_file *file)
}
#ifdef CONFIG_BPF_EVENTS
-unsigned int trace_call_bpf(struct bpf_prog *prog, void *ctx);
+unsigned int trace_call_bpf(struct trace_event_call *call, void *ctx);
+int perf_event_attach_bpf_prog(struct perf_event *event, struct bpf_prog *prog);
+void perf_event_detach_bpf_prog(struct perf_event *event);
#else
-static inline unsigned int trace_call_bpf(struct bpf_prog *prog, void *ctx)
+static inline unsigned int trace_call_bpf(struct trace_event_call *call, void *ctx)
{
return 1;
}
+
+static inline int
+perf_event_attach_bpf_prog(struct perf_event *event, struct bpf_prog *prog)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline void perf_event_detach_bpf_prog(struct perf_event *event) { }
+
#endif
enum {
@@ -508,6 +542,7 @@ perf_trace_buf_submit(void *raw_data, int size, int rctx, u16 type,
{
perf_tp_event(type, count, raw_data, size, regs, head, rctx, task);
}
+
#endif
#endif /* _LINUX_TRACE_EVENT_H */
diff --git a/include/linux/tty.h b/include/linux/tty.h
index bcfeb9e..6f84114 100644
--- a/include/linux/tty.h
+++ b/include/linux/tty.h
@@ -360,6 +360,7 @@ struct tty_file_private {
#define TTY_NO_WRITE_SPLIT 17 /* Preserve write boundaries to driver */
#define TTY_HUPPED 18 /* Post driver->hangup() */
#define TTY_HUPPING 19 /* Hangup in progress */
+#define TTY_LDISC_CHANGING 20 /* Change pending - non-block IO */
#define TTY_LDISC_HALTED 22 /* Line discipline is halted */
/* Values for tty->flow_change */
@@ -377,6 +378,12 @@ static inline void tty_set_flow_change(struct tty_struct *tty, int val)
smp_mb();
}
+static inline bool tty_io_nonblock(struct tty_struct *tty, struct file *file)
+{
+ return file->f_flags & O_NONBLOCK ||
+ test_bit(TTY_LDISC_CHANGING, &tty->flags);
+}
+
static inline bool tty_io_error(struct tty_struct *tty)
{
return test_bit(TTY_IO_ERROR, &tty->flags);
diff --git a/include/math-emu/soft-fp.h b/include/math-emu/soft-fp.h
index 3f284bc..5650c16 100644
--- a/include/math-emu/soft-fp.h
+++ b/include/math-emu/soft-fp.h
@@ -138,7 +138,7 @@ do { \
_FP_FRAC_ADDI_##wc(X, _FP_WORK_ROUND); \
} while (0)
-#define _FP_ROUND_ZERO(wc, X) 0
+#define _FP_ROUND_ZERO(wc, X) (void)0
#define _FP_ROUND_PINF(wc, X) \
do { \
diff --git a/include/net/cnss2.h b/include/net/cnss2.h
index 601f021..d316a3b 100644
--- a/include/net/cnss2.h
+++ b/include/net/cnss2.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -181,6 +181,8 @@ enum cnss_recovery_reason {
extern int cnss_wlan_register_driver(struct cnss_wlan_driver *driver);
extern void cnss_wlan_unregister_driver(struct cnss_wlan_driver *driver);
extern void cnss_device_crashed(struct device *dev);
+extern int cnss_pci_prevent_l1(struct device *dev);
+extern void cnss_pci_allow_l1(struct device *dev);
extern int cnss_pci_link_down(struct device *dev);
extern int cnss_pci_is_device_down(struct device *dev);
extern void cnss_schedule_recovery(struct device *dev,
diff --git a/include/net/cnss_nl.h b/include/net/cnss_nl.h
index b8a7cfd..ede9505 100644
--- a/include/net/cnss_nl.h
+++ b/include/net/cnss_nl.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -26,6 +26,10 @@
* @CLD80211_ATTR_META_DATA: Embed meta data for above data. This will help
* wlan driver to peek into request message packet without opening up definition
* of complete request message.
+ * @CLD80211_ATTR_CMD: cld80211 vendor subcommand in this attribute
+ * @CLD80211_ATTR_CMD_TAG_DATA: cld80211 vendor subcommand data is present in
+ * this attribute. It is a nested attribute with sub attributes of specified
+ * vendor sub command.
*
* Any new message in future can be added as another attribute
*/
@@ -33,6 +37,8 @@ enum cld80211_attr {
CLD80211_ATTR_VENDOR_DATA = 1,
CLD80211_ATTR_DATA,
CLD80211_ATTR_META_DATA,
+ CLD80211_ATTR_CMD,
+ CLD80211_ATTR_CMD_TAG_DATA,
/* add new attributes above here */
__CLD80211_ATTR_AFTER_LAST,
diff --git a/include/net/dst.h b/include/net/dst.h
index ddcff17..e57e8fb 100644
--- a/include/net/dst.h
+++ b/include/net/dst.h
@@ -110,7 +110,7 @@ struct dst_entry {
struct dst_metrics {
u32 metrics[RTAX_MAX];
atomic_t refcnt;
-};
+} __aligned(4); /* Low pointer bits contain DST_METRICS_FLAGS */
extern const struct dst_metrics dst_default_metrics;
u32 *dst_cow_metrics_generic(struct dst_entry *dst, unsigned long old);
diff --git a/include/net/inet_hashtables.h b/include/net/inet_hashtables.h
index 0574493..fc445e7 100644
--- a/include/net/inet_hashtables.h
+++ b/include/net/inet_hashtables.h
@@ -98,12 +98,18 @@ struct inet_bind_hashbucket {
struct hlist_head chain;
};
-/*
- * Sockets can be hashed in established or listening table
+/* Sockets can be hashed in established or listening table.
+ * We must use different 'nulls' end-of-chain value for all hash buckets :
+ * A socket might transition from ESTABLISH to LISTEN state without
+ * RCU grace period. A lookup in ehash table needs to handle this case.
*/
+#define LISTENING_NULLS_BASE (1U << 29)
struct inet_listen_hashbucket {
spinlock_t lock;
- struct hlist_head head;
+ union {
+ struct hlist_head head;
+ struct hlist_nulls_head nulls_head;
+ };
};
/* This is for listening sockets, thus all sockets which possess wildcards. */
diff --git a/include/net/ip.h b/include/net/ip.h
index db6e110..06ad424 100644
--- a/include/net/ip.h
+++ b/include/net/ip.h
@@ -623,4 +623,9 @@ extern int sysctl_icmp_msgs_burst;
int ip_misc_proc_init(void);
#endif
+static inline bool inetdev_valid_mtu(unsigned int mtu)
+{
+ return likely(mtu >= IPV4_MIN_MTU);
+}
+
#endif /* _IP_H */
diff --git a/include/net/sock.h b/include/net/sock.h
index 646cc97..7a57d6f 100644
--- a/include/net/sock.h
+++ b/include/net/sock.h
@@ -662,6 +662,11 @@ static inline void __sk_nulls_add_node_rcu(struct sock *sk, struct hlist_nulls_h
hlist_nulls_add_head_rcu(&sk->sk_nulls_node, list);
}
+static inline void __sk_nulls_add_node_tail_rcu(struct sock *sk, struct hlist_nulls_head *list)
+{
+ hlist_nulls_add_tail_rcu(&sk->sk_nulls_node, list);
+}
+
static inline void sk_nulls_add_node_rcu(struct sock *sk, struct hlist_nulls_head *list)
{
sock_hold(sk);
diff --git a/include/net/tcp.h b/include/net/tcp.h
index 709ec95..92a5e83 100644
--- a/include/net/tcp.h
+++ b/include/net/tcp.h
@@ -510,19 +510,27 @@ struct sock *cookie_v4_check(struct sock *sk, struct sk_buff *skb);
*/
static inline void tcp_synq_overflow(const struct sock *sk)
{
- unsigned long last_overflow = tcp_sk(sk)->rx_opt.ts_recent_stamp;
+ unsigned long last_overflow = READ_ONCE(tcp_sk(sk)->rx_opt.ts_recent_stamp);
unsigned long now = jiffies;
- if (time_after(now, last_overflow + HZ))
- tcp_sk(sk)->rx_opt.ts_recent_stamp = now;
+ if (!time_between32(now, last_overflow, last_overflow + HZ))
+ WRITE_ONCE(tcp_sk(sk)->rx_opt.ts_recent_stamp, now);
}
/* syncookies: no recent synqueue overflow on this listening socket? */
static inline bool tcp_synq_no_recent_overflow(const struct sock *sk)
{
- unsigned long last_overflow = tcp_sk(sk)->rx_opt.ts_recent_stamp;
+ unsigned long last_overflow = READ_ONCE(tcp_sk(sk)->rx_opt.ts_recent_stamp);
- return time_after(jiffies, last_overflow + TCP_SYNCOOKIE_VALID);
+ /* If last_overflow <= jiffies <= last_overflow + TCP_SYNCOOKIE_VALID,
+ * then we're under synflood. However, we have to use
+ * 'last_overflow - HZ' as lower bound. That's because a concurrent
+ * tcp_synq_overflow() could update .ts_recent_stamp after we read
+ * jiffies but before we store .ts_recent_stamp into last_overflow,
+ * which could lead to rejecting a valid syncookie.
+ */
+ return !time_between32(jiffies, last_overflow - HZ,
+ last_overflow + TCP_SYNCOOKIE_VALID);
}
static inline u32 tcp_cookie_time(void)
diff --git a/include/scsi/iscsi_proto.h b/include/scsi/iscsi_proto.h
index c1260d8..1a2ae08 100644
--- a/include/scsi/iscsi_proto.h
+++ b/include/scsi/iscsi_proto.h
@@ -638,6 +638,7 @@ struct iscsi_reject {
#define ISCSI_REASON_BOOKMARK_INVALID 9
#define ISCSI_REASON_BOOKMARK_NO_RESOURCES 10
#define ISCSI_REASON_NEGOTIATION_RESET 11
+#define ISCSI_REASON_WAITING_FOR_LOGOUT 12
/* Max. number of Key=Value pairs in a text message */
#define MAX_KEY_VALUE_PAIRS 8192
diff --git a/include/trace/events/sched.h b/include/trace/events/sched.h
old mode 100644
new mode 100755
index be3d8b2..2b5c0e2
--- a/include/trace/events/sched.h
+++ b/include/trace/events/sched.h
@@ -1793,6 +1793,27 @@ TRACE_EVENT(sched_get_nr_running_avg,
__field( int, iowait_avg )
__field( unsigned int, max_nr )
__field( unsigned int, big_max_nr )
+ __array( char, comm, TASK_COMM_LEN )
+ __field( pid_t, pid )
+ __field( pid_t, cur_pid )
+ __field( u64, wallclock )
+ __field( u64, mark_start )
+ __field( u64, delta_m )
+ __field( u64, win_start )
+ __field( u64, delta )
+ __field( u64, irqtime )
+ __field( int, evt )
+ __field(unsigned int, demand )
+ __field(unsigned int, sum )
+ __field( int, cpu )
+ __field( u64, cs )
+ __field( u64, ps )
+ __field( u64, util )
+ __field( u32, curr_window )
+ __field( u32, prev_window )
+ __field( u64, nt_cs )
+ __field( u64, nt_ps )
+ __field( u32, active_windows )
),
TP_fast_assign(
@@ -1803,9 +1824,20 @@ TRACE_EVENT(sched_get_nr_running_avg,
__entry->big_max_nr = big_max_nr;
),
- TP_printk("avg=%d big_avg=%d iowait_avg=%d max_nr=%u big_max_nr=%u",
+ TP_printk("avg=%d big_avg=%d iowait_avg=%d max_nr=%u big_max_nr=%u"
+ " wc %llu ws %llu delta %llu event %d cpu %d cur_pid %d task %d (%s) ms %llu delta %llu demand %u sum %u irqtime %llu"
+ " cs %llu ps %llu util %llu cur_window %u prev_window %u active_wins %u",
__entry->avg, __entry->big_avg, __entry->iowait_avg,
- __entry->max_nr, __entry->big_max_nr)
+ __entry->max_nr, __entry->big_max_nr,
+ __entry->wallclock, __entry->win_start, __entry->delta,
+ __entry->evt, __entry->cpu, __entry->cur_pid,
+ __entry->pid, __entry->comm, __entry->mark_start,
+ __entry->delta_m, __entry->demand,
+ __entry->sum, __entry->irqtime,
+ __entry->cs, __entry->ps, __entry->util,
+ __entry->curr_window, __entry->prev_window,
+ __entry->active_windows
+ )
);
TRACE_EVENT(core_ctl_eval_need,
diff --git a/include/trace/perf.h b/include/trace/perf.h
index 04fe68bb..14f127b6 100644
--- a/include/trace/perf.h
+++ b/include/trace/perf.h
@@ -34,7 +34,6 @@ perf_trace_##call(void *__data, proto) \
struct trace_event_call *event_call = __data; \
struct trace_event_data_offsets_##call __maybe_unused __data_offsets;\
struct trace_event_raw_##call *entry; \
- struct bpf_prog *prog = event_call->prog; \
struct pt_regs *__regs; \
u64 __count = 1; \
struct task_struct *__task = NULL; \
@@ -46,8 +45,9 @@ perf_trace_##call(void *__data, proto) \
__data_size = trace_event_get_offsets_##call(&__data_offsets, args); \
\
head = this_cpu_ptr(event_call->perf_events); \
- if (!prog && __builtin_constant_p(!__task) && !__task && \
- hlist_empty(head)) \
+ if (!bpf_prog_array_valid(event_call) && \
+ __builtin_constant_p(!__task) && !__task && \
+ hlist_empty(head)) \
return; \
\
__entry_size = ALIGN(__data_size + sizeof(*entry) + sizeof(u32),\
diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h
index a339bea..67d7d77 100644
--- a/include/uapi/linux/bpf.h
+++ b/include/uapi/linux/bpf.h
@@ -109,11 +109,47 @@ enum bpf_attach_type {
#define MAX_BPF_ATTACH_TYPE __MAX_BPF_ATTACH_TYPE
-/* If BPF_F_ALLOW_OVERRIDE flag is used in BPF_PROG_ATTACH command
- * to the given target_fd cgroup the descendent cgroup will be able to
- * override effective bpf program that was inherited from this cgroup
+/* cgroup-bpf attach flags used in BPF_PROG_ATTACH command
+ *
+ * NONE(default): No further bpf programs allowed in the subtree.
+ *
+ * BPF_F_ALLOW_OVERRIDE: If a sub-cgroup installs some bpf program,
+ * the program in this cgroup yields to sub-cgroup program.
+ *
+ * BPF_F_ALLOW_MULTI: If a sub-cgroup installs some bpf program,
+ * that cgroup program gets run in addition to the program in this cgroup.
+ *
+ * Only one program is allowed to be attached to a cgroup with
+ * NONE or BPF_F_ALLOW_OVERRIDE flag.
+ * Attaching another program on top of NONE or BPF_F_ALLOW_OVERRIDE will
+ * release old program and attach the new one. Attach flags has to match.
+ *
+ * Multiple programs are allowed to be attached to a cgroup with
+ * BPF_F_ALLOW_MULTI flag. They are executed in FIFO order
+ * (those that were attached first, run first)
+ * The programs of sub-cgroup are executed first, then programs of
+ * this cgroup and then programs of parent cgroup.
+ * When children program makes decision (like picking TCP CA or sock bind)
+ * parent program has a chance to override it.
+ *
+ * A cgroup with MULTI or OVERRIDE flag allows any attach flags in sub-cgroups.
+ * A cgroup with NONE doesn't allow any programs in sub-cgroups.
+ * Ex1:
+ * cgrp1 (MULTI progs A, B) ->
+ * cgrp2 (OVERRIDE prog C) ->
+ * cgrp3 (MULTI prog D) ->
+ * cgrp4 (OVERRIDE prog E) ->
+ * cgrp5 (NONE prog F)
+ * the event in cgrp5 triggers execution of F,D,A,B in that order.
+ * if prog F is detached, the execution is E,D,A,B
+ * if prog F and D are detached, the execution is E,A,B
+ * if prog F, E and D are detached, the execution is C,A,B
+ *
+ * All eligible programs are executed regardless of return code from
+ * earlier programs.
*/
#define BPF_F_ALLOW_OVERRIDE (1U << 0)
+#define BPF_F_ALLOW_MULTI (1U << 1)
#define BPF_PSEUDO_MAP_FD 1
diff --git a/include/uapi/linux/msm_mdp.h b/include/uapi/linux/msm_mdp.h
index 8a0e4cf..9102741 100644
--- a/include/uapi/linux/msm_mdp.h
+++ b/include/uapi/linux/msm_mdp.h
@@ -7,6 +7,7 @@
#include <linux/types.h>
#endif
#include <linux/fb.h>
+#include <stdbool.h>
#define MSMFB_IOCTL_MAGIC 'm'
#define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int)
@@ -1275,6 +1276,8 @@ enum {
metadata_op_get_caps,
metadata_op_crc,
metadata_op_get_ion_fd,
+ metadata_op_secure_bl_set,
+ metadata_op_secure_reg,
metadata_op_max
};
@@ -1309,6 +1312,8 @@ struct msmfb_metadata {
struct mdss_hw_caps caps;
uint8_t secure_en;
int fbmem_ionfd;
+ bool sec_bl_update_en;
+ bool sec_reg_on;
} data;
};
diff --git a/kernel/audit_watch.c b/kernel/audit_watch.c
index f036b6a..712469a 100644
--- a/kernel/audit_watch.c
+++ b/kernel/audit_watch.c
@@ -365,12 +365,12 @@ static int audit_get_nd(struct audit_watch *watch, struct path *parent)
struct dentry *d = kern_path_locked(watch->path, parent);
if (IS_ERR(d))
return PTR_ERR(d);
- inode_unlock(d_backing_inode(parent->dentry));
if (d_is_positive(d)) {
/* update watch filter fields */
watch->dev = d->d_sb->s_dev;
watch->ino = d_backing_inode(d)->i_ino;
}
+ inode_unlock(d_backing_inode(parent->dentry));
dput(d);
return 0;
}
diff --git a/kernel/bpf/cgroup.c b/kernel/bpf/cgroup.c
index a44a7e4..54c47a9 100644
--- a/kernel/bpf/cgroup.c
+++ b/kernel/bpf/cgroup.c
@@ -27,129 +27,361 @@ void cgroup_bpf_put(struct cgroup *cgrp)
{
unsigned int type;
- for (type = 0; type < ARRAY_SIZE(cgrp->bpf.prog); type++) {
- struct bpf_prog *prog = cgrp->bpf.prog[type];
+ for (type = 0; type < ARRAY_SIZE(cgrp->bpf.progs); type++) {
+ struct list_head *progs = &cgrp->bpf.progs[type];
+ struct bpf_prog_list *pl, *tmp;
- if (prog) {
- bpf_prog_put(prog);
+ list_for_each_entry_safe(pl, tmp, progs, node) {
+ list_del(&pl->node);
+ bpf_prog_put(pl->prog);
+ kfree(pl);
static_branch_dec(&cgroup_bpf_enabled_key);
}
+ bpf_prog_array_free(cgrp->bpf.effective[type]);
}
}
+/* count number of elements in the list.
+ * it's slow but the list cannot be long
+ */
+static u32 prog_list_length(struct list_head *head)
+{
+ struct bpf_prog_list *pl;
+ u32 cnt = 0;
+
+ list_for_each_entry(pl, head, node) {
+ if (!pl->prog)
+ continue;
+ cnt++;
+ }
+ return cnt;
+}
+
+/* if parent has non-overridable prog attached,
+ * disallow attaching new programs to the descendent cgroup.
+ * if parent has overridable or multi-prog, allow attaching
+ */
+static bool hierarchy_allows_attach(struct cgroup *cgrp,
+ enum bpf_attach_type type,
+ u32 new_flags)
+{
+ struct cgroup *p;
+
+ p = cgroup_parent(cgrp);
+ if (!p)
+ return true;
+ do {
+ u32 flags = p->bpf.flags[type];
+ u32 cnt;
+
+ if (flags & BPF_F_ALLOW_MULTI)
+ return true;
+ cnt = prog_list_length(&p->bpf.progs[type]);
+ WARN_ON_ONCE(cnt > 1);
+ if (cnt == 1)
+ return !!(flags & BPF_F_ALLOW_OVERRIDE);
+ p = cgroup_parent(p);
+ } while (p);
+ return true;
+}
+
+/* compute a chain of effective programs for a given cgroup:
+ * start from the list of programs in this cgroup and add
+ * all parent programs.
+ * Note that parent's F_ALLOW_OVERRIDE-type program is yielding
+ * to programs in this cgroup
+ */
+static int compute_effective_progs(struct cgroup *cgrp,
+ enum bpf_attach_type type,
+ struct bpf_prog_array __rcu **array)
+{
+ struct bpf_prog_array __rcu *progs;
+ struct bpf_prog_list *pl;
+ struct cgroup *p = cgrp;
+ int cnt = 0;
+
+ /* count number of effective programs by walking parents */
+ do {
+ if (cnt == 0 || (p->bpf.flags[type] & BPF_F_ALLOW_MULTI))
+ cnt += prog_list_length(&p->bpf.progs[type]);
+ p = cgroup_parent(p);
+ } while (p);
+
+ progs = bpf_prog_array_alloc(cnt, GFP_KERNEL);
+ if (!progs)
+ return -ENOMEM;
+
+ /* populate the array with effective progs */
+ cnt = 0;
+ p = cgrp;
+ do {
+ if (cnt == 0 || (p->bpf.flags[type] & BPF_F_ALLOW_MULTI))
+ list_for_each_entry(pl,
+ &p->bpf.progs[type], node) {
+ if (!pl->prog)
+ continue;
+ rcu_dereference_protected(progs, 1)->
+ progs[cnt++] = pl->prog;
+ }
+ p = cgroup_parent(p);
+ } while (p);
+
+ *array = progs;
+ return 0;
+}
+
+static void activate_effective_progs(struct cgroup *cgrp,
+ enum bpf_attach_type type,
+ struct bpf_prog_array __rcu *array)
+{
+ struct bpf_prog_array __rcu *old_array;
+
+ old_array = xchg(&cgrp->bpf.effective[type], array);
+ /* free prog array after grace period, since __cgroup_bpf_run_*()
+ * might be still walking the array
+ */
+ bpf_prog_array_free(old_array);
+}
+
/**
* cgroup_bpf_inherit() - inherit effective programs from parent
* @cgrp: the cgroup to modify
- * @parent: the parent to inherit from
*/
-void cgroup_bpf_inherit(struct cgroup *cgrp, struct cgroup *parent)
+int cgroup_bpf_inherit(struct cgroup *cgrp)
{
- unsigned int type;
+/* has to use marco instead of const int, since compiler thinks
+ * that array below is variable length
+ */
+#define NR ARRAY_SIZE(cgrp->bpf.effective)
+ struct bpf_prog_array __rcu *arrays[NR] = {};
+ int i;
- for (type = 0; type < ARRAY_SIZE(cgrp->bpf.effective); type++) {
- struct bpf_prog *e;
+ for (i = 0; i < NR; i++)
+ INIT_LIST_HEAD(&cgrp->bpf.progs[i]);
- e = rcu_dereference_protected(parent->bpf.effective[type],
- lockdep_is_held(&cgroup_mutex));
- rcu_assign_pointer(cgrp->bpf.effective[type], e);
- cgrp->bpf.disallow_override[type] = parent->bpf.disallow_override[type];
- }
+ for (i = 0; i < NR; i++)
+ if (compute_effective_progs(cgrp, i, &arrays[i]))
+ goto cleanup;
+
+ for (i = 0; i < NR; i++)
+ activate_effective_progs(cgrp, i, arrays[i]);
+
+ return 0;
+cleanup:
+ for (i = 0; i < NR; i++)
+ bpf_prog_array_free(arrays[i]);
+ return -ENOMEM;
}
+#define BPF_CGROUP_MAX_PROGS 64
+
/**
- * __cgroup_bpf_update() - Update the pinned program of a cgroup, and
+ * __cgroup_bpf_attach() - Attach the program to a cgroup, and
* propagate the change to descendants
* @cgrp: The cgroup which descendants to traverse
- * @parent: The parent of @cgrp, or %NULL if @cgrp is the root
- * @prog: A new program to pin
- * @type: Type of pinning operation (ingress/egress)
- *
- * Each cgroup has a set of two pointers for bpf programs; one for eBPF
- * programs it owns, and which is effective for execution.
- *
- * If @prog is not %NULL, this function attaches a new program to the cgroup
- * and releases the one that is currently attached, if any. @prog is then made
- * the effective program of type @type in that cgroup.
- *
- * If @prog is %NULL, the currently attached program of type @type is released,
- * and the effective program of the parent cgroup (if any) is inherited to
- * @cgrp.
- *
- * Then, the descendants of @cgrp are walked and the effective program for
- * each of them is set to the effective program of @cgrp unless the
- * descendant has its own program attached, in which case the subbranch is
- * skipped. This ensures that delegated subcgroups with own programs are left
- * untouched.
+ * @prog: A program to attach
+ * @type: Type of attach operation
*
* Must be called with cgroup_mutex held.
*/
-int __cgroup_bpf_update(struct cgroup *cgrp, struct cgroup *parent,
- struct bpf_prog *prog, enum bpf_attach_type type,
- bool new_overridable)
+int __cgroup_bpf_attach(struct cgroup *cgrp, struct bpf_prog *prog,
+ enum bpf_attach_type type, u32 flags)
{
- struct bpf_prog *old_prog, *effective = NULL;
- struct cgroup_subsys_state *pos;
- bool overridable = true;
+ struct list_head *progs = &cgrp->bpf.progs[type];
+ struct bpf_prog *old_prog = NULL;
+ struct cgroup_subsys_state *css;
+ struct bpf_prog_list *pl;
+ bool pl_was_allocated;
+ u32 old_flags;
+ int err;
- if (parent) {
- overridable = !parent->bpf.disallow_override[type];
- effective = rcu_dereference_protected(parent->bpf.effective[type],
- lockdep_is_held(&cgroup_mutex));
- }
+ if ((flags & BPF_F_ALLOW_OVERRIDE) && (flags & BPF_F_ALLOW_MULTI))
+ /* invalid combination */
+ return -EINVAL;
- if (prog && effective && !overridable)
- /* if parent has non-overridable prog attached, disallow
- * attaching new programs to descendent cgroup
+ if (!hierarchy_allows_attach(cgrp, type, flags))
+ return -EPERM;
+
+ if (!list_empty(progs) && cgrp->bpf.flags[type] != flags)
+ /* Disallow attaching non-overridable on top
+ * of existing overridable in this cgroup.
+ * Disallow attaching multi-prog if overridable or none
*/
return -EPERM;
- if (prog && effective && overridable != new_overridable)
- /* if parent has overridable prog attached, only
- * allow overridable programs in descendent cgroup
- */
- return -EPERM;
+ if (prog_list_length(progs) >= BPF_CGROUP_MAX_PROGS)
+ return -E2BIG;
- old_prog = cgrp->bpf.prog[type];
+ if (flags & BPF_F_ALLOW_MULTI) {
+ list_for_each_entry(pl, progs, node)
+ if (pl->prog == prog)
+ /* disallow attaching the same prog twice */
+ return -EINVAL;
- if (prog) {
- overridable = new_overridable;
- effective = prog;
- if (old_prog &&
- cgrp->bpf.disallow_override[type] == new_overridable)
- /* disallow attaching non-overridable on top
- * of existing overridable in this cgroup
- * and vice versa
- */
- return -EPERM;
- }
-
- if (!prog && !old_prog)
- /* report error when trying to detach and nothing is attached */
- return -ENOENT;
-
- cgrp->bpf.prog[type] = prog;
-
- css_for_each_descendant_pre(pos, &cgrp->self) {
- struct cgroup *desc = container_of(pos, struct cgroup, self);
-
- /* skip the subtree if the descendant has its own program */
- if (desc->bpf.prog[type] && desc != cgrp) {
- pos = css_rightmost_descendant(pos);
+ pl = kmalloc(sizeof(*pl), GFP_KERNEL);
+ if (!pl)
+ return -ENOMEM;
+ pl_was_allocated = true;
+ pl->prog = prog;
+ list_add_tail(&pl->node, progs);
+ } else {
+ if (list_empty(progs)) {
+ pl = kmalloc(sizeof(*pl), GFP_KERNEL);
+ if (!pl)
+ return -ENOMEM;
+ pl_was_allocated = true;
+ list_add_tail(&pl->node, progs);
} else {
- rcu_assign_pointer(desc->bpf.effective[type],
- effective);
- desc->bpf.disallow_override[type] = !overridable;
+ pl = list_first_entry(progs, typeof(*pl), node);
+ old_prog = pl->prog;
+ pl_was_allocated = false;
}
+ pl->prog = prog;
}
- if (prog)
- static_branch_inc(&cgroup_bpf_enabled_key);
+ old_flags = cgrp->bpf.flags[type];
+ cgrp->bpf.flags[type] = flags;
+ /* allocate and recompute effective prog arrays */
+ css_for_each_descendant_pre(css, &cgrp->self) {
+ struct cgroup *desc = container_of(css, struct cgroup, self);
+
+ err = compute_effective_progs(desc, type, &desc->bpf.inactive);
+ if (err)
+ goto cleanup;
+ }
+
+ /* all allocations were successful. Activate all prog arrays */
+ css_for_each_descendant_pre(css, &cgrp->self) {
+ struct cgroup *desc = container_of(css, struct cgroup, self);
+
+ activate_effective_progs(desc, type, desc->bpf.inactive);
+ desc->bpf.inactive = NULL;
+ }
+
+ static_branch_inc(&cgroup_bpf_enabled_key);
if (old_prog) {
bpf_prog_put(old_prog);
static_branch_dec(&cgroup_bpf_enabled_key);
}
return 0;
+
+cleanup:
+ /* oom while computing effective. Free all computed effective arrays
+ * since they were not activated
+ */
+ css_for_each_descendant_pre(css, &cgrp->self) {
+ struct cgroup *desc = container_of(css, struct cgroup, self);
+
+ bpf_prog_array_free(desc->bpf.inactive);
+ desc->bpf.inactive = NULL;
+ }
+
+ /* and cleanup the prog list */
+ pl->prog = old_prog;
+ if (pl_was_allocated) {
+ list_del(&pl->node);
+ kfree(pl);
+ }
+ return err;
+}
+
+/**
+ * __cgroup_bpf_detach() - Detach the program from a cgroup, and
+ * propagate the change to descendants
+ * @cgrp: The cgroup which descendants to traverse
+ * @prog: A program to detach or NULL
+ * @type: Type of detach operation
+ *
+ * Must be called with cgroup_mutex held.
+ */
+int __cgroup_bpf_detach(struct cgroup *cgrp, struct bpf_prog *prog,
+ enum bpf_attach_type type, u32 unused_flags)
+{
+ struct list_head *progs = &cgrp->bpf.progs[type];
+ u32 flags = cgrp->bpf.flags[type];
+ struct bpf_prog *old_prog = NULL;
+ struct cgroup_subsys_state *css;
+ struct bpf_prog_list *pl;
+ int err;
+
+ if (flags & BPF_F_ALLOW_MULTI) {
+ if (!prog)
+ /* to detach MULTI prog the user has to specify valid FD
+ * of the program to be detached
+ */
+ return -EINVAL;
+ } else {
+ if (list_empty(progs))
+ /* report error when trying to detach and nothing is attached */
+ return -ENOENT;
+ }
+
+ if (flags & BPF_F_ALLOW_MULTI) {
+ /* find the prog and detach it */
+ list_for_each_entry(pl, progs, node) {
+ if (pl->prog != prog)
+ continue;
+ old_prog = prog;
+ /* mark it deleted, so it's ignored while
+ * recomputing effective
+ */
+ pl->prog = NULL;
+ break;
+ }
+ if (!old_prog)
+ return -ENOENT;
+ } else {
+ /* to maintain backward compatibility NONE and OVERRIDE cgroups
+ * allow detaching with invalid FD (prog==NULL)
+ */
+ pl = list_first_entry(progs, typeof(*pl), node);
+ old_prog = pl->prog;
+ pl->prog = NULL;
+ }
+
+ /* allocate and recompute effective prog arrays */
+ css_for_each_descendant_pre(css, &cgrp->self) {
+ struct cgroup *desc = container_of(css, struct cgroup, self);
+
+ err = compute_effective_progs(desc, type, &desc->bpf.inactive);
+ if (err)
+ goto cleanup;
+ }
+
+ /* all allocations were successful. Activate all prog arrays */
+ css_for_each_descendant_pre(css, &cgrp->self) {
+ struct cgroup *desc = container_of(css, struct cgroup, self);
+
+ activate_effective_progs(desc, type, desc->bpf.inactive);
+ desc->bpf.inactive = NULL;
+ }
+
+ /* now can actually delete it from this cgroup list */
+ list_del(&pl->node);
+ kfree(pl);
+ if (list_empty(progs))
+ /* last program was detached, reset flags to zero */
+ cgrp->bpf.flags[type] = 0;
+
+ bpf_prog_put(old_prog);
+ static_branch_dec(&cgroup_bpf_enabled_key);
+ return 0;
+
+cleanup:
+ /* oom while computing effective. Free all computed effective arrays
+ * since they were not activated
+ */
+ css_for_each_descendant_pre(css, &cgrp->self) {
+ struct cgroup *desc = container_of(css, struct cgroup, self);
+
+ bpf_prog_array_free(desc->bpf.inactive);
+ desc->bpf.inactive = NULL;
+ }
+
+ /* and restore back old_prog */
+ pl->prog = old_prog;
+ return err;
}
/**
@@ -171,35 +403,25 @@ int __cgroup_bpf_run_filter(struct sock *sk,
struct sk_buff *skb,
enum bpf_attach_type type)
{
- struct bpf_prog *prog;
+ unsigned int offset = skb->data - skb_network_header(skb);
+ struct sock *save_sk;
struct cgroup *cgrp;
- int ret = 0;
+ int ret;
if (!sk || !sk_fullsock(sk))
return 0;
- if (sk->sk_family != AF_INET &&
- sk->sk_family != AF_INET6)
+ if (sk->sk_family != AF_INET && sk->sk_family != AF_INET6)
return 0;
cgrp = sock_cgroup_ptr(&sk->sk_cgrp_data);
-
- rcu_read_lock();
-
- prog = rcu_dereference(cgrp->bpf.effective[type]);
- if (prog) {
- unsigned int offset = skb->data - skb_network_header(skb);
- struct sock *save_sk = skb->sk;
-
- skb->sk = sk;
- __skb_push(skb, offset);
- ret = bpf_prog_run_save_cb(prog, skb) == 1 ? 0 : -EPERM;
- __skb_pull(skb, offset);
- skb->sk = save_sk;
- }
-
- rcu_read_unlock();
-
- return ret;
+ save_sk = skb->sk;
+ skb->sk = sk;
+ __skb_push(skb, offset);
+ ret = BPF_PROG_RUN_ARRAY(cgrp->bpf.effective[type], skb,
+ bpf_prog_run_save_cb);
+ __skb_pull(skb, offset);
+ skb->sk = save_sk;
+ return ret == 1 ? 0 : -EPERM;
}
EXPORT_SYMBOL(__cgroup_bpf_run_filter);
diff --git a/kernel/bpf/core.c b/kernel/bpf/core.c
index b373c78..8def8ae 100644
--- a/kernel/bpf/core.c
+++ b/kernel/bpf/core.c
@@ -1069,6 +1069,118 @@ struct bpf_prog *bpf_prog_select_runtime(struct bpf_prog *fp, int *err)
}
EXPORT_SYMBOL_GPL(bpf_prog_select_runtime);
+static unsigned int __bpf_prog_ret1(const struct sk_buff *ctx,
+ const struct bpf_insn *insn)
+{
+ return 1;
+}
+
+static struct bpf_prog_dummy {
+ struct bpf_prog prog;
+} dummy_bpf_prog = {
+ .prog = {
+ .bpf_func = __bpf_prog_ret1,
+ },
+};
+
+/* to avoid allocating empty bpf_prog_array for cgroups that
+ * don't have bpf program attached use one global 'empty_prog_array'
+ * It will not be modified the caller of bpf_prog_array_alloc()
+ * (since caller requested prog_cnt == 0)
+ * that pointer should be 'freed' by bpf_prog_array_free()
+ */
+static struct {
+ struct bpf_prog_array hdr;
+ struct bpf_prog *null_prog;
+} empty_prog_array = {
+ .null_prog = NULL,
+};
+
+struct bpf_prog_array __rcu *bpf_prog_array_alloc(u32 prog_cnt, gfp_t flags)
+{
+ if (prog_cnt)
+ return kzalloc(sizeof(struct bpf_prog_array) +
+ sizeof(struct bpf_prog *) * (prog_cnt + 1),
+ flags);
+
+ return &empty_prog_array.hdr;
+}
+
+void bpf_prog_array_free(struct bpf_prog_array __rcu *progs)
+{
+ if (!progs ||
+ progs == (struct bpf_prog_array __rcu *)&empty_prog_array.hdr)
+ return;
+ kfree_rcu(progs, rcu);
+}
+
+void bpf_prog_array_delete_safe(struct bpf_prog_array __rcu *progs,
+ struct bpf_prog *old_prog)
+{
+ struct bpf_prog **prog = progs->progs;
+
+ for (; *prog; prog++)
+ if (*prog == old_prog) {
+ WRITE_ONCE(*prog, &dummy_bpf_prog.prog);
+ break;
+ }
+}
+
+int bpf_prog_array_copy(struct bpf_prog_array __rcu *old_array,
+ struct bpf_prog *exclude_prog,
+ struct bpf_prog *include_prog,
+ struct bpf_prog_array **new_array)
+{
+ int new_prog_cnt, carry_prog_cnt = 0;
+ struct bpf_prog **existing_prog;
+ struct bpf_prog_array *array;
+ int new_prog_idx = 0;
+
+ /* Figure out how many existing progs we need to carry over to
+ * the new array.
+ */
+ if (old_array) {
+ existing_prog = old_array->progs;
+ for (; *existing_prog; existing_prog++) {
+ if (*existing_prog != exclude_prog &&
+ *existing_prog != &dummy_bpf_prog.prog)
+ carry_prog_cnt++;
+ if (*existing_prog == include_prog)
+ return -EEXIST;
+ }
+ }
+
+ /* How many progs (not NULL) will be in the new array? */
+ new_prog_cnt = carry_prog_cnt;
+ if (include_prog)
+ new_prog_cnt += 1;
+
+ /* Do we have any prog (not NULL) in the new array? */
+ if (!new_prog_cnt) {
+ *new_array = NULL;
+ return 0;
+ }
+
+ /* +1 as the end of prog_array is marked with NULL */
+ array = bpf_prog_array_alloc(new_prog_cnt + 1, GFP_KERNEL);
+ if (!array)
+ return -ENOMEM;
+
+ /* Fill in the new prog array */
+ if (carry_prog_cnt) {
+ existing_prog = old_array->progs;
+ for (; *existing_prog; existing_prog++)
+ if (*existing_prog != exclude_prog &&
+ *existing_prog != &dummy_bpf_prog.prog)
+ array->progs[new_prog_idx++] = *existing_prog;
+ }
+ if (include_prog)
+ array->progs[new_prog_idx++] = include_prog;
+ array->progs[new_prog_idx] = NULL;
+ *new_array = array;
+ return 0;
+}
+
static void bpf_prog_free_deferred(struct work_struct *work)
{
struct bpf_prog_aux *aux;
diff --git a/kernel/bpf/syscall.c b/kernel/bpf/syscall.c
index 85ea598..42af9fa 100644
--- a/kernel/bpf/syscall.c
+++ b/kernel/bpf/syscall.c
@@ -894,6 +894,9 @@ static int bpf_obj_get(const union bpf_attr *attr)
#define BPF_PROG_ATTACH_LAST_FIELD attach_flags
+#define BPF_F_ATTACH_MASK \
+ (BPF_F_ALLOW_OVERRIDE | BPF_F_ALLOW_MULTI)
+
static int bpf_prog_attach(const union bpf_attr *attr)
{
struct bpf_prog *prog;
@@ -906,7 +909,7 @@ static int bpf_prog_attach(const union bpf_attr *attr)
if (CHECK_ATTR(BPF_PROG_ATTACH))
return -EINVAL;
- if (attr->attach_flags & ~BPF_F_ALLOW_OVERRIDE)
+ if (attr->attach_flags & ~BPF_F_ATTACH_MASK)
return -EINVAL;
switch (attr->attach_type) {
@@ -923,8 +926,8 @@ static int bpf_prog_attach(const union bpf_attr *attr)
return PTR_ERR(cgrp);
}
- ret = cgroup_bpf_update(cgrp, prog, attr->attach_type,
- attr->attach_flags & BPF_F_ALLOW_OVERRIDE);
+ ret = cgroup_bpf_attach(cgrp, prog, attr->attach_type,
+ attr->attach_flags);
if (ret)
bpf_prog_put(prog);
cgroup_put(cgrp);
@@ -941,6 +944,8 @@ static int bpf_prog_attach(const union bpf_attr *attr)
static int bpf_prog_detach(const union bpf_attr *attr)
{
+ enum bpf_prog_type ptype;
+ struct bpf_prog *prog;
struct cgroup *cgrp;
int ret;
@@ -953,18 +958,25 @@ static int bpf_prog_detach(const union bpf_attr *attr)
switch (attr->attach_type) {
case BPF_CGROUP_INET_INGRESS:
case BPF_CGROUP_INET_EGRESS:
- cgrp = cgroup_get_from_fd(attr->target_fd);
- if (IS_ERR(cgrp))
- return PTR_ERR(cgrp);
-
- ret = cgroup_bpf_update(cgrp, NULL, attr->attach_type, false);
- cgroup_put(cgrp);
+ ptype = BPF_PROG_TYPE_CGROUP_SKB;
break;
default:
return -EINVAL;
}
+ cgrp = cgroup_get_from_fd(attr->target_fd);
+ if (IS_ERR(cgrp))
+ return PTR_ERR(cgrp);
+
+ prog = bpf_prog_get_type(attr->attach_bpf_fd, ptype);
+ if (IS_ERR(prog))
+ prog = NULL;
+
+ ret = cgroup_bpf_detach(cgrp, prog, attr->attach_type, 0);
+ if (prog)
+ bpf_prog_put(prog);
+ cgroup_put(cgrp);
return ret;
}
#endif /* CONFIG_CGROUP_BPF */
diff --git a/kernel/cgroup.c b/kernel/cgroup.c
index 1953033..0ded03f 100644
--- a/kernel/cgroup.c
+++ b/kernel/cgroup.c
@@ -2020,6 +2020,9 @@ static int cgroup_setup_root(struct cgroup_root *root, u16 ss_mask)
if (ret)
goto destroy_root;
+ ret = cgroup_bpf_inherit(root_cgrp);
+ WARN_ON_ONCE(ret);
+
trace_cgroup_setup_root(root);
/*
@@ -5400,6 +5403,9 @@ static struct cgroup *cgroup_create(struct cgroup *parent)
cgrp->self.parent = &parent->self;
cgrp->root = root;
cgrp->level = level;
+ ret = cgroup_bpf_inherit(cgrp);
+ if (ret)
+ goto out_idr_free;
for (tcgrp = cgrp; tcgrp; tcgrp = cgroup_parent(tcgrp))
cgrp->ancestor_ids[tcgrp->level] = tcgrp->id;
@@ -5436,9 +5442,6 @@ static struct cgroup *cgroup_create(struct cgroup *parent)
goto out_idr_free;
}
- if (parent)
- cgroup_bpf_inherit(cgrp, parent);
-
cgroup_propagate_control(cgrp);
return cgrp;
@@ -6657,14 +6660,23 @@ static __init int cgroup_namespaces_init(void)
subsys_initcall(cgroup_namespaces_init);
#ifdef CONFIG_CGROUP_BPF
-int cgroup_bpf_update(struct cgroup *cgrp, struct bpf_prog *prog,
- enum bpf_attach_type type, bool overridable)
+int cgroup_bpf_attach(struct cgroup *cgrp, struct bpf_prog *prog,
+ enum bpf_attach_type type, u32 flags)
{
- struct cgroup *parent = cgroup_parent(cgrp);
int ret;
mutex_lock(&cgroup_mutex);
- ret = __cgroup_bpf_update(cgrp, parent, prog, type, overridable);
+ ret = __cgroup_bpf_attach(cgrp, prog, type, flags);
+ mutex_unlock(&cgroup_mutex);
+ return ret;
+}
+int cgroup_bpf_detach(struct cgroup *cgrp, struct bpf_prog *prog,
+ enum bpf_attach_type type, u32 flags)
+{
+ int ret;
+
+ mutex_lock(&cgroup_mutex);
+ ret = __cgroup_bpf_detach(cgrp, prog, type, flags);
mutex_unlock(&cgroup_mutex);
return ret;
}
diff --git a/kernel/cgroup_pids.c b/kernel/cgroup_pids.c
index a57242e..b8b898e 100644
--- a/kernel/cgroup_pids.c
+++ b/kernel/cgroup_pids.c
@@ -48,7 +48,7 @@ struct pids_cgroup {
* %PIDS_MAX = (%PID_MAX_LIMIT + 1).
*/
atomic64_t counter;
- int64_t limit;
+ atomic64_t limit;
/* Handle for "pids.events" */
struct cgroup_file events_file;
@@ -76,8 +76,8 @@ pids_css_alloc(struct cgroup_subsys_state *parent)
if (!pids)
return ERR_PTR(-ENOMEM);
- pids->limit = PIDS_MAX;
atomic64_set(&pids->counter, 0);
+ atomic64_set(&pids->limit, PIDS_MAX);
atomic64_set(&pids->events_limit, 0);
return &pids->css;
}
@@ -149,13 +149,14 @@ static int pids_try_charge(struct pids_cgroup *pids, int num)
for (p = pids; parent_pids(p); p = parent_pids(p)) {
int64_t new = atomic64_add_return(num, &p->counter);
+ int64_t limit = atomic64_read(&p->limit);
/*
* Since new is capped to the maximum number of pid_t, if
* p->limit is %PIDS_MAX then we know that this test will never
* fail.
*/
- if (new > p->limit)
+ if (new > limit)
goto revert;
}
@@ -280,7 +281,7 @@ static ssize_t pids_max_write(struct kernfs_open_file *of, char *buf,
* Limit updates don't need to be mutex'd, since it isn't
* critical that any racing fork()s follow the new limit.
*/
- pids->limit = limit;
+ atomic64_set(&pids->limit, limit);
return nbytes;
}
@@ -288,7 +289,7 @@ static int pids_max_show(struct seq_file *sf, void *v)
{
struct cgroup_subsys_state *css = seq_css(sf);
struct pids_cgroup *pids = css_pids(css);
- int64_t limit = pids->limit;
+ int64_t limit = atomic64_read(&pids->limit);
if (limit >= PIDS_MAX)
seq_printf(sf, "%s\n", PIDS_MAX_STR);
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 1aa14fb..22c1190a 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -7877,11 +7877,9 @@ void perf_trace_run_bpf_submit(void *raw_data, int size, int rctx,
struct pt_regs *regs, struct hlist_head *head,
struct task_struct *task)
{
- struct bpf_prog *prog = call->prog;
-
- if (prog) {
+ if (bpf_prog_array_valid(call)) {
*(struct pt_regs **)raw_data = regs;
- if (!trace_call_bpf(prog, raw_data) || hlist_empty(head)) {
+ if (!trace_call_bpf(call, raw_data) || hlist_empty(head)) {
perf_swevent_put_recursion_context(rctx);
return;
}
@@ -8067,6 +8065,7 @@ static int perf_event_set_bpf_prog(struct perf_event *event, u32 prog_fd)
{
bool is_kprobe, is_tracepoint;
struct bpf_prog *prog;
+ int ret;
if (event->attr.type == PERF_TYPE_HARDWARE ||
event->attr.type == PERF_TYPE_SOFTWARE)
@@ -8075,9 +8074,6 @@ static int perf_event_set_bpf_prog(struct perf_event *event, u32 prog_fd)
if (event->attr.type != PERF_TYPE_TRACEPOINT)
return -EINVAL;
- if (event->tp_event->prog)
- return -EEXIST;
-
is_kprobe = event->tp_event->flags & TRACE_EVENT_FL_UKPROBE;
is_tracepoint = event->tp_event->flags & TRACE_EVENT_FL_TRACEPOINT;
if (!is_kprobe && !is_tracepoint)
@@ -8103,26 +8099,20 @@ static int perf_event_set_bpf_prog(struct perf_event *event, u32 prog_fd)
return -EACCES;
}
}
- event->tp_event->prog = prog;
- event->tp_event->bpf_prog_owner = event;
- return 0;
+ ret = perf_event_attach_bpf_prog(event, prog);
+ if (ret)
+ bpf_prog_put(prog);
+ return ret;
}
static void perf_event_free_bpf_prog(struct perf_event *event)
{
- struct bpf_prog *prog;
-
- perf_event_free_bpf_handler(event);
-
- if (!event->tp_event)
+ if (event->attr.type != PERF_TYPE_TRACEPOINT) {
+ perf_event_free_bpf_handler(event);
return;
-
- prog = event->tp_event->prog;
- if (prog && event->tp_event->bpf_prog_owner == event) {
- event->tp_event->prog = NULL;
- bpf_prog_put(prog);
}
+ perf_event_detach_bpf_prog(event);
}
#else
diff --git a/kernel/module.c b/kernel/module.c
index ee3c9f1..5eb3bf7 100644
--- a/kernel/module.c
+++ b/kernel/module.c
@@ -995,6 +995,8 @@ SYSCALL_DEFINE2(delete_module, const char __user *, name_user,
strlcpy(last_unloaded_module, mod->name, sizeof(last_unloaded_module));
free_module(mod);
+ /* someone could wait for the module in add_unformed_module() */
+ wake_up_all(&module_wq);
return 0;
out:
mutex_unlock(&module_mutex);
diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
index 40e7d10..dc669e3 100755
--- a/kernel/sched/fair.c
+++ b/kernel/sched/fair.c
@@ -4748,20 +4748,28 @@ static enum hrtimer_restart sched_cfs_period_timer(struct hrtimer *timer)
if (++count > 3) {
u64 new, old = ktime_to_ns(cfs_b->period);
- new = (old * 147) / 128; /* ~115% */
- new = min(new, max_cfs_quota_period);
+ /*
+ * Grow period by a factor of 2 to avoid losing precision.
+ * Precision loss in the quota/period ratio can cause __cfs_schedulable
+ * to fail.
+ */
+ new = old * 2;
+ if (new < max_cfs_quota_period) {
+ cfs_b->period = ns_to_ktime(new);
+ cfs_b->quota *= 2;
- cfs_b->period = ns_to_ktime(new);
-
- /* since max is 1s, this is limited to 1e9^2, which fits in u64 */
- cfs_b->quota *= new;
- cfs_b->quota = div64_u64(cfs_b->quota, old);
-
- pr_warn_ratelimited(
- "cfs_period_timer[cpu%d]: period too short, scaling up (new cfs_period_us %lld, cfs_quota_us = %lld)\n",
- smp_processor_id(),
- div_u64(new, NSEC_PER_USEC),
- div_u64(cfs_b->quota, NSEC_PER_USEC));
+ pr_warn_ratelimited(
+ "cfs_period_timer[cpu%d]: period too short, scaling up (new cfs_period_us = %lld, cfs_quota_us = %lld)\n",
+ smp_processor_id(),
+ div_u64(new, NSEC_PER_USEC),
+ div_u64(cfs_b->quota, NSEC_PER_USEC));
+ } else {
+ pr_warn_ratelimited(
+ "cfs_period_timer[cpu%d]: period too short, but cannot scale up without losing precision (cfs_period_us = %lld, cfs_quota_us = %lld)\n",
+ smp_processor_id(),
+ div_u64(old, NSEC_PER_USEC),
+ div_u64(cfs_b->quota, NSEC_PER_USEC));
+ }
/* reset count so we don't come right back in here */
count = 0;
diff --git a/kernel/sysctl.c b/kernel/sysctl.c
index 0dc8c07..f3a22c9 100644
--- a/kernel/sysctl.c
+++ b/kernel/sysctl.c
@@ -1573,7 +1573,7 @@ static struct ctl_table vm_table[] = {
.procname = "drop_caches",
.data = &sysctl_drop_caches,
.maxlen = sizeof(int),
- .mode = 0644,
+ .mode = 0200,
.proc_handler = drop_caches_sysctl_handler,
.extra1 = &one,
.extra2 = &four,
diff --git a/kernel/time/hrtimer.c b/kernel/time/hrtimer.c
old mode 100644
new mode 100755
index d471752..049ed34
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -844,7 +844,8 @@ static int enqueue_hrtimer(struct hrtimer *timer,
base->cpu_base->active_bases |= 1 << base->index;
- timer->state |= HRTIMER_STATE_ENQUEUED;
+ /* Pairs with the lockless read in hrtimer_is_queued() */
+ WRITE_ONCE(timer->state, HRTIMER_STATE_ENQUEUED);
return timerqueue_add(&base->active, &timer->node);
}
@@ -864,9 +865,12 @@ static void __remove_hrtimer(struct hrtimer *timer,
u8 newstate, int reprogram)
{
struct hrtimer_cpu_base *cpu_base = base->cpu_base;
+ unsigned int state = timer->state;
- if (!(timer->state & HRTIMER_STATE_ENQUEUED))
+ if (!(state & HRTIMER_STATE_ENQUEUED))
goto out;
+ /* Pairs with the lockless read in hrtimer_is_queued() */
+ WRITE_ONCE(timer->state, newstate);
if (!timerqueue_del(&base->active, &timer->node))
cpu_base->active_bases &= ~(1 << base->index);
@@ -898,8 +902,9 @@ static void __remove_hrtimer(struct hrtimer *timer,
static inline int
remove_hrtimer(struct hrtimer *timer, struct hrtimer_clock_base *base, bool restart)
{
- if (hrtimer_is_queued(timer)) {
- u8 state = timer->state;
+ u8 state = timer->state;
+
+ if (state & HRTIMER_STATE_ENQUEUED) {
int reprogram;
/*
diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c
index c7aab15..afdb7e7 100644
--- a/kernel/trace/bpf_trace.c
+++ b/kernel/trace/bpf_trace.c
@@ -17,7 +17,7 @@
/**
* trace_call_bpf - invoke BPF program
- * @prog: BPF program
+ * @call: tracepoint event
* @ctx: opaque context pointer
*
* kprobe handlers execute BPF programs via this helper.
@@ -29,7 +29,7 @@
* 1 - store kprobe event into ring buffer
* Other values are reserved and currently alias to 1
*/
-unsigned int trace_call_bpf(struct bpf_prog *prog, void *ctx)
+unsigned int trace_call_bpf(struct trace_event_call *call, void *ctx)
{
unsigned int ret;
@@ -49,9 +49,22 @@ unsigned int trace_call_bpf(struct bpf_prog *prog, void *ctx)
goto out;
}
- rcu_read_lock();
- ret = BPF_PROG_RUN(prog, ctx);
- rcu_read_unlock();
+ /*
+ * Instead of moving rcu_read_lock/rcu_dereference/rcu_read_unlock
+ * to all call sites, we did a bpf_prog_array_valid() there to check
+ * whether call->prog_array is empty or not, which is
+ * a heurisitc to speed up execution.
+ *
+ * If bpf_prog_array_valid() fetched prog_array was
+ * non-NULL, we go into trace_call_bpf() and do the actual
+ * proper rcu_dereference() under RCU lock.
+ * If it turns out that prog_array is NULL then, we bail out.
+ * For the opposite, if the bpf_prog_array_valid() fetched pointer
+ * was NULL, you'll skip the prog_array with the risk of missing
+ * out of events when it was updated in between this and the
+ * rcu_dereference() which is accepted risk.
+ */
+ ret = BPF_PROG_RUN_ARRAY_CHECK(call->prog_array, ctx, BPF_PROG_RUN);
out:
__this_cpu_dec(bpf_prog_active);
@@ -663,6 +676,65 @@ static const struct bpf_verifier_ops perf_event_prog_ops = {
.convert_ctx_access = pe_prog_convert_ctx_access,
};
+static DEFINE_MUTEX(bpf_event_mutex);
+
+int perf_event_attach_bpf_prog(struct perf_event *event,
+ struct bpf_prog *prog)
+{
+ struct bpf_prog_array __rcu *old_array;
+ struct bpf_prog_array *new_array;
+ int ret = -EEXIST;
+
+ mutex_lock(&bpf_event_mutex);
+
+ if (event->prog)
+ goto out;
+
+ old_array = rcu_dereference_protected(event->tp_event->prog_array,
+ lockdep_is_held(&bpf_event_mutex));
+ ret = bpf_prog_array_copy(old_array, NULL, prog, &new_array);
+ if (ret < 0)
+ goto out;
+
+ /* set the new array to event->tp_event and set event->prog */
+ event->prog = prog;
+ rcu_assign_pointer(event->tp_event->prog_array, new_array);
+ bpf_prog_array_free(old_array);
+
+out:
+ mutex_unlock(&bpf_event_mutex);
+ return ret;
+}
+
+void perf_event_detach_bpf_prog(struct perf_event *event)
+{
+ struct bpf_prog_array __rcu *old_array;
+ struct bpf_prog_array *new_array;
+ int ret;
+
+ mutex_lock(&bpf_event_mutex);
+
+ if (!event->prog)
+ goto out;
+
+ old_array = rcu_dereference_protected(event->tp_event->prog_array,
+ lockdep_is_held(&bpf_event_mutex));
+
+ ret = bpf_prog_array_copy(old_array, event->prog, NULL, &new_array);
+ if (ret < 0) {
+ bpf_prog_array_delete_safe(old_array, event->prog);
+ } else {
+ rcu_assign_pointer(event->tp_event->prog_array, new_array);
+ bpf_prog_array_free(old_array);
+ }
+
+ bpf_prog_put(event->prog);
+ event->prog = NULL;
+
+out:
+ mutex_unlock(&bpf_event_mutex);
+}
+
static struct bpf_prog_type_list perf_event_tl = {
.ops = &perf_event_prog_ops,
.type = BPF_PROG_TYPE_PERF_EVENT,
diff --git a/kernel/trace/trace_kprobe.c b/kernel/trace/trace_kprobe.c
index 3b4cd44..c49f046 100644
--- a/kernel/trace/trace_kprobe.c
+++ b/kernel/trace/trace_kprobe.c
@@ -1142,13 +1142,12 @@ static void
kprobe_perf_func(struct trace_kprobe *tk, struct pt_regs *regs)
{
struct trace_event_call *call = &tk->tp.call;
- struct bpf_prog *prog = call->prog;
struct kprobe_trace_entry_head *entry;
struct hlist_head *head;
int size, __size, dsize;
int rctx;
- if (prog && !trace_call_bpf(prog, regs))
+ if (bpf_prog_array_valid(call) && !trace_call_bpf(call, regs))
return;
head = this_cpu_ptr(call->perf_events);
@@ -1178,13 +1177,12 @@ kretprobe_perf_func(struct trace_kprobe *tk, struct kretprobe_instance *ri,
struct pt_regs *regs)
{
struct trace_event_call *call = &tk->tp.call;
- struct bpf_prog *prog = call->prog;
struct kretprobe_trace_entry_head *entry;
struct hlist_head *head;
int size, __size, dsize;
int rctx;
- if (prog && !trace_call_bpf(prog, regs))
+ if (bpf_prog_array_valid(call) && !trace_call_bpf(call, regs))
return;
head = this_cpu_ptr(call->perf_events);
diff --git a/kernel/trace/trace_syscalls.c b/kernel/trace/trace_syscalls.c
index fa5fe21..7e6c2e4 100644
--- a/kernel/trace/trace_syscalls.c
+++ b/kernel/trace/trace_syscalls.c
@@ -564,6 +564,7 @@ static void perf_syscall_enter(void *ignore, struct pt_regs *regs, long id)
struct syscall_metadata *sys_data;
struct syscall_trace_enter *rec;
struct hlist_head *head;
+ bool valid_prog_array;
int syscall_nr;
int rctx;
int size;
@@ -579,7 +580,8 @@ static void perf_syscall_enter(void *ignore, struct pt_regs *regs, long id)
return;
head = this_cpu_ptr(sys_data->enter_event->perf_events);
- if (hlist_empty(head))
+ valid_prog_array = bpf_prog_array_valid(sys_data->enter_event);
+ if (!valid_prog_array && hlist_empty(head))
return;
/* get the size after alignment with the u32 buffer size field */
@@ -638,6 +640,7 @@ static void perf_syscall_exit(void *ignore, struct pt_regs *regs, long ret)
struct syscall_metadata *sys_data;
struct syscall_trace_exit *rec;
struct hlist_head *head;
+ bool valid_prog_array;
int syscall_nr;
int rctx;
int size;
@@ -653,7 +656,8 @@ static void perf_syscall_exit(void *ignore, struct pt_regs *regs, long ret)
return;
head = this_cpu_ptr(sys_data->exit_event->perf_events);
- if (hlist_empty(head))
+ valid_prog_array = bpf_prog_array_valid(sys_data->exit_event);
+ if (!valid_prog_array && hlist_empty(head))
return;
/* We can probably do that at build time */
diff --git a/kernel/trace/trace_uprobe.c b/kernel/trace/trace_uprobe.c
index 255a824..3fd4ec0 100644
--- a/kernel/trace/trace_uprobe.c
+++ b/kernel/trace/trace_uprobe.c
@@ -1119,13 +1119,12 @@ static void __uprobe_perf_func(struct trace_uprobe *tu,
{
struct trace_event_call *call = &tu->tp.call;
struct uprobe_trace_entry_head *entry;
- struct bpf_prog *prog = call->prog;
struct hlist_head *head;
void *data;
int size, esize;
int rctx;
- if (prog && !trace_call_bpf(prog, regs))
+ if (bpf_prog_array_valid(call) && !trace_call_bpf(call, regs))
return;
esize = SIZEOF_TRACE_ENTRY(is_ret_probe(tu));
diff --git a/kernel/workqueue.c b/kernel/workqueue.c
index e14c99521..6ffc72e 100644
--- a/kernel/workqueue.c
+++ b/kernel/workqueue.c
@@ -2376,8 +2376,14 @@ static int rescuer_thread(void *__rescuer)
*/
if (need_to_create_worker(pool)) {
spin_lock(&wq_mayday_lock);
- get_pwq(pwq);
- list_move_tail(&pwq->mayday_node, &wq->maydays);
+ /*
+ * Queue iff we aren't racing destruction
+ * and somebody else hasn't queued it already.
+ */
+ if (wq->rescuer && list_empty(&pwq->mayday_node)) {
+ get_pwq(pwq);
+ list_add_tail(&pwq->mayday_node, &wq->maydays);
+ }
spin_unlock(&wq_mayday_lock);
}
}
@@ -4077,9 +4083,29 @@ void destroy_workqueue(struct workqueue_struct *wq)
struct pool_workqueue *pwq;
int node;
+ /*
+ * Remove it from sysfs first so that sanity check failure doesn't
+ * lead to sysfs name conflicts.
+ */
+ workqueue_sysfs_unregister(wq);
+
/* drain it before proceeding with destruction */
drain_workqueue(wq);
+ /* kill rescuer, if sanity checks fail, leave it w/o rescuer */
+ if (wq->rescuer) {
+ struct worker *rescuer = wq->rescuer;
+
+ /* this prevents new queueing */
+ spin_lock_irq(&wq_mayday_lock);
+ wq->rescuer = NULL;
+ spin_unlock_irq(&wq_mayday_lock);
+
+ /* rescuer will empty maydays list before exiting */
+ kthread_stop(rescuer->task);
+ kfree(rescuer);
+ }
+
/* sanity checks */
mutex_lock(&wq->mutex);
for_each_pwq(pwq, wq) {
@@ -4109,11 +4135,6 @@ void destroy_workqueue(struct workqueue_struct *wq)
list_del_rcu(&wq->list);
mutex_unlock(&wq_pool_mutex);
- workqueue_sysfs_unregister(wq);
-
- if (wq->rescuer)
- kthread_stop(wq->rescuer->task);
-
if (!(wq->flags & WQ_UNBOUND)) {
/*
* The base ref is never dropped on per-cpu pwqs. Directly
@@ -4390,7 +4411,8 @@ static void show_pwq(struct pool_workqueue *pwq)
pr_info(" pwq %d:", pool->id);
pr_cont_pool_info(pool);
- pr_cont(" active=%d/%d%s\n", pwq->nr_active, pwq->max_active,
+ pr_cont(" active=%d/%d refcnt=%d%s\n",
+ pwq->nr_active, pwq->max_active, pwq->refcnt,
!list_empty(&pwq->mayday_node) ? " MAYDAY" : "");
hash_for_each(pool->busy_hash, bkt, worker, hentry) {
diff --git a/lib/dma-debug.c b/lib/dma-debug.c
index 8971370..4435bec 100644
--- a/lib/dma-debug.c
+++ b/lib/dma-debug.c
@@ -435,6 +435,7 @@ void debug_dma_dump_mappings(struct device *dev)
}
spin_unlock_irqrestore(&bucket->lock, flags);
+ cond_resched();
}
}
EXPORT_SYMBOL(debug_dma_dump_mappings);
diff --git a/lib/raid6/unroll.awk b/lib/raid6/unroll.awk
index c6aa036..0809805 100644
--- a/lib/raid6/unroll.awk
+++ b/lib/raid6/unroll.awk
@@ -13,7 +13,7 @@
for (i = 0; i < rep; ++i) {
tmp = $0
gsub(/\$\$/, i, tmp)
- gsub(/\$\#/, n, tmp)
+ gsub(/\$#/, n, tmp)
gsub(/\$\*/, "$", tmp)
print tmp
}
diff --git a/mm/shmem.c b/mm/shmem.c
index f4af71c..f42d873 100644
--- a/mm/shmem.c
+++ b/mm/shmem.c
@@ -2695,7 +2695,7 @@ static long shmem_fallocate(struct file *file, int mode, loff_t offset,
}
shmem_falloc.waitq = &shmem_falloc_waitq;
- shmem_falloc.start = unmap_start >> PAGE_SHIFT;
+ shmem_falloc.start = (u64)unmap_start >> PAGE_SHIFT;
shmem_falloc.next = (unmap_end + 1) >> PAGE_SHIFT;
spin_lock(&inode->i_lock);
inode->i_private = &shmem_falloc;
diff --git a/net/appletalk/aarp.c b/net/appletalk/aarp.c
index 8ad3ec2..b9e85a4 100644
--- a/net/appletalk/aarp.c
+++ b/net/appletalk/aarp.c
@@ -879,15 +879,24 @@ static struct notifier_block aarp_notifier = {
static unsigned char aarp_snap_id[] = { 0x00, 0x00, 0x00, 0x80, 0xF3 };
-void __init aarp_proto_init(void)
+int __init aarp_proto_init(void)
{
+ int rc;
+
aarp_dl = register_snap_client(aarp_snap_id, aarp_rcv);
- if (!aarp_dl)
+ if (!aarp_dl) {
printk(KERN_CRIT "Unable to register AARP with SNAP.\n");
+ return -ENOMEM;
+ }
setup_timer(&aarp_timer, aarp_expire_timeout, 0);
aarp_timer.expires = jiffies + sysctl_aarp_expiry_time;
add_timer(&aarp_timer);
- register_netdevice_notifier(&aarp_notifier);
+ rc = register_netdevice_notifier(&aarp_notifier);
+ if (rc) {
+ del_timer_sync(&aarp_timer);
+ unregister_snap_client(aarp_dl);
+ }
+ return rc;
}
/* Remove the AARP entries associated with a device. */
diff --git a/net/appletalk/ddp.c b/net/appletalk/ddp.c
index d74092c..93209c0 100644
--- a/net/appletalk/ddp.c
+++ b/net/appletalk/ddp.c
@@ -1911,9 +1911,6 @@ static unsigned char ddp_snap_id[] = { 0x08, 0x00, 0x07, 0x80, 0x9B };
EXPORT_SYMBOL(atrtr_get_dev);
EXPORT_SYMBOL(atalk_find_dev_addr);
-static const char atalk_err_snap[] __initconst =
- KERN_CRIT "Unable to register DDP with SNAP.\n";
-
/* Called by proto.c on kernel start up */
static int __init atalk_init(void)
{
@@ -1928,17 +1925,23 @@ static int __init atalk_init(void)
goto out_proto;
ddp_dl = register_snap_client(ddp_snap_id, atalk_rcv);
- if (!ddp_dl)
- printk(atalk_err_snap);
+ if (!ddp_dl) {
+ pr_crit("Unable to register DDP with SNAP.\n");
+ rc = -ENOMEM;
+ goto out_sock;
+ }
dev_add_pack(<alk_packet_type);
dev_add_pack(&ppptalk_packet_type);
rc = register_netdevice_notifier(&ddp_notifier);
if (rc)
- goto out_sock;
+ goto out_snap;
- aarp_proto_init();
+ rc = aarp_proto_init();
+ if (rc)
+ goto out_dev;
+
rc = atalk_proc_init();
if (rc)
goto out_aarp;
@@ -1952,11 +1955,13 @@ static int __init atalk_init(void)
atalk_proc_exit();
out_aarp:
aarp_cleanup_module();
+out_dev:
unregister_netdevice_notifier(&ddp_notifier);
-out_sock:
+out_snap:
dev_remove_pack(&ppptalk_packet_type);
dev_remove_pack(<alk_packet_type);
unregister_snap_client(ddp_dl);
+out_sock:
sock_unregister(PF_APPLETALK);
out_proto:
proto_unregister(&ddp_proto);
diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c
index 4bd72d2..a70b078 100644
--- a/net/bluetooth/hci_core.c
+++ b/net/bluetooth/hci_core.c
@@ -4180,7 +4180,14 @@ static void hci_rx_work(struct work_struct *work)
hci_send_to_sock(hdev, skb);
}
- if (hci_dev_test_flag(hdev, HCI_USER_CHANNEL)) {
+ /* If the device has been opened in HCI_USER_CHANNEL,
+ * the userspace has exclusive access to device.
+ * When device is HCI_INIT, we still need to process
+ * the data packets to the driver in order
+ * to complete its setup().
+ */
+ if (hci_dev_test_flag(hdev, HCI_USER_CHANNEL) &&
+ !test_bit(HCI_INIT, &hdev->flags)) {
kfree_skb(skb);
continue;
}
diff --git a/net/bluetooth/hci_request.c b/net/bluetooth/hci_request.c
index 1015d9c..4a89e12 100644
--- a/net/bluetooth/hci_request.c
+++ b/net/bluetooth/hci_request.c
@@ -1093,6 +1093,14 @@ static u8 create_instance_adv_data(struct hci_dev *hdev, u8 instance, u8 *ptr)
instance_flags = get_adv_instance_flags(hdev, instance);
+ /* If instance already has the flags set skip adding it once
+ * again.
+ */
+ if (adv_instance && eir_get_data(adv_instance->adv_data,
+ adv_instance->adv_data_len, EIR_FLAGS,
+ NULL))
+ goto skip_flags;
+
/* The Add Advertising command allows userspace to set both the general
* and limited discoverable flags.
*/
@@ -1125,6 +1133,7 @@ static u8 create_instance_adv_data(struct hci_dev *hdev, u8 instance, u8 *ptr)
}
}
+skip_flags:
if (adv_instance) {
memcpy(ptr, adv_instance->adv_data,
adv_instance->adv_data_len);
diff --git a/net/bridge/br_device.c b/net/bridge/br_device.c
index 04eea2f..bef3cca 100644
--- a/net/bridge/br_device.c
+++ b/net/bridge/br_device.c
@@ -211,6 +211,12 @@ static int br_set_mac_address(struct net_device *dev, void *p)
if (!is_valid_ether_addr(addr->sa_data))
return -EADDRNOTAVAIL;
+ /* dev_set_mac_addr() can be called by a master device on bridge's
+ * NETDEV_UNREGISTER, but since it's being destroyed do nothing
+ */
+ if (dev->reg_state != NETREG_REGISTERED)
+ return -EBUSY;
+
spin_lock_bh(&br->lock);
if (!ether_addr_equal(dev->dev_addr, addr->sa_data)) {
/* Mac address will be changed in br_stp_change_bridge_id(). */
diff --git a/net/bridge/br_netfilter_hooks.c b/net/bridge/br_netfilter_hooks.c
index 0c96773..62e045c 100644
--- a/net/bridge/br_netfilter_hooks.c
+++ b/net/bridge/br_netfilter_hooks.c
@@ -643,6 +643,9 @@ static unsigned int br_nf_forward_arp(void *priv,
nf_bridge_pull_encap_header(skb);
}
+ if (unlikely(!pskb_may_pull(skb, sizeof(struct arphdr))))
+ return NF_DROP;
+
if (arp_hdr(skb)->ar_pln != 4) {
if (IS_VLAN_ARP(skb))
nf_bridge_push_encap_header(skb);
diff --git a/net/bridge/netfilter/ebtables.c b/net/bridge/netfilter/ebtables.c
index 4a47918..56b7197 100644
--- a/net/bridge/netfilter/ebtables.c
+++ b/net/bridge/netfilter/ebtables.c
@@ -1894,7 +1894,7 @@ static int ebt_buf_count(struct ebt_entries_buf_state *state, unsigned int sz)
}
static int ebt_buf_add(struct ebt_entries_buf_state *state,
- void *data, unsigned int sz)
+ const void *data, unsigned int sz)
{
if (state->buf_kern_start == NULL)
goto count_only;
@@ -1928,7 +1928,7 @@ enum compat_mwt {
EBT_COMPAT_TARGET,
};
-static int compat_mtw_from_user(struct compat_ebt_entry_mwt *mwt,
+static int compat_mtw_from_user(const struct compat_ebt_entry_mwt *mwt,
enum compat_mwt compat_mwt,
struct ebt_entries_buf_state *state,
const unsigned char *base)
@@ -2004,22 +2004,23 @@ static int compat_mtw_from_user(struct compat_ebt_entry_mwt *mwt,
/* return size of all matches, watchers or target, including necessary
* alignment and padding.
*/
-static int ebt_size_mwt(struct compat_ebt_entry_mwt *match32,
+static int ebt_size_mwt(const struct compat_ebt_entry_mwt *match32,
unsigned int size_left, enum compat_mwt type,
struct ebt_entries_buf_state *state, const void *base)
{
+ const char *buf = (const char *)match32;
int growth = 0;
- char *buf;
if (size_left == 0)
return 0;
- buf = (char *) match32;
-
- while (size_left >= sizeof(*match32)) {
+ do {
struct ebt_entry_match *match_kern;
int ret;
+ if (size_left < sizeof(*match32))
+ return -EINVAL;
+
match_kern = (struct ebt_entry_match *) state->buf_kern_start;
if (match_kern) {
char *tmp;
@@ -2056,22 +2057,18 @@ static int ebt_size_mwt(struct compat_ebt_entry_mwt *match32,
if (match_kern)
match_kern->match_size = ret;
- /* rule should have no remaining data after target */
- if (type == EBT_COMPAT_TARGET && size_left)
- return -EINVAL;
-
match32 = (struct compat_ebt_entry_mwt *) buf;
- }
+ } while (size_left);
return growth;
}
/* called for all ebt_entry structures. */
-static int size_entry_mwt(struct ebt_entry *entry, const unsigned char *base,
+static int size_entry_mwt(const struct ebt_entry *entry, const unsigned char *base,
unsigned int *total,
struct ebt_entries_buf_state *state)
{
- unsigned int i, j, startoff, new_offset = 0;
+ unsigned int i, j, startoff, next_expected_off, new_offset = 0;
/* stores match/watchers/targets & offset of next struct ebt_entry: */
unsigned int offsets[4];
unsigned int *offsets_update = NULL;
@@ -2158,11 +2155,13 @@ static int size_entry_mwt(struct ebt_entry *entry, const unsigned char *base,
return ret;
}
- startoff = state->buf_user_offset - startoff;
-
- if (WARN_ON(*total < startoff))
+ next_expected_off = state->buf_user_offset - startoff;
+ if (next_expected_off != entry->next_offset)
return -EINVAL;
- *total -= startoff;
+
+ if (*total < entry->next_offset)
+ return -EINVAL;
+ *total -= entry->next_offset;
return 0;
}
diff --git a/net/core/dev.c b/net/core/dev.c
index 69ac821..19f36d6 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -6716,7 +6716,8 @@ static int __dev_set_mtu(struct net_device *dev, int new_mtu)
if (ops->ndo_change_mtu)
return ops->ndo_change_mtu(dev, new_mtu);
- dev->mtu = new_mtu;
+ /* Pairs with all the lockless reads of dev->mtu in the stack */
+ WRITE_ONCE(dev->mtu, new_mtu);
return 0;
}
diff --git a/net/core/sysctl_net_core.c b/net/core/sysctl_net_core.c
index a6fc827..b4318c1 100644
--- a/net/core/sysctl_net_core.c
+++ b/net/core/sysctl_net_core.c
@@ -255,6 +255,7 @@ static int proc_dointvec_minmax_bpf_enable(struct ctl_table *table, int write,
return ret;
}
+# ifdef CONFIG_HAVE_EBPF_JIT
static int
proc_dointvec_minmax_bpf_restricted(struct ctl_table *table, int write,
void __user *buffer, size_t *lenp,
@@ -265,6 +266,7 @@ proc_dointvec_minmax_bpf_restricted(struct ctl_table *table, int write,
return proc_dointvec_minmax(table, write, buffer, lenp, ppos);
}
+# endif /* CONFIG_HAVE_EBPF_JIT */
static int
proc_dolongvec_minmax_bpf_restricted(struct ctl_table *table, int write,
diff --git a/net/ipv4/devinet.c b/net/ipv4/devinet.c
index 9155cc5..e831ff5 100644
--- a/net/ipv4/devinet.c
+++ b/net/ipv4/devinet.c
@@ -1386,11 +1386,6 @@ static void inetdev_changename(struct net_device *dev, struct in_device *in_dev)
}
}
-static bool inetdev_valid_mtu(unsigned int mtu)
-{
- return mtu >= IPV4_MIN_MTU;
-}
-
static void inetdev_send_gratuitous_arp(struct net_device *dev,
struct in_device *in_dev)
diff --git a/net/ipv4/icmp.c b/net/ipv4/icmp.c
index 8a94cbc..5dab158 100644
--- a/net/ipv4/icmp.c
+++ b/net/ipv4/icmp.c
@@ -256,10 +256,11 @@ bool icmp_global_allow(void)
bool rc = false;
/* Check if token bucket is empty and cannot be refilled
- * without taking the spinlock.
+ * without taking the spinlock. The READ_ONCE() are paired
+ * with the following WRITE_ONCE() in this same function.
*/
- if (!icmp_global.credit) {
- delta = min_t(u32, now - icmp_global.stamp, HZ);
+ if (!READ_ONCE(icmp_global.credit)) {
+ delta = min_t(u32, now - READ_ONCE(icmp_global.stamp), HZ);
if (delta < HZ / 50)
return false;
}
@@ -269,14 +270,14 @@ bool icmp_global_allow(void)
if (delta >= HZ / 50) {
incr = sysctl_icmp_msgs_per_sec * delta / HZ ;
if (incr)
- icmp_global.stamp = now;
+ WRITE_ONCE(icmp_global.stamp, now);
}
credit = min_t(u32, icmp_global.credit + incr, sysctl_icmp_msgs_burst);
if (credit) {
credit--;
rc = true;
}
- icmp_global.credit = credit;
+ WRITE_ONCE(icmp_global.credit, credit);
spin_unlock(&icmp_global.lock);
return rc;
}
diff --git a/net/ipv4/inet_diag.c b/net/ipv4/inet_diag.c
index e4d16fc..4273576 100644
--- a/net/ipv4/inet_diag.c
+++ b/net/ipv4/inet_diag.c
@@ -868,12 +868,13 @@ void inet_diag_dump_icsk(struct inet_hashinfo *hashinfo, struct sk_buff *skb,
for (i = s_i; i < INET_LHTABLE_SIZE; i++) {
struct inet_listen_hashbucket *ilb;
+ struct hlist_nulls_node *node;
struct sock *sk;
num = 0;
ilb = &hashinfo->listening_hash[i];
spin_lock_bh(&ilb->lock);
- sk_for_each(sk, &ilb->head) {
+ sk_nulls_for_each(sk, node, &ilb->nulls_head) {
struct inet_sock *inet = inet_sk(sk);
if (!net_eq(sock_net(sk), net))
diff --git a/net/ipv4/inet_hashtables.c b/net/ipv4/inet_hashtables.c
index b9bcf3d..4bf542f 100644
--- a/net/ipv4/inet_hashtables.c
+++ b/net/ipv4/inet_hashtables.c
@@ -218,9 +218,10 @@ struct sock *__inet_lookup_listener(struct net *net,
int score, hiscore = 0, matches = 0, reuseport = 0;
bool exact_dif = inet_exact_dif_match(net, skb);
struct sock *sk, *result = NULL;
+ struct hlist_nulls_node *node;
u32 phash = 0;
- sk_for_each_rcu(sk, &ilb->head) {
+ sk_nulls_for_each_rcu(sk, node, &ilb->nulls_head) {
score = compute_score(sk, net, hnum, daddr, dif, exact_dif);
if (score > hiscore) {
reuseport = sk->sk_reuseport;
@@ -441,10 +442,11 @@ static int inet_reuseport_add_sock(struct sock *sk,
bool match_wildcard))
{
struct inet_bind_bucket *tb = inet_csk(sk)->icsk_bind_hash;
+ const struct hlist_nulls_node *node;
struct sock *sk2;
kuid_t uid = sock_i_uid(sk);
- sk_for_each_rcu(sk2, &ilb->head) {
+ sk_nulls_for_each_rcu(sk2, node, &ilb->nulls_head) {
if (sk2 != sk &&
sk2->sk_family == sk->sk_family &&
ipv6_only_sock(sk2) == ipv6_only_sock(sk) &&
@@ -482,9 +484,9 @@ int __inet_hash(struct sock *sk, struct sock *osk,
}
if (IS_ENABLED(CONFIG_IPV6) && sk->sk_reuseport &&
sk->sk_family == AF_INET6)
- hlist_add_tail_rcu(&sk->sk_node, &ilb->head);
+ __sk_nulls_add_node_tail_rcu(sk, &ilb->nulls_head);
else
- hlist_add_head_rcu(&sk->sk_node, &ilb->head);
+ __sk_nulls_add_node_rcu(sk, &ilb->nulls_head);
sock_set_flag(sk, SOCK_RCU_FREE);
sock_prot_inuse_add(sock_net(sk), sk->sk_prot, 1);
unlock:
@@ -527,10 +529,7 @@ void inet_unhash(struct sock *sk)
spin_lock_bh(lock);
if (rcu_access_pointer(sk->sk_reuseport_cb))
reuseport_detach_sock(sk);
- if (listener)
- done = __sk_del_node_init(sk);
- else
- done = __sk_nulls_del_node_init_rcu(sk);
+ done = __sk_nulls_del_node_init_rcu(sk);
if (done)
sock_prot_inuse_add(sock_net(sk), sk->sk_prot, -1);
spin_unlock_bh(lock);
@@ -666,7 +665,8 @@ void inet_hashinfo_init(struct inet_hashinfo *h)
for (i = 0; i < INET_LHTABLE_SIZE; i++) {
spin_lock_init(&h->listening_hash[i].lock);
- INIT_HLIST_HEAD(&h->listening_hash[i].head);
+ INIT_HLIST_NULLS_HEAD(&h->listening_hash[i].nulls_head,
+ i + LISTENING_NULLS_BASE);
}
}
EXPORT_SYMBOL_GPL(inet_hashinfo_init);
diff --git a/net/ipv4/ip_output.c b/net/ipv4/ip_output.c
index 4d3ef37..8eaf20a6 100644
--- a/net/ipv4/ip_output.c
+++ b/net/ipv4/ip_output.c
@@ -1181,13 +1181,17 @@ static int ip_setup_cork(struct sock *sk, struct inet_cork *cork,
rt = *rtp;
if (unlikely(!rt))
return -EFAULT;
- /*
- * We steal reference to this route, caller should not release it
- */
- *rtp = NULL;
+
cork->fragsize = ip_sk_use_pmtu(sk) ?
- dst_mtu(&rt->dst) : rt->dst.dev->mtu;
+ dst_mtu(&rt->dst) : READ_ONCE(rt->dst.dev->mtu);
+
+ if (!inetdev_valid_mtu(cork->fragsize))
+ return -ENETUNREACH;
+
cork->dst = &rt->dst;
+ /* We stole this route, caller should not release it. */
+ *rtp = NULL;
+
cork->length = 0;
cork->ttl = ipc->ttl;
cork->tos = ipc->tos;
diff --git a/net/ipv4/tcp_ipv4.c b/net/ipv4/tcp_ipv4.c
index f9ad41c..78a25d6 100644
--- a/net/ipv4/tcp_ipv4.c
+++ b/net/ipv4/tcp_ipv4.c
@@ -1927,13 +1927,14 @@ static void *listening_get_next(struct seq_file *seq, void *cur)
struct tcp_iter_state *st = seq->private;
struct net *net = seq_file_net(seq);
struct inet_listen_hashbucket *ilb;
+ struct hlist_nulls_node *node;
struct sock *sk = cur;
if (!sk) {
get_head:
ilb = &tcp_hashinfo.listening_hash[st->bucket];
spin_lock_bh(&ilb->lock);
- sk = sk_head(&ilb->head);
+ sk = sk_nulls_head(&ilb->nulls_head);
st->offset = 0;
goto get_sk;
}
@@ -1941,9 +1942,9 @@ static void *listening_get_next(struct seq_file *seq, void *cur)
++st->num;
++st->offset;
- sk = sk_next(sk);
+ sk = sk_nulls_next(sk);
get_sk:
- sk_for_each_from(sk) {
+ sk_nulls_for_each_from(sk, node) {
if (!net_eq(sock_net(sk), net))
continue;
if (sk->sk_family == st->family)
diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c
index bcf39c1..a7c86c8 100644
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -707,8 +707,9 @@ static unsigned int tcp_established_options(struct sock *sk, struct sk_buff *skb
min_t(unsigned int, eff_sacks,
(remaining - TCPOLEN_SACK_BASE_ALIGNED) /
TCPOLEN_SACK_PERBLOCK);
- size += TCPOLEN_SACK_BASE_ALIGNED +
- opts->num_sack_blocks * TCPOLEN_SACK_PERBLOCK;
+ if (likely(opts->num_sack_blocks))
+ size += TCPOLEN_SACK_BASE_ALIGNED +
+ opts->num_sack_blocks * TCPOLEN_SACK_PERBLOCK;
}
return size;
@@ -2232,6 +2233,14 @@ static bool tcp_write_xmit(struct sock *sk, unsigned int mss_now, int nonagle,
if (tcp_small_queue_check(sk, skb, 0))
break;
+ /* Argh, we hit an empty skb(), presumably a thread
+ * is sleeping in sendmsg()/sk_stream_wait_memory().
+ * We do not want to send a pure-ack packet and have
+ * a strange looking rtx queue with empty packet(s).
+ */
+ if (TCP_SKB_CB(skb)->end_seq == TCP_SKB_CB(skb)->seq)
+ break;
+
if (unlikely(tcp_transmit_skb(sk, skb, 1, gfp)))
break;
diff --git a/net/ipv4/tcp_timer.c b/net/ipv4/tcp_timer.c
index d962922..95ee069 100644
--- a/net/ipv4/tcp_timer.c
+++ b/net/ipv4/tcp_timer.c
@@ -404,7 +404,7 @@ static void tcp_probe_timer(struct sock *sk)
return;
}
- if (icsk->icsk_probes_out > max_probes) {
+ if (icsk->icsk_probes_out >= max_probes) {
abort: tcp_write_err(sk);
} else {
/* Only send another probe if we didn't close things up. */
@@ -510,11 +510,12 @@ void tcp_retransmit_timer(struct sock *sk)
goto out_reset_timer;
}
+ __NET_INC_STATS(sock_net(sk), LINUX_MIB_TCPTIMEOUTS);
if (tcp_write_timeout(sk))
goto out;
if (icsk->icsk_retransmits == 0) {
- int mib_idx;
+ int mib_idx = 0;
if (icsk->icsk_ca_state == TCP_CA_Recovery) {
if (tcp_is_sack(tp))
@@ -529,10 +530,9 @@ void tcp_retransmit_timer(struct sock *sk)
mib_idx = LINUX_MIB_TCPSACKFAILURES;
else
mib_idx = LINUX_MIB_TCPRENOFAILURES;
- } else {
- mib_idx = LINUX_MIB_TCPTIMEOUTS;
}
- __NET_INC_STATS(sock_net(sk), mib_idx);
+ if (mib_idx)
+ __NET_INC_STATS(sock_net(sk), mib_idx);
}
tcp_enter_loss(sk);
diff --git a/net/ipv6/inet6_hashtables.c b/net/ipv6/inet6_hashtables.c
index 02761c9..d47cab6 100644
--- a/net/ipv6/inet6_hashtables.c
+++ b/net/ipv6/inet6_hashtables.c
@@ -133,9 +133,10 @@ struct sock *inet6_lookup_listener(struct net *net,
int score, hiscore = 0, matches = 0, reuseport = 0;
bool exact_dif = inet6_exact_dif_match(net, skb);
struct sock *sk, *result = NULL;
+ struct hlist_nulls_node *node;
u32 phash = 0;
- sk_for_each(sk, &ilb->head) {
+ sk_nulls_for_each(sk, node, &ilb->nulls_head) {
score = compute_score(sk, net, hnum, daddr, dif, exact_dif);
if (score > hiscore) {
reuseport = sk->sk_reuseport;
diff --git a/net/nfc/nci/uart.c b/net/nfc/nci/uart.c
index c468eab..90268b6 100644
--- a/net/nfc/nci/uart.c
+++ b/net/nfc/nci/uart.c
@@ -348,7 +348,7 @@ static int nci_uart_default_recv_buf(struct nci_uart *nu, const u8 *data,
nu->rx_packet_len = -1;
nu->rx_skb = nci_skb_alloc(nu->ndev,
NCI_MAX_PACKET_SIZE,
- GFP_KERNEL);
+ GFP_ATOMIC);
if (!nu->rx_skb)
return -ENOMEM;
}
diff --git a/net/openvswitch/conntrack.c b/net/openvswitch/conntrack.c
index 02d6f38..beb2897 100644
--- a/net/openvswitch/conntrack.c
+++ b/net/openvswitch/conntrack.c
@@ -709,6 +709,17 @@ static int ovs_ct_nat(struct net *net, struct sw_flow_key *key,
}
err = ovs_ct_nat_execute(skb, ct, ctinfo, &info->range, maniptype);
+ if (err == NF_ACCEPT &&
+ ct->status & IPS_SRC_NAT && ct->status & IPS_DST_NAT) {
+ if (maniptype == NF_NAT_MANIP_SRC)
+ maniptype = NF_NAT_MANIP_DST;
+ else
+ maniptype = NF_NAT_MANIP_SRC;
+
+ err = ovs_ct_nat_execute(skb, ct, ctinfo, &info->range,
+ maniptype);
+ }
+
/* Mark NAT done if successful and update the flow key. */
if (err == NF_ACCEPT)
ovs_nat_update_key(key, skb, maniptype);
diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c
index e3f0a17..e2c6ef8 100644
--- a/net/packet/af_packet.c
+++ b/net/packet/af_packet.c
@@ -587,7 +587,8 @@ static int prb_calc_retire_blk_tmo(struct packet_sock *po,
msec = 1;
div = ecmd.base.speed / 1000;
}
- }
+ } else
+ return DEFAULT_PRB_RETIRE_TOV;
mbits = (blk_size_in_bytes * 8) / (1024 * 1024);
diff --git a/net/sctp/protocol.c b/net/sctp/protocol.c
index 9cb06ca..446503d 100644
--- a/net/sctp/protocol.c
+++ b/net/sctp/protocol.c
@@ -257,6 +257,7 @@ static void sctp_v4_from_sk(union sctp_addr *addr, struct sock *sk)
addr->v4.sin_family = AF_INET;
addr->v4.sin_port = 0;
addr->v4.sin_addr.s_addr = inet_sk(sk)->inet_rcv_saddr;
+ memset(addr->v4.sin_zero, 0, sizeof(addr->v4.sin_zero));
}
/* Initialize sk->sk_rcv_saddr from sctp_addr. */
@@ -279,6 +280,7 @@ static void sctp_v4_from_addr_param(union sctp_addr *addr,
addr->v4.sin_family = AF_INET;
addr->v4.sin_port = port;
addr->v4.sin_addr.s_addr = param->v4.addr.s_addr;
+ memset(addr->v4.sin_zero, 0, sizeof(addr->v4.sin_zero));
}
/* Initialize an address parameter from a sctp_addr and return the length
@@ -303,6 +305,7 @@ static void sctp_v4_dst_saddr(union sctp_addr *saddr, struct flowi4 *fl4,
saddr->v4.sin_family = AF_INET;
saddr->v4.sin_port = port;
saddr->v4.sin_addr.s_addr = fl4->saddr;
+ memset(saddr->v4.sin_zero, 0, sizeof(saddr->v4.sin_zero));
}
/* Compare two addresses exactly. */
@@ -325,6 +328,7 @@ static void sctp_v4_inaddr_any(union sctp_addr *addr, __be16 port)
addr->v4.sin_family = AF_INET;
addr->v4.sin_addr.s_addr = htonl(INADDR_ANY);
addr->v4.sin_port = port;
+ memset(addr->v4.sin_zero, 0, sizeof(addr->v4.sin_zero));
}
/* Is this a wildcard address? */
diff --git a/net/sunrpc/cache.c b/net/sunrpc/cache.c
index cdcc0fe..24e4291 100644
--- a/net/sunrpc/cache.c
+++ b/net/sunrpc/cache.c
@@ -54,9 +54,6 @@ static void cache_init(struct cache_head *h, struct cache_detail *detail)
h->last_refresh = now;
}
-static inline int cache_is_valid(struct cache_head *h);
-static void cache_fresh_locked(struct cache_head *head, time_t expiry,
- struct cache_detail *detail);
static void cache_fresh_unlocked(struct cache_head *head,
struct cache_detail *detail);
@@ -101,9 +98,6 @@ struct cache_head *sunrpc_cache_lookup(struct cache_detail *detail,
if (cache_is_expired(detail, tmp)) {
hlist_del_init(&tmp->cache_list);
detail->entries --;
- if (cache_is_valid(tmp) == -EAGAIN)
- set_bit(CACHE_NEGATIVE, &tmp->flags);
- cache_fresh_locked(tmp, 0, detail);
freeme = tmp;
break;
}
diff --git a/net/tipc/core.c b/net/tipc/core.c
index 59980de..799900c 100644
--- a/net/tipc/core.c
+++ b/net/tipc/core.c
@@ -116,14 +116,6 @@ static int __init tipc_init(void)
sysctl_tipc_rmem[1] = RCVBUF_DEF;
sysctl_tipc_rmem[2] = RCVBUF_MAX;
- err = tipc_netlink_start();
- if (err)
- goto out_netlink;
-
- err = tipc_netlink_compat_start();
- if (err)
- goto out_netlink_compat;
-
err = tipc_register_sysctl();
if (err)
goto out_sysctl;
@@ -144,8 +136,21 @@ static int __init tipc_init(void)
if (err)
goto out_bearer;
+ err = tipc_netlink_start();
+ if (err)
+ goto out_netlink;
+
+ err = tipc_netlink_compat_start();
+ if (err)
+ goto out_netlink_compat;
+
pr_info("Started in single node mode\n");
return 0;
+
+out_netlink_compat:
+ tipc_netlink_stop();
+out_netlink:
+ tipc_bearer_cleanup();
out_bearer:
unregister_pernet_device(&tipc_topsrv_net_ops);
out_pernet_topsrv:
@@ -155,22 +160,18 @@ static int __init tipc_init(void)
out_pernet:
tipc_unregister_sysctl();
out_sysctl:
- tipc_netlink_compat_stop();
-out_netlink_compat:
- tipc_netlink_stop();
-out_netlink:
pr_err("Unable to start in single node mode\n");
return err;
}
static void __exit tipc_exit(void)
{
+ tipc_netlink_compat_stop();
+ tipc_netlink_stop();
tipc_bearer_cleanup();
unregister_pernet_device(&tipc_topsrv_net_ops);
tipc_socket_stop();
unregister_pernet_device(&tipc_net_ops);
- tipc_netlink_stop();
- tipc_netlink_compat_stop();
tipc_unregister_sysctl();
pr_info("Deactivated\n");
diff --git a/net/x25/af_x25.c b/net/x25/af_x25.c
index 770abab..6c2560f 100644
--- a/net/x25/af_x25.c
+++ b/net/x25/af_x25.c
@@ -100,7 +100,7 @@ int x25_parse_address_block(struct sk_buff *skb,
}
len = *skb->data;
- needed = 1 + (len >> 4) + (len & 0x0f);
+ needed = 1 + ((len >> 4) + (len & 0x0f) + 1) / 2;
if (!pskb_may_pull(skb, needed)) {
/* packet is too short to hold the addresses it claims
@@ -288,7 +288,7 @@ static struct sock *x25_find_listener(struct x25_address *addr,
sk_for_each(s, &x25_list)
if ((!strcmp(addr->x25_addr,
x25_sk(s)->source_addr.x25_addr) ||
- !strcmp(addr->x25_addr,
+ !strcmp(x25_sk(s)->source_addr.x25_addr,
null_x25_address.x25_addr)) &&
s->sk_state == TCP_LISTEN) {
/*
@@ -684,11 +684,15 @@ static int x25_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len)
goto out;
}
- len = strlen(addr->sx25_addr.x25_addr);
- for (i = 0; i < len; i++) {
- if (!isdigit(addr->sx25_addr.x25_addr[i])) {
- rc = -EINVAL;
- goto out;
+ /* check for the null_x25_address */
+ if (strcmp(addr->sx25_addr.x25_addr, null_x25_address.x25_addr)) {
+
+ len = strlen(addr->sx25_addr.x25_addr);
+ for (i = 0; i < len; i++) {
+ if (!isdigit(addr->sx25_addr.x25_addr[i])) {
+ rc = -EINVAL;
+ goto out;
+ }
}
}
diff --git a/samples/pktgen/functions.sh b/samples/pktgen/functions.sh
index 205e4cd..065a7e2 100644
--- a/samples/pktgen/functions.sh
+++ b/samples/pktgen/functions.sh
@@ -5,6 +5,8 @@
# Author: Jesper Dangaaard Brouer
# License: GPL
+set -o errexit
+
## -- General shell logging cmds --
function err() {
local exitcode=$1
@@ -58,6 +60,7 @@
function proc_cmd() {
local result
local proc_file=$1
+ local status=0
# after shift, the remaining args are contained in $@
shift
local proc_ctrl=${PROC_DIR}/$proc_file
@@ -73,13 +76,13 @@
echo "cmd: $@ > $proc_ctrl"
fi
# Quoting of "$@" is important for space expansion
- echo "$@" > "$proc_ctrl"
- local status=$?
+ echo "$@" > "$proc_ctrl" || status=$?
- result=$(grep "Result: OK:" $proc_ctrl)
- # Due to pgctrl, cannot use exit code $? from grep
- if [[ "$result" == "" ]]; then
- grep "Result:" $proc_ctrl >&2
+ if [[ "$proc_file" != "pgctrl" ]]; then
+ result=$(grep "Result: OK:" $proc_ctrl) || true
+ if [[ "$result" == "" ]]; then
+ grep "Result:" $proc_ctrl >&2
+ fi
fi
if (( $status != 0 )); then
err 5 "Write error($status) occurred cmd: \"$@ > $proc_ctrl\""
@@ -105,6 +108,8 @@
fi
}
+[[ $EUID -eq 0 ]] && trap 'pg_ctrl "reset"' EXIT
+
## -- General shell tricks --
function root_check_run_with_sudo() {
diff --git a/scripts/kallsyms.c b/scripts/kallsyms.c
index 2c8b8c6..6402b0d 100644
--- a/scripts/kallsyms.c
+++ b/scripts/kallsyms.c
@@ -498,6 +498,8 @@ static void build_initial_tok_table(void)
table[pos] = table[i];
learn_symbol(table[pos].sym, table[pos].len);
pos++;
+ } else {
+ free(table[i].sym);
}
}
table_cnt = pos;
diff --git a/scripts/mod/modpost.c b/scripts/mod/modpost.c
index e5c4114..3dda774 100644
--- a/scripts/mod/modpost.c
+++ b/scripts/mod/modpost.c
@@ -1159,6 +1159,15 @@ static const struct sectioncheck *section_mismatch(
* refsymname = *.constprop.*
*
* Pattern 6:
+ * Hide section mismatch warnings for ELF local symbols. The goal
+ * is to eliminate false positive modpost warnings caused by
+ * compiler-generated ELF local symbol names such as ".LANCHOR1".
+ * Autogenerated symbol names bypass modpost's "Pattern 2"
+ * whitelisting, which relies on pattern-matching against symbol
+ * names to work. (One situation where gcc can autogenerate ELF
+ * local symbols is when "-fsection-anchors" is used.)
+ *
+ * Pattern 7:
* With CONFIG_CFI_CLANG, clang appends .cfi to all indirectly called
* functions and creates a function stub with the original name. This
* stub is always placed in .text, even if the actual function with the
@@ -1207,6 +1216,10 @@ static int secref_whitelist(const struct sectioncheck *mismatch,
return 0;
/* Check for pattern 6 */
+ if (strstarts(fromsym, ".L"))
+ return 0;
+
+ /* Check for pattern 7 */
if (match(fromsec, text_sections) &&
match(tosec, init_exit_sections) &&
match(tosym, cfi_symbols))
diff --git a/sound/core/oss/linear.c b/sound/core/oss/linear.c
index 2045697..797d838 100644
--- a/sound/core/oss/linear.c
+++ b/sound/core/oss/linear.c
@@ -107,6 +107,8 @@ static snd_pcm_sframes_t linear_transfer(struct snd_pcm_plugin *plugin,
}
}
#endif
+ if (frames > dst_channels[0].frames)
+ frames = dst_channels[0].frames;
convert(plugin, src_channels, dst_channels, frames);
return frames;
}
diff --git a/sound/core/oss/mulaw.c b/sound/core/oss/mulaw.c
index 7915564..3788906 100644
--- a/sound/core/oss/mulaw.c
+++ b/sound/core/oss/mulaw.c
@@ -269,6 +269,8 @@ static snd_pcm_sframes_t mulaw_transfer(struct snd_pcm_plugin *plugin,
}
}
#endif
+ if (frames > dst_channels[0].frames)
+ frames = dst_channels[0].frames;
data = (struct mulaw_priv *)plugin->extra_data;
data->func(plugin, src_channels, dst_channels, frames);
return frames;
diff --git a/sound/core/oss/route.c b/sound/core/oss/route.c
index c8171f5..72dea04 100644
--- a/sound/core/oss/route.c
+++ b/sound/core/oss/route.c
@@ -57,6 +57,8 @@ static snd_pcm_sframes_t route_transfer(struct snd_pcm_plugin *plugin,
return -ENXIO;
if (frames == 0)
return 0;
+ if (frames > dst_channels[0].frames)
+ frames = dst_channels[0].frames;
nsrcs = plugin->src_format.channels;
ndsts = plugin->dst_format.channels;
diff --git a/sound/core/pcm_lib.c b/sound/core/pcm_lib.c
index 2bae2a3..3640269 100644
--- a/sound/core/pcm_lib.c
+++ b/sound/core/pcm_lib.c
@@ -1892,11 +1892,14 @@ void snd_pcm_period_elapsed(struct snd_pcm_substream *substream)
struct snd_pcm_runtime *runtime;
unsigned long flags;
- if (PCM_RUNTIME_CHECK(substream))
+ if (snd_BUG_ON(!substream))
return;
- runtime = substream->runtime;
snd_pcm_stream_lock_irqsave(substream, flags);
+ if (PCM_RUNTIME_CHECK(substream))
+ goto _unlock;
+ runtime = substream->runtime;
+
if (!snd_pcm_running(substream) ||
snd_pcm_update_hw_ptr0(substream, 1) < 0)
goto _end;
@@ -1907,6 +1910,7 @@ void snd_pcm_period_elapsed(struct snd_pcm_substream *substream)
#endif
_end:
kill_fasync(&runtime->fasync, SIGIO, POLL_IN);
+ _unlock:
snd_pcm_stream_unlock_irqrestore(substream, flags);
}
diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c
index 0a747df..855e911 100755
--- a/sound/core/pcm_native.c
+++ b/sound/core/pcm_native.c
@@ -587,6 +587,10 @@ static int snd_pcm_hw_params(struct snd_pcm_substream *substream,
LONG_MAX - runtime->buffer_size)
runtime->boundary *= 2;
+ /* clear the buffer for avoiding possible kernel info leaks */
+ if (runtime->dma_area)
+ memset(runtime->dma_area, 0, runtime->dma_bytes);
+
snd_pcm_timer_resolution_change(substream);
snd_pcm_set_state(substream, SNDRV_PCM_STATE_SETUP);
diff --git a/sound/core/timer.c b/sound/core/timer.c
index 4eb0859..be9e517 100644
--- a/sound/core/timer.c
+++ b/sound/core/timer.c
@@ -87,6 +87,9 @@ static LIST_HEAD(snd_timer_slave_list);
/* lock for slave active lists */
static DEFINE_SPINLOCK(slave_active_lock);
+#define MAX_SLAVE_INSTANCES 1000
+static int num_slaves;
+
static DEFINE_MUTEX(register_mutex);
static int snd_timer_free(struct snd_timer *timer);
@@ -265,6 +268,10 @@ int snd_timer_open(struct snd_timer_instance **ti,
err = -EINVAL;
goto unlock;
}
+ if (num_slaves >= MAX_SLAVE_INSTANCES) {
+ err = -EBUSY;
+ goto unlock;
+ }
timeri = snd_timer_instance_new(owner, NULL);
if (!timeri) {
err = -ENOMEM;
@@ -274,6 +281,7 @@ int snd_timer_open(struct snd_timer_instance **ti,
timeri->slave_id = tid->device;
timeri->flags |= SNDRV_TIMER_IFLG_SLAVE;
list_add_tail(&timeri->open_list, &snd_timer_slave_list);
+ num_slaves++;
err = snd_timer_check_slave(timeri);
if (err < 0) {
snd_timer_close_locked(timeri, &card_dev_to_put);
@@ -363,6 +371,8 @@ static int snd_timer_close_locked(struct snd_timer_instance *timeri,
struct snd_timer_instance *slave, *tmp;
list_del(&timeri->open_list);
+ if (timeri->flags & SNDRV_TIMER_IFLG_SLAVE)
+ num_slaves--;
/* force to stop the timer */
snd_timer_stop(timeri);
diff --git a/sound/pci/hda/hda_bind.c b/sound/pci/hda/hda_bind.c
index 7ea201c..d0d6dfb 100644
--- a/sound/pci/hda/hda_bind.c
+++ b/sound/pci/hda/hda_bind.c
@@ -42,6 +42,10 @@ static void hda_codec_unsol_event(struct hdac_device *dev, unsigned int ev)
{
struct hda_codec *codec = container_of(dev, struct hda_codec, core);
+ /* ignore unsol events during shutdown */
+ if (codec->bus->shutdown)
+ return;
+
if (codec->patch_ops.unsol_event)
codec->patch_ops.unsol_event(codec, ev);
}
diff --git a/sound/pci/hda/hda_controller.c b/sound/pci/hda/hda_controller.c
index c5e8232..bd0e471 100644
--- a/sound/pci/hda/hda_controller.c
+++ b/sound/pci/hda/hda_controller.c
@@ -872,7 +872,7 @@ static int azx_rirb_get_response(struct hdac_bus *bus, unsigned int addr,
return -EAGAIN; /* give a chance to retry */
}
- dev_WARN(chip->card->dev,
+ dev_err(chip->card->dev,
"azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
bus->last_cmd[addr]);
chip->single_cmd = 1;
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index f2f1d9f..3234e9c 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -1275,8 +1275,11 @@ static int azx_free(struct azx *chip)
static int azx_dev_disconnect(struct snd_device *device)
{
struct azx *chip = device->device_data;
+ struct hdac_bus *bus = azx_bus(chip);
chip->bus.shutdown = 1;
+ cancel_work_sync(&bus->unsol_work);
+
return 0;
}
diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c
index 475b2c6..bf7593f 100644
--- a/sound/pci/hda/patch_ca0132.c
+++ b/sound/pci/hda/patch_ca0132.c
@@ -1300,13 +1300,14 @@ struct scp_msg {
static void dspio_clear_response_queue(struct hda_codec *codec)
{
+ unsigned long timeout = jiffies + msecs_to_jiffies(1000);
unsigned int dummy = 0;
- int status = -1;
+ int status;
/* clear all from the response queue */
do {
status = dspio_read(codec, &dummy);
- } while (status == 0);
+ } while (status == 0 && time_before(jiffies, timeout));
}
static int dspio_get_response_data(struct hda_codec *codec)
@@ -4424,12 +4425,14 @@ static void ca0132_process_dsp_response(struct hda_codec *codec,
struct ca0132_spec *spec = codec->spec;
codec_dbg(codec, "ca0132_process_dsp_response\n");
+ snd_hda_power_up_pm(codec);
if (spec->wait_scp) {
if (dspio_get_response_data(codec) >= 0)
spec->wait_scp = 0;
}
dspio_clear_response_queue(codec);
+ snd_hda_power_down_pm(codec);
}
static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 91f409b..b4c914c 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -204,6 +204,7 @@
select SND_SOC_WM9712 if SND_SOC_AC97_BUS
select SND_SOC_WM9713 if SND_SOC_AC97_BUS
select SND_SOC_AW8896 if I2C
+ select SND_SOC_TFA98XX if I2C
help
Normally ASoC codec drivers are only built if a machine driver which
uses them is also built since they are only usable with a machine
@@ -1096,4 +1097,9 @@
help
Enables support for aw8896 series Smart PA.
+config SND_SOC_TFA98XX
+ tristate "NXP Semiconductors TFA98XX amplifier"
+ depends on I2C
+ help
+ Enables support for NXP98xx Smart PA.
endmenu
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index b08cbe0..cf30a19 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -221,6 +221,10 @@
snd-soc-tpa6130a2-objs := tpa6130a2.o
snd-soc-tas2552-objs := tas2552.o
snd-soc-aw8896-objs := aw8896.o
+snd-soc-tfa98xx-objs := tfa98xx.o
+snd-soc-tfa98xx-objs += tfa_container.o
+snd-soc-tfa98xx-objs += tfa_dsp.o
+snd-soc-tfa98xx-objs += tfa_init.o
obj-$(CONFIG_SND_SOC_88PM860X) += snd-soc-88pm860x.o
obj-$(CONFIG_SND_SOC_AB8500_CODEC) += snd-soc-ab8500-codec.o
@@ -442,3 +446,4 @@
obj-$(CONFIG_SND_SOC_MAX98504) += snd-soc-max98504.o
obj-$(CONFIG_SND_SOC_TPA6130A2) += snd-soc-tpa6130a2.o
obj-$(CONFIG_SND_SOC_AW8896) += snd-soc-aw8896.o
+obj-$(CONFIG_SND_SOC_TFA98XX) += snd-soc-tfa98xx.o
diff --git a/inc/config.h b/sound/soc/codecs/config.h
similarity index 71%
rename from inc/config.h
rename to sound/soc/codecs/config.h
index a7eb863..85b0aeb 100644
--- a/inc/config.h
+++ b/sound/soc/codecs/config.h
@@ -1,34 +1,39 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-/*
- Linux kernel specific definitions used by code shared with
- Linux/Windows user space.
-*/
-
-#ifndef __CONFIG_LINUX_KERNEL_INC__
-#define __CONFIG_LINUX_KERNEL_INC__
-
-#include <linux/ctype.h>
-#include <linux/delay.h>
-#include <linux/slab.h>
-#include <linux/crc32.h>
-#include <linux/ftrace.h>
-
-#define _ASSERT(e)
-#define PRINT_ASSERT(e)if ((e)) printk(KERN_ERR "PrintAssert:%s (%s:%d) error code:%d\n",__FUNCTION__,__FILE__,__LINE__, e)
-
-#if defined(CONFIG_TRACING) && defined(DEBUG)
- #define tfa98xx_trace_printk(...) trace_printk(__VA_ARGS__)
-#else
- #define tfa98xx_trace_printk(...)
-#endif
-
-#endif /* __CONFIG_LINUX_KERNEL_INC__ */
-
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/*
+ * Linux kernel specific definitions used by code shared with
+ * Linux/Windows user space.
+ */
+
+#ifndef __CONFIG_LINUX_KERNEL_INC__
+#define __CONFIG_LINUX_KERNEL_INC__
+
+#include <linux/ctype.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/crc32.h>
+#include <linux/ftrace.h>
+
+#define _ASSERT(e)
+#ifndef PRINT_ASSERT
+#define PRINT_ASSERT(e) {\
+ (if ((e))\
+ printk(KERN_ERR "PrintAssert:%s (%s:%d) error code:%d\n",\
+ __FUNCTION__, __FILE__, __LINE__, e)) \
+ }
+#endif
+#if defined(CONFIG_TRACING) && defined(DEBUG)
+ #define tfa98xx_trace_printk(...) trace_printk(__VA_ARGS__)
+#else
+ #define tfa98xx_trace_printk(...)
+#endif
+
+#endif /* __CONFIG_LINUX_KERNEL_INC__ */
+
diff --git a/sound/soc/codecs/dbgprint.h b/sound/soc/codecs/dbgprint.h
new file mode 100644
index 0000000..bcd3bda
--- /dev/null
+++ b/sound/soc/codecs/dbgprint.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _DBGPRINT_H
+# define _DBGPRINT_H
+
+/* Debugging macro's. */
+# ifndef DEBUG
+# define DEBUG
+# endif
+
+# ifndef ASSERT
+//#define ASSERT
+# endif
+ //TODO wwwim
+# ifndef _ASSERT
+ #define _ASSERT(e)
+# endif
+
+# ifndef PREFIX
+# define PREFIX "tfa98xx: "
+# define DRIVER_NAME "tfa98xx"
+# endif
+
+#ifdef __KERNEL__
+
+# ifdef DEBUG
+# define _DEBUG(level, fmt, va...) do {\
+ if (unlikely(debug >= (level))) \
+ printk(KERN_INFO PREFIX "%s:%d: "fmt,\
+ __func__, __LINE__, ##va); \
+ } while (0);
+
+# else
+# define _DEBUG(level, fmt, va...) do {} while (0)
+# endif
+
+# define MSG(fmt, va...) printk(KERN_INFO PREFIX "%s:%d: "fmt,\
+ __func__, __LINE__, ##va)
+# define _ERRORMSG(fmt, va...) printk(KERN_ERR PREFIX "ERROR %s:%d: "fmt,\
+ __func__, __LINE__, ##va)
+
+
+# define DEBUG0(x...) MSG(x)
+# define DEBUG1(x...) _DEBUG(1, x)
+# define DEBUG2(x...) _DEBUG(2, x)
+# define DEBUG3(x...) _DEBUG(3, x)
+# define ERRORMSG(x...) _ERRORMSG(x)
+# define PRINT(x...) printk(x)
+# define PRINT_ERROR(x...) printk(KERN_INFO PREFIX " **ERROR** " x)
+# define PRINT_ASSERT(e) if (e) printk(KERN_ERR\
+ "PrintAssert:%s (%s:%d) error code:%d\n",\
+ __FUNCTION__, __FILE__, __LINE__, e)
+
+# define PRINT_ENTRY DEBUG2("+[%s]\n", __func__)
+# define PRINT_EXIT DEBUG2("-[%s]\n", __func__)
+
+# ifdef ASSERT
+# define assert(cond, action) do {\
+ if (unlikely(!(cond))) {
+ DEBUG0("Assert:\
+ %s\n", #cond); action; } } \
+ while (0)
+# else
+# define assert(cond, action) do { } while (0)
+# endif
+
+#else /* __KERNEL__ */
+#if defined(WIN32) || defined(_X64)
+#include <stdio.h>
+/* user mode */
+# ifdef DEBUG
+# define _DEBUGMSG(level, fmt, ...) printf(PREFIX "%s:%d: "fmt,\
+ __FUNCTION__, __LINE__, __VA_ARGS__)
+# else
+# define _DEBUGMSG(level, fmt, ...) do {} while (0)
+# endif
+
+# define _ERRORMSG(fmt, ...) printf(PREFIX "%s:%s:%d: "fmt, __FILE__,\
+ __FUNCTION__, __LINE__, __VA_ARGS__)
+
+# define DEBUG0(...) MSG(__VA_ARGS__)
+# define DEBUG1(...) _DEBUGMSG(1, __VA_ARGS__)
+# define DEBUG2(...) _DEBUGMSG(2, __VA_ARGS__)
+# define DEBUG3(...) _DEBUGMSG(3, __VA_ARGS__)
+# define ERRORMSG(fmt, ...) _ERRORMSG(fmt, __VA_ARGS__)
+# define PRINT(...) printf(__VA_ARGS__)
+/*
+# define PRINT(...) { FILE *stream; \
+ if((stream = freopen("nxp_tfa.txt", "ab+", stdout)) == NULL) exit(-1);\
+ printf(__VA_ARGS__); \
+ freopen( "CON", "ab+", stdout ); \
+ }
+*/
+# define PRINT_ERROR(...) fprintf(stderr, __VA_ARGS__)
+# define PRINT_FILE(file, ...) fprintf(file, __VA_ARGS__)
+# define PRINT_ASSERT(e) {\
+ if ((e))\
+ fprintf(stderr, "PrintAssert:%s (%s:%d)\
+ error code:%d\n", __FUNCTION__,\
+ __FILE__, __LINE__, e)\
+ }
+//# define PRINT_ASSERT(e) if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) %s\n",__FUNCTION__,__FILE__,__LINE__, Tfa98xx_GetErrorString(e))
+
+#elif defined(__CODE_RED)
+#include "app_global.h"
+# ifdef DEBUG
+# define _DEBUG(level, fmt, va...) TB_TRACE_INF(TbTracePfx2("tfa",\
+ TB_FUNC, va))
+//printf(PREFIX "%s:%d: "fmt,__func__,__LINE__,##va);
+# else
+# define _DEBUG(level, fmt, va...) do {} while (0)
+# endif
+
+# define MSG(fmt, ...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, __VA_ARGS__))
+//printf(PREFIX "%s:%s:%d: "fmt,__FILE__,__func__,__LINE__,##va)
+//TB_TRACE_INF(TbTracePfx2(APP_PFX,TB_FUNC,"path=%s, chan=%u, muted=%s, vol=%d\n",
+// path->isRecording ? "recording" : "playback",
+// i,
+// channelVol.currentMuteValue ? "YES" : "NO",
+// channelVol.currentVolumeValue
+// ));
+//# define _ERRORMSG(fmt,va...) TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,va))
+# define ERRORMSG(...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, __VA_ARGS__))
+//fprintf(stderr, PREFIX "ERROR %s:%s:%d: "fmt,__FILE__,__func__,__LINE__, ##va)
+
+#define DEBUG0(x...) MSG(x)
+#define DEBUG1(x...) _DEBUG(1, x)
+#define DEBUG2(x...) _DEBUG(2, x)
+#define DEBUG3(x...) _DEBUG(3, x)
+//# define ERRORMSG(x...) _ERRORMSG(x)
+#define PRINT(x...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, x))
+//printf(x)
+#define PRINT_ERROR(x...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, x))
+//fprintf(stderr,__VA_ARGS__)
+#define PRINT_FILE(file, x...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, x))
+//fprintf(file,__VA_ARGS__)
+#define PRINT_ASSERT(e)
+//TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,Tfa98xx_GetErrorString(e)))
+//if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) %s\n",__FUNCTION__,__FILE__,__LINE__, Tfa98xx_GetErrorString(e))
+#else
+#include <stdio.h>
+/* user mode */
+# ifdef DEBUG
+# define _DEBUG(level, fmt, va...) printf(PREFIX "%s:%d: "fmt, __func__,\
+ __LINE__, ##va);
+# else
+# define _DEBUG(level, fmt, va...) do {} while (0)
+# endif
+
+# define MSG(fmt, va...) printf(PREFIX "%s:%s:%d: "fmt, __FILE__, __func__,\
+ __LINE__, ##va)
+# define _ERRORMSG(fmt, va...) fprintf(stderr, PREFIX "ERROR %s:%s:%d: "fmt,\
+ __FILE__, __func__, __LINE__, ##va)
+
+#define DEBUG0(x...) MSG(x)
+#define DEBUG1(x...) _DEBUG(1, x)
+#define DEBUG2(x...) _DEBUG(2, x)
+#define DEBUG3(x...) _DEBUG(3, x)
+#define ERRORMSG(x...) _ERRORMSG(x)
+#define PRINT(x...) printf(x)
+#define PRINT_ERROR(...) fprintf(stderr, __VA_ARGS__)
+#define PRINT_FILE(file, ...) fprintf(file, __VA_ARGS__)
+#define PRINT_ASSERT(e)if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d)\
+ error code:%d\n", __FUNCTION__, __FILE__, __LINE__, e)
+//# define PRINT_ASSERT(e) if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) %s\n", __FUNCTION__, __FILE__, __LINE__, Tfa98xx_GetErrorString(e))
+
+
+#endif /* WIN32 */
+
+#endif /* user */
+
+#endif /* _DBGPRINT_H --------------- */
diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c
index 65ac451..49ab26e 100644
--- a/sound/soc/codecs/rt5677.c
+++ b/sound/soc/codecs/rt5677.c
@@ -305,6 +305,7 @@ static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
case RT5677_I2C_MASTER_CTRL7:
case RT5677_I2C_MASTER_CTRL8:
case RT5677_HAP_GENE_CTRL2:
+ case RT5677_PWR_ANLG2: /* Modified by DSP firmware */
case RT5677_PWR_DSP_ST:
case RT5677_PRIV_DATA:
case RT5677_ASRC_22:
diff --git a/sound/soc/codecs/tfa.h b/sound/soc/codecs/tfa.h
new file mode 100644
index 0000000..92410b7
--- /dev/null
+++ b/sound/soc/codecs/tfa.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef TFA_H_
+#define TFA_H_
+
+/* set the limit for the container file length */
+#define TFA_MAX_CNT_LENGTH (256*1024)
+
+extern struct tfa_device **devs;
+
+/**
+ * tfa error return codes
+ */
+enum tfa_error {
+ tfa_error_ok, /**< no error */
+ tfa_error_device, /**< no response from device */
+ tfa_error_bad_param,/**< parameter no accepted */
+ tfa_error_noclock, /**< required clock not present */
+ tfa_error_timeout, /**< a timeout occurred */
+ tfa_error_dsp, /**< a DSP error was returned */
+ tfa_error_container,/**< no or wrong container file */
+ tfa_error_max /**< impossible value, max enum */
+};
+
+enum Tfa98xx_Error tfa_write_filters(struct tfa_device *tfa, int prof_idx);
+
+struct tfa_device **tfa_devs_create(int count);
+void tfa_devs_destroy(int count);
+
+struct tfa_device **tfa_get_device_struct(void);
+
+int tfa_plop_noise_interrupt(struct tfa_device *tfa, int profile, int vstep);
+void tfa_lp_mode_interrupt(struct tfa_device *tfa);
+
+#endif /* TFA_H_ */
diff --git a/sound/soc/codecs/tfa1_tfafieldnames.h b/sound/soc/codecs/tfa1_tfafieldnames.h
new file mode 100644
index 0000000..81fed6a
--- /dev/null
+++ b/sound/soc/codecs/tfa1_tfafieldnames.h
@@ -0,0 +1,921 @@
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#define TFA9897_I2CVERSION 34
+typedef enum nxpTfa1BfEnumList {
+TFA1_BF_VDDS = 0x0000, /*!< Power-on-reset flag */
+TFA1_BF_PLLS = 0x0010, /*!< PLL lock */
+TFA1_BF_OTDS = 0x0020, /*!< Over Temperature Protection alarm */
+TFA1_BF_OVDS = 0x0030, /*!< Over Voltage Protection alarm */
+TFA1_BF_UVDS = 0x0040, /*!< Under Voltage Protection alarm */
+TFA1_BF_OCDS = 0x0050, /*!< Over Current Protection alarm */
+TFA1_BF_CLKS = 0x0060, /*!< Clocks stable flag */
+TFA1_BF_CLIPS = 0x0070, /*!< Amplifier clipping */
+TFA1_BF_MTPB = 0x0080, /*!< MTP busy */
+TFA1_BF_NOCLK = 0x0090, /*!< Flag lost clock from clock generationunit*/
+TFA1_BF_SPKS = 0x00a0, /*!< Speaker error flag */
+TFA1_BF_ACS = 0x00b0, /*!< Cold Start flag */
+TFA1_BF_SWS = 0x00c0, /*!< Flag Engage */
+TFA1_BF_WDS = 0x00d0, /*!< Flag watchdog reset */
+TFA1_BF_AMPS = 0x00e0, /*!< Amplifier is enabled by manager */
+TFA1_BF_AREFS = 0x00f0, /*!< References are enabled by manager */
+TFA1_BF_BATS = 0x0109, /*!< Battery voltage readout; 0 .. 5.5 [V] */
+TFA1_BF_TEMPS = 0x0208, /*!< Temperature readout from the temperature
+ * sensor */
+TFA1_BF_REV = 0x030b, /*!< Device type number is B97 */
+TFA1_BF_RCV = 0x0420, /*!< Enable Receiver Mode */
+TFA1_BF_CHS12 = 0x0431, /*!< Channel Selection TDM input for Coolflux */
+TFA1_BF_INPLVL = 0x0450, /*!< Input level selection control */
+TFA1_BF_CHSA = 0x0461, /*!< Input selection for amplifier */
+TFA1_BF_I2SDOE = 0x04b0, /*!< Enable data output */
+TFA1_BF_AUDFS = 0x04c3, /*!< Audio sample rate setting */
+TFA1_BF_BSSCR = 0x0501, /*!< Protection Attack Time */
+TFA1_BF_BSST = 0x0523, /*!< ProtectionThreshold */
+TFA1_BF_BSSRL = 0x0561, /*!< Protection Maximum Reduction */
+TFA1_BF_BSSRR = 0x0582, /*!< Battery Protection Release Time */
+TFA1_BF_BSSHY = 0x05b1, /*!< Battery Protection Hysteresis */
+TFA1_BF_BSSR = 0x05e0, /*!< battery voltage for I2C read out only */
+TFA1_BF_BSSBY = 0x05f0, /*!< bypass clipper battery protection */
+TFA1_BF_DPSA = 0x0600, /*!< Enable dynamic powerstage activation */
+TFA1_BF_CFSM = 0x0650, /*!< Soft mute in CoolFlux */
+TFA1_BF_BSSS = 0x0670, /*!< BatSenseSteepness */
+TFA1_BF_VOL = 0x0687, /*!< volume control (in CoolFlux) */
+TFA1_BF_DCVO = 0x0702, /*!< Boost Voltage */
+TFA1_BF_DCMCC = 0x0733, /*!< Max boost coil current - step of 175 mA */
+TFA1_BF_DCIE = 0x07a0, /*!< Adaptive boost mode */
+TFA1_BF_DCSR = 0x07b0, /*!< Soft RampUp/Down mode for DCDC controller*/
+TFA1_BF_DCPAVG = 0x07c0, /*!< ctrl_peak2avg for analog part of DCDC */
+TFA1_BF_TROS = 0x0800, /*!< Select external temperature also the ext_temp
+ * will be put on the temp read out */
+TFA1_BF_EXTTS = 0x0818, /*!< external temperature setting to be given
+ * by host*/
+TFA1_BF_PWDN = 0x0900, /*!< Device Mode */
+TFA1_BF_I2CR = 0x0910, /*!< I2C Reset */
+TFA1_BF_CFE = 0x0920, /*!< Enable CoolFlux */
+TFA1_BF_AMPE = 0x0930, /*!< Enable Amplifier */
+TFA1_BF_DCA = 0x0940, /*!< EnableBoost */
+TFA1_BF_SBSL = 0x0950, /*!< Coolflux configured */
+TFA1_BF_AMPC = 0x0960, /*!< Selection on how Amplifier is enabled */
+TFA1_BF_DCDIS = 0x0970, /*!< DCDC not connected */
+TFA1_BF_PSDR = 0x0980, /*!< IDDQ test amplifier */
+TFA1_BF_DCCV = 0x0991, /*!< Coil Value */
+TFA1_BF_CCFD = 0x09b0, /*!< Selection CoolFlux Clock */
+TFA1_BF_INTPAD = 0x09c1, /*!< INT pad configuration control */
+TFA1_BF_IPLL = 0x09e0, /*!< PLL input reference clock selection */
+TFA1_BF_MTPK = 0x0b07, /*!< 5Ah, 90d To access KEY1_Protected registers
+ * (Default for engineering) */
+TFA1_BF_CVFDLY = 0x0c25, /*!< Fractional delay adjustment between current
+ and voltage sense */
+TFA1_BF_TDMPRF = 0x1011, /*!< TDM_usecase */
+TFA1_BF_TDMEN = 0x1030, /*!< TDM interface control */
+TFA1_BF_TDMCKINV = 0x1040, /*!< TDM clock inversion */
+TFA1_BF_TDMFSLN = 0x1053, /*!< TDM FS length */
+TFA1_BF_TDMFSPOL = 0x1090, /*!< TDM FS polarity */
+TFA1_BF_TDMSAMSZ = 0x10a4, /*!< TDM Sample Size for all tdm
+ sinks/sources */
+TFA1_BF_TDMSLOTS = 0x1103, /*!< Number of slots */
+TFA1_BF_TDMSLLN = 0x1144, /*!< Slot length */
+TFA1_BF_TDMBRMG = 0x1194, /*!< Bits remaining */
+TFA1_BF_TDMDDEL = 0x11e0, /*!< Data delay */
+TFA1_BF_TDMDADJ = 0x11f0, /*!< Data adjustment */
+TFA1_BF_TDMTXFRM = 0x1201, /*!< TXDATA format */
+TFA1_BF_TDMUUS0 = 0x1221, /*!< TXDATA format unused slot sd0 */
+TFA1_BF_TDMUUS1 = 0x1241, /*!< TXDATA format unused slot sd1 */
+TFA1_BF_TDMSI0EN = 0x1270, /*!< TDM sink0 enable */
+TFA1_BF_TDMSI1EN = 0x1280, /*!< TDM sink1 enable */
+TFA1_BF_TDMSI2EN = 0x1290, /*!< TDM sink2 enable */
+TFA1_BF_TDMSO0EN = 0x12a0, /*!< TDM source0 enable */
+TFA1_BF_TDMSO1EN = 0x12b0, /*!< TDM source1 enable */
+TFA1_BF_TDMSO2EN = 0x12c0, /*!< TDM source2 enable */
+TFA1_BF_TDMSI0IO = 0x12d0, /*!< tdm_sink0_io */
+TFA1_BF_TDMSI1IO = 0x12e0, /*!< tdm_sink1_io */
+TFA1_BF_TDMSI2IO = 0x12f0, /*!< tdm_sink2_io */
+TFA1_BF_TDMSO0IO = 0x1300, /*!< tdm_source0_io */
+TFA1_BF_TDMSO1IO = 0x1310, /*!< tdm_source1_io */
+TFA1_BF_TDMSO2IO = 0x1320, /*!< tdm_source2_io */
+TFA1_BF_TDMSI0SL = 0x1333, /*!< sink0_slot [GAIN IN] */
+TFA1_BF_TDMSI1SL = 0x1373, /*!< sink1_slot [CH1 IN] */
+TFA1_BF_TDMSI2SL = 0x13b3, /*!< sink2_slot [CH2 IN] */
+TFA1_BF_TDMSO0SL = 0x1403, /*!< source0_slot [GAIN OUT] */
+TFA1_BF_TDMSO1SL = 0x1443, /*!< source1_slot [Voltage Sense] */
+TFA1_BF_TDMSO2SL = 0x1483, /*!< source2_slot [Current Sense] */
+TFA1_BF_NBCK = 0x14c3, /*!< NBCK */
+TFA1_BF_INTOVDDS = 0x2000, /*!< flag_por_int_out */
+TFA1_BF_INTOPLLS = 0x2010, /*!< flag_pll_lock_int_out */
+TFA1_BF_INTOOTDS = 0x2020, /*!< flag_otpok_int_out */
+TFA1_BF_INTOOVDS = 0x2030, /*!< flag_ovpok_int_out */
+TFA1_BF_INTOUVDS = 0x2040, /*!< flag_uvpok_int_out */
+TFA1_BF_INTOOCDS = 0x2050, /*!< flag_ocp_alarm_int_out */
+TFA1_BF_INTOCLKS = 0x2060, /*!< flag_clocks_stable_int_out */
+TFA1_BF_INTOCLIPS = 0x2070, /*!< flag_clip_int_out */
+TFA1_BF_INTOMTPB = 0x2080, /*!< mtp_busy_int_out */
+TFA1_BF_INTONOCLK = 0x2090, /*!< flag_lost_clk_int_out */
+TFA1_BF_INTOSPKS = 0x20a0, /*!< flag_cf_speakererror_int_out */
+TFA1_BF_INTOACS = 0x20b0, /*!< flag_cold_started_int_out */
+TFA1_BF_INTOSWS = 0x20c0, /*!< flag_engage_int_out */
+TFA1_BF_INTOWDS = 0x20d0, /*!< flag_watchdog_reset_int_out */
+TFA1_BF_INTOAMPS = 0x20e0, /*!< flag_enbl_amp_int_out */
+TFA1_BF_INTOAREFS = 0x20f0, /*!< flag_enbl_ref_int_out */
+TFA1_BF_INTOACK = 0x2201, /*!< Interrupt status register output -
+ * Corresponding flag */
+TFA1_BF_INTIVDDS = 0x2300, /*!< flag_por_int_in */
+TFA1_BF_INTIPLLS = 0x2310, /*!< flag_pll_lock_int_in */
+TFA1_BF_INTIOTDS = 0x2320, /*!< flag_otpok_int_in */
+TFA1_BF_INTIOVDS = 0x2330, /*!< flag_ovpok_int_in */
+TFA1_BF_INTIUVDS = 0x2340, /*!< flag_uvpok_int_in */
+TFA1_BF_INTIOCDS = 0x2350, /*!< flag_ocp_alarm_int_in */
+TFA1_BF_INTICLKS = 0x2360, /*!< flag_clocks_stable_int_in */
+TFA1_BF_INTICLIPS = 0x2370, /*!< flag_clip_int_in */
+TFA1_BF_INTIMTPB = 0x2380, /*!< mtp_busy_int_in */
+TFA1_BF_INTINOCLK = 0x2390, /*!< flag_lost_clk_int_in */
+TFA1_BF_INTISPKS = 0x23a0, /*!< flag_cf_speakererror_int_in */
+TFA1_BF_INTIACS = 0x23b0, /*!< flag_cold_started_int_in */
+TFA1_BF_INTISWS = 0x23c0, /*!< flag_engage_int_in */
+TFA1_BF_INTIWDS = 0x23d0, /*!< flag_watchdog_reset_int_in */
+TFA1_BF_INTIAMPS = 0x23e0, /*!< flag_enbl_amp_int_in */
+TFA1_BF_INTIAREFS = 0x23f0, /*!< flag_enbl_ref_int_in */
+TFA1_BF_INTIACK = 0x2501, /*!< Interrupt register input */
+TFA1_BF_INTENVDDS = 0x2600, /*!< flag_por_int_enable */
+TFA1_BF_INTENPLLS = 0x2610, /*!< flag_pll_lock_int_enable */
+TFA1_BF_INTENOTDS = 0x2620, /*!< flag_otpok_int_enable */
+TFA1_BF_INTENOVDS = 0x2630, /*!< flag_ovpok_int_enable */
+TFA1_BF_INTENUVDS = 0x2640, /*!< flag_uvpok_int_enable */
+TFA1_BF_INTENOCDS = 0x2650, /*!< flag_ocp_alarm_int_enable */
+TFA1_BF_INTENCLKS = 0x2660, /*!< flag_clocks_stable_int_enable */
+TFA1_BF_INTENCLIPS = 0x2670, /*!< flag_clip_int_enable */
+TFA1_BF_INTENMTPB = 0x2680, /*!< mtp_busy_int_enable */
+TFA1_BF_INTENNOCLK = 0x2690, /*!< flag_lost_clk_int_enable */
+TFA1_BF_INTENSPKS = 0x26a0, /*!< flag_cf_speakererror_int_enable */
+TFA1_BF_INTENACS = 0x26b0, /*!< flag_cold_started_int_enable */
+TFA1_BF_INTENSWS = 0x26c0, /*!< flag_engage_int_enable */
+TFA1_BF_INTENWDS = 0x26d0, /*!< flag_watchdog_reset_int_enable */
+TFA1_BF_INTENAMPS = 0x26e0, /*!< flag_enbl_amp_int_enable */
+TFA1_BF_INTENAREFS = 0x26f0, /*!< flag_enbl_ref_int_enable */
+TFA1_BF_INTENACK = 0x2801, /*!< Interrupt enable register */
+TFA1_BF_INTPOLVDDS = 0x2900, /*!< flag_por_int_pol */
+TFA1_BF_INTPOLPLLS = 0x2910, /*!< flag_pll_lock_int_pol */
+TFA1_BF_INTPOLOTDS = 0x2920, /*!< flag_otpok_int_pol */
+TFA1_BF_INTPOLOVDS = 0x2930, /*!< flag_ovpok_int_pol */
+TFA1_BF_INTPOLUVDS = 0x2940, /*!< flag_uvpok_int_pol */
+TFA1_BF_INTPOLOCDS = 0x2950, /*!< flag_ocp_alarm_int_pol */
+TFA1_BF_INTPOLCLKS = 0x2960, /*!< flag_clocks_stable_int_pol */
+TFA1_BF_INTPOLCLIPS = 0x2970, /*!< flag_clip_int_pol */
+TFA1_BF_INTPOLMTPB = 0x2980, /*!< mtp_busy_int_pol */
+TFA1_BF_INTPOLNOCLK = 0x2990, /*!< flag_lost_clk_int_pol */
+TFA1_BF_INTPOLSPKS = 0x29a0, /*!< flag_cf_speakererror_int_pol */
+TFA1_BF_INTPOLACS = 0x29b0, /*!< flag_cold_started_int_pol */
+TFA1_BF_INTPOLSWS = 0x29c0, /*!< flag_engage_int_pol */
+TFA1_BF_INTPOLWDS = 0x29d0, /*!< flag_watchdog_reset_int_pol */
+TFA1_BF_INTPOLAMPS = 0x29e0, /*!< flag_enbl_amp_int_pol */
+TFA1_BF_INTPOLAREFS = 0x29f0, /*!< flag_enbl_ref_int_pol */
+TFA1_BF_INTPOLACK = 0x2b01, /*!< Interrupt status flags
+ * polarity register */
+TFA1_BF_CLIP = 0x4900, /*!< Bypass clip control */
+TFA1_BF_CIMTP = 0x62b0, /*!< start copying all the data from i2cregs_mtp
+ to mtp [Key 2 protected] */
+TFA1_BF_RST = 0x7000, /*!< Reset CoolFlux DSP */
+TFA1_BF_DMEM = 0x7011, /*!< Target memory for access */
+TFA1_BF_AIF = 0x7030, /*!< Autoincrement-flag for memory-address */
+TFA1_BF_CFINT = 0x7040, /*!< Interrupt CoolFlux DSP */
+TFA1_BF_REQ = 0x7087, /*!< request for access (8 channels) */
+TFA1_BF_REQCMD = 0x7080, /*!< Firmware event request rpc command */
+TFA1_BF_REQRST = 0x7090, /*!< Firmware event request reset restart */
+TFA1_BF_REQMIPS = 0x70a0, /*!< Firmware event request short on mips */
+TFA1_BF_REQMUTED = 0x70b0, /*!< Firmware event request mute sequence ready*/
+TFA1_BF_REQVOL = 0x70c0, /*!< Firmware event request volume ready */
+TFA1_BF_REQDMG = 0x70d0, /*!< Firmware event request speaker damage detected*/
+TFA1_BF_REQCAL = 0x70e0, /*!< Firmware event request calibration completed */
+TFA1_BF_REQRSV = 0x70f0, /*!< Firmware event request reserved */
+TFA1_BF_MADD = 0x710f, /*!< memory-address to be accessed */
+TFA1_BF_MEMA = 0x720f, /*!< activate memory access (24- or 32-bits data is
+ * written/read to/from memory */
+TFA1_BF_ERR = 0x7307, /*!< Coolflux error flags */
+TFA1_BF_ACK = 0x7387, /*!< acknowledge of requests (8 channels) */
+TFA1_BF_MTPOTC = 0x8000, /*!< Calibration schedule (key2 protected) */
+TFA1_BF_MTPEX = 0x8010, /*!< (key2 protected) */
+} nxpTfa1BfEnumList_t;
+#define TFA1_NAMETABLE static tfaBfName_t Tfa1DatasheetNames[] = {\
+{ 0x0, "VDDS"}, /* Power-on-reset flag , */\
+{ 0x10, "PLLS"}, /* PLL lock , */\
+{ 0x20, "OTDS"}, /* Over Temperature Protection alarm , */\
+{ 0x30, "OVDS"}, /* Over Voltage Protection alarm , */\
+{ 0x40, "UVDS"}, /* Under Voltage Protection alarm , */\
+{ 0x50, "OCDS"}, /* Over Current Protection alarm , */\
+{ 0x60, "CLKS"}, /* Clocks stable flag , */\
+{ 0x70, "CLIPS"}, /* Amplifier clipping , */\
+{ 0x80, "MTPB"}, /* MTP busy , */\
+{ 0x90, "NOCLK"}, /* Flag lost clock from clock generation unit , */\
+{ 0xa0, "SPKS"}, /* Speaker error flag , */\
+{ 0xb0, "ACS"}, /* Cold Start flag , */\
+{ 0xc0, "SWS"}, /* Flag Engage , */\
+{ 0xd0, "WDS"}, /* Flag watchdog reset , */\
+{ 0xe0, "AMPS"}, /* Amplifier is enabled by manager , */\
+{ 0xf0, "AREFS"}, /* References are enabled by manager , */\
+{ 0x109, "BATS"}, /* Battery voltage readout; 0 .. 5.5 [V] , */\
+{ 0x208, "TEMPS"}, /* Temperature readout from the temperature sensor , */\
+{ 0x30b, "REV"}, /* Device type number is B97 , */\
+{ 0x420, "RCV"}, /* Enable Receiver Mode , */\
+{ 0x431, "CHS12"}, /* Channel Selection TDM input for Coolflux , */\
+{ 0x450, "INPLVL"}, /* Input level selection control , */\
+{ 0x461, "CHSA"}, /* Input selection for amplifier , */\
+{ 0x4b0, "I2SDOE"}, /* Enable data output , */\
+{ 0x4c3, "AUDFS"}, /* Audio sample rate setting , */\
+{ 0x501, "SSCR"}, /* Protection Attack Time , */\
+{ 0x523, "SST"}, /* ProtectionThreshold , */\
+{ 0x561, "SSRL"}, /* Protection Maximum Reduction , */\
+{ 0x582, "SSRR"}, /* Battery Protection Release Time , */\
+{ 0x5b1, "SSHY"}, /* Battery Protection Hysteresis , */\
+{ 0x5e0, "SSR"}, /* battery voltage for I2C read out only , */\
+{ 0x5f0, "SSBY"}, /* bypass clipper battery protection , */\
+{ 0x600, "DPSA"}, /* Enable dynamic powerstage activation , */\
+{ 0x650, "CFSM"}, /* Soft mute in CoolFlux , */\
+{ 0x670, "SSS"}, /* BatSenseSteepness , */\
+{ 0x687, "VOL"}, /* volume control (in CoolFlux) , */\
+{ 0x702, "DCVO"}, /* Boost Voltage , */\
+{ 0x733, "DCMCC"}, /* Max boost coil current - step of 175 mA , */\
+{ 0x7a0, "DCIE"}, /* Adaptive boost mode , */\
+{ 0x7b0, "DCSR"}, /* Soft RampUp/Down mode for DCDC controller , */\
+{ 0x7c0, "DCPAVG"}, /* ctrl_peak2avg for analog part of DCDC , */\
+{ 0x800, "TROS"}, /* Select external temperature also the ext_temp will be
+ * put on the temp read out , */\
+{ 0x818, "EXTTS"}, /* external temperature setting to be given by host , */\
+{ 0x900, "PWDN"}, /* Device Mode , */\
+{ 0x910, "I2CR"}, /* I2C Reset , */\
+{ 0x920, "CFE"}, /* Enable CoolFlux , */\
+{ 0x930, "AMPE"}, /* Enable Amplifier , */\
+{ 0x940, "DCA"}, /* EnableBoost , */\
+{ 0x950, "SBSL"}, /* Coolflux configured , */\
+{ 0x960, "AMPC"}, /* Selection on how Amplifier is enabled , */\
+{ 0x970, "DCDIS"}, /* DCDC not connected , */\
+{ 0x980, "PSDR"}, /* IDDQ test amplifier , */\
+{ 0x991, "DCCV"}, /* Coil Value , */\
+{ 0x9b0, "CCFD"}, /* Selection CoolFlux Clock , */\
+{ 0x9c1, "INTPAD"}, /* INT pad configuration control , */\
+{ 0x9e0, "IPLL"}, /* PLL input reference clock selection , */\
+{ 0xb07, "MTPK"}, /* 5Ah, 90d To access KEY1_Protected registers
+ * (Default for engineering), */\
+{ 0xc25, "CVFDLY"}, /* Fractional delay adjustment between current and
+ * voltage sense, */\
+{ 0x1011, "TDMPRF"}, /* TDM_usecase , */\
+{ 0x1030, "TDMEN"}, /* TDM interface control , */\
+{ 0x1040, "TDMCKINV"}, /* TDM clock inversion , */\
+{ 0x1053, "TDMFSLN"}, /* TDM FS length , */\
+{ 0x1090, "TDMFSPOL"}, /* TDM FS polarity , */\
+{ 0x10a4, "TDMSAMSZ"}, /* TDM Sample Size for all tdm sinks/sources , */\
+{ 0x1103, "TDMSLOTS"}, /* Number of slots , */\
+{ 0x1144, "TDMSLLN"}, /* Slot length , */\
+{ 0x1194, "TDMBRMG"}, /* Bits remaining , */\
+{ 0x11e0, "TDMDDEL"}, /* Data delay , */\
+{ 0x11f0, "TDMDADJ"}, /* Data adjustment , */\
+{ 0x1201, "TDMTXFRM"}, /* TXDATA format , */\
+{ 0x1221, "TDMUUS0"}, /* TXDATA format unused slot sd0 , */\
+{ 0x1241, "TDMUUS1"}, /* TXDATA format unused slot sd1 , */\
+{ 0x1270, "TDMSI0EN"}, /* TDM sink0 enable , */\
+{ 0x1280, "TDMSI1EN"}, /* TDM sink1 enable , */\
+{ 0x1290, "TDMSI2EN"}, /* TDM sink2 enable , */\
+{ 0x12a0, "TDMSO0EN"}, /* TDM source0 enable , */\
+{ 0x12b0, "TDMSO1EN"}, /* TDM source1 enable , */\
+{ 0x12c0, "TDMSO2EN"}, /* TDM source2 enable , */\
+{ 0x12d0, "TDMSI0IO"}, /* tdm_sink0_io , */\
+{ 0x12e0, "TDMSI1IO"}, /* tdm_sink1_io , */\
+{ 0x12f0, "TDMSI2IO"}, /* tdm_sink2_io , */\
+{ 0x1300, "TDMSO0IO"}, /* tdm_source0_io , */\
+{ 0x1310, "TDMSO1IO"}, /* tdm_source1_io , */\
+{ 0x1320, "TDMSO2IO"}, /* tdm_source2_io , */\
+{ 0x1333, "TDMSI0SL"}, /* sink0_slot [GAIN IN] , */\
+{ 0x1373, "TDMSI1SL"}, /* sink1_slot [CH1 IN] , */\
+{ 0x13b3, "TDMSI2SL"}, /* sink2_slot [CH2 IN] , */\
+{ 0x1403, "TDMSO0SL"}, /* source0_slot [GAIN OUT] , */\
+{ 0x1443, "TDMSO1SL"}, /* source1_slot [Voltage Sense] , */\
+{ 0x1483, "TDMSO2SL"}, /* source2_slot [Current Sense] , */\
+{ 0x14c3, "NBCK"}, /* NBCK , */\
+{ 0x2000, "INTOVDDS"}, /* flag_por_int_out , */\
+{ 0x2010, "INTOPLLS"}, /* flag_pll_lock_int_out , */\
+{ 0x2020, "INTOOTDS"}, /* flag_otpok_int_out , */\
+{ 0x2030, "INTOOVDS"}, /* flag_ovpok_int_out , */\
+{ 0x2040, "INTOUVDS"}, /* flag_uvpok_int_out , */\
+{ 0x2050, "INTOOCDS"}, /* flag_ocp_alarm_int_out , */\
+{ 0x2060, "INTOCLKS"}, /* flag_clocks_stable_int_out , */\
+{ 0x2070, "INTOCLIPS"}, /* flag_clip_int_out , */\
+{ 0x2080, "INTOMTPB"}, /* mtp_busy_int_out , */\
+{ 0x2090, "INTONOCLK"}, /* flag_lost_clk_int_out , */\
+{ 0x20a0, "INTOSPKS"}, /* flag_cf_speakererror_int_out , */\
+{ 0x20b0, "INTOACS"}, /* flag_cold_started_int_out , */\
+{ 0x20c0, "INTOSWS"}, /* flag_engage_int_out , */\
+{ 0x20d0, "INTOWDS"}, /* flag_watchdog_reset_int_out , */\
+{ 0x20e0, "INTOAMPS"}, /* flag_enbl_amp_int_out , */\
+{ 0x20f0, "INTOAREFS"}, /* flag_enbl_ref_int_out , */\
+{ 0x2201, "INTOACK"}, /* Interrupt status register output
+ * - Corresponding flag, */\
+{ 0x2300, "INTIVDDS"}, /* flag_por_int_in , */\
+{ 0x2310, "INTIPLLS"}, /* flag_pll_lock_int_in , */\
+{ 0x2320, "INTIOTDS"}, /* flag_otpok_int_in , */\
+{ 0x2330, "INTIOVDS"}, /* flag_ovpok_int_in , */\
+{ 0x2340, "INTIUVDS"}, /* flag_uvpok_int_in , */\
+{ 0x2350, "INTIOCDS"}, /* flag_ocp_alarm_int_in , */\
+{ 0x2360, "INTICLKS"}, /* flag_clocks_stable_int_in , */\
+{ 0x2370, "INTICLIPS"}, /* flag_clip_int_in , */\
+{ 0x2380, "INTIMTPB"}, /* mtp_busy_int_in , */\
+{ 0x2390, "INTINOCLK"}, /* flag_lost_clk_int_in , */\
+{ 0x23a0, "INTISPKS"}, /* flag_cf_speakererror_int_in , */\
+{ 0x23b0, "INTIACS"}, /* flag_cold_started_int_in , */\
+{ 0x23c0, "INTISWS"}, /* flag_engage_int_in , */\
+{ 0x23d0, "INTIWDS"}, /* flag_watchdog_reset_int_in , */\
+{ 0x23e0, "INTIAMPS"}, /* flag_enbl_amp_int_in , */\
+{ 0x23f0, "INTIAREFS"}, /* flag_enbl_ref_int_in , */\
+{ 0x2501, "INTIACK"}, /* Interrupt register input , */\
+{ 0x2600, "INTENVDDS"}, /* flag_por_int_enable , */\
+{ 0x2610, "INTENPLLS"}, /* flag_pll_lock_int_enable , */\
+{ 0x2620, "INTENOTDS"}, /* flag_otpok_int_enable , */\
+{ 0x2630, "INTENOVDS"}, /* flag_ovpok_int_enable , */\
+{ 0x2640, "INTENUVDS"}, /* flag_uvpok_int_enable , */\
+{ 0x2650, "INTENOCDS"}, /* flag_ocp_alarm_int_enable , */\
+{ 0x2660, "INTENCLKS"}, /* flag_clocks_stable_int_enable , */\
+{ 0x2670, "INTENCLIPS"}, /* flag_clip_int_enable , */\
+{ 0x2680, "INTENMTPB"}, /* mtp_busy_int_enable , */\
+{ 0x2690, "INTENNOCLK"}, /* flag_lost_clk_int_enable , */\
+{ 0x26a0, "INTENSPKS"}, /* flag_cf_speakererror_int_enable , */\
+{ 0x26b0, "INTENACS"}, /* flag_cold_started_int_enable , */\
+{ 0x26c0, "INTENSWS"}, /* flag_engage_int_enable , */\
+{ 0x26d0, "INTENWDS"}, /* flag_watchdog_reset_int_enable , */\
+{ 0x26e0, "INTENAMPS"}, /* flag_enbl_amp_int_enable , */\
+{ 0x26f0, "INTENAREFS"}, /* flag_enbl_ref_int_enable , */\
+{ 0x2801, "INTENACK"}, /* Interrupt enable register , */\
+{ 0x2900, "INTPOLVDDS"}, /* flag_por_int_pol , */\
+{ 0x2910, "INTPOLPLLS"}, /* flag_pll_lock_int_pol , */\
+{ 0x2920, "INTPOLOTDS"}, /* flag_otpok_int_pol , */\
+{ 0x2930, "INTPOLOVDS"}, /* flag_ovpok_int_pol , */\
+{ 0x2940, "INTPOLUVDS"}, /* flag_uvpok_int_pol , */\
+{ 0x2950, "INTPOLOCDS"}, /* flag_ocp_alarm_int_pol , */\
+{ 0x2960, "INTPOLCLKS"}, /* flag_clocks_stable_int_pol , */\
+{ 0x2970, "INTPOLCLIPS"}, /* flag_clip_int_pol , */\
+{ 0x2980, "INTPOLMTPB"}, /* mtp_busy_int_pol , */\
+{ 0x2990, "INTPOLNOCLK"}, /* flag_lost_clk_int_pol , */\
+{ 0x29a0, "INTPOLSPKS"}, /* flag_cf_speakererror_int_pol , */\
+{ 0x29b0, "INTPOLACS"}, /* flag_cold_started_int_pol , */\
+{ 0x29c0, "INTPOLSWS"}, /* flag_engage_int_pol , */\
+{ 0x29d0, "INTPOLWDS"}, /* flag_watchdog_reset_int_pol , */\
+{ 0x29e0, "INTPOLAMPS"}, /* flag_enbl_amp_int_pol , */\
+{ 0x29f0, "INTPOLAREFS"}, /* flag_enbl_ref_int_pol , */\
+{ 0x2b01, "INTPOLACK"}, /* Interrupt status flags polarity register , */\
+{ 0x4900, "CLIP"}, /* Bypass clip control , */\
+{ 0x62b0, "CIMTP"}, /* start copying all the data from i2cregs_mtp
+ * to mtp [Key 2 protected], */\
+{ 0x7000, "RST"}, /* Reset CoolFlux DSP , */\
+{ 0x7011, "DMEM"}, /* Target memory for access , */\
+{ 0x7030, "AIF"}, /* Autoincrement-flag for memory-address , */\
+{ 0x7040, "CFINT"}, /* Interrupt CoolFlux DSP , */\
+{ 0x7087, "REQ"}, /* request for access (8 channels) , */\
+{ 0x7080, "REQCMD"}, /* Firmware event request rpc command , */\
+{ 0x7090, "REQRST"}, /* Firmware event request reset restart , */\
+{ 0x70a0, "REQMIPS"}, /* Firmware event request short on mips , */\
+{ 0x70b0, "REQMUTED"}, /* Firmware event request mute sequence ready , */\
+{ 0x70c0, "REQVOL"}, /* Firmware event request volume ready , */\
+{ 0x70d0, "REQDMG"}, /* Firmware event request speaker damage detected , */\
+{ 0x70e0, "REQCAL"}, /* Firmware event request calibration completed , */\
+{ 0x70f0, "REQRSV"}, /* Firmware event request reserved , */\
+{ 0x710f, "MADD"}, /* memory-address to be accessed , */\
+{ 0x720f, "MEMA"}, /* activate memory access (24- or 32-bits data is
+ * written/read to/from memory, */\
+{ 0x7307, "ERR"}, /* Coolflux error flags , */\
+{ 0x7387, "ACK"}, /* acknowledge of requests (8 channels) , */\
+{ 0x7380, "ACKCMD"}, /* Firmware event acknowledge rpc command , */\
+{ 0x7390, "ACKRST"}, /* Firmware event acknowledge reset restart , */\
+{ 0x73a0, "ACKMIPS"}, /* Firmware event acknowledge short on mips , */\
+{ 0x73b0, "ACKMUTED"}, /* Firmware event acknowledge mute sequence ready,*/\
+{ 0x73c0, "ACKVOL"}, /* Firmware event acknowledge volume ready ,*/\
+{ 0x73d0, "ACKDMG"}, /* Firmware event acknowledge speaker
+ * damage detected,*/\
+{ 0x73e0, "ACKCAL"}, /* Firmware event acknowledge calibration completed,*/\
+{ 0x73f0, "ACKRSV"}, /* Firmware event acknowledge reserved ,*/\
+{ 0x8000, "MTPOTC"}, /* Calibration schedule (key2 protected) ,*/\
+{ 0x8010, "MTPEX"}, /* (key2 protected) ,*/\
+{ 0x8045, "SWPROFIL" },\
+{ 0x80a5, "SWVSTEP" },\
+{ 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+
+#define TFA1_BITNAMETABLE static tfaBfName_t Tfa1BitNames[] = {\
+{ 0x0, "flag_por"}, /* Power-on-reset flag , */\
+{ 0x10, "flag_pll_lock"}, /* PLL lock , */\
+{ 0x20, "flag_otpok"}, /* Over Temperature Protection alarm , */\
+{ 0x30, "flag_ovpok"}, /* Over Voltage Protection alarm , */\
+{ 0x40, "flag_uvpok"}, /* Under Voltage Protection alarm , */\
+{ 0x50, "flag_ocp_alarm"}, /* Over Current Protection alarm , */\
+{ 0x60, "flag_clocks_stable"}, /* Clocks stable flag , */\
+{ 0x70, "flag_clip"}, /* Amplifier clipping , */\
+{ 0x80, "mtp_busy"}, /* MTP busy , */\
+{ 0x90, "flag_lost_clk"}, /* Flag lost clock from clock generation unit , */\
+{ 0xa0, "flag_cf_speakererror"}, /* Speaker error flag , */\
+{ 0xb0, "flag_cold_started"}, /* Cold Start flag , */\
+{ 0xc0, "flag_engage"}, /* Flag Engage , */\
+{ 0xd0, "flag_watchdog_reset"}, /* Flag watchdog reset , */\
+{ 0xe0, "flag_enbl_amp"}, /* Amplifier is enabled by manager , */\
+{ 0xf0, "flag_enbl_ref"}, /* References are enabled by manager , */\
+{ 0x109, "bat_adc"}, /* Battery voltage readout; 0 .. 5.5 [V] , */\
+{ 0x208, "temp_adc"}, /* Temperature readout from the temperature sensor , */\
+{ 0x30b, "rev_reg"}, /* Device type number is B97 , */\
+{ 0x420, "ctrl_rcv"}, /* Enable Receiver Mode , */\
+{ 0x431, "chan_sel"}, /* Channel Selection TDM input for Coolflux , */\
+{ 0x450, "input_level"}, /* Input level selection control , */\
+{ 0x461, "vamp_sel"}, /* Input selection for amplifier , */\
+{ 0x4c3, "audio_fs"}, /* Audio sample rate setting , */\
+{ 0x501, "vbat_prot_attacktime"}, /* Protection Attack Time , */\
+{ 0x523, "vbat_prot_thlevel"}, /* ProtectionThreshold , */\
+{ 0x561, "vbat_prot_max_reduct"}, /* Protection Maximum Reduction , */\
+{ 0x582, "vbat_prot_release_t"}, /* Battery Protection Release Time , */\
+{ 0x5b1, "vbat_prot_hysterese"}, /* Battery Protection Hysteresis , */\
+{ 0x5d0, "reset_min_vbat"}, /* reset clipper , */\
+{ 0x5e0, "sel_vbat"}, /* battery voltage for I2C read out only , */\
+{ 0x5f0, "bypass_clipper"}, /* bypass clipper battery protection , */\
+{ 0x600, "dpsa"}, /* Enable dynamic powerstage activation , */\
+{ 0x650, "cf_mute"}, /* Soft mute in CoolFlux , */\
+{ 0x670, "batsense_steepness"}, /* BatSenseSteepness , */\
+{ 0x687, "vol"}, /* volume control (in CoolFlux) , */\
+{ 0x702, "boost_volt"}, /* Boost Voltage , */\
+{ 0x733, "boost_cur"}, /* Max boost coil current - step of 175 mA , */\
+{ 0x7a0, "boost_intel"}, /* Adaptive boost mode , */\
+{ 0x7b0, "boost_speed"}, /* Soft RampUp/Down mode for DCDC controller , */\
+{ 0x7c0, "boost_peak2avg"}, /* ctrl_peak2avg for analog part of DCDC , */\
+{ 0x800, "ext_temp_sel"}, /* Select external temperature also the ext_temp will be put on the temp read out , */\
+{ 0x818, "ext_temp"}, /* external temperature setting to be given by host , */\
+{ 0x8b2, "dcdc_synchronisation"}, /* DCDC synchronisation off + 7 positions , */\
+{ 0x900, "powerdown"}, /* Device Mode , */\
+{ 0x910, "reset"}, /* I2C Reset , */\
+{ 0x920, "enbl_coolflux"}, /* Enable CoolFlux , */\
+{ 0x930, "enbl_amplifier"}, /* Enable Amplifier , */\
+{ 0x940, "enbl_boost"}, /* EnableBoost , */\
+{ 0x950, "coolflux_configured"}, /* Coolflux configured , */\
+{ 0x960, "sel_enbl_amplifier"}, /* Selection on how Amplifier is enabled , */\
+{ 0x970, "dcdcoff_mode"}, /* DCDC not connected , */\
+{ 0x980, "iddqtest"}, /* IDDQ test amplifier , */\
+{ 0x991, "coil_value"}, /* Coil Value , */\
+{ 0x9b0, "sel_cf_clock"}, /* Selection CoolFlux Clock , */\
+{ 0x9c1, "int_pad_io"}, /* INT pad configuration control , */\
+{ 0x9e0, "sel_fs_bck"}, /* PLL input reference clock selection , */\
+{ 0x9f0, "sel_scl_cf_clock"}, /* Coolflux sub-system clock , */\
+{ 0xb07, "mtpkey2"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
+{ 0xc00, "enbl_volt_sense"}, /* Voltage sense enabling control bit , */\
+{ 0xc10, "vsense_pwm_sel"}, /* Voltage sense PWM source selection control , */\
+{ 0xc25, "vi_frac_delay"}, /* Fractional delay adjustment between current and voltage sense, */\
+{ 0xc80, "sel_voltsense_out"}, /* TDM output data selection control , */\
+{ 0xc90, "vsense_bypass_avg"}, /* Voltage Sense Average Block Bypass , */\
+{ 0xd05, "cf_frac_delay"}, /* Fractional delay adjustment between current and voltage sense by firmware, */\
+{ 0xe00, "bypass_dcdc_curr_prot"}, /* Control to switch off dcdc current reduction with bat protection, */\
+{ 0xe80, "disable_clock_sh_prot"}, /* disable clock_sh protection , */\
+{ 0xe96, "reserve_reg_1_15_9"}, /* , */\
+{ 0x1011, "tdm_usecase"}, /* TDM_usecase , */\
+{ 0x1030, "tdm_enable"}, /* TDM interface control , */\
+{ 0x1040, "tdm_clk_inversion"}, /* TDM clock inversion , */\
+{ 0x1053, "tdm_fs_ws_length"}, /* TDM FS length , */\
+{ 0x1090, "tdm_fs_ws_polarity"}, /* TDM FS polarity , */\
+{ 0x10a4, "tdm_sample_size"}, /* TDM Sample Size for all tdm sinks/sources , */\
+{ 0x1103, "tdm_nb_of_slots"}, /* Number of slots , */\
+{ 0x1144, "tdm_slot_length"}, /* Slot length , */\
+{ 0x1194, "tdm_bits_remaining"}, /* Bits remaining , */\
+{ 0x11e0, "tdm_data_delay"}, /* Data delay , */\
+{ 0x11f0, "tdm_data_adjustment"}, /* Data adjustment , */\
+{ 0x1201, "tdm_txdata_format"}, /* TXDATA format , */\
+{ 0x1221, "tdm_txdata_format_unused_slot_sd0"}, /* TXDATA format unused slot sd0 , */\
+{ 0x1241, "tdm_txdata_format_unused_slot_sd1"}, /* TXDATA format unused slot sd1 , */\
+{ 0x1270, "tdm_sink0_enable"}, /* TDM sink0 enable , */\
+{ 0x1280, "tdm_sink1_enable"}, /* TDM sink1 enable , */\
+{ 0x1290, "tdm_sink2_enable"}, /* TDM sink2 enable , */\
+{ 0x12a0, "tdm_source0_enable"}, /* TDM source0 enable , */\
+{ 0x12b0, "tdm_source1_enable"}, /* TDM source1 enable , */\
+{ 0x12c0, "tdm_source2_enable"}, /* TDM source2 enable , */\
+{ 0x12d0, "tdm_sink0_io"}, /* tdm_sink0_io , */\
+{ 0x12e0, "tdm_sink1_io"}, /* tdm_sink1_io , */\
+{ 0x12f0, "tdm_sink2_io"}, /* tdm_sink2_io , */\
+{ 0x1300, "tdm_source0_io"}, /* tdm_source0_io , */\
+{ 0x1310, "tdm_source1_io"}, /* tdm_source1_io , */\
+{ 0x1320, "tdm_source2_io"}, /* tdm_source2_io , */\
+{ 0x1333, "tdm_sink0_slot"}, /* sink0_slot [GAIN IN] , */\
+{ 0x1373, "tdm_sink1_slot"}, /* sink1_slot [CH1 IN] , */\
+{ 0x13b3, "tdm_sink2_slot"}, /* sink2_slot [CH2 IN] , */\
+{ 0x1403, "tdm_source0_slot"}, /* source0_slot [GAIN OUT] , */\
+{ 0x1443, "tdm_source1_slot"}, /* source1_slot [Voltage Sense] , */\
+{ 0x1483, "tdm_source2_slot"}, /* source2_slot [Current Sense] , */\
+{ 0x14c3, "tdm_nbck"}, /* NBCK , */\
+{ 0x1500, "flag_tdm_lut_error"}, /* TDM LUT error flag , */\
+{ 0x1512, "flag_tdm_status"}, /* TDM interface status bits , */\
+{ 0x1540, "flag_tdm_error"}, /* TDM interface error indicator , */\
+{ 0x2000, "flag_por_int_out"}, /* flag_por_int_out , */\
+{ 0x2010, "flag_pll_lock_int_out"}, /* flag_pll_lock_int_out , */\
+{ 0x2020, "flag_otpok_int_out"}, /* flag_otpok_int_out , */\
+{ 0x2030, "flag_ovpok_int_out"}, /* flag_ovpok_int_out , */\
+{ 0x2040, "flag_uvpok_int_out"}, /* flag_uvpok_int_out , */\
+{ 0x2050, "flag_ocp_alarm_int_out"}, /* flag_ocp_alarm_int_out , */\
+{ 0x2060, "flag_clocks_stable_int_out"}, /* flag_clocks_stable_int_out , */\
+{ 0x2070, "flag_clip_int_out"}, /* flag_clip_int_out , */\
+{ 0x2080, "mtp_busy_int_out"}, /* mtp_busy_int_out , */\
+{ 0x2090, "flag_lost_clk_int_out"}, /* flag_lost_clk_int_out , */\
+{ 0x20a0, "flag_cf_speakererror_int_out"}, /* flag_cf_speakererror_int_out , */\
+{ 0x20b0, "flag_cold_started_int_out"}, /* flag_cold_started_int_out , */\
+{ 0x20c0, "flag_engage_int_out"}, /* flag_engage_int_out , */\
+{ 0x20d0, "flag_watchdog_reset_int_out"}, /* flag_watchdog_reset_int_out , */\
+{ 0x20e0, "flag_enbl_amp_int_out"}, /* flag_enbl_amp_int_out , */\
+{ 0x20f0, "flag_enbl_ref_int_out"}, /* flag_enbl_ref_int_out , */\
+{ 0x2100, "flag_voutcomp_int_out"}, /* flag_voutcomp_int_out , */\
+{ 0x2110, "flag_voutcomp93_int_out"}, /* flag_voutcomp93_int_out , */\
+{ 0x2120, "flag_voutcomp86_int_out"}, /* flag_voutcomp86_int_out , */\
+{ 0x2130, "flag_hiz_int_out"}, /* flag_hiz_int_out , */\
+{ 0x2140, "flag_ocpokbst_int_out"}, /* flag_ocpokbst_int_out , */\
+{ 0x2150, "flag_peakcur_int_out"}, /* flag_peakcur_int_out , */\
+{ 0x2160, "flag_ocpokap_int_out"}, /* flag_ocpokap_int_out , */\
+{ 0x2170, "flag_ocpokan_int_out"}, /* flag_ocpokan_int_out , */\
+{ 0x2180, "flag_ocpokbp_int_out"}, /* flag_ocpokbp_int_out , */\
+{ 0x2190, "flag_ocpokbn_int_out"}, /* flag_ocpokbn_int_out , */\
+{ 0x21a0, "flag_adc10_ready_int_out"}, /* flag_adc10_ready_int_out , */\
+{ 0x21b0, "flag_clipa_high_int_out"}, /* flag_clipa_high_int_out , */\
+{ 0x21c0, "flag_clipa_low_int_out"}, /* flag_clipa_low_int_out , */\
+{ 0x21d0, "flag_clipb_high_int_out"}, /* flag_clipb_high_int_out , */\
+{ 0x21e0, "flag_clipb_low_int_out"}, /* flag_clipb_low_int_out , */\
+{ 0x21f0, "flag_tdm_error_int_out"}, /* flag_tdm_error_int_out , */\
+{ 0x2201, "interrupt_out3"}, /* Interrupt status register output - Corresponding flag, */\
+{ 0x2300, "flag_por_int_in"}, /* flag_por_int_in , */\
+{ 0x2310, "flag_pll_lock_int_in"}, /* flag_pll_lock_int_in , */\
+{ 0x2320, "flag_otpok_int_in"}, /* flag_otpok_int_in , */\
+{ 0x2330, "flag_ovpok_int_in"}, /* flag_ovpok_int_in , */\
+{ 0x2340, "flag_uvpok_int_in"}, /* flag_uvpok_int_in , */\
+{ 0x2350, "flag_ocp_alarm_int_in"}, /* flag_ocp_alarm_int_in , */\
+{ 0x2360, "flag_clocks_stable_int_in"}, /* flag_clocks_stable_int_in , */\
+{ 0x2370, "flag_clip_int_in"}, /* flag_clip_int_in , */\
+{ 0x2380, "mtp_busy_int_in"}, /* mtp_busy_int_in , */\
+{ 0x2390, "flag_lost_clk_int_in"}, /* flag_lost_clk_int_in , */\
+{ 0x23a0, "flag_cf_speakererror_int_in"}, /* flag_cf_speakererror_int_in , */\
+{ 0x23b0, "flag_cold_started_int_in"}, /* flag_cold_started_int_in , */\
+{ 0x23c0, "flag_engage_int_in"}, /* flag_engage_int_in , */\
+{ 0x23d0, "flag_watchdog_reset_int_in"}, /* flag_watchdog_reset_int_in , */\
+{ 0x23e0, "flag_enbl_amp_int_in"}, /* flag_enbl_amp_int_in , */\
+{ 0x23f0, "flag_enbl_ref_int_in"}, /* flag_enbl_ref_int_in , */\
+{ 0x2400, "flag_voutcomp_int_in"}, /* flag_voutcomp_int_in , */\
+{ 0x2410, "flag_voutcomp93_int_in"}, /* flag_voutcomp93_int_in , */\
+{ 0x2420, "flag_voutcomp86_int_in"}, /* flag_voutcomp86_int_in , */\
+{ 0x2430, "flag_hiz_int_in"}, /* flag_hiz_int_in , */\
+{ 0x2440, "flag_ocpokbst_int_in"}, /* flag_ocpokbst_int_in , */\
+{ 0x2450, "flag_peakcur_int_in"}, /* flag_peakcur_int_in , */\
+{ 0x2460, "flag_ocpokap_int_in"}, /* flag_ocpokap_int_in , */\
+{ 0x2470, "flag_ocpokan_int_in"}, /* flag_ocpokan_int_in , */\
+{ 0x2480, "flag_ocpokbp_int_in"}, /* flag_ocpokbp_int_in , */\
+{ 0x2490, "flag_ocpokbn_int_in"}, /* flag_ocpokbn_int_in , */\
+{ 0x24a0, "flag_adc10_ready_int_in"}, /* flag_adc10_ready_int_in , */\
+{ 0x24b0, "flag_clipa_high_int_in"}, /* flag_clipa_high_int_in , */\
+{ 0x24c0, "flag_clipa_low_int_in"}, /* flag_clipa_low_int_in , */\
+{ 0x24d0, "flag_clipb_high_int_in"}, /* flag_clipb_high_int_in , */\
+{ 0x24e0, "flag_clipb_low_int_in"}, /* flag_clipb_low_int_in , */\
+{ 0x24f0, "flag_tdm_error_int_in"}, /* flag_tdm_error_int_in , */\
+{ 0x2501, "interrupt_in3"}, /* Interrupt register input , */\
+{ 0x2600, "flag_por_int_enable"}, /* flag_por_int_enable , */\
+{ 0x2610, "flag_pll_lock_int_enable"}, /* flag_pll_lock_int_enable , */\
+{ 0x2620, "flag_otpok_int_enable"}, /* flag_otpok_int_enable , */\
+{ 0x2630, "flag_ovpok_int_enable"}, /* flag_ovpok_int_enable , */\
+{ 0x2640, "flag_uvpok_int_enable"}, /* flag_uvpok_int_enable , */\
+{ 0x2650, "flag_ocp_alarm_int_enable"}, /* flag_ocp_alarm_int_enable , */\
+{ 0x2660, "flag_clocks_stable_int_enable"}, /* flag_clocks_stable_int_enable , */\
+{ 0x2670, "flag_clip_int_enable"}, /* flag_clip_int_enable , */\
+{ 0x2680, "mtp_busy_int_enable"}, /* mtp_busy_int_enable , */\
+{ 0x2690, "flag_lost_clk_int_enable"}, /* flag_lost_clk_int_enable , */\
+{ 0x26a0, "flag_cf_speakererror_int_enable"}, /* flag_cf_speakererror_int_enable , */\
+{ 0x26b0, "flag_cold_started_int_enable"}, /* flag_cold_started_int_enable , */\
+{ 0x26c0, "flag_engage_int_enable"}, /* flag_engage_int_enable , */\
+{ 0x26d0, "flag_watchdog_reset_int_enable"}, /* flag_watchdog_reset_int_enable , */\
+{ 0x26e0, "flag_enbl_amp_int_enable"}, /* flag_enbl_amp_int_enable , */\
+{ 0x26f0, "flag_enbl_ref_int_enable"}, /* flag_enbl_ref_int_enable , */\
+{ 0x2700, "flag_voutcomp_int_enable"}, /* flag_voutcomp_int_enable , */\
+{ 0x2710, "flag_voutcomp93_int_enable"}, /* flag_voutcomp93_int_enable , */\
+{ 0x2720, "flag_voutcomp86_int_enable"}, /* flag_voutcomp86_int_enable , */\
+{ 0x2730, "flag_hiz_int_enable"}, /* flag_hiz_int_enable , */\
+{ 0x2740, "flag_ocpokbst_int_enable"}, /* flag_ocpokbst_int_enable , */\
+{ 0x2750, "flag_peakcur_int_enable"}, /* flag_peakcur_int_enable , */\
+{ 0x2760, "flag_ocpokap_int_enable"}, /* flag_ocpokap_int_enable , */\
+{ 0x2770, "flag_ocpokan_int_enable"}, /* flag_ocpokan_int_enable , */\
+{ 0x2780, "flag_ocpokbp_int_enable"}, /* flag_ocpokbp_int_enable , */\
+{ 0x2790, "flag_ocpokbn_int_enable"}, /* flag_ocpokbn_int_enable , */\
+{ 0x27a0, "flag_adc10_ready_int_enable"}, /* flag_adc10_ready_int_enable , */\
+{ 0x27b0, "flag_clipa_high_int_enable"}, /* flag_clipa_high_int_enable , */\
+{ 0x27c0, "flag_clipa_low_int_enable"}, /* flag_clipa_low_int_enable , */\
+{ 0x27d0, "flag_clipb_high_int_enable"}, /* flag_clipb_high_int_enable , */\
+{ 0x27e0, "flag_clipb_low_int_enable"}, /* flag_clipb_low_int_enable , */\
+{ 0x27f0, "flag_tdm_error_int_enable"}, /* flag_tdm_error_int_enable , */\
+{ 0x2801, "interrupt_enable3"}, /* Interrupt enable register , */\
+{ 0x2900, "flag_por_int_pol"}, /* flag_por_int_pol , */\
+{ 0x2910, "flag_pll_lock_int_pol"}, /* flag_pll_lock_int_pol , */\
+{ 0x2920, "flag_otpok_int_pol"}, /* flag_otpok_int_pol , */\
+{ 0x2930, "flag_ovpok_int_pol"}, /* flag_ovpok_int_pol , */\
+{ 0x2940, "flag_uvpok_int_pol"}, /* flag_uvpok_int_pol , */\
+{ 0x2950, "flag_ocp_alarm_int_pol"}, /* flag_ocp_alarm_int_pol , */\
+{ 0x2960, "flag_clocks_stable_int_pol"}, /* flag_clocks_stable_int_pol , */\
+{ 0x2970, "flag_clip_int_pol"}, /* flag_clip_int_pol , */\
+{ 0x2980, "mtp_busy_int_pol"}, /* mtp_busy_int_pol , */\
+{ 0x2990, "flag_lost_clk_int_pol"}, /* flag_lost_clk_int_pol , */\
+{ 0x29a0, "flag_cf_speakererror_int_pol"}, /* flag_cf_speakererror_int_pol , */\
+{ 0x29b0, "flag_cold_started_int_pol"}, /* flag_cold_started_int_pol , */\
+{ 0x29c0, "flag_engage_int_pol"}, /* flag_engage_int_pol , */\
+{ 0x29d0, "flag_watchdog_reset_int_pol"}, /* flag_watchdog_reset_int_pol , */\
+{ 0x29e0, "flag_enbl_amp_int_pol"}, /* flag_enbl_amp_int_pol , */\
+{ 0x29f0, "flag_enbl_ref_int_pol"}, /* flag_enbl_ref_int_pol , */\
+{ 0x2a00, "flag_voutcomp_int_pol"}, /* flag_voutcomp_int_pol , */\
+{ 0x2a10, "flag_voutcomp93_int_pol"}, /* flag_voutcomp93_int_pol , */\
+{ 0x2a20, "flag_voutcomp86_int_pol"}, /* flag_voutcomp86_int_pol , */\
+{ 0x2a30, "flag_hiz_int_pol"}, /* flag_hiz_int_pol , */\
+{ 0x2a40, "flag_ocpokbst_int_pol"}, /* flag_ocpokbst_int_pol , */\
+{ 0x2a50, "flag_peakcur_int_pol"}, /* flag_peakcur_int_pol , */\
+{ 0x2a60, "flag_ocpokap_int_pol"}, /* flag_ocpokap_int_pol , */\
+{ 0x2a70, "flag_ocpokan_int_pol"}, /* flag_ocpokan_int_pol , */\
+{ 0x2a80, "flag_ocpokbp_int_pol"}, /* flag_ocpokbp_int_pol , */\
+{ 0x2a90, "flag_ocpokbn_int_pol"}, /* flag_ocpokbn_int_pol , */\
+{ 0x2aa0, "flag_adc10_ready_int_pol"}, /* flag_adc10_ready_int_pol , */\
+{ 0x2ab0, "flag_clipa_high_int_pol"}, /* flag_clipa_high_int_pol , */\
+{ 0x2ac0, "flag_clipa_low_int_pol"}, /* flag_clipa_low_int_pol , */\
+{ 0x2ad0, "flag_clipb_high_int_pol"}, /* flag_clipb_high_int_pol , */\
+{ 0x2ae0, "flag_clipb_low_int_pol"}, /* flag_clipb_low_int_pol , */\
+{ 0x2af0, "flag_tdm_error_int_pol"}, /* flag_tdm_error_int_pol , */\
+{ 0x2b01, "status_polarity3"}, /* Interrupt status flags polarity register , */\
+{ 0x3000, "flag_voutcomp"}, /* flag_voutcomp, indication Vset is larger than Vbat, */\
+{ 0x3010, "flag_voutcomp93"}, /* flag_voutcomp93, indication Vset is larger than 1.07* Vbat, */\
+{ 0x3020, "flag_voutcomp86"}, /* flag_voutcomp86, indication Vset is larger than 1.14* Vbat, */\
+{ 0x3030, "flag_hiz"}, /* flag_hiz, indication Vbst is larger than Vbat , */\
+{ 0x3040, "flag_ocpokbst"}, /* flag_ocpokbst, indication no over current in boost converter pmos switch, */\
+{ 0x3050, "flag_peakcur"}, /* flag_peakcur, indication current is max in dcdc converter, */\
+{ 0x3060, "flag_ocpokap"}, /* flag_ocpokap, indication no over current in amplifier "a" pmos output stage, */\
+{ 0x3070, "flag_ocpokan"}, /* flag_ocpokan, indication no over current in amplifier "a" nmos output stage, */\
+{ 0x3080, "flag_ocpokbp"}, /* flag_ocpokbp, indication no over current in amplifier "b" pmos output stage, */\
+{ 0x3090, "flag_ocpokbn"}, /* flag_ocpokbn, indication no over current in amplifier"b" nmos output stage, */\
+{ 0x30a0, "flag_adc10_ready"}, /* flag_adc10_ready, indication adc10 is ready , */\
+{ 0x30b0, "flag_clipa_high"}, /* flag_clipa_high, indication pmos amplifier "a" is clipping, */\
+{ 0x30c0, "flag_clipa_low"}, /* flag_clipa_low, indication nmos amplifier "a" is clipping, */\
+{ 0x30d0, "flag_clipb_high"}, /* flag_clipb_high, indication pmos amplifier "b" is clipping, */\
+{ 0x30e0, "flag_clipb_low"}, /* flag_clipb_low, indication nmos amplifier "b" is clipping, */\
+{ 0x310f, "mtp_man_data_out"}, /* single word read from MTP (manual copy) , */\
+{ 0x3200, "key01_locked"}, /* key01_locked, indication key 1 is locked , */\
+{ 0x3210, "key02_locked"}, /* key02_locked, indication key 2 is locked , */\
+{ 0x3225, "mtp_ecc_tcout"}, /* mtp_ecc_tcout , */\
+{ 0x3280, "mtpctrl_valid_test_rd"}, /* mtp test readout for read , */\
+{ 0x3290, "mtpctrl_valid_test_wr"}, /* mtp test readout for write , */\
+{ 0x32a0, "flag_in_alarm_state"}, /* Alarm state , */\
+{ 0x32b0, "mtp_ecc_err2"}, /* two or more bit errors detected in MTP, can not reconstruct value, */\
+{ 0x32c0, "mtp_ecc_err1"}, /* one bit error detected in MTP, reconstructed value, */\
+{ 0x32d0, "mtp_mtp_hvf"}, /* high voltage ready flag for MTP , */\
+{ 0x32f0, "mtp_zero_check_fail"}, /* zero check failed (tbd) for MTP , */\
+{ 0x3309, "data_adc10_tempbat"}, /* data_adc10_tempbat[9;0], adc 10 data output for testing, */\
+{ 0x400f, "hid_code"}, /* 5A6Bh, 23147d to access registers (Default for engineering), */\
+{ 0x4100, "bypass_hp"}, /* Bypass_High Pass Filter , */\
+{ 0x4110, "hard_mute"}, /* Hard Mute , */\
+{ 0x4120, "soft_mute"}, /* Soft Mute , */\
+{ 0x4134, "pwm_delay"}, /* PWM DelayBits to set the delay , */\
+{ 0x4180, "pwm_shape"}, /* PWM Shape , */\
+{ 0x4190, "pwm_bitlength"}, /* PWM Bitlength in noise shaper , */\
+{ 0x4203, "drive"}, /* Drive bits to select amount of power stage amplifier, */\
+{ 0x4240, "reclock_pwm"}, /* , */\
+{ 0x4250, "reclock_voltsense"}, /* , */\
+{ 0x4281, "dpsalevel"}, /* DPSA Threshold level , */\
+{ 0x42a1, "dpsa_release"}, /* DPSA Release time , */\
+{ 0x42c0, "coincidence"}, /* Prevent simultaneously switching of output stage , */\
+{ 0x42d0, "kickback"}, /* Prevent double pulses of output stage , */\
+{ 0x4306, "drivebst"}, /* Drive bits to select the powertransistor sections boost converter, */\
+{ 0x43a0, "ocptestbst"}, /* Boost OCP. For old ocp (ctrl_reversebst is 0);For new ocp (ctrl_reversebst is 1);, */\
+{ 0x43d0, "test_abistfft_enbl"}, /* FFT coolflux , */\
+{ 0x43f0, "test_bcontrol"}, /* test _bcontrol , */\
+{ 0x4400, "reversebst"}, /* OverCurrent Protection selection of power stage boost converter, */\
+{ 0x4410, "sensetest"}, /* Test option for the sense NMOS in booster for current mode control., */\
+{ 0x4420, "enbl_engagebst"}, /* Enable power stage dcdc controller , */\
+{ 0x4470, "enbl_slopecur"}, /* Enable bit of max-current dac , */\
+{ 0x4480, "enbl_voutcomp"}, /* Enable vout comparators , */\
+{ 0x4490, "enbl_voutcomp93"}, /* Enable vout-93 comparators , */\
+{ 0x44a0, "enbl_voutcomp86"}, /* Enable vout-86 comparators , */\
+{ 0x44b0, "enbl_hizcom"}, /* Enable hiz comparator , */\
+{ 0x44c0, "enbl_peakcur"}, /* Enable peak current , */\
+{ 0x44d0, "bypass_ovpglitch"}, /* Bypass OVP Glitch Filter , */\
+{ 0x44e0, "enbl_windac"}, /* Enable window dac , */\
+{ 0x44f0, "enbl_powerbst"}, /* Enable line of the powerstage , */\
+{ 0x4507, "ocp_thr"}, /* ocp_thr threshold level for OCP , */\
+{ 0x4580, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
+{ 0x4590, "bypass_ovp"}, /* Bypass OVP , */\
+{ 0x45a0, "bypass_uvp"}, /* Bypass UVP , */\
+{ 0x45b0, "bypass_otp"}, /* Bypass OTP , */\
+{ 0x45c0, "bypass_ocp"}, /* Bypass OCP , */\
+{ 0x45d0, "bypass_ocpcounter"}, /* BypassOCPCounter , */\
+{ 0x45e0, "bypass_lost_clk"}, /* Bypasslost_clk detector , */\
+{ 0x45f0, "vpalarm"}, /* vpalarm (uvp ovp handling) , */\
+{ 0x4600, "bypass_gc"}, /* bypass_gc, bypasses the CS gain correction , */\
+{ 0x4610, "cs_gain_control"}, /* gain control by means of MTP or i2c; 0 is MTP , */\
+{ 0x4627, "cs_gain"}, /* + / - 128 steps in steps of 1/4 percent 2's compliment, */\
+{ 0x46a0, "bypass_lp"}, /* bypass Low-Pass filter in temperature sensor , */\
+{ 0x46b0, "bypass_pwmcounter"}, /* bypass_pwmcounter , */\
+{ 0x46c0, "cs_negfixed"}, /* does not switch to neg , */\
+{ 0x46d2, "cs_neghyst"}, /* switches to neg depending on level , */\
+{ 0x4700, "switch_fb"}, /* switch_fb , */\
+{ 0x4713, "se_hyst"}, /* se_hyst , */\
+{ 0x4754, "se_level"}, /* se_level , */\
+{ 0x47a5, "ktemp"}, /* temperature compensation trimming , */\
+{ 0x4800, "cs_negin"}, /* negin , */\
+{ 0x4810, "cs_sein"}, /* cs_sein , */\
+{ 0x4820, "cs_coincidence"}, /* Coincidence current sense , */\
+{ 0x4830, "iddqtestbst"}, /* for iddq testing in powerstage of boost convertor , */\
+{ 0x4840, "coincidencebst"}, /* Switch protection on to prevent simultaneously switching power stages bst and amp, */\
+{ 0x4876, "delay_se_neg"}, /* delay of se and neg , */\
+{ 0x48e1, "cs_ttrack"}, /* sample & hold track time , */\
+{ 0x4900, "bypass_clip"}, /* Bypass clip control , */\
+{ 0x4920, "cf_cgate_off"}, /* to disable clock gating in the coolflux , */\
+{ 0x4940, "clipfast"}, /* clock switch for battery protection clipper, it switches back to old frequency, */\
+{ 0x4950, "cs_8ohm"}, /* 8 ohm mode for current sense (gain mode) , */\
+{ 0x4974, "delay_clock_sh"}, /* delay_sh, tunes S7H delay , */\
+{ 0x49c0, "inv_clksh"}, /* Invert the sample/hold clock for current sense ADC, */\
+{ 0x49d0, "inv_neg"}, /* Invert neg signal , */\
+{ 0x49e0, "inv_se"}, /* Invert se signal , */\
+{ 0x49f0, "setse"}, /* switches between Single Ende and differential mode; 1 is single ended, */\
+{ 0x4a12, "adc10_sel"}, /* select the input to convert the 10b ADC , */\
+{ 0x4a60, "adc10_reset"}, /* Global asynchronous reset (active HIGH) 10 bit ADC, */\
+{ 0x4a81, "adc10_test"}, /* Test mode selection signal 10 bit ADC , */\
+{ 0x4aa0, "bypass_lp_vbat"}, /* lp filter in batt sensor , */\
+{ 0x4ae0, "dc_offset"}, /* switch offset control on/off, is decimator offset control, */\
+{ 0x4af0, "tsense_hibias"}, /* bit to set the biasing in temp sensor to high , */\
+{ 0x4b00, "adc13_iset"}, /* Micadc Setting of current consumption. Debug use only, */\
+{ 0x4b14, "adc13_gain"}, /* Micadc gain setting (2-compl) , */\
+{ 0x4b61, "adc13_slowdel"}, /* Micadc Delay setting for internal clock. Debug use only, */\
+{ 0x4b83, "adc13_offset"}, /* Micadc ADC offset setting , */\
+{ 0x4bc0, "adc13_bsoinv"}, /* Micadc bit stream output invert mode for test , */\
+{ 0x4bd0, "adc13_resonator_enable"}, /* Micadc Give extra SNR with less stability. Debug use only, */\
+{ 0x4be0, "testmicadc"}, /* Mux at input of MICADC for test purpose , */\
+{ 0x4c0f, "abist_offset"}, /* offset control for ABIST testing , */\
+{ 0x4d05, "windac"}, /* for testing direct control windac , */\
+{ 0x4dc3, "pwm_dcc_cnt"}, /* control pwm duty cycle when enbl_pwm_dcc is 1 , */\
+{ 0x4e04, "slopecur"}, /* for testing direct control slopecur , */\
+{ 0x4e50, "ctrl_dem"}, /* dyn element matching control, rest of codes are optional, */\
+{ 0x4ed0, "enbl_pwm_dcc"}, /* to enable direct control of pwm duty cycle , */\
+{ 0x5007, "gain"}, /* Gain setting of the gain multiplier , */\
+{ 0x5081, "sourceb"}, /* Set OUTB to , */\
+{ 0x50a1, "sourcea"}, /* Set OUTA to , */\
+{ 0x50c1, "sourcebst"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
+{ 0x50e0, "tdm_enable_loopback"}, /* TDM loopback test , */\
+{ 0x5104, "pulselengthbst"}, /* pulse length setting test input for boost converter, */\
+{ 0x5150, "bypasslatchbst"}, /* bypass_latch in boost converter , */\
+{ 0x5160, "invertbst"}, /* invert pwmbst test signal , */\
+{ 0x5174, "pulselength"}, /* pulse length setting test input for amplifier , */\
+{ 0x51c0, "bypasslatch"}, /* bypass_latch in PWM source selection module , */\
+{ 0x51d0, "invertb"}, /* invert pwmb test signal , */\
+{ 0x51e0, "inverta"}, /* invert pwma test signal , */\
+{ 0x51f0, "bypass_ctrlloop"}, /* bypass_ctrlloop bypasses the control loop of the amplifier, */\
+{ 0x5210, "test_rdsona"}, /* tbd for rdson testing , */\
+{ 0x5220, "test_rdsonb"}, /* tbd for rdson testing , */\
+{ 0x5230, "test_rdsonbst"}, /* tbd for rdson testing , */\
+{ 0x5240, "test_cvia"}, /* tbd for rdson testing , */\
+{ 0x5250, "test_cvib"}, /* tbd for rdson testing , */\
+{ 0x5260, "test_cvibst"}, /* tbd for rdson testing , */\
+{ 0x5306, "digimuxa_sel"}, /* DigimuxA input selection control (see Digimux list for details), */\
+{ 0x5376, "digimuxb_sel"}, /* DigimuxB input selection control (see Digimux list for details), */\
+{ 0x5400, "hs_mode"}, /* hs_mode, high speed mode I2C bus , */\
+{ 0x5412, "test_parametric_io"}, /* test_parametric_io for testing pads , */\
+{ 0x5440, "enbl_ringo"}, /* enbl_ringo, for test purpose to check with ringo , */\
+{ 0x5456, "digimuxc_sel"}, /* DigimuxC input selection control (see Digimux list for details), */\
+{ 0x54c0, "dio_ehs"}, /* Slew control for DIO in output mode , */\
+{ 0x54d0, "gainio_ehs"}, /* Slew control for GAINIO in output mode , */\
+{ 0x550d, "enbl_amp"}, /* enbl_amp for testing to enable all analoge blocks in amplifier, */\
+{ 0x5600, "use_direct_ctrls"}, /* use_direct_ctrls, to overrule several functions direct for testing, */\
+{ 0x5610, "rst_datapath"}, /* rst_datapath, datapath reset , */\
+{ 0x5620, "rst_cgu"}, /* rst_cgu, cgu reset , */\
+{ 0x5637, "enbl_ref"}, /* for testing to enable all analoge blocks in references, */\
+{ 0x56b0, "enbl_engage"}, /* Enable output stage amplifier , */\
+{ 0x56c0, "use_direct_clk_ctrl"}, /* use_direct_clk_ctrl, to overrule several functions direct for testing, */\
+{ 0x56d0, "use_direct_pll_ctrl"}, /* use_direct_pll_ctrl, to overrule several functions direct for testing, */\
+{ 0x56e0, "use_direct_ctrls_2"}, /* use_direct_sourseamp_ctrls, to overrule several functions direct for testing, */\
+{ 0x5707, "anamux"}, /* Anamux control , */\
+{ 0x57c0, "ocptest"}, /* ctrl_ocptest, deactivates the over current protection in the power stages of the amplifier. The ocp flag signals stay active., */\
+{ 0x57e0, "otptest"}, /* otptest, test mode otp amplifier , */\
+{ 0x57f0, "reverse"}, /* 1: Normal mode, slope is controlled , */\
+{ 0x5813, "pll_selr"}, /* pll_selr , */\
+{ 0x5854, "pll_selp"}, /* pll_selp , */\
+{ 0x58a5, "pll_seli"}, /* pll_seli , */\
+{ 0x5950, "pll_mdec_msb"}, /* most significant bits of pll_mdec[16] , */\
+{ 0x5960, "pll_ndec_msb"}, /* most significant bits of pll_ndec[9] , */\
+{ 0x5970, "pll_frm"}, /* pll_frm , */\
+{ 0x5980, "pll_directi"}, /* pll_directi , */\
+{ 0x5990, "pll_directo"}, /* pll_directo , */\
+{ 0x59a0, "enbl_pll"}, /* enbl_pll , */\
+{ 0x59f0, "pll_bypass"}, /* pll_bypass , */\
+{ 0x5a0f, "tsig_freq"}, /* tsig_freq, internal sinus test generator, frequency control, */\
+{ 0x5b02, "tsig_freq_msb"}, /* select internal sinus test generator, frequency control msb bits, */\
+{ 0x5b30, "inject_tsig"}, /* inject_tsig, control bit to switch to internal sinus test generator, */\
+{ 0x5b44, "adc10_prog_sample"}, /* control ADC10 , */\
+{ 0x5c0f, "pll_mdec"}, /* bits 15..0 of pll_mdec[16;0] , */\
+{ 0x5d06, "pll_pdec"}, /* pll_pdec , */\
+{ 0x5d78, "pll_ndec"}, /* bits 8..0 of pll_ndec[9;0] , */\
+{ 0x6007, "mtpkey1"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
+{ 0x6185, "mtp_ecc_tcin"}, /* Mtp_ecc_tcin , */\
+{ 0x6203, "mtp_man_address_in"}, /* address from I2C regs for writing one word single mtp, */\
+{ 0x6260, "mtp_ecc_eeb"}, /* enable code bit generation (active low!) , */\
+{ 0x6270, "mtp_ecc_ecb"}, /* enable correction signal (active low!) , */\
+{ 0x6280, "man_copy_mtp_to_iic"}, /* start copying single word from mtp to i2cregs_mtp , */\
+{ 0x6290, "man_copy_iic_to_mtp"}, /* start copying single word from i2cregs_mtp to mtp [Key 1 protected], */\
+{ 0x62a0, "auto_copy_mtp_to_iic"}, /* start copying all the data from mtp to i2cregs_mtp, */\
+{ 0x62b0, "auto_copy_iic_to_mtp"}, /* start copying all the data from i2cregs_mtp to mtp [Key 2 protected], */\
+{ 0x62d2, "mtp_speed_mode"}, /* Speed mode , */\
+{ 0x6340, "mtp_direct_enable"}, /* mtp_direct_enable (key1 protected) , */\
+{ 0x6350, "mtp_direct_wr"}, /* mtp_direct_wr (key1 protected) , */\
+{ 0x6360, "mtp_direct_rd"}, /* mtp_direct_rd (key1 protected) , */\
+{ 0x6370, "mtp_direct_rst"}, /* mtp_direct_rst (key1 protected) , */\
+{ 0x6380, "mtp_direct_ers"}, /* mtp_direct_ers (key1 protected) , */\
+{ 0x6390, "mtp_direct_prg"}, /* mtp_direct_prg (key1 protected) , */\
+{ 0x63a0, "mtp_direct_epp"}, /* mtp_direct_epp (key1 protected) , */\
+{ 0x63b4, "mtp_direct_test"}, /* mtp_direct_test (key1 protected) , */\
+{ 0x640f, "mtp_man_data_in"}, /* single word to be written to MTP (manual copy) , */\
+{ 0x7000, "cf_rst_dsp"}, /* Reset CoolFlux DSP , */\
+{ 0x7011, "cf_dmem"}, /* Target memory for access , */\
+{ 0x7030, "cf_aif"}, /* Autoincrement-flag for memory-address , */\
+{ 0x7040, "cf_int"}, /* Interrupt CoolFlux DSP , */\
+{ 0x7087, "cf_req"}, /* request for access (8 channels) , */\
+{ 0x710f, "cf_madd"}, /* memory-address to be accessed , */\
+{ 0x720f, "cf_mema"}, /* activate memory access (24- or 32-bits data is written/read to/from memory, */\
+{ 0x7307, "cf_err"}, /* Coolflux error flags , */\
+{ 0x7387, "cf_ack"}, /* acknowledge of requests (8 channels) , */\
+{ 0x8000, "calibration_onetime"}, /* Calibration schedule (key2 protected) , */\
+{ 0x8010, "calibr_ron_done"}, /* (key2 protected) , */\
+{ 0x8105, "calibr_vout_offset"}, /* calibr_vout_offset (DCDCoffset) 2's compliment (key1 protected), */\
+{ 0x8163, "calibr_delta_gain"}, /* delta gain for vamp (alpha) 2's compliment (key1 protected), */\
+{ 0x81a5, "calibr_offs_amp"}, /* offset for vamp (Ampoffset) 2's compliment (key1 protected), */\
+{ 0x8207, "calibr_gain_cs"}, /* gain current sense (Imeasalpha) 2's compliment (key1 protected), */\
+{ 0x8284, "calibr_temp_offset"}, /* temperature offset 2's compliment (key1 protected), */\
+{ 0x82d2, "calibr_temp_gain"}, /* temperature gain 2's compliment (key1 protected) , */\
+{ 0x830f, "calibr_ron"}, /* Ron resistance of coil (key1 protected) , */\
+{ 0x8505, "type_bits_HW"}, /* Key1_Protected_MTP5 , */\
+{ 0x8601, "type_bits_1_0_SW"}, /* MTP-control SW , */\
+{ 0x8681, "type_bits_8_9_SW"}, /* MTP-control SW , */\
+{ 0x870f, "type_bits2_SW"}, /* MTP-control SW2 , */\
+{ 0x8806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
+{ 0x8870, "htol_iic_addr_en"}, /* HTOL_I2C_Address_Enable , */\
+{ 0x8881, "ctrl_ovp_response"}, /* OVP response control , */\
+{ 0x88a0, "disable_ovp_alarm_state"}, /* OVP alarm state control , */\
+{ 0x88b0, "enbl_stretch_ovp"}, /* OVP alram strech control , */\
+{ 0x88c0, "cf_debug_mode"}, /* Coolflux debug mode , */\
+{ 0x8a0f, "production_data1"}, /* (key1 protected) , */\
+{ 0x8b0f, "production_data2"}, /* (key1 protected) , */\
+{ 0x8c0f, "production_data3"}, /* (key1 protected) , */\
+{ 0x8d0f, "production_data4"}, /* (key1 protected) , */\
+{ 0x8e0f, "production_data5"}, /* (key1 protected) , */\
+{ 0x8f0f, "production_data6"}, /* (key1 protected) , */\
+{ 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+
+enum tfa1_irq {
+tfa1_irq_vdds = 0,
+tfa1_irq_plls = 1,
+tfa1_irq_ds = 2,
+tfa1_irq_vds = 3,
+tfa1_irq_uvds = 4,
+tfa1_irq_cds = 5,
+tfa1_irq_clks = 6,
+tfa1_irq_clips = 7,
+tfa1_irq_mtpb = 8,
+tfa1_irq_clk = 9,
+tfa1_irq_spks = 10,
+tfa1_irq_acs = 11,
+tfa1_irq_sws = 12,
+tfa1_irq_wds = 13,
+tfa1_irq_amps = 14,
+tfa1_irq_arefs = 15,
+tfa1_irq_ack = 32,
+tfa1_irq_max = 33,
+tfa1_irq_all = -1 /* all irqs */};
+
+#define TFA1_IRQ_NAMETABLE static tfaIrqName_t Tfa1IrqNames[] = {\
+{ 0, "VDDS"},\
+{ 1, "PLLS"},\
+{ 2, "DS"},\
+{ 3, "VDS"},\
+{ 4, "UVDS"},\
+{ 5, "CDS"},\
+{ 6, "CLKS"},\
+{ 7, "CLIPS"},\
+{ 8, "MTPB"},\
+{ 9, "CLK"},\
+{ 10, "SPKS"},\
+{ 11, "ACS"},\
+{ 12, "SWS"},\
+{ 13, "WDS"},\
+{ 14, "AMPS"},\
+{ 15, "AREFS"},\
+{ 16, "16"},\
+{ 17, "17"},\
+{ 18, "18"},\
+{ 19, "19"},\
+{ 20, "20"},\
+{ 21, "21"},\
+{ 22, "22"},\
+{ 23, "23"},\
+{ 24, "24"},\
+{ 25, "25"},\
+{ 26, "26"},\
+{ 27, "27"},\
+{ 28, "28"},\
+{ 29, "29"},\
+{ 30, "30"},\
+{ 31, "31"},\
+{ 32, "ACK"},\
+{ 33, "33"},\
+};
diff --git a/inc/tfa2_tfafieldnames_N1C.h b/sound/soc/codecs/tfa2_tfafieldnames_N1C.h
similarity index 81%
rename from inc/tfa2_tfafieldnames_N1C.h
rename to sound/soc/codecs/tfa2_tfafieldnames_N1C.h
index 09c0083..2bd61cc 100644
--- a/inc/tfa2_tfafieldnames_N1C.h
+++ b/sound/soc/codecs/tfa2_tfafieldnames_N1C.h
@@ -1,1526 +1,1526 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#define TFA9888_I2CVERSION 18
-typedef enum nxpTfa2BfEnumList {
- TFA2_BF_PWDN = 0x0000, /*!< Powerdown selection */
- TFA2_BF_I2CR = 0x0010, /*!< I2C Reset - Auto clear */
- TFA2_BF_CFE = 0x0020, /*!< Enable CoolFlux */
- TFA2_BF_AMPE = 0x0030, /*!< Activate Amplifier */
- TFA2_BF_DCA = 0x0040, /*!< Activate DC-to-DC converter */
- TFA2_BF_SBSL = 0x0050, /*!< Coolflux configured */
- TFA2_BF_AMPC = 0x0060, /*!< CoolFlux controls amplifier */
- TFA2_BF_INTP = 0x0071, /*!< Interrupt config */
- TFA2_BF_FSSSEL= 0x0091, /*!< Audio sample reference */
- TFA2_BF_BYPOCP= 0x00b0, /*!< Bypass OCP */
- TFA2_BF_TSTOCP= 0x00c0, /*!< OCP testing control */
- TFA2_BF_AMPINSEL= 0x0101, /*!< Amplifier input selection */
- TFA2_BF_MANSCONF= 0x0120, /*!< I2C configured */
- TFA2_BF_MANCOLD= 0x0130, /*!< Execute cold start */
- TFA2_BF_MANAOOSC= 0x0140, /*!< Internal osc off at PWDN */
- TFA2_BF_MANROBOD= 0x0150, /*!< Reaction on BOD */
- TFA2_BF_BODE = 0x0160, /*!< BOD Enable */
- TFA2_BF_BODHYS= 0x0170, /*!< BOD Hysteresis */
- TFA2_BF_BODFILT= 0x0181, /*!< BOD filter */
- TFA2_BF_BODTHLVL= 0x01a1, /*!< BOD threshold */
- TFA2_BF_MUTETO= 0x01d0, /*!< Time out SB mute sequence */
- TFA2_BF_RCVNS = 0x01e0, /*!< Noise shaper selection */
- TFA2_BF_MANWDE= 0x01f0, /*!< Watchdog manager reaction */
- TFA2_BF_AUDFS = 0x0203, /*!< Sample rate (fs) */
- TFA2_BF_INPLEV= 0x0240, /*!< TDM output attenuation */
- TFA2_BF_FRACTDEL= 0x0255, /*!< V/I Fractional delay */
- TFA2_BF_BYPHVBF= 0x02b0, /*!< Bypass HVBAT filter */
- TFA2_BF_LDOBYP= 0x02c0, /*!< Receiver LDO bypass */
- TFA2_BF_REV = 0x030f, /*!< Revision info */
- TFA2_BF_REFCKEXT= 0x0401, /*!< PLL external ref clock */
- TFA2_BF_REFCKSEL= 0x0420, /*!< PLL internal ref clock */
- TFA2_BF_SSLEFTE= 0x0500, /*!< Enable left channel */
- TFA2_BF_SSRIGHTE= 0x0510, /*!< Enable right channel */
- TFA2_BF_VSLEFTE= 0x0520, /*!< Voltage sense left */
- TFA2_BF_VSRIGHTE= 0x0530, /*!< Voltage sense right */
- TFA2_BF_CSLEFTE= 0x0540, /*!< Current sense left */
- TFA2_BF_CSRIGHTE= 0x0550, /*!< Current sense right */
- TFA2_BF_SSPDME= 0x0560, /*!< Sub-system PDM */
- TFA2_BF_STGAIN= 0x0d18, /*!< Side tone gain */
- TFA2_BF_PDMSMUTE= 0x0da0, /*!< Side tone soft mute */
- TFA2_BF_SWVSTEP= 0x0e06, /*!< Register for the host SW to record the current active vstep */
- TFA2_BF_VDDS = 0x1000, /*!< POR */
- TFA2_BF_PLLS = 0x1010, /*!< PLL lock */
- TFA2_BF_OTDS = 0x1020, /*!< OTP alarm */
- TFA2_BF_OVDS = 0x1030, /*!< OVP alarm */
- TFA2_BF_UVDS = 0x1040, /*!< UVP alarm */
- TFA2_BF_CLKS = 0x1050, /*!< Clocks stable */
- TFA2_BF_MTPB = 0x1060, /*!< MTP busy */
- TFA2_BF_NOCLK = 0x1070, /*!< Lost clock */
- TFA2_BF_SPKS = 0x1080, /*!< Speaker error */
- TFA2_BF_ACS = 0x1090, /*!< Cold Start */
- TFA2_BF_SWS = 0x10a0, /*!< Amplifier engage */
- TFA2_BF_WDS = 0x10b0, /*!< Watchdog */
- TFA2_BF_AMPS = 0x10c0, /*!< Amplifier enable */
- TFA2_BF_AREFS = 0x10d0, /*!< References enable */
- TFA2_BF_ADCCR = 0x10e0, /*!< Control ADC */
- TFA2_BF_BODNOK= 0x10f0, /*!< BOD */
- TFA2_BF_DCIL = 0x1100, /*!< DCDC current limiting */
- TFA2_BF_DCDCA = 0x1110, /*!< DCDC active */
- TFA2_BF_DCOCPOK= 0x1120, /*!< DCDC OCP nmos */
- TFA2_BF_DCHVBAT= 0x1140, /*!< DCDC level 1x */
- TFA2_BF_DCH114= 0x1150, /*!< DCDC level 1.14x */
- TFA2_BF_DCH107= 0x1160, /*!< DCDC level 1.07x */
- TFA2_BF_STMUTEB= 0x1170, /*!< side tone (un)mute busy */
- TFA2_BF_STMUTE= 0x1180, /*!< side tone mute state */
- TFA2_BF_TDMLUTER= 0x1190, /*!< TDM LUT error */
- TFA2_BF_TDMSTAT= 0x11a2, /*!< TDM status bits */
- TFA2_BF_TDMERR= 0x11d0, /*!< TDM error */
- TFA2_BF_HAPTIC= 0x11e0, /*!< Status haptic driver */
- TFA2_BF_OCPOAPL= 0x1200, /*!< OCPOK pmos A left */
- TFA2_BF_OCPOANL= 0x1210, /*!< OCPOK nmos A left */
- TFA2_BF_OCPOBPL= 0x1220, /*!< OCPOK pmos B left */
- TFA2_BF_OCPOBNL= 0x1230, /*!< OCPOK nmos B left */
- TFA2_BF_CLIPAHL= 0x1240, /*!< Clipping A left to Vddp */
- TFA2_BF_CLIPALL= 0x1250, /*!< Clipping A left to gnd */
- TFA2_BF_CLIPBHL= 0x1260, /*!< Clipping B left to Vddp */
- TFA2_BF_CLIPBLL= 0x1270, /*!< Clipping B left to gnd */
- TFA2_BF_OCPOAPRC= 0x1280, /*!< OCPOK pmos A RCV */
- TFA2_BF_OCPOANRC= 0x1290, /*!< OCPOK nmos A RCV */
- TFA2_BF_OCPOBPRC= 0x12a0, /*!< OCPOK pmos B RCV */
- TFA2_BF_OCPOBNRC= 0x12b0, /*!< OCPOK nmos B RCV */
- TFA2_BF_RCVLDOR= 0x12c0, /*!< RCV LDO regulates */
- TFA2_BF_RCVLDOBR= 0x12d0, /*!< Receiver LDO ready */
- TFA2_BF_OCDSL = 0x12e0, /*!< OCP left amplifier */
- TFA2_BF_CLIPSL= 0x12f0, /*!< Amplifier left clipping */
- TFA2_BF_OCPOAPR= 0x1300, /*!< OCPOK pmos A right */
- TFA2_BF_OCPOANR= 0x1310, /*!< OCPOK nmos A right */
- TFA2_BF_OCPOBPR= 0x1320, /*!< OCPOK pmos B right */
- TFA2_BF_OCPOBNR= 0x1330, /*!< OCPOK nmos B right */
- TFA2_BF_CLIPAHR= 0x1340, /*!< Clipping A right to Vddp */
- TFA2_BF_CLIPALR= 0x1350, /*!< Clipping A right to gnd */
- TFA2_BF_CLIPBHR= 0x1360, /*!< Clipping B left to Vddp */
- TFA2_BF_CLIPBLR= 0x1370, /*!< Clipping B right to gnd */
- TFA2_BF_OCDSR = 0x1380, /*!< OCP right amplifier */
- TFA2_BF_CLIPSR= 0x1390, /*!< Amplifier right clipping */
- TFA2_BF_OCPOKMC= 0x13a0, /*!< OCPOK MICVDD */
- TFA2_BF_MANALARM= 0x13b0, /*!< Alarm state */
- TFA2_BF_MANWAIT1= 0x13c0, /*!< Wait HW I2C settings */
- TFA2_BF_MANWAIT2= 0x13d0, /*!< Wait CF config */
- TFA2_BF_MANMUTE= 0x13e0, /*!< Audio mute sequence */
- TFA2_BF_MANOPER= 0x13f0, /*!< Operating state */
- TFA2_BF_SPKSL = 0x1400, /*!< Left speaker status */
- TFA2_BF_SPKSR = 0x1410, /*!< Right speaker status */
- TFA2_BF_CLKOOR= 0x1420, /*!< External clock status */
- TFA2_BF_MANSTATE= 0x1433, /*!< Device manager status */
- TFA2_BF_BATS = 0x1509, /*!< Battery voltage (V) */
- TFA2_BF_TEMPS = 0x1608, /*!< IC Temperature (C) */
- TFA2_BF_TDMUC = 0x2003, /*!< Usecase setting */
- TFA2_BF_TDME = 0x2040, /*!< Enable interface */
- TFA2_BF_TDMMODE= 0x2050, /*!< Slave/master */
- TFA2_BF_TDMCLINV= 0x2060, /*!< Reception data to BCK clock */
- TFA2_BF_TDMFSLN= 0x2073, /*!< FS length (master mode only) */
- TFA2_BF_TDMFSPOL= 0x20b0, /*!< FS polarity */
- TFA2_BF_TDMNBCK= 0x20c3, /*!< N-BCK's in FS */
- TFA2_BF_TDMSLOTS= 0x2103, /*!< N-slots in Frame */
- TFA2_BF_TDMSLLN= 0x2144, /*!< N-bits in slot */
- TFA2_BF_TDMBRMG= 0x2194, /*!< N-bits remaining */
- TFA2_BF_TDMDEL= 0x21e0, /*!< data delay to FS */
- TFA2_BF_TDMADJ= 0x21f0, /*!< data adjustment */
- TFA2_BF_TDMOOMP= 0x2201, /*!< Received audio compression */
- TFA2_BF_TDMSSIZE= 0x2224, /*!< Sample size per slot */
- TFA2_BF_TDMTXDFO= 0x2271, /*!< Format unused bits */
- TFA2_BF_TDMTXUS0= 0x2291, /*!< Format unused slots GAINIO */
- TFA2_BF_TDMTXUS1= 0x22b1, /*!< Format unused slots DIO1 */
- TFA2_BF_TDMTXUS2= 0x22d1, /*!< Format unused slots DIO2 */
- TFA2_BF_TDMLE = 0x2310, /*!< Control audio left */
- TFA2_BF_TDMRE = 0x2320, /*!< Control audio right */
- TFA2_BF_TDMVSRE= 0x2340, /*!< Control voltage sense right */
- TFA2_BF_TDMCSRE= 0x2350, /*!< Control current sense right */
- TFA2_BF_TDMVSLE= 0x2360, /*!< Voltage sense left control */
- TFA2_BF_TDMCSLE= 0x2370, /*!< Current sense left control */
- TFA2_BF_TDMCFRE= 0x2380, /*!< DSP out right control */
- TFA2_BF_TDMCFLE= 0x2390, /*!< DSP out left control */
- TFA2_BF_TDMCF3E= 0x23a0, /*!< AEC ref left control */
- TFA2_BF_TDMCF4E= 0x23b0, /*!< AEC ref right control */
- TFA2_BF_TDMPD1E= 0x23c0, /*!< PDM 1 control */
- TFA2_BF_TDMPD2E= 0x23d0, /*!< PDM 2 control */
- TFA2_BF_TDMLIO= 0x2421, /*!< IO audio left */
- TFA2_BF_TDMRIO= 0x2441, /*!< IO audio right */
- TFA2_BF_TDMVSRIO= 0x2481, /*!< IO voltage sense right */
- TFA2_BF_TDMCSRIO= 0x24a1, /*!< IO current sense right */
- TFA2_BF_TDMVSLIO= 0x24c1, /*!< IO voltage sense left */
- TFA2_BF_TDMCSLIO= 0x24e1, /*!< IO current sense left */
- TFA2_BF_TDMCFRIO= 0x2501, /*!< IO dspout right */
- TFA2_BF_TDMCFLIO= 0x2521, /*!< IO dspout left */
- TFA2_BF_TDMCF3IO= 0x2541, /*!< IO AEC ref left control */
- TFA2_BF_TDMCF4IO= 0x2561, /*!< IO AEC ref right control */
- TFA2_BF_TDMPD1IO= 0x2581, /*!< IO pdm1 */
- TFA2_BF_TDMPD2IO= 0x25a1, /*!< IO pdm2 */
- TFA2_BF_TDMLS = 0x2643, /*!< Position audio left */
- TFA2_BF_TDMRS = 0x2683, /*!< Position audio right */
- TFA2_BF_TDMVSRS= 0x2703, /*!< Position voltage sense right */
- TFA2_BF_TDMCSRS= 0x2743, /*!< Position current sense right */
- TFA2_BF_TDMVSLS= 0x2783, /*!< Position voltage sense left */
- TFA2_BF_TDMCSLS= 0x27c3, /*!< Position current sense left */
- TFA2_BF_TDMCFRS= 0x2803, /*!< Position dspout right */
- TFA2_BF_TDMCFLS= 0x2843, /*!< Position dspout left */
- TFA2_BF_TDMCF3S= 0x2883, /*!< Position AEC ref left control */
- TFA2_BF_TDMCF4S= 0x28c3, /*!< Position AEC ref right control */
- TFA2_BF_TDMPD1S= 0x2903, /*!< Position pdm1 */
- TFA2_BF_TDMPD2S= 0x2943, /*!< Position pdm2 */
- TFA2_BF_PDMSM = 0x3100, /*!< PDM control */
- TFA2_BF_PDMSTSEL= 0x3111, /*!< Side tone input */
- TFA2_BF_PDMLSEL= 0x3130, /*!< PDM data selection for left channel during PDM direct mode */
- TFA2_BF_PDMRSEL= 0x3140, /*!< PDM data selection for right channel during PDM direct mode */
- TFA2_BF_MICVDDE= 0x3150, /*!< Enable MICVDD */
- TFA2_BF_PDMCLRAT= 0x3201, /*!< PDM BCK/Fs ratio */
- TFA2_BF_PDMGAIN= 0x3223, /*!< PDM gain */
- TFA2_BF_PDMOSEL= 0x3263, /*!< PDM output selection - RE/FE data combination */
- TFA2_BF_SELCFHAPD= 0x32a0, /*!< Select the source for haptic data output (not for customer) */
- TFA2_BF_HAPTIME= 0x3307, /*!< Duration (ms) */
- TFA2_BF_HAPLEVEL= 0x3387, /*!< DC value (FFS) */
- TFA2_BF_GPIODIN= 0x3403, /*!< Receiving value */
- TFA2_BF_GPIOCTRL= 0x3500, /*!< GPIO master control over GPIO1/2 ports (not for customer) */
- TFA2_BF_GPIOCONF= 0x3513, /*!< Configuration */
- TFA2_BF_GPIODOUT= 0x3553, /*!< Transmitting value */
- TFA2_BF_ISTVDDS= 0x4000, /*!< Status POR */
- TFA2_BF_ISTPLLS= 0x4010, /*!< Status PLL lock */
- TFA2_BF_ISTOTDS= 0x4020, /*!< Status OTP alarm */
- TFA2_BF_ISTOVDS= 0x4030, /*!< Status OVP alarm */
- TFA2_BF_ISTUVDS= 0x4040, /*!< Status UVP alarm */
- TFA2_BF_ISTCLKS= 0x4050, /*!< Status clocks stable */
- TFA2_BF_ISTMTPB= 0x4060, /*!< Status MTP busy */
- TFA2_BF_ISTNOCLK= 0x4070, /*!< Status lost clock */
- TFA2_BF_ISTSPKS= 0x4080, /*!< Status speaker error */
- TFA2_BF_ISTACS= 0x4090, /*!< Status cold start */
- TFA2_BF_ISTSWS= 0x40a0, /*!< Status amplifier engage */
- TFA2_BF_ISTWDS= 0x40b0, /*!< Status watchdog */
- TFA2_BF_ISTAMPS= 0x40c0, /*!< Status amplifier enable */
- TFA2_BF_ISTAREFS= 0x40d0, /*!< Status Ref enable */
- TFA2_BF_ISTADCCR= 0x40e0, /*!< Status Control ADC */
- TFA2_BF_ISTBODNOK= 0x40f0, /*!< Status BOD */
- TFA2_BF_ISTBSTCU= 0x4100, /*!< Status DCDC current limiting */
- TFA2_BF_ISTBSTHI= 0x4110, /*!< Status DCDC active */
- TFA2_BF_ISTBSTOC= 0x4120, /*!< Status DCDC OCP */
- TFA2_BF_ISTBSTPKCUR= 0x4130, /*!< Status bst peakcur */
- TFA2_BF_ISTBSTVC= 0x4140, /*!< Status DCDC level 1x */
- TFA2_BF_ISTBST86= 0x4150, /*!< Status DCDC level 1.14x */
- TFA2_BF_ISTBST93= 0x4160, /*!< Status DCDC level 1.07x */
- TFA2_BF_ISTRCVLD= 0x4170, /*!< Status rcvldop ready */
- TFA2_BF_ISTOCPL= 0x4180, /*!< Status ocp alarm left */
- TFA2_BF_ISTOCPR= 0x4190, /*!< Status ocp alarm right */
- TFA2_BF_ISTMWSRC= 0x41a0, /*!< Status Waits HW I2C settings */
- TFA2_BF_ISTMWCFC= 0x41b0, /*!< Status waits CF config */
- TFA2_BF_ISTMWSMU= 0x41c0, /*!< Status Audio mute sequence */
- TFA2_BF_ISTCFMER= 0x41d0, /*!< Status cfma error */
- TFA2_BF_ISTCFMAC= 0x41e0, /*!< Status cfma ack */
- TFA2_BF_ISTCLKOOR= 0x41f0, /*!< Status flag_clk_out_of_range */
- TFA2_BF_ISTTDMER= 0x4200, /*!< Status tdm error */
- TFA2_BF_ISTCLPL= 0x4210, /*!< Status clip left */
- TFA2_BF_ISTCLPR= 0x4220, /*!< Status clip right */
- TFA2_BF_ISTOCPM= 0x4230, /*!< Status mic ocpok */
- TFA2_BF_ICLVDDS= 0x4400, /*!< Clear POR */
- TFA2_BF_ICLPLLS= 0x4410, /*!< Clear PLL lock */
- TFA2_BF_ICLOTDS= 0x4420, /*!< Clear OTP alarm */
- TFA2_BF_ICLOVDS= 0x4430, /*!< Clear OVP alarm */
- TFA2_BF_ICLUVDS= 0x4440, /*!< Clear UVP alarm */
- TFA2_BF_ICLCLKS= 0x4450, /*!< Clear clocks stable */
- TFA2_BF_ICLMTPB= 0x4460, /*!< Clear mtp busy */
- TFA2_BF_ICLNOCLK= 0x4470, /*!< Clear lost clk */
- TFA2_BF_ICLSPKS= 0x4480, /*!< Clear speaker error */
- TFA2_BF_ICLACS= 0x4490, /*!< Clear cold started */
- TFA2_BF_ICLSWS= 0x44a0, /*!< Clear amplifier engage */
- TFA2_BF_ICLWDS= 0x44b0, /*!< Clear watchdog */
- TFA2_BF_ICLAMPS= 0x44c0, /*!< Clear enbl amp */
- TFA2_BF_ICLAREFS= 0x44d0, /*!< Clear ref enable */
- TFA2_BF_ICLADCCR= 0x44e0, /*!< Clear control ADC */
- TFA2_BF_ICLBODNOK= 0x44f0, /*!< Clear BOD */
- TFA2_BF_ICLBSTCU= 0x4500, /*!< Clear DCDC current limiting */
- TFA2_BF_ICLBSTHI= 0x4510, /*!< Clear DCDC active */
- TFA2_BF_ICLBSTOC= 0x4520, /*!< Clear DCDC OCP */
- TFA2_BF_ICLBSTPC= 0x4530, /*!< Clear bst peakcur */
- TFA2_BF_ICLBSTVC= 0x4540, /*!< Clear DCDC level 1x */
- TFA2_BF_ICLBST86= 0x4550, /*!< Clear DCDC level 1.14x */
- TFA2_BF_ICLBST93= 0x4560, /*!< Clear DCDC level 1.07x */
- TFA2_BF_ICLRCVLD= 0x4570, /*!< Clear rcvldop ready */
- TFA2_BF_ICLOCPL= 0x4580, /*!< Clear ocp alarm left */
- TFA2_BF_ICLOCPR= 0x4590, /*!< Clear ocp alarm right */
- TFA2_BF_ICLMWSRC= 0x45a0, /*!< Clear wait HW I2C settings */
- TFA2_BF_ICLMWCFC= 0x45b0, /*!< Clear wait cf config */
- TFA2_BF_ICLMWSMU= 0x45c0, /*!< Clear audio mute sequence */
- TFA2_BF_ICLCFMER= 0x45d0, /*!< Clear cfma err */
- TFA2_BF_ICLCFMAC= 0x45e0, /*!< Clear cfma ack */
- TFA2_BF_ICLCLKOOR= 0x45f0, /*!< Clear flag_clk_out_of_range */
- TFA2_BF_ICLTDMER= 0x4600, /*!< Clear tdm error */
- TFA2_BF_ICLCLPL= 0x4610, /*!< Clear clip left */
- TFA2_BF_ICLCLPR= 0x4620, /*!< Clear clip right */
- TFA2_BF_ICLOCPM= 0x4630, /*!< Clear mic ocpok */
- TFA2_BF_IEVDDS= 0x4800, /*!< Enable por */
- TFA2_BF_IEPLLS= 0x4810, /*!< Enable pll lock */
- TFA2_BF_IEOTDS= 0x4820, /*!< Enable OTP alarm */
- TFA2_BF_IEOVDS= 0x4830, /*!< Enable OVP alarm */
- TFA2_BF_IEUVDS= 0x4840, /*!< Enable UVP alarm */
- TFA2_BF_IECLKS= 0x4850, /*!< Enable clocks stable */
- TFA2_BF_IEMTPB= 0x4860, /*!< Enable mtp busy */
- TFA2_BF_IENOCLK= 0x4870, /*!< Enable lost clk */
- TFA2_BF_IESPKS= 0x4880, /*!< Enable speaker error */
- TFA2_BF_IEACS = 0x4890, /*!< Enable cold started */
- TFA2_BF_IESWS = 0x48a0, /*!< Enable amplifier engage */
- TFA2_BF_IEWDS = 0x48b0, /*!< Enable watchdog */
- TFA2_BF_IEAMPS= 0x48c0, /*!< Enable enbl amp */
- TFA2_BF_IEAREFS= 0x48d0, /*!< Enable ref enable */
- TFA2_BF_IEADCCR= 0x48e0, /*!< Enable Control ADC */
- TFA2_BF_IEBODNOK= 0x48f0, /*!< Enable BOD */
- TFA2_BF_IEBSTCU= 0x4900, /*!< Enable DCDC current limiting */
- TFA2_BF_IEBSTHI= 0x4910, /*!< Enable DCDC active */
- TFA2_BF_IEBSTOC= 0x4920, /*!< Enable DCDC OCP */
- TFA2_BF_IEBSTPC= 0x4930, /*!< Enable bst peakcur */
- TFA2_BF_IEBSTVC= 0x4940, /*!< Enable DCDC level 1x */
- TFA2_BF_IEBST86= 0x4950, /*!< Enable DCDC level 1.14x */
- TFA2_BF_IEBST93= 0x4960, /*!< Enable DCDC level 1.07x */
- TFA2_BF_IERCVLD= 0x4970, /*!< Enable rcvldop ready */
- TFA2_BF_IEOCPL= 0x4980, /*!< Enable ocp alarm left */
- TFA2_BF_IEOCPR= 0x4990, /*!< Enable ocp alarm right */
- TFA2_BF_IEMWSRC= 0x49a0, /*!< Enable waits HW I2C settings */
- TFA2_BF_IEMWCFC= 0x49b0, /*!< Enable man wait cf config */
- TFA2_BF_IEMWSMU= 0x49c0, /*!< Enable man Audio mute sequence */
- TFA2_BF_IECFMER= 0x49d0, /*!< Enable cfma err */
- TFA2_BF_IECFMAC= 0x49e0, /*!< Enable cfma ack */
- TFA2_BF_IECLKOOR= 0x49f0, /*!< Enable flag_clk_out_of_range */
- TFA2_BF_IETDMER= 0x4a00, /*!< Enable tdm error */
- TFA2_BF_IECLPL= 0x4a10, /*!< Enable clip left */
- TFA2_BF_IECLPR= 0x4a20, /*!< Enable clip right */
- TFA2_BF_IEOCPM1= 0x4a30, /*!< Enable mic ocpok */
- TFA2_BF_IPOVDDS= 0x4c00, /*!< Polarity por */
- TFA2_BF_IPOPLLS= 0x4c10, /*!< Polarity pll lock */
- TFA2_BF_IPOOTDS= 0x4c20, /*!< Polarity OTP alarm */
- TFA2_BF_IPOOVDS= 0x4c30, /*!< Polarity OVP alarm */
- TFA2_BF_IPOUVDS= 0x4c40, /*!< Polarity UVP alarm */
- TFA2_BF_IPOCLKS= 0x4c50, /*!< Polarity clocks stable */
- TFA2_BF_IPOMTPB= 0x4c60, /*!< Polarity mtp busy */
- TFA2_BF_IPONOCLK= 0x4c70, /*!< Polarity lost clk */
- TFA2_BF_IPOSPKS= 0x4c80, /*!< Polarity speaker error */
- TFA2_BF_IPOACS= 0x4c90, /*!< Polarity cold started */
- TFA2_BF_IPOSWS= 0x4ca0, /*!< Polarity amplifier engage */
- TFA2_BF_IPOWDS= 0x4cb0, /*!< Polarity watchdog */
- TFA2_BF_IPOAMPS= 0x4cc0, /*!< Polarity enbl amp */
- TFA2_BF_IPOAREFS= 0x4cd0, /*!< Polarity ref enable */
- TFA2_BF_IPOADCCR= 0x4ce0, /*!< Polarity Control ADC */
- TFA2_BF_IPOBODNOK= 0x4cf0, /*!< Polarity BOD */
- TFA2_BF_IPOBSTCU= 0x4d00, /*!< Polarity DCDC current limiting */
- TFA2_BF_IPOBSTHI= 0x4d10, /*!< Polarity DCDC active */
- TFA2_BF_IPOBSTOC= 0x4d20, /*!< Polarity DCDC OCP */
- TFA2_BF_IPOBSTPC= 0x4d30, /*!< Polarity bst peakcur */
- TFA2_BF_IPOBSTVC= 0x4d40, /*!< Polarity DCDC level 1x */
- TFA2_BF_IPOBST86= 0x4d50, /*!< Polarity DCDC level 1.14x */
- TFA2_BF_IPOBST93= 0x4d60, /*!< Polarity DCDC level 1.07x */
- TFA2_BF_IPORCVLD= 0x4d70, /*!< Polarity rcvldop ready */
- TFA2_BF_IPOOCPL= 0x4d80, /*!< Polarity ocp alarm left */
- TFA2_BF_IPOOCPR= 0x4d90, /*!< Polarity ocp alarm right */
- TFA2_BF_IPOMWSRC= 0x4da0, /*!< Polarity waits HW I2C settings */
- TFA2_BF_IPOMWCFC= 0x4db0, /*!< Polarity man wait cf config */
- TFA2_BF_IPOMWSMU= 0x4dc0, /*!< Polarity man audio mute sequence */
- TFA2_BF_IPOCFMER= 0x4dd0, /*!< Polarity cfma err */
- TFA2_BF_IPOCFMAC= 0x4de0, /*!< Polarity cfma ack */
- TFA2_BF_IPCLKOOR= 0x4df0, /*!< Polarity flag_clk_out_of_range */
- TFA2_BF_IPOTDMER= 0x4e00, /*!< Polarity tdm error */
- TFA2_BF_IPOCLPL= 0x4e10, /*!< Polarity clip left */
- TFA2_BF_IPOCLPR= 0x4e20, /*!< Polarity clip right */
- TFA2_BF_IPOOCPM= 0x4e30, /*!< Polarity mic ocpok */
- TFA2_BF_BSSCR = 0x5001, /*!< Battery protection attack Time */
- TFA2_BF_BSST = 0x5023, /*!< Battery protection threshold voltage level */
- TFA2_BF_BSSRL = 0x5061, /*!< Battery protection maximum reduction */
- TFA2_BF_BSSRR = 0x5082, /*!< Battery protection release time */
- TFA2_BF_BSSHY = 0x50b1, /*!< Battery protection hysteresis */
- TFA2_BF_BSSR = 0x50e0, /*!< Battery voltage read out */
- TFA2_BF_BSSBY = 0x50f0, /*!< Bypass HW clipper */
- TFA2_BF_BSSS = 0x5100, /*!< Vbat prot steepness */
- TFA2_BF_INTSMUTE= 0x5110, /*!< Soft mute HW */
- TFA2_BF_CFSML = 0x5120, /*!< Soft mute FW left */
- TFA2_BF_CFSMR = 0x5130, /*!< Soft mute FW right */
- TFA2_BF_HPFBYPL= 0x5140, /*!< Bypass HPF left */
- TFA2_BF_HPFBYPR= 0x5150, /*!< Bypass HPF right */
- TFA2_BF_DPSAL = 0x5160, /*!< Enable DPSA left */
- TFA2_BF_DPSAR = 0x5170, /*!< Enable DPSA right */
- TFA2_BF_VOL = 0x5187, /*!< FW volume control for primary audio channel */
- TFA2_BF_HNDSFRCV= 0x5200, /*!< Selection receiver */
- TFA2_BF_CLIPCTRL= 0x5222, /*!< Clip control setting */
- TFA2_BF_AMPGAIN= 0x5257, /*!< Amplifier gain */
- TFA2_BF_SLOPEE= 0x52d0, /*!< Enables slope control */
- TFA2_BF_SLOPESET= 0x52e1, /*!< Set slope */
- TFA2_BF_VOLSEC= 0x5a07, /*!< FW volume control for secondary audio channel */
- TFA2_BF_SWPROFIL= 0x5a87, /*!< Software profile data */
- TFA2_BF_DCVO = 0x7002, /*!< Boost voltage */
- TFA2_BF_DCMCC = 0x7033, /*!< Max coil current */
- TFA2_BF_DCCV = 0x7071, /*!< Coil Value */
- TFA2_BF_DCIE = 0x7090, /*!< Adaptive boost mode */
- TFA2_BF_DCSR = 0x70a0, /*!< Soft ramp up/down */
- TFA2_BF_DCSYNCP= 0x70b2, /*!< DCDC synchronization off + 7 positions */
- TFA2_BF_DCDIS = 0x70e0, /*!< DCDC on/off */
- TFA2_BF_RST = 0x9000, /*!< Reset */
- TFA2_BF_DMEM = 0x9011, /*!< Target memory */
- TFA2_BF_AIF = 0x9030, /*!< Auto increment */
- TFA2_BF_CFINT = 0x9040, /*!< Interrupt - auto clear */
- TFA2_BF_CFCGATE= 0x9050, /*!< Coolflux clock gating disabling control */
- TFA2_BF_REQ = 0x9087, /*!< request for access (8 channels) */
- TFA2_BF_REQCMD= 0x9080, /*!< Firmware event request rpc command */
- TFA2_BF_REQRST= 0x9090, /*!< Firmware event request reset restart */
- TFA2_BF_REQMIPS= 0x90a0, /*!< Firmware event request short on mips */
- TFA2_BF_REQMUTED= 0x90b0, /*!< Firmware event request mute sequence ready */
- TFA2_BF_REQVOL= 0x90c0, /*!< Firmware event request volume ready */
- TFA2_BF_REQDMG= 0x90d0, /*!< Firmware event request speaker damage detected */
- TFA2_BF_REQCAL= 0x90e0, /*!< Firmware event request calibration completed */
- TFA2_BF_REQRSV= 0x90f0, /*!< Firmware event request reserved */
- TFA2_BF_MADD = 0x910f, /*!< Memory address */
- TFA2_BF_MEMA = 0x920f, /*!< Activate memory access */
- TFA2_BF_ERR = 0x9307, /*!< Error flags */
- TFA2_BF_ACK = 0x9387, /*!< Acknowledge of requests */
- TFA2_BF_ACKCMD= 0x9380, /*!< Firmware event acknowledge rpc command */
- TFA2_BF_ACKRST= 0x9390, /*!< Firmware event acknowledge reset restart */
- TFA2_BF_ACKMIPS= 0x93a0, /*!< Firmware event acknowledge short on mips */
- TFA2_BF_ACKMUTED= 0x93b0, /*!< Firmware event acknowledge mute sequence ready */
- TFA2_BF_ACKVOL= 0x93c0, /*!< Firmware event acknowledge volume ready */
- TFA2_BF_ACKDMG= 0x93d0, /*!< Firmware event acknowledge speaker damage detected */
- TFA2_BF_ACKCAL= 0x93e0, /*!< Firmware event acknowledge calibration completed */
- TFA2_BF_ACKRSV= 0x93f0, /*!< Firmware event acknowledge reserved */
- TFA2_BF_MTPK = 0xa107, /*!< MTP KEY2 register */
- TFA2_BF_KEY1LOCKED= 0xa200, /*!< Indicates KEY1 is locked */
- TFA2_BF_KEY2LOCKED= 0xa210, /*!< Indicates KEY2 is locked */
- TFA2_BF_CIMTP = 0xa360, /*!< Start copying data from I2C mtp registers to mtp */
- TFA2_BF_MTPRDMSB= 0xa50f, /*!< MSB word of MTP manual read data */
- TFA2_BF_MTPRDLSB= 0xa60f, /*!< LSB word of MTP manual read data */
- TFA2_BF_EXTTS = 0xb108, /*!< External temperature (C) */
- TFA2_BF_TROS = 0xb190, /*!< Select temp Speaker calibration */
- TFA2_BF_MTPOTC= 0xf000, /*!< Calibration schedule */
- TFA2_BF_MTPEX = 0xf010, /*!< Calibration Ron executed */
- TFA2_BF_DCMCCAPI= 0xf020, /*!< Calibration current limit DCDC */
- TFA2_BF_DCMCCSB= 0xf030, /*!< Sign bit for delta calibration current limit DCDC */
- TFA2_BF_USERDEF= 0xf042, /*!< Calibration delta current limit DCDC */
- TFA2_BF_R25CL = 0xf40f, /*!< Ron resistance of left channel speaker coil */
- TFA2_BF_R25CR = 0xf50f, /*!< Ron resistance of right channel speaker coil */
-} nxpTfa2BfEnumList_t;
-#define TFA2_NAMETABLE static tfaBfName_t Tfa2DatasheetNames[]= {\
- { 0x0, "PWDN"}, /* Powerdown selection , */\
- { 0x10, "I2CR"}, /* I2C Reset - Auto clear , */\
- { 0x20, "CFE"}, /* Enable CoolFlux , */\
- { 0x30, "AMPE"}, /* Activate Amplifier , */\
- { 0x40, "DCA"}, /* Activate DC-to-DC converter , */\
- { 0x50, "SBSL"}, /* Coolflux configured , */\
- { 0x60, "AMPC"}, /* CoolFlux controls amplifier , */\
- { 0x71, "INTP"}, /* Interrupt config , */\
- { 0x91, "FSSSEL"}, /* Audio sample reference , */\
- { 0xb0, "BYPOCP"}, /* Bypass OCP , */\
- { 0xc0, "TSTOCP"}, /* OCP testing control , */\
- { 0x101, "AMPINSEL"}, /* Amplifier input selection , */\
- { 0x120, "MANSCONF"}, /* I2C configured , */\
- { 0x130, "MANCOLD"}, /* Execute cold start , */\
- { 0x140, "MANAOOSC"}, /* Internal osc off at PWDN , */\
- { 0x150, "MANROBOD"}, /* Reaction on BOD , */\
- { 0x160, "BODE"}, /* BOD Enable , */\
- { 0x170, "BODHYS"}, /* BOD Hysteresis , */\
- { 0x181, "BODFILT"}, /* BOD filter , */\
- { 0x1a1, "BODTHLVL"}, /* BOD threshold , */\
- { 0x1d0, "MUTETO"}, /* Time out SB mute sequence , */\
- { 0x1e0, "RCVNS"}, /* Noise shaper selection , */\
- { 0x1f0, "MANWDE"}, /* Watchdog manager reaction , */\
- { 0x203, "AUDFS"}, /* Sample rate (fs) , */\
- { 0x240, "INPLEV"}, /* TDM output attenuation , */\
- { 0x255, "FRACTDEL"}, /* V/I Fractional delay , */\
- { 0x2b0, "BYPHVBF"}, /* Bypass HVBAT filter , */\
- { 0x2c0, "LDOBYP"}, /* Receiver LDO bypass , */\
- { 0x30f, "REV"}, /* Revision info , */\
- { 0x401, "REFCKEXT"}, /* PLL external ref clock , */\
- { 0x420, "REFCKSEL"}, /* PLL internal ref clock , */\
- { 0x500, "SSLEFTE"}, /* Enable left channel , */\
- { 0x510, "SSRIGHTE"}, /* Enable right channel , */\
- { 0x520, "VSLEFTE"}, /* Voltage sense left , */\
- { 0x530, "VSRIGHTE"}, /* Voltage sense right , */\
- { 0x540, "CSLEFTE"}, /* Current sense left , */\
- { 0x550, "CSRIGHTE"}, /* Current sense right , */\
- { 0x560, "SSPDME"}, /* Sub-system PDM , */\
- { 0xd18, "STGAIN"}, /* Side tone gain , */\
- { 0xda0, "PDMSMUTE"}, /* Side tone soft mute , */\
- { 0xe06, "SWVSTEP"}, /* Register for the host SW to record the current active vstep, */\
- { 0x1000, "VDDS"}, /* POR , */\
- { 0x1010, "PLLS"}, /* PLL lock , */\
- { 0x1020, "OTDS"}, /* OTP alarm , */\
- { 0x1030, "OVDS"}, /* OVP alarm , */\
- { 0x1040, "UVDS"}, /* UVP alarm , */\
- { 0x1050, "CLKS"}, /* Clocks stable , */\
- { 0x1060, "MTPB"}, /* MTP busy , */\
- { 0x1070, "NOCLK"}, /* Lost clock , */\
- { 0x1080, "SPKS"}, /* Speaker error , */\
- { 0x1090, "ACS"}, /* Cold Start , */\
- { 0x10a0, "SWS"}, /* Amplifier engage , */\
- { 0x10b0, "WDS"}, /* Watchdog , */\
- { 0x10c0, "AMPS"}, /* Amplifier enable , */\
- { 0x10d0, "AREFS"}, /* References enable , */\
- { 0x10e0, "ADCCR"}, /* Control ADC , */\
- { 0x10f0, "BODNOK"}, /* BOD , */\
- { 0x1100, "DCIL"}, /* DCDC current limiting , */\
- { 0x1110, "DCDCA"}, /* DCDC active , */\
- { 0x1120, "DCOCPOK"}, /* DCDC OCP nmos , */\
- { 0x1140, "DCHVBAT"}, /* DCDC level 1x , */\
- { 0x1150, "DCH114"}, /* DCDC level 1.14x , */\
- { 0x1160, "DCH107"}, /* DCDC level 1.07x , */\
- { 0x1170, "STMUTEB"}, /* side tone (un)mute busy , */\
- { 0x1180, "STMUTE"}, /* side tone mute state , */\
- { 0x1190, "TDMLUTER"}, /* TDM LUT error , */\
- { 0x11a2, "TDMSTAT"}, /* TDM status bits , */\
- { 0x11d0, "TDMERR"}, /* TDM error , */\
- { 0x11e0, "HAPTIC"}, /* Status haptic driver , */\
- { 0x1200, "OCPOAPL"}, /* OCPOK pmos A left , */\
- { 0x1210, "OCPOANL"}, /* OCPOK nmos A left , */\
- { 0x1220, "OCPOBPL"}, /* OCPOK pmos B left , */\
- { 0x1230, "OCPOBNL"}, /* OCPOK nmos B left , */\
- { 0x1240, "CLIPAHL"}, /* Clipping A left to Vddp , */\
- { 0x1250, "CLIPALL"}, /* Clipping A left to gnd , */\
- { 0x1260, "CLIPBHL"}, /* Clipping B left to Vddp , */\
- { 0x1270, "CLIPBLL"}, /* Clipping B left to gnd , */\
- { 0x1280, "OCPOAPRC"}, /* OCPOK pmos A RCV , */\
- { 0x1290, "OCPOANRC"}, /* OCPOK nmos A RCV , */\
- { 0x12a0, "OCPOBPRC"}, /* OCPOK pmos B RCV , */\
- { 0x12b0, "OCPOBNRC"}, /* OCPOK nmos B RCV , */\
- { 0x12c0, "RCVLDOR"}, /* RCV LDO regulates , */\
- { 0x12d0, "RCVLDOBR"}, /* Receiver LDO ready , */\
- { 0x12e0, "OCDSL"}, /* OCP left amplifier , */\
- { 0x12f0, "CLIPSL"}, /* Amplifier left clipping , */\
- { 0x1300, "OCPOAPR"}, /* OCPOK pmos A right , */\
- { 0x1310, "OCPOANR"}, /* OCPOK nmos A right , */\
- { 0x1320, "OCPOBPR"}, /* OCPOK pmos B right , */\
- { 0x1330, "OCPOBNR"}, /* OCPOK nmos B right , */\
- { 0x1340, "CLIPAHR"}, /* Clipping A right to Vddp , */\
- { 0x1350, "CLIPALR"}, /* Clipping A right to gnd , */\
- { 0x1360, "CLIPBHR"}, /* Clipping B left to Vddp , */\
- { 0x1370, "CLIPBLR"}, /* Clipping B right to gnd , */\
- { 0x1380, "OCDSR"}, /* OCP right amplifier , */\
- { 0x1390, "CLIPSR"}, /* Amplifier right clipping , */\
- { 0x13a0, "OCPOKMC"}, /* OCPOK MICVDD , */\
- { 0x13b0, "MANALARM"}, /* Alarm state , */\
- { 0x13c0, "MANWAIT1"}, /* Wait HW I2C settings , */\
- { 0x13d0, "MANWAIT2"}, /* Wait CF config , */\
- { 0x13e0, "MANMUTE"}, /* Audio mute sequence , */\
- { 0x13f0, "MANOPER"}, /* Operating state , */\
- { 0x1400, "SPKSL"}, /* Left speaker status , */\
- { 0x1410, "SPKSR"}, /* Right speaker status , */\
- { 0x1420, "CLKOOR"}, /* External clock status , */\
- { 0x1433, "MANSTATE"}, /* Device manager status , */\
- { 0x1509, "BATS"}, /* Battery voltage (V) , */\
- { 0x1608, "TEMPS"}, /* IC Temperature (C) , */\
- { 0x2003, "TDMUC"}, /* Usecase setting , */\
- { 0x2040, "TDME"}, /* Enable interface , */\
- { 0x2050, "TDMMODE"}, /* Slave/master , */\
- { 0x2060, "TDMCLINV"}, /* Reception data to BCK clock , */\
- { 0x2073, "TDMFSLN"}, /* FS length (master mode only) , */\
- { 0x20b0, "TDMFSPOL"}, /* FS polarity , */\
- { 0x20c3, "TDMNBCK"}, /* N-BCK's in FS , */\
- { 0x2103, "TDMSLOTS"}, /* N-slots in Frame , */\
- { 0x2144, "TDMSLLN"}, /* N-bits in slot , */\
- { 0x2194, "TDMBRMG"}, /* N-bits remaining , */\
- { 0x21e0, "TDMDEL"}, /* data delay to FS , */\
- { 0x21f0, "TDMADJ"}, /* data adjustment , */\
- { 0x2201, "TDMOOMP"}, /* Received audio compression , */\
- { 0x2224, "TDMSSIZE"}, /* Sample size per slot , */\
- { 0x2271, "TDMTXDFO"}, /* Format unused bits , */\
- { 0x2291, "TDMTXUS0"}, /* Format unused slots GAINIO , */\
- { 0x22b1, "TDMTXUS1"}, /* Format unused slots DIO1 , */\
- { 0x22d1, "TDMTXUS2"}, /* Format unused slots DIO2 , */\
- { 0x2310, "TDMLE"}, /* Control audio left , */\
- { 0x2320, "TDMRE"}, /* Control audio right , */\
- { 0x2340, "TDMVSRE"}, /* Control voltage sense right , */\
- { 0x2350, "TDMCSRE"}, /* Control current sense right , */\
- { 0x2360, "TDMVSLE"}, /* Voltage sense left control , */\
- { 0x2370, "TDMCSLE"}, /* Current sense left control , */\
- { 0x2380, "TDMCFRE"}, /* DSP out right control , */\
- { 0x2390, "TDMCFLE"}, /* DSP out left control , */\
- { 0x23a0, "TDMCF3E"}, /* AEC ref left control , */\
- { 0x23b0, "TDMCF4E"}, /* AEC ref right control , */\
- { 0x23c0, "TDMPD1E"}, /* PDM 1 control , */\
- { 0x23d0, "TDMPD2E"}, /* PDM 2 control , */\
- { 0x2421, "TDMLIO"}, /* IO audio left , */\
- { 0x2441, "TDMRIO"}, /* IO audio right , */\
- { 0x2481, "TDMVSRIO"}, /* IO voltage sense right , */\
- { 0x24a1, "TDMCSRIO"}, /* IO current sense right , */\
- { 0x24c1, "TDMVSLIO"}, /* IO voltage sense left , */\
- { 0x24e1, "TDMCSLIO"}, /* IO current sense left , */\
- { 0x2501, "TDMCFRIO"}, /* IO dspout right , */\
- { 0x2521, "TDMCFLIO"}, /* IO dspout left , */\
- { 0x2541, "TDMCF3IO"}, /* IO AEC ref left control , */\
- { 0x2561, "TDMCF4IO"}, /* IO AEC ref right control , */\
- { 0x2581, "TDMPD1IO"}, /* IO pdm1 , */\
- { 0x25a1, "TDMPD2IO"}, /* IO pdm2 , */\
- { 0x2643, "TDMLS"}, /* Position audio left , */\
- { 0x2683, "TDMRS"}, /* Position audio right , */\
- { 0x2703, "TDMVSRS"}, /* Position voltage sense right , */\
- { 0x2743, "TDMCSRS"}, /* Position current sense right , */\
- { 0x2783, "TDMVSLS"}, /* Position voltage sense left , */\
- { 0x27c3, "TDMCSLS"}, /* Position current sense left , */\
- { 0x2803, "TDMCFRS"}, /* Position dspout right , */\
- { 0x2843, "TDMCFLS"}, /* Position dspout left , */\
- { 0x2883, "TDMCF3S"}, /* Position AEC ref left control , */\
- { 0x28c3, "TDMCF4S"}, /* Position AEC ref right control , */\
- { 0x2903, "TDMPD1S"}, /* Position pdm1 , */\
- { 0x2943, "TDMPD2S"}, /* Position pdm2 , */\
- { 0x3100, "PDMSM"}, /* PDM control , */\
- { 0x3111, "PDMSTSEL"}, /* Side tone input , */\
- { 0x3130, "PDMLSEL"}, /* PDM data selection for left channel during PDM direct mode, */\
- { 0x3140, "PDMRSEL"}, /* PDM data selection for right channel during PDM direct mode, */\
- { 0x3150, "MICVDDE"}, /* Enable MICVDD , */\
- { 0x3201, "PDMCLRAT"}, /* PDM BCK/Fs ratio , */\
- { 0x3223, "PDMGAIN"}, /* PDM gain , */\
- { 0x3263, "PDMOSEL"}, /* PDM output selection - RE/FE data combination , */\
- { 0x32a0, "SELCFHAPD"}, /* Select the source for haptic data output (not for customer), */\
- { 0x3307, "HAPTIME"}, /* Duration (ms) , */\
- { 0x3387, "HAPLEVEL"}, /* DC value (FFS) , */\
- { 0x3403, "GPIODIN"}, /* Receiving value , */\
- { 0x3500, "GPIOCTRL"}, /* GPIO master control over GPIO1/2 ports (not for customer), */\
- { 0x3513, "GPIOCONF"}, /* Configuration , */\
- { 0x3553, "GPIODOUT"}, /* Transmitting value , */\
- { 0x4000, "ISTVDDS"}, /* Status POR , */\
- { 0x4010, "ISTPLLS"}, /* Status PLL lock , */\
- { 0x4020, "ISTOTDS"}, /* Status OTP alarm , */\
- { 0x4030, "ISTOVDS"}, /* Status OVP alarm , */\
- { 0x4040, "ISTUVDS"}, /* Status UVP alarm , */\
- { 0x4050, "ISTCLKS"}, /* Status clocks stable , */\
- { 0x4060, "ISTMTPB"}, /* Status MTP busy , */\
- { 0x4070, "ISTNOCLK"}, /* Status lost clock , */\
- { 0x4080, "ISTSPKS"}, /* Status speaker error , */\
- { 0x4090, "ISTACS"}, /* Status cold start , */\
- { 0x40a0, "ISTSWS"}, /* Status amplifier engage , */\
- { 0x40b0, "ISTWDS"}, /* Status watchdog , */\
- { 0x40c0, "ISTAMPS"}, /* Status amplifier enable , */\
- { 0x40d0, "ISTAREFS"}, /* Status Ref enable , */\
- { 0x40e0, "ISTADCCR"}, /* Status Control ADC , */\
- { 0x40f0, "ISTBODNOK"}, /* Status BOD , */\
- { 0x4100, "ISTBSTCU"}, /* Status DCDC current limiting , */\
- { 0x4110, "ISTBSTHI"}, /* Status DCDC active , */\
- { 0x4120, "ISTBSTOC"}, /* Status DCDC OCP , */\
- { 0x4130, "ISTBSTPKCUR"}, /* Status bst peakcur , */\
- { 0x4140, "ISTBSTVC"}, /* Status DCDC level 1x , */\
- { 0x4150, "ISTBST86"}, /* Status DCDC level 1.14x , */\
- { 0x4160, "ISTBST93"}, /* Status DCDC level 1.07x , */\
- { 0x4170, "ISTRCVLD"}, /* Status rcvldop ready , */\
- { 0x4180, "ISTOCPL"}, /* Status ocp alarm left , */\
- { 0x4190, "ISTOCPR"}, /* Status ocp alarm right , */\
- { 0x41a0, "ISTMWSRC"}, /* Status Waits HW I2C settings , */\
- { 0x41b0, "ISTMWCFC"}, /* Status waits CF config , */\
- { 0x41c0, "ISTMWSMU"}, /* Status Audio mute sequence , */\
- { 0x41d0, "ISTCFMER"}, /* Status cfma error , */\
- { 0x41e0, "ISTCFMAC"}, /* Status cfma ack , */\
- { 0x41f0, "ISTCLKOOR"}, /* Status flag_clk_out_of_range , */\
- { 0x4200, "ISTTDMER"}, /* Status tdm error , */\
- { 0x4210, "ISTCLPL"}, /* Status clip left , */\
- { 0x4220, "ISTCLPR"}, /* Status clip right , */\
- { 0x4230, "ISTOCPM"}, /* Status mic ocpok , */\
- { 0x4400, "ICLVDDS"}, /* Clear POR , */\
- { 0x4410, "ICLPLLS"}, /* Clear PLL lock , */\
- { 0x4420, "ICLOTDS"}, /* Clear OTP alarm , */\
- { 0x4430, "ICLOVDS"}, /* Clear OVP alarm , */\
- { 0x4440, "ICLUVDS"}, /* Clear UVP alarm , */\
- { 0x4450, "ICLCLKS"}, /* Clear clocks stable , */\
- { 0x4460, "ICLMTPB"}, /* Clear mtp busy , */\
- { 0x4470, "ICLNOCLK"}, /* Clear lost clk , */\
- { 0x4480, "ICLSPKS"}, /* Clear speaker error , */\
- { 0x4490, "ICLACS"}, /* Clear cold started , */\
- { 0x44a0, "ICLSWS"}, /* Clear amplifier engage , */\
- { 0x44b0, "ICLWDS"}, /* Clear watchdog , */\
- { 0x44c0, "ICLAMPS"}, /* Clear enbl amp , */\
- { 0x44d0, "ICLAREFS"}, /* Clear ref enable , */\
- { 0x44e0, "ICLADCCR"}, /* Clear control ADC , */\
- { 0x44f0, "ICLBODNOK"}, /* Clear BOD , */\
- { 0x4500, "ICLBSTCU"}, /* Clear DCDC current limiting , */\
- { 0x4510, "ICLBSTHI"}, /* Clear DCDC active , */\
- { 0x4520, "ICLBSTOC"}, /* Clear DCDC OCP , */\
- { 0x4530, "ICLBSTPC"}, /* Clear bst peakcur , */\
- { 0x4540, "ICLBSTVC"}, /* Clear DCDC level 1x , */\
- { 0x4550, "ICLBST86"}, /* Clear DCDC level 1.14x , */\
- { 0x4560, "ICLBST93"}, /* Clear DCDC level 1.07x , */\
- { 0x4570, "ICLRCVLD"}, /* Clear rcvldop ready , */\
- { 0x4580, "ICLOCPL"}, /* Clear ocp alarm left , */\
- { 0x4590, "ICLOCPR"}, /* Clear ocp alarm right , */\
- { 0x45a0, "ICLMWSRC"}, /* Clear wait HW I2C settings , */\
- { 0x45b0, "ICLMWCFC"}, /* Clear wait cf config , */\
- { 0x45c0, "ICLMWSMU"}, /* Clear audio mute sequence , */\
- { 0x45d0, "ICLCFMER"}, /* Clear cfma err , */\
- { 0x45e0, "ICLCFMAC"}, /* Clear cfma ack , */\
- { 0x45f0, "ICLCLKOOR"}, /* Clear flag_clk_out_of_range , */\
- { 0x4600, "ICLTDMER"}, /* Clear tdm error , */\
- { 0x4610, "ICLCLPL"}, /* Clear clip left , */\
- { 0x4620, "ICLCLPR"}, /* Clear clip right , */\
- { 0x4630, "ICLOCPM"}, /* Clear mic ocpok , */\
- { 0x4800, "IEVDDS"}, /* Enable por , */\
- { 0x4810, "IEPLLS"}, /* Enable pll lock , */\
- { 0x4820, "IEOTDS"}, /* Enable OTP alarm , */\
- { 0x4830, "IEOVDS"}, /* Enable OVP alarm , */\
- { 0x4840, "IEUVDS"}, /* Enable UVP alarm , */\
- { 0x4850, "IECLKS"}, /* Enable clocks stable , */\
- { 0x4860, "IEMTPB"}, /* Enable mtp busy , */\
- { 0x4870, "IENOCLK"}, /* Enable lost clk , */\
- { 0x4880, "IESPKS"}, /* Enable speaker error , */\
- { 0x4890, "IEACS"}, /* Enable cold started , */\
- { 0x48a0, "IESWS"}, /* Enable amplifier engage , */\
- { 0x48b0, "IEWDS"}, /* Enable watchdog , */\
- { 0x48c0, "IEAMPS"}, /* Enable enbl amp , */\
- { 0x48d0, "IEAREFS"}, /* Enable ref enable , */\
- { 0x48e0, "IEADCCR"}, /* Enable Control ADC , */\
- { 0x48f0, "IEBODNOK"}, /* Enable BOD , */\
- { 0x4900, "IEBSTCU"}, /* Enable DCDC current limiting , */\
- { 0x4910, "IEBSTHI"}, /* Enable DCDC active , */\
- { 0x4920, "IEBSTOC"}, /* Enable DCDC OCP , */\
- { 0x4930, "IEBSTPC"}, /* Enable bst peakcur , */\
- { 0x4940, "IEBSTVC"}, /* Enable DCDC level 1x , */\
- { 0x4950, "IEBST86"}, /* Enable DCDC level 1.14x , */\
- { 0x4960, "IEBST93"}, /* Enable DCDC level 1.07x , */\
- { 0x4970, "IERCVLD"}, /* Enable rcvldop ready , */\
- { 0x4980, "IEOCPL"}, /* Enable ocp alarm left , */\
- { 0x4990, "IEOCPR"}, /* Enable ocp alarm right , */\
- { 0x49a0, "IEMWSRC"}, /* Enable waits HW I2C settings , */\
- { 0x49b0, "IEMWCFC"}, /* Enable man wait cf config , */\
- { 0x49c0, "IEMWSMU"}, /* Enable man Audio mute sequence , */\
- { 0x49d0, "IECFMER"}, /* Enable cfma err , */\
- { 0x49e0, "IECFMAC"}, /* Enable cfma ack , */\
- { 0x49f0, "IECLKOOR"}, /* Enable flag_clk_out_of_range , */\
- { 0x4a00, "IETDMER"}, /* Enable tdm error , */\
- { 0x4a10, "IECLPL"}, /* Enable clip left , */\
- { 0x4a20, "IECLPR"}, /* Enable clip right , */\
- { 0x4a30, "IEOCPM1"}, /* Enable mic ocpok , */\
- { 0x4c00, "IPOVDDS"}, /* Polarity por , */\
- { 0x4c10, "IPOPLLS"}, /* Polarity pll lock , */\
- { 0x4c20, "IPOOTDS"}, /* Polarity OTP alarm , */\
- { 0x4c30, "IPOOVDS"}, /* Polarity OVP alarm , */\
- { 0x4c40, "IPOUVDS"}, /* Polarity UVP alarm , */\
- { 0x4c50, "IPOCLKS"}, /* Polarity clocks stable , */\
- { 0x4c60, "IPOMTPB"}, /* Polarity mtp busy , */\
- { 0x4c70, "IPONOCLK"}, /* Polarity lost clk , */\
- { 0x4c80, "IPOSPKS"}, /* Polarity speaker error , */\
- { 0x4c90, "IPOACS"}, /* Polarity cold started , */\
- { 0x4ca0, "IPOSWS"}, /* Polarity amplifier engage , */\
- { 0x4cb0, "IPOWDS"}, /* Polarity watchdog , */\
- { 0x4cc0, "IPOAMPS"}, /* Polarity enbl amp , */\
- { 0x4cd0, "IPOAREFS"}, /* Polarity ref enable , */\
- { 0x4ce0, "IPOADCCR"}, /* Polarity Control ADC , */\
- { 0x4cf0, "IPOBODNOK"}, /* Polarity BOD , */\
- { 0x4d00, "IPOBSTCU"}, /* Polarity DCDC current limiting , */\
- { 0x4d10, "IPOBSTHI"}, /* Polarity DCDC active , */\
- { 0x4d20, "IPOBSTOC"}, /* Polarity DCDC OCP , */\
- { 0x4d30, "IPOBSTPC"}, /* Polarity bst peakcur , */\
- { 0x4d40, "IPOBSTVC"}, /* Polarity DCDC level 1x , */\
- { 0x4d50, "IPOBST86"}, /* Polarity DCDC level 1.14x , */\
- { 0x4d60, "IPOBST93"}, /* Polarity DCDC level 1.07x , */\
- { 0x4d70, "IPORCVLD"}, /* Polarity rcvldop ready , */\
- { 0x4d80, "IPOOCPL"}, /* Polarity ocp alarm left , */\
- { 0x4d90, "IPOOCPR"}, /* Polarity ocp alarm right , */\
- { 0x4da0, "IPOMWSRC"}, /* Polarity waits HW I2C settings , */\
- { 0x4db0, "IPOMWCFC"}, /* Polarity man wait cf config , */\
- { 0x4dc0, "IPOMWSMU"}, /* Polarity man audio mute sequence , */\
- { 0x4dd0, "IPOCFMER"}, /* Polarity cfma err , */\
- { 0x4de0, "IPOCFMAC"}, /* Polarity cfma ack , */\
- { 0x4df0, "IPCLKOOR"}, /* Polarity flag_clk_out_of_range , */\
- { 0x4e00, "IPOTDMER"}, /* Polarity tdm error , */\
- { 0x4e10, "IPOCLPL"}, /* Polarity clip left , */\
- { 0x4e20, "IPOCLPR"}, /* Polarity clip right , */\
- { 0x4e30, "IPOOCPM"}, /* Polarity mic ocpok , */\
- { 0x5001, "BSSCR"}, /* Battery protection attack Time , */\
- { 0x5023, "BSST"}, /* Battery protection threshold voltage level , */\
- { 0x5061, "BSSRL"}, /* Battery protection maximum reduction , */\
- { 0x5082, "BSSRR"}, /* Battery protection release time , */\
- { 0x50b1, "BSSHY"}, /* Battery protection hysteresis , */\
- { 0x50e0, "BSSR"}, /* Battery voltage read out , */\
- { 0x50f0, "BSSBY"}, /* Bypass HW clipper , */\
- { 0x5100, "BSSS"}, /* Vbat prot steepness , */\
- { 0x5110, "INTSMUTE"}, /* Soft mute HW , */\
- { 0x5120, "CFSML"}, /* Soft mute FW left , */\
- { 0x5130, "CFSMR"}, /* Soft mute FW right , */\
- { 0x5140, "HPFBYPL"}, /* Bypass HPF left , */\
- { 0x5150, "HPFBYPR"}, /* Bypass HPF right , */\
- { 0x5160, "DPSAL"}, /* Enable DPSA left , */\
- { 0x5170, "DPSAR"}, /* Enable DPSA right , */\
- { 0x5187, "VOL"}, /* FW volume control for primary audio channel , */\
- { 0x5200, "HNDSFRCV"}, /* Selection receiver , */\
- { 0x5222, "CLIPCTRL"}, /* Clip control setting , */\
- { 0x5257, "AMPGAIN"}, /* Amplifier gain , */\
- { 0x52d0, "SLOPEE"}, /* Enables slope control , */\
- { 0x52e1, "SLOPESET"}, /* Set slope , */\
- { 0x5a07, "VOLSEC"}, /* FW volume control for secondary audio channel , */\
- { 0x5a87, "SWPROFIL"}, /* Software profile data , */\
- { 0x7002, "DCVO"}, /* Boost voltage , */\
- { 0x7033, "DCMCC"}, /* Max coil current , */\
- { 0x7071, "DCCV"}, /* Coil Value , */\
- { 0x7090, "DCIE"}, /* Adaptive boost mode , */\
- { 0x70a0, "DCSR"}, /* Soft ramp up/down , */\
- { 0x70b2, "DCSYNCP"}, /* DCDC synchronization off + 7 positions , */\
- { 0x70e0, "DCDIS"}, /* DCDC on/off , */\
- { 0x9000, "RST"}, /* Reset , */\
- { 0x9011, "DMEM"}, /* Target memory , */\
- { 0x9030, "AIF"}, /* Auto increment , */\
- { 0x9040, "CFINT"}, /* Interrupt - auto clear , */\
- { 0x9050, "CFCGATE"}, /* Coolflux clock gating disabling control , */\
- { 0x9080, "REQCMD"}, /* Firmware event request rpc command , */\
- { 0x9090, "REQRST"}, /* Firmware event request reset restart , */\
- { 0x90a0, "REQMIPS"}, /* Firmware event request short on mips , */\
- { 0x90b0, "REQMUTED"}, /* Firmware event request mute sequence ready , */\
- { 0x90c0, "REQVOL"}, /* Firmware event request volume ready , */\
- { 0x90d0, "REQDMG"}, /* Firmware event request speaker damage detected , */\
- { 0x90e0, "REQCAL"}, /* Firmware event request calibration completed , */\
- { 0x90f0, "REQRSV"}, /* Firmware event request reserved , */\
- { 0x910f, "MADD"}, /* Memory address , */\
- { 0x920f, "MEMA"}, /* Activate memory access , */\
- { 0x9307, "ERR"}, /* Error flags , */\
- { 0x9387, "ACK"}, /* Acknowledge of requests , */\
- { 0x9380, "ACKCMD"}, /* Firmware event acknowledge rpc command , */\
- { 0x9390, "ACKRST"}, /* Firmware event acknowledge reset restart , */\
- { 0x93a0, "ACKMIPS"}, /* Firmware event acknowledge short on mips , */\
- { 0x93b0, "ACKMUTED"}, /* Firmware event acknowledge mute sequence ready , */\
- { 0x93c0, "ACKVOL"}, /* Firmware event acknowledge volume ready , */\
- { 0x93d0, "ACKDMG"}, /* Firmware event acknowledge speaker damage detected, */\
- { 0x93e0, "ACKCAL"}, /* Firmware event acknowledge calibration completed , */\
- { 0x93f0, "ACKRSV"}, /* Firmware event acknowledge reserved , */\
- { 0xa107, "MTPK"}, /* MTP KEY2 register , */\
- { 0xa200, "KEY1LOCKED"}, /* Indicates KEY1 is locked , */\
- { 0xa210, "KEY2LOCKED"}, /* Indicates KEY2 is locked , */\
- { 0xa360, "CIMTP"}, /* Start copying data from I2C mtp registers to mtp , */\
- { 0xa50f, "MTPRDMSB"}, /* MSB word of MTP manual read data , */\
- { 0xa60f, "MTPRDLSB"}, /* LSB word of MTP manual read data , */\
- { 0xb108, "EXTTS"}, /* External temperature (C) , */\
- { 0xb190, "TROS"}, /* Select temp Speaker calibration , */\
- { 0xf000, "MTPOTC"}, /* Calibration schedule , */\
- { 0xf010, "MTPEX"}, /* Calibration Ron executed , */\
- { 0xf020, "DCMCCAPI"}, /* Calibration current limit DCDC , */\
- { 0xf030, "DCMCCSB"}, /* Sign bit for delta calibration current limit DCDC , */\
- { 0xf042, "USERDEF"}, /* Calibration delta current limit DCDC , */\
- { 0xf40f, "R25CL"}, /* Ron resistance of left channel speaker coil , */\
- { 0xf50f, "R25CR"}, /* Ron resistance of right channel speaker coil , */\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-
-#define TFA2_BITNAMETABLE static tfaBfName_t Tfa2BitNames[]= {\
- { 0x0, "powerdown"}, /* Powerdown selection , */\
- { 0x10, "reset"}, /* I2C Reset - Auto clear , */\
- { 0x20, "enbl_coolflux"}, /* Enable CoolFlux , */\
- { 0x30, "enbl_amplifier"}, /* Activate Amplifier , */\
- { 0x40, "enbl_boost"}, /* Activate DC-to-DC converter , */\
- { 0x50, "coolflux_configured"}, /* Coolflux configured , */\
- { 0x60, "sel_enbl_amplifier"}, /* CoolFlux controls amplifier , */\
- { 0x71, "int_pad_io"}, /* Interrupt config , */\
- { 0x91, "fs_pulse_sel"}, /* Audio sample reference , */\
- { 0xb0, "bypass_ocp"}, /* Bypass OCP , */\
- { 0xc0, "test_ocp"}, /* OCP testing control , */\
- { 0x101, "vamp_sel"}, /* Amplifier input selection , */\
- { 0x120, "src_set_configured"}, /* I2C configured , */\
- { 0x130, "execute_cold_start"}, /* Execute cold start , */\
- { 0x140, "enbl_osc1m_auto_off"}, /* Internal osc off at PWDN , */\
- { 0x150, "man_enbl_brown_out"}, /* Reaction on BOD , */\
- { 0x160, "enbl_bod"}, /* BOD Enable , */\
- { 0x170, "enbl_bod_hyst"}, /* BOD Hysteresis , */\
- { 0x181, "bod_delay"}, /* BOD filter , */\
- { 0x1a1, "bod_lvlsel"}, /* BOD threshold , */\
- { 0x1d0, "disable_mute_time_out"}, /* Time out SB mute sequence , */\
- { 0x1e0, "pwm_sel_rcv_ns"}, /* Noise shaper selection , */\
- { 0x1f0, "man_enbl_watchdog"}, /* Watchdog manager reaction , */\
- { 0x203, "audio_fs"}, /* Sample rate (fs) , */\
- { 0x240, "input_level"}, /* TDM output attenuation , */\
- { 0x255, "cs_frac_delay"}, /* V/I Fractional delay , */\
- { 0x2b0, "bypass_hvbat_filter"}, /* Bypass HVBAT filter , */\
- { 0x2c0, "ctrl_rcvldop_bypass"}, /* Receiver LDO bypass , */\
- { 0x30f, "device_rev"}, /* Revision info , */\
- { 0x401, "pll_clkin_sel"}, /* PLL external ref clock , */\
- { 0x420, "pll_clkin_sel_osc"}, /* PLL internal ref clock , */\
- { 0x500, "enbl_spkr_ss_left"}, /* Enable left channel , */\
- { 0x510, "enbl_spkr_ss_right"}, /* Enable right channel , */\
- { 0x520, "enbl_volsense_left"}, /* Voltage sense left , */\
- { 0x530, "enbl_volsense_right"}, /* Voltage sense right , */\
- { 0x540, "enbl_cursense_left"}, /* Current sense left , */\
- { 0x550, "enbl_cursense_right"}, /* Current sense right , */\
- { 0x560, "enbl_pdm_ss"}, /* Sub-system PDM , */\
- { 0xd00, "side_tone_gain_sel"}, /* PDM side tone gain selector , */\
- { 0xd18, "side_tone_gain"}, /* Side tone gain , */\
- { 0xda0, "mute_side_tone"}, /* Side tone soft mute , */\
- { 0xe06, "ctrl_digtoana"}, /* Register for the host SW to record the current active vstep, */\
- { 0xe70, "enbl_cmfb_left"}, /* Current sense common mode feedback control for left channel, */\
- { 0xf0f, "hidden_code"}, /* 5A6Bh, 23147d to access registers (default for engineering), */\
- { 0x1000, "flag_por"}, /* POR , */\
- { 0x1010, "flag_pll_lock"}, /* PLL lock , */\
- { 0x1020, "flag_otpok"}, /* OTP alarm , */\
- { 0x1030, "flag_ovpok"}, /* OVP alarm , */\
- { 0x1040, "flag_uvpok"}, /* UVP alarm , */\
- { 0x1050, "flag_clocks_stable"}, /* Clocks stable , */\
- { 0x1060, "flag_mtp_busy"}, /* MTP busy , */\
- { 0x1070, "flag_lost_clk"}, /* Lost clock , */\
- { 0x1080, "flag_cf_speakererror"}, /* Speaker error , */\
- { 0x1090, "flag_cold_started"}, /* Cold Start , */\
- { 0x10a0, "flag_engage"}, /* Amplifier engage , */\
- { 0x10b0, "flag_watchdog_reset"}, /* Watchdog , */\
- { 0x10c0, "flag_enbl_amp"}, /* Amplifier enable , */\
- { 0x10d0, "flag_enbl_ref"}, /* References enable , */\
- { 0x10e0, "flag_adc10_ready"}, /* Control ADC , */\
- { 0x10f0, "flag_bod_vddd_nok"}, /* BOD , */\
- { 0x1100, "flag_bst_bstcur"}, /* DCDC current limiting , */\
- { 0x1110, "flag_bst_hiz"}, /* DCDC active , */\
- { 0x1120, "flag_bst_ocpok"}, /* DCDC OCP nmos , */\
- { 0x1130, "flag_bst_peakcur"}, /* Indicates current is max in DC-to-DC converter , */\
- { 0x1140, "flag_bst_voutcomp"}, /* DCDC level 1x , */\
- { 0x1150, "flag_bst_voutcomp86"}, /* DCDC level 1.14x , */\
- { 0x1160, "flag_bst_voutcomp93"}, /* DCDC level 1.07x , */\
- { 0x1170, "flag_soft_mute_busy"}, /* side tone (un)mute busy , */\
- { 0x1180, "flag_soft_mute_state"}, /* side tone mute state , */\
- { 0x1190, "flag_tdm_lut_error"}, /* TDM LUT error , */\
- { 0x11a2, "flag_tdm_status"}, /* TDM status bits , */\
- { 0x11d0, "flag_tdm_error"}, /* TDM error , */\
- { 0x11e0, "flag_haptic_busy"}, /* Status haptic driver , */\
- { 0x1200, "flag_ocpokap_left"}, /* OCPOK pmos A left , */\
- { 0x1210, "flag_ocpokan_left"}, /* OCPOK nmos A left , */\
- { 0x1220, "flag_ocpokbp_left"}, /* OCPOK pmos B left , */\
- { 0x1230, "flag_ocpokbn_left"}, /* OCPOK nmos B left , */\
- { 0x1240, "flag_clipa_high_left"}, /* Clipping A left to Vddp , */\
- { 0x1250, "flag_clipa_low_left"}, /* Clipping A left to gnd , */\
- { 0x1260, "flag_clipb_high_left"}, /* Clipping B left to Vddp , */\
- { 0x1270, "flag_clipb_low_left"}, /* Clipping B left to gnd , */\
- { 0x1280, "flag_ocpokap_rcv"}, /* OCPOK pmos A RCV , */\
- { 0x1290, "flag_ocpokan_rcv"}, /* OCPOK nmos A RCV , */\
- { 0x12a0, "flag_ocpokbp_rcv"}, /* OCPOK pmos B RCV , */\
- { 0x12b0, "flag_ocpokbn_rcv"}, /* OCPOK nmos B RCV , */\
- { 0x12c0, "flag_rcvldop_ready"}, /* RCV LDO regulates , */\
- { 0x12d0, "flag_rcvldop_bypassready"}, /* Receiver LDO ready , */\
- { 0x12e0, "flag_ocp_alarm_left"}, /* OCP left amplifier , */\
- { 0x12f0, "flag_clip_left"}, /* Amplifier left clipping , */\
- { 0x1300, "flag_ocpokap_right"}, /* OCPOK pmos A right , */\
- { 0x1310, "flag_ocpokan_right"}, /* OCPOK nmos A right , */\
- { 0x1320, "flag_ocpokbp_right"}, /* OCPOK pmos B right , */\
- { 0x1330, "flag_ocpokbn_right"}, /* OCPOK nmos B right , */\
- { 0x1340, "flag_clipa_high_right"}, /* Clipping A right to Vddp , */\
- { 0x1350, "flag_clipa_low_right"}, /* Clipping A right to gnd , */\
- { 0x1360, "flag_clipb_high_right"}, /* Clipping B left to Vddp , */\
- { 0x1370, "flag_clipb_low_right"}, /* Clipping B right to gnd , */\
- { 0x1380, "flag_ocp_alarm_right"}, /* OCP right amplifier , */\
- { 0x1390, "flag_clip_right"}, /* Amplifier right clipping , */\
- { 0x13a0, "flag_mic_ocpok"}, /* OCPOK MICVDD , */\
- { 0x13b0, "flag_man_alarm_state"}, /* Alarm state , */\
- { 0x13c0, "flag_man_wait_src_settings"}, /* Wait HW I2C settings , */\
- { 0x13d0, "flag_man_wait_cf_config"}, /* Wait CF config , */\
- { 0x13e0, "flag_man_start_mute_audio"}, /* Audio mute sequence , */\
- { 0x13f0, "flag_man_operating_state"}, /* Operating state , */\
- { 0x1400, "flag_cf_speakererror_left"}, /* Left speaker status , */\
- { 0x1410, "flag_cf_speakererror_right"}, /* Right speaker status , */\
- { 0x1420, "flag_clk_out_of_range"}, /* External clock status , */\
- { 0x1433, "man_state"}, /* Device manager status , */\
- { 0x1509, "bat_adc"}, /* Battery voltage (V) , */\
- { 0x1608, "temp_adc"}, /* IC Temperature (C) , */\
- { 0x2003, "tdm_usecase"}, /* Usecase setting , */\
- { 0x2040, "tdm_enable"}, /* Enable interface , */\
- { 0x2050, "tdm_mode"}, /* Slave/master , */\
- { 0x2060, "tdm_clk_inversion"}, /* Reception data to BCK clock , */\
- { 0x2073, "tdm_fs_ws_length"}, /* FS length (master mode only) , */\
- { 0x20b0, "tdm_fs_ws_polarity"}, /* FS polarity , */\
- { 0x20c3, "tdm_nbck"}, /* N-BCK's in FS , */\
- { 0x2103, "tdm_nb_of_slots"}, /* N-slots in Frame , */\
- { 0x2144, "tdm_slot_length"}, /* N-bits in slot , */\
- { 0x2194, "tdm_bits_remaining"}, /* N-bits remaining , */\
- { 0x21e0, "tdm_data_delay"}, /* data delay to FS , */\
- { 0x21f0, "tdm_data_adjustment"}, /* data adjustment , */\
- { 0x2201, "tdm_audio_sample_compression"}, /* Received audio compression , */\
- { 0x2224, "tdm_sample_size"}, /* Sample size per slot , */\
- { 0x2271, "tdm_txdata_format"}, /* Format unused bits , */\
- { 0x2291, "tdm_txdata_format_unused_slot_sd0"}, /* Format unused slots GAINIO , */\
- { 0x22b1, "tdm_txdata_format_unused_slot_sd1"}, /* Format unused slots DIO1 , */\
- { 0x22d1, "tdm_txdata_format_unused_slot_sd2"}, /* Format unused slots DIO2 , */\
- { 0x2300, "tdm_sink0_enable"}, /* Control gainin (not used in DSP) , */\
- { 0x2310, "tdm_sink1_enable"}, /* Control audio left , */\
- { 0x2320, "tdm_sink2_enable"}, /* Control audio right , */\
- { 0x2330, "tdm_source0_enable"}, /* Control gainout (not used in DSP) , */\
- { 0x2340, "tdm_source1_enable"}, /* Control voltage sense right , */\
- { 0x2350, "tdm_source2_enable"}, /* Control current sense right , */\
- { 0x2360, "tdm_source3_enable"}, /* Voltage sense left control , */\
- { 0x2370, "tdm_source4_enable"}, /* Current sense left control , */\
- { 0x2380, "tdm_source5_enable"}, /* DSP out right control , */\
- { 0x2390, "tdm_source6_enable"}, /* DSP out left control , */\
- { 0x23a0, "tdm_source7_enable"}, /* AEC ref left control , */\
- { 0x23b0, "tdm_source8_enable"}, /* AEC ref right control , */\
- { 0x23c0, "tdm_source9_enable"}, /* PDM 1 control , */\
- { 0x23d0, "tdm_source10_enable"}, /* PDM 2 control , */\
- { 0x2401, "tdm_sink0_io"}, /* IO gainin (not used in DSP) , */\
- { 0x2421, "tdm_sink1_io"}, /* IO audio left , */\
- { 0x2441, "tdm_sink2_io"}, /* IO audio right , */\
- { 0x2461, "tdm_source0_io"}, /* IO gainout (not used in DSP) , */\
- { 0x2481, "tdm_source1_io"}, /* IO voltage sense right , */\
- { 0x24a1, "tdm_source2_io"}, /* IO current sense right , */\
- { 0x24c1, "tdm_source3_io"}, /* IO voltage sense left , */\
- { 0x24e1, "tdm_source4_io"}, /* IO current sense left , */\
- { 0x2501, "tdm_source5_io"}, /* IO dspout right , */\
- { 0x2521, "tdm_source6_io"}, /* IO dspout left , */\
- { 0x2541, "tdm_source7_io"}, /* IO AEC ref left control , */\
- { 0x2561, "tdm_source8_io"}, /* IO AEC ref right control , */\
- { 0x2581, "tdm_source9_io"}, /* IO pdm1 , */\
- { 0x25a1, "tdm_source10_io"}, /* IO pdm2 , */\
- { 0x2603, "tdm_sink0_slot"}, /* Position gainin (not used in DSP) , */\
- { 0x2643, "tdm_sink1_slot"}, /* Position audio left , */\
- { 0x2683, "tdm_sink2_slot"}, /* Position audio right , */\
- { 0x26c3, "tdm_source0_slot"}, /* Position gainout (not used in DSP) , */\
- { 0x2703, "tdm_source1_slot"}, /* Position voltage sense right , */\
- { 0x2743, "tdm_source2_slot"}, /* Position current sense right , */\
- { 0x2783, "tdm_source3_slot"}, /* Position voltage sense left , */\
- { 0x27c3, "tdm_source4_slot"}, /* Position current sense left , */\
- { 0x2803, "tdm_source5_slot"}, /* Position dspout right , */\
- { 0x2843, "tdm_source6_slot"}, /* Position dspout left , */\
- { 0x2883, "tdm_source7_slot"}, /* Position AEC ref left control , */\
- { 0x28c3, "tdm_source8_slot"}, /* Position AEC ref right control , */\
- { 0x2903, "tdm_source9_slot"}, /* Position pdm1 , */\
- { 0x2943, "tdm_source10_slot"}, /* Position pdm2 , */\
- { 0x3100, "pdm_mode"}, /* PDM control , */\
- { 0x3111, "pdm_side_tone_sel"}, /* Side tone input , */\
- { 0x3130, "pdm_left_sel"}, /* PDM data selection for left channel during PDM direct mode, */\
- { 0x3140, "pdm_right_sel"}, /* PDM data selection for right channel during PDM direct mode, */\
- { 0x3150, "enbl_micvdd"}, /* Enable MICVDD , */\
- { 0x3160, "bypass_micvdd_ocp"}, /* Bypass control for the MICVDD OCP flag processing , */\
- { 0x3201, "pdm_nbck"}, /* PDM BCK/Fs ratio , */\
- { 0x3223, "pdm_gain"}, /* PDM gain , */\
- { 0x3263, "sel_pdm_out_data"}, /* PDM output selection - RE/FE data combination , */\
- { 0x32a0, "sel_cf_haptic_data"}, /* Select the source for haptic data output (not for customer), */\
- { 0x3307, "haptic_duration"}, /* Duration (ms) , */\
- { 0x3387, "haptic_data"}, /* DC value (FFS) , */\
- { 0x3403, "gpio_datain"}, /* Receiving value , */\
- { 0x3500, "gpio_ctrl"}, /* GPIO master control over GPIO1/2 ports (not for customer), */\
- { 0x3513, "gpio_dir"}, /* Configuration , */\
- { 0x3553, "gpio_dataout"}, /* Transmitting value , */\
- { 0x4000, "int_out_flag_por"}, /* Status POR , */\
- { 0x4010, "int_out_flag_pll_lock"}, /* Status PLL lock , */\
- { 0x4020, "int_out_flag_otpok"}, /* Status OTP alarm , */\
- { 0x4030, "int_out_flag_ovpok"}, /* Status OVP alarm , */\
- { 0x4040, "int_out_flag_uvpok"}, /* Status UVP alarm , */\
- { 0x4050, "int_out_flag_clocks_stable"}, /* Status clocks stable , */\
- { 0x4060, "int_out_flag_mtp_busy"}, /* Status MTP busy , */\
- { 0x4070, "int_out_flag_lost_clk"}, /* Status lost clock , */\
- { 0x4080, "int_out_flag_cf_speakererror"}, /* Status speaker error , */\
- { 0x4090, "int_out_flag_cold_started"}, /* Status cold start , */\
- { 0x40a0, "int_out_flag_engage"}, /* Status amplifier engage , */\
- { 0x40b0, "int_out_flag_watchdog_reset"}, /* Status watchdog , */\
- { 0x40c0, "int_out_flag_enbl_amp"}, /* Status amplifier enable , */\
- { 0x40d0, "int_out_flag_enbl_ref"}, /* Status Ref enable , */\
- { 0x40e0, "int_out_flag_adc10_ready"}, /* Status Control ADC , */\
- { 0x40f0, "int_out_flag_bod_vddd_nok"}, /* Status BOD , */\
- { 0x4100, "int_out_flag_bst_bstcur"}, /* Status DCDC current limiting , */\
- { 0x4110, "int_out_flag_bst_hiz"}, /* Status DCDC active , */\
- { 0x4120, "int_out_flag_bst_ocpok"}, /* Status DCDC OCP , */\
- { 0x4130, "int_out_flag_bst_peakcur"}, /* Status bst peakcur , */\
- { 0x4140, "int_out_flag_bst_voutcomp"}, /* Status DCDC level 1x , */\
- { 0x4150, "int_out_flag_bst_voutcomp86"}, /* Status DCDC level 1.14x , */\
- { 0x4160, "int_out_flag_bst_voutcomp93"}, /* Status DCDC level 1.07x , */\
- { 0x4170, "int_out_flag_rcvldop_ready"}, /* Status rcvldop ready , */\
- { 0x4180, "int_out_flag_ocp_alarm_left"}, /* Status ocp alarm left , */\
- { 0x4190, "int_out_flag_ocp_alarm_right"}, /* Status ocp alarm right , */\
- { 0x41a0, "int_out_flag_man_wait_src_settings"}, /* Status Waits HW I2C settings , */\
- { 0x41b0, "int_out_flag_man_wait_cf_config"}, /* Status waits CF config , */\
- { 0x41c0, "int_out_flag_man_start_mute_audio"}, /* Status Audio mute sequence , */\
- { 0x41d0, "int_out_flag_cfma_err"}, /* Status cfma error , */\
- { 0x41e0, "int_out_flag_cfma_ack"}, /* Status cfma ack , */\
- { 0x41f0, "int_out_flag_clk_out_of_range"}, /* Status flag_clk_out_of_range , */\
- { 0x4200, "int_out_flag_tdm_error"}, /* Status tdm error , */\
- { 0x4210, "int_out_flag_clip_left"}, /* Status clip left , */\
- { 0x4220, "int_out_flag_clip_right"}, /* Status clip right , */\
- { 0x4230, "int_out_flag_mic_ocpok"}, /* Status mic ocpok , */\
- { 0x4400, "int_in_flag_por"}, /* Clear POR , */\
- { 0x4410, "int_in_flag_pll_lock"}, /* Clear PLL lock , */\
- { 0x4420, "int_in_flag_otpok"}, /* Clear OTP alarm , */\
- { 0x4430, "int_in_flag_ovpok"}, /* Clear OVP alarm , */\
- { 0x4440, "int_in_flag_uvpok"}, /* Clear UVP alarm , */\
- { 0x4450, "int_in_flag_clocks_stable"}, /* Clear clocks stable , */\
- { 0x4460, "int_in_flag_mtp_busy"}, /* Clear mtp busy , */\
- { 0x4470, "int_in_flag_lost_clk"}, /* Clear lost clk , */\
- { 0x4480, "int_in_flag_cf_speakererror"}, /* Clear speaker error , */\
- { 0x4490, "int_in_flag_cold_started"}, /* Clear cold started , */\
- { 0x44a0, "int_in_flag_engage"}, /* Clear amplifier engage , */\
- { 0x44b0, "int_in_flag_watchdog_reset"}, /* Clear watchdog , */\
- { 0x44c0, "int_in_flag_enbl_amp"}, /* Clear enbl amp , */\
- { 0x44d0, "int_in_flag_enbl_ref"}, /* Clear ref enable , */\
- { 0x44e0, "int_in_flag_adc10_ready"}, /* Clear control ADC , */\
- { 0x44f0, "int_in_flag_bod_vddd_nok"}, /* Clear BOD , */\
- { 0x4500, "int_in_flag_bst_bstcur"}, /* Clear DCDC current limiting , */\
- { 0x4510, "int_in_flag_bst_hiz"}, /* Clear DCDC active , */\
- { 0x4520, "int_in_flag_bst_ocpok"}, /* Clear DCDC OCP , */\
- { 0x4530, "int_in_flag_bst_peakcur"}, /* Clear bst peakcur , */\
- { 0x4540, "int_in_flag_bst_voutcomp"}, /* Clear DCDC level 1x , */\
- { 0x4550, "int_in_flag_bst_voutcomp86"}, /* Clear DCDC level 1.14x , */\
- { 0x4560, "int_in_flag_bst_voutcomp93"}, /* Clear DCDC level 1.07x , */\
- { 0x4570, "int_in_flag_rcvldop_ready"}, /* Clear rcvldop ready , */\
- { 0x4580, "int_in_flag_ocp_alarm_left"}, /* Clear ocp alarm left , */\
- { 0x4590, "int_in_flag_ocp_alarm_right"}, /* Clear ocp alarm right , */\
- { 0x45a0, "int_in_flag_man_wait_src_settings"}, /* Clear wait HW I2C settings , */\
- { 0x45b0, "int_in_flag_man_wait_cf_config"}, /* Clear wait cf config , */\
- { 0x45c0, "int_in_flag_man_start_mute_audio"}, /* Clear audio mute sequence , */\
- { 0x45d0, "int_in_flag_cfma_err"}, /* Clear cfma err , */\
- { 0x45e0, "int_in_flag_cfma_ack"}, /* Clear cfma ack , */\
- { 0x45f0, "int_in_flag_clk_out_of_range"}, /* Clear flag_clk_out_of_range , */\
- { 0x4600, "int_in_flag_tdm_error"}, /* Clear tdm error , */\
- { 0x4610, "int_in_flag_clip_left"}, /* Clear clip left , */\
- { 0x4620, "int_in_flag_clip_right"}, /* Clear clip right , */\
- { 0x4630, "int_in_flag_mic_ocpok"}, /* Clear mic ocpok , */\
- { 0x4800, "int_enable_flag_por"}, /* Enable por , */\
- { 0x4810, "int_enable_flag_pll_lock"}, /* Enable pll lock , */\
- { 0x4820, "int_enable_flag_otpok"}, /* Enable OTP alarm , */\
- { 0x4830, "int_enable_flag_ovpok"}, /* Enable OVP alarm , */\
- { 0x4840, "int_enable_flag_uvpok"}, /* Enable UVP alarm , */\
- { 0x4850, "int_enable_flag_clocks_stable"}, /* Enable clocks stable , */\
- { 0x4860, "int_enable_flag_mtp_busy"}, /* Enable mtp busy , */\
- { 0x4870, "int_enable_flag_lost_clk"}, /* Enable lost clk , */\
- { 0x4880, "int_enable_flag_cf_speakererror"}, /* Enable speaker error , */\
- { 0x4890, "int_enable_flag_cold_started"}, /* Enable cold started , */\
- { 0x48a0, "int_enable_flag_engage"}, /* Enable amplifier engage , */\
- { 0x48b0, "int_enable_flag_watchdog_reset"}, /* Enable watchdog , */\
- { 0x48c0, "int_enable_flag_enbl_amp"}, /* Enable enbl amp , */\
- { 0x48d0, "int_enable_flag_enbl_ref"}, /* Enable ref enable , */\
- { 0x48e0, "int_enable_flag_adc10_ready"}, /* Enable Control ADC , */\
- { 0x48f0, "int_enable_flag_bod_vddd_nok"}, /* Enable BOD , */\
- { 0x4900, "int_enable_flag_bst_bstcur"}, /* Enable DCDC current limiting , */\
- { 0x4910, "int_enable_flag_bst_hiz"}, /* Enable DCDC active , */\
- { 0x4920, "int_enable_flag_bst_ocpok"}, /* Enable DCDC OCP , */\
- { 0x4930, "int_enable_flag_bst_peakcur"}, /* Enable bst peakcur , */\
- { 0x4940, "int_enable_flag_bst_voutcomp"}, /* Enable DCDC level 1x , */\
- { 0x4950, "int_enable_flag_bst_voutcomp86"}, /* Enable DCDC level 1.14x , */\
- { 0x4960, "int_enable_flag_bst_voutcomp93"}, /* Enable DCDC level 1.07x , */\
- { 0x4970, "int_enable_flag_rcvldop_ready"}, /* Enable rcvldop ready , */\
- { 0x4980, "int_enable_flag_ocp_alarm_left"}, /* Enable ocp alarm left , */\
- { 0x4990, "int_enable_flag_ocp_alarm_right"}, /* Enable ocp alarm right , */\
- { 0x49a0, "int_enable_flag_man_wait_src_settings"}, /* Enable waits HW I2C settings , */\
- { 0x49b0, "int_enable_flag_man_wait_cf_config"}, /* Enable man wait cf config , */\
- { 0x49c0, "int_enable_flag_man_start_mute_audio"}, /* Enable man Audio mute sequence , */\
- { 0x49d0, "int_enable_flag_cfma_err"}, /* Enable cfma err , */\
- { 0x49e0, "int_enable_flag_cfma_ack"}, /* Enable cfma ack , */\
- { 0x49f0, "int_enable_flag_clk_out_of_range"}, /* Enable flag_clk_out_of_range , */\
- { 0x4a00, "int_enable_flag_tdm_error"}, /* Enable tdm error , */\
- { 0x4a10, "int_enable_flag_clip_left"}, /* Enable clip left , */\
- { 0x4a20, "int_enable_flag_clip_right"}, /* Enable clip right , */\
- { 0x4a30, "int_enable_flag_mic_ocpok"}, /* Enable mic ocpok , */\
- { 0x4c00, "int_polarity_flag_por"}, /* Polarity por , */\
- { 0x4c10, "int_polarity_flag_pll_lock"}, /* Polarity pll lock , */\
- { 0x4c20, "int_polarity_flag_otpok"}, /* Polarity OTP alarm , */\
- { 0x4c30, "int_polarity_flag_ovpok"}, /* Polarity OVP alarm , */\
- { 0x4c40, "int_polarity_flag_uvpok"}, /* Polarity UVP alarm , */\
- { 0x4c50, "int_polarity_flag_clocks_stable"}, /* Polarity clocks stable , */\
- { 0x4c60, "int_polarity_flag_mtp_busy"}, /* Polarity mtp busy , */\
- { 0x4c70, "int_polarity_flag_lost_clk"}, /* Polarity lost clk , */\
- { 0x4c80, "int_polarity_flag_cf_speakererror"}, /* Polarity speaker error , */\
- { 0x4c90, "int_polarity_flag_cold_started"}, /* Polarity cold started , */\
- { 0x4ca0, "int_polarity_flag_engage"}, /* Polarity amplifier engage , */\
- { 0x4cb0, "int_polarity_flag_watchdog_reset"}, /* Polarity watchdog , */\
- { 0x4cc0, "int_polarity_flag_enbl_amp"}, /* Polarity enbl amp , */\
- { 0x4cd0, "int_polarity_flag_enbl_ref"}, /* Polarity ref enable , */\
- { 0x4ce0, "int_polarity_flag_adc10_ready"}, /* Polarity Control ADC , */\
- { 0x4cf0, "int_polarity_flag_bod_vddd_nok"}, /* Polarity BOD , */\
- { 0x4d00, "int_polarity_flag_bst_bstcur"}, /* Polarity DCDC current limiting , */\
- { 0x4d10, "int_polarity_flag_bst_hiz"}, /* Polarity DCDC active , */\
- { 0x4d20, "int_polarity_flag_bst_ocpok"}, /* Polarity DCDC OCP , */\
- { 0x4d30, "int_polarity_flag_bst_peakcur"}, /* Polarity bst peakcur , */\
- { 0x4d40, "int_polarity_flag_bst_voutcomp"}, /* Polarity DCDC level 1x , */\
- { 0x4d50, "int_polarity_flag_bst_voutcomp86"}, /* Polarity DCDC level 1.14x , */\
- { 0x4d60, "int_polarity_flag_bst_voutcomp93"}, /* Polarity DCDC level 1.07x , */\
- { 0x4d70, "int_polarity_flag_rcvldop_ready"}, /* Polarity rcvldop ready , */\
- { 0x4d80, "int_polarity_flag_ocp_alarm_left"}, /* Polarity ocp alarm left , */\
- { 0x4d90, "int_polarity_flag_ocp_alarm_right"}, /* Polarity ocp alarm right , */\
- { 0x4da0, "int_polarity_flag_man_wait_src_settings"}, /* Polarity waits HW I2C settings , */\
- { 0x4db0, "int_polarity_flag_man_wait_cf_config"}, /* Polarity man wait cf config , */\
- { 0x4dc0, "int_polarity_flag_man_start_mute_audio"}, /* Polarity man audio mute sequence , */\
- { 0x4dd0, "int_polarity_flag_cfma_err"}, /* Polarity cfma err , */\
- { 0x4de0, "int_polarity_flag_cfma_ack"}, /* Polarity cfma ack , */\
- { 0x4df0, "int_polarity_flag_clk_out_of_range"}, /* Polarity flag_clk_out_of_range , */\
- { 0x4e00, "int_polarity_flag_tdm_error"}, /* Polarity tdm error , */\
- { 0x4e10, "int_polarity_flag_clip_left"}, /* Polarity clip left , */\
- { 0x4e20, "int_polarity_flag_clip_right"}, /* Polarity clip right , */\
- { 0x4e30, "int_polarity_flag_mic_ocpok"}, /* Polarity mic ocpok , */\
- { 0x5001, "vbat_prot_attack_time"}, /* Battery protection attack Time , */\
- { 0x5023, "vbat_prot_thlevel"}, /* Battery protection threshold voltage level , */\
- { 0x5061, "vbat_prot_max_reduct"}, /* Battery protection maximum reduction , */\
- { 0x5082, "vbat_prot_release_time"}, /* Battery protection release time , */\
- { 0x50b1, "vbat_prot_hysterese"}, /* Battery protection hysteresis , */\
- { 0x50d0, "rst_min_vbat"}, /* Reset clipper - Auto clear , */\
- { 0x50e0, "sel_vbat"}, /* Battery voltage read out , */\
- { 0x50f0, "bypass_clipper"}, /* Bypass HW clipper , */\
- { 0x5100, "batsense_steepness"}, /* Vbat prot steepness , */\
- { 0x5110, "soft_mute"}, /* Soft mute HW , */\
- { 0x5120, "cf_mute_left"}, /* Soft mute FW left , */\
- { 0x5130, "cf_mute_right"}, /* Soft mute FW right , */\
- { 0x5140, "bypass_hp_left"}, /* Bypass HPF left , */\
- { 0x5150, "bypass_hp_right"}, /* Bypass HPF right , */\
- { 0x5160, "enbl_dpsa_left"}, /* Enable DPSA left , */\
- { 0x5170, "enbl_dpsa_right"}, /* Enable DPSA right , */\
- { 0x5187, "cf_volume"}, /* FW volume control for primary audio channel , */\
- { 0x5200, "ctrl_rcv"}, /* Selection receiver , */\
- { 0x5210, "ctrl_rcv_fb_100k"}, /* Selection of feedback resistor for receiver mode (not for customer), */\
- { 0x5222, "ctrl_cc"}, /* Clip control setting , */\
- { 0x5257, "gain"}, /* Amplifier gain , */\
- { 0x52d0, "ctrl_slopectrl"}, /* Enables slope control , */\
- { 0x52e1, "ctrl_slope"}, /* Set slope , */\
- { 0x5301, "dpsa_level"}, /* DPSA threshold levels , */\
- { 0x5321, "dpsa_release"}, /* DPSA Release time , */\
- { 0x5340, "clipfast"}, /* Clock selection for HW clipper for battery protection, */\
- { 0x5350, "bypass_lp"}, /* Bypass the low power filter inside temperature sensor, */\
- { 0x5360, "enbl_low_latency"}, /* CF low latency outputs for add module , */\
- { 0x5400, "first_order_mode"}, /* Overrule to 1st order mode of control stage when clipping, */\
- { 0x5410, "bypass_ctrlloop"}, /* Switch amplifier into open loop configuration , */\
- { 0x5420, "fb_hz"}, /* Feedback resistor set to high ohmic , */\
- { 0x5430, "icomp_engage"}, /* Engage of icomp , */\
- { 0x5440, "ctrl_kickback"}, /* Prevent double pulses of output stage , */\
- { 0x5450, "icomp_engage_overrule"}, /* To overrule the functional icomp_engage signal during validation, */\
- { 0x5503, "ctrl_dem"}, /* Enable DEM icomp and DEM one bit dac , */\
- { 0x5543, "ctrl_dem_mismatch"}, /* Enable DEM icomp mismatch for testing , */\
- { 0x5581, "dpsa_drive"}, /* Control of the number of power stage sections, total of 4 sections. Each section is 1/4 of the total power stages., */\
- { 0x560a, "enbl_amp_left"}, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually - Left channel, */\
- { 0x56b0, "enbl_engage_left"}, /* Enables/engage power stage and control loop - left channel, */\
- { 0x570a, "enbl_amp_right"}, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually - Right channel, */\
- { 0x57b0, "enbl_engage_right"}, /* Enables/engage power stage and control loop - right channel, */\
- { 0x5800, "hard_mute_left"}, /* Hard mute - PWM module left , */\
- { 0x5810, "hard_mute_right"}, /* Hard mute - PWM module right , */\
- { 0x5820, "pwm_shape"}, /* PWM shape , */\
- { 0x5830, "pwm_bitlength"}, /* PWM bit length in noise shaper , */\
- { 0x5844, "pwm_delay"}, /* PWM delay bits to set the delay, clockd is 1/(k*2048*fs), */\
- { 0x5890, "reclock_pwm"}, /* Reclock the pwm signal inside analog , */\
- { 0x58a0, "reclock_voltsense"}, /* Reclock the voltage sense pwm signal , */\
- { 0x58b0, "enbl_pwm_phase_shift_left"}, /* Control for pwm phase shift, inverted function - left channel, */\
- { 0x58c0, "enbl_pwm_phase_shift_right"}, /* Control for pwm phase shift - right channel , */\
- { 0x5900, "ctrl_rcvldop_pulldown"}, /* Pulldown of LDO (2.7V) , */\
- { 0x5910, "ctrl_rcvldop_test_comp"}, /* Enable testing of LDO comparator , */\
- { 0x5920, "ctrl_rcvldop_test_loadedldo"}, /* Load connected to rcvldo , */\
- { 0x5930, "enbl_rcvldop"}, /* Enables the LDO (2.7) , */\
- { 0x5a07, "cf_volume_sec"}, /* FW volume control for secondary audio channel , */\
- { 0x5a87, "sw_profile"}, /* Software profile data , */\
- { 0x7002, "boost_volt"}, /* Boost voltage , */\
- { 0x7033, "boost_cur"}, /* Max coil current , */\
- { 0x7071, "bst_coil_value"}, /* Coil Value , */\
- { 0x7090, "boost_intel"}, /* Adaptive boost mode , */\
- { 0x70a0, "boost_speed"}, /* Soft ramp up/down , */\
- { 0x70b2, "dcdc_synchronisation"}, /* DCDC synchronization off + 7 positions , */\
- { 0x70e0, "dcdcoff_mode"}, /* DCDC on/off , */\
- { 0x7104, "bst_drive"}, /* Binary coded drive setting for boost converter power stage, */\
- { 0x7151, "bst_scalecur"}, /* For testing direct control scale current , */\
- { 0x7174, "bst_slopecur"}, /* For testing direct control slope current , */\
- { 0x71c1, "bst_slope"}, /* Boost slope speed , */\
- { 0x71e0, "bst_bypass_bstcur"}, /* Bypass control for boost current settings , */\
- { 0x71f0, "bst_bypass_bstfoldback"}, /* Bypass control for boost foldback , */\
- { 0x7200, "enbl_bst_engage"}, /* Enable power stage dcdc controller , */\
- { 0x7210, "enbl_bst_hizcom"}, /* Enable hiz comparator , */\
- { 0x7220, "enbl_bst_peak2avg"}, /* Enable boost peak2avg functionality , */\
- { 0x7230, "enbl_bst_peakcur"}, /* Enable peak current , */\
- { 0x7240, "enbl_bst_power"}, /* Enable line of the powerstage , */\
- { 0x7250, "enbl_bst_slopecur"}, /* Enable bit of max-current dac , */\
- { 0x7260, "enbl_bst_voutcomp"}, /* Enable vout comparators , */\
- { 0x7270, "enbl_bst_voutcomp86"}, /* Enable vout-86 comparators , */\
- { 0x7280, "enbl_bst_voutcomp93"}, /* Enable vout-93 comparators , */\
- { 0x7290, "enbl_bst_windac"}, /* Enable window dac , */\
- { 0x72a5, "bst_windac"}, /* for testing direct control windac , */\
- { 0x7300, "boost_alg"}, /* Control for boost adaptive loop gain , */\
- { 0x7311, "boost_loopgain"}, /* DCDC boost loopgain setting , */\
- { 0x7332, "bst_freq"}, /* DCDC bost frequency control , */\
- { 0x8001, "sel_clk_cs"}, /* Current sense clock duty cycle control , */\
- { 0x8021, "micadc_speed"}, /* Current sense clock for MiCADC selection - 32/44.1/48 KHz Fs band only, */\
- { 0x8040, "cs_dc_offset"}, /* Current sense decimator offset control , */\
- { 0x8050, "cs_gain_control"}, /* Current sense gain control , */\
- { 0x8060, "cs_bypass_gc"}, /* Bypasses the CS gain correction , */\
- { 0x8087, "cs_gain"}, /* Current sense gain , */\
- { 0x8110, "invertpwm_left"}, /* Current sense common mode feedback pwm invert control for left channel, */\
- { 0x8122, "cmfb_gain_left"}, /* Current sense common mode feedback control gain for left channel, */\
- { 0x8154, "cmfb_offset_left"}, /* Current sense common mode feedback control offset for left channel, */\
- { 0x8200, "enbl_cmfb_right"}, /* Current sense common mode feedback control for right channel, */\
- { 0x8210, "invertpwm_right"}, /* Current sense common mode feedback pwm invert control for right channel, */\
- { 0x8222, "cmfb_gain_right"}, /* Current sense common mode feedback control gain for right channel, */\
- { 0x8254, "cmfb_offset_right"}, /* Current sense common mode feedback control offset for right channel, */\
- { 0x8305, "cs_ktemp"}, /* Current sense temperature compensation trimming (1 - VALUE*TEMP)*signal, */\
- { 0x8400, "cs_adc_bsoinv"}, /* Bitstream inversion for current sense ADC , */\
- { 0x8421, "cs_adc_hifreq"}, /* Frequency mode current sense ADC , */\
- { 0x8440, "cs_adc_nortz"}, /* Return to zero for current sense ADC , */\
- { 0x8453, "cs_adc_offset"}, /* Micadc ADC offset setting , */\
- { 0x8490, "cs_adc_slowdel"}, /* Select delay for current sense ADC (internal decision circuitry), */\
- { 0x84a4, "cs_adc_gain"}, /* Gain setting for current sense ADC (two's complement), */\
- { 0x8500, "cs_resonator_enable"}, /* Enable for resonator to improve SRN , */\
- { 0x8510, "cs_classd_tran_skip"}, /* Skip current sense connection during a classD amplifier transition, */\
- { 0x8530, "cs_inn_short"}, /* Short current sense negative to common mode , */\
- { 0x8540, "cs_inp_short"}, /* Short current sense positive to common mode , */\
- { 0x8550, "cs_ldo_bypass"}, /* Bypass current sense LDO , */\
- { 0x8560, "cs_ldo_pulldown"}, /* Pull down current sense LDO, only valid if left_enbl_cs_ldo is high, */\
- { 0x8574, "cs_ldo_voset"}, /* Current sense LDO voltage level setting (two's complement), */\
- { 0x8600, "enbl_cs_adc_left"}, /* Enable current sense ADC , */\
- { 0x8610, "enbl_cs_inn1_left"}, /* Enable connection of current sense negative1 , */\
- { 0x8630, "enbl_cs_inp1_left"}, /* Enable connection of current sense positive1 , */\
- { 0x8650, "enbl_cs_ldo_left"}, /* Enable current sense LDO , */\
- { 0x8660, "enbl_cs_nofloating_n_left"}, /* Connect current sense negative to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */\
- { 0x8670, "enbl_cs_nofloating_p_left"}, /* Connect current sense positive to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */\
- { 0x8680, "enbl_cs_vbatldo_left"}, /* Enable of current sense LDO , */\
- { 0x8700, "enbl_cs_adc_right"}, /* Enable current sense ADC , */\
- { 0x8710, "enbl_cs_inn1_right"}, /* Enable connection of current sense negative1 , */\
- { 0x8730, "enbl_cs_inp1_right"}, /* Enable connection of current sense positive1 , */\
- { 0x8750, "enbl_cs_ldo_right"}, /* Enable current sense LDO , */\
- { 0x8760, "enbl_cs_nofloating_n_right"}, /* Connect current sense negative to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */\
- { 0x8770, "enbl_cs_nofloating_p_right"}, /* Connect current sense positive to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */\
- { 0x8780, "enbl_cs_vbatldo_right"}, /* Enable of current sense LDO , */\
- { 0x8800, "volsense_pwm_sel"}, /* Voltage sense PWM source selection control , */\
- { 0x8810, "volsense_dc_offset"}, /* Voltage sense decimator offset control , */\
- { 0x9000, "cf_rst_dsp"}, /* Reset , */\
- { 0x9011, "cf_dmem"}, /* Target memory , */\
- { 0x9030, "cf_aif"}, /* Auto increment , */\
- { 0x9040, "cf_int"}, /* Interrupt - auto clear , */\
- { 0x9050, "cf_cgate_off"}, /* Coolflux clock gating disabling control , */\
- { 0x9080, "cf_req_cmd"}, /* Firmware event request rpc command , */\
- { 0x9090, "cf_req_reset"}, /* Firmware event request reset restart , */\
- { 0x90a0, "cf_req_mips"}, /* Firmware event request short on mips , */\
- { 0x90b0, "cf_req_mute_ready"}, /* Firmware event request mute sequence ready , */\
- { 0x90c0, "cf_req_volume_ready"}, /* Firmware event request volume ready , */\
- { 0x90d0, "cf_req_damage"}, /* Firmware event request speaker damage detected , */\
- { 0x90e0, "cf_req_calibrate_ready"}, /* Firmware event request calibration completed , */\
- { 0x90f0, "cf_req_reserved"}, /* Firmware event request reserved , */\
- { 0x910f, "cf_madd"}, /* Memory address , */\
- { 0x920f, "cf_mema"}, /* Activate memory access , */\
- { 0x9307, "cf_err"}, /* Error flags , */\
- { 0x9387, "cf_ack"}, /* Acknowledge of requests , */\
- { 0x9380, "cf_ack_cmd"}, /* Firmware event acknowledge rpc command , */\
- { 0x9390, "cf_ack_reset"}, /* Firmware event acknowledge reset restart , */\
- { 0x93a0, "cf_ack_mips"}, /* Firmware event acknowledge short on mips , */\
- { 0x93b0, "cf_ack_mute_ready"}, /* Firmware event acknowledge mute sequence ready , */\
- { 0x93c0, "cf_ack_volume_ready"}, /* Firmware event acknowledge volume ready , */\
- { 0x93d0, "cf_ack_damage"}, /* Firmware event acknowledge speaker damage detected, */\
- { 0x93e0, "cf_ack_calibrate_ready"}, /* Firmware event acknowledge calibration completed , */\
- { 0x93f0, "cf_ack_reserved"}, /* Firmware event acknowledge reserved , */\
- { 0x980f, "ivt_addr0_msb"}, /* Coolflux interrupt vector table address0 MSB , */\
- { 0x990f, "ivt_addr0_lsb"}, /* Coolflux interrupt vector table address0 LSB , */\
- { 0x9a0f, "ivt_addr1_msb"}, /* Coolflux interrupt vector table address1 MSB , */\
- { 0x9b0f, "ivt_addr1_lsb"}, /* Coolflux interrupt vector table address1 LSB , */\
- { 0x9c0f, "ivt_addr2_msb"}, /* Coolflux interrupt vector table address2 MSB , */\
- { 0x9d0f, "ivt_addr2_lsb"}, /* Coolflux interrupt vector table address2 LSB , */\
- { 0x9e0f, "ivt_addr3_msb"}, /* Coolflux interrupt vector table address3 MSB , */\
- { 0x9f0f, "ivt_addr3_lsb"}, /* Coolflux interrupt vector table address3 LSB , */\
- { 0xa007, "mtpkey1"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
- { 0xa107, "mtpkey2"}, /* MTP KEY2 register , */\
- { 0xa200, "key01_locked"}, /* Indicates KEY1 is locked , */\
- { 0xa210, "key02_locked"}, /* Indicates KEY2 is locked , */\
- { 0xa302, "mtp_man_address_in"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
- { 0xa330, "man_copy_mtp_to_iic"}, /* Start copying single word from mtp to I2C mtp register, */\
- { 0xa340, "man_copy_iic_to_mtp"}, /* Start copying single word from I2C mtp register to mtp, */\
- { 0xa350, "auto_copy_mtp_to_iic"}, /* Start copying all the data from mtp to I2C mtp registers, */\
- { 0xa360, "auto_copy_iic_to_mtp"}, /* Start copying data from I2C mtp registers to mtp , */\
- { 0xa400, "faim_set_clkws"}, /* Sets the faim controller clock wait state register, */\
- { 0xa410, "faim_sel_evenrows"}, /* All even rows of the faim are selected, active high, */\
- { 0xa420, "faim_sel_oddrows"}, /* All odd rows of the faim are selected, all rows in combination with sel_evenrows, */\
- { 0xa430, "faim_program_only"}, /* Skip the erase access at wr_faim command (write-program-marginread), */\
- { 0xa440, "faim_erase_only"}, /* Skip the program access at wr_faim command (write-erase-marginread), */\
- { 0xa50f, "mtp_man_data_out_msb"}, /* MSB word of MTP manual read data , */\
- { 0xa60f, "mtp_man_data_out_lsb"}, /* LSB word of MTP manual read data , */\
- { 0xa70f, "mtp_man_data_in_msb"}, /* MSB word of write data for MTP manual write , */\
- { 0xa80f, "mtp_man_data_in_lsb"}, /* LSB word of write data for MTP manual write , */\
- { 0xb010, "bypass_ocpcounter"}, /* Bypass OCP Counter , */\
- { 0xb020, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
- { 0xb030, "bypass_ovp"}, /* Bypass OVP , */\
- { 0xb040, "bypass_uvp"}, /* Bypass UVP , */\
- { 0xb050, "bypass_otp"}, /* Bypass OTP , */\
- { 0xb060, "bypass_lost_clk"}, /* Bypass lost clock detector , */\
- { 0xb070, "ctrl_vpalarm"}, /* vpalarm (uvp ovp handling) , */\
- { 0xb087, "ocp_threshold"}, /* OCP threshold level , */\
- { 0xb108, "ext_temp"}, /* External temperature (C) , */\
- { 0xb190, "ext_temp_sel"}, /* Select temp Speaker calibration , */\
- { 0xc000, "use_direct_ctrls"}, /* Direct control to overrule several functions for testing, */\
- { 0xc010, "rst_datapath"}, /* Direct control for datapath reset , */\
- { 0xc020, "rst_cgu"}, /* Direct control for cgu reset , */\
- { 0xc038, "enbl_ref"}, /* Switch on the analog references, each part of the references can be switched on/off individually, */\
- { 0xc0d0, "enbl_ringo"}, /* Enable the ring oscillator for test purpose , */\
- { 0xc0e0, "use_direct_clk_ctrl"}, /* Direct clock control to overrule several functions for testing, */\
- { 0xc0f0, "use_direct_pll_ctrl"}, /* Direct PLL control to overrule several functions for testing, */\
- { 0xc100, "enbl_tsense"}, /* Temperature sensor enable control - I2C direct mode, */\
- { 0xc110, "tsense_hibias"}, /* Bit to set the biasing in temp sensor to high , */\
- { 0xc120, "enbl_flag_vbg"}, /* Enable flagging of bandgap out of control , */\
- { 0xc20f, "abist_offset"}, /* Offset control for ABIST testing (two's complement), */\
- { 0xc300, "bypasslatch"}, /* Bypass latch , */\
- { 0xc311, "sourcea"}, /* Set OUTA to , */\
- { 0xc331, "sourceb"}, /* Set OUTB to , */\
- { 0xc350, "inverta"}, /* Invert pwma test signal , */\
- { 0xc360, "invertb"}, /* Invert pwmb test signal , */\
- { 0xc374, "pulselength"}, /* Pulse length setting test input for amplifier (clock d - k*2048*fs), */\
- { 0xc3c0, "tdm_enable_loopback"}, /* TDM loopback test , */\
- { 0xc3d0, "test_abistfft_enbl"}, /* FFT Coolflux , */\
- { 0xc3e0, "test_pwr_switch"}, /* Test mode for digital power switches core sw/mem sw/micvdd sw, */\
- { 0xc400, "bst_bypasslatch"}, /* Bypass latch in boost converter , */\
- { 0xc411, "bst_source"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
- { 0xc430, "bst_invertb"}, /* Invert pwmbst test signal , */\
- { 0xc444, "bst_pulselength"}, /* Pulse length setting test input for boost converter , */\
- { 0xc490, "test_bst_ctrlsthv"}, /* Test mode for boost control stage , */\
- { 0xc4a0, "test_bst_iddq"}, /* IDDQ testing in power stage of boost converter , */\
- { 0xc4b0, "test_bst_rdson"}, /* RDSON testing - boost power stage , */\
- { 0xc4c0, "test_bst_cvi"}, /* CVI testing - boost power stage , */\
- { 0xc4d0, "test_bst_ocp"}, /* Boost OCP. For old ocp (ctrl_reversebst is 0), For new ocp (ctrl_reversebst is 1), */\
- { 0xc4e0, "test_bst_sense"}, /* Test option for the sense NMOS in booster for current mode control., */\
- { 0xc500, "test_cvi"}, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */\
- { 0xc510, "test_discrete"}, /* Test function noise measurement , */\
- { 0xc520, "test_iddq"}, /* Set the power stages in iddq mode for gate stress., */\
- { 0xc540, "test_rdson"}, /* Analog BIST, switch to enable Rdson measurement , */\
- { 0xc550, "test_sdelta"}, /* Analog BIST, noise test , */\
- { 0xc570, "test_enbl_cs"}, /* Enable for digimux mode of current sense , */\
- { 0xc600, "enbl_pwm_dcc"}, /* Enables direct control of pwm duty cycle for DCDC power stage, */\
- { 0xc613, "pwm_dcc_cnt"}, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */\
- { 0xc650, "enbl_ldo_stress"}, /* Enable stress of internal supply voltages powerstages, */\
- { 0xc660, "bypass_diosw_ovp"}, /* Bypass ovp for memory switch diosw , */\
- { 0xc670, "enbl_powerswitch"}, /* Vddd core power switch control - overrules the manager control, */\
- { 0xc707, "digimuxa_sel"}, /* DigimuxA input selection control routed to GPIO1 (see Digimux list for details), */\
- { 0xc787, "digimuxb_sel"}, /* DigimuxB input selection control routed to GPIO2 (see Digimux list for details), */\
- { 0xc807, "digimuxc_sel"}, /* DigimuxC input selection control routed to GPIO3 (see Digimux list for details), */\
- { 0xc887, "digimuxd_sel"}, /* DigimuxD input selection control routed to GPIO4 (see Digimux list for details), */\
- { 0xc901, "dio1_ehs"}, /* Speed/load setting for DIO1 IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
- { 0xc921, "dio2_ehs"}, /* Speed/load setting for DIO2 IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
- { 0xc941, "gainio_ehs"}, /* Speed/load setting for GAINIO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
- { 0xc961, "pdmo_ehs"}, /* Speed/load setting for PDMO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
- { 0xc981, "int_ehs"}, /* Speed/load setting for INT IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
- { 0xc9a1, "tdo_ehs"}, /* Speed/load setting for TDO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
- { 0xc9c0, "hs_mode"}, /* I2C high speed mode control , */\
- { 0xca00, "enbl_anamux1"}, /* Enable anamux1 , */\
- { 0xca10, "enbl_anamux2"}, /* Enable anamux2 , */\
- { 0xca20, "enbl_anamux3"}, /* Enable anamux3 , */\
- { 0xca30, "enbl_anamux4"}, /* Enable anamux4 , */\
- { 0xca40, "enbl_anamux5"}, /* Enable anamux5 , */\
- { 0xca50, "enbl_anamux6"}, /* Enable anamux6 , */\
- { 0xca60, "enbl_anamux7"}, /* Enable anamux7 , */\
- { 0xca74, "anamux1"}, /* Anamux selection control - anamux on TEST1 , */\
- { 0xcb04, "anamux2"}, /* Anamux selection control - anamux on TEST2 , */\
- { 0xcb54, "anamux3"}, /* Anamux selection control - anamux on TEST3 , */\
- { 0xcba4, "anamux4"}, /* Anamux selection control - anamux on TEST4 , */\
- { 0xcc04, "anamux5"}, /* Anamux selection control - anamux on TEST5 , */\
- { 0xcc54, "anamux6"}, /* Anamux selection control - anamux on TEST6 , */\
- { 0xcca4, "anamux7"}, /* Anamux selection control - anamux on TEST7 , */\
- { 0xcd05, "pll_seli"}, /* PLL SELI - I2C direct PLL control mode only , */\
- { 0xcd64, "pll_selp"}, /* PLL SELP - I2C direct PLL control mode only , */\
- { 0xcdb3, "pll_selr"}, /* PLL SELR - I2C direct PLL control mode only , */\
- { 0xcdf0, "pll_frm"}, /* PLL free running mode control; 1 in TCB direct control mode, else this control bit, */\
- { 0xce09, "pll_ndec"}, /* PLL NDEC - I2C direct PLL control mode only , */\
- { 0xcea0, "pll_mdec_msb"}, /* MSB of pll_mdec - I2C direct PLL control mode only, */\
- { 0xceb0, "enbl_pll"}, /* Enables PLL in I2C direct PLL control mode only , */\
- { 0xcec0, "enbl_osc"}, /* Enables OSC1M in I2C direct control mode only , */\
- { 0xced0, "pll_bypass"}, /* PLL bypass control in I2C direct PLL control mode only, */\
- { 0xcee0, "pll_directi"}, /* PLL directi control in I2C direct PLL control mode only, */\
- { 0xcef0, "pll_directo"}, /* PLL directo control in I2C direct PLL control mode only, */\
- { 0xcf0f, "pll_mdec_lsb"}, /* Bits 15..0 of PLL MDEC are I2C direct PLL control mode only, */\
- { 0xd006, "pll_pdec"}, /* PLL PDEC - I2C direct PLL control mode only , */\
- { 0xd10f, "tsig_freq_lsb"}, /* Internal sinus test generator frequency control , */\
- { 0xd202, "tsig_freq_msb"}, /* Select internal sinus test generator, frequency control msb bits, */\
- { 0xd230, "inject_tsig"}, /* Control bit to switch to internal sinus test generator, */\
- { 0xd243, "tsig_gain_left"}, /* Test signal gain for left channel , */\
- { 0xd283, "tsig_gain_right"}, /* Test signal gain for right channel , */\
- { 0xd300, "adc10_reset"}, /* Reset for ADC10 - I2C direct control mode , */\
- { 0xd311, "adc10_test"}, /* Test mode selection signal for ADC10 - I2C direct control mode, */\
- { 0xd332, "adc10_sel"}, /* Select the input to convert for ADC10 - I2C direct control mode, */\
- { 0xd364, "adc10_prog_sample"}, /* ADC10 program sample setting - I2C direct control mode, */\
- { 0xd3b0, "adc10_enbl"}, /* Enable ADC10 - I2C direct control mode , */\
- { 0xd3c0, "bypass_lp_vbat"}, /* Bypass control for Low pass filter in batt sensor , */\
- { 0xd409, "data_adc10_tempbat"}, /* ADC 10 data output data for testing , */\
- { 0xd506, "ctrl_digtoana_hidden"}, /* Spare digital to analog control bits - Hidden , */\
- { 0xd570, "enbl_clk_out_of_range"}, /* Clock out of range , */\
- { 0xf000, "calibration_onetime"}, /* Calibration schedule , */\
- { 0xf010, "calibr_ron_done"}, /* Calibration Ron executed , */\
- { 0xf020, "calibr_dcdc_api_calibrate"}, /* Calibration current limit DCDC , */\
- { 0xf030, "calibr_dcdc_delta_sign"}, /* Sign bit for delta calibration current limit DCDC , */\
- { 0xf042, "calibr_dcdc_delta"}, /* Calibration delta current limit DCDC , */\
- { 0xf078, "calibr_speaker_info"}, /* Reserved space for allowing customer to store speaker information, */\
- { 0xf105, "calibr_vout_offset"}, /* DCDC offset calibration 2's complement (key1 protected), */\
- { 0xf163, "calibr_gain_left"}, /* HW gain module - left channel (2's complement) , */\
- { 0xf1a5, "calibr_offset_left"}, /* Offset for amplifier, HW gain module - left channel (2's complement), */\
- { 0xf203, "calibr_gain_right"}, /* HW gain module - right channel (2's complement) , */\
- { 0xf245, "calibr_offset_right"}, /* Offset for amplifier, HW gain module - right channel (2's complement), */\
- { 0xf2a3, "calibr_rcvldop_trim"}, /* Trimming of LDO (2.7V) , */\
- { 0xf307, "calibr_gain_cs_left"}, /* Current sense gain - left channel (signed two's complement format), */\
- { 0xf387, "calibr_gain_cs_right"}, /* Current sense gain - right channel (signed two's complement format), */\
- { 0xf40f, "calibr_R25C_L"}, /* Ron resistance of left channel speaker coil , */\
- { 0xf50f, "calibr_R25C_R"}, /* Ron resistance of right channel speaker coil , */\
- { 0xf606, "ctrl_offset_a_left"}, /* Offset of left amplifier level shifter A , */\
- { 0xf686, "ctrl_offset_b_left"}, /* Offset of left amplifier level shifter B , */\
- { 0xf706, "ctrl_offset_a_right"}, /* Offset of right amplifier level shifter A , */\
- { 0xf786, "ctrl_offset_b_right"}, /* Offset of right amplifier level shifter B , */\
- { 0xf806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
- { 0xf870, "htol_iic_addr_en"}, /* HTOL I2C address enable control , */\
- { 0xf884, "calibr_temp_offset"}, /* Temperature offset 2's compliment (key1 protected), */\
- { 0xf8d2, "calibr_temp_gain"}, /* Temperature gain 2's compliment (key1 protected) , */\
- { 0xf900, "mtp_lock_dcdcoff_mode"}, /* Disable function dcdcoff_mode , */\
- { 0xf910, "mtp_lock_enbl_coolflux"}, /* Disable function enbl_coolflux , */\
- { 0xf920, "mtp_lock_bypass_clipper"}, /* Disable function bypass_clipper , */\
- { 0xf930, "mtp_lock_max_dcdc_voltage"}, /* Disable programming of max dcdc boost voltage , */\
- { 0xf943, "calibr_vbg_trim"}, /* Bandgap trimming control , */\
- { 0xf987, "type_bits_fw"}, /* MTP-control FW - See Firmware I2C API document for details, */\
- { 0xfa0f, "mtpdataA"}, /* MTPdataA (key1 protected) , */\
- { 0xfb0f, "mtpdataB"}, /* MTPdataB (key1 protected) , */\
- { 0xfc0f, "mtpdataC"}, /* MTPdataC (key1 protected) , */\
- { 0xfd0f, "mtpdataD"}, /* MTPdataD (key1 protected) , */\
- { 0xfe0f, "mtpdataE"}, /* MTPdataE (key1 protected) , */\
- { 0xff05, "calibr_osc_delta_ndiv"}, /* Calibration data for OSC1M, signed number representation, */\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-
-enum tfa2_irq {
- tfa2_irq_stvdds = 0,
- tfa2_irq_stplls = 1,
- tfa2_irq_stotds = 2,
- tfa2_irq_stovds = 3,
- tfa2_irq_stuvds = 4,
- tfa2_irq_stclks = 5,
- tfa2_irq_stmtpb = 6,
- tfa2_irq_stnoclk = 7,
- tfa2_irq_stspks = 8,
- tfa2_irq_stacs = 9,
- tfa2_irq_stsws = 10,
- tfa2_irq_stwds = 11,
- tfa2_irq_stamps = 12,
- tfa2_irq_starefs = 13,
- tfa2_irq_stadccr = 14,
- tfa2_irq_stbodnok = 15,
- tfa2_irq_stbstcu = 16,
- tfa2_irq_stbsthi = 17,
- tfa2_irq_stbstoc = 18,
- tfa2_irq_stbstpkcur = 19,
- tfa2_irq_stbstvc = 20,
- tfa2_irq_stbst86 = 21,
- tfa2_irq_stbst93 = 22,
- tfa2_irq_strcvld = 23,
- tfa2_irq_stocpl = 24,
- tfa2_irq_stocpr = 25,
- tfa2_irq_stmwsrc = 26,
- tfa2_irq_stmwcfc = 27,
- tfa2_irq_stmwsmu = 28,
- tfa2_irq_stcfmer = 29,
- tfa2_irq_stcfmac = 30,
- tfa2_irq_stclkoor = 31,
- tfa2_irq_sttdmer = 32,
- tfa2_irq_stclpl = 33,
- tfa2_irq_stclpr = 34,
- tfa2_irq_stocpm = 35,
- tfa2_irq_max = 36,
- tfa2_irq_all = -1 /* all irqs */};
-
-#define TFA2_IRQ_NAMETABLE static tfaIrqName_t Tfa2IrqNames[]= {\
- { 0, "STVDDS"},\
- { 1, "STPLLS"},\
- { 2, "STOTDS"},\
- { 3, "STOVDS"},\
- { 4, "STUVDS"},\
- { 5, "STCLKS"},\
- { 6, "STMTPB"},\
- { 7, "STNOCLK"},\
- { 8, "STSPKS"},\
- { 9, "STACS"},\
- { 10, "STSWS"},\
- { 11, "STWDS"},\
- { 12, "STAMPS"},\
- { 13, "STAREFS"},\
- { 14, "STADCCR"},\
- { 15, "STBODNOK"},\
- { 16, "STBSTCU"},\
- { 17, "STBSTHI"},\
- { 18, "STBSTOC"},\
- { 19, "STBSTPKCUR"},\
- { 20, "STBSTVC"},\
- { 21, "STBST86"},\
- { 22, "STBST93"},\
- { 23, "STRCVLD"},\
- { 24, "STOCPL"},\
- { 25, "STOCPR"},\
- { 26, "STMWSRC"},\
- { 27, "STMWCFC"},\
- { 28, "STMWSMU"},\
- { 29, "STCFMER"},\
- { 30, "STCFMAC"},\
- { 31, "STCLKOOR"},\
- { 32, "STTDMER"},\
- { 33, "STCLPL"},\
- { 34, "STCLPR"},\
- { 35, "STOCPM"},\
- { 36, "36"},\
-};
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#define TFA9888_I2CVERSION 18
+typedef enum nxpTfa2BfEnumList {
+ TFA2_BF_PWDN = 0x0000, /*!< Powerdown selection */
+ TFA2_BF_I2CR = 0x0010, /*!< I2C Reset - Auto clear */
+ TFA2_BF_CFE = 0x0020, /*!< Enable CoolFlux */
+ TFA2_BF_AMPE = 0x0030, /*!< Activate Amplifier */
+ TFA2_BF_DCA = 0x0040, /*!< Activate DC-to-DC converter */
+ TFA2_BF_SBSL = 0x0050, /*!< Coolflux configured */
+ TFA2_BF_AMPC = 0x0060, /*!< CoolFlux controls amplifier */
+ TFA2_BF_INTP = 0x0071, /*!< Interrupt config */
+ TFA2_BF_FSSSEL = 0x0091, /*!< Audio sample reference */
+ TFA2_BF_BYPOCP = 0x00b0, /*!< Bypass OCP */
+ TFA2_BF_TSTOCP = 0x00c0, /*!< OCP testing control */
+ TFA2_BF_AMPINSEL = 0x0101, /*!< Amplifier input selection */
+ TFA2_BF_MANSCONF = 0x0120, /*!< I2C configured */
+ TFA2_BF_MANCOLD = 0x0130, /*!< Execute cold start */
+ TFA2_BF_MANAOOSC = 0x0140, /*!< Internal osc off at PWDN */
+ TFA2_BF_MANROBOD = 0x0150, /*!< Reaction on BOD */
+ TFA2_BF_BODE = 0x0160, /*!< BOD Enable */
+ TFA2_BF_BODHYS = 0x0170, /*!< BOD Hysteresis */
+ TFA2_BF_BODFILT = 0x0181, /*!< BOD filter */
+ TFA2_BF_BODTHLVL = 0x01a1, /*!< BOD threshold */
+ TFA2_BF_MUTETO = 0x01d0, /*!< Time out SB mute sequence */
+ TFA2_BF_RCVNS = 0x01e0, /*!< Noise shaper selection */
+ TFA2_BF_MANWDE = 0x01f0, /*!< Watchdog manager reaction */
+ TFA2_BF_AUDFS = 0x0203, /*!< Sample rate (fs) */
+ TFA2_BF_INPLEV = 0x0240, /*!< TDM output attenuation */
+ TFA2_BF_FRACTDEL = 0x0255, /*!< V/I Fractional delay */
+ TFA2_BF_BYPHVBF = 0x02b0, /*!< Bypass HVBAT filter */
+ TFA2_BF_LDOBYP = 0x02c0, /*!< Receiver LDO bypass */
+ TFA2_BF_REV = 0x030f, /*!< Revision info */
+ TFA2_BF_REFCKEXT = 0x0401, /*!< PLL external ref clock */
+ TFA2_BF_REFCKSEL = 0x0420, /*!< PLL internal ref clock */
+ TFA2_BF_SSLEFTE = 0x0500, /*!< Enable left channel */
+ TFA2_BF_SSRIGHTE = 0x0510, /*!< Enable right channel */
+ TFA2_BF_VSLEFTE = 0x0520, /*!< Voltage sense left */
+ TFA2_BF_VSRIGHTE = 0x0530, /*!< Voltage sense right */
+ TFA2_BF_CSLEFTE = 0x0540, /*!< Current sense left */
+ TFA2_BF_CSRIGHTE = 0x0550, /*!< Current sense right */
+ TFA2_BF_SSPDME = 0x0560, /*!< Sub-system PDM */
+ TFA2_BF_STGAIN = 0x0d18, /*!< Side tone gain */
+ TFA2_BF_PDMSMUTE = 0x0da0, /*!< Side tone soft mute */
+ TFA2_BF_SWVSTEP = 0x0e06, /*!< Register for the host SW to record the current active vstep */
+ TFA2_BF_VDDS = 0x1000, /*!< POR */
+ TFA2_BF_PLLS = 0x1010, /*!< PLL lock */
+ TFA2_BF_OTDS = 0x1020, /*!< OTP alarm */
+ TFA2_BF_OVDS = 0x1030, /*!< OVP alarm */
+ TFA2_BF_UVDS = 0x1040, /*!< UVP alarm */
+ TFA2_BF_CLKS = 0x1050, /*!< Clocks stable */
+ TFA2_BF_MTPB = 0x1060, /*!< MTP busy */
+ TFA2_BF_NOCLK = 0x1070, /*!< Lost clock */
+ TFA2_BF_SPKS = 0x1080, /*!< Speaker error */
+ TFA2_BF_ACS = 0x1090, /*!< Cold Start */
+ TFA2_BF_SWS = 0x10a0, /*!< Amplifier engage */
+ TFA2_BF_WDS = 0x10b0, /*!< Watchdog */
+ TFA2_BF_AMPS = 0x10c0, /*!< Amplifier enable */
+ TFA2_BF_AREFS = 0x10d0, /*!< References enable */
+ TFA2_BF_ADCCR = 0x10e0, /*!< Control ADC */
+ TFA2_BF_BODNOK = 0x10f0, /*!< BOD */
+ TFA2_BF_DCIL = 0x1100, /*!< DCDC current limiting */
+ TFA2_BF_DCDCA = 0x1110, /*!< DCDC active */
+ TFA2_BF_DCOCPOK = 0x1120, /*!< DCDC OCP nmos */
+ TFA2_BF_DCHVBAT = 0x1140, /*!< DCDC level 1x */
+ TFA2_BF_DCH114 = 0x1150, /*!< DCDC level 1.14x */
+ TFA2_BF_DCH107 = 0x1160, /*!< DCDC level 1.07x */
+ TFA2_BF_STMUTEB = 0x1170, /*!< side tone (un)mute busy */
+ TFA2_BF_STMUTE = 0x1180, /*!< side tone mute state */
+ TFA2_BF_TDMLUTER = 0x1190, /*!< TDM LUT error */
+ TFA2_BF_TDMSTAT = 0x11a2, /*!< TDM status bits */
+ TFA2_BF_TDMERR = 0x11d0, /*!< TDM error */
+ TFA2_BF_HAPTIC = 0x11e0, /*!< Status haptic driver */
+ TFA2_BF_OCPOAPL = 0x1200, /*!< OCPOK pmos A left */
+ TFA2_BF_OCPOANL = 0x1210, /*!< OCPOK nmos A left */
+ TFA2_BF_OCPOBPL = 0x1220, /*!< OCPOK pmos B left */
+ TFA2_BF_OCPOBNL = 0x1230, /*!< OCPOK nmos B left */
+ TFA2_BF_CLIPAHL = 0x1240, /*!< Clipping A left to Vddp */
+ TFA2_BF_CLIPALL = 0x1250, /*!< Clipping A left to gnd */
+ TFA2_BF_CLIPBHL = 0x1260, /*!< Clipping B left to Vddp */
+ TFA2_BF_CLIPBLL = 0x1270, /*!< Clipping B left to gnd */
+ TFA2_BF_OCPOAPRC = 0x1280, /*!< OCPOK pmos A RCV */
+ TFA2_BF_OCPOANRC = 0x1290, /*!< OCPOK nmos A RCV */
+ TFA2_BF_OCPOBPRC = 0x12a0, /*!< OCPOK pmos B RCV */
+ TFA2_BF_OCPOBNRC = 0x12b0, /*!< OCPOK nmos B RCV */
+ TFA2_BF_RCVLDOR = 0x12c0, /*!< RCV LDO regulates */
+ TFA2_BF_RCVLDOBR = 0x12d0, /*!< Receiver LDO ready */
+ TFA2_BF_OCDSL = 0x12e0, /*!< OCP left amplifier */
+ TFA2_BF_CLIPSL = 0x12f0, /*!< Amplifier left clipping */
+ TFA2_BF_OCPOAPR = 0x1300, /*!< OCPOK pmos A right */
+ TFA2_BF_OCPOANR = 0x1310, /*!< OCPOK nmos A right */
+ TFA2_BF_OCPOBPR = 0x1320, /*!< OCPOK pmos B right */
+ TFA2_BF_OCPOBNR = 0x1330, /*!< OCPOK nmos B right */
+ TFA2_BF_CLIPAHR = 0x1340, /*!< Clipping A right to Vddp */
+ TFA2_BF_CLIPALR = 0x1350, /*!< Clipping A right to gnd */
+ TFA2_BF_CLIPBHR = 0x1360, /*!< Clipping B left to Vddp */
+ TFA2_BF_CLIPBLR = 0x1370, /*!< Clipping B right to gnd */
+ TFA2_BF_OCDSR = 0x1380, /*!< OCP right amplifier */
+ TFA2_BF_CLIPSR = 0x1390, /*!< Amplifier right clipping */
+ TFA2_BF_OCPOKMC = 0x13a0, /*!< OCPOK MICVDD */
+ TFA2_BF_MANALARM = 0x13b0, /*!< Alarm state */
+ TFA2_BF_MANWAIT1 = 0x13c0, /*!< Wait HW I2C settings */
+ TFA2_BF_MANWAIT2 = 0x13d0, /*!< Wait CF config */
+ TFA2_BF_MANMUTE = 0x13e0, /*!< Audio mute sequence */
+ TFA2_BF_MANOPER = 0x13f0, /*!< Operating state */
+ TFA2_BF_SPKSL = 0x1400, /*!< Left speaker status */
+ TFA2_BF_SPKSR = 0x1410, /*!< Right speaker status */
+ TFA2_BF_CLKOOR = 0x1420, /*!< External clock status */
+ TFA2_BF_MANSTATE = 0x1433, /*!< Device manager status */
+ TFA2_BF_BATS = 0x1509, /*!< Battery voltage (V) */
+ TFA2_BF_TEMPS = 0x1608, /*!< IC Temperature (C) */
+ TFA2_BF_TDMUC = 0x2003, /*!< Usecase setting */
+ TFA2_BF_TDME = 0x2040, /*!< Enable interface */
+ TFA2_BF_TDMMODE = 0x2050, /*!< Slave/master */
+ TFA2_BF_TDMCLINV = 0x2060, /*!< Reception data to BCK clock */
+ TFA2_BF_TDMFSLN = 0x2073, /*!< FS length (master mode only) */
+ TFA2_BF_TDMFSPOL = 0x20b0, /*!< FS polarity */
+ TFA2_BF_TDMNBCK = 0x20c3, /*!< N-BCK's in FS */
+ TFA2_BF_TDMSLOTS = 0x2103, /*!< N-slots in Frame */
+ TFA2_BF_TDMSLLN = 0x2144, /*!< N-bits in slot */
+ TFA2_BF_TDMBRMG = 0x2194, /*!< N-bits remaining */
+ TFA2_BF_TDMDEL = 0x21e0, /*!< data delay to FS */
+ TFA2_BF_TDMADJ = 0x21f0, /*!< data adjustment */
+ TFA2_BF_TDMOOMP = 0x2201, /*!< Received audio compression */
+ TFA2_BF_TDMSSIZE = 0x2224, /*!< Sample size per slot */
+ TFA2_BF_TDMTXDFO = 0x2271, /*!< Format unused bits */
+ TFA2_BF_TDMTXUS0 = 0x2291, /*!< Format unused slots GAINIO */
+ TFA2_BF_TDMTXUS1 = 0x22b1, /*!< Format unused slots DIO1 */
+ TFA2_BF_TDMTXUS2 = 0x22d1, /*!< Format unused slots DIO2 */
+ TFA2_BF_TDMLE = 0x2310, /*!< Control audio left */
+ TFA2_BF_TDMRE = 0x2320, /*!< Control audio right */
+ TFA2_BF_TDMVSRE = 0x2340, /*!< Control voltage sense right */
+ TFA2_BF_TDMCSRE = 0x2350, /*!< Control current sense right */
+ TFA2_BF_TDMVSLE = 0x2360, /*!< Voltage sense left control */
+ TFA2_BF_TDMCSLE = 0x2370, /*!< Current sense left control */
+ TFA2_BF_TDMCFRE = 0x2380, /*!< DSP out right control */
+ TFA2_BF_TDMCFLE = 0x2390, /*!< DSP out left control */
+ TFA2_BF_TDMCF3E = 0x23a0, /*!< AEC ref left control */
+ TFA2_BF_TDMCF4E = 0x23b0, /*!< AEC ref right control */
+ TFA2_BF_TDMPD1E = 0x23c0, /*!< PDM 1 control */
+ TFA2_BF_TDMPD2E = 0x23d0, /*!< PDM 2 control */
+ TFA2_BF_TDMLIO = 0x2421, /*!< IO audio left */
+ TFA2_BF_TDMRIO = 0x2441, /*!< IO audio right */
+ TFA2_BF_TDMVSRIO = 0x2481, /*!< IO voltage sense right */
+ TFA2_BF_TDMCSRIO = 0x24a1, /*!< IO current sense right */
+ TFA2_BF_TDMVSLIO = 0x24c1, /*!< IO voltage sense left */
+ TFA2_BF_TDMCSLIO = 0x24e1, /*!< IO current sense left */
+ TFA2_BF_TDMCFRIO = 0x2501, /*!< IO dspout right */
+ TFA2_BF_TDMCFLIO = 0x2521, /*!< IO dspout left */
+ TFA2_BF_TDMCF3IO = 0x2541, /*!< IO AEC ref left control */
+ TFA2_BF_TDMCF4IO = 0x2561, /*!< IO AEC ref right control */
+ TFA2_BF_TDMPD1IO = 0x2581, /*!< IO pdm1 */
+ TFA2_BF_TDMPD2IO = 0x25a1, /*!< IO pdm2 */
+ TFA2_BF_TDMLS = 0x2643, /*!< Position audio left */
+ TFA2_BF_TDMRS = 0x2683, /*!< Position audio right */
+ TFA2_BF_TDMVSRS = 0x2703, /*!< Position voltage sense right */
+ TFA2_BF_TDMCSRS = 0x2743, /*!< Position current sense right */
+ TFA2_BF_TDMVSLS = 0x2783, /*!< Position voltage sense left */
+ TFA2_BF_TDMCSLS = 0x27c3, /*!< Position current sense left */
+ TFA2_BF_TDMCFRS = 0x2803, /*!< Position dspout right */
+ TFA2_BF_TDMCFLS = 0x2843, /*!< Position dspout left */
+ TFA2_BF_TDMCF3S = 0x2883, /*!< Position AEC ref left control */
+ TFA2_BF_TDMCF4S = 0x28c3, /*!< Position AEC ref right control */
+ TFA2_BF_TDMPD1S = 0x2903, /*!< Position pdm1 */
+ TFA2_BF_TDMPD2S = 0x2943, /*!< Position pdm2 */
+ TFA2_BF_PDMSM = 0x3100, /*!< PDM control */
+ TFA2_BF_PDMSTSEL = 0x3111, /*!< Side tone input */
+ TFA2_BF_PDMLSEL = 0x3130, /*!< PDM data selection for left channel during PDM direct mode */
+ TFA2_BF_PDMRSEL = 0x3140, /*!< PDM data selection for right channel during PDM direct mode */
+ TFA2_BF_MICVDDE = 0x3150, /*!< Enable MICVDD */
+ TFA2_BF_PDMCLRAT = 0x3201, /*!< PDM BCK/Fs ratio */
+ TFA2_BF_PDMGAIN = 0x3223, /*!< PDM gain */
+ TFA2_BF_PDMOSEL = 0x3263, /*!< PDM output selection - RE/FE data combination */
+ TFA2_BF_SELCFHAPD = 0x32a0, /*!< Select the source for haptic data output (not for customer) */
+ TFA2_BF_HAPTIME = 0x3307, /*!< Duration (ms) */
+ TFA2_BF_HAPLEVEL = 0x3387, /*!< DC value (FFS) */
+ TFA2_BF_GPIODIN = 0x3403, /*!< Receiving value */
+ TFA2_BF_GPIOCTRL = 0x3500, /*!< GPIO master control over GPIO1/2 ports (not for customer) */
+ TFA2_BF_GPIOCONF = 0x3513, /*!< Configuration */
+ TFA2_BF_GPIODOUT = 0x3553, /*!< Transmitting value */
+ TFA2_BF_ISTVDDS = 0x4000, /*!< Status POR */
+ TFA2_BF_ISTPLLS = 0x4010, /*!< Status PLL lock */
+ TFA2_BF_ISTOTDS = 0x4020, /*!< Status OTP alarm */
+ TFA2_BF_ISTOVDS = 0x4030, /*!< Status OVP alarm */
+ TFA2_BF_ISTUVDS = 0x4040, /*!< Status UVP alarm */
+ TFA2_BF_ISTCLKS = 0x4050, /*!< Status clocks stable */
+ TFA2_BF_ISTMTPB = 0x4060, /*!< Status MTP busy */
+ TFA2_BF_ISTNOCLK = 0x4070, /*!< Status lost clock */
+ TFA2_BF_ISTSPKS = 0x4080, /*!< Status speaker error */
+ TFA2_BF_ISTACS = 0x4090, /*!< Status cold start */
+ TFA2_BF_ISTSWS = 0x40a0, /*!< Status amplifier engage */
+ TFA2_BF_ISTWDS = 0x40b0, /*!< Status watchdog */
+ TFA2_BF_ISTAMPS = 0x40c0, /*!< Status amplifier enable */
+ TFA2_BF_ISTAREFS = 0x40d0, /*!< Status Ref enable */
+ TFA2_BF_ISTADCCR = 0x40e0, /*!< Status Control ADC */
+ TFA2_BF_ISTBODNOK = 0x40f0, /*!< Status BOD */
+ TFA2_BF_ISTBSTCU = 0x4100, /*!< Status DCDC current limiting */
+ TFA2_BF_ISTBSTHI = 0x4110, /*!< Status DCDC active */
+ TFA2_BF_ISTBSTOC = 0x4120, /*!< Status DCDC OCP */
+ TFA2_BF_ISTBSTPKCUR = 0x4130, /*!< Status bst peakcur */
+ TFA2_BF_ISTBSTVC = 0x4140, /*!< Status DCDC level 1x */
+ TFA2_BF_ISTBST86 = 0x4150, /*!< Status DCDC level 1.14x */
+ TFA2_BF_ISTBST93 = 0x4160, /*!< Status DCDC level 1.07x */
+ TFA2_BF_ISTRCVLD = 0x4170, /*!< Status rcvldop ready */
+ TFA2_BF_ISTOCPL = 0x4180, /*!< Status ocp alarm left */
+ TFA2_BF_ISTOCPR = 0x4190, /*!< Status ocp alarm right */
+ TFA2_BF_ISTMWSRC = 0x41a0, /*!< Status Waits HW I2C settings */
+ TFA2_BF_ISTMWCFC = 0x41b0, /*!< Status waits CF config */
+ TFA2_BF_ISTMWSMU = 0x41c0, /*!< Status Audio mute sequence */
+ TFA2_BF_ISTCFMER = 0x41d0, /*!< Status cfma error */
+ TFA2_BF_ISTCFMAC = 0x41e0, /*!< Status cfma ack */
+ TFA2_BF_ISTCLKOOR = 0x41f0, /*!< Status flag_clk_out_of_range */
+ TFA2_BF_ISTTDMER = 0x4200, /*!< Status tdm error */
+ TFA2_BF_ISTCLPL = 0x4210, /*!< Status clip left */
+ TFA2_BF_ISTCLPR = 0x4220, /*!< Status clip right */
+ TFA2_BF_ISTOCPM = 0x4230, /*!< Status mic ocpok */
+ TFA2_BF_ICLVDDS = 0x4400, /*!< Clear POR */
+ TFA2_BF_ICLPLLS = 0x4410, /*!< Clear PLL lock */
+ TFA2_BF_ICLOTDS = 0x4420, /*!< Clear OTP alarm */
+ TFA2_BF_ICLOVDS = 0x4430, /*!< Clear OVP alarm */
+ TFA2_BF_ICLUVDS = 0x4440, /*!< Clear UVP alarm */
+ TFA2_BF_ICLCLKS = 0x4450, /*!< Clear clocks stable */
+ TFA2_BF_ICLMTPB = 0x4460, /*!< Clear mtp busy */
+ TFA2_BF_ICLNOCLK = 0x4470, /*!< Clear lost clk */
+ TFA2_BF_ICLSPKS = 0x4480, /*!< Clear speaker error */
+ TFA2_BF_ICLACS = 0x4490, /*!< Clear cold started */
+ TFA2_BF_ICLSWS = 0x44a0, /*!< Clear amplifier engage */
+ TFA2_BF_ICLWDS = 0x44b0, /*!< Clear watchdog */
+ TFA2_BF_ICLAMPS = 0x44c0, /*!< Clear enbl amp */
+ TFA2_BF_ICLAREFS = 0x44d0, /*!< Clear ref enable */
+ TFA2_BF_ICLADCCR = 0x44e0, /*!< Clear control ADC */
+ TFA2_BF_ICLBODNOK = 0x44f0, /*!< Clear BOD */
+ TFA2_BF_ICLBSTCU = 0x4500, /*!< Clear DCDC current limiting */
+ TFA2_BF_ICLBSTHI = 0x4510, /*!< Clear DCDC active */
+ TFA2_BF_ICLBSTOC = 0x4520, /*!< Clear DCDC OCP */
+ TFA2_BF_ICLBSTPC = 0x4530, /*!< Clear bst peakcur */
+ TFA2_BF_ICLBSTVC = 0x4540, /*!< Clear DCDC level 1x */
+ TFA2_BF_ICLBST86 = 0x4550, /*!< Clear DCDC level 1.14x */
+ TFA2_BF_ICLBST93 = 0x4560, /*!< Clear DCDC level 1.07x */
+ TFA2_BF_ICLRCVLD = 0x4570, /*!< Clear rcvldop ready */
+ TFA2_BF_ICLOCPL = 0x4580, /*!< Clear ocp alarm left */
+ TFA2_BF_ICLOCPR = 0x4590, /*!< Clear ocp alarm right */
+ TFA2_BF_ICLMWSRC = 0x45a0, /*!< Clear wait HW I2C settings */
+ TFA2_BF_ICLMWCFC = 0x45b0, /*!< Clear wait cf config */
+ TFA2_BF_ICLMWSMU = 0x45c0, /*!< Clear audio mute sequence */
+ TFA2_BF_ICLCFMER = 0x45d0, /*!< Clear cfma err */
+ TFA2_BF_ICLCFMAC = 0x45e0, /*!< Clear cfma ack */
+ TFA2_BF_ICLCLKOOR = 0x45f0, /*!< Clear flag_clk_out_of_range */
+ TFA2_BF_ICLTDMER = 0x4600, /*!< Clear tdm error */
+ TFA2_BF_ICLCLPL = 0x4610, /*!< Clear clip left */
+ TFA2_BF_ICLCLPR = 0x4620, /*!< Clear clip right */
+ TFA2_BF_ICLOCPM = 0x4630, /*!< Clear mic ocpok */
+ TFA2_BF_IEVDDS = 0x4800, /*!< Enable por */
+ TFA2_BF_IEPLLS = 0x4810, /*!< Enable pll lock */
+ TFA2_BF_IEOTDS = 0x4820, /*!< Enable OTP alarm */
+ TFA2_BF_IEOVDS = 0x4830, /*!< Enable OVP alarm */
+ TFA2_BF_IEUVDS = 0x4840, /*!< Enable UVP alarm */
+ TFA2_BF_IECLKS = 0x4850, /*!< Enable clocks stable */
+ TFA2_BF_IEMTPB = 0x4860, /*!< Enable mtp busy */
+ TFA2_BF_IENOCLK = 0x4870, /*!< Enable lost clk */
+ TFA2_BF_IESPKS = 0x4880, /*!< Enable speaker error */
+ TFA2_BF_IEACS = 0x4890, /*!< Enable cold started */
+ TFA2_BF_IESWS = 0x48a0, /*!< Enable amplifier engage */
+ TFA2_BF_IEWDS = 0x48b0, /*!< Enable watchdog */
+ TFA2_BF_IEAMPS = 0x48c0, /*!< Enable enbl amp */
+ TFA2_BF_IEAREFS = 0x48d0, /*!< Enable ref enable */
+ TFA2_BF_IEADCCR = 0x48e0, /*!< Enable Control ADC */
+ TFA2_BF_IEBODNOK = 0x48f0, /*!< Enable BOD */
+ TFA2_BF_IEBSTCU = 0x4900, /*!< Enable DCDC current limiting */
+ TFA2_BF_IEBSTHI = 0x4910, /*!< Enable DCDC active */
+ TFA2_BF_IEBSTOC = 0x4920, /*!< Enable DCDC OCP */
+ TFA2_BF_IEBSTPC = 0x4930, /*!< Enable bst peakcur */
+ TFA2_BF_IEBSTVC = 0x4940, /*!< Enable DCDC level 1x */
+ TFA2_BF_IEBST86 = 0x4950, /*!< Enable DCDC level 1.14x */
+ TFA2_BF_IEBST93 = 0x4960, /*!< Enable DCDC level 1.07x */
+ TFA2_BF_IERCVLD = 0x4970, /*!< Enable rcvldop ready */
+ TFA2_BF_IEOCPL = 0x4980, /*!< Enable ocp alarm left */
+ TFA2_BF_IEOCPR = 0x4990, /*!< Enable ocp alarm right */
+ TFA2_BF_IEMWSRC = 0x49a0, /*!< Enable waits HW I2C settings */
+ TFA2_BF_IEMWCFC = 0x49b0, /*!< Enable man wait cf config */
+ TFA2_BF_IEMWSMU = 0x49c0, /*!< Enable man Audio mute sequence */
+ TFA2_BF_IECFMER = 0x49d0, /*!< Enable cfma err */
+ TFA2_BF_IECFMAC = 0x49e0, /*!< Enable cfma ack */
+ TFA2_BF_IECLKOOR = 0x49f0, /*!< Enable flag_clk_out_of_range */
+ TFA2_BF_IETDMER = 0x4a00, /*!< Enable tdm error */
+ TFA2_BF_IECLPL = 0x4a10, /*!< Enable clip left */
+ TFA2_BF_IECLPR = 0x4a20, /*!< Enable clip right */
+ TFA2_BF_IEOCPM1 = 0x4a30, /*!< Enable mic ocpok */
+ TFA2_BF_IPOVDDS = 0x4c00, /*!< Polarity por */
+ TFA2_BF_IPOPLLS = 0x4c10, /*!< Polarity pll lock */
+ TFA2_BF_IPOOTDS = 0x4c20, /*!< Polarity OTP alarm */
+ TFA2_BF_IPOOVDS = 0x4c30, /*!< Polarity OVP alarm */
+ TFA2_BF_IPOUVDS = 0x4c40, /*!< Polarity UVP alarm */
+ TFA2_BF_IPOCLKS = 0x4c50, /*!< Polarity clocks stable */
+ TFA2_BF_IPOMTPB = 0x4c60, /*!< Polarity mtp busy */
+ TFA2_BF_IPONOCLK = 0x4c70, /*!< Polarity lost clk */
+ TFA2_BF_IPOSPKS = 0x4c80, /*!< Polarity speaker error */
+ TFA2_BF_IPOACS = 0x4c90, /*!< Polarity cold started */
+ TFA2_BF_IPOSWS = 0x4ca0, /*!< Polarity amplifier engage */
+ TFA2_BF_IPOWDS = 0x4cb0, /*!< Polarity watchdog */
+ TFA2_BF_IPOAMPS = 0x4cc0, /*!< Polarity enbl amp */
+ TFA2_BF_IPOAREFS = 0x4cd0, /*!< Polarity ref enable */
+ TFA2_BF_IPOADCCR = 0x4ce0, /*!< Polarity Control ADC */
+ TFA2_BF_IPOBODNOK = 0x4cf0, /*!< Polarity BOD */
+ TFA2_BF_IPOBSTCU = 0x4d00, /*!< Polarity DCDC current limiting */
+ TFA2_BF_IPOBSTHI = 0x4d10, /*!< Polarity DCDC active */
+ TFA2_BF_IPOBSTOC = 0x4d20, /*!< Polarity DCDC OCP */
+ TFA2_BF_IPOBSTPC = 0x4d30, /*!< Polarity bst peakcur */
+ TFA2_BF_IPOBSTVC = 0x4d40, /*!< Polarity DCDC level 1x */
+ TFA2_BF_IPOBST86 = 0x4d50, /*!< Polarity DCDC level 1.14x */
+ TFA2_BF_IPOBST93 = 0x4d60, /*!< Polarity DCDC level 1.07x */
+ TFA2_BF_IPORCVLD = 0x4d70, /*!< Polarity rcvldop ready */
+ TFA2_BF_IPOOCPL = 0x4d80, /*!< Polarity ocp alarm left */
+ TFA2_BF_IPOOCPR = 0x4d90, /*!< Polarity ocp alarm right */
+ TFA2_BF_IPOMWSRC = 0x4da0, /*!< Polarity waits HW I2C settings */
+ TFA2_BF_IPOMWCFC = 0x4db0, /*!< Polarity man wait cf config */
+ TFA2_BF_IPOMWSMU = 0x4dc0, /*!< Polarity man audio mute sequence */
+ TFA2_BF_IPOCFMER = 0x4dd0, /*!< Polarity cfma err */
+ TFA2_BF_IPOCFMAC = 0x4de0, /*!< Polarity cfma ack */
+ TFA2_BF_IPCLKOOR = 0x4df0, /*!< Polarity flag_clk_out_of_range */
+ TFA2_BF_IPOTDMER = 0x4e00, /*!< Polarity tdm error */
+ TFA2_BF_IPOCLPL = 0x4e10, /*!< Polarity clip left */
+ TFA2_BF_IPOCLPR = 0x4e20, /*!< Polarity clip right */
+ TFA2_BF_IPOOCPM = 0x4e30, /*!< Polarity mic ocpok */
+ TFA2_BF_BSSCR = 0x5001, /*!< Battery protection attack Time */
+ TFA2_BF_BSST = 0x5023, /*!< Battery protection threshold voltage level */
+ TFA2_BF_BSSRL = 0x5061, /*!< Battery protection maximum reduction */
+ TFA2_BF_BSSRR = 0x5082, /*!< Battery protection release time */
+ TFA2_BF_BSSHY = 0x50b1, /*!< Battery protection hysteresis */
+ TFA2_BF_BSSR = 0x50e0, /*!< Battery voltage read out */
+ TFA2_BF_BSSBY = 0x50f0, /*!< Bypass HW clipper */
+ TFA2_BF_BSSS = 0x5100, /*!< Vbat prot steepness */
+ TFA2_BF_INTSMUTE = 0x5110, /*!< Soft mute HW */
+ TFA2_BF_CFSML = 0x5120, /*!< Soft mute FW left */
+ TFA2_BF_CFSMR = 0x5130, /*!< Soft mute FW right */
+ TFA2_BF_HPFBYPL = 0x5140, /*!< Bypass HPF left */
+ TFA2_BF_HPFBYPR = 0x5150, /*!< Bypass HPF right */
+ TFA2_BF_DPSAL = 0x5160, /*!< Enable DPSA left */
+ TFA2_BF_DPSAR = 0x5170, /*!< Enable DPSA right */
+ TFA2_BF_VOL = 0x5187, /*!< FW volume control for primary audio channel */
+ TFA2_BF_HNDSFRCV = 0x5200, /*!< Selection receiver */
+ TFA2_BF_CLIPCTRL = 0x5222, /*!< Clip control setting */
+ TFA2_BF_AMPGAIN = 0x5257, /*!< Amplifier gain */
+ TFA2_BF_SLOPEE = 0x52d0, /*!< Enables slope control */
+ TFA2_BF_SLOPESET = 0x52e1, /*!< Set slope */
+ TFA2_BF_VOLSEC = 0x5a07, /*!< FW volume control for secondary audio channel */
+ TFA2_BF_SWPROFIL = 0x5a87, /*!< Software profile data */
+ TFA2_BF_DCVO = 0x7002, /*!< Boost voltage */
+ TFA2_BF_DCMCC = 0x7033, /*!< Max coil current */
+ TFA2_BF_DCCV = 0x7071, /*!< Coil Value */
+ TFA2_BF_DCIE = 0x7090, /*!< Adaptive boost mode */
+ TFA2_BF_DCSR = 0x70a0, /*!< Soft ramp up/down */
+ TFA2_BF_DCSYNCP = 0x70b2, /*!< DCDC synchronization off + 7 positions */
+ TFA2_BF_DCDIS = 0x70e0, /*!< DCDC on/off */
+ TFA2_BF_RST = 0x9000, /*!< Reset */
+ TFA2_BF_DMEM = 0x9011, /*!< Target memory */
+ TFA2_BF_AIF = 0x9030, /*!< Auto increment */
+ TFA2_BF_CFINT = 0x9040, /*!< Interrupt - auto clear */
+ TFA2_BF_CFCGATE = 0x9050, /*!< Coolflux clock gating disabling control */
+ TFA2_BF_REQ = 0x9087, /*!< request for access (8 channels) */
+ TFA2_BF_REQCMD = 0x9080, /*!< Firmware event request rpc command */
+ TFA2_BF_REQRST = 0x9090, /*!< Firmware event request reset restart */
+ TFA2_BF_REQMIPS = 0x90a0, /*!< Firmware event request short on mips */
+ TFA2_BF_REQMUTED = 0x90b0, /*!< Firmware event request mute sequence ready */
+ TFA2_BF_REQVOL = 0x90c0, /*!< Firmware event request volume ready */
+ TFA2_BF_REQDMG = 0x90d0, /*!< Firmware event request speaker damage detected */
+ TFA2_BF_REQCAL = 0x90e0, /*!< Firmware event request calibration completed */
+ TFA2_BF_REQRSV = 0x90f0, /*!< Firmware event request reserved */
+ TFA2_BF_MADD = 0x910f, /*!< Memory address */
+ TFA2_BF_MEMA = 0x920f, /*!< Activate memory access */
+ TFA2_BF_ERR = 0x9307, /*!< Error flags */
+ TFA2_BF_ACK = 0x9387, /*!< Acknowledge of requests */
+ TFA2_BF_ACKCMD = 0x9380, /*!< Firmware event acknowledge rpc command */
+ TFA2_BF_ACKRST = 0x9390, /*!< Firmware event acknowledge reset restart */
+ TFA2_BF_ACKMIPS = 0x93a0, /*!< Firmware event acknowledge short on mips */
+ TFA2_BF_ACKMUTED = 0x93b0, /*!< Firmware event acknowledge mute sequence ready */
+ TFA2_BF_ACKVOL = 0x93c0, /*!< Firmware event acknowledge volume ready */
+ TFA2_BF_ACKDMG = 0x93d0, /*!< Firmware event acknowledge speaker damage detected */
+ TFA2_BF_ACKCAL = 0x93e0, /*!< Firmware event acknowledge calibration completed */
+ TFA2_BF_ACKRSV = 0x93f0, /*!< Firmware event acknowledge reserved */
+ TFA2_BF_MTPK = 0xa107, /*!< MTP KEY2 register */
+ TFA2_BF_KEY1LOCKED = 0xa200, /*!< Indicates KEY1 is locked */
+ TFA2_BF_KEY2LOCKED = 0xa210, /*!< Indicates KEY2 is locked */
+ TFA2_BF_CIMTP = 0xa360, /*!< Start copying data from I2C mtp registers to mtp */
+ TFA2_BF_MTPRDMSB = 0xa50f, /*!< MSB word of MTP manual read data */
+ TFA2_BF_MTPRDLSB = 0xa60f, /*!< LSB word of MTP manual read data */
+ TFA2_BF_EXTTS = 0xb108, /*!< External temperature (C) */
+ TFA2_BF_TROS = 0xb190, /*!< Select temp Speaker calibration */
+ TFA2_BF_MTPOTC = 0xf000, /*!< Calibration schedule */
+ TFA2_BF_MTPEX = 0xf010, /*!< Calibration Ron executed */
+ TFA2_BF_DCMCCAPI = 0xf020, /*!< Calibration current limit DCDC */
+ TFA2_BF_DCMCCSB = 0xf030, /*!< Sign bit for delta calibration current limit DCDC */
+ TFA2_BF_USERDEF = 0xf042, /*!< Calibration delta current limit DCDC */
+ TFA2_BF_R25CL = 0xf40f, /*!< Ron resistance of left channel speaker coil */
+ TFA2_BF_R25CR = 0xf50f, /*!< Ron resistance of right channel speaker coil */
+} nxpTfa2BfEnumList_t;
+#define TFA2_NAMETABLE static tfaBfName_t Tfa2DatasheetNames[] = {\
+ { 0x0, "PWDN"}, /* Powerdown selection , */\
+ { 0x10, "I2CR"}, /* I2C Reset - Auto clear , */\
+ { 0x20, "CFE"}, /* Enable CoolFlux , */\
+ { 0x30, "AMPE"}, /* Activate Amplifier , */\
+ { 0x40, "DCA"}, /* Activate DC-to-DC converter , */\
+ { 0x50, "SBSL"}, /* Coolflux configured , */\
+ { 0x60, "AMPC"}, /* CoolFlux controls amplifier , */\
+ { 0x71, "INTP"}, /* Interrupt config , */\
+ { 0x91, "FSSSEL"}, /* Audio sample reference , */\
+ { 0xb0, "BYPOCP"}, /* Bypass OCP , */\
+ { 0xc0, "TSTOCP"}, /* OCP testing control , */\
+ { 0x101, "AMPINSEL"}, /* Amplifier input selection , */\
+ { 0x120, "MANSCONF"}, /* I2C configured , */\
+ { 0x130, "MANCOLD"}, /* Execute cold start , */\
+ { 0x140, "MANAOOSC"}, /* Internal osc off at PWDN , */\
+ { 0x150, "MANROBOD"}, /* Reaction on BOD , */\
+ { 0x160, "BODE"}, /* BOD Enable , */\
+ { 0x170, "BODHYS"}, /* BOD Hysteresis , */\
+ { 0x181, "BODFILT"}, /* BOD filter , */\
+ { 0x1a1, "BODTHLVL"}, /* BOD threshold , */\
+ { 0x1d0, "MUTETO"}, /* Time out SB mute sequence , */\
+ { 0x1e0, "RCVNS"}, /* Noise shaper selection , */\
+ { 0x1f0, "MANWDE"}, /* Watchdog manager reaction , */\
+ { 0x203, "AUDFS"}, /* Sample rate (fs) , */\
+ { 0x240, "INPLEV"}, /* TDM output attenuation , */\
+ { 0x255, "FRACTDEL"}, /* V/I Fractional delay , */\
+ { 0x2b0, "BYPHVBF"}, /* Bypass HVBAT filter , */\
+ { 0x2c0, "LDOBYP"}, /* Receiver LDO bypass , */\
+ { 0x30f, "REV"}, /* Revision info , */\
+ { 0x401, "REFCKEXT"}, /* PLL external ref clock , */\
+ { 0x420, "REFCKSEL"}, /* PLL internal ref clock , */\
+ { 0x500, "SSLEFTE"}, /* Enable left channel , */\
+ { 0x510, "SSRIGHTE"}, /* Enable right channel , */\
+ { 0x520, "VSLEFTE"}, /* Voltage sense left , */\
+ { 0x530, "VSRIGHTE"}, /* Voltage sense right , */\
+ { 0x540, "CSLEFTE"}, /* Current sense left , */\
+ { 0x550, "CSRIGHTE"}, /* Current sense right , */\
+ { 0x560, "SSPDME"}, /* Sub-system PDM , */\
+ { 0xd18, "STGAIN"}, /* Side tone gain , */\
+ { 0xda0, "PDMSMUTE"}, /* Side tone soft mute , */\
+ { 0xe06, "SWVSTEP"}, /* Register for the host SW to record the current active vstep, */\
+ { 0x1000, "VDDS"}, /* POR , */\
+ { 0x1010, "PLLS"}, /* PLL lock , */\
+ { 0x1020, "OTDS"}, /* OTP alarm , */\
+ { 0x1030, "OVDS"}, /* OVP alarm , */\
+ { 0x1040, "UVDS"}, /* UVP alarm , */\
+ { 0x1050, "CLKS"}, /* Clocks stable , */\
+ { 0x1060, "MTPB"}, /* MTP busy , */\
+ { 0x1070, "NOCLK"}, /* Lost clock , */\
+ { 0x1080, "SPKS"}, /* Speaker error , */\
+ { 0x1090, "ACS"}, /* Cold Start , */\
+ { 0x10a0, "SWS"}, /* Amplifier engage , */\
+ { 0x10b0, "WDS"}, /* Watchdog , */\
+ { 0x10c0, "AMPS"}, /* Amplifier enable , */\
+ { 0x10d0, "AREFS"}, /* References enable , */\
+ { 0x10e0, "ADCCR"}, /* Control ADC , */\
+ { 0x10f0, "BODNOK"}, /* BOD , */\
+ { 0x1100, "DCIL"}, /* DCDC current limiting , */\
+ { 0x1110, "DCDCA"}, /* DCDC active , */\
+ { 0x1120, "DCOCPOK"}, /* DCDC OCP nmos , */\
+ { 0x1140, "DCHVBAT"}, /* DCDC level 1x , */\
+ { 0x1150, "DCH114"}, /* DCDC level 1.14x , */\
+ { 0x1160, "DCH107"}, /* DCDC level 1.07x , */\
+ { 0x1170, "STMUTEB"}, /* side tone (un)mute busy , */\
+ { 0x1180, "STMUTE"}, /* side tone mute state , */\
+ { 0x1190, "TDMLUTER"}, /* TDM LUT error , */\
+ { 0x11a2, "TDMSTAT"}, /* TDM status bits , */\
+ { 0x11d0, "TDMERR"}, /* TDM error , */\
+ { 0x11e0, "HAPTIC"}, /* Status haptic driver , */\
+ { 0x1200, "OCPOAPL"}, /* OCPOK pmos A left , */\
+ { 0x1210, "OCPOANL"}, /* OCPOK nmos A left , */\
+ { 0x1220, "OCPOBPL"}, /* OCPOK pmos B left , */\
+ { 0x1230, "OCPOBNL"}, /* OCPOK nmos B left , */\
+ { 0x1240, "CLIPAHL"}, /* Clipping A left to Vddp , */\
+ { 0x1250, "CLIPALL"}, /* Clipping A left to gnd , */\
+ { 0x1260, "CLIPBHL"}, /* Clipping B left to Vddp , */\
+ { 0x1270, "CLIPBLL"}, /* Clipping B left to gnd , */\
+ { 0x1280, "OCPOAPRC"}, /* OCPOK pmos A RCV , */\
+ { 0x1290, "OCPOANRC"}, /* OCPOK nmos A RCV , */\
+ { 0x12a0, "OCPOBPRC"}, /* OCPOK pmos B RCV , */\
+ { 0x12b0, "OCPOBNRC"}, /* OCPOK nmos B RCV , */\
+ { 0x12c0, "RCVLDOR"}, /* RCV LDO regulates , */\
+ { 0x12d0, "RCVLDOBR"}, /* Receiver LDO ready , */\
+ { 0x12e0, "OCDSL"}, /* OCP left amplifier , */\
+ { 0x12f0, "CLIPSL"}, /* Amplifier left clipping , */\
+ { 0x1300, "OCPOAPR"}, /* OCPOK pmos A right , */\
+ { 0x1310, "OCPOANR"}, /* OCPOK nmos A right , */\
+ { 0x1320, "OCPOBPR"}, /* OCPOK pmos B right , */\
+ { 0x1330, "OCPOBNR"}, /* OCPOK nmos B right , */\
+ { 0x1340, "CLIPAHR"}, /* Clipping A right to Vddp , */\
+ { 0x1350, "CLIPALR"}, /* Clipping A right to gnd , */\
+ { 0x1360, "CLIPBHR"}, /* Clipping B left to Vddp , */\
+ { 0x1370, "CLIPBLR"}, /* Clipping B right to gnd , */\
+ { 0x1380, "OCDSR"}, /* OCP right amplifier , */\
+ { 0x1390, "CLIPSR"}, /* Amplifier right clipping , */\
+ { 0x13a0, "OCPOKMC"}, /* OCPOK MICVDD , */\
+ { 0x13b0, "MANALARM"}, /* Alarm state , */\
+ { 0x13c0, "MANWAIT1"}, /* Wait HW I2C settings , */\
+ { 0x13d0, "MANWAIT2"}, /* Wait CF config , */\
+ { 0x13e0, "MANMUTE"}, /* Audio mute sequence , */\
+ { 0x13f0, "MANOPER"}, /* Operating state , */\
+ { 0x1400, "SPKSL"}, /* Left speaker status , */\
+ { 0x1410, "SPKSR"}, /* Right speaker status , */\
+ { 0x1420, "CLKOOR"}, /* External clock status , */\
+ { 0x1433, "MANSTATE"}, /* Device manager status , */\
+ { 0x1509, "BATS"}, /* Battery voltage (V) , */\
+ { 0x1608, "TEMPS"}, /* IC Temperature (C) , */\
+ { 0x2003, "TDMUC"}, /* Usecase setting , */\
+ { 0x2040, "TDME"}, /* Enable interface , */\
+ { 0x2050, "TDMMODE"}, /* Slave/master , */\
+ { 0x2060, "TDMCLINV"}, /* Reception data to BCK clock , */\
+ { 0x2073, "TDMFSLN"}, /* FS length (master mode only) , */\
+ { 0x20b0, "TDMFSPOL"}, /* FS polarity , */\
+ { 0x20c3, "TDMNBCK"}, /* N-BCK's in FS , */\
+ { 0x2103, "TDMSLOTS"}, /* N-slots in Frame , */\
+ { 0x2144, "TDMSLLN"}, /* N-bits in slot , */\
+ { 0x2194, "TDMBRMG"}, /* N-bits remaining , */\
+ { 0x21e0, "TDMDEL"}, /* data delay to FS , */\
+ { 0x21f0, "TDMADJ"}, /* data adjustment , */\
+ { 0x2201, "TDMOOMP"}, /* Received audio compression , */\
+ { 0x2224, "TDMSSIZE"}, /* Sample size per slot , */\
+ { 0x2271, "TDMTXDFO"}, /* Format unused bits , */\
+ { 0x2291, "TDMTXUS0"}, /* Format unused slots GAINIO , */\
+ { 0x22b1, "TDMTXUS1"}, /* Format unused slots DIO1 , */\
+ { 0x22d1, "TDMTXUS2"}, /* Format unused slots DIO2 , */\
+ { 0x2310, "TDMLE"}, /* Control audio left , */\
+ { 0x2320, "TDMRE"}, /* Control audio right , */\
+ { 0x2340, "TDMVSRE"}, /* Control voltage sense right , */\
+ { 0x2350, "TDMCSRE"}, /* Control current sense right , */\
+ { 0x2360, "TDMVSLE"}, /* Voltage sense left control , */\
+ { 0x2370, "TDMCSLE"}, /* Current sense left control , */\
+ { 0x2380, "TDMCFRE"}, /* DSP out right control , */\
+ { 0x2390, "TDMCFLE"}, /* DSP out left control , */\
+ { 0x23a0, "TDMCF3E"}, /* AEC ref left control , */\
+ { 0x23b0, "TDMCF4E"}, /* AEC ref right control , */\
+ { 0x23c0, "TDMPD1E"}, /* PDM 1 control , */\
+ { 0x23d0, "TDMPD2E"}, /* PDM 2 control , */\
+ { 0x2421, "TDMLIO"}, /* IO audio left , */\
+ { 0x2441, "TDMRIO"}, /* IO audio right , */\
+ { 0x2481, "TDMVSRIO"}, /* IO voltage sense right , */\
+ { 0x24a1, "TDMCSRIO"}, /* IO current sense right , */\
+ { 0x24c1, "TDMVSLIO"}, /* IO voltage sense left , */\
+ { 0x24e1, "TDMCSLIO"}, /* IO current sense left , */\
+ { 0x2501, "TDMCFRIO"}, /* IO dspout right , */\
+ { 0x2521, "TDMCFLIO"}, /* IO dspout left , */\
+ { 0x2541, "TDMCF3IO"}, /* IO AEC ref left control , */\
+ { 0x2561, "TDMCF4IO"}, /* IO AEC ref right control , */\
+ { 0x2581, "TDMPD1IO"}, /* IO pdm1 , */\
+ { 0x25a1, "TDMPD2IO"}, /* IO pdm2 , */\
+ { 0x2643, "TDMLS"}, /* Position audio left , */\
+ { 0x2683, "TDMRS"}, /* Position audio right , */\
+ { 0x2703, "TDMVSRS"}, /* Position voltage sense right , */\
+ { 0x2743, "TDMCSRS"}, /* Position current sense right , */\
+ { 0x2783, "TDMVSLS"}, /* Position voltage sense left , */\
+ { 0x27c3, "TDMCSLS"}, /* Position current sense left , */\
+ { 0x2803, "TDMCFRS"}, /* Position dspout right , */\
+ { 0x2843, "TDMCFLS"}, /* Position dspout left , */\
+ { 0x2883, "TDMCF3S"}, /* Position AEC ref left control , */\
+ { 0x28c3, "TDMCF4S"}, /* Position AEC ref right control , */\
+ { 0x2903, "TDMPD1S"}, /* Position pdm1 , */\
+ { 0x2943, "TDMPD2S"}, /* Position pdm2 , */\
+ { 0x3100, "PDMSM"}, /* PDM control , */\
+ { 0x3111, "PDMSTSEL"}, /* Side tone input , */\
+ { 0x3130, "PDMLSEL"}, /* PDM data selection for left channel during PDM direct mode, */\
+ { 0x3140, "PDMRSEL"}, /* PDM data selection for right channel during PDM direct mode, */\
+ { 0x3150, "MICVDDE"}, /* Enable MICVDD , */\
+ { 0x3201, "PDMCLRAT"}, /* PDM BCK/Fs ratio , */\
+ { 0x3223, "PDMGAIN"}, /* PDM gain , */\
+ { 0x3263, "PDMOSEL"}, /* PDM output selection - RE/FE data combination , */\
+ { 0x32a0, "SELCFHAPD"}, /* Select the source for haptic data output (not for customer), */\
+ { 0x3307, "HAPTIME"}, /* Duration (ms) , */\
+ { 0x3387, "HAPLEVEL"}, /* DC value (FFS) , */\
+ { 0x3403, "GPIODIN"}, /* Receiving value , */\
+ { 0x3500, "GPIOCTRL"}, /* GPIO master control over GPIO1/2 ports (not for customer), */\
+ { 0x3513, "GPIOCONF"}, /* Configuration , */\
+ { 0x3553, "GPIODOUT"}, /* Transmitting value , */\
+ { 0x4000, "ISTVDDS"}, /* Status POR , */\
+ { 0x4010, "ISTPLLS"}, /* Status PLL lock , */\
+ { 0x4020, "ISTOTDS"}, /* Status OTP alarm , */\
+ { 0x4030, "ISTOVDS"}, /* Status OVP alarm , */\
+ { 0x4040, "ISTUVDS"}, /* Status UVP alarm , */\
+ { 0x4050, "ISTCLKS"}, /* Status clocks stable , */\
+ { 0x4060, "ISTMTPB"}, /* Status MTP busy , */\
+ { 0x4070, "ISTNOCLK"}, /* Status lost clock , */\
+ { 0x4080, "ISTSPKS"}, /* Status speaker error , */\
+ { 0x4090, "ISTACS"}, /* Status cold start , */\
+ { 0x40a0, "ISTSWS"}, /* Status amplifier engage , */\
+ { 0x40b0, "ISTWDS"}, /* Status watchdog , */\
+ { 0x40c0, "ISTAMPS"}, /* Status amplifier enable , */\
+ { 0x40d0, "ISTAREFS"}, /* Status Ref enable , */\
+ { 0x40e0, "ISTADCCR"}, /* Status Control ADC , */\
+ { 0x40f0, "ISTBODNOK"}, /* Status BOD , */\
+ { 0x4100, "ISTBSTCU"}, /* Status DCDC current limiting , */\
+ { 0x4110, "ISTBSTHI"}, /* Status DCDC active , */\
+ { 0x4120, "ISTBSTOC"}, /* Status DCDC OCP , */\
+ { 0x4130, "ISTBSTPKCUR"}, /* Status bst peakcur , */\
+ { 0x4140, "ISTBSTVC"}, /* Status DCDC level 1x , */\
+ { 0x4150, "ISTBST86"}, /* Status DCDC level 1.14x , */\
+ { 0x4160, "ISTBST93"}, /* Status DCDC level 1.07x , */\
+ { 0x4170, "ISTRCVLD"}, /* Status rcvldop ready , */\
+ { 0x4180, "ISTOCPL"}, /* Status ocp alarm left , */\
+ { 0x4190, "ISTOCPR"}, /* Status ocp alarm right , */\
+ { 0x41a0, "ISTMWSRC"}, /* Status Waits HW I2C settings , */\
+ { 0x41b0, "ISTMWCFC"}, /* Status waits CF config , */\
+ { 0x41c0, "ISTMWSMU"}, /* Status Audio mute sequence , */\
+ { 0x41d0, "ISTCFMER"}, /* Status cfma error , */\
+ { 0x41e0, "ISTCFMAC"}, /* Status cfma ack , */\
+ { 0x41f0, "ISTCLKOOR"}, /* Status flag_clk_out_of_range , */\
+ { 0x4200, "ISTTDMER"}, /* Status tdm error , */\
+ { 0x4210, "ISTCLPL"}, /* Status clip left , */\
+ { 0x4220, "ISTCLPR"}, /* Status clip right , */\
+ { 0x4230, "ISTOCPM"}, /* Status mic ocpok , */\
+ { 0x4400, "ICLVDDS"}, /* Clear POR , */\
+ { 0x4410, "ICLPLLS"}, /* Clear PLL lock , */\
+ { 0x4420, "ICLOTDS"}, /* Clear OTP alarm , */\
+ { 0x4430, "ICLOVDS"}, /* Clear OVP alarm , */\
+ { 0x4440, "ICLUVDS"}, /* Clear UVP alarm , */\
+ { 0x4450, "ICLCLKS"}, /* Clear clocks stable , */\
+ { 0x4460, "ICLMTPB"}, /* Clear mtp busy , */\
+ { 0x4470, "ICLNOCLK"}, /* Clear lost clk , */\
+ { 0x4480, "ICLSPKS"}, /* Clear speaker error , */\
+ { 0x4490, "ICLACS"}, /* Clear cold started , */\
+ { 0x44a0, "ICLSWS"}, /* Clear amplifier engage , */\
+ { 0x44b0, "ICLWDS"}, /* Clear watchdog , */\
+ { 0x44c0, "ICLAMPS"}, /* Clear enbl amp , */\
+ { 0x44d0, "ICLAREFS"}, /* Clear ref enable , */\
+ { 0x44e0, "ICLADCCR"}, /* Clear control ADC , */\
+ { 0x44f0, "ICLBODNOK"}, /* Clear BOD , */\
+ { 0x4500, "ICLBSTCU"}, /* Clear DCDC current limiting , */\
+ { 0x4510, "ICLBSTHI"}, /* Clear DCDC active , */\
+ { 0x4520, "ICLBSTOC"}, /* Clear DCDC OCP , */\
+ { 0x4530, "ICLBSTPC"}, /* Clear bst peakcur , */\
+ { 0x4540, "ICLBSTVC"}, /* Clear DCDC level 1x , */\
+ { 0x4550, "ICLBST86"}, /* Clear DCDC level 1.14x , */\
+ { 0x4560, "ICLBST93"}, /* Clear DCDC level 1.07x , */\
+ { 0x4570, "ICLRCVLD"}, /* Clear rcvldop ready , */\
+ { 0x4580, "ICLOCPL"}, /* Clear ocp alarm left , */\
+ { 0x4590, "ICLOCPR"}, /* Clear ocp alarm right , */\
+ { 0x45a0, "ICLMWSRC"}, /* Clear wait HW I2C settings , */\
+ { 0x45b0, "ICLMWCFC"}, /* Clear wait cf config , */\
+ { 0x45c0, "ICLMWSMU"}, /* Clear audio mute sequence , */\
+ { 0x45d0, "ICLCFMER"}, /* Clear cfma err , */\
+ { 0x45e0, "ICLCFMAC"}, /* Clear cfma ack , */\
+ { 0x45f0, "ICLCLKOOR"}, /* Clear flag_clk_out_of_range , */\
+ { 0x4600, "ICLTDMER"}, /* Clear tdm error , */\
+ { 0x4610, "ICLCLPL"}, /* Clear clip left , */\
+ { 0x4620, "ICLCLPR"}, /* Clear clip right , */\
+ { 0x4630, "ICLOCPM"}, /* Clear mic ocpok , */\
+ { 0x4800, "IEVDDS"}, /* Enable por , */\
+ { 0x4810, "IEPLLS"}, /* Enable pll lock , */\
+ { 0x4820, "IEOTDS"}, /* Enable OTP alarm , */\
+ { 0x4830, "IEOVDS"}, /* Enable OVP alarm , */\
+ { 0x4840, "IEUVDS"}, /* Enable UVP alarm , */\
+ { 0x4850, "IECLKS"}, /* Enable clocks stable , */\
+ { 0x4860, "IEMTPB"}, /* Enable mtp busy , */\
+ { 0x4870, "IENOCLK"}, /* Enable lost clk , */\
+ { 0x4880, "IESPKS"}, /* Enable speaker error , */\
+ { 0x4890, "IEACS"}, /* Enable cold started , */\
+ { 0x48a0, "IESWS"}, /* Enable amplifier engage , */\
+ { 0x48b0, "IEWDS"}, /* Enable watchdog , */\
+ { 0x48c0, "IEAMPS"}, /* Enable enbl amp , */\
+ { 0x48d0, "IEAREFS"}, /* Enable ref enable , */\
+ { 0x48e0, "IEADCCR"}, /* Enable Control ADC , */\
+ { 0x48f0, "IEBODNOK"}, /* Enable BOD , */\
+ { 0x4900, "IEBSTCU"}, /* Enable DCDC current limiting , */\
+ { 0x4910, "IEBSTHI"}, /* Enable DCDC active , */\
+ { 0x4920, "IEBSTOC"}, /* Enable DCDC OCP , */\
+ { 0x4930, "IEBSTPC"}, /* Enable bst peakcur , */\
+ { 0x4940, "IEBSTVC"}, /* Enable DCDC level 1x , */\
+ { 0x4950, "IEBST86"}, /* Enable DCDC level 1.14x , */\
+ { 0x4960, "IEBST93"}, /* Enable DCDC level 1.07x , */\
+ { 0x4970, "IERCVLD"}, /* Enable rcvldop ready , */\
+ { 0x4980, "IEOCPL"}, /* Enable ocp alarm left , */\
+ { 0x4990, "IEOCPR"}, /* Enable ocp alarm right , */\
+ { 0x49a0, "IEMWSRC"}, /* Enable waits HW I2C settings , */\
+ { 0x49b0, "IEMWCFC"}, /* Enable man wait cf config , */\
+ { 0x49c0, "IEMWSMU"}, /* Enable man Audio mute sequence , */\
+ { 0x49d0, "IECFMER"}, /* Enable cfma err , */\
+ { 0x49e0, "IECFMAC"}, /* Enable cfma ack , */\
+ { 0x49f0, "IECLKOOR"}, /* Enable flag_clk_out_of_range , */\
+ { 0x4a00, "IETDMER"}, /* Enable tdm error , */\
+ { 0x4a10, "IECLPL"}, /* Enable clip left , */\
+ { 0x4a20, "IECLPR"}, /* Enable clip right , */\
+ { 0x4a30, "IEOCPM1"}, /* Enable mic ocpok , */\
+ { 0x4c00, "IPOVDDS"}, /* Polarity por , */\
+ { 0x4c10, "IPOPLLS"}, /* Polarity pll lock , */\
+ { 0x4c20, "IPOOTDS"}, /* Polarity OTP alarm , */\
+ { 0x4c30, "IPOOVDS"}, /* Polarity OVP alarm , */\
+ { 0x4c40, "IPOUVDS"}, /* Polarity UVP alarm , */\
+ { 0x4c50, "IPOCLKS"}, /* Polarity clocks stable , */\
+ { 0x4c60, "IPOMTPB"}, /* Polarity mtp busy , */\
+ { 0x4c70, "IPONOCLK"}, /* Polarity lost clk , */\
+ { 0x4c80, "IPOSPKS"}, /* Polarity speaker error , */\
+ { 0x4c90, "IPOACS"}, /* Polarity cold started , */\
+ { 0x4ca0, "IPOSWS"}, /* Polarity amplifier engage , */\
+ { 0x4cb0, "IPOWDS"}, /* Polarity watchdog , */\
+ { 0x4cc0, "IPOAMPS"}, /* Polarity enbl amp , */\
+ { 0x4cd0, "IPOAREFS"}, /* Polarity ref enable , */\
+ { 0x4ce0, "IPOADCCR"}, /* Polarity Control ADC , */\
+ { 0x4cf0, "IPOBODNOK"}, /* Polarity BOD , */\
+ { 0x4d00, "IPOBSTCU"}, /* Polarity DCDC current limiting , */\
+ { 0x4d10, "IPOBSTHI"}, /* Polarity DCDC active , */\
+ { 0x4d20, "IPOBSTOC"}, /* Polarity DCDC OCP , */\
+ { 0x4d30, "IPOBSTPC"}, /* Polarity bst peakcur , */\
+ { 0x4d40, "IPOBSTVC"}, /* Polarity DCDC level 1x , */\
+ { 0x4d50, "IPOBST86"}, /* Polarity DCDC level 1.14x , */\
+ { 0x4d60, "IPOBST93"}, /* Polarity DCDC level 1.07x , */\
+ { 0x4d70, "IPORCVLD"}, /* Polarity rcvldop ready , */\
+ { 0x4d80, "IPOOCPL"}, /* Polarity ocp alarm left , */\
+ { 0x4d90, "IPOOCPR"}, /* Polarity ocp alarm right , */\
+ { 0x4da0, "IPOMWSRC"}, /* Polarity waits HW I2C settings , */\
+ { 0x4db0, "IPOMWCFC"}, /* Polarity man wait cf config , */\
+ { 0x4dc0, "IPOMWSMU"}, /* Polarity man audio mute sequence , */\
+ { 0x4dd0, "IPOCFMER"}, /* Polarity cfma err , */\
+ { 0x4de0, "IPOCFMAC"}, /* Polarity cfma ack , */\
+ { 0x4df0, "IPCLKOOR"}, /* Polarity flag_clk_out_of_range , */\
+ { 0x4e00, "IPOTDMER"}, /* Polarity tdm error , */\
+ { 0x4e10, "IPOCLPL"}, /* Polarity clip left , */\
+ { 0x4e20, "IPOCLPR"}, /* Polarity clip right , */\
+ { 0x4e30, "IPOOCPM"}, /* Polarity mic ocpok , */\
+ { 0x5001, "BSSCR"}, /* Battery protection attack Time , */\
+ { 0x5023, "BSST"}, /* Battery protection threshold voltage level , */\
+ { 0x5061, "BSSRL"}, /* Battery protection maximum reduction , */\
+ { 0x5082, "BSSRR"}, /* Battery protection release time , */\
+ { 0x50b1, "BSSHY"}, /* Battery protection hysteresis , */\
+ { 0x50e0, "BSSR"}, /* Battery voltage read out , */\
+ { 0x50f0, "BSSBY"}, /* Bypass HW clipper , */\
+ { 0x5100, "BSSS"}, /* Vbat prot steepness , */\
+ { 0x5110, "INTSMUTE"}, /* Soft mute HW , */\
+ { 0x5120, "CFSML"}, /* Soft mute FW left , */\
+ { 0x5130, "CFSMR"}, /* Soft mute FW right , */\
+ { 0x5140, "HPFBYPL"}, /* Bypass HPF left , */\
+ { 0x5150, "HPFBYPR"}, /* Bypass HPF right , */\
+ { 0x5160, "DPSAL"}, /* Enable DPSA left , */\
+ { 0x5170, "DPSAR"}, /* Enable DPSA right , */\
+ { 0x5187, "VOL"}, /* FW volume control for primary audio channel , */\
+ { 0x5200, "HNDSFRCV"}, /* Selection receiver , */\
+ { 0x5222, "CLIPCTRL"}, /* Clip control setting , */\
+ { 0x5257, "AMPGAIN"}, /* Amplifier gain , */\
+ { 0x52d0, "SLOPEE"}, /* Enables slope control , */\
+ { 0x52e1, "SLOPESET"}, /* Set slope , */\
+ { 0x5a07, "VOLSEC"}, /* FW volume control for secondary audio channel , */\
+ { 0x5a87, "SWPROFIL"}, /* Software profile data , */\
+ { 0x7002, "DCVO"}, /* Boost voltage , */\
+ { 0x7033, "DCMCC"}, /* Max coil current , */\
+ { 0x7071, "DCCV"}, /* Coil Value , */\
+ { 0x7090, "DCIE"}, /* Adaptive boost mode , */\
+ { 0x70a0, "DCSR"}, /* Soft ramp up/down , */\
+ { 0x70b2, "DCSYNCP"}, /* DCDC synchronization off + 7 positions , */\
+ { 0x70e0, "DCDIS"}, /* DCDC on/off , */\
+ { 0x9000, "RST"}, /* Reset , */\
+ { 0x9011, "DMEM"}, /* Target memory , */\
+ { 0x9030, "AIF"}, /* Auto increment , */\
+ { 0x9040, "CFINT"}, /* Interrupt - auto clear , */\
+ { 0x9050, "CFCGATE"}, /* Coolflux clock gating disabling control , */\
+ { 0x9080, "REQCMD"}, /* Firmware event request rpc command , */\
+ { 0x9090, "REQRST"}, /* Firmware event request reset restart , */\
+ { 0x90a0, "REQMIPS"}, /* Firmware event request short on mips , */\
+ { 0x90b0, "REQMUTED"}, /* Firmware event request mute sequence ready , */\
+ { 0x90c0, "REQVOL"}, /* Firmware event request volume ready , */\
+ { 0x90d0, "REQDMG"}, /* Firmware event request speaker damage detected , */\
+ { 0x90e0, "REQCAL"}, /* Firmware event request calibration completed , */\
+ { 0x90f0, "REQRSV"}, /* Firmware event request reserved , */\
+ { 0x910f, "MADD"}, /* Memory address , */\
+ { 0x920f, "MEMA"}, /* Activate memory access , */\
+ { 0x9307, "ERR"}, /* Error flags , */\
+ { 0x9387, "ACK"}, /* Acknowledge of requests , */\
+ { 0x9380, "ACKCMD"}, /* Firmware event acknowledge rpc command , */\
+ { 0x9390, "ACKRST"}, /* Firmware event acknowledge reset restart , */\
+ { 0x93a0, "ACKMIPS"}, /* Firmware event acknowledge short on mips , */\
+ { 0x93b0, "ACKMUTED"}, /* Firmware event acknowledge mute sequence ready , */\
+ { 0x93c0, "ACKVOL"}, /* Firmware event acknowledge volume ready , */\
+ { 0x93d0, "ACKDMG"}, /* Firmware event acknowledge speaker damage detected, */\
+ { 0x93e0, "ACKCAL"}, /* Firmware event acknowledge calibration completed , */\
+ { 0x93f0, "ACKRSV"}, /* Firmware event acknowledge reserved , */\
+ { 0xa107, "MTPK"}, /* MTP KEY2 register , */\
+ { 0xa200, "KEY1LOCKED"}, /* Indicates KEY1 is locked , */\
+ { 0xa210, "KEY2LOCKED"}, /* Indicates KEY2 is locked , */\
+ { 0xa360, "CIMTP"}, /* Start copying data from I2C mtp registers to mtp , */\
+ { 0xa50f, "MTPRDMSB"}, /* MSB word of MTP manual read data , */\
+ { 0xa60f, "MTPRDLSB"}, /* LSB word of MTP manual read data , */\
+ { 0xb108, "EXTTS"}, /* External temperature (C) , */\
+ { 0xb190, "TROS"}, /* Select temp Speaker calibration , */\
+ { 0xf000, "MTPOTC"}, /* Calibration schedule , */\
+ { 0xf010, "MTPEX"}, /* Calibration Ron executed , */\
+ { 0xf020, "DCMCCAPI"}, /* Calibration current limit DCDC , */\
+ { 0xf030, "DCMCCSB"}, /* Sign bit for delta calibration current limit DCDC , */\
+ { 0xf042, "USERDEF"}, /* Calibration delta current limit DCDC , */\
+ { 0xf40f, "R25CL"}, /* Ron resistance of left channel speaker coil , */\
+ { 0xf50f, "R25CR"}, /* Ron resistance of right channel speaker coil , */\
+ { 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+
+#define TFA2_BITNAMETABLE static tfaBfName_t Tfa2BitNames[] = {\
+ { 0x0, "powerdown"}, /* Powerdown selection , */\
+ { 0x10, "reset"}, /* I2C Reset - Auto clear , */\
+ { 0x20, "enbl_coolflux"}, /* Enable CoolFlux , */\
+ { 0x30, "enbl_amplifier"}, /* Activate Amplifier , */\
+ { 0x40, "enbl_boost"}, /* Activate DC-to-DC converter , */\
+ { 0x50, "coolflux_configured"}, /* Coolflux configured , */\
+ { 0x60, "sel_enbl_amplifier"}, /* CoolFlux controls amplifier , */\
+ { 0x71, "int_pad_io"}, /* Interrupt config , */\
+ { 0x91, "fs_pulse_sel"}, /* Audio sample reference , */\
+ { 0xb0, "bypass_ocp"}, /* Bypass OCP , */\
+ { 0xc0, "test_ocp"}, /* OCP testing control , */\
+ { 0x101, "vamp_sel"}, /* Amplifier input selection , */\
+ { 0x120, "src_set_configured"}, /* I2C configured , */\
+ { 0x130, "execute_cold_start"}, /* Execute cold start , */\
+ { 0x140, "enbl_osc1m_auto_off"}, /* Internal osc off at PWDN , */\
+ { 0x150, "man_enbl_brown_out"}, /* Reaction on BOD , */\
+ { 0x160, "enbl_bod"}, /* BOD Enable , */\
+ { 0x170, "enbl_bod_hyst"}, /* BOD Hysteresis , */\
+ { 0x181, "bod_delay"}, /* BOD filter , */\
+ { 0x1a1, "bod_lvlsel"}, /* BOD threshold , */\
+ { 0x1d0, "disable_mute_time_out"}, /* Time out SB mute sequence , */\
+ { 0x1e0, "pwm_sel_rcv_ns"}, /* Noise shaper selection , */\
+ { 0x1f0, "man_enbl_watchdog"}, /* Watchdog manager reaction , */\
+ { 0x203, "audio_fs"}, /* Sample rate (fs) , */\
+ { 0x240, "input_level"}, /* TDM output attenuation , */\
+ { 0x255, "cs_frac_delay"}, /* V/I Fractional delay , */\
+ { 0x2b0, "bypass_hvbat_filter"}, /* Bypass HVBAT filter , */\
+ { 0x2c0, "ctrl_rcvldop_bypass"}, /* Receiver LDO bypass , */\
+ { 0x30f, "device_rev"}, /* Revision info , */\
+ { 0x401, "pll_clkin_sel"}, /* PLL external ref clock , */\
+ { 0x420, "pll_clkin_sel_osc"}, /* PLL internal ref clock , */\
+ { 0x500, "enbl_spkr_ss_left"}, /* Enable left channel , */\
+ { 0x510, "enbl_spkr_ss_right"}, /* Enable right channel , */\
+ { 0x520, "enbl_volsense_left"}, /* Voltage sense left , */\
+ { 0x530, "enbl_volsense_right"}, /* Voltage sense right , */\
+ { 0x540, "enbl_cursense_left"}, /* Current sense left , */\
+ { 0x550, "enbl_cursense_right"}, /* Current sense right , */\
+ { 0x560, "enbl_pdm_ss"}, /* Sub-system PDM , */\
+ { 0xd00, "side_tone_gain_sel"}, /* PDM side tone gain selector , */\
+ { 0xd18, "side_tone_gain"}, /* Side tone gain , */\
+ { 0xda0, "mute_side_tone"}, /* Side tone soft mute , */\
+ { 0xe06, "ctrl_digtoana"}, /* Register for the host SW to record the current active vstep, */\
+ { 0xe70, "enbl_cmfb_left"}, /* Current sense common mode feedback control for left channel, */\
+ { 0xf0f, "hidden_code"}, /* 5A6Bh, 23147d to access registers (default for engineering), */\
+ { 0x1000, "flag_por"}, /* POR , */\
+ { 0x1010, "flag_pll_lock"}, /* PLL lock , */\
+ { 0x1020, "flag_otpok"}, /* OTP alarm , */\
+ { 0x1030, "flag_ovpok"}, /* OVP alarm , */\
+ { 0x1040, "flag_uvpok"}, /* UVP alarm , */\
+ { 0x1050, "flag_clocks_stable"}, /* Clocks stable , */\
+ { 0x1060, "flag_mtp_busy"}, /* MTP busy , */\
+ { 0x1070, "flag_lost_clk"}, /* Lost clock , */\
+ { 0x1080, "flag_cf_speakererror"}, /* Speaker error , */\
+ { 0x1090, "flag_cold_started"}, /* Cold Start , */\
+ { 0x10a0, "flag_engage"}, /* Amplifier engage , */\
+ { 0x10b0, "flag_watchdog_reset"}, /* Watchdog , */\
+ { 0x10c0, "flag_enbl_amp"}, /* Amplifier enable , */\
+ { 0x10d0, "flag_enbl_ref"}, /* References enable , */\
+ { 0x10e0, "flag_adc10_ready"}, /* Control ADC , */\
+ { 0x10f0, "flag_bod_vddd_nok"}, /* BOD , */\
+ { 0x1100, "flag_bst_bstcur"}, /* DCDC current limiting , */\
+ { 0x1110, "flag_bst_hiz"}, /* DCDC active , */\
+ { 0x1120, "flag_bst_ocpok"}, /* DCDC OCP nmos , */\
+ { 0x1130, "flag_bst_peakcur"}, /* Indicates current is max in DC-to-DC converter , */\
+ { 0x1140, "flag_bst_voutcomp"}, /* DCDC level 1x , */\
+ { 0x1150, "flag_bst_voutcomp86"}, /* DCDC level 1.14x , */\
+ { 0x1160, "flag_bst_voutcomp93"}, /* DCDC level 1.07x , */\
+ { 0x1170, "flag_soft_mute_busy"}, /* side tone (un)mute busy , */\
+ { 0x1180, "flag_soft_mute_state"}, /* side tone mute state , */\
+ { 0x1190, "flag_tdm_lut_error"}, /* TDM LUT error , */\
+ { 0x11a2, "flag_tdm_status"}, /* TDM status bits , */\
+ { 0x11d0, "flag_tdm_error"}, /* TDM error , */\
+ { 0x11e0, "flag_haptic_busy"}, /* Status haptic driver , */\
+ { 0x1200, "flag_ocpokap_left"}, /* OCPOK pmos A left , */\
+ { 0x1210, "flag_ocpokan_left"}, /* OCPOK nmos A left , */\
+ { 0x1220, "flag_ocpokbp_left"}, /* OCPOK pmos B left , */\
+ { 0x1230, "flag_ocpokbn_left"}, /* OCPOK nmos B left , */\
+ { 0x1240, "flag_clipa_high_left"}, /* Clipping A left to Vddp , */\
+ { 0x1250, "flag_clipa_low_left"}, /* Clipping A left to gnd , */\
+ { 0x1260, "flag_clipb_high_left"}, /* Clipping B left to Vddp , */\
+ { 0x1270, "flag_clipb_low_left"}, /* Clipping B left to gnd , */\
+ { 0x1280, "flag_ocpokap_rcv"}, /* OCPOK pmos A RCV , */\
+ { 0x1290, "flag_ocpokan_rcv"}, /* OCPOK nmos A RCV , */\
+ { 0x12a0, "flag_ocpokbp_rcv"}, /* OCPOK pmos B RCV , */\
+ { 0x12b0, "flag_ocpokbn_rcv"}, /* OCPOK nmos B RCV , */\
+ { 0x12c0, "flag_rcvldop_ready"}, /* RCV LDO regulates , */\
+ { 0x12d0, "flag_rcvldop_bypassready"}, /* Receiver LDO ready , */\
+ { 0x12e0, "flag_ocp_alarm_left"}, /* OCP left amplifier , */\
+ { 0x12f0, "flag_clip_left"}, /* Amplifier left clipping , */\
+ { 0x1300, "flag_ocpokap_right"}, /* OCPOK pmos A right , */\
+ { 0x1310, "flag_ocpokan_right"}, /* OCPOK nmos A right , */\
+ { 0x1320, "flag_ocpokbp_right"}, /* OCPOK pmos B right , */\
+ { 0x1330, "flag_ocpokbn_right"}, /* OCPOK nmos B right , */\
+ { 0x1340, "flag_clipa_high_right"}, /* Clipping A right to Vddp , */\
+ { 0x1350, "flag_clipa_low_right"}, /* Clipping A right to gnd , */\
+ { 0x1360, "flag_clipb_high_right"}, /* Clipping B left to Vddp , */\
+ { 0x1370, "flag_clipb_low_right"}, /* Clipping B right to gnd , */\
+ { 0x1380, "flag_ocp_alarm_right"}, /* OCP right amplifier , */\
+ { 0x1390, "flag_clip_right"}, /* Amplifier right clipping , */\
+ { 0x13a0, "flag_mic_ocpok"}, /* OCPOK MICVDD , */\
+ { 0x13b0, "flag_man_alarm_state"}, /* Alarm state , */\
+ { 0x13c0, "flag_man_wait_src_settings"}, /* Wait HW I2C settings , */\
+ { 0x13d0, "flag_man_wait_cf_config"}, /* Wait CF config , */\
+ { 0x13e0, "flag_man_start_mute_audio"}, /* Audio mute sequence , */\
+ { 0x13f0, "flag_man_operating_state"}, /* Operating state , */\
+ { 0x1400, "flag_cf_speakererror_left"}, /* Left speaker status , */\
+ { 0x1410, "flag_cf_speakererror_right"}, /* Right speaker status , */\
+ { 0x1420, "flag_clk_out_of_range"}, /* External clock status , */\
+ { 0x1433, "man_state"}, /* Device manager status , */\
+ { 0x1509, "bat_adc"}, /* Battery voltage (V) , */\
+ { 0x1608, "temp_adc"}, /* IC Temperature (C) , */\
+ { 0x2003, "tdm_usecase"}, /* Usecase setting , */\
+ { 0x2040, "tdm_enable"}, /* Enable interface , */\
+ { 0x2050, "tdm_mode"}, /* Slave/master , */\
+ { 0x2060, "tdm_clk_inversion"}, /* Reception data to BCK clock , */\
+ { 0x2073, "tdm_fs_ws_length"}, /* FS length (master mode only) , */\
+ { 0x20b0, "tdm_fs_ws_polarity"}, /* FS polarity , */\
+ { 0x20c3, "tdm_nbck"}, /* N-BCK's in FS , */\
+ { 0x2103, "tdm_nb_of_slots"}, /* N-slots in Frame , */\
+ { 0x2144, "tdm_slot_length"}, /* N-bits in slot , */\
+ { 0x2194, "tdm_bits_remaining"}, /* N-bits remaining , */\
+ { 0x21e0, "tdm_data_delay"}, /* data delay to FS , */\
+ { 0x21f0, "tdm_data_adjustment"}, /* data adjustment , */\
+ { 0x2201, "tdm_audio_sample_compression"}, /* Received audio compression , */\
+ { 0x2224, "tdm_sample_size"}, /* Sample size per slot , */\
+ { 0x2271, "tdm_txdata_format"}, /* Format unused bits , */\
+ { 0x2291, "tdm_txdata_format_unused_slot_sd0"}, /* Format unused slots GAINIO , */\
+ { 0x22b1, "tdm_txdata_format_unused_slot_sd1"}, /* Format unused slots DIO1 , */\
+ { 0x22d1, "tdm_txdata_format_unused_slot_sd2"}, /* Format unused slots DIO2 , */\
+ { 0x2300, "tdm_sink0_enable"}, /* Control gainin (not used in DSP) , */\
+ { 0x2310, "tdm_sink1_enable"}, /* Control audio left , */\
+ { 0x2320, "tdm_sink2_enable"}, /* Control audio right , */\
+ { 0x2330, "tdm_source0_enable"}, /* Control gainout (not used in DSP) , */\
+ { 0x2340, "tdm_source1_enable"}, /* Control voltage sense right , */\
+ { 0x2350, "tdm_source2_enable"}, /* Control current sense right , */\
+ { 0x2360, "tdm_source3_enable"}, /* Voltage sense left control , */\
+ { 0x2370, "tdm_source4_enable"}, /* Current sense left control , */\
+ { 0x2380, "tdm_source5_enable"}, /* DSP out right control , */\
+ { 0x2390, "tdm_source6_enable"}, /* DSP out left control , */\
+ { 0x23a0, "tdm_source7_enable"}, /* AEC ref left control , */\
+ { 0x23b0, "tdm_source8_enable"}, /* AEC ref right control , */\
+ { 0x23c0, "tdm_source9_enable"}, /* PDM 1 control , */\
+ { 0x23d0, "tdm_source10_enable"}, /* PDM 2 control , */\
+ { 0x2401, "tdm_sink0_io"}, /* IO gainin (not used in DSP) , */\
+ { 0x2421, "tdm_sink1_io"}, /* IO audio left , */\
+ { 0x2441, "tdm_sink2_io"}, /* IO audio right , */\
+ { 0x2461, "tdm_source0_io"}, /* IO gainout (not used in DSP) , */\
+ { 0x2481, "tdm_source1_io"}, /* IO voltage sense right , */\
+ { 0x24a1, "tdm_source2_io"}, /* IO current sense right , */\
+ { 0x24c1, "tdm_source3_io"}, /* IO voltage sense left , */\
+ { 0x24e1, "tdm_source4_io"}, /* IO current sense left , */\
+ { 0x2501, "tdm_source5_io"}, /* IO dspout right , */\
+ { 0x2521, "tdm_source6_io"}, /* IO dspout left , */\
+ { 0x2541, "tdm_source7_io"}, /* IO AEC ref left control , */\
+ { 0x2561, "tdm_source8_io"}, /* IO AEC ref right control , */\
+ { 0x2581, "tdm_source9_io"}, /* IO pdm1 , */\
+ { 0x25a1, "tdm_source10_io"}, /* IO pdm2 , */\
+ { 0x2603, "tdm_sink0_slot"}, /* Position gainin (not used in DSP) , */\
+ { 0x2643, "tdm_sink1_slot"}, /* Position audio left , */\
+ { 0x2683, "tdm_sink2_slot"}, /* Position audio right , */\
+ { 0x26c3, "tdm_source0_slot"}, /* Position gainout (not used in DSP) , */\
+ { 0x2703, "tdm_source1_slot"}, /* Position voltage sense right , */\
+ { 0x2743, "tdm_source2_slot"}, /* Position current sense right , */\
+ { 0x2783, "tdm_source3_slot"}, /* Position voltage sense left , */\
+ { 0x27c3, "tdm_source4_slot"}, /* Position current sense left , */\
+ { 0x2803, "tdm_source5_slot"}, /* Position dspout right , */\
+ { 0x2843, "tdm_source6_slot"}, /* Position dspout left , */\
+ { 0x2883, "tdm_source7_slot"}, /* Position AEC ref left control , */\
+ { 0x28c3, "tdm_source8_slot"}, /* Position AEC ref right control , */\
+ { 0x2903, "tdm_source9_slot"}, /* Position pdm1 , */\
+ { 0x2943, "tdm_source10_slot"}, /* Position pdm2 , */\
+ { 0x3100, "pdm_mode"}, /* PDM control , */\
+ { 0x3111, "pdm_side_tone_sel"}, /* Side tone input , */\
+ { 0x3130, "pdm_left_sel"}, /* PDM data selection for left channel during PDM direct mode, */\
+ { 0x3140, "pdm_right_sel"}, /* PDM data selection for right channel during PDM direct mode, */\
+ { 0x3150, "enbl_micvdd"}, /* Enable MICVDD , */\
+ { 0x3160, "bypass_micvdd_ocp"}, /* Bypass control for the MICVDD OCP flag processing , */\
+ { 0x3201, "pdm_nbck"}, /* PDM BCK/Fs ratio , */\
+ { 0x3223, "pdm_gain"}, /* PDM gain , */\
+ { 0x3263, "sel_pdm_out_data"}, /* PDM output selection - RE/FE data combination , */\
+ { 0x32a0, "sel_cf_haptic_data"}, /* Select the source for haptic data output (not for customer), */\
+ { 0x3307, "haptic_duration"}, /* Duration (ms) , */\
+ { 0x3387, "haptic_data"}, /* DC value (FFS) , */\
+ { 0x3403, "gpio_datain"}, /* Receiving value , */\
+ { 0x3500, "gpio_ctrl"}, /* GPIO master control over GPIO1/2 ports (not for customer), */\
+ { 0x3513, "gpio_dir"}, /* Configuration , */\
+ { 0x3553, "gpio_dataout"}, /* Transmitting value , */\
+ { 0x4000, "int_out_flag_por"}, /* Status POR , */\
+ { 0x4010, "int_out_flag_pll_lock"}, /* Status PLL lock , */\
+ { 0x4020, "int_out_flag_otpok"}, /* Status OTP alarm , */\
+ { 0x4030, "int_out_flag_ovpok"}, /* Status OVP alarm , */\
+ { 0x4040, "int_out_flag_uvpok"}, /* Status UVP alarm , */\
+ { 0x4050, "int_out_flag_clocks_stable"}, /* Status clocks stable , */\
+ { 0x4060, "int_out_flag_mtp_busy"}, /* Status MTP busy , */\
+ { 0x4070, "int_out_flag_lost_clk"}, /* Status lost clock , */\
+ { 0x4080, "int_out_flag_cf_speakererror"}, /* Status speaker error , */\
+ { 0x4090, "int_out_flag_cold_started"}, /* Status cold start , */\
+ { 0x40a0, "int_out_flag_engage"}, /* Status amplifier engage , */\
+ { 0x40b0, "int_out_flag_watchdog_reset"}, /* Status watchdog , */\
+ { 0x40c0, "int_out_flag_enbl_amp"}, /* Status amplifier enable , */\
+ { 0x40d0, "int_out_flag_enbl_ref"}, /* Status Ref enable , */\
+ { 0x40e0, "int_out_flag_adc10_ready"}, /* Status Control ADC , */\
+ { 0x40f0, "int_out_flag_bod_vddd_nok"}, /* Status BOD , */\
+ { 0x4100, "int_out_flag_bst_bstcur"}, /* Status DCDC current limiting , */\
+ { 0x4110, "int_out_flag_bst_hiz"}, /* Status DCDC active , */\
+ { 0x4120, "int_out_flag_bst_ocpok"}, /* Status DCDC OCP , */\
+ { 0x4130, "int_out_flag_bst_peakcur"}, /* Status bst peakcur , */\
+ { 0x4140, "int_out_flag_bst_voutcomp"}, /* Status DCDC level 1x , */\
+ { 0x4150, "int_out_flag_bst_voutcomp86"}, /* Status DCDC level 1.14x , */\
+ { 0x4160, "int_out_flag_bst_voutcomp93"}, /* Status DCDC level 1.07x , */\
+ { 0x4170, "int_out_flag_rcvldop_ready"}, /* Status rcvldop ready , */\
+ { 0x4180, "int_out_flag_ocp_alarm_left"}, /* Status ocp alarm left , */\
+ { 0x4190, "int_out_flag_ocp_alarm_right"}, /* Status ocp alarm right , */\
+ { 0x41a0, "int_out_flag_man_wait_src_settings"}, /* Status Waits HW I2C settings , */\
+ { 0x41b0, "int_out_flag_man_wait_cf_config"}, /* Status waits CF config , */\
+ { 0x41c0, "int_out_flag_man_start_mute_audio"}, /* Status Audio mute sequence , */\
+ { 0x41d0, "int_out_flag_cfma_err"}, /* Status cfma error , */\
+ { 0x41e0, "int_out_flag_cfma_ack"}, /* Status cfma ack , */\
+ { 0x41f0, "int_out_flag_clk_out_of_range"}, /* Status flag_clk_out_of_range , */\
+ { 0x4200, "int_out_flag_tdm_error"}, /* Status tdm error , */\
+ { 0x4210, "int_out_flag_clip_left"}, /* Status clip left , */\
+ { 0x4220, "int_out_flag_clip_right"}, /* Status clip right , */\
+ { 0x4230, "int_out_flag_mic_ocpok"}, /* Status mic ocpok , */\
+ { 0x4400, "int_in_flag_por"}, /* Clear POR , */\
+ { 0x4410, "int_in_flag_pll_lock"}, /* Clear PLL lock , */\
+ { 0x4420, "int_in_flag_otpok"}, /* Clear OTP alarm , */\
+ { 0x4430, "int_in_flag_ovpok"}, /* Clear OVP alarm , */\
+ { 0x4440, "int_in_flag_uvpok"}, /* Clear UVP alarm , */\
+ { 0x4450, "int_in_flag_clocks_stable"}, /* Clear clocks stable , */\
+ { 0x4460, "int_in_flag_mtp_busy"}, /* Clear mtp busy , */\
+ { 0x4470, "int_in_flag_lost_clk"}, /* Clear lost clk , */\
+ { 0x4480, "int_in_flag_cf_speakererror"}, /* Clear speaker error , */\
+ { 0x4490, "int_in_flag_cold_started"}, /* Clear cold started , */\
+ { 0x44a0, "int_in_flag_engage"}, /* Clear amplifier engage , */\
+ { 0x44b0, "int_in_flag_watchdog_reset"}, /* Clear watchdog , */\
+ { 0x44c0, "int_in_flag_enbl_amp"}, /* Clear enbl amp , */\
+ { 0x44d0, "int_in_flag_enbl_ref"}, /* Clear ref enable , */\
+ { 0x44e0, "int_in_flag_adc10_ready"}, /* Clear control ADC , */\
+ { 0x44f0, "int_in_flag_bod_vddd_nok"}, /* Clear BOD , */\
+ { 0x4500, "int_in_flag_bst_bstcur"}, /* Clear DCDC current limiting , */\
+ { 0x4510, "int_in_flag_bst_hiz"}, /* Clear DCDC active , */\
+ { 0x4520, "int_in_flag_bst_ocpok"}, /* Clear DCDC OCP , */\
+ { 0x4530, "int_in_flag_bst_peakcur"}, /* Clear bst peakcur , */\
+ { 0x4540, "int_in_flag_bst_voutcomp"}, /* Clear DCDC level 1x , */\
+ { 0x4550, "int_in_flag_bst_voutcomp86"}, /* Clear DCDC level 1.14x , */\
+ { 0x4560, "int_in_flag_bst_voutcomp93"}, /* Clear DCDC level 1.07x , */\
+ { 0x4570, "int_in_flag_rcvldop_ready"}, /* Clear rcvldop ready , */\
+ { 0x4580, "int_in_flag_ocp_alarm_left"}, /* Clear ocp alarm left , */\
+ { 0x4590, "int_in_flag_ocp_alarm_right"}, /* Clear ocp alarm right , */\
+ { 0x45a0, "int_in_flag_man_wait_src_settings"}, /* Clear wait HW I2C settings , */\
+ { 0x45b0, "int_in_flag_man_wait_cf_config"}, /* Clear wait cf config , */\
+ { 0x45c0, "int_in_flag_man_start_mute_audio"}, /* Clear audio mute sequence , */\
+ { 0x45d0, "int_in_flag_cfma_err"}, /* Clear cfma err , */\
+ { 0x45e0, "int_in_flag_cfma_ack"}, /* Clear cfma ack , */\
+ { 0x45f0, "int_in_flag_clk_out_of_range"}, /* Clear flag_clk_out_of_range , */\
+ { 0x4600, "int_in_flag_tdm_error"}, /* Clear tdm error , */\
+ { 0x4610, "int_in_flag_clip_left"}, /* Clear clip left , */\
+ { 0x4620, "int_in_flag_clip_right"}, /* Clear clip right , */\
+ { 0x4630, "int_in_flag_mic_ocpok"}, /* Clear mic ocpok , */\
+ { 0x4800, "int_enable_flag_por"}, /* Enable por , */\
+ { 0x4810, "int_enable_flag_pll_lock"}, /* Enable pll lock , */\
+ { 0x4820, "int_enable_flag_otpok"}, /* Enable OTP alarm , */\
+ { 0x4830, "int_enable_flag_ovpok"}, /* Enable OVP alarm , */\
+ { 0x4840, "int_enable_flag_uvpok"}, /* Enable UVP alarm , */\
+ { 0x4850, "int_enable_flag_clocks_stable"}, /* Enable clocks stable , */\
+ { 0x4860, "int_enable_flag_mtp_busy"}, /* Enable mtp busy , */\
+ { 0x4870, "int_enable_flag_lost_clk"}, /* Enable lost clk , */\
+ { 0x4880, "int_enable_flag_cf_speakererror"}, /* Enable speaker error , */\
+ { 0x4890, "int_enable_flag_cold_started"}, /* Enable cold started , */\
+ { 0x48a0, "int_enable_flag_engage"}, /* Enable amplifier engage , */\
+ { 0x48b0, "int_enable_flag_watchdog_reset"}, /* Enable watchdog , */\
+ { 0x48c0, "int_enable_flag_enbl_amp"}, /* Enable enbl amp , */\
+ { 0x48d0, "int_enable_flag_enbl_ref"}, /* Enable ref enable , */\
+ { 0x48e0, "int_enable_flag_adc10_ready"}, /* Enable Control ADC , */\
+ { 0x48f0, "int_enable_flag_bod_vddd_nok"}, /* Enable BOD , */\
+ { 0x4900, "int_enable_flag_bst_bstcur"}, /* Enable DCDC current limiting , */\
+ { 0x4910, "int_enable_flag_bst_hiz"}, /* Enable DCDC active , */\
+ { 0x4920, "int_enable_flag_bst_ocpok"}, /* Enable DCDC OCP , */\
+ { 0x4930, "int_enable_flag_bst_peakcur"}, /* Enable bst peakcur , */\
+ { 0x4940, "int_enable_flag_bst_voutcomp"}, /* Enable DCDC level 1x , */\
+ { 0x4950, "int_enable_flag_bst_voutcomp86"}, /* Enable DCDC level 1.14x , */\
+ { 0x4960, "int_enable_flag_bst_voutcomp93"}, /* Enable DCDC level 1.07x , */\
+ { 0x4970, "int_enable_flag_rcvldop_ready"}, /* Enable rcvldop ready , */\
+ { 0x4980, "int_enable_flag_ocp_alarm_left"}, /* Enable ocp alarm left , */\
+ { 0x4990, "int_enable_flag_ocp_alarm_right"}, /* Enable ocp alarm right , */\
+ { 0x49a0, "int_enable_flag_man_wait_src_settings"}, /* Enable waits HW I2C settings , */\
+ { 0x49b0, "int_enable_flag_man_wait_cf_config"}, /* Enable man wait cf config , */\
+ { 0x49c0, "int_enable_flag_man_start_mute_audio"}, /* Enable man Audio mute sequence , */\
+ { 0x49d0, "int_enable_flag_cfma_err"}, /* Enable cfma err , */\
+ { 0x49e0, "int_enable_flag_cfma_ack"}, /* Enable cfma ack , */\
+ { 0x49f0, "int_enable_flag_clk_out_of_range"}, /* Enable flag_clk_out_of_range , */\
+ { 0x4a00, "int_enable_flag_tdm_error"}, /* Enable tdm error , */\
+ { 0x4a10, "int_enable_flag_clip_left"}, /* Enable clip left , */\
+ { 0x4a20, "int_enable_flag_clip_right"}, /* Enable clip right , */\
+ { 0x4a30, "int_enable_flag_mic_ocpok"}, /* Enable mic ocpok , */\
+ { 0x4c00, "int_polarity_flag_por"}, /* Polarity por , */\
+ { 0x4c10, "int_polarity_flag_pll_lock"}, /* Polarity pll lock , */\
+ { 0x4c20, "int_polarity_flag_otpok"}, /* Polarity OTP alarm , */\
+ { 0x4c30, "int_polarity_flag_ovpok"}, /* Polarity OVP alarm , */\
+ { 0x4c40, "int_polarity_flag_uvpok"}, /* Polarity UVP alarm , */\
+ { 0x4c50, "int_polarity_flag_clocks_stable"}, /* Polarity clocks stable , */\
+ { 0x4c60, "int_polarity_flag_mtp_busy"}, /* Polarity mtp busy , */\
+ { 0x4c70, "int_polarity_flag_lost_clk"}, /* Polarity lost clk , */\
+ { 0x4c80, "int_polarity_flag_cf_speakererror"}, /* Polarity speaker error , */\
+ { 0x4c90, "int_polarity_flag_cold_started"}, /* Polarity cold started , */\
+ { 0x4ca0, "int_polarity_flag_engage"}, /* Polarity amplifier engage , */\
+ { 0x4cb0, "int_polarity_flag_watchdog_reset"}, /* Polarity watchdog , */\
+ { 0x4cc0, "int_polarity_flag_enbl_amp"}, /* Polarity enbl amp , */\
+ { 0x4cd0, "int_polarity_flag_enbl_ref"}, /* Polarity ref enable , */\
+ { 0x4ce0, "int_polarity_flag_adc10_ready"}, /* Polarity Control ADC , */\
+ { 0x4cf0, "int_polarity_flag_bod_vddd_nok"}, /* Polarity BOD , */\
+ { 0x4d00, "int_polarity_flag_bst_bstcur"}, /* Polarity DCDC current limiting , */\
+ { 0x4d10, "int_polarity_flag_bst_hiz"}, /* Polarity DCDC active , */\
+ { 0x4d20, "int_polarity_flag_bst_ocpok"}, /* Polarity DCDC OCP , */\
+ { 0x4d30, "int_polarity_flag_bst_peakcur"}, /* Polarity bst peakcur , */\
+ { 0x4d40, "int_polarity_flag_bst_voutcomp"}, /* Polarity DCDC level 1x , */\
+ { 0x4d50, "int_polarity_flag_bst_voutcomp86"}, /* Polarity DCDC level 1.14x , */\
+ { 0x4d60, "int_polarity_flag_bst_voutcomp93"}, /* Polarity DCDC level 1.07x , */\
+ { 0x4d70, "int_polarity_flag_rcvldop_ready"}, /* Polarity rcvldop ready , */\
+ { 0x4d80, "int_polarity_flag_ocp_alarm_left"}, /* Polarity ocp alarm left , */\
+ { 0x4d90, "int_polarity_flag_ocp_alarm_right"}, /* Polarity ocp alarm right , */\
+ { 0x4da0, "int_polarity_flag_man_wait_src_settings"}, /* Polarity waits HW I2C settings , */\
+ { 0x4db0, "int_polarity_flag_man_wait_cf_config"}, /* Polarity man wait cf config , */\
+ { 0x4dc0, "int_polarity_flag_man_start_mute_audio"}, /* Polarity man audio mute sequence , */\
+ { 0x4dd0, "int_polarity_flag_cfma_err"}, /* Polarity cfma err , */\
+ { 0x4de0, "int_polarity_flag_cfma_ack"}, /* Polarity cfma ack , */\
+ { 0x4df0, "int_polarity_flag_clk_out_of_range"}, /* Polarity flag_clk_out_of_range , */\
+ { 0x4e00, "int_polarity_flag_tdm_error"}, /* Polarity tdm error , */\
+ { 0x4e10, "int_polarity_flag_clip_left"}, /* Polarity clip left , */\
+ { 0x4e20, "int_polarity_flag_clip_right"}, /* Polarity clip right , */\
+ { 0x4e30, "int_polarity_flag_mic_ocpok"}, /* Polarity mic ocpok , */\
+ { 0x5001, "vbat_prot_attack_time"}, /* Battery protection attack Time , */\
+ { 0x5023, "vbat_prot_thlevel"}, /* Battery protection threshold voltage level , */\
+ { 0x5061, "vbat_prot_max_reduct"}, /* Battery protection maximum reduction , */\
+ { 0x5082, "vbat_prot_release_time"}, /* Battery protection release time , */\
+ { 0x50b1, "vbat_prot_hysterese"}, /* Battery protection hysteresis , */\
+ { 0x50d0, "rst_min_vbat"}, /* Reset clipper - Auto clear , */\
+ { 0x50e0, "sel_vbat"}, /* Battery voltage read out , */\
+ { 0x50f0, "bypass_clipper"}, /* Bypass HW clipper , */\
+ { 0x5100, "batsense_steepness"}, /* Vbat prot steepness , */\
+ { 0x5110, "soft_mute"}, /* Soft mute HW , */\
+ { 0x5120, "cf_mute_left"}, /* Soft mute FW left , */\
+ { 0x5130, "cf_mute_right"}, /* Soft mute FW right , */\
+ { 0x5140, "bypass_hp_left"}, /* Bypass HPF left , */\
+ { 0x5150, "bypass_hp_right"}, /* Bypass HPF right , */\
+ { 0x5160, "enbl_dpsa_left"}, /* Enable DPSA left , */\
+ { 0x5170, "enbl_dpsa_right"}, /* Enable DPSA right , */\
+ { 0x5187, "cf_volume"}, /* FW volume control for primary audio channel , */\
+ { 0x5200, "ctrl_rcv"}, /* Selection receiver , */\
+ { 0x5210, "ctrl_rcv_fb_100k"}, /* Selection of feedback resistor for receiver mode (not for customer), */\
+ { 0x5222, "ctrl_cc"}, /* Clip control setting , */\
+ { 0x5257, "gain"}, /* Amplifier gain , */\
+ { 0x52d0, "ctrl_slopectrl"}, /* Enables slope control , */\
+ { 0x52e1, "ctrl_slope"}, /* Set slope , */\
+ { 0x5301, "dpsa_level"}, /* DPSA threshold levels , */\
+ { 0x5321, "dpsa_release"}, /* DPSA Release time , */\
+ { 0x5340, "clipfast"}, /* Clock selection for HW clipper for battery protection, */\
+ { 0x5350, "bypass_lp"}, /* Bypass the low power filter inside temperature sensor, */\
+ { 0x5360, "enbl_low_latency"}, /* CF low latency outputs for add module , */\
+ { 0x5400, "first_order_mode"}, /* Overrule to 1st order mode of control stage when clipping, */\
+ { 0x5410, "bypass_ctrlloop"}, /* Switch amplifier into open loop configuration , */\
+ { 0x5420, "fb_hz"}, /* Feedback resistor set to high ohmic , */\
+ { 0x5430, "icomp_engage"}, /* Engage of icomp , */\
+ { 0x5440, "ctrl_kickback"}, /* Prevent double pulses of output stage , */\
+ { 0x5450, "icomp_engage_overrule"}, /* To overrule the functional icomp_engage signal during validation, */\
+ { 0x5503, "ctrl_dem"}, /* Enable DEM icomp and DEM one bit dac , */\
+ { 0x5543, "ctrl_dem_mismatch"}, /* Enable DEM icomp mismatch for testing , */\
+ { 0x5581, "dpsa_drive"}, /* Control of the number of power stage sections, total of 4 sections. Each section is 1/4 of the total power stages., */\
+ { 0x560a, "enbl_amp_left"}, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually - Left channel, */\
+ { 0x56b0, "enbl_engage_left"}, /* Enables/engage power stage and control loop - left channel, */\
+ { 0x570a, "enbl_amp_right"}, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually - Right channel, */\
+ { 0x57b0, "enbl_engage_right"}, /* Enables/engage power stage and control loop - right channel, */\
+ { 0x5800, "hard_mute_left"}, /* Hard mute - PWM module left , */\
+ { 0x5810, "hard_mute_right"}, /* Hard mute - PWM module right , */\
+ { 0x5820, "pwm_shape"}, /* PWM shape , */\
+ { 0x5830, "pwm_bitlength"}, /* PWM bit length in noise shaper , */\
+ { 0x5844, "pwm_delay"}, /* PWM delay bits to set the delay, clockd is 1/(k*2048*fs), */\
+ { 0x5890, "reclock_pwm"}, /* Reclock the pwm signal inside analog , */\
+ { 0x58a0, "reclock_voltsense"}, /* Reclock the voltage sense pwm signal , */\
+ { 0x58b0, "enbl_pwm_phase_shift_left"}, /* Control for pwm phase shift, inverted function - left channel, */\
+ { 0x58c0, "enbl_pwm_phase_shift_right"}, /* Control for pwm phase shift - right channel , */\
+ { 0x5900, "ctrl_rcvldop_pulldown"}, /* Pulldown of LDO (2.7V) , */\
+ { 0x5910, "ctrl_rcvldop_test_comp"}, /* Enable testing of LDO comparator , */\
+ { 0x5920, "ctrl_rcvldop_test_loadedldo"}, /* Load connected to rcvldo , */\
+ { 0x5930, "enbl_rcvldop"}, /* Enables the LDO (2.7) , */\
+ { 0x5a07, "cf_volume_sec"}, /* FW volume control for secondary audio channel , */\
+ { 0x5a87, "sw_profile"}, /* Software profile data , */\
+ { 0x7002, "boost_volt"}, /* Boost voltage , */\
+ { 0x7033, "boost_cur"}, /* Max coil current , */\
+ { 0x7071, "bst_coil_value"}, /* Coil Value , */\
+ { 0x7090, "boost_intel"}, /* Adaptive boost mode , */\
+ { 0x70a0, "boost_speed"}, /* Soft ramp up/down , */\
+ { 0x70b2, "dcdc_synchronisation"}, /* DCDC synchronization off + 7 positions , */\
+ { 0x70e0, "dcdcoff_mode"}, /* DCDC on/off , */\
+ { 0x7104, "bst_drive"}, /* Binary coded drive setting for boost converter power stage, */\
+ { 0x7151, "bst_scalecur"}, /* For testing direct control scale current , */\
+ { 0x7174, "bst_slopecur"}, /* For testing direct control slope current , */\
+ { 0x71c1, "bst_slope"}, /* Boost slope speed , */\
+ { 0x71e0, "bst_bypass_bstcur"}, /* Bypass control for boost current settings , */\
+ { 0x71f0, "bst_bypass_bstfoldback"}, /* Bypass control for boost foldback , */\
+ { 0x7200, "enbl_bst_engage"}, /* Enable power stage dcdc controller , */\
+ { 0x7210, "enbl_bst_hizcom"}, /* Enable hiz comparator , */\
+ { 0x7220, "enbl_bst_peak2avg"}, /* Enable boost peak2avg functionality , */\
+ { 0x7230, "enbl_bst_peakcur"}, /* Enable peak current , */\
+ { 0x7240, "enbl_bst_power"}, /* Enable line of the powerstage , */\
+ { 0x7250, "enbl_bst_slopecur"}, /* Enable bit of max-current dac , */\
+ { 0x7260, "enbl_bst_voutcomp"}, /* Enable vout comparators , */\
+ { 0x7270, "enbl_bst_voutcomp86"}, /* Enable vout-86 comparators , */\
+ { 0x7280, "enbl_bst_voutcomp93"}, /* Enable vout-93 comparators , */\
+ { 0x7290, "enbl_bst_windac"}, /* Enable window dac , */\
+ { 0x72a5, "bst_windac"}, /* for testing direct control windac , */\
+ { 0x7300, "boost_alg"}, /* Control for boost adaptive loop gain , */\
+ { 0x7311, "boost_loopgain"}, /* DCDC boost loopgain setting , */\
+ { 0x7332, "bst_freq"}, /* DCDC bost frequency control , */\
+ { 0x8001, "sel_clk_cs"}, /* Current sense clock duty cycle control , */\
+ { 0x8021, "micadc_speed"}, /* Current sense clock for MiCADC selection - 32/44.1/48 KHz Fs band only, */\
+ { 0x8040, "cs_dc_offset"}, /* Current sense decimator offset control , */\
+ { 0x8050, "cs_gain_control"}, /* Current sense gain control , */\
+ { 0x8060, "cs_bypass_gc"}, /* Bypasses the CS gain correction , */\
+ { 0x8087, "cs_gain"}, /* Current sense gain , */\
+ { 0x8110, "invertpwm_left"}, /* Current sense common mode feedback pwm invert control for left channel, */\
+ { 0x8122, "cmfb_gain_left"}, /* Current sense common mode feedback control gain for left channel, */\
+ { 0x8154, "cmfb_offset_left"}, /* Current sense common mode feedback control offset for left channel, */\
+ { 0x8200, "enbl_cmfb_right"}, /* Current sense common mode feedback control for right channel, */\
+ { 0x8210, "invertpwm_right"}, /* Current sense common mode feedback pwm invert control for right channel, */\
+ { 0x8222, "cmfb_gain_right"}, /* Current sense common mode feedback control gain for right channel, */\
+ { 0x8254, "cmfb_offset_right"}, /* Current sense common mode feedback control offset for right channel, */\
+ { 0x8305, "cs_ktemp"}, /* Current sense temperature compensation trimming (1 - VALUE*TEMP)*signal, */\
+ { 0x8400, "cs_adc_bsoinv"}, /* Bitstream inversion for current sense ADC , */\
+ { 0x8421, "cs_adc_hifreq"}, /* Frequency mode current sense ADC , */\
+ { 0x8440, "cs_adc_nortz"}, /* Return to zero for current sense ADC , */\
+ { 0x8453, "cs_adc_offset"}, /* Micadc ADC offset setting , */\
+ { 0x8490, "cs_adc_slowdel"}, /* Select delay for current sense ADC (internal decision circuitry), */\
+ { 0x84a4, "cs_adc_gain"}, /* Gain setting for current sense ADC (two's complement), */\
+ { 0x8500, "cs_resonator_enable"}, /* Enable for resonator to improve SRN , */\
+ { 0x8510, "cs_classd_tran_skip"}, /* Skip current sense connection during a classD amplifier transition, */\
+ { 0x8530, "cs_inn_short"}, /* Short current sense negative to common mode , */\
+ { 0x8540, "cs_inp_short"}, /* Short current sense positive to common mode , */\
+ { 0x8550, "cs_ldo_bypass"}, /* Bypass current sense LDO , */\
+ { 0x8560, "cs_ldo_pulldown"}, /* Pull down current sense LDO, only valid if left_enbl_cs_ldo is high, */\
+ { 0x8574, "cs_ldo_voset"}, /* Current sense LDO voltage level setting (two's complement), */\
+ { 0x8600, "enbl_cs_adc_left"}, /* Enable current sense ADC , */\
+ { 0x8610, "enbl_cs_inn1_left"}, /* Enable connection of current sense negative1 , */\
+ { 0x8630, "enbl_cs_inp1_left"}, /* Enable connection of current sense positive1 , */\
+ { 0x8650, "enbl_cs_ldo_left"}, /* Enable current sense LDO , */\
+ { 0x8660, "enbl_cs_nofloating_n_left"}, /* Connect current sense negative to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */\
+ { 0x8670, "enbl_cs_nofloating_p_left"}, /* Connect current sense positive to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */\
+ { 0x8680, "enbl_cs_vbatldo_left"}, /* Enable of current sense LDO , */\
+ { 0x8700, "enbl_cs_adc_right"}, /* Enable current sense ADC , */\
+ { 0x8710, "enbl_cs_inn1_right"}, /* Enable connection of current sense negative1 , */\
+ { 0x8730, "enbl_cs_inp1_right"}, /* Enable connection of current sense positive1 , */\
+ { 0x8750, "enbl_cs_ldo_right"}, /* Enable current sense LDO , */\
+ { 0x8760, "enbl_cs_nofloating_n_right"}, /* Connect current sense negative to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */\
+ { 0x8770, "enbl_cs_nofloating_p_right"}, /* Connect current sense positive to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */\
+ { 0x8780, "enbl_cs_vbatldo_right"}, /* Enable of current sense LDO , */\
+ { 0x8800, "volsense_pwm_sel"}, /* Voltage sense PWM source selection control , */\
+ { 0x8810, "volsense_dc_offset"}, /* Voltage sense decimator offset control , */\
+ { 0x9000, "cf_rst_dsp"}, /* Reset , */\
+ { 0x9011, "cf_dmem"}, /* Target memory , */\
+ { 0x9030, "cf_aif"}, /* Auto increment , */\
+ { 0x9040, "cf_int"}, /* Interrupt - auto clear , */\
+ { 0x9050, "cf_cgate_off"}, /* Coolflux clock gating disabling control , */\
+ { 0x9080, "cf_req_cmd"}, /* Firmware event request rpc command , */\
+ { 0x9090, "cf_req_reset"}, /* Firmware event request reset restart , */\
+ { 0x90a0, "cf_req_mips"}, /* Firmware event request short on mips , */\
+ { 0x90b0, "cf_req_mute_ready"}, /* Firmware event request mute sequence ready , */\
+ { 0x90c0, "cf_req_volume_ready"}, /* Firmware event request volume ready , */\
+ { 0x90d0, "cf_req_damage"}, /* Firmware event request speaker damage detected , */\
+ { 0x90e0, "cf_req_calibrate_ready"}, /* Firmware event request calibration completed , */\
+ { 0x90f0, "cf_req_reserved"}, /* Firmware event request reserved , */\
+ { 0x910f, "cf_madd"}, /* Memory address , */\
+ { 0x920f, "cf_mema"}, /* Activate memory access , */\
+ { 0x9307, "cf_err"}, /* Error flags , */\
+ { 0x9387, "cf_ack"}, /* Acknowledge of requests , */\
+ { 0x9380, "cf_ack_cmd"}, /* Firmware event acknowledge rpc command , */\
+ { 0x9390, "cf_ack_reset"}, /* Firmware event acknowledge reset restart , */\
+ { 0x93a0, "cf_ack_mips"}, /* Firmware event acknowledge short on mips , */\
+ { 0x93b0, "cf_ack_mute_ready"}, /* Firmware event acknowledge mute sequence ready , */\
+ { 0x93c0, "cf_ack_volume_ready"}, /* Firmware event acknowledge volume ready , */\
+ { 0x93d0, "cf_ack_damage"}, /* Firmware event acknowledge speaker damage detected, */\
+ { 0x93e0, "cf_ack_calibrate_ready"}, /* Firmware event acknowledge calibration completed , */\
+ { 0x93f0, "cf_ack_reserved"}, /* Firmware event acknowledge reserved , */\
+ { 0x980f, "ivt_addr0_msb"}, /* Coolflux interrupt vector table address0 MSB , */\
+ { 0x990f, "ivt_addr0_lsb"}, /* Coolflux interrupt vector table address0 LSB , */\
+ { 0x9a0f, "ivt_addr1_msb"}, /* Coolflux interrupt vector table address1 MSB , */\
+ { 0x9b0f, "ivt_addr1_lsb"}, /* Coolflux interrupt vector table address1 LSB , */\
+ { 0x9c0f, "ivt_addr2_msb"}, /* Coolflux interrupt vector table address2 MSB , */\
+ { 0x9d0f, "ivt_addr2_lsb"}, /* Coolflux interrupt vector table address2 LSB , */\
+ { 0x9e0f, "ivt_addr3_msb"}, /* Coolflux interrupt vector table address3 MSB , */\
+ { 0x9f0f, "ivt_addr3_lsb"}, /* Coolflux interrupt vector table address3 LSB , */\
+ { 0xa007, "mtpkey1"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
+ { 0xa107, "mtpkey2"}, /* MTP KEY2 register , */\
+ { 0xa200, "key01_locked"}, /* Indicates KEY1 is locked , */\
+ { 0xa210, "key02_locked"}, /* Indicates KEY2 is locked , */\
+ { 0xa302, "mtp_man_address_in"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
+ { 0xa330, "man_copy_mtp_to_iic"}, /* Start copying single word from mtp to I2C mtp register, */\
+ { 0xa340, "man_copy_iic_to_mtp"}, /* Start copying single word from I2C mtp register to mtp, */\
+ { 0xa350, "auto_copy_mtp_to_iic"}, /* Start copying all the data from mtp to I2C mtp registers, */\
+ { 0xa360, "auto_copy_iic_to_mtp"}, /* Start copying data from I2C mtp registers to mtp , */\
+ { 0xa400, "faim_set_clkws"}, /* Sets the faim controller clock wait state register, */\
+ { 0xa410, "faim_sel_evenrows"}, /* All even rows of the faim are selected, active high, */\
+ { 0xa420, "faim_sel_oddrows"}, /* All odd rows of the faim are selected, all rows in combination with sel_evenrows, */\
+ { 0xa430, "faim_program_only"}, /* Skip the erase access at wr_faim command (write-program-marginread), */\
+ { 0xa440, "faim_erase_only"}, /* Skip the program access at wr_faim command (write-erase-marginread), */\
+ { 0xa50f, "mtp_man_data_out_msb"}, /* MSB word of MTP manual read data , */\
+ { 0xa60f, "mtp_man_data_out_lsb"}, /* LSB word of MTP manual read data , */\
+ { 0xa70f, "mtp_man_data_in_msb"}, /* MSB word of write data for MTP manual write , */\
+ { 0xa80f, "mtp_man_data_in_lsb"}, /* LSB word of write data for MTP manual write , */\
+ { 0xb010, "bypass_ocpcounter"}, /* Bypass OCP Counter , */\
+ { 0xb020, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
+ { 0xb030, "bypass_ovp"}, /* Bypass OVP , */\
+ { 0xb040, "bypass_uvp"}, /* Bypass UVP , */\
+ { 0xb050, "bypass_otp"}, /* Bypass OTP , */\
+ { 0xb060, "bypass_lost_clk"}, /* Bypass lost clock detector , */\
+ { 0xb070, "ctrl_vpalarm"}, /* vpalarm (uvp ovp handling) , */\
+ { 0xb087, "ocp_threshold"}, /* OCP threshold level , */\
+ { 0xb108, "ext_temp"}, /* External temperature (C) , */\
+ { 0xb190, "ext_temp_sel"}, /* Select temp Speaker calibration , */\
+ { 0xc000, "use_direct_ctrls"}, /* Direct control to overrule several functions for testing, */\
+ { 0xc010, "rst_datapath"}, /* Direct control for datapath reset , */\
+ { 0xc020, "rst_cgu"}, /* Direct control for cgu reset , */\
+ { 0xc038, "enbl_ref"}, /* Switch on the analog references, each part of the references can be switched on/off individually, */\
+ { 0xc0d0, "enbl_ringo"}, /* Enable the ring oscillator for test purpose , */\
+ { 0xc0e0, "use_direct_clk_ctrl"}, /* Direct clock control to overrule several functions for testing, */\
+ { 0xc0f0, "use_direct_pll_ctrl"}, /* Direct PLL control to overrule several functions for testing, */\
+ { 0xc100, "enbl_tsense"}, /* Temperature sensor enable control - I2C direct mode, */\
+ { 0xc110, "tsense_hibias"}, /* Bit to set the biasing in temp sensor to high , */\
+ { 0xc120, "enbl_flag_vbg"}, /* Enable flagging of bandgap out of control , */\
+ { 0xc20f, "abist_offset"}, /* Offset control for ABIST testing (two's complement), */\
+ { 0xc300, "bypasslatch"}, /* Bypass latch , */\
+ { 0xc311, "sourcea"}, /* Set OUTA to , */\
+ { 0xc331, "sourceb"}, /* Set OUTB to , */\
+ { 0xc350, "inverta"}, /* Invert pwma test signal , */\
+ { 0xc360, "invertb"}, /* Invert pwmb test signal , */\
+ { 0xc374, "pulselength"}, /* Pulse length setting test input for amplifier (clock d - k*2048*fs), */\
+ { 0xc3c0, "tdm_enable_loopback"}, /* TDM loopback test , */\
+ { 0xc3d0, "test_abistfft_enbl"}, /* FFT Coolflux , */\
+ { 0xc3e0, "test_pwr_switch"}, /* Test mode for digital power switches core sw/mem sw/micvdd sw, */\
+ { 0xc400, "bst_bypasslatch"}, /* Bypass latch in boost converter , */\
+ { 0xc411, "bst_source"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
+ { 0xc430, "bst_invertb"}, /* Invert pwmbst test signal , */\
+ { 0xc444, "bst_pulselength"}, /* Pulse length setting test input for boost converter , */\
+ { 0xc490, "test_bst_ctrlsthv"}, /* Test mode for boost control stage , */\
+ { 0xc4a0, "test_bst_iddq"}, /* IDDQ testing in power stage of boost converter , */\
+ { 0xc4b0, "test_bst_rdson"}, /* RDSON testing - boost power stage , */\
+ { 0xc4c0, "test_bst_cvi"}, /* CVI testing - boost power stage , */\
+ { 0xc4d0, "test_bst_ocp"}, /* Boost OCP. For old ocp (ctrl_reversebst is 0), For new ocp (ctrl_reversebst is 1), */\
+ { 0xc4e0, "test_bst_sense"}, /* Test option for the sense NMOS in booster for current mode control., */\
+ { 0xc500, "test_cvi"}, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */\
+ { 0xc510, "test_discrete"}, /* Test function noise measurement , */\
+ { 0xc520, "test_iddq"}, /* Set the power stages in iddq mode for gate stress., */\
+ { 0xc540, "test_rdson"}, /* Analog BIST, switch to enable Rdson measurement , */\
+ { 0xc550, "test_sdelta"}, /* Analog BIST, noise test , */\
+ { 0xc570, "test_enbl_cs"}, /* Enable for digimux mode of current sense , */\
+ { 0xc600, "enbl_pwm_dcc"}, /* Enables direct control of pwm duty cycle for DCDC power stage, */\
+ { 0xc613, "pwm_dcc_cnt"}, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */\
+ { 0xc650, "enbl_ldo_stress"}, /* Enable stress of internal supply voltages powerstages, */\
+ { 0xc660, "bypass_diosw_ovp"}, /* Bypass ovp for memory switch diosw , */\
+ { 0xc670, "enbl_powerswitch"}, /* Vddd core power switch control - overrules the manager control, */\
+ { 0xc707, "digimuxa_sel"}, /* DigimuxA input selection control routed to GPIO1 (see Digimux list for details), */\
+ { 0xc787, "digimuxb_sel"}, /* DigimuxB input selection control routed to GPIO2 (see Digimux list for details), */\
+ { 0xc807, "digimuxc_sel"}, /* DigimuxC input selection control routed to GPIO3 (see Digimux list for details), */\
+ { 0xc887, "digimuxd_sel"}, /* DigimuxD input selection control routed to GPIO4 (see Digimux list for details), */\
+ { 0xc901, "dio1_ehs"}, /* Speed/load setting for DIO1 IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
+ { 0xc921, "dio2_ehs"}, /* Speed/load setting for DIO2 IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
+ { 0xc941, "gainio_ehs"}, /* Speed/load setting for GAINIO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
+ { 0xc961, "pdmo_ehs"}, /* Speed/load setting for PDMO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
+ { 0xc981, "int_ehs"}, /* Speed/load setting for INT IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
+ { 0xc9a1, "tdo_ehs"}, /* Speed/load setting for TDO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
+ { 0xc9c0, "hs_mode"}, /* I2C high speed mode control , */\
+ { 0xca00, "enbl_anamux1"}, /* Enable anamux1 , */\
+ { 0xca10, "enbl_anamux2"}, /* Enable anamux2 , */\
+ { 0xca20, "enbl_anamux3"}, /* Enable anamux3 , */\
+ { 0xca30, "enbl_anamux4"}, /* Enable anamux4 , */\
+ { 0xca40, "enbl_anamux5"}, /* Enable anamux5 , */\
+ { 0xca50, "enbl_anamux6"}, /* Enable anamux6 , */\
+ { 0xca60, "enbl_anamux7"}, /* Enable anamux7 , */\
+ { 0xca74, "anamux1"}, /* Anamux selection control - anamux on TEST1 , */\
+ { 0xcb04, "anamux2"}, /* Anamux selection control - anamux on TEST2 , */\
+ { 0xcb54, "anamux3"}, /* Anamux selection control - anamux on TEST3 , */\
+ { 0xcba4, "anamux4"}, /* Anamux selection control - anamux on TEST4 , */\
+ { 0xcc04, "anamux5"}, /* Anamux selection control - anamux on TEST5 , */\
+ { 0xcc54, "anamux6"}, /* Anamux selection control - anamux on TEST6 , */\
+ { 0xcca4, "anamux7"}, /* Anamux selection control - anamux on TEST7 , */\
+ { 0xcd05, "pll_seli"}, /* PLL SELI - I2C direct PLL control mode only , */\
+ { 0xcd64, "pll_selp"}, /* PLL SELP - I2C direct PLL control mode only , */\
+ { 0xcdb3, "pll_selr"}, /* PLL SELR - I2C direct PLL control mode only , */\
+ { 0xcdf0, "pll_frm"}, /* PLL free running mode control; 1 in TCB direct control mode, else this control bit, */\
+ { 0xce09, "pll_ndec"}, /* PLL NDEC - I2C direct PLL control mode only , */\
+ { 0xcea0, "pll_mdec_msb"}, /* MSB of pll_mdec - I2C direct PLL control mode only, */\
+ { 0xceb0, "enbl_pll"}, /* Enables PLL in I2C direct PLL control mode only , */\
+ { 0xcec0, "enbl_osc"}, /* Enables OSC1M in I2C direct control mode only , */\
+ { 0xced0, "pll_bypass"}, /* PLL bypass control in I2C direct PLL control mode only, */\
+ { 0xcee0, "pll_directi"}, /* PLL directi control in I2C direct PLL control mode only, */\
+ { 0xcef0, "pll_directo"}, /* PLL directo control in I2C direct PLL control mode only, */\
+ { 0xcf0f, "pll_mdec_lsb"}, /* Bits 15..0 of PLL MDEC are I2C direct PLL control mode only, */\
+ { 0xd006, "pll_pdec"}, /* PLL PDEC - I2C direct PLL control mode only , */\
+ { 0xd10f, "tsig_freq_lsb"}, /* Internal sinus test generator frequency control , */\
+ { 0xd202, "tsig_freq_msb"}, /* Select internal sinus test generator, frequency control msb bits, */\
+ { 0xd230, "inject_tsig"}, /* Control bit to switch to internal sinus test generator, */\
+ { 0xd243, "tsig_gain_left"}, /* Test signal gain for left channel , */\
+ { 0xd283, "tsig_gain_right"}, /* Test signal gain for right channel , */\
+ { 0xd300, "adc10_reset"}, /* Reset for ADC10 - I2C direct control mode , */\
+ { 0xd311, "adc10_test"}, /* Test mode selection signal for ADC10 - I2C direct control mode, */\
+ { 0xd332, "adc10_sel"}, /* Select the input to convert for ADC10 - I2C direct control mode, */\
+ { 0xd364, "adc10_prog_sample"}, /* ADC10 program sample setting - I2C direct control mode, */\
+ { 0xd3b0, "adc10_enbl"}, /* Enable ADC10 - I2C direct control mode , */\
+ { 0xd3c0, "bypass_lp_vbat"}, /* Bypass control for Low pass filter in batt sensor , */\
+ { 0xd409, "data_adc10_tempbat"}, /* ADC 10 data output data for testing , */\
+ { 0xd506, "ctrl_digtoana_hidden"}, /* Spare digital to analog control bits - Hidden , */\
+ { 0xd570, "enbl_clk_out_of_range"}, /* Clock out of range , */\
+ { 0xf000, "calibration_onetime"}, /* Calibration schedule , */\
+ { 0xf010, "calibr_ron_done"}, /* Calibration Ron executed , */\
+ { 0xf020, "calibr_dcdc_api_calibrate"}, /* Calibration current limit DCDC , */\
+ { 0xf030, "calibr_dcdc_delta_sign"}, /* Sign bit for delta calibration current limit DCDC , */\
+ { 0xf042, "calibr_dcdc_delta"}, /* Calibration delta current limit DCDC , */\
+ { 0xf078, "calibr_speaker_info"}, /* Reserved space for allowing customer to store speaker information, */\
+ { 0xf105, "calibr_vout_offset"}, /* DCDC offset calibration 2's complement (key1 protected), */\
+ { 0xf163, "calibr_gain_left"}, /* HW gain module - left channel (2's complement) , */\
+ { 0xf1a5, "calibr_offset_left"}, /* Offset for amplifier, HW gain module - left channel (2's complement), */\
+ { 0xf203, "calibr_gain_right"}, /* HW gain module - right channel (2's complement) , */\
+ { 0xf245, "calibr_offset_right"}, /* Offset for amplifier, HW gain module - right channel (2's complement), */\
+ { 0xf2a3, "calibr_rcvldop_trim"}, /* Trimming of LDO (2.7V) , */\
+ { 0xf307, "calibr_gain_cs_left"}, /* Current sense gain - left channel (signed two's complement format), */\
+ { 0xf387, "calibr_gain_cs_right"}, /* Current sense gain - right channel (signed two's complement format), */\
+ { 0xf40f, "calibr_R25C_L"}, /* Ron resistance of left channel speaker coil , */\
+ { 0xf50f, "calibr_R25C_R"}, /* Ron resistance of right channel speaker coil , */\
+ { 0xf606, "ctrl_offset_a_left"}, /* Offset of left amplifier level shifter A , */\
+ { 0xf686, "ctrl_offset_b_left"}, /* Offset of left amplifier level shifter B , */\
+ { 0xf706, "ctrl_offset_a_right"}, /* Offset of right amplifier level shifter A , */\
+ { 0xf786, "ctrl_offset_b_right"}, /* Offset of right amplifier level shifter B , */\
+ { 0xf806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
+ { 0xf870, "htol_iic_addr_en"}, /* HTOL I2C address enable control , */\
+ { 0xf884, "calibr_temp_offset"}, /* Temperature offset 2's compliment (key1 protected), */\
+ { 0xf8d2, "calibr_temp_gain"}, /* Temperature gain 2's compliment (key1 protected) , */\
+ { 0xf900, "mtp_lock_dcdcoff_mode"}, /* Disable function dcdcoff_mode , */\
+ { 0xf910, "mtp_lock_enbl_coolflux"}, /* Disable function enbl_coolflux , */\
+ { 0xf920, "mtp_lock_bypass_clipper"}, /* Disable function bypass_clipper , */\
+ { 0xf930, "mtp_lock_max_dcdc_voltage"}, /* Disable programming of max dcdc boost voltage , */\
+ { 0xf943, "calibr_vbg_trim"}, /* Bandgap trimming control , */\
+ { 0xf987, "type_bits_fw"}, /* MTP-control FW - See Firmware I2C API document for details, */\
+ { 0xfa0f, "mtpdataA"}, /* MTPdataA (key1 protected) , */\
+ { 0xfb0f, "mtpdataB"}, /* MTPdataB (key1 protected) , */\
+ { 0xfc0f, "mtpdataC"}, /* MTPdataC (key1 protected) , */\
+ { 0xfd0f, "mtpdataD"}, /* MTPdataD (key1 protected) , */\
+ { 0xfe0f, "mtpdataE"}, /* MTPdataE (key1 protected) , */\
+ { 0xff05, "calibr_osc_delta_ndiv"}, /* Calibration data for OSC1M, signed number representation, */\
+ { 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+
+enum tfa2_irq {
+ tfa2_irq_stvdds = 0,
+ tfa2_irq_stplls = 1,
+ tfa2_irq_stotds = 2,
+ tfa2_irq_stovds = 3,
+ tfa2_irq_stuvds = 4,
+ tfa2_irq_stclks = 5,
+ tfa2_irq_stmtpb = 6,
+ tfa2_irq_stnoclk = 7,
+ tfa2_irq_stspks = 8,
+ tfa2_irq_stacs = 9,
+ tfa2_irq_stsws = 10,
+ tfa2_irq_stwds = 11,
+ tfa2_irq_stamps = 12,
+ tfa2_irq_starefs = 13,
+ tfa2_irq_stadccr = 14,
+ tfa2_irq_stbodnok = 15,
+ tfa2_irq_stbstcu = 16,
+ tfa2_irq_stbsthi = 17,
+ tfa2_irq_stbstoc = 18,
+ tfa2_irq_stbstpkcur = 19,
+ tfa2_irq_stbstvc = 20,
+ tfa2_irq_stbst86 = 21,
+ tfa2_irq_stbst93 = 22,
+ tfa2_irq_strcvld = 23,
+ tfa2_irq_stocpl = 24,
+ tfa2_irq_stocpr = 25,
+ tfa2_irq_stmwsrc = 26,
+ tfa2_irq_stmwcfc = 27,
+ tfa2_irq_stmwsmu = 28,
+ tfa2_irq_stcfmer = 29,
+ tfa2_irq_stcfmac = 30,
+ tfa2_irq_stclkoor = 31,
+ tfa2_irq_sttdmer = 32,
+ tfa2_irq_stclpl = 33,
+ tfa2_irq_stclpr = 34,
+ tfa2_irq_stocpm = 35,
+ tfa2_irq_max = 36,
+ tfa2_irq_all = -1 /* all irqs */};
+
+#define TFA2_IRQ_NAMETABLE static tfaIrqName_t Tfa2IrqNames[] = {\
+ { 0, "STVDDS"},\
+ { 1, "STPLLS"},\
+ { 2, "STOTDS"},\
+ { 3, "STOVDS"},\
+ { 4, "STUVDS"},\
+ { 5, "STCLKS"},\
+ { 6, "STMTPB"},\
+ { 7, "STNOCLK"},\
+ { 8, "STSPKS"},\
+ { 9, "STACS"},\
+ { 10, "STSWS"},\
+ { 11, "STWDS"},\
+ { 12, "STAMPS"},\
+ { 13, "STAREFS"},\
+ { 14, "STADCCR"},\
+ { 15, "STBODNOK"},\
+ { 16, "STBSTCU"},\
+ { 17, "STBSTHI"},\
+ { 18, "STBSTOC"},\
+ { 19, "STBSTPKCUR"},\
+ { 20, "STBSTVC"},\
+ { 21, "STBST86"},\
+ { 22, "STBST93"},\
+ { 23, "STRCVLD"},\
+ { 24, "STOCPL"},\
+ { 25, "STOCPR"},\
+ { 26, "STMWSRC"},\
+ { 27, "STMWCFC"},\
+ { 28, "STMWSMU"},\
+ { 29, "STCFMER"},\
+ { 30, "STCFMAC"},\
+ { 31, "STCLKOOR"},\
+ { 32, "STTDMER"},\
+ { 33, "STCLPL"},\
+ { 34, "STCLPR"},\
+ { 35, "STOCPM"},\
+ { 36, "36"},\
+};
diff --git a/sound/soc/codecs/tfa9872_tfafieldnames.h b/sound/soc/codecs/tfa9872_tfafieldnames.h
new file mode 100644
index 0000000..6dd639e
--- /dev/null
+++ b/sound/soc/codecs/tfa9872_tfafieldnames.h
@@ -0,0 +1,1221 @@
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _TFA9872_TFAFIELDNAMES_H
+#define _TFA9872_TFAFIELDNAMES_H
+
+#define TFA9872_I2CVERSION_N1A 26
+#define TFA9872_I2CVERSION_N1B 29
+#define TFA9872_I2CVERSION_N1B2 25
+
+typedef enum nxpTfa9872BfEnumList {
+TFA9872_BF_PWDN = 0x0000, /*!< Powerdown selection */
+TFA9872_BF_I2CR = 0x0010, /*!< I2C Reset - Auto clear */
+TFA9872_BF_AMPE = 0x0030, /*!< Activate Amplifier */
+TFA9872_BF_DCA = 0x0040, /*!< Activate DC-to-DC converter */
+TFA9872_BF_INTP = 0x0071, /*!< Interrupt config */
+TFA9872_BF_BYPOCP = 0x00b0, /*!< Bypass OCP */
+TFA9872_BF_TSTOCP = 0x00c0, /*!< OCP testing control */
+TFA9872_BF_MANSCONF = 0x0120, /*!< I2C configured */
+TFA9872_BF_MANAOOSC = 0x0140, /*!< Internal osc off at PWDN */
+TFA9872_BF_MUTETO = 0x01d0, /*!< Time out SB mute sequence */
+TFA9872_BF_RCVNS = 0x01e0, /*!< Noise shaper selection */
+TFA9872_BF_AUDFS = 0x0203, /*!< Sample rate (fs) */
+TFA9872_BF_INPLEV = 0x0240, /*!< TDM output attenuation */
+TFA9872_BF_FRACTDEL = 0x0255, /*!< V/I Fractional delay */
+TFA9872_BF_BYPHVBF = 0x02b0, /*!< Bypass HVBAT filter */
+TFA9872_BF_REV = 0x030f, /*!< Revision info */
+TFA9872_BF_REFCKEXT = 0x0401, /*!< PLL external ref clock */
+TFA9872_BF_REFCKSEL = 0x0420, /*!< PLL internal ref clock */
+TFA9872_BF_SSE = 0x0510, /*!< Enable speaker path */
+TFA9872_BF_VSE = 0x0530, /*!< Voltage sense */
+TFA9872_BF_CSE = 0x0550, /*!< Current sense */
+TFA9872_BF_SSPDME = 0x0560, /*!< Sub-system PDM */
+TFA9872_BF_PGAE = 0x0580, /*!< Enable PGA chop clock */
+TFA9872_BF_SSTDME = 0x0590, /*!< Sub-system TDM */
+TFA9872_BF_SSPBSTE = 0x05a0, /*!< Sub-system boost */
+TFA9872_BF_SSADCE = 0x05b0, /*!< Sub-system ADC */
+TFA9872_BF_SSFAIME = 0x05c0, /*!< Sub-system FAIM */
+TFA9872_BF_STGAIN = 0x0d18, /*!< Side tone gain */
+TFA9872_BF_STSMUTE = 0x0da0, /*!< Side tone soft mute */
+TFA9872_BF_ST1C = 0x0db0, /*!< side tone one s complement */
+TFA9872_BF_VDDS = 0x1000, /*!< POR */
+TFA9872_BF_PLLS = 0x1010, /*!< PLL lock */
+TFA9872_BF_OTDS = 0x1020, /*!< OTP alarm */
+TFA9872_BF_OVDS = 0x1030, /*!< OVP alarm */
+TFA9872_BF_UVDS = 0x1040, /*!< UVP alarm */
+TFA9872_BF_CLKS = 0x1050, /*!< Clocks stable */
+TFA9872_BF_MTPB = 0x1060, /*!< MTP busy */
+TFA9872_BF_NOCLK = 0x1070, /*!< Lost clock */
+TFA9872_BF_SWS = 0x10a0, /*!< Amplifier engage */
+TFA9872_BF_AMPS = 0x10c0, /*!< Amplifier enable */
+TFA9872_BF_AREFS = 0x10d0, /*!< References enable */
+TFA9872_BF_ADCCR = 0x10e0, /*!< Control ADC */
+TFA9872_BF_DCIL = 0x1100, /*!< DCDC current limiting */
+TFA9872_BF_DCDCA = 0x1110, /*!< DCDC active */
+TFA9872_BF_DCOCPOK = 0x1120, /*!< DCDC OCP nmos */
+TFA9872_BF_DCHVBAT = 0x1140, /*!< DCDC level 1x */
+TFA9872_BF_DCH114 = 0x1150, /*!< DCDC level 1.14x */
+TFA9872_BF_DCH107 = 0x1160, /*!< DCDC level 1.07x */
+TFA9872_BF_STMUTEB = 0x1170, /*!< side tone (un)mute busy */
+TFA9872_BF_STMUTE = 0x1180, /*!< side tone mute state */
+TFA9872_BF_TDMLUTER = 0x1190, /*!< TDM LUT error */
+TFA9872_BF_TDMSTAT = 0x11a2, /*!< TDM status bits */
+TFA9872_BF_TDMERR = 0x11d0, /*!< TDM error */
+TFA9872_BF_OCPOAP = 0x1300, /*!< OCPOK pmos A */
+TFA9872_BF_OCPOAN = 0x1310, /*!< OCPOK nmos A */
+TFA9872_BF_OCPOBP = 0x1320, /*!< OCPOK pmos B */
+TFA9872_BF_OCPOBN = 0x1330, /*!< OCPOK nmos B */
+TFA9872_BF_CLIPAH = 0x1340, /*!< Clipping A to Vddp */
+TFA9872_BF_CLIPAL = 0x1350, /*!< Clipping A to gnd */
+TFA9872_BF_CLIPBH = 0x1360, /*!< Clipping B to Vddp */
+TFA9872_BF_CLIPBL = 0x1370, /*!< Clipping B to gnd */
+TFA9872_BF_OCDS = 0x1380, /*!< OCP amplifier */
+TFA9872_BF_CLIPS = 0x1390, /*!< Amplifier clipping */
+TFA9872_BF_OCPOKMC = 0x13a0, /*!< OCPOK MICVDD */
+TFA9872_BF_MANALARM = 0x13b0, /*!< Alarm state */
+TFA9872_BF_MANWAIT1 = 0x13c0, /*!< Wait HW I2C settings */
+TFA9872_BF_MANMUTE = 0x13e0, /*!< Audio mute sequence */
+TFA9872_BF_MANOPER = 0x13f0, /*!< Operating state */
+TFA9872_BF_CLKOOR = 0x1420, /*!< External clock status */
+TFA9872_BF_MANSTATE = 0x1433, /*!< Device manager status */
+TFA9872_BF_DCMODE = 0x1471, /*!< DCDC mode status bits */
+TFA9872_BF_BATS = 0x1509, /*!< Battery voltage (V) */
+TFA9872_BF_TEMPS = 0x1608, /*!< IC Temperature (C) */
+TFA9872_BF_VDDPS = 0x1709, /*!< IC VDDP voltage ( 1023*VDDP/9.5 V) */
+TFA9872_BF_TDME = 0x2040, /*!< Enable interface */
+TFA9872_BF_TDMMODE = 0x2050, /*!< Slave/master */
+TFA9872_BF_TDMCLINV = 0x2060, /*!< Reception data to BCK clock */
+TFA9872_BF_TDMFSLN = 0x2073, /*!< FS length (master mode only) */
+TFA9872_BF_TDMFSPOL = 0x20b0, /*!< FS polarity */
+TFA9872_BF_TDMNBCK = 0x20c3, /*!< N-BCK's in FS */
+TFA9872_BF_TDMSLOTS = 0x2103, /*!< N-slots in Frame */
+TFA9872_BF_TDMSLLN = 0x2144, /*!< N-bits in slot */
+TFA9872_BF_TDMBRMG = 0x2194, /*!< N-bits remaining */
+TFA9872_BF_TDMDEL = 0x21e0, /*!< data delay to FS */
+TFA9872_BF_TDMADJ = 0x21f0, /*!< data adjustment */
+TFA9872_BF_TDMOOMP = 0x2201, /*!< Received audio compression */
+TFA9872_BF_TDMSSIZE = 0x2224, /*!< Sample size per slot */
+TFA9872_BF_TDMTXDFO = 0x2271, /*!< Format unused bits */
+TFA9872_BF_TDMTXUS0 = 0x2291, /*!< Format unused slots DATAO */
+TFA9872_BF_TDMSPKE = 0x2300, /*!< Control audio tdm channel in 0 (spkr + dcdc) */
+TFA9872_BF_TDMDCE = 0x2310, /*!< Control audio tdm channel in 1 (dcdc) */
+TFA9872_BF_TDMCSE = 0x2330, /*!< current sense vbat temperature and vddp feedback */
+TFA9872_BF_TDMVSE = 0x2340, /*!< Voltage sense vbat temperature and vddp feedback */
+TFA9872_BF_TDMSPKS = 0x2603, /*!< tdm slot for sink 0 (speaker + dcdc) */
+TFA9872_BF_TDMDCS = 0x2643, /*!< tdm slot for sink 1 (dcdc) */
+TFA9872_BF_TDMCSS = 0x26c3, /*!< Slot Position of current sense vbat temperature and vddp feedback */
+TFA9872_BF_TDMVSS = 0x2703, /*!< Slot Position of Voltage sense vbat temperature and vddp feedback */
+TFA9872_BF_PDMSTSEL = 0x3111, /*!< Side tone input */
+TFA9872_BF_ISTVDDS = 0x4000, /*!< Status POR */
+TFA9872_BF_ISTPLLS = 0x4010, /*!< Status PLL lock */
+TFA9872_BF_ISTOTDS = 0x4020, /*!< Status OTP alarm */
+TFA9872_BF_ISTOVDS = 0x4030, /*!< Status OVP alarm */
+TFA9872_BF_ISTUVDS = 0x4040, /*!< Status UVP alarm */
+TFA9872_BF_ISTCLKS = 0x4050, /*!< Status clocks stable */
+TFA9872_BF_ISTMTPB = 0x4060, /*!< Status MTP busy */
+TFA9872_BF_ISTNOCLK = 0x4070, /*!< Status lost clock */
+TFA9872_BF_ISTSWS = 0x40a0, /*!< Status amplifier engage */
+TFA9872_BF_ISTAMPS = 0x40c0, /*!< Status amplifier enable */
+TFA9872_BF_ISTAREFS = 0x40d0, /*!< Status Ref enable */
+TFA9872_BF_ISTADCCR = 0x40e0, /*!< Status Control ADC */
+TFA9872_BF_ISTBSTCU = 0x4100, /*!< Status DCDC current limiting */
+TFA9872_BF_ISTBSTHI = 0x4110, /*!< Status DCDC active */
+TFA9872_BF_ISTBSTOC = 0x4120, /*!< Status DCDC OCP */
+TFA9872_BF_ISTBSTPKCUR = 0x4130, /*!< Status bst peakcur */
+TFA9872_BF_ISTBSTVC = 0x4140, /*!< Status DCDC level 1x */
+TFA9872_BF_ISTBST86 = 0x4150, /*!< Status DCDC level 1.14x */
+TFA9872_BF_ISTBST93 = 0x4160, /*!< Status DCDC level 1.07x */
+TFA9872_BF_ISTOCPR = 0x4190, /*!< Status ocp alarm */
+TFA9872_BF_ISTMWSRC = 0x41a0, /*!< Status Waits HW I2C settings */
+TFA9872_BF_ISTMWSMU = 0x41c0, /*!< Status Audio mute sequence */
+TFA9872_BF_ISTCLKOOR = 0x41f0, /*!< Status flag_clk_out_of_range */
+TFA9872_BF_ISTTDMER = 0x4200, /*!< Status tdm error */
+TFA9872_BF_ISTCLPR = 0x4220, /*!< Status clip */
+TFA9872_BF_ISTLP0 = 0x4240, /*!< Status low power mode0 */
+TFA9872_BF_ISTLP1 = 0x4250, /*!< Status low power mode1 */
+TFA9872_BF_ISTLA = 0x4260, /*!< Status low noise detection */
+TFA9872_BF_ISTVDDPH = 0x4270, /*!< Status VDDP greater than VBAT */
+TFA9872_BF_ICLVDDS = 0x4400, /*!< Clear POR */
+TFA9872_BF_ICLPLLS = 0x4410, /*!< Clear PLL lock */
+TFA9872_BF_ICLOTDS = 0x4420, /*!< Clear OTP alarm */
+TFA9872_BF_ICLOVDS = 0x4430, /*!< Clear OVP alarm */
+TFA9872_BF_ICLUVDS = 0x4440, /*!< Clear UVP alarm */
+TFA9872_BF_ICLCLKS = 0x4450, /*!< Clear clocks stable */
+TFA9872_BF_ICLMTPB = 0x4460, /*!< Clear mtp busy */
+TFA9872_BF_ICLNOCLK = 0x4470, /*!< Clear lost clk */
+TFA9872_BF_ICLSWS = 0x44a0, /*!< Clear amplifier engage */
+TFA9872_BF_ICLAMPS = 0x44c0, /*!< Clear enbl amp */
+TFA9872_BF_ICLAREFS = 0x44d0, /*!< Clear ref enable */
+TFA9872_BF_ICLADCCR = 0x44e0, /*!< Clear control ADC */
+TFA9872_BF_ICLBSTCU = 0x4500, /*!< Clear DCDC current limiting */
+TFA9872_BF_ICLBSTHI = 0x4510, /*!< Clear DCDC active */
+TFA9872_BF_ICLBSTOC = 0x4520, /*!< Clear DCDC OCP */
+TFA9872_BF_ICLBSTPC = 0x4530, /*!< Clear bst peakcur */
+TFA9872_BF_ICLBSTVC = 0x4540, /*!< Clear DCDC level 1x */
+TFA9872_BF_ICLBST86 = 0x4550, /*!< Clear DCDC level 1.14x */
+TFA9872_BF_ICLBST93 = 0x4560, /*!< Clear DCDC level 1.07x */
+TFA9872_BF_ICLOCPR = 0x4590, /*!< Clear ocp alarm */
+TFA9872_BF_ICLMWSRC = 0x45a0, /*!< Clear wait HW I2C settings */
+TFA9872_BF_ICLMWSMU = 0x45c0, /*!< Clear audio mute sequence */
+TFA9872_BF_ICLCLKOOR = 0x45f0, /*!< Clear flag_clk_out_of_range */
+TFA9872_BF_ICLTDMER = 0x4600, /*!< Clear tdm error */
+TFA9872_BF_ICLCLPR = 0x4620, /*!< Clear clip */
+TFA9872_BF_ICLLP0 = 0x4640, /*!< Clear low power mode0 */
+TFA9872_BF_ICLLP1 = 0x4650, /*!< Clear low power mode1 */
+TFA9872_BF_ICLLA = 0x4660, /*!< Clear low noise detection */
+TFA9872_BF_ICLVDDPH = 0x4670, /*!< Clear VDDP greater then VBAT */
+TFA9872_BF_IEVDDS = 0x4800, /*!< Enable por */
+TFA9872_BF_IEPLLS = 0x4810, /*!< Enable pll lock */
+TFA9872_BF_IEOTDS = 0x4820, /*!< Enable OTP alarm */
+TFA9872_BF_IEOVDS = 0x4830, /*!< Enable OVP alarm */
+TFA9872_BF_IEUVDS = 0x4840, /*!< Enable UVP alarm */
+TFA9872_BF_IECLKS = 0x4850, /*!< Enable clocks stable */
+TFA9872_BF_IEMTPB = 0x4860, /*!< Enable mtp busy */
+TFA9872_BF_IENOCLK = 0x4870, /*!< Enable lost clk */
+TFA9872_BF_IESWS = 0x48a0, /*!< Enable amplifier engage */
+TFA9872_BF_IEAMPS = 0x48c0, /*!< Enable enbl amp */
+TFA9872_BF_IEAREFS = 0x48d0, /*!< Enable ref enable */
+TFA9872_BF_IEADCCR = 0x48e0, /*!< Enable Control ADC */
+TFA9872_BF_IEBSTCU = 0x4900, /*!< Enable DCDC current limiting */
+TFA9872_BF_IEBSTHI = 0x4910, /*!< Enable DCDC active */
+TFA9872_BF_IEBSTOC = 0x4920, /*!< Enable DCDC OCP */
+TFA9872_BF_IEBSTPC = 0x4930, /*!< Enable bst peakcur */
+TFA9872_BF_IEBSTVC = 0x4940, /*!< Enable DCDC level 1x */
+TFA9872_BF_IEBST86 = 0x4950, /*!< Enable DCDC level 1.14x */
+TFA9872_BF_IEBST93 = 0x4960, /*!< Enable DCDC level 1.07x */
+TFA9872_BF_IEOCPR = 0x4990, /*!< Enable ocp alarm */
+TFA9872_BF_IEMWSRC = 0x49a0, /*!< Enable waits HW I2C settings */
+TFA9872_BF_IEMWSMU = 0x49c0, /*!< Enable man Audio mute sequence */
+TFA9872_BF_IECLKOOR = 0x49f0, /*!< Enable flag_clk_out_of_range */
+TFA9872_BF_IETDMER = 0x4a00, /*!< Enable tdm error */
+TFA9872_BF_IECLPR = 0x4a20, /*!< Enable clip */
+TFA9872_BF_IELP0 = 0x4a40, /*!< Enable low power mode0 */
+TFA9872_BF_IELP1 = 0x4a50, /*!< Enable low power mode1 */
+TFA9872_BF_IELA = 0x4a60, /*!< Enable low noise detection */
+TFA9872_BF_IEVDDPH = 0x4a70, /*!< Enable VDDP greater tehn VBAT */
+TFA9872_BF_IPOVDDS = 0x4c00, /*!< Polarity por */
+TFA9872_BF_IPOPLLS = 0x4c10, /*!< Polarity pll lock */
+TFA9872_BF_IPOOTDS = 0x4c20, /*!< Polarity OTP alarm */
+TFA9872_BF_IPOOVDS = 0x4c30, /*!< Polarity OVP alarm */
+TFA9872_BF_IPOUVDS = 0x4c40, /*!< Polarity UVP alarm */
+TFA9872_BF_IPOCLKS = 0x4c50, /*!< Polarity clocks stable */
+TFA9872_BF_IPOMTPB = 0x4c60, /*!< Polarity mtp busy */
+TFA9872_BF_IPONOCLK = 0x4c70, /*!< Polarity lost clk */
+TFA9872_BF_IPOSWS = 0x4ca0, /*!< Polarity amplifier engage */
+TFA9872_BF_IPOAMPS = 0x4cc0, /*!< Polarity enbl amp */
+TFA9872_BF_IPOAREFS = 0x4cd0, /*!< Polarity ref enable */
+TFA9872_BF_IPOADCCR = 0x4ce0, /*!< Polarity Control ADC */
+TFA9872_BF_IPOBSTCU = 0x4d00, /*!< Polarity DCDC current limiting */
+TFA9872_BF_IPOBSTHI = 0x4d10, /*!< Polarity DCDC active */
+TFA9872_BF_IPOBSTOC = 0x4d20, /*!< Polarity DCDC OCP */
+TFA9872_BF_IPOBSTPC = 0x4d30, /*!< Polarity bst peakcur */
+TFA9872_BF_IPOBSTVC = 0x4d40, /*!< Polarity DCDC level 1x */
+TFA9872_BF_IPOBST86 = 0x4d50, /*!< Polarity DCDC level 1.14x */
+TFA9872_BF_IPOBST93 = 0x4d60, /*!< Polarity DCDC level 1.07x */
+TFA9872_BF_IPOOCPR = 0x4d90, /*!< Polarity ocp alarm */
+TFA9872_BF_IPOMWSRC = 0x4da0, /*!< Polarity waits HW I2C settings */
+TFA9872_BF_IPOMWSMU = 0x4dc0, /*!< Polarity man audio mute sequence */
+TFA9872_BF_IPCLKOOR = 0x4df0, /*!< Polarity flag_clk_out_of_range */
+TFA9872_BF_IPOTDMER = 0x4e00, /*!< Polarity tdm error */
+TFA9872_BF_IPOCLPR = 0x4e20, /*!< Polarity clip right */
+TFA9872_BF_IPOLP0 = 0x4e40, /*!< Polarity low power mode0 */
+TFA9872_BF_IPOLP1 = 0x4e50, /*!< Polarity low power mode1 */
+TFA9872_BF_IPOLA = 0x4e60, /*!< Polarity low noise mode */
+TFA9872_BF_IPOVDDPH = 0x4e70, /*!< Polarity VDDP greater than VBAT */
+TFA9872_BF_BSSCR = 0x5001, /*!< Battery Safeguard attack time */
+TFA9872_BF_BSST = 0x5023, /*!< Battery Safeguard threshold voltage level */
+TFA9872_BF_BSSRL = 0x5061, /*!< Battery Safeguard maximum reduction */
+TFA9872_BF_BSSR = 0x50e0, /*!< Battery voltage read out */
+TFA9872_BF_BSSBY = 0x50f0, /*!< Bypass battery safeguard */
+TFA9872_BF_BSSS = 0x5100, /*!< Vbat prot steepness */
+TFA9872_BF_INTSMUTE = 0x5110, /*!< Soft mute HW */
+TFA9872_BF_HPFBYP = 0x5150, /*!< Bypass HPF */
+TFA9872_BF_DPSA = 0x5170, /*!< Enable DPSA */
+TFA9872_BF_CLIPCTRL = 0x5222, /*!< Clip control setting */
+TFA9872_BF_AMPGAIN = 0x5257, /*!< Amplifier gain */
+TFA9872_BF_SLOPEE = 0x52d0, /*!< Enables slope control */
+TFA9872_BF_SLOPESET = 0x52e0, /*!< Slope speed setting (bin. coded) */
+TFA9872_BF_PGAGAIN = 0x6081, /*!< PGA gain selection */
+TFA9872_BF_PGALPE = 0x60b0, /*!< Lowpass enable */
+TFA9872_BF_LPM0BYP = 0x6110, /*!< bypass low power idle mode */
+TFA9872_BF_TDMDCG = 0x6123, /*!< Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE) */
+TFA9872_BF_TDMSPKG = 0x6163, /*!< Total gain depending on INPLEV setting (channel 0) */
+TFA9872_BF_STIDLEEN = 0x61b0, /*!< enable idle feature for channel 1 */
+TFA9872_BF_LNMODE = 0x62e1, /*!< ctrl select mode */
+TFA9872_BF_LPM1MODE = 0x64e1, /*!< low power mode control */
+TFA9872_BF_LPM1DIS = 0x65c0, /*!< low power mode1 detector control */
+TFA9872_BF_TDMSRCMAP = 0x6801, /*!< tdm source mapping */
+TFA9872_BF_TDMSRCAS = 0x6821, /*!< Sensed value A */
+TFA9872_BF_TDMSRCBS = 0x6841, /*!< Sensed value B */
+TFA9872_BF_ANCSEL = 0x6881, /*!< anc input */
+TFA9872_BF_ANC1C = 0x68a0, /*!< ANC one s complement */
+TFA9872_BF_SAMMODE = 0x6901, /*!< sam enable */
+TFA9872_BF_SAMSEL = 0x6920, /*!< sam source */
+TFA9872_BF_PDMOSELH = 0x6931, /*!< pdm out value when pdm_clk is higth */
+TFA9872_BF_PDMOSELL = 0x6951, /*!< pdm out value when pdm_clk is low */
+TFA9872_BF_SAMOSEL = 0x6970, /*!< ram output on mode sam and audio */
+TFA9872_BF_LP0 = 0x6e00, /*!< low power mode 0 detection */
+TFA9872_BF_LP1 = 0x6e10, /*!< low power mode 1 detection */
+TFA9872_BF_LA = 0x6e20, /*!< low amplitude detection */
+TFA9872_BF_VDDPH = 0x6e30, /*!< vddp greater than vbat */
+TFA9872_BF_DELCURCOMP = 0x6f02, /*!< delay to allign compensation signal with current sense signal */
+TFA9872_BF_SIGCURCOMP = 0x6f40, /*!< polarity of compensation for current sense */
+TFA9872_BF_ENCURCOMP = 0x6f50, /*!< enable current sense compensation */
+TFA9872_BF_SELCLPPWM = 0x6f60, /*!< Select pwm clip flag */
+TFA9872_BF_LVLCLPPWM = 0x6f72, /*!< set the amount of pwm pulse that may be skipped before clip-flag is triggered */
+TFA9872_BF_DCVOS = 0x7002, /*!< Second boost voltage level */
+TFA9872_BF_DCMCC = 0x7033, /*!< Max coil current */
+TFA9872_BF_DCCV = 0x7071, /*!< Slope compensation current, represents LxF (inductance x frequency) value */
+TFA9872_BF_DCIE = 0x7090, /*!< Adaptive boost mode */
+TFA9872_BF_DCSR = 0x70a0, /*!< Soft ramp up/down */
+TFA9872_BF_DCDIS = 0x70e0, /*!< DCDC on/off */
+TFA9872_BF_DCPWM = 0x70f0, /*!< DCDC PWM only mode */
+TFA9872_BF_DCVOF = 0x7402, /*!< 1st boost voltage level */
+TFA9872_BF_DCTRACK = 0x7430, /*!< Boost algorithm selection, effective only when boost_intelligent is set to 1 */
+TFA9872_BF_DCTRIP = 0x7444, /*!< 1st Adaptive boost trip levels, effective only when DCIE is set to 1 */
+TFA9872_BF_DCHOLD = 0x7494, /*!< Hold time for DCDC booster, effective only when boost_intelligent is set to 1 */
+TFA9872_BF_DCTRIP2 = 0x7534, /*!< 2nd Adaptive boost trip levels, effective only when DCIE is set to 1 */
+TFA9872_BF_DCTRIPT = 0x7584, /*!< Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1 */
+TFA9872_BF_MTPK = 0xa107, /*!< MTP KEY2 register */
+TFA9872_BF_KEY1LOCKED = 0xa200, /*!< Indicates KEY1 is locked */
+TFA9872_BF_KEY2LOCKED = 0xa210, /*!< Indicates KEY2 is locked */
+TFA9872_BF_CMTPI = 0xa350, /*!< Start copying all the data from mtp to I2C mtp registers */
+TFA9872_BF_CIMTP = 0xa360, /*!< Start copying data from I2C mtp registers to mtp */
+TFA9872_BF_MTPRDMSB = 0xa50f, /*!< MSB word of MTP manual read data */
+TFA9872_BF_MTPRDLSB = 0xa60f, /*!< LSB word of MTP manual read data */
+TFA9872_BF_EXTTS = 0xb108, /*!< External temperature (C) */
+TFA9872_BF_TROS = 0xb190, /*!< Select temp Speaker calibration */
+TFA9872_BF_SWPROFIL = 0xee0f, /*!< Software profile data */
+TFA9872_BF_SWVSTEP = 0xef0f, /*!< Software vstep information */
+TFA9872_BF_MTPOTC = 0xf000, /*!< Calibration schedule */
+TFA9872_BF_MTPEX = 0xf010, /*!< Calibration Ron executed */
+TFA9872_BF_DCMCCAPI = 0xf020, /*!< Calibration current limit DCDC */
+TFA9872_BF_DCMCCSB = 0xf030, /*!< Sign bit for delta calibration current limit DCDC */
+TFA9872_BF_USERDEF = 0xf042, /*!< Calibration delta current limit DCDC */
+TFA9872_BF_CUSTINFO = 0xf078, /*!< Reserved space for allowing customer to store speaker information */
+TFA9872_BF_R25C = 0xf50f, /*!< Ron resistance of speaker coil */
+} nxpTfa9872BfEnumList_t;
+#define TFA9872_NAMETABLE static tfaBfName_t Tfa9872DatasheetNames[] = {\
+{ 0x0, "PWDN"}, /* Powerdown selection , */\
+{ 0x10, "I2CR"}, /* I2C Reset - Auto clear , */\
+{ 0x30, "AMPE"}, /* Activate Amplifier , */\
+{ 0x40, "DCA"}, /* Activate DC-to-DC converter , */\
+{ 0x71, "INTP"}, /* Interrupt config , */\
+{ 0xb0, "BYPOCP"}, /* Bypass OCP , */\
+{ 0xc0, "TSTOCP"}, /* OCP testing control , */\
+{ 0x120, "MANSCONF"}, /* I2C configured , */\
+{ 0x140, "MANAOOSC"}, /* Internal osc off at PWDN , */\
+{ 0x1d0, "MUTETO"}, /* Time out SB mute sequence , */\
+{ 0x1e0, "RCVNS"}, /* Noise shaper selection , */\
+{ 0x203, "AUDFS"}, /* Sample rate (fs) , */\
+{ 0x240, "INPLEV"}, /* TDM output attenuation , */\
+{ 0x255, "FRACTDEL"}, /* V/I Fractional delay , */\
+{ 0x2b0, "BYPHVBF"}, /* Bypass HVBAT filter , */\
+{ 0x30f, "REV"}, /* Revision info , */\
+{ 0x401, "REFCKEXT"}, /* PLL external ref clock , */\
+{ 0x420, "REFCKSEL"}, /* PLL internal ref clock , */\
+{ 0x510, "SSE"}, /* Enable speaker path , */\
+{ 0x530, "VSE"}, /* Voltage sense , */\
+{ 0x550, "CSE"}, /* Current sense , */\
+{ 0x560, "SSPDME"}, /* Sub-system PDM , */\
+{ 0x580, "PGAE"}, /* Enable PGA chop clock , */\
+{ 0x590, "SSTDME"}, /* Sub-system TDM , */\
+{ 0x5a0, "SSPBSTE"}, /* Sub-system boost , */\
+{ 0x5b0, "SSADCE"}, /* Sub-system ADC , */\
+{ 0x5c0, "SSFAIME"}, /* Sub-system FAIM , */\
+{ 0xd18, "STGAIN"}, /* Side tone gain , */\
+{ 0xda0, "STSMUTE"}, /* Side tone soft mute , */\
+{ 0xdb0, "ST1C"}, /* side tone one s complement , */\
+{ 0x1000, "VDDS"}, /* POR , */\
+{ 0x1010, "PLLS"}, /* PLL lock , */\
+{ 0x1020, "OTDS"}, /* OTP alarm , */\
+{ 0x1030, "OVDS"}, /* OVP alarm , */\
+{ 0x1040, "UVDS"}, /* UVP alarm , */\
+{ 0x1050, "CLKS"}, /* Clocks stable , */\
+{ 0x1060, "MTPB"}, /* MTP busy , */\
+{ 0x1070, "NOCLK"}, /* Lost clock , */\
+{ 0x10a0, "SWS"}, /* Amplifier engage , */\
+{ 0x10c0, "AMPS"}, /* Amplifier enable , */\
+{ 0x10d0, "AREFS"}, /* References enable , */\
+{ 0x10e0, "ADCCR"}, /* Control ADC , */\
+{ 0x1100, "DCIL"}, /* DCDC current limiting , */\
+{ 0x1110, "DCDCA"}, /* DCDC active , */\
+{ 0x1120, "DCOCPOK"}, /* DCDC OCP nmos , */\
+{ 0x1140, "DCHVBAT"}, /* DCDC level 1x , */\
+{ 0x1150, "DCH114"}, /* DCDC level 1.14x , */\
+{ 0x1160, "DCH107"}, /* DCDC level 1.07x , */\
+{ 0x1170, "STMUTEB"}, /* side tone (un)mute busy , */\
+{ 0x1180, "STMUTE"}, /* side tone mute state , */\
+{ 0x1190, "TDMLUTER"}, /* TDM LUT error , */\
+{ 0x11a2, "TDMSTAT"}, /* TDM status bits , */\
+{ 0x11d0, "TDMERR"}, /* TDM error , */\
+{ 0x1300, "OCPOAP"}, /* OCPOK pmos A , */\
+{ 0x1310, "OCPOAN"}, /* OCPOK nmos A , */\
+{ 0x1320, "OCPOBP"}, /* OCPOK pmos B , */\
+{ 0x1330, "OCPOBN"}, /* OCPOK nmos B , */\
+{ 0x1340, "CLIPAH"}, /* Clipping A to Vddp , */\
+{ 0x1350, "CLIPAL"}, /* Clipping A to gnd , */\
+{ 0x1360, "CLIPBH"}, /* Clipping B to Vddp , */\
+{ 0x1370, "CLIPBL"}, /* Clipping B to gnd , */\
+{ 0x1380, "OCDS"}, /* OCP amplifier , */\
+{ 0x1390, "CLIPS"}, /* Amplifier clipping , */\
+{ 0x13a0, "OCPOKMC"}, /* OCPOK MICVDD , */\
+{ 0x13b0, "MANALARM"}, /* Alarm state , */\
+{ 0x13c0, "MANWAIT1"}, /* Wait HW I2C settings , */\
+{ 0x13e0, "MANMUTE"}, /* Audio mute sequence , */\
+{ 0x13f0, "MANOPER"}, /* Operating state , */\
+{ 0x1420, "CLKOOR"}, /* External clock status , */\
+{ 0x1433, "MANSTATE"}, /* Device manager status , */\
+{ 0x1471, "DCMODE"}, /* DCDC mode status bits , */\
+{ 0x1509, "BATS"}, /* Battery voltage (V) , */\
+{ 0x1608, "TEMPS"}, /* IC Temperature (C) , */\
+{ 0x1709, "VDDPS"}, /* IC VDDP voltage ( 1023*VDDP/9.5 V) , */\
+{ 0x2040, "TDME"}, /* Enable interface , */\
+{ 0x2050, "TDMMODE"}, /* Slave/master , */\
+{ 0x2060, "TDMCLINV"}, /* Reception data to BCK clock , */\
+{ 0x2073, "TDMFSLN"}, /* FS length (master mode only) , */\
+{ 0x20b0, "TDMFSPOL"}, /* FS polarity , */\
+{ 0x20c3, "TDMNBCK"}, /* N-BCK's in FS , */\
+{ 0x2103, "TDMSLOTS"}, /* N-slots in Frame , */\
+{ 0x2144, "TDMSLLN"}, /* N-bits in slot , */\
+{ 0x2194, "TDMBRMG"}, /* N-bits remaining , */\
+{ 0x21e0, "TDMDEL"}, /* data delay to FS , */\
+{ 0x21f0, "TDMADJ"}, /* data adjustment , */\
+{ 0x2201, "TDMOOMP"}, /* Received audio compression , */\
+{ 0x2224, "TDMSSIZE"}, /* Sample size per slot , */\
+{ 0x2271, "TDMTXDFO"}, /* Format unused bits , */\
+{ 0x2291, "TDMTXUS0"}, /* Format unused slots DATAO , */\
+{ 0x2300, "TDMSPKE"}, /* Control audio tdm channel in 0 (spkr + dcdc) , */\
+{ 0x2310, "TDMDCE"}, /* Control audio tdm channel in 1 (dcdc) , */\
+{ 0x2330, "TDMCSE"}, /* current sense vbat temperature and vddp feedback , */\
+{ 0x2340, "TDMVSE"}, /* Voltage sense vbat temperature and vddp feedback , */\
+{ 0x2603, "TDMSPKS"}, /* tdm slot for sink 0 (speaker + dcdc) , */\
+{ 0x2643, "TDMDCS"}, /* tdm slot for sink 1 (dcdc) , */\
+{ 0x26c3, "TDMCSS"}, /* Slot Position of current sense vbat temperature and vddp feedback, */\
+{ 0x2703, "TDMVSS"}, /* Slot Position of Voltage sense vbat temperature and vddp feedback, */\
+{ 0x3111, "PDMSTSEL"}, /* Side tone input , */\
+{ 0x4000, "ISTVDDS"}, /* Status POR , */\
+{ 0x4010, "ISTPLLS"}, /* Status PLL lock , */\
+{ 0x4020, "ISTOTDS"}, /* Status OTP alarm , */\
+{ 0x4030, "ISTOVDS"}, /* Status OVP alarm , */\
+{ 0x4040, "ISTUVDS"}, /* Status UVP alarm , */\
+{ 0x4050, "ISTCLKS"}, /* Status clocks stable , */\
+{ 0x4060, "ISTMTPB"}, /* Status MTP busy , */\
+{ 0x4070, "ISTNOCLK"}, /* Status lost clock , */\
+{ 0x40a0, "ISTSWS"}, /* Status amplifier engage , */\
+{ 0x40c0, "ISTAMPS"}, /* Status amplifier enable , */\
+{ 0x40d0, "ISTAREFS"}, /* Status Ref enable , */\
+{ 0x40e0, "ISTADCCR"}, /* Status Control ADC , */\
+{ 0x4100, "ISTBSTCU"}, /* Status DCDC current limiting , */\
+{ 0x4110, "ISTBSTHI"}, /* Status DCDC active , */\
+{ 0x4120, "ISTBSTOC"}, /* Status DCDC OCP , */\
+{ 0x4130, "ISTBSTPKCUR"}, /* Status bst peakcur , */\
+{ 0x4140, "ISTBSTVC"}, /* Status DCDC level 1x , */\
+{ 0x4150, "ISTBST86"}, /* Status DCDC level 1.14x , */\
+{ 0x4160, "ISTBST93"}, /* Status DCDC level 1.07x , */\
+{ 0x4190, "ISTOCPR"}, /* Status ocp alarm , */\
+{ 0x41a0, "ISTMWSRC"}, /* Status Waits HW I2C settings , */\
+{ 0x41c0, "ISTMWSMU"}, /* Status Audio mute sequence , */\
+{ 0x41f0, "ISTCLKOOR"}, /* Status flag_clk_out_of_range , */\
+{ 0x4200, "ISTTDMER"}, /* Status tdm error , */\
+{ 0x4220, "ISTCLPR"}, /* Status clip , */\
+{ 0x4240, "ISTLP0"}, /* Status low power mode0 , */\
+{ 0x4250, "ISTLP1"}, /* Status low power mode1 , */\
+{ 0x4260, "ISTLA"}, /* Status low noise detection , */\
+{ 0x4270, "ISTVDDPH"}, /* Status VDDP greater than VBAT , */\
+{ 0x4400, "ICLVDDS"}, /* Clear POR , */\
+{ 0x4410, "ICLPLLS"}, /* Clear PLL lock , */\
+{ 0x4420, "ICLOTDS"}, /* Clear OTP alarm , */\
+{ 0x4430, "ICLOVDS"}, /* Clear OVP alarm , */\
+{ 0x4440, "ICLUVDS"}, /* Clear UVP alarm , */\
+{ 0x4450, "ICLCLKS"}, /* Clear clocks stable , */\
+{ 0x4460, "ICLMTPB"}, /* Clear mtp busy , */\
+{ 0x4470, "ICLNOCLK"}, /* Clear lost clk , */\
+{ 0x44a0, "ICLSWS"}, /* Clear amplifier engage , */\
+{ 0x44c0, "ICLAMPS"}, /* Clear enbl amp , */\
+{ 0x44d0, "ICLAREFS"}, /* Clear ref enable , */\
+{ 0x44e0, "ICLADCCR"}, /* Clear control ADC , */\
+{ 0x4500, "ICLBSTCU"}, /* Clear DCDC current limiting , */\
+{ 0x4510, "ICLBSTHI"}, /* Clear DCDC active , */\
+{ 0x4520, "ICLBSTOC"}, /* Clear DCDC OCP , */\
+{ 0x4530, "ICLBSTPC"}, /* Clear bst peakcur , */\
+{ 0x4540, "ICLBSTVC"}, /* Clear DCDC level 1x , */\
+{ 0x4550, "ICLBST86"}, /* Clear DCDC level 1.14x , */\
+{ 0x4560, "ICLBST93"}, /* Clear DCDC level 1.07x , */\
+{ 0x4590, "ICLOCPR"}, /* Clear ocp alarm , */\
+{ 0x45a0, "ICLMWSRC"}, /* Clear wait HW I2C settings , */\
+{ 0x45c0, "ICLMWSMU"}, /* Clear audio mute sequence , */\
+{ 0x45f0, "ICLCLKOOR"}, /* Clear flag_clk_out_of_range , */\
+{ 0x4600, "ICLTDMER"}, /* Clear tdm error , */\
+{ 0x4620, "ICLCLPR"}, /* Clear clip , */\
+{ 0x4640, "ICLLP0"}, /* Clear low power mode0 , */\
+{ 0x4650, "ICLLP1"}, /* Clear low power mode1 , */\
+{ 0x4660, "ICLLA"}, /* Clear low noise detection , */\
+{ 0x4670, "ICLVDDPH"}, /* Clear VDDP greater then VBAT , */\
+{ 0x4800, "IEVDDS"}, /* Enable por , */\
+{ 0x4810, "IEPLLS"}, /* Enable pll lock , */\
+{ 0x4820, "IEOTDS"}, /* Enable OTP alarm , */\
+{ 0x4830, "IEOVDS"}, /* Enable OVP alarm , */\
+{ 0x4840, "IEUVDS"}, /* Enable UVP alarm , */\
+{ 0x4850, "IECLKS"}, /* Enable clocks stable , */\
+{ 0x4860, "IEMTPB"}, /* Enable mtp busy , */\
+{ 0x4870, "IENOCLK"}, /* Enable lost clk , */\
+{ 0x48a0, "IESWS"}, /* Enable amplifier engage , */\
+{ 0x48c0, "IEAMPS"}, /* Enable enbl amp , */\
+{ 0x48d0, "IEAREFS"}, /* Enable ref enable , */\
+{ 0x48e0, "IEADCCR"}, /* Enable Control ADC , */\
+{ 0x4900, "IEBSTCU"}, /* Enable DCDC current limiting , */\
+{ 0x4910, "IEBSTHI"}, /* Enable DCDC active , */\
+{ 0x4920, "IEBSTOC"}, /* Enable DCDC OCP , */\
+{ 0x4930, "IEBSTPC"}, /* Enable bst peakcur , */\
+{ 0x4940, "IEBSTVC"}, /* Enable DCDC level 1x , */\
+{ 0x4950, "IEBST86"}, /* Enable DCDC level 1.14x , */\
+{ 0x4960, "IEBST93"}, /* Enable DCDC level 1.07x , */\
+{ 0x4990, "IEOCPR"}, /* Enable ocp alarm , */\
+{ 0x49a0, "IEMWSRC"}, /* Enable waits HW I2C settings , */\
+{ 0x49c0, "IEMWSMU"}, /* Enable man Audio mute sequence , */\
+{ 0x49f0, "IECLKOOR"}, /* Enable flag_clk_out_of_range , */\
+{ 0x4a00, "IETDMER"}, /* Enable tdm error , */\
+{ 0x4a20, "IECLPR"}, /* Enable clip , */\
+{ 0x4a40, "IELP0"}, /* Enable low power mode0 , */\
+{ 0x4a50, "IELP1"}, /* Enable low power mode1 , */\
+{ 0x4a60, "IELA"}, /* Enable low noise detection , */\
+{ 0x4a70, "IEVDDPH"}, /* Enable VDDP greater tehn VBAT , */\
+{ 0x4c00, "IPOVDDS"}, /* Polarity por , */\
+{ 0x4c10, "IPOPLLS"}, /* Polarity pll lock , */\
+{ 0x4c20, "IPOOTDS"}, /* Polarity OTP alarm , */\
+{ 0x4c30, "IPOOVDS"}, /* Polarity OVP alarm , */\
+{ 0x4c40, "IPOUVDS"}, /* Polarity UVP alarm , */\
+{ 0x4c50, "IPOCLKS"}, /* Polarity clocks stable , */\
+{ 0x4c60, "IPOMTPB"}, /* Polarity mtp busy , */\
+{ 0x4c70, "IPONOCLK"}, /* Polarity lost clk , */\
+{ 0x4ca0, "IPOSWS"}, /* Polarity amplifier engage , */\
+{ 0x4cc0, "IPOAMPS"}, /* Polarity enbl amp , */\
+{ 0x4cd0, "IPOAREFS"}, /* Polarity ref enable , */\
+{ 0x4ce0, "IPOADCCR"}, /* Polarity Control ADC , */\
+{ 0x4d00, "IPOBSTCU"}, /* Polarity DCDC current limiting , */\
+{ 0x4d10, "IPOBSTHI"}, /* Polarity DCDC active , */\
+{ 0x4d20, "IPOBSTOC"}, /* Polarity DCDC OCP , */\
+{ 0x4d30, "IPOBSTPC"}, /* Polarity bst peakcur , */\
+{ 0x4d40, "IPOBSTVC"}, /* Polarity DCDC level 1x , */\
+{ 0x4d50, "IPOBST86"}, /* Polarity DCDC level 1.14x , */\
+{ 0x4d60, "IPOBST93"}, /* Polarity DCDC level 1.07x , */\
+{ 0x4d90, "IPOOCPR"}, /* Polarity ocp alarm , */\
+{ 0x4da0, "IPOMWSRC"}, /* Polarity waits HW I2C settings , */\
+{ 0x4dc0, "IPOMWSMU"}, /* Polarity man audio mute sequence , */\
+{ 0x4df0, "IPCLKOOR"}, /* Polarity flag_clk_out_of_range , */\
+{ 0x4e00, "IPOTDMER"}, /* Polarity tdm error , */\
+{ 0x4e20, "IPOCLPR"}, /* Polarity clip right , */\
+{ 0x4e40, "IPOLP0"}, /* Polarity low power mode0 , */\
+{ 0x4e50, "IPOLP1"}, /* Polarity low power mode1 , */\
+{ 0x4e60, "IPOLA"}, /* Polarity low noise mode , */\
+{ 0x4e70, "IPOVDDPH"}, /* Polarity VDDP greater than VBAT , */\
+{ 0x5001, "BSSCR"}, /* Battery Safeguard attack time , */\
+{ 0x5023, "BSST"}, /* Battery Safeguard threshold voltage level , */\
+{ 0x5061, "BSSRL"}, /* Battery Safeguard maximum reduction , */\
+{ 0x50e0, "BSSR"}, /* Battery voltage read out , */\
+{ 0x50f0, "BSSBY"}, /* Bypass battery safeguard , */\
+{ 0x5100, "BSSS"}, /* Vbat prot steepness , */\
+{ 0x5110, "INTSMUTE"}, /* Soft mute HW , */\
+{ 0x5150, "HPFBYP"}, /* Bypass HPF , */\
+{ 0x5170, "DPSA"}, /* Enable DPSA , */\
+{ 0x5222, "CLIPCTRL"}, /* Clip control setting , */\
+{ 0x5257, "AMPGAIN"}, /* Amplifier gain , */\
+{ 0x52d0, "SLOPEE"}, /* Enables slope control , */\
+{ 0x52e0, "SLOPESET"}, /* Slope speed setting (bin. coded) , */\
+{ 0x6081, "PGAGAIN"}, /* PGA gain selection , */\
+{ 0x60b0, "PGALPE"}, /* Lowpass enable , */\
+{ 0x6110, "LPM0BYP"}, /* bypass low power idle mode , */\
+{ 0x6123, "TDMDCG"}, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */\
+{ 0x6163, "TDMSPKG"}, /* Total gain depending on INPLEV setting (channel 0), */\
+{ 0x61b0, "STIDLEEN"}, /* enable idle feature for channel 1 , */\
+{ 0x62e1, "LNMODE"}, /* ctrl select mode , */\
+{ 0x64e1, "LPM1MODE"}, /* low power mode control , */\
+{ 0x65c0, "LPM1DIS"}, /* low power mode1 detector control , */\
+{ 0x6801, "TDMSRCMAP"}, /* tdm source mapping , */\
+{ 0x6821, "TDMSRCAS"}, /* Sensed value A , */\
+{ 0x6841, "TDMSRCBS"}, /* Sensed value B , */\
+{ 0x6881, "ANCSEL"}, /* anc input , */\
+{ 0x68a0, "ANC1C"}, /* ANC one s complement , */\
+{ 0x6901, "SAMMODE"}, /* sam enable , */\
+{ 0x6920, "SAMSEL"}, /* sam source , */\
+{ 0x6931, "PDMOSELH"}, /* pdm out value when pdm_clk is higth , */\
+{ 0x6951, "PDMOSELL"}, /* pdm out value when pdm_clk is low , */\
+{ 0x6970, "SAMOSEL"}, /* ram output on mode sam and audio , */\
+{ 0x6e00, "LP0"}, /* low power mode 0 detection , */\
+{ 0x6e10, "LP1"}, /* low power mode 1 detection , */\
+{ 0x6e20, "LA"}, /* low amplitude detection , */\
+{ 0x6e30, "VDDPH"}, /* vddp greater than vbat , */\
+{ 0x6f02, "DELCURCOMP"}, /* delay to allign compensation signal with current sense signal, */\
+{ 0x6f40, "SIGCURCOMP"}, /* polarity of compensation for current sense , */\
+{ 0x6f50, "ENCURCOMP"}, /* enable current sense compensation , */\
+{ 0x6f60, "SELCLPPWM"}, /* Select pwm clip flag , */\
+{ 0x6f72, "LVLCLPPWM"}, /* set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
+{ 0x7002, "DCVOS"}, /* Second boost voltage level , */\
+{ 0x7033, "DCMCC"}, /* Max coil current , */\
+{ 0x7071, "DCCV"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
+{ 0x7090, "DCIE"}, /* Adaptive boost mode , */\
+{ 0x70a0, "DCSR"}, /* Soft ramp up/down , */\
+{ 0x70e0, "DCDIS"}, /* DCDC on/off , */\
+{ 0x70f0, "DCPWM"}, /* DCDC PWM only mode , */\
+{ 0x7402, "DCVOF"}, /* 1st boost voltage level , */\
+{ 0x7430, "DCTRACK"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
+{ 0x7444, "DCTRIP"}, /* 1st Adaptive boost trip levels, effective only when DCIE is set to 1, */\
+{ 0x7494, "DCHOLD"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
+{ 0x7534, "DCTRIP2"}, /* 2nd Adaptive boost trip levels, effective only when DCIE is set to 1, */\
+{ 0x7584, "DCTRIPT"}, /* Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
+{ 0xa107, "MTPK"}, /* MTP KEY2 register , */\
+{ 0xa200, "KEY1LOCKED"}, /* Indicates KEY1 is locked , */\
+{ 0xa210, "KEY2LOCKED"}, /* Indicates KEY2 is locked , */\
+{ 0xa350, "CMTPI"}, /* Start copying all the data from mtp to I2C mtp registers, */\
+{ 0xa360, "CIMTP"}, /* Start copying data from I2C mtp registers to mtp , */\
+{ 0xa50f, "MTPRDMSB"}, /* MSB word of MTP manual read data , */\
+{ 0xa60f, "MTPRDLSB"}, /* LSB word of MTP manual read data , */\
+{ 0xb108, "EXTTS"}, /* External temperature (C) , */\
+{ 0xb190, "TROS"}, /* Select temp Speaker calibration , */\
+{ 0xee0f, "SWPROFIL"}, /* Software profile data , */\
+{ 0xef0f, "SWVSTEP"}, /* Software vstep information , */\
+{ 0xf000, "MTPOTC"}, /* Calibration schedule , */\
+{ 0xf010, "MTPEX"}, /* Calibration Ron executed , */\
+{ 0xf020, "DCMCCAPI"}, /* Calibration current limit DCDC , */\
+{ 0xf030, "DCMCCSB"}, /* Sign bit for delta calibration current limit DCDC , */\
+{ 0xf042, "USERDEF"}, /* Calibration delta current limit DCDC , */\
+{ 0xf078, "CUSTINFO"}, /* Reserved space for allowing customer to store speaker information, */\
+{ 0xf50f, "R25C"}, /* Ron resistance of speaker coil , */\
+{ 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+
+#define TFA9872_BITNAMETABLE static tfaBfName_t Tfa9872BitNames[] = {\
+{ 0x0, "powerdown"}, /* Powerdown selection , */\
+{ 0x10, "reset"}, /* I2C Reset - Auto clear , */\
+{ 0x30, "enbl_amplifier"}, /* Activate Amplifier , */\
+{ 0x40, "enbl_boost"}, /* Activate DC-to-DC converter , */\
+{ 0x71, "int_pad_io"}, /* Interrupt config , */\
+{ 0xb0, "bypass_ocp"}, /* Bypass OCP , */\
+{ 0xc0, "test_ocp"}, /* OCP testing control , */\
+{ 0x120, "src_set_configured"}, /* I2C configured , */\
+{ 0x140, "enbl_osc1m_auto_off"}, /* Internal osc off at PWDN , */\
+{ 0x1d0, "disable_mute_time_out"}, /* Time out SB mute sequence , */\
+{ 0x203, "audio_fs"}, /* Sample rate (fs) , */\
+{ 0x240, "input_level"}, /* TDM output attenuation , */\
+{ 0x255, "cs_frac_delay"}, /* V/I Fractional delay , */\
+{ 0x2b0, "bypass_hvbat_filter"}, /* Bypass HVBAT filter , */\
+{ 0x2d0, "sel_hysteresis"}, /* Select hysteresis for clock range detector , */\
+{ 0x30f, "device_rev"}, /* Revision info , */\
+{ 0x401, "pll_clkin_sel"}, /* PLL external ref clock , */\
+{ 0x420, "pll_clkin_sel_osc"}, /* PLL internal ref clock , */\
+{ 0x510, "enbl_spkr_ss"}, /* Enable speaker path , */\
+{ 0x530, "enbl_volsense"}, /* Voltage sense , */\
+{ 0x550, "enbl_cursense"}, /* Current sense , */\
+{ 0x560, "enbl_pdm_ss"}, /* Sub-system PDM , */\
+{ 0x580, "enbl_pga_chop"}, /* Enable PGA chop clock , */\
+{ 0x590, "enbl_tdm_ss"}, /* Sub-system TDM , */\
+{ 0x5a0, "enbl_bst_ss"}, /* Sub-system boost , */\
+{ 0x5b0, "enbl_adc_ss"}, /* Sub-system ADC , */\
+{ 0x5c0, "enbl_faim_ss"}, /* Sub-system FAIM , */\
+{ 0xd18, "side_tone_gain"}, /* Side tone gain , */\
+{ 0xda0, "mute_side_tone"}, /* Side tone soft mute , */\
+{ 0xdb0, "side_tone_1scomplement"}, /* side tone one s complement , */\
+{ 0xe07, "ctrl_digtoana"}, /* Spare control from digital to analog , */\
+{ 0xf0f, "hidden_code"}, /* 5A6Bh, 23147d to access registers (default for engineering), */\
+{ 0x1000, "flag_por"}, /* POR , */\
+{ 0x1010, "flag_pll_lock"}, /* PLL lock , */\
+{ 0x1020, "flag_otpok"}, /* OTP alarm , */\
+{ 0x1030, "flag_ovpok"}, /* OVP alarm , */\
+{ 0x1040, "flag_uvpok"}, /* UVP alarm , */\
+{ 0x1050, "flag_clocks_stable"}, /* Clocks stable , */\
+{ 0x1060, "flag_mtp_busy"}, /* MTP busy , */\
+{ 0x1070, "flag_lost_clk"}, /* Lost clock , */\
+{ 0x10a0, "flag_engage"}, /* Amplifier engage , */\
+{ 0x10c0, "flag_enbl_amp"}, /* Amplifier enable , */\
+{ 0x10d0, "flag_enbl_ref"}, /* References enable , */\
+{ 0x10e0, "flag_adc10_ready"}, /* Control ADC , */\
+{ 0x1100, "flag_bst_bstcur"}, /* DCDC current limiting , */\
+{ 0x1110, "flag_bst_hiz"}, /* DCDC active , */\
+{ 0x1120, "flag_bst_ocpok"}, /* DCDC OCP nmos , */\
+{ 0x1130, "flag_bst_peakcur"}, /* Indicates current is max in DC-to-DC converter , */\
+{ 0x1140, "flag_bst_voutcomp"}, /* DCDC level 1x , */\
+{ 0x1150, "flag_bst_voutcomp86"}, /* DCDC level 1.14x , */\
+{ 0x1160, "flag_bst_voutcomp93"}, /* DCDC level 1.07x , */\
+{ 0x1170, "flag_soft_mute_busy"}, /* side tone (un)mute busy , */\
+{ 0x1180, "flag_soft_mute_state"}, /* side tone mute state , */\
+{ 0x1190, "flag_tdm_lut_error"}, /* TDM LUT error , */\
+{ 0x11a2, "flag_tdm_status"}, /* TDM status bits , */\
+{ 0x11d0, "flag_tdm_error"}, /* TDM error , */\
+{ 0x1300, "flag_ocpokap"}, /* OCPOK pmos A , */\
+{ 0x1310, "flag_ocpokan"}, /* OCPOK nmos A , */\
+{ 0x1320, "flag_ocpokbp"}, /* OCPOK pmos B , */\
+{ 0x1330, "flag_ocpokbn"}, /* OCPOK nmos B , */\
+{ 0x1340, "flag_clipa_high"}, /* Clipping A to Vddp , */\
+{ 0x1350, "flag_clipa_low"}, /* Clipping A to gnd , */\
+{ 0x1360, "flag_clipb_high"}, /* Clipping B to Vddp , */\
+{ 0x1370, "flag_clipb_low"}, /* Clipping B to gnd , */\
+{ 0x1380, "flag_ocp_alarm"}, /* OCP amplifier , */\
+{ 0x1390, "flag_clip"}, /* Amplifier clipping , */\
+{ 0x13b0, "flag_man_alarm_state"}, /* Alarm state , */\
+{ 0x13c0, "flag_man_wait_src_settings"}, /* Wait HW I2C settings , */\
+{ 0x13e0, "flag_man_start_mute_audio"}, /* Audio mute sequence , */\
+{ 0x13f0, "flag_man_operating_state"}, /* Operating state , */\
+{ 0x1420, "flag_clk_out_of_range"}, /* External clock status , */\
+{ 0x1433, "man_state"}, /* Device manager status , */\
+{ 0x1471, "status_bst_mode"}, /* DCDC mode status bits , */\
+{ 0x1509, "bat_adc"}, /* Battery voltage (V) , */\
+{ 0x1608, "temp_adc"}, /* IC Temperature (C) , */\
+{ 0x1709, "vddp_adc"}, /* IC VDDP voltage ( 1023*VDDP/9.5 V) , */\
+{ 0x2040, "tdm_enable"}, /* Enable interface , */\
+{ 0x2050, "tdm_mode"}, /* Slave/master , */\
+{ 0x2060, "tdm_clk_inversion"}, /* Reception data to BCK clock , */\
+{ 0x2073, "tdm_fs_ws_length"}, /* FS length (master mode only) , */\
+{ 0x20b0, "tdm_fs_ws_polarity"}, /* FS polarity , */\
+{ 0x20c3, "tdm_nbck"}, /* N-BCK's in FS , */\
+{ 0x2103, "tdm_nb_of_slots"}, /* N-slots in Frame , */\
+{ 0x2144, "tdm_slot_length"}, /* N-bits in slot , */\
+{ 0x2194, "tdm_bits_remaining"}, /* N-bits remaining , */\
+{ 0x21e0, "tdm_data_delay"}, /* data delay to FS , */\
+{ 0x21f0, "tdm_data_adjustment"}, /* data adjustment , */\
+{ 0x2201, "tdm_audio_sample_compression"}, /* Received audio compression , */\
+{ 0x2224, "tdm_sample_size"}, /* Sample size per slot , */\
+{ 0x2271, "tdm_txdata_format"}, /* Format unused bits , */\
+{ 0x2291, "tdm_txdata_format_unused_slot_sd0"}, /* Format unused slots DATAO , */\
+{ 0x2300, "tdm_sink0_enable"}, /* Control audio tdm channel in 0 (spkr + dcdc) , */\
+{ 0x2310, "tdm_sink1_enable"}, /* Control audio tdm channel in 1 (dcdc) , */\
+{ 0x2330, "tdm_source0_enable"}, /* current sense vbat temperature and vddp feedback , */\
+{ 0x2340, "tdm_source1_enable"}, /* Voltage sense vbat temperature and vddp feedback , */\
+{ 0x2603, "tdm_sink0_slot"}, /* tdm slot for sink 0 (speaker + dcdc) , */\
+{ 0x2643, "tdm_sink1_slot"}, /* tdm slot for sink 1 (dcdc) , */\
+{ 0x26c3, "tdm_source0_slot"}, /* Slot Position of current sense vbat temperature and vddp feedback, */\
+{ 0x2703, "tdm_source1_slot"}, /* Slot Position of Voltage sense vbat temperature and vddp feedback, */\
+{ 0x3111, "pdm_side_tone_sel"}, /* Side tone input , */\
+{ 0x3201, "pdm_nbck"}, /* PDM BCK/Fs ratio , */\
+{ 0x4000, "int_out_flag_por"}, /* Status POR , */\
+{ 0x4010, "int_out_flag_pll_lock"}, /* Status PLL lock , */\
+{ 0x4020, "int_out_flag_otpok"}, /* Status OTP alarm , */\
+{ 0x4030, "int_out_flag_ovpok"}, /* Status OVP alarm , */\
+{ 0x4040, "int_out_flag_uvpok"}, /* Status UVP alarm , */\
+{ 0x4050, "int_out_flag_clocks_stable"}, /* Status clocks stable , */\
+{ 0x4060, "int_out_flag_mtp_busy"}, /* Status MTP busy , */\
+{ 0x4070, "int_out_flag_lost_clk"}, /* Status lost clock , */\
+{ 0x40a0, "int_out_flag_engage"}, /* Status amplifier engage , */\
+{ 0x40c0, "int_out_flag_enbl_amp"}, /* Status amplifier enable , */\
+{ 0x40d0, "int_out_flag_enbl_ref"}, /* Status Ref enable , */\
+{ 0x40e0, "int_out_flag_adc10_ready"}, /* Status Control ADC , */\
+{ 0x4100, "int_out_flag_bst_bstcur"}, /* Status DCDC current limiting , */\
+{ 0x4110, "int_out_flag_bst_hiz"}, /* Status DCDC active , */\
+{ 0x4120, "int_out_flag_bst_ocpok"}, /* Status DCDC OCP , */\
+{ 0x4130, "int_out_flag_bst_peakcur"}, /* Status bst peakcur , */\
+{ 0x4140, "int_out_flag_bst_voutcomp"}, /* Status DCDC level 1x , */\
+{ 0x4150, "int_out_flag_bst_voutcomp86"}, /* Status DCDC level 1.14x , */\
+{ 0x4160, "int_out_flag_bst_voutcomp93"}, /* Status DCDC level 1.07x , */\
+{ 0x4190, "int_out_flag_ocp_alarm"}, /* Status ocp alarm , */\
+{ 0x41a0, "int_out_flag_man_wait_src_settings"}, /* Status Waits HW I2C settings , */\
+{ 0x41c0, "int_out_flag_man_start_mute_audio"}, /* Status Audio mute sequence , */\
+{ 0x41f0, "int_out_flag_clk_out_of_range"}, /* Status flag_clk_out_of_range , */\
+{ 0x4200, "int_out_flag_tdm_error"}, /* Status tdm error , */\
+{ 0x4220, "int_out_flag_clip"}, /* Status clip , */\
+{ 0x4240, "int_out_flag_lp_detect_mode0"}, /* Status low power mode0 , */\
+{ 0x4250, "int_out_flag_lp_detect_mode1"}, /* Status low power mode1 , */\
+{ 0x4260, "int_out_flag_low_amplitude"}, /* Status low noise detection , */\
+{ 0x4270, "int_out_flag_vddp_gt_vbat"}, /* Status VDDP greater than VBAT , */\
+{ 0x4400, "int_in_flag_por"}, /* Clear POR , */\
+{ 0x4410, "int_in_flag_pll_lock"}, /* Clear PLL lock , */\
+{ 0x4420, "int_in_flag_otpok"}, /* Clear OTP alarm , */\
+{ 0x4430, "int_in_flag_ovpok"}, /* Clear OVP alarm , */\
+{ 0x4440, "int_in_flag_uvpok"}, /* Clear UVP alarm , */\
+{ 0x4450, "int_in_flag_clocks_stable"}, /* Clear clocks stable , */\
+{ 0x4460, "int_in_flag_mtp_busy"}, /* Clear mtp busy , */\
+{ 0x4470, "int_in_flag_lost_clk"}, /* Clear lost clk , */\
+{ 0x44a0, "int_in_flag_engage"}, /* Clear amplifier engage , */\
+{ 0x44c0, "int_in_flag_enbl_amp"}, /* Clear enbl amp , */\
+{ 0x44d0, "int_in_flag_enbl_ref"}, /* Clear ref enable , */\
+{ 0x44e0, "int_in_flag_adc10_ready"}, /* Clear control ADC , */\
+{ 0x4500, "int_in_flag_bst_bstcur"}, /* Clear DCDC current limiting , */\
+{ 0x4510, "int_in_flag_bst_hiz"}, /* Clear DCDC active , */\
+{ 0x4520, "int_in_flag_bst_ocpok"}, /* Clear DCDC OCP , */\
+{ 0x4530, "int_in_flag_bst_peakcur"}, /* Clear bst peakcur , */\
+{ 0x4540, "int_in_flag_bst_voutcomp"}, /* Clear DCDC level 1x , */\
+{ 0x4550, "int_in_flag_bst_voutcomp86"}, /* Clear DCDC level 1.14x , */\
+{ 0x4560, "int_in_flag_bst_voutcomp93"}, /* Clear DCDC level 1.07x , */\
+{ 0x4590, "int_in_flag_ocp_alarm"}, /* Clear ocp alarm , */\
+{ 0x45a0, "int_in_flag_man_wait_src_settings"}, /* Clear wait HW I2C settings , */\
+{ 0x45c0, "int_in_flag_man_start_mute_audio"}, /* Clear audio mute sequence , */\
+{ 0x45f0, "int_in_flag_clk_out_of_range"}, /* Clear flag_clk_out_of_range , */\
+{ 0x4600, "int_in_flag_tdm_error"}, /* Clear tdm error , */\
+{ 0x4620, "int_in_flag_clip"}, /* Clear clip , */\
+{ 0x4640, "int_in_flag_lp_detect_mode0"}, /* Clear low power mode0 , */\
+{ 0x4650, "int_in_flag_lp_detect_mode1"}, /* Clear low power mode1 , */\
+{ 0x4660, "int_in_flag_low_amplitude"}, /* Clear low noise detection , */\
+{ 0x4670, "int_in_flag_vddp_gt_vbat"}, /* Clear VDDP greater then VBAT , */\
+{ 0x4800, "int_enable_flag_por"}, /* Enable por , */\
+{ 0x4810, "int_enable_flag_pll_lock"}, /* Enable pll lock , */\
+{ 0x4820, "int_enable_flag_otpok"}, /* Enable OTP alarm , */\
+{ 0x4830, "int_enable_flag_ovpok"}, /* Enable OVP alarm , */\
+{ 0x4840, "int_enable_flag_uvpok"}, /* Enable UVP alarm , */\
+{ 0x4850, "int_enable_flag_clocks_stable"}, /* Enable clocks stable , */\
+{ 0x4860, "int_enable_flag_mtp_busy"}, /* Enable mtp busy , */\
+{ 0x4870, "int_enable_flag_lost_clk"}, /* Enable lost clk , */\
+{ 0x48a0, "int_enable_flag_engage"}, /* Enable amplifier engage , */\
+{ 0x48c0, "int_enable_flag_enbl_amp"}, /* Enable enbl amp , */\
+{ 0x48d0, "int_enable_flag_enbl_ref"}, /* Enable ref enable , */\
+{ 0x48e0, "int_enable_flag_adc10_ready"}, /* Enable Control ADC , */\
+{ 0x4900, "int_enable_flag_bst_bstcur"}, /* Enable DCDC current limiting , */\
+{ 0x4910, "int_enable_flag_bst_hiz"}, /* Enable DCDC active , */\
+{ 0x4920, "int_enable_flag_bst_ocpok"}, /* Enable DCDC OCP , */\
+{ 0x4930, "int_enable_flag_bst_peakcur"}, /* Enable bst peakcur , */\
+{ 0x4940, "int_enable_flag_bst_voutcomp"}, /* Enable DCDC level 1x , */\
+{ 0x4950, "int_enable_flag_bst_voutcomp86"}, /* Enable DCDC level 1.14x , */\
+{ 0x4960, "int_enable_flag_bst_voutcomp93"}, /* Enable DCDC level 1.07x , */\
+{ 0x4990, "int_enable_flag_ocp_alarm"}, /* Enable ocp alarm , */\
+{ 0x49a0, "int_enable_flag_man_wait_src_settings"}, /* Enable waits HW I2C settings , */\
+{ 0x49c0, "int_enable_flag_man_start_mute_audio"}, /* Enable man Audio mute sequence , */\
+{ 0x49f0, "int_enable_flag_clk_out_of_range"}, /* Enable flag_clk_out_of_range , */\
+{ 0x4a00, "int_enable_flag_tdm_error"}, /* Enable tdm error , */\
+{ 0x4a20, "int_enable_flag_clip"}, /* Enable clip , */\
+{ 0x4a40, "int_enable_flag_lp_detect_mode0"}, /* Enable low power mode0 , */\
+{ 0x4a50, "int_enable_flag_lp_detect_mode1"}, /* Enable low power mode1 , */\
+{ 0x4a60, "int_enable_flag_low_amplitude"}, /* Enable low noise detection , */\
+{ 0x4a70, "int_enable_flag_vddp_gt_vbat"}, /* Enable VDDP greater tehn VBAT , */\
+{ 0x4c00, "int_polarity_flag_por"}, /* Polarity por , */\
+{ 0x4c10, "int_polarity_flag_pll_lock"}, /* Polarity pll lock , */\
+{ 0x4c20, "int_polarity_flag_otpok"}, /* Polarity OTP alarm , */\
+{ 0x4c30, "int_polarity_flag_ovpok"}, /* Polarity OVP alarm , */\
+{ 0x4c40, "int_polarity_flag_uvpok"}, /* Polarity UVP alarm , */\
+{ 0x4c50, "int_polarity_flag_clocks_stable"}, /* Polarity clocks stable , */\
+{ 0x4c60, "int_polarity_flag_mtp_busy"}, /* Polarity mtp busy , */\
+{ 0x4c70, "int_polarity_flag_lost_clk"}, /* Polarity lost clk , */\
+{ 0x4ca0, "int_polarity_flag_engage"}, /* Polarity amplifier engage , */\
+{ 0x4cc0, "int_polarity_flag_enbl_amp"}, /* Polarity enbl amp , */\
+{ 0x4cd0, "int_polarity_flag_enbl_ref"}, /* Polarity ref enable , */\
+{ 0x4ce0, "int_polarity_flag_adc10_ready"}, /* Polarity Control ADC , */\
+{ 0x4d00, "int_polarity_flag_bst_bstcur"}, /* Polarity DCDC current limiting , */\
+{ 0x4d10, "int_polarity_flag_bst_hiz"}, /* Polarity DCDC active , */\
+{ 0x4d20, "int_polarity_flag_bst_ocpok"}, /* Polarity DCDC OCP , */\
+{ 0x4d30, "int_polarity_flag_bst_peakcur"}, /* Polarity bst peakcur , */\
+{ 0x4d40, "int_polarity_flag_bst_voutcomp"}, /* Polarity DCDC level 1x , */\
+{ 0x4d50, "int_polarity_flag_bst_voutcomp86"}, /* Polarity DCDC level 1.14x , */\
+{ 0x4d60, "int_polarity_flag_bst_voutcomp93"}, /* Polarity DCDC level 1.07x , */\
+{ 0x4d90, "int_polarity_flag_ocp_alarm"}, /* Polarity ocp alarm , */\
+{ 0x4da0, "int_polarity_flag_man_wait_src_settings"}, /* Polarity waits HW I2C settings , */\
+{ 0x4dc0, "int_polarity_flag_man_start_mute_audio"}, /* Polarity man audio mute sequence , */\
+{ 0x4df0, "int_polarity_flag_clk_out_of_range"}, /* Polarity flag_clk_out_of_range , */\
+{ 0x4e00, "int_polarity_flag_tdm_error"}, /* Polarity tdm error , */\
+{ 0x4e20, "int_polarity_flag_clip"}, /* Polarity clip right , */\
+{ 0x4e40, "int_polarity_flag_lp_detect_mode0"}, /* Polarity low power mode0 , */\
+{ 0x4e50, "int_polarity_flag_lp_detect_mode1"}, /* Polarity low power mode1 , */\
+{ 0x4e60, "int_polarity_flag_low_amplitude"}, /* Polarity low noise mode , */\
+{ 0x4e70, "int_polarity_flag_vddp_gt_vbat"}, /* Polarity VDDP greater than VBAT , */\
+{ 0x5001, "vbat_prot_attack_time"}, /* Battery Safeguard attack time , */\
+{ 0x5023, "vbat_prot_thlevel"}, /* Battery Safeguard threshold voltage level , */\
+{ 0x5061, "vbat_prot_max_reduct"}, /* Battery Safeguard maximum reduction , */\
+{ 0x50d0, "rst_min_vbat"}, /* Reset clipper - Auto clear , */\
+{ 0x50e0, "sel_vbat"}, /* Battery voltage read out , */\
+{ 0x50f0, "bypass_clipper"}, /* Bypass battery safeguard , */\
+{ 0x5100, "batsense_steepness"}, /* Vbat prot steepness , */\
+{ 0x5110, "soft_mute"}, /* Soft mute HW , */\
+{ 0x5150, "bypass_hp"}, /* Bypass HPF , */\
+{ 0x5170, "enbl_dpsa"}, /* Enable DPSA , */\
+{ 0x5222, "ctrl_cc"}, /* Clip control setting , */\
+{ 0x5257, "gain"}, /* Amplifier gain , */\
+{ 0x52d0, "ctrl_slopectrl"}, /* Enables slope control , */\
+{ 0x52e0, "ctrl_slope"}, /* Slope speed setting (bin. coded) , */\
+{ 0x5301, "dpsa_level"}, /* DPSA threshold levels , */\
+{ 0x5321, "dpsa_release"}, /* DPSA Release time , */\
+{ 0x5340, "clipfast"}, /* Clock selection for HW clipper for Battery Safeguard, */\
+{ 0x5350, "bypass_lp"}, /* Bypass the low power filter inside temperature sensor, */\
+{ 0x5400, "first_order_mode"}, /* Overrule to 1st order mode of control stage when clipping, */\
+{ 0x5410, "bypass_ctrlloop"}, /* Switch amplifier into open loop configuration , */\
+{ 0x5420, "fb_hz"}, /* Feedback resistor set to high ohmic , */\
+{ 0x5430, "icomp_engage"}, /* Engage of icomp , */\
+{ 0x5440, "ctrl_kickback"}, /* Prevent double pulses of output stage , */\
+{ 0x5450, "icomp_engage_overrule"}, /* To overrule the functional icomp_engage signal during validation, */\
+{ 0x5503, "ctrl_dem"}, /* Enable DEM icomp and DEM one bit dac , */\
+{ 0x5543, "ctrl_dem_mismatch"}, /* Enable DEM icomp mismatch for testing , */\
+{ 0x5582, "dpsa_drive"}, /* Drive setting (bin. coded) , */\
+{ 0x570a, "enbl_amp"}, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually, */\
+{ 0x57b0, "enbl_engage"}, /* Enables/engage power stage and control loop , */\
+{ 0x57c0, "enbl_engage_pst"}, /* Enables/engage power stage and control loop , */\
+{ 0x5810, "hard_mute"}, /* Hard mute - PWM , */\
+{ 0x5820, "pwm_shape"}, /* PWM shape , */\
+{ 0x5844, "pwm_delay"}, /* PWM delay bits to set the delay, clockd is 1/(k*2048*fs), */\
+{ 0x5890, "reclock_pwm"}, /* Reclock the pwm signal inside analog , */\
+{ 0x58a0, "reclock_voltsense"}, /* Reclock the voltage sense pwm signal , */\
+{ 0x58c0, "enbl_pwm_phase_shift"}, /* Control for pwm phase shift , */\
+{ 0x6081, "pga_gain_set"}, /* PGA gain selection , */\
+{ 0x60b0, "pga_lowpass_enable"}, /* Lowpass enable , */\
+{ 0x60c0, "pga_pwr_enable"}, /* Power enable, directcontrol mode only , */\
+{ 0x60d0, "pga_switch_enable"}, /* Switch enable, directcontrol mode only , */\
+{ 0x60e0, "pga_switch_aux_enable"}, /* Switch enable aux, directcontrol mode only , */\
+{ 0x6100, "force_idle"}, /* force low power in idle mode , */\
+{ 0x6110, "bypass_idle"}, /* bypass low power idle mode , */\
+{ 0x6123, "ctrl_attl"}, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */\
+{ 0x6163, "ctrl_attr"}, /* Total gain depending on INPLEV setting (channel 0), */\
+{ 0x61a0, "idle_cnt"}, /* idle counter , */\
+{ 0x61b0, "enbl_idle_ch1"}, /* enable idle feature for channel 1 , */\
+{ 0x6265, "zero_lvl"}, /* low noise gain switch zero trigger level , */\
+{ 0x62c1, "ctrl_fb_classd"}, /* class D gain ctrl_fb_50k ctrl_fb_100k , */\
+{ 0x62e1, "lownoisegain_mode"}, /* ctrl select mode , */\
+{ 0x6305, "threshold_lvl"}, /* low noise gain switch trigger level , */\
+{ 0x6365, "hold_time"}, /* ctrl hold time before low audio is reckoned to be low audio, */\
+{ 0x6405, "lpm1_cal_offset"}, /* low power mode1 detector ctrl cal_offset from gain module , */\
+{ 0x6465, "lpm1_zero_lvl"}, /* low power mode1 zero crossing detection level , */\
+{ 0x64e1, "lpm1_mode"}, /* low power mode control , */\
+{ 0x6505, "lpm1_threshold_lvl"}, /* low power mode1 amplitude trigger level , */\
+{ 0x6565, "lpm1_hold_time"}, /* low power mode1 detector ctrl hold time before low audio is reckoned to be low audio, */\
+{ 0x65c0, "disable_low_power_mode"}, /* low power mode1 detector control , */\
+{ 0x6600, "dcdc_pfm20khz_limit"}, /* DCDC in PFM mode pwm mode is activated each 50us to force a pwm pulse, */\
+{ 0x6611, "dcdc_ctrl_maxzercnt"}, /* DCDC. Number of zero current flags to count before going to pfm mode, */\
+{ 0x6656, "dcdc_vbat_delta_detect"}, /* Threshold before booster is reacting on a delta Vbat (in PFM mode) by temporarily switching to PWM mode, */\
+{ 0x66c0, "dcdc_ignore_vbat"}, /* Ignore an increase on Vbat , */\
+{ 0x6700, "enbl_minion"}, /* Enables minion (small) power stage , */\
+{ 0x6713, "vth_vddpvbat"}, /* select vddp-vbat thres signal , */\
+{ 0x6750, "lpen_vddpvbat"}, /* select vddp-vbat filtred vs unfiltered compare , */\
+{ 0x6801, "tdm_source_mapping"}, /* tdm source mapping , */\
+{ 0x6821, "tdm_sourcea_frame_sel"}, /* Sensed value A , */\
+{ 0x6841, "tdm_sourceb_frame_sel"}, /* Sensed value B , */\
+{ 0x6881, "pdm_anc_sel"}, /* anc input , */\
+{ 0x68a0, "anc_1scomplement"}, /* ANC one s complement , */\
+{ 0x6901, "sam_mode"}, /* sam enable , */\
+{ 0x6920, "sam_src"}, /* sam source , */\
+{ 0x6931, "pdmdat_h_sel"}, /* pdm out value when pdm_clk is higth , */\
+{ 0x6951, "pdmdat_l_sel"}, /* pdm out value when pdm_clk is low , */\
+{ 0x6970, "sam_spkr_sel"}, /* ram output on mode sam and audio , */\
+{ 0x6a02, "rst_min_vbat_delay"}, /* rst_min_vbat delay (nb fs) , */\
+{ 0x6b00, "disable_auto_engage"}, /* disable auto engange , */\
+{ 0x6b10, "sel_tdm_data_valid"}, /* select tdm valid for speaker subsystem , */\
+{ 0x6c02, "ns_hp2ln_criterion"}, /* 0..7 zeroes at ns as threshold to swap from high_power to low_noise, */\
+{ 0x6c32, "ns_ln2hp_criterion"}, /* 0..7 zeroes at ns as threshold to swap from low_noise to high_power, */\
+{ 0x6c69, "spare_out"}, /* spare_out , */\
+{ 0x6d0f, "spare_in"}, /* spare_in , */\
+{ 0x6e00, "flag_lp_detect_mode0"}, /* low power mode 0 detection , */\
+{ 0x6e10, "flag_lp_detect_mode1"}, /* low power mode 1 detection , */\
+{ 0x6e20, "flag_low_amplitude"}, /* low amplitude detection , */\
+{ 0x6e30, "flag_vddp_gt_vbat"}, /* vddp greater than vbat , */\
+{ 0x6f02, "cursense_comp_delay"}, /* delay to allign compensation signal with current sense signal, */\
+{ 0x6f40, "cursense_comp_sign"}, /* polarity of compensation for current sense , */\
+{ 0x6f50, "enbl_cursense_comp"}, /* enable current sense compensation , */\
+{ 0x6f60, "sel_clip_pwms"}, /* Select pwm clip flag , */\
+{ 0x6f72, "pwms_clip_lvl"}, /* set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
+{ 0x7002, "scnd_boost_voltage"}, /* Second boost voltage level , */\
+{ 0x7033, "boost_cur"}, /* Max coil current , */\
+{ 0x7071, "bst_slpcmplvl"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
+{ 0x7090, "boost_intel"}, /* Adaptive boost mode , */\
+{ 0x70a0, "boost_speed"}, /* Soft ramp up/down , */\
+{ 0x70e0, "dcdcoff_mode"}, /* DCDC on/off , */\
+{ 0x70f0, "dcdc_pwmonly"}, /* DCDC PWM only mode , */\
+{ 0x7104, "bst_drive"}, /* Binary coded drive setting for boost converter power stage, */\
+{ 0x7151, "bst_scalecur"}, /* For testing direct control scale current , */\
+{ 0x7174, "bst_slopecur"}, /* For testing direct control slope current , */\
+{ 0x71c1, "bst_slope"}, /* Boost slope speed , */\
+{ 0x71e0, "bst_bypass_bstcur"}, /* Bypass control for boost current settings , */\
+{ 0x71f0, "bst_bypass_bstfoldback"}, /* Bypass control for boost foldback , */\
+{ 0x7200, "enbl_bst_engage"}, /* Enable power stage dcdc controller , */\
+{ 0x7210, "enbl_bst_hizcom"}, /* Enable hiz comparator , */\
+{ 0x7220, "enbl_bst_peak2avg"}, /* Enable boost peak2avg functionality , */\
+{ 0x7230, "enbl_bst_peakcur"}, /* Enable peak current , */\
+{ 0x7240, "enbl_bst_power"}, /* Enable line of the powerstage , */\
+{ 0x7250, "enbl_bst_slopecur"}, /* Enable bit of max-current dac , */\
+{ 0x7260, "enbl_bst_voutcomp"}, /* Enable vout comparators , */\
+{ 0x7270, "enbl_bst_voutcomp86"}, /* Enable vout-86 comparators , */\
+{ 0x7280, "enbl_bst_voutcomp93"}, /* Enable vout-93 comparators , */\
+{ 0x7290, "enbl_bst_windac"}, /* Enable window dac , */\
+{ 0x72a5, "bst_windac"}, /* for testing direct control windac , */\
+{ 0x7300, "boost_alg"}, /* Control for boost adaptive loop gain , */\
+{ 0x7311, "boost_loopgain"}, /* DCDC boost loopgain setting , */\
+{ 0x7331, "bst_freq"}, /* DCDC boost frequency control , */\
+{ 0x7402, "frst_boost_voltage"}, /* 1st boost voltage level , */\
+{ 0x7430, "boost_track"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
+{ 0x7444, "boost_trip_lvl_1st"}, /* 1st Adaptive boost trip levels, effective only when DCIE is set to 1, */\
+{ 0x7494, "boost_hold_time"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
+{ 0x74e0, "sel_dcdc_envelope_8fs"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
+{ 0x74f0, "ignore_flag_voutcomp86"}, /* Ignore flag_voutcomp86 , */\
+{ 0x7502, "track_decay"}, /* DCDC Boost decay speed after a peak value, effective only when boost_track is set to 1, */\
+{ 0x7534, "boost_trip_lvl_2nd"}, /* 2nd Adaptive boost trip levels, effective only when DCIE is set to 1, */\
+{ 0x7584, "boost_trip_lvl_track"}, /* Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
+{ 0x7620, "pga_test_ldo_bypass"}, /* bypass internal PGA LDO , */\
+{ 0x8001, "sel_clk_cs"}, /* Current sense clock duty cycle control , */\
+{ 0x8021, "micadc_speed"}, /* Current sense clock for MiCADC selection - 32/44.1/48 KHz Fs band only, */\
+{ 0x8050, "cs_gain_control"}, /* Current sense gain control , */\
+{ 0x8060, "cs_bypass_gc"}, /* Bypasses the CS gain correction , */\
+{ 0x8087, "cs_gain"}, /* Current sense gain , */\
+{ 0x8200, "enbl_cmfb"}, /* Current sense common mode feedback control , */\
+{ 0x8210, "invertpwm"}, /* Current sense common mode feedback pwm invert control, */\
+{ 0x8222, "cmfb_gain"}, /* Current sense common mode feedback control gain , */\
+{ 0x8254, "cmfb_offset"}, /* Current sense common mode feedback control offset , */\
+{ 0x82a0, "cs_sam_set"}, /* Enable SAM input for current sense , */\
+{ 0x8305, "cs_ktemp"}, /* Current sense temperature compensation trimming (1 - VALUE*TEMP)*signal, */\
+{ 0x8400, "cs_adc_bsoinv"}, /* Bitstream inversion for current sense ADC , */\
+{ 0x8421, "cs_adc_hifreq"}, /* Frequency mode current sense ADC , */\
+{ 0x8440, "cs_adc_nortz"}, /* Return to zero for current sense ADC , */\
+{ 0x8453, "cs_adc_offset"}, /* Micadc ADC offset setting , */\
+{ 0x8490, "cs_adc_slowdel"}, /* Select delay for current sense ADC (internal decision circuitry), */\
+{ 0x84a4, "cs_adc_gain"}, /* Gain setting for current sense ADC (two's complement), */\
+{ 0x8500, "cs_resonator_enable"}, /* Enable for resonator to improve SRN , */\
+{ 0x8510, "cs_classd_tran_skip"}, /* Skip current sense connection during a classD amplifier transition, */\
+{ 0x8530, "cs_inn_short"}, /* Short current sense negative to common mode , */\
+{ 0x8540, "cs_inp_short"}, /* Short current sense positive to common mode , */\
+{ 0x8550, "cs_ldo_bypass"}, /* Bypass current sense LDO , */\
+{ 0x8560, "cs_ldo_pulldown"}, /* Pull down current sense LDO, only valid if left_enbl_cs_ldo is high, */\
+{ 0x8574, "cs_ldo_voset"}, /* Current sense LDO voltage level setting (two's complement), */\
+{ 0x8700, "enbl_cs_adc"}, /* Enable current sense ADC , */\
+{ 0x8710, "enbl_cs_inn1"}, /* Enable connection of current sense negative1 , */\
+{ 0x8720, "enbl_cs_inn2"}, /* Enable connection of current sense negative2 , */\
+{ 0x8730, "enbl_cs_inp1"}, /* Enable connection of current sense positive1 , */\
+{ 0x8740, "enbl_cs_inp2"}, /* Enable connection of current sense positive2 , */\
+{ 0x8750, "enbl_cs_ldo"}, /* Enable current sense LDO , */\
+{ 0x8760, "enbl_cs_nofloating_n"}, /* Connect current sense negative to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */\
+{ 0x8770, "enbl_cs_nofloating_p"}, /* Connect current sense positive to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */\
+{ 0x8780, "enbl_cs_vbatldo"}, /* Enable of current sense LDO , */\
+{ 0x8800, "volsense_pwm_sel"}, /* Voltage sense PWM source selection control , */\
+{ 0x8810, "vol_cur_sense_dc_offset"}, /* voltage and current sense decimator offset control, */\
+{ 0xa007, "mtpkey1"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
+{ 0xa107, "mtpkey2"}, /* MTP KEY2 register , */\
+{ 0xa200, "key01_locked"}, /* Indicates KEY1 is locked , */\
+{ 0xa210, "key02_locked"}, /* Indicates KEY2 is locked , */\
+{ 0xa302, "mtp_man_address_in"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
+{ 0xa330, "man_copy_mtp_to_iic"}, /* Start copying single word from mtp to I2C mtp register, */\
+{ 0xa340, "man_copy_iic_to_mtp"}, /* Start copying single word from I2C mtp register to mtp, */\
+{ 0xa350, "auto_copy_mtp_to_iic"}, /* Start copying all the data from mtp to I2C mtp registers, */\
+{ 0xa360, "auto_copy_iic_to_mtp"}, /* Start copying data from I2C mtp registers to mtp , */\
+{ 0xa400, "faim_set_clkws"}, /* Sets the faim controller clock wait state register, */\
+{ 0xa410, "faim_sel_evenrows"}, /* All even rows of the faim are selected, active high, */\
+{ 0xa420, "faim_sel_oddrows"}, /* All odd rows of the faim are selected, all rows in combination with sel_evenrows, */\
+{ 0xa430, "faim_program_only"}, /* Skip the erase access at wr_faim command (write-program-marginread), */\
+{ 0xa440, "faim_erase_only"}, /* Skip the program access at wr_faim command (write-erase-marginread), */\
+{ 0xa50f, "mtp_man_data_out_msb"}, /* MSB word of MTP manual read data , */\
+{ 0xa60f, "mtp_man_data_out_lsb"}, /* LSB word of MTP manual read data , */\
+{ 0xa70f, "mtp_man_data_in_msb"}, /* MSB word of write data for MTP manual write , */\
+{ 0xa80f, "mtp_man_data_in_lsb"}, /* LSB word of write data for MTP manual write , */\
+{ 0xb010, "bypass_ocpcounter"}, /* Bypass OCP Counter , */\
+{ 0xb020, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
+{ 0xb030, "bypass_ovp"}, /* Bypass OVP , */\
+{ 0xb040, "bypass_uvp"}, /* Bypass UVP , */\
+{ 0xb050, "bypass_otp"}, /* Bypass OTP , */\
+{ 0xb060, "bypass_lost_clk"}, /* Bypass lost clock detector , */\
+{ 0xb070, "ctrl_vpalarm"}, /* vpalarm (uvp ovp handling) , */\
+{ 0xb087, "ocp_threshold"}, /* OCP threshold level , */\
+{ 0xb108, "ext_temp"}, /* External temperature (C) , */\
+{ 0xb190, "ext_temp_sel"}, /* Select temp Speaker calibration , */\
+{ 0xc000, "use_direct_ctrls"}, /* Direct control to overrule several functions for testing, */\
+{ 0xc010, "rst_datapath"}, /* Direct control for datapath reset , */\
+{ 0xc020, "rst_cgu"}, /* Direct control for cgu reset , */\
+{ 0xc038, "enbl_ref"}, /* Switch on the analog references, each part of the references can be switched on/off individually, */\
+{ 0xc0d0, "enbl_ringo"}, /* Enable the ring oscillator for test purpose , */\
+{ 0xc0e0, "use_direct_clk_ctrl"}, /* Direct clock control to overrule several functions for testing, */\
+{ 0xc0f0, "use_direct_pll_ctrl"}, /* Direct PLL control to overrule several functions for testing, */\
+{ 0xc100, "enbl_tsense"}, /* Temperature sensor enable control - I2C direct mode, */\
+{ 0xc110, "tsense_hibias"}, /* Bit to set the biasing in temp sensor to high , */\
+{ 0xc120, "enbl_flag_vbg"}, /* Enable flagging of bandgap out of control , */\
+{ 0xc20f, "abist_offset"}, /* Offset control for ABIST testing (two's complement), */\
+{ 0xc300, "bypasslatch"}, /* Bypass latch , */\
+{ 0xc311, "sourcea"}, /* Set OUTA to , */\
+{ 0xc331, "sourceb"}, /* Set OUTB to , */\
+{ 0xc350, "inverta"}, /* Invert pwma test signal , */\
+{ 0xc360, "invertb"}, /* Invert pwmb test signal , */\
+{ 0xc374, "pulselength"}, /* Pulse length setting test input for amplifier (clock d - k*2048*fs), */\
+{ 0xc3c0, "tdm_enable_loopback"}, /* TDM loopback test , */\
+{ 0xc400, "bst_bypasslatch"}, /* Bypass latch in boost converter , */\
+{ 0xc411, "bst_source"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
+{ 0xc430, "bst_invertb"}, /* Invert pwmbst test signal , */\
+{ 0xc444, "bst_pulselength"}, /* Pulse length setting test input for boost converter , */\
+{ 0xc490, "test_bst_ctrlsthv"}, /* Test mode for boost control stage , */\
+{ 0xc4a0, "test_bst_iddq"}, /* IDDQ testing in power stage of boost converter , */\
+{ 0xc4b0, "test_bst_rdson"}, /* RDSON testing - boost power stage , */\
+{ 0xc4c0, "test_bst_cvi"}, /* CVI testing - boost power stage , */\
+{ 0xc4d0, "test_bst_ocp"}, /* Boost OCP. For old ocp (ctrl_reversebst is 0), For new ocp (ctrl_reversebst is 1), */\
+{ 0xc4e0, "test_bst_sense"}, /* Test option for the sense NMOS in booster for current mode control., */\
+{ 0xc500, "test_cvi"}, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */\
+{ 0xc510, "test_discrete"}, /* Test function noise measurement , */\
+{ 0xc520, "test_iddq"}, /* Set the power stages in iddq mode for gate stress., */\
+{ 0xc540, "test_rdson"}, /* Analog BIST, switch to enable Rdson measurement , */\
+{ 0xc550, "test_sdelta"}, /* Analog BIST, noise test , */\
+{ 0xc570, "test_enbl_cs"}, /* Enable for digimux mode of current sense , */\
+{ 0xc5b0, "pga_test_enable"}, /* Enable PGA test mode , */\
+{ 0xc5c0, "pga_test_offset_enable"}, /* Enable PGA test offset , */\
+{ 0xc5d0, "pga_test_shortinput_enable"}, /* Enable PGA test shortinput , */\
+{ 0xc600, "enbl_pwm_dcc"}, /* Enables direct control of pwm duty cycle for DCDC power stage, */\
+{ 0xc613, "pwm_dcc_cnt"}, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */\
+{ 0xc650, "enbl_ldo_stress"}, /* Enable stress of internal supply voltages powerstages, */\
+{ 0xc707, "digimuxa_sel"}, /* DigimuxA input selection control routed to DATAO (see Digimux list for details), */\
+{ 0xc787, "digimuxb_sel"}, /* DigimuxB input selection control routed to INT (see Digimux list for details), */\
+{ 0xc807, "digimuxc_sel"}, /* DigimuxC input selection control routed to PDMDAT (see Digimux list for details), */\
+{ 0xc981, "int_ehs"}, /* Speed/load setting for INT IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
+{ 0xc9c0, "hs_mode"}, /* I2C high speed mode control , */\
+{ 0xca00, "enbl_anamux1"}, /* Enable anamux1 , */\
+{ 0xca10, "enbl_anamux2"}, /* Enable anamux2 , */\
+{ 0xca20, "enbl_anamux3"}, /* Enable anamux3 , */\
+{ 0xca30, "enbl_anamux4"}, /* Enable anamux4 , */\
+{ 0xca74, "anamux1"}, /* Anamux selection control - anamux on TEST1 , */\
+{ 0xcb04, "anamux2"}, /* Anamux selection control - anamux on TEST2 , */\
+{ 0xcb54, "anamux3"}, /* Anamux selection control - anamux on TEST3 , */\
+{ 0xcba4, "anamux4"}, /* Anamux selection control - anamux on TEST4 , */\
+{ 0xcd05, "pll_seli"}, /* PLL SELI - I2C direct PLL control mode only , */\
+{ 0xcd64, "pll_selp"}, /* PLL SELP - I2C direct PLL control mode only , */\
+{ 0xcdb3, "pll_selr"}, /* PLL SELR - I2C direct PLL control mode only , */\
+{ 0xcdf0, "pll_frm"}, /* PLL free running mode control; 1 in TCB direct control mode, else this control bit, */\
+{ 0xce09, "pll_ndec"}, /* PLL NDEC - I2C direct PLL control mode only , */\
+{ 0xcea0, "pll_mdec_msb"}, /* MSB of pll_mdec - I2C direct PLL control mode only, */\
+{ 0xceb0, "enbl_pll"}, /* Enables PLL in I2C direct PLL control mode only , */\
+{ 0xcec0, "enbl_osc"}, /* Enables OSC1M in I2C direct control mode only , */\
+{ 0xced0, "pll_bypass"}, /* PLL bypass control in I2C direct PLL control mode only, */\
+{ 0xcee0, "pll_directi"}, /* PLL directi control in I2C direct PLL control mode only, */\
+{ 0xcef0, "pll_directo"}, /* PLL directo control in I2C direct PLL control mode only, */\
+{ 0xcf0f, "pll_mdec_lsb"}, /* Bits 15..0 of PLL MDEC are I2C direct PLL control mode only, */\
+{ 0xd006, "pll_pdec"}, /* PLL PDEC - I2C direct PLL control mode only , */\
+{ 0xd10f, "tsig_freq_lsb"}, /* Internal sinus test generator frequency control , */\
+{ 0xd202, "tsig_freq_msb"}, /* Select internal sinus test generator, frequency control msb bits, */\
+{ 0xd230, "inject_tsig"}, /* Control bit to switch to internal sinus test generator, */\
+{ 0xd283, "tsig_gain"}, /* Test signal gain , */\
+{ 0xd300, "adc10_reset"}, /* Reset for ADC10 - I2C direct control mode , */\
+{ 0xd311, "adc10_test"}, /* Test mode selection signal for ADC10 - I2C direct control mode, */\
+{ 0xd332, "adc10_sel"}, /* Select the input to convert for ADC10 - I2C direct control mode, */\
+{ 0xd364, "adc10_prog_sample"}, /* ADC10 program sample setting - I2C direct control mode, */\
+{ 0xd3b0, "adc10_enbl"}, /* Enable ADC10 - I2C direct control mode , */\
+{ 0xd3c0, "bypass_lp_vbat"}, /* Bypass control for Low pass filter in batt sensor , */\
+{ 0xd409, "data_adc10_tempbat"}, /* ADC 10 data output data for testing , */\
+{ 0xd507, "ctrl_digtoana_hidden"}, /* Spare digital to analog control bits - Hidden , */\
+{ 0xd580, "enbl_clk_out_of_range"}, /* Clock out of range , */\
+{ 0xd621, "clkdiv_audio_sel"}, /* Audio clock divider selection in direct clock control mode, */\
+{ 0xd641, "clkdiv_muxa_sel"}, /* DCDC MUXA clock divider selection in direct clock control mode, */\
+{ 0xd661, "clkdiv_muxb_sel"}, /* DCDC MUXB clock divider selection in direct clock control mode, */\
+{ 0xd701, "pdmdat_ehs"}, /* Speed/load setting for PDMDAT IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
+{ 0xd721, "datao_ehs"}, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
+{ 0xd740, "bck_ehs"}, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
+{ 0xd750, "datai_ehs"}, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
+{ 0xd760, "pdmclk_ehs"}, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
+{ 0xd800, "source_in_testmode"}, /* tdm source in test mode (return only current and voltage sense), */\
+{ 0xd810, "gainatt_feedback"}, /* gainatt feedback to tdm , */\
+{ 0xd822, "test_parametric_io"}, /* test io parametric , */\
+{ 0xd850, "ctrl_bst_clk_lp1"}, /* boost clock control in low power mode1 , */\
+{ 0xd861, "test_spare_out1"}, /* test spare out 1 , */\
+{ 0xd880, "bst_dcmbst"}, /* dcm boost , */\
+{ 0xd890, "pdm_loopback"}, /* pdm loop back to tdm , */\
+{ 0xd8a1, "force_pga_clock"}, /* force pga clock , */\
+{ 0xd8c3, "test_spare_out2"}, /* test spare out 1 , */\
+{ 0xee0f, "sw_profile"}, /* Software profile data , */\
+{ 0xef0f, "sw_vstep"}, /* Software vstep information , */\
+{ 0xf000, "calibration_onetime"}, /* Calibration schedule , */\
+{ 0xf010, "calibr_ron_done"}, /* Calibration Ron executed , */\
+{ 0xf020, "calibr_dcdc_api_calibrate"}, /* Calibration current limit DCDC , */\
+{ 0xf030, "calibr_dcdc_delta_sign"}, /* Sign bit for delta calibration current limit DCDC , */\
+{ 0xf042, "calibr_dcdc_delta"}, /* Calibration delta current limit DCDC , */\
+{ 0xf078, "calibr_speaker_info"}, /* Reserved space for allowing customer to store speaker information, */\
+{ 0xf105, "calibr_vout_offset"}, /* DCDC offset calibration 2's complement (key1 protected), */\
+{ 0xf163, "spare_mpt1_9_6"}, /* HW gain module - left channel (2's complement) , */\
+{ 0xf1a5, "spare_mpt1_15_10"}, /* Offset for amplifier, HW gain module - left channel (2's complement), */\
+{ 0xf203, "calibr_gain"}, /* HW gain module (2's complement) , */\
+{ 0xf245, "calibr_offset"}, /* Offset for amplifier, HW gain module (2's complement), */\
+{ 0xf2a3, "spare_mpt2_13_10"}, /* Trimming of LDO (2.7V) , */\
+{ 0xf307, "spare_mpt3_7_0"}, /* SPARE , */\
+{ 0xf387, "calibr_gain_cs"}, /* Current sense gain (signed two's complement format), */\
+{ 0xf40f, "spare_mtp4_15_0"}, /* SPARE , */\
+{ 0xf50f, "calibr_R25C_R"}, /* Ron resistance of speaker coil , */\
+{ 0xf606, "spare_mpt6_6_0"}, /* SPARE , */\
+{ 0xf686, "spare_mpt6_14_8"}, /* Offset of left amplifier level shifter B , */\
+{ 0xf706, "ctrl_offset_a"}, /* Offset of level shifter A , */\
+{ 0xf786, "ctrl_offset_b"}, /* Offset of amplifier level shifter B , */\
+{ 0xf806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
+{ 0xf870, "htol_iic_addr_en"}, /* HTOL I2C address enable control , */\
+{ 0xf884, "calibr_temp_offset"}, /* Temperature offset 2's compliment (key1 protected), */\
+{ 0xf8d2, "calibr_temp_gain"}, /* Temperature gain 2's compliment (key1 protected) , */\
+{ 0xf900, "mtp_lock_dcdcoff_mode"}, /* Disable function dcdcoff_mode , */\
+{ 0xf910, "disable_sam_mode"}, /* Disable same mode , */\
+{ 0xf920, "mtp_lock_bypass_clipper"}, /* Disable function bypass_clipper , */\
+{ 0xf930, "mtp_lock_max_dcdc_voltage"}, /* Disable programming of max dcdc boost voltage , */\
+{ 0xf943, "calibr_vbg_trim"}, /* Bandgap trimming control , */\
+{ 0xf980, "mtp_enbl_amp_in_state_alarm"}, /* Enbl_amp in alarm state , */\
+{ 0xf990, "mtp_enbl_pwm_delay_clock_gating"}, /* pwm delay clock auto gating , */\
+{ 0xf9a0, "mtp_enbl_ocp_clock_gating"}, /* ocpclock auto gating , */\
+{ 0xf9b0, "mtp_gate_cgu_clock_for_test"}, /* cgu test clock control , */\
+{ 0xf9c3, "spare_mtp9_15_12"}, /* MTP-control FW - See Firmware I2C API document for details, */\
+{ 0xfa0f, "mtpdataA"}, /* MTPdataA (key1 protected) , */\
+{ 0xfb0f, "mtpdataB"}, /* MTPdataB (key1 protected) , */\
+{ 0xfc0f, "mtpdataC"}, /* MTPdataC (key1 protected) , */\
+{ 0xfd0f, "mtpdataD"}, /* MTPdataD (key1 protected) , */\
+{ 0xfe0f, "mtpdataE"}, /* MTPdataE (key1 protected) , */\
+{ 0xff07, "calibr_osc_delta_ndiv"}, /* Calibration data for OSC1M, signed number representation, */\
+{ 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+
+enum tfa9872_irq {
+tfa9872_irq_stvdds = 0,
+tfa9872_irq_stplls = 1,
+tfa9872_irq_stotds = 2,
+tfa9872_irq_stovds = 3,
+tfa9872_irq_stuvds = 4,
+tfa9872_irq_stclks = 5,
+tfa9872_irq_stmtpb = 6,
+tfa9872_irq_stnoclk = 7,
+tfa9872_irq_stsws = 10,
+tfa9872_irq_stamps = 12,
+tfa9872_irq_starefs = 13,
+tfa9872_irq_stadccr = 14,
+tfa9872_irq_stbstcu = 16,
+tfa9872_irq_stbsthi = 17,
+tfa9872_irq_stbstoc = 18,
+tfa9872_irq_stbstpkcur = 19,
+tfa9872_irq_stbstvc = 20,
+tfa9872_irq_stbst86 = 21,
+tfa9872_irq_stbst93 = 22,
+tfa9872_irq_stocpr = 25,
+tfa9872_irq_stmwsrc = 26,
+tfa9872_irq_stmwsmu = 28,
+tfa9872_irq_stclkoor = 31,
+tfa9872_irq_sttdmer = 32,
+tfa9872_irq_stclpr = 34,
+tfa9872_irq_stlp0 = 36,
+tfa9872_irq_stlp1 = 37,
+tfa9872_irq_stla = 38,
+tfa9872_irq_stvddph = 39,
+tfa9872_irq_max = 40,
+tfa9872_irq_all = -1 /* all irqs */};
+
+#define TFA9872_IRQ_NAMETABLE static tfaIrqName_t Tfa9872IrqNames[] = {\
+{ 0, "STVDDS"},\
+{ 1, "STPLLS"},\
+{ 2, "STOTDS"},\
+{ 3, "STOVDS"},\
+{ 4, "STUVDS"},\
+{ 5, "STCLKS"},\
+{ 6, "STMTPB"},\
+{ 7, "STNOCLK"},\
+{ 8, "8"},\
+{ 9, "9"},\
+{ 10, "STSWS"},\
+{ 11, "11"},\
+{ 12, "STAMPS"},\
+{ 13, "STAREFS"},\
+{ 14, "STADCCR"},\
+{ 15, "15"},\
+{ 16, "STBSTCU"},\
+{ 17, "STBSTHI"},\
+{ 18, "STBSTOC"},\
+{ 19, "STBSTPKCUR"},\
+{ 20, "STBSTVC"},\
+{ 21, "STBST86"},\
+{ 22, "STBST93"},\
+{ 23, "23"},\
+{ 24, "24"},\
+{ 25, "STOCPR"},\
+{ 26, "STMWSRC"},\
+{ 27, "27"},\
+{ 28, "STMWSMU"},\
+{ 29, "29"},\
+{ 30, "30"},\
+{ 31, "STCLKOOR"},\
+{ 32, "STTDMER"},\
+{ 33, "33"},\
+{ 34, "STCLPR"},\
+{ 35, "35"},\
+{ 36, "STLP0"},\
+{ 37, "STLP1"},\
+{ 38, "STLA"},\
+{ 39, "STVDDPH"},\
+{ 40, "40"},\
+};
+#endif /* _TFA9872_TFAFIELDNAMES_H */
diff --git a/sound/soc/codecs/tfa9874_tfafieldnames.h b/sound/soc/codecs/tfa9874_tfafieldnames.h
new file mode 100644
index 0000000..5c6a233
--- /dev/null
+++ b/sound/soc/codecs/tfa9874_tfafieldnames.h
@@ -0,0 +1,836 @@
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _TFA9874_TFAFIELDNAMES_H
+#define _TFA9874_TFAFIELDNAMES_H
+
+
+#define TFA9874_I2CVERSION 1.16
+
+typedef enum nxpTfa9874BfEnumList {
+TFA9874_BF_PWDN = 0x0000, /*!< Powerdown selection */
+TFA9874_BF_I2CR = 0x0010, /*!< I2C Reset - Auto clear */
+TFA9874_BF_AMPE = 0x0030, /*!< Activate Amplifier */
+TFA9874_BF_DCA = 0x0040, /*!< Activate DC-to-DC converter */
+TFA9874_BF_INTP = 0x0071, /*!< Interrupt config */
+TFA9874_BF_BYPOCP = 0x00b0, /*!< Bypass OCP */
+TFA9874_BF_TSTOCP = 0x00c0, /*!< OCP testing control */
+TFA9874_BF_MANSCONF = 0x0120, /*!< I2C configured */
+TFA9874_BF_MANAOOSC = 0x0140, /*!< Internal osc off at PWDN */
+TFA9874_BF_MUTETO = 0x01d0, /*!< Time out SB mute sequence */
+TFA9874_BF_OPENMTP = 0x01e0, /*!< Control for FAIM protection */
+TFA9874_BF_AUDFS = 0x0203, /*!< Sample rate (fs) */
+TFA9874_BF_INPLEV = 0x0240, /*!< TDM output attenuation */
+TFA9874_BF_FRACTDEL = 0x0255, /*!< V/I Fractional delay */
+TFA9874_BF_REV = 0x030f, /*!< Revision info */
+TFA9874_BF_REFCKEXT = 0x0401, /*!< PLL external ref clock */
+TFA9874_BF_REFCKSEL = 0x0420, /*!< PLL internal ref clock */
+TFA9874_BF_SSFAIME = 0x05c0, /*!< Sub-system FAIM */
+TFA9874_BF_AMPOCRT = 0x0802, /*!< Amplifier on-off criteria for shutdown */
+TFA9874_BF_VDDS = 0x1000, /*!< POR */
+TFA9874_BF_DCOCPOK = 0x1010, /*!< DCDC OCP nmos (sticky register , clear on read) */
+TFA9874_BF_OTDS = 0x1020, /*!< OTP alarm (sticky register , clear on read) */
+TFA9874_BF_OCDS = 0x1030, /*!< OCP amplifier (sticky register , clear on read) */
+TFA9874_BF_UVDS = 0x1040, /*!< UVP alarm (sticky register , clear on read) */
+TFA9874_BF_MANALARM = 0x1050, /*!< Alarm state */
+TFA9874_BF_TDMERR = 0x1060, /*!< TDM error */
+TFA9874_BF_NOCLK = 0x1070, /*!< Lost clock (sticky register , clear on read) */
+TFA9874_BF_DCIL = 0x1100, /*!< DCDC current limiting */
+TFA9874_BF_DCDCA = 0x1110, /*!< DCDC active (sticky register , clear on read) */
+TFA9874_BF_DCHVBAT = 0x1130, /*!< DCDC level 1x */
+TFA9874_BF_DCH114 = 0x1140, /*!< DCDC level 1.14x */
+TFA9874_BF_DCH107 = 0x1150, /*!< DCDC level 1.07x */
+TFA9874_BF_PLLS = 0x1160, /*!< PLL lock */
+TFA9874_BF_CLKS = 0x1170, /*!< Clocks stable */
+TFA9874_BF_TDMLUTER = 0x1180, /*!< TDM LUT error */
+TFA9874_BF_TDMSTAT = 0x1192, /*!< TDM status bits */
+TFA9874_BF_MTPB = 0x11c0, /*!< MTP busy */
+TFA9874_BF_SWS = 0x11d0, /*!< Amplifier engage */
+TFA9874_BF_AMPS = 0x11e0, /*!< Amplifier enable */
+TFA9874_BF_AREFS = 0x11f0, /*!< References enable */
+TFA9874_BF_OCPOAP = 0x1300, /*!< OCPOK pmos A */
+TFA9874_BF_OCPOAN = 0x1310, /*!< OCPOK nmos A */
+TFA9874_BF_OCPOBP = 0x1320, /*!< OCPOK pmos B */
+TFA9874_BF_OCPOBN = 0x1330, /*!< OCPOK nmos B */
+TFA9874_BF_OVDS = 0x1380, /*!< OVP alarm */
+TFA9874_BF_CLIPS = 0x1390, /*!< Amplifier clipping */
+TFA9874_BF_ADCCR = 0x13a0, /*!< Control ADC */
+TFA9874_BF_MANWAIT1 = 0x13c0, /*!< Wait HW I2C settings */
+TFA9874_BF_MANMUTE = 0x13e0, /*!< Audio mute sequence */
+TFA9874_BF_MANOPER = 0x13f0, /*!< Operating state */
+TFA9874_BF_CLKOOR = 0x1420, /*!< External clock status */
+TFA9874_BF_MANSTATE = 0x1433, /*!< Device manager status */
+TFA9874_BF_DCMODE = 0x1471, /*!< DCDC mode status bits */
+TFA9874_BF_BATS = 0x1509, /*!< Battery voltage (V) */
+TFA9874_BF_TEMPS = 0x1608, /*!< IC Temperature (C) */
+TFA9874_BF_VDDPS = 0x1709, /*!< IC VDDP voltage ( 1023*VDDP/13 V) */
+TFA9874_BF_TDME = 0x2040, /*!< Enable interface */
+TFA9874_BF_TDMMODE = 0x2050, /*!< Slave/master */
+TFA9874_BF_TDMCLINV = 0x2060, /*!< Reception data to BCK clock */
+TFA9874_BF_TDMFSLN = 0x2073, /*!< FS length (master mode only) */
+TFA9874_BF_TDMFSPOL = 0x20b0, /*!< FS polarity */
+TFA9874_BF_TDMNBCK = 0x20c3, /*!< N-BCK's in FS */
+TFA9874_BF_TDMSLOTS = 0x2103, /*!< N-slots in Frame */
+TFA9874_BF_TDMSLLN = 0x2144, /*!< N-bits in slot */
+TFA9874_BF_TDMBRMG = 0x2194, /*!< N-bits remaining */
+TFA9874_BF_TDMDEL = 0x21e0, /*!< data delay to FS */
+TFA9874_BF_TDMADJ = 0x21f0, /*!< data adjustment */
+TFA9874_BF_TDMOOMP = 0x2201, /*!< Received audio compression */
+TFA9874_BF_TDMSSIZE = 0x2224, /*!< Sample size per slot */
+TFA9874_BF_TDMTXDFO = 0x2271, /*!< Format unused bits */
+TFA9874_BF_TDMTXUS0 = 0x2291, /*!< Format unused slots DATAO */
+TFA9874_BF_TDMSPKE = 0x2300, /*!< Control audio tdm channel in 0 (spkr + dcdc) */
+TFA9874_BF_TDMDCE = 0x2310, /*!< Control audio tdm channel in 1 (dcdc) */
+TFA9874_BF_TDMCSE = 0x2330, /*!< current sense vbat temperature and vddp feedback */
+TFA9874_BF_TDMVSE = 0x2340, /*!< Voltage sense vbat temperature and vddp feedback */
+TFA9874_BF_TDMSPKS = 0x2603, /*!< tdm slot for sink 0 (speaker + dcdc) */
+TFA9874_BF_TDMDCS = 0x2643, /*!< tdm slot for sink 1 (dcdc) */
+TFA9874_BF_TDMCSS = 0x26c3, /*!< Slot Position of current sense vbat temperature and vddp feedback */
+TFA9874_BF_TDMVSS = 0x2703, /*!< Slot Position of Voltage sense vbat temperature and vddp feedback */
+TFA9874_BF_ISTVDDS = 0x4000, /*!< Status POR */
+TFA9874_BF_ISTBSTOC = 0x4010, /*!< Status DCDC OCP */
+TFA9874_BF_ISTOTDS = 0x4020, /*!< Status OTP alarm */
+TFA9874_BF_ISTOCPR = 0x4030, /*!< Status ocp alarm */
+TFA9874_BF_ISTUVDS = 0x4040, /*!< Status UVP alarm */
+TFA9874_BF_ISTMANALARM = 0x4050, /*!< Status nanager Alarm state */
+TFA9874_BF_ISTTDMER = 0x4060, /*!< Status tdm error */
+TFA9874_BF_ISTNOCLK = 0x4070, /*!< Status lost clock */
+TFA9874_BF_ICLVDDS = 0x4400, /*!< Clear POR */
+TFA9874_BF_ICLBSTOC = 0x4410, /*!< Clear DCDC OCP */
+TFA9874_BF_ICLOTDS = 0x4420, /*!< Clear OTP alarm */
+TFA9874_BF_ICLOCPR = 0x4430, /*!< Clear ocp alarm */
+TFA9874_BF_ICLUVDS = 0x4440, /*!< Clear UVP alarm */
+TFA9874_BF_ICLMANALARM = 0x4450, /*!< clear nanager Alarm state */
+TFA9874_BF_ICLTDMER = 0x4460, /*!< Clear tdm error */
+TFA9874_BF_ICLNOCLK = 0x4470, /*!< Clear lost clk */
+TFA9874_BF_IEVDDS = 0x4800, /*!< Enable por */
+TFA9874_BF_IEBSTOC = 0x4810, /*!< Enable DCDC OCP */
+TFA9874_BF_IEOTDS = 0x4820, /*!< Enable OTP alarm */
+TFA9874_BF_IEOCPR = 0x4830, /*!< Enable ocp alarm */
+TFA9874_BF_IEUVDS = 0x4840, /*!< Enable UVP alarm */
+TFA9874_BF_IEMANALARM = 0x4850, /*!< Enable nanager Alarm state */
+TFA9874_BF_IETDMER = 0x4860, /*!< Enable tdm error */
+TFA9874_BF_IENOCLK = 0x4870, /*!< Enable lost clk */
+TFA9874_BF_IPOVDDS = 0x4c00, /*!< Polarity por */
+TFA9874_BF_IPOBSTOC = 0x4c10, /*!< Polarity DCDC OCP */
+TFA9874_BF_IPOOTDS = 0x4c20, /*!< Polarity OTP alarm */
+TFA9874_BF_IPOOCPR = 0x4c30, /*!< Polarity ocp alarm */
+TFA9874_BF_IPOUVDS = 0x4c40, /*!< Polarity UVP alarm */
+TFA9874_BF_IPOMANALARM = 0x4c50, /*!< Polarity nanager Alarm state */
+TFA9874_BF_IPOTDMER = 0x4c60, /*!< Polarity tdm error */
+TFA9874_BF_IPONOCLK = 0x4c70, /*!< Polarity lost clk */
+TFA9874_BF_BSSCR = 0x5001, /*!< Battery Safeguard attack time */
+TFA9874_BF_BSST = 0x5023, /*!< Battery Safeguard threshold voltage level */
+TFA9874_BF_BSSRL = 0x5061, /*!< Battery Safeguard maximum reduction */
+TFA9874_BF_VBATFLTL = 0x5080, /*!< vbat filter limit */
+TFA9874_BF_BSSR = 0x50e0, /*!< Battery voltage read out */
+TFA9874_BF_BSSBY = 0x50f0, /*!< Bypass battery safeguard */
+TFA9874_BF_BSSS = 0x5100, /*!< Vbat prot steepness */
+TFA9874_BF_HPFBYP = 0x5150, /*!< Bypass HPF */
+TFA9874_BF_DPSA = 0x5170, /*!< Enable DPSA */
+TFA9874_BF_CLIPCTRL = 0x5222, /*!< Clip control setting */
+TFA9874_BF_AMPGAIN = 0x5257, /*!< Amplifier gain */
+TFA9874_BF_SLOPEE = 0x52d0, /*!< Enables slope control */
+TFA9874_BF_SLOPESET = 0x52e0, /*!< Slope speed setting (bin. coded) */
+TFA9874_BF_TDMDCG = 0x6123, /*!< Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE) */
+TFA9874_BF_TDMSPKG = 0x6163, /*!< Total gain depending on INPLEV setting (channel 0) */
+TFA9874_BF_LNMODE = 0x62e1, /*!< ctrl select mode */
+TFA9874_BF_LPM1MODE = 0x64e1, /*!< low power mode control */
+TFA9874_BF_TDMSRCMAP = 0x6802, /*!< tdm source mapping */
+TFA9874_BF_TDMSRCAS = 0x6831, /*!< Sensed value A */
+TFA9874_BF_TDMSRCBS = 0x6851, /*!< Sensed value B */
+TFA9874_BF_TDMSRCACLIP = 0x6871, /*!< clip information (analog /digital) for source0 */
+TFA9874_BF_TDMSRCBCLIP = 0x6891, /*!< clip information (analog /digital) for source1 */
+TFA9874_BF_LP1 = 0x6e10, /*!< low power mode 1 detection */
+TFA9874_BF_LA = 0x6e20, /*!< low amplitude detection */
+TFA9874_BF_VDDPH = 0x6e30, /*!< vddp greater than vbat */
+TFA9874_BF_DELCURCOMP = 0x6f02, /*!< delay to allign compensation signal with current sense signal */
+TFA9874_BF_SIGCURCOMP = 0x6f40, /*!< polarity of compensation for current sense */
+TFA9874_BF_ENCURCOMP = 0x6f50, /*!< enable current sense compensation */
+TFA9874_BF_LVLCLPPWM = 0x6f72, /*!< set the amount of pwm pulse that may be skipped before clip-flag is triggered */
+TFA9874_BF_DCMCC = 0x7033, /*!< Max coil current */
+TFA9874_BF_DCCV = 0x7071, /*!< Slope compensation current, represents LxF (inductance x frequency) value */
+TFA9874_BF_DCIE = 0x7090, /*!< Adaptive boost mode */
+TFA9874_BF_DCSR = 0x70a0, /*!< Soft ramp up/down */
+TFA9874_BF_DCDIS = 0x70e0, /*!< DCDC on/off */
+TFA9874_BF_DCPWM = 0x70f0, /*!< DCDC PWM only mode */
+TFA9874_BF_DCTRACK = 0x7430, /*!< Boost algorithm selection, effective only when boost_intelligent is set to 1 */
+TFA9874_BF_DCTRIP = 0x7444, /*!< 1st Adaptive boost trip levels, effective only when DCIE is set to 1 */
+TFA9874_BF_DCHOLD = 0x7494, /*!< Hold time for DCDC booster, effective only when boost_intelligent is set to 1 */
+TFA9874_BF_DCINT = 0x74e0, /*!< Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1 */
+TFA9874_BF_DCTRIP2 = 0x7534, /*!< 2nd Adaptive boost trip levels, effective only when DCIE is set to 1 */
+TFA9874_BF_DCTRIPT = 0x7584, /*!< Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1 */
+TFA9874_BF_DCTRIPHYSTE = 0x75f0, /*!< Enable hysteresis on booster trip levels */
+TFA9874_BF_DCVOF = 0x7635, /*!< First boost voltage level */
+TFA9874_BF_DCVOS = 0x7695, /*!< Second boost voltage level */
+TFA9874_BF_MTPK = 0xa107, /*!< MTP KEY2 register */
+TFA9874_BF_KEY1LOCKED = 0xa200, /*!< Indicates KEY1 is locked */
+TFA9874_BF_KEY2LOCKED = 0xa210, /*!< Indicates KEY2 is locked */
+TFA9874_BF_CIMTP = 0xa360, /*!< Start copying data from I2C mtp registers to mtp */
+TFA9874_BF_MTPRDMSB = 0xa50f, /*!< MSB word of MTP manual read data */
+TFA9874_BF_MTPRDLSB = 0xa60f, /*!< LSB word of MTP manual read data */
+TFA9874_BF_EXTTS = 0xb108, /*!< External temperature (C) */
+TFA9874_BF_TROS = 0xb190, /*!< Select temp Speaker calibration */
+TFA9874_BF_SWPROFIL = 0xee0f, /*!< Software profile data */
+TFA9874_BF_SWVSTEP = 0xef0f, /*!< Software vstep information */
+TFA9874_BF_MTPOTC = 0xf000, /*!< Calibration schedule */
+TFA9874_BF_MTPEX = 0xf010, /*!< Calibration Ron executed */
+TFA9874_BF_DCMCCAPI = 0xf020, /*!< Calibration current limit DCDC */
+TFA9874_BF_DCMCCSB = 0xf030, /*!< Sign bit for delta calibration current limit DCDC */
+TFA9874_BF_USERDEF = 0xf042, /*!< Calibration delta current limit DCDC */
+TFA9874_BF_CUSTINFO = 0xf078, /*!< Reserved space for allowing customer to store speaker information */
+TFA9874_BF_R25C = 0xf50f, /*!< Ron resistance of speaker coil */
+} nxpTfa9874BfEnumList_t;
+#define TFA9874_NAMETABLE static tfaBfName_t Tfa9874DatasheetNames[] = {\
+{ 0x0, "PWDN"}, /* Powerdown selection , */\
+{ 0x10, "I2CR"}, /* I2C Reset - Auto clear , */\
+{ 0x30, "AMPE"}, /* Activate Amplifier , */\
+{ 0x40, "DCA"}, /* Activate DC-to-DC converter , */\
+{ 0x71, "INTP"}, /* Interrupt config , */\
+{ 0xb0, "BYPOCP"}, /* Bypass OCP , */\
+{ 0xc0, "TSTOCP"}, /* OCP testing control , */\
+{ 0x120, "MANSCONF"}, /* I2C configured , */\
+{ 0x140, "MANAOOSC"}, /* Internal osc off at PWDN , */\
+{ 0x1d0, "MUTETO"}, /* Time out SB mute sequence , */\
+{ 0x1e0, "OPENMTP"}, /* Control for FAIM protection , */\
+{ 0x203, "AUDFS"}, /* Sample rate (fs) , */\
+{ 0x240, "INPLEV"}, /* TDM output attenuation , */\
+{ 0x255, "FRACTDEL"}, /* V/I Fractional delay , */\
+{ 0x30f, "REV"}, /* Revision info , */\
+{ 0x401, "REFCKEXT"}, /* PLL external ref clock , */\
+{ 0x420, "REFCKSEL"}, /* PLL internal ref clock , */\
+{ 0x5c0, "SSFAIME"}, /* Sub-system FAIM , */\
+{ 0x802, "AMPOCRT"}, /* Amplifier on-off criteria for shutdown , */\
+{ 0x1000, "VDDS"}, /* POR , */\
+{ 0x1010, "DCOCPOK"}, /* DCDC OCP nmos (sticky register , clear on read) , */\
+{ 0x1020, "OTDS"}, /* OTP alarm (sticky register , clear on read) , */\
+{ 0x1030, "OCDS"}, /* OCP amplifier (sticky register , clear on read), */\
+{ 0x1040, "UVDS"}, /* UVP alarm (sticky register , clear on read) , */\
+{ 0x1050, "MANALARM"}, /* Alarm state , */\
+{ 0x1060, "TDMERR"}, /* TDM error , */\
+{ 0x1070, "NOCLK"}, /* Lost clock (sticky register , clear on read) , */\
+{ 0x1100, "DCIL"}, /* DCDC current limiting , */\
+{ 0x1110, "DCDCA"}, /* DCDC active (sticky register , clear on read) , */\
+{ 0x1130, "DCHVBAT"}, /* DCDC level 1x , */\
+{ 0x1140, "DCH114"}, /* DCDC level 1.14x , */\
+{ 0x1150, "DCH107"}, /* DCDC level 1.07x , */\
+{ 0x1160, "PLLS"}, /* PLL lock , */\
+{ 0x1170, "CLKS"}, /* Clocks stable , */\
+{ 0x1180, "TDMLUTER"}, /* TDM LUT error , */\
+{ 0x1192, "TDMSTAT"}, /* TDM status bits , */\
+{ 0x11c0, "MTPB"}, /* MTP busy , */\
+{ 0x11d0, "SWS"}, /* Amplifier engage , */\
+{ 0x11e0, "AMPS"}, /* Amplifier enable , */\
+{ 0x11f0, "AREFS"}, /* References enable , */\
+{ 0x1300, "OCPOAP"}, /* OCPOK pmos A , */\
+{ 0x1310, "OCPOAN"}, /* OCPOK nmos A , */\
+{ 0x1320, "OCPOBP"}, /* OCPOK pmos B , */\
+{ 0x1330, "OCPOBN"}, /* OCPOK nmos B , */\
+{ 0x1380, "OVDS"}, /* OVP alarm , */\
+{ 0x1390, "CLIPS"}, /* Amplifier clipping , */\
+{ 0x13a0, "ADCCR"}, /* Control ADC , */\
+{ 0x13c0, "MANWAIT1"}, /* Wait HW I2C settings , */\
+{ 0x13e0, "MANMUTE"}, /* Audio mute sequence , */\
+{ 0x13f0, "MANOPER"}, /* Operating state , */\
+{ 0x1420, "CLKOOR"}, /* External clock status , */\
+{ 0x1433, "MANSTATE"}, /* Device manager status , */\
+{ 0x1471, "DCMODE"}, /* DCDC mode status bits , */\
+{ 0x1509, "BATS"}, /* Battery voltage (V) , */\
+{ 0x1608, "TEMPS"}, /* IC Temperature (C) , */\
+{ 0x1709, "VDDPS"}, /* IC VDDP voltage ( 1023*VDDP/13 V) , */\
+{ 0x2040, "TDME"}, /* Enable interface , */\
+{ 0x2050, "TDMMODE"}, /* Slave/master , */\
+{ 0x2060, "TDMCLINV"}, /* Reception data to BCK clock , */\
+{ 0x2073, "TDMFSLN"}, /* FS length (master mode only) , */\
+{ 0x20b0, "TDMFSPOL"}, /* FS polarity , */\
+{ 0x20c3, "TDMNBCK"}, /* N-BCK's in FS , */\
+{ 0x2103, "TDMSLOTS"}, /* N-slots in Frame , */\
+{ 0x2144, "TDMSLLN"}, /* N-bits in slot , */\
+{ 0x2194, "TDMBRMG"}, /* N-bits remaining , */\
+{ 0x21e0, "TDMDEL"}, /* data delay to FS , */\
+{ 0x21f0, "TDMADJ"}, /* data adjustment , */\
+{ 0x2201, "TDMOOMP"}, /* Received audio compression , */\
+{ 0x2224, "TDMSSIZE"}, /* Sample size per slot , */\
+{ 0x2271, "TDMTXDFO"}, /* Format unused bits , */\
+{ 0x2291, "TDMTXUS0"}, /* Format unused slots DATAO , */\
+{ 0x2300, "TDMSPKE"}, /* Control audio tdm channel in 0 (spkr + dcdc) , */\
+{ 0x2310, "TDMDCE"}, /* Control audio tdm channel in 1 (dcdc) , */\
+{ 0x2330, "TDMCSE"}, /* current sense vbat temperature and vddp feedback , */\
+{ 0x2340, "TDMVSE"}, /* Voltage sense vbat temperature and vddp feedback , */\
+{ 0x2603, "TDMSPKS"}, /* tdm slot for sink 0 (speaker + dcdc) , */\
+{ 0x2643, "TDMDCS"}, /* tdm slot for sink 1 (dcdc) , */\
+{ 0x26c3, "TDMCSS"}, /* Slot Position of current sense vbat temperature and vddp feedback, */\
+{ 0x2703, "TDMVSS"}, /* Slot Position of Voltage sense vbat temperature and vddp feedback, */\
+{ 0x4000, "ISTVDDS"}, /* Status POR , */\
+{ 0x4010, "ISTBSTOC"}, /* Status DCDC OCP , */\
+{ 0x4020, "ISTOTDS"}, /* Status OTP alarm , */\
+{ 0x4030, "ISTOCPR"}, /* Status ocp alarm , */\
+{ 0x4040, "ISTUVDS"}, /* Status UVP alarm , */\
+{ 0x4050, "ISTMANALARM"}, /* Status nanager Alarm state , */\
+{ 0x4060, "ISTTDMER"}, /* Status tdm error , */\
+{ 0x4070, "ISTNOCLK"}, /* Status lost clock , */\
+{ 0x4400, "ICLVDDS"}, /* Clear POR , */\
+{ 0x4410, "ICLBSTOC"}, /* Clear DCDC OCP , */\
+{ 0x4420, "ICLOTDS"}, /* Clear OTP alarm , */\
+{ 0x4430, "ICLOCPR"}, /* Clear ocp alarm , */\
+{ 0x4440, "ICLUVDS"}, /* Clear UVP alarm , */\
+{ 0x4450, "ICLMANALARM"}, /* clear nanager Alarm state , */\
+{ 0x4460, "ICLTDMER"}, /* Clear tdm error , */\
+{ 0x4470, "ICLNOCLK"}, /* Clear lost clk , */\
+{ 0x4800, "IEVDDS"}, /* Enable por , */\
+{ 0x4810, "IEBSTOC"}, /* Enable DCDC OCP , */\
+{ 0x4820, "IEOTDS"}, /* Enable OTP alarm , */\
+{ 0x4830, "IEOCPR"}, /* Enable ocp alarm , */\
+{ 0x4840, "IEUVDS"}, /* Enable UVP alarm , */\
+{ 0x4850, "IEMANALARM"}, /* Enable nanager Alarm state , */\
+{ 0x4860, "IETDMER"}, /* Enable tdm error , */\
+{ 0x4870, "IENOCLK"}, /* Enable lost clk , */\
+{ 0x4c00, "IPOVDDS"}, /* Polarity por , */\
+{ 0x4c10, "IPOBSTOC"}, /* Polarity DCDC OCP , */\
+{ 0x4c20, "IPOOTDS"}, /* Polarity OTP alarm , */\
+{ 0x4c30, "IPOOCPR"}, /* Polarity ocp alarm , */\
+{ 0x4c40, "IPOUVDS"}, /* Polarity UVP alarm , */\
+{ 0x4c50, "IPOMANALARM"}, /* Polarity nanager Alarm state , */\
+{ 0x4c60, "IPOTDMER"}, /* Polarity tdm error , */\
+{ 0x4c70, "IPONOCLK"}, /* Polarity lost clk , */\
+{ 0x5001, "BSSCR"}, /* Battery Safeguard attack time , */\
+{ 0x5023, "BSST"}, /* Battery Safeguard threshold voltage level , */\
+{ 0x5061, "BSSRL"}, /* Battery Safeguard maximum reduction , */\
+{ 0x5080, "VBATFLTL"}, /* vbat filter limit , */\
+{ 0x50e0, "BSSR"}, /* Battery voltage read out , */\
+{ 0x50f0, "BSSBY"}, /* Bypass battery safeguard , */\
+{ 0x5100, "BSSS"}, /* Vbat prot steepness , */\
+{ 0x5150, "HPFBYP"}, /* Bypass HPF , */\
+{ 0x5170, "DPSA"}, /* Enable DPSA , */\
+{ 0x5222, "CLIPCTRL"}, /* Clip control setting , */\
+{ 0x5257, "AMPGAIN"}, /* Amplifier gain , */\
+{ 0x52d0, "SLOPEE"}, /* Enables slope control , */\
+{ 0x52e0, "SLOPESET"}, /* Slope speed setting (bin. coded) , */\
+{ 0x6123, "TDMDCG"}, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */\
+{ 0x6163, "TDMSPKG"}, /* Total gain depending on INPLEV setting (channel 0), */\
+{ 0x62e1, "LNMODE"}, /* ctrl select mode , */\
+{ 0x64e1, "LPM1MODE"}, /* low power mode control , */\
+{ 0x6802, "TDMSRCMAP"}, /* tdm source mapping , */\
+{ 0x6831, "TDMSRCAS"}, /* Sensed value A , */\
+{ 0x6851, "TDMSRCBS"}, /* Sensed value B , */\
+{ 0x6871, "TDMSRCACLIP"}, /* clip information (analog /digital) for source0 , */\
+{ 0x6891, "TDMSRCBCLIP"}, /* clip information (analog /digital) for source1 , */\
+{ 0x6e10, "LP1"}, /* low power mode 1 detection , */\
+{ 0x6e20, "LA"}, /* low amplitude detection , */\
+{ 0x6e30, "VDDPH"}, /* vddp greater than vbat , */\
+{ 0x6f02, "DELCURCOMP"}, /* delay to allign compensation signal with current sense signal, */\
+{ 0x6f40, "SIGCURCOMP"}, /* polarity of compensation for current sense , */\
+{ 0x6f50, "ENCURCOMP"}, /* enable current sense compensation , */\
+{ 0x6f72, "LVLCLPPWM"}, /* set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
+{ 0x7033, "DCMCC"}, /* Max coil current , */\
+{ 0x7071, "DCCV"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
+{ 0x7090, "DCIE"}, /* Adaptive boost mode , */\
+{ 0x70a0, "DCSR"}, /* Soft ramp up/down , */\
+{ 0x70e0, "DCDIS"}, /* DCDC on/off , */\
+{ 0x70f0, "DCPWM"}, /* DCDC PWM only mode , */\
+{ 0x7430, "DCTRACK"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
+{ 0x7444, "DCTRIP"}, /* 1st Adaptive boost trip levels, effective only when DCIE is set to 1, */\
+{ 0x7494, "DCHOLD"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
+{ 0x74e0, "DCINT"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
+{ 0x7534, "DCTRIP2"}, /* 2nd Adaptive boost trip levels, effective only when DCIE is set to 1, */\
+{ 0x7584, "DCTRIPT"}, /* Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
+{ 0x75f0, "DCTRIPHYSTE"}, /* Enable hysteresis on booster trip levels , */\
+{ 0x7635, "DCVOF"}, /* First boost voltage level , */\
+{ 0x7695, "DCVOS"}, /* Second boost voltage level , */\
+{ 0xa107, "MTPK"}, /* MTP KEY2 register , */\
+{ 0xa200, "KEY1LOCKED"}, /* Indicates KEY1 is locked , */\
+{ 0xa210, "KEY2LOCKED"}, /* Indicates KEY2 is locked , */\
+{ 0xa360, "CIMTP"}, /* Start copying data from I2C mtp registers to mtp , */\
+{ 0xa50f, "MTPRDMSB"}, /* MSB word of MTP manual read data , */\
+{ 0xa60f, "MTPRDLSB"}, /* LSB word of MTP manual read data , */\
+{ 0xb108, "EXTTS"}, /* External temperature (C) , */\
+{ 0xb190, "TROS"}, /* Select temp Speaker calibration , */\
+{ 0xee0f, "SWPROFIL"}, /* Software profile data , */\
+{ 0xef0f, "SWVSTEP"}, /* Software vstep information , */\
+{ 0xf000, "MTPOTC"}, /* Calibration schedule , */\
+{ 0xf010, "MTPEX"}, /* Calibration Ron executed , */\
+{ 0xf020, "DCMCCAPI"}, /* Calibration current limit DCDC , */\
+{ 0xf030, "DCMCCSB"}, /* Sign bit for delta calibration current limit DCDC , */\
+{ 0xf042, "USERDEF"}, /* Calibration delta current limit DCDC , */\
+{ 0xf078, "CUSTINFO"}, /* Reserved space for allowing customer to store speaker information, */\
+{ 0xf50f, "R25C"}, /* Ron resistance of speaker coil , */\
+{ 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+
+#define TFA9874_BITNAMETABLE static tfaBfName_t Tfa9874BitNames[] = {\
+{ 0x0, "powerdown"}, /* Powerdown selection , */\
+{ 0x10, "reset"}, /* I2C Reset - Auto clear , */\
+{ 0x30, "enbl_amplifier"}, /* Activate Amplifier , */\
+{ 0x40, "enbl_boost"}, /* Activate DC-to-DC converter , */\
+{ 0x71, "int_pad_io"}, /* Interrupt config , */\
+{ 0xb0, "bypass_ocp"}, /* Bypass OCP , */\
+{ 0xc0, "test_ocp"}, /* OCP testing control , */\
+{ 0x120, "src_set_configured"}, /* I2C configured , */\
+{ 0x140, "enbl_osc1m_auto_off"}, /* Internal osc off at PWDN , */\
+{ 0x1d0, "disable_mute_time_out"}, /* Time out SB mute sequence , */\
+{ 0x1e0, "unprotect_faim"}, /* Control for FAIM protection , */\
+{ 0x203, "audio_fs"}, /* Sample rate (fs) , */\
+{ 0x240, "input_level"}, /* TDM output attenuation , */\
+{ 0x255, "cs_frac_delay"}, /* V/I Fractional delay , */\
+{ 0x2d0, "sel_hysteresis"}, /* Select hysteresis for clock range detector , */\
+{ 0x30f, "device_rev"}, /* Revision info , */\
+{ 0x401, "pll_clkin_sel"}, /* PLL external ref clock , */\
+{ 0x420, "pll_clkin_sel_osc"}, /* PLL internal ref clock , */\
+{ 0x5c0, "enbl_faim_ss"}, /* Sub-system FAIM , */\
+{ 0x802, "ctrl_on2off_criterion"}, /* Amplifier on-off criteria for shutdown , */\
+{ 0xe07, "ctrl_digtoana"}, /* Spare control from digital to analog , */\
+{ 0xf0f, "hidden_code"}, /* 5A6Bh, 23147d to access registers (default for engineering), */\
+{ 0x1000, "flag_por"}, /* POR , */\
+{ 0x1010, "flag_bst_ocpok"}, /* DCDC OCP nmos (sticky register , clear on read) , */\
+{ 0x1020, "flag_otpok"}, /* OTP alarm (sticky register , clear on read) , */\
+{ 0x1030, "flag_ocp_alarm"}, /* OCP amplifier (sticky register , clear on read), */\
+{ 0x1040, "flag_uvpok"}, /* UVP alarm (sticky register , clear on read) , */\
+{ 0x1050, "flag_man_alarm_state"}, /* Alarm state , */\
+{ 0x1060, "flag_tdm_error"}, /* TDM error , */\
+{ 0x1070, "flag_lost_clk"}, /* Lost clock (sticky register , clear on read) , */\
+{ 0x1100, "flag_bst_bstcur"}, /* DCDC current limiting , */\
+{ 0x1110, "flag_bst_hiz"}, /* DCDC active (sticky register , clear on read) , */\
+{ 0x1120, "flag_bst_peakcur"}, /* Indicates current is max in DC-to-DC converter , */\
+{ 0x1130, "flag_bst_voutcomp"}, /* DCDC level 1x , */\
+{ 0x1140, "flag_bst_voutcomp86"}, /* DCDC level 1.14x , */\
+{ 0x1150, "flag_bst_voutcomp93"}, /* DCDC level 1.07x , */\
+{ 0x1160, "flag_pll_lock"}, /* PLL lock , */\
+{ 0x1170, "flag_clocks_stable"}, /* Clocks stable , */\
+{ 0x1180, "flag_tdm_lut_error"}, /* TDM LUT error , */\
+{ 0x1192, "flag_tdm_status"}, /* TDM status bits , */\
+{ 0x11c0, "flag_mtp_busy"}, /* MTP busy , */\
+{ 0x11d0, "flag_engage"}, /* Amplifier engage , */\
+{ 0x11e0, "flag_enbl_amp"}, /* Amplifier enable , */\
+{ 0x11f0, "flag_enbl_ref"}, /* References enable , */\
+{ 0x1300, "flag_ocpokap"}, /* OCPOK pmos A , */\
+{ 0x1310, "flag_ocpokan"}, /* OCPOK nmos A , */\
+{ 0x1320, "flag_ocpokbp"}, /* OCPOK pmos B , */\
+{ 0x1330, "flag_ocpokbn"}, /* OCPOK nmos B , */\
+{ 0x1380, "flag_ovpok"}, /* OVP alarm , */\
+{ 0x1390, "flag_clip"}, /* Amplifier clipping , */\
+{ 0x13a0, "flag_adc10_ready"}, /* Control ADC , */\
+{ 0x13c0, "flag_man_wait_src_settings"}, /* Wait HW I2C settings , */\
+{ 0x13e0, "flag_man_start_mute_audio"}, /* Audio mute sequence , */\
+{ 0x13f0, "flag_man_operating_state"}, /* Operating state , */\
+{ 0x1420, "flag_clk_out_of_range"}, /* External clock status , */\
+{ 0x1433, "man_state"}, /* Device manager status , */\
+{ 0x1471, "status_bst_mode"}, /* DCDC mode status bits , */\
+{ 0x1509, "bat_adc"}, /* Battery voltage (V) , */\
+{ 0x1608, "temp_adc"}, /* IC Temperature (C) , */\
+{ 0x1709, "vddp_adc"}, /* IC VDDP voltage ( 1023*VDDP/13 V) , */\
+{ 0x2040, "tdm_enable"}, /* Enable interface , */\
+{ 0x2050, "tdm_mode"}, /* Slave/master , */\
+{ 0x2060, "tdm_clk_inversion"}, /* Reception data to BCK clock , */\
+{ 0x2073, "tdm_fs_ws_length"}, /* FS length (master mode only) , */\
+{ 0x20b0, "tdm_fs_ws_polarity"}, /* FS polarity , */\
+{ 0x20c3, "tdm_nbck"}, /* N-BCK's in FS , */\
+{ 0x2103, "tdm_nb_of_slots"}, /* N-slots in Frame , */\
+{ 0x2144, "tdm_slot_length"}, /* N-bits in slot , */\
+{ 0x2194, "tdm_bits_remaining"}, /* N-bits remaining , */\
+{ 0x21e0, "tdm_data_delay"}, /* data delay to FS , */\
+{ 0x21f0, "tdm_data_adjustment"}, /* data adjustment , */\
+{ 0x2201, "tdm_audio_sample_compression"}, /* Received audio compression , */\
+{ 0x2224, "tdm_sample_size"}, /* Sample size per slot , */\
+{ 0x2271, "tdm_txdata_format"}, /* Format unused bits , */\
+{ 0x2291, "tdm_txdata_format_unused_slot_sd0"}, /* Format unused slots DATAO , */\
+{ 0x2300, "tdm_sink0_enable"}, /* Control audio tdm channel in 0 (spkr + dcdc) , */\
+{ 0x2310, "tdm_sink1_enable"}, /* Control audio tdm channel in 1 (dcdc) , */\
+{ 0x2330, "tdm_source0_enable"}, /* current sense vbat temperature and vddp feedback , */\
+{ 0x2340, "tdm_source1_enable"}, /* Voltage sense vbat temperature and vddp feedback , */\
+{ 0x2603, "tdm_sink0_slot"}, /* tdm slot for sink 0 (speaker + dcdc) , */\
+{ 0x2643, "tdm_sink1_slot"}, /* tdm slot for sink 1 (dcdc) , */\
+{ 0x26c3, "tdm_source0_slot"}, /* Slot Position of current sense vbat temperature and vddp feedback, */\
+{ 0x2703, "tdm_source1_slot"}, /* Slot Position of Voltage sense vbat temperature and vddp feedback, */\
+{ 0x4000, "int_out_flag_por"}, /* Status POR , */\
+{ 0x4010, "int_out_flag_bst_ocpok"}, /* Status DCDC OCP , */\
+{ 0x4020, "int_out_flag_otpok"}, /* Status OTP alarm , */\
+{ 0x4030, "int_out_flag_ocp_alarm"}, /* Status ocp alarm , */\
+{ 0x4040, "int_out_flag_uvpok"}, /* Status UVP alarm , */\
+{ 0x4050, "int_out_flag_man_alarm_state"}, /* Status nanager Alarm state , */\
+{ 0x4060, "int_out_flag_tdm_error"}, /* Status tdm error , */\
+{ 0x4070, "int_out_flag_lost_clk"}, /* Status lost clock , */\
+{ 0x4400, "int_in_flag_por"}, /* Clear POR , */\
+{ 0x4410, "int_in_flag_bst_ocpok"}, /* Clear DCDC OCP , */\
+{ 0x4420, "int_in_flag_otpok"}, /* Clear OTP alarm , */\
+{ 0x4430, "int_in_flag_ocp_alarm"}, /* Clear ocp alarm , */\
+{ 0x4440, "int_in_flag_uvpok"}, /* Clear UVP alarm , */\
+{ 0x4450, "int_in_flag_man_alarm_state"}, /* clear nanager Alarm state , */\
+{ 0x4460, "int_in_flag_tdm_error"}, /* Clear tdm error , */\
+{ 0x4470, "int_in_flag_lost_clk"}, /* Clear lost clk , */\
+{ 0x4800, "int_enable_flag_por"}, /* Enable por , */\
+{ 0x4810, "int_enable_flag_bst_ocpok"}, /* Enable DCDC OCP , */\
+{ 0x4820, "int_enable_flag_otpok"}, /* Enable OTP alarm , */\
+{ 0x4830, "int_enable_flag_ocp_alarm"}, /* Enable ocp alarm , */\
+{ 0x4840, "int_enable_flag_uvpok"}, /* Enable UVP alarm , */\
+{ 0x4850, "int_enable_flag_man_alarm_state"}, /* Enable nanager Alarm state , */\
+{ 0x4860, "int_enable_flag_tdm_error"}, /* Enable tdm error , */\
+{ 0x4870, "int_enable_flag_lost_clk"}, /* Enable lost clk , */\
+{ 0x4c00, "int_polarity_flag_por"}, /* Polarity por , */\
+{ 0x4c10, "int_polarity_flag_bst_ocpok"}, /* Polarity DCDC OCP , */\
+{ 0x4c20, "int_polarity_flag_otpok"}, /* Polarity OTP alarm , */\
+{ 0x4c30, "int_polarity_flag_ocp_alarm"}, /* Polarity ocp alarm , */\
+{ 0x4c40, "int_polarity_flag_uvpok"}, /* Polarity UVP alarm , */\
+{ 0x4c50, "int_polarity_flag_man_alarm_state"}, /* Polarity nanager Alarm state , */\
+{ 0x4c60, "int_polarity_flag_tdm_error"}, /* Polarity tdm error , */\
+{ 0x4c70, "int_polarity_flag_lost_clk"}, /* Polarity lost clk , */\
+{ 0x5001, "vbat_prot_attack_time"}, /* Battery Safeguard attack time , */\
+{ 0x5023, "vbat_prot_thlevel"}, /* Battery Safeguard threshold voltage level , */\
+{ 0x5061, "vbat_prot_max_reduct"}, /* Battery Safeguard maximum reduction , */\
+{ 0x5080, "vbat_flt_limit"}, /* vbat filter limit , */\
+{ 0x50d0, "rst_min_vbat"}, /* Reset clipper - Auto clear , */\
+{ 0x50e0, "sel_vbat"}, /* Battery voltage read out , */\
+{ 0x50f0, "bypass_clipper"}, /* Bypass battery safeguard , */\
+{ 0x5100, "batsense_steepness"}, /* Vbat prot steepness , */\
+{ 0x5150, "bypass_hp"}, /* Bypass HPF , */\
+{ 0x5170, "enbl_dpsa"}, /* Enable DPSA , */\
+{ 0x5222, "ctrl_cc"}, /* Clip control setting , */\
+{ 0x5257, "gain"}, /* Amplifier gain , */\
+{ 0x52d0, "ctrl_slopectrl"}, /* Enables slope control , */\
+{ 0x52e0, "ctrl_slope"}, /* Slope speed setting (bin. coded) , */\
+{ 0x5301, "dpsa_level"}, /* DPSA threshold levels , */\
+{ 0x5321, "dpsa_release"}, /* DPSA Release time , */\
+{ 0x5340, "clipfast"}, /* Clock selection for HW clipper for Battery Safeguard, */\
+{ 0x5350, "bypass_lp"}, /* Bypass the low power filter inside temperature sensor, */\
+{ 0x5400, "first_order_mode"}, /* Overrule to 1st order mode of control stage when clipping, */\
+{ 0x5410, "bypass_ctrlloop"}, /* Switch amplifier into open loop configuration , */\
+{ 0x5430, "icomp_engage"}, /* Engage of icomp , */\
+{ 0x5440, "ctrl_kickback"}, /* Prevent double pulses of output stage , */\
+{ 0x5450, "icomp_engage_overrule"}, /* To overrule the functional icomp_engage signal during validation, */\
+{ 0x5503, "ctrl_dem"}, /* Enable DEM icomp and DEM one bit dac , */\
+{ 0x5543, "ctrl_dem_mismatch"}, /* Enable DEM icomp mismatch for testing , */\
+{ 0x5582, "dpsa_drive"}, /* Drive setting (bin. coded) , */\
+{ 0x5690, "sel_pwm_delay_src"}, /* Control for selection for PWM delay line source , */\
+{ 0x56a1, "enbl_odd_up_even_down"}, /* Control for PWM reference sawtooth generartion , */\
+{ 0x570a, "enbl_amp"}, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually, */\
+{ 0x57b0, "enbl_engage"}, /* Enables/engage power stage and control loop , */\
+{ 0x57c0, "enbl_engage_pst"}, /* Enables/engage power stage and control loop , */\
+{ 0x5810, "hard_mute"}, /* Hard mute - PWM , */\
+{ 0x5820, "pwm_shape"}, /* PWM shape , */\
+{ 0x5844, "pwm_delay"}, /* PWM delay bits to set the delay, clockd is 1/(k*2048*fs), */\
+{ 0x5890, "reclock_pwm"}, /* Reclock the pwm signal inside analog , */\
+{ 0x58a0, "reclock_voltsense"}, /* Reclock the voltage sense pwm signal , */\
+{ 0x58c0, "enbl_pwm_phase_shift"}, /* Control for pwm phase shift , */\
+{ 0x6123, "ctrl_attl"}, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */\
+{ 0x6163, "ctrl_attr"}, /* Total gain depending on INPLEV setting (channel 0), */\
+{ 0x6265, "zero_lvl"}, /* low noise gain switch zero trigger level , */\
+{ 0x62c1, "ctrl_fb_resistor"}, /* Select amplifier feedback resistor connection , */\
+{ 0x62e1, "lownoisegain_mode"}, /* ctrl select mode , */\
+{ 0x6305, "threshold_lvl"}, /* low noise gain switch trigger level , */\
+{ 0x6365, "hold_time"}, /* ctrl hold time before low audio is reckoned to be low audio, */\
+{ 0x6405, "lpm1_cal_offset"}, /* low power mode1 detector ctrl cal_offset from gain module , */\
+{ 0x6465, "lpm1_zero_lvl"}, /* low power mode1 zero crossing detection level , */\
+{ 0x64e1, "lpm1_mode"}, /* low power mode control , */\
+{ 0x6505, "lpm1_threshold_lvl"}, /* low power mode1 amplitude trigger level , */\
+{ 0x6565, "lpm1_hold_time"}, /* low power mode1 detector ctrl hold time before low audio is reckoned to be low audio, */\
+{ 0x65c0, "disable_low_power_mode"}, /* low power mode1 detector control , */\
+{ 0x6600, "dcdc_pfm20khz_limit"}, /* DCDC in PFM mode pwm mode is activated each 50us to force a pwm pulse, */\
+{ 0x6611, "dcdc_ctrl_maxzercnt"}, /* DCDC. Number of zero current flags to count before going to pfm mode, */\
+{ 0x6656, "dcdc_vbat_delta_detect"}, /* Threshold before booster is reacting on a delta Vbat (in PFM mode) by temporarily switching to PWM mode, */\
+{ 0x66c0, "dcdc_ignore_vbat"}, /* Ignore an increase on Vbat , */\
+{ 0x6700, "enbl_minion"}, /* Enables minion (small) power stage , */\
+{ 0x6713, "vth_vddpvbat"}, /* select vddp-vbat thres signal , */\
+{ 0x6750, "lpen_vddpvbat"}, /* select vddp-vbat filtred vs unfiltered compare , */\
+{ 0x6761, "ctrl_rfb"}, /* Feedback resistor selection - I2C direct mode , */\
+{ 0x6802, "tdm_source_mapping"}, /* tdm source mapping , */\
+{ 0x6831, "tdm_sourcea_frame_sel"}, /* Sensed value A , */\
+{ 0x6851, "tdm_sourceb_frame_sel"}, /* Sensed value B , */\
+{ 0x6871, "tdm_source0_clip_sel"}, /* clip information (analog /digital) for source0 , */\
+{ 0x6891, "tdm_source1_clip_sel"}, /* clip information (analog /digital) for source1 , */\
+{ 0x6a02, "rst_min_vbat_delay"}, /* rst_min_vbat delay (nb fs) , */\
+{ 0x6b00, "disable_auto_engage"}, /* disable auto engange , */\
+{ 0x6b10, "disable_engage"}, /* disable engange , */\
+{ 0x6c02, "ns_hp2ln_criterion"}, /* 0..7 zeroes at ns as threshold to swap from high_power to low_noise, */\
+{ 0x6c32, "ns_ln2hp_criterion"}, /* 0..7 zeroes at ns as threshold to swap from low_noise to high_power, */\
+{ 0x6c69, "spare_out"}, /* spare_out , */\
+{ 0x6d0f, "spare_in"}, /* spare_in , */\
+{ 0x6e10, "flag_lp_detect_mode1"}, /* low power mode 1 detection , */\
+{ 0x6e20, "flag_low_amplitude"}, /* low amplitude detection , */\
+{ 0x6e30, "flag_vddp_gt_vbat"}, /* vddp greater than vbat , */\
+{ 0x6f02, "cursense_comp_delay"}, /* delay to allign compensation signal with current sense signal, */\
+{ 0x6f40, "cursense_comp_sign"}, /* polarity of compensation for current sense , */\
+{ 0x6f50, "enbl_cursense_comp"}, /* enable current sense compensation , */\
+{ 0x6f72, "pwms_clip_lvl"}, /* set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
+{ 0x7033, "boost_cur"}, /* Max coil current , */\
+{ 0x7071, "bst_slpcmplvl"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
+{ 0x7090, "boost_intel"}, /* Adaptive boost mode , */\
+{ 0x70a0, "boost_speed"}, /* Soft ramp up/down , */\
+{ 0x70e0, "dcdcoff_mode"}, /* DCDC on/off , */\
+{ 0x70f0, "dcdc_pwmonly"}, /* DCDC PWM only mode , */\
+{ 0x7104, "bst_drive"}, /* Binary coded drive setting for boost converter power stage, */\
+{ 0x7151, "bst_scalecur"}, /* For testing direct control scale current , */\
+{ 0x7174, "bst_slopecur"}, /* For testing direct control slope current , */\
+{ 0x71c1, "bst_slope"}, /* Boost slope speed , */\
+{ 0x71e0, "bst_bypass_bstcur"}, /* Bypass control for boost current settings , */\
+{ 0x71f0, "bst_bypass_bstfoldback"}, /* Bypass control for boost foldback , */\
+{ 0x7200, "enbl_bst_engage"}, /* Enable power stage dcdc controller , */\
+{ 0x7210, "enbl_bst_hizcom"}, /* Enable hiz comparator , */\
+{ 0x7220, "enbl_bst_peak2avg"}, /* Enable boost peak2avg functionality , */\
+{ 0x7230, "enbl_bst_peakcur"}, /* Enable peak current , */\
+{ 0x7240, "enbl_bst_power"}, /* Enable line of the powerstage , */\
+{ 0x7250, "enbl_bst_slopecur"}, /* Enable bit of max-current dac , */\
+{ 0x7260, "enbl_bst_voutcomp"}, /* Enable vout comparators , */\
+{ 0x7270, "enbl_bst_voutcomp86"}, /* Enable vout-86 comparators , */\
+{ 0x7280, "enbl_bst_voutcomp93"}, /* Enable vout-93 comparators , */\
+{ 0x7290, "enbl_bst_windac"}, /* Enable window dac , */\
+{ 0x72a5, "bst_windac"}, /* for testing direct control windac , */\
+{ 0x7300, "boost_alg"}, /* Control for boost adaptive loop gain , */\
+{ 0x7311, "boost_loopgain"}, /* DCDC boost loopgain setting , */\
+{ 0x7331, "bst_freq"}, /* DCDC boost frequency control , */\
+{ 0x7360, "bst_use_new_zercur_detect"}, /* Enable new zero current detection for boost control, */\
+{ 0x7430, "boost_track"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
+{ 0x7444, "boost_trip_lvl_1st"}, /* 1st Adaptive boost trip levels, effective only when DCIE is set to 1, */\
+{ 0x7494, "boost_hold_time"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
+{ 0x74e0, "sel_dcdc_envelope_8fs"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
+{ 0x74f0, "ignore_flag_voutcomp86"}, /* Determines the maximum PWM frequency be the most efficient in relation to the Booster inductor value, */\
+{ 0x7534, "boost_trip_lvl_2nd"}, /* 2nd Adaptive boost trip levels, effective only when DCIE is set to 1, */\
+{ 0x7584, "boost_trip_lvl_track"}, /* Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
+{ 0x75f0, "enbl_trip_hyst"}, /* Enable hysteresis on booster trip levels , */\
+{ 0x7635, "frst_boost_voltage"}, /* First boost voltage level , */\
+{ 0x7695, "scnd_boost_voltage"}, /* Second boost voltage level , */\
+{ 0x8001, "sel_clk_cs"}, /* Current sense clock duty cycle control , */\
+{ 0x8021, "micadc_speed"}, /* Current sense clock for MiCADC selection - 32/44.1/48 KHz Fs band only, */\
+{ 0x8050, "cs_gain_control"}, /* Current sense gain control , */\
+{ 0x8060, "cs_bypass_gc"}, /* Bypasses the CS gain correction , */\
+{ 0x8087, "cs_gain"}, /* Current sense gain , */\
+{ 0x8210, "invertpwm"}, /* Current sense common mode feedback pwm invert control, */\
+{ 0x8305, "cs_ktemp"}, /* Current sense temperature compensation trimming (1 - VALUE*TEMP)*signal, */\
+{ 0x8364, "cs_ktemp2"}, /* Second order temperature compensation coefficient , */\
+{ 0x8400, "cs_adc_bsoinv"}, /* Bitstream inversion for current sense ADC , */\
+{ 0x8421, "cs_adc_hifreq"}, /* Frequency mode current sense ADC , */\
+{ 0x8440, "cs_adc_nortz"}, /* Return to zero for current sense ADC , */\
+{ 0x8453, "cs_adc_offset"}, /* Micadc ADC offset setting , */\
+{ 0x8490, "cs_adc_slowdel"}, /* Select delay for current sense ADC (internal decision circuitry), */\
+{ 0x84a4, "cs_adc_gain"}, /* Gain setting for current sense ADC (two's complement), */\
+{ 0x8500, "cs_resonator_enable"}, /* Enable for resonator to improve SRN , */\
+{ 0x8510, "cs_classd_tran_skip"}, /* Skip current sense connection during a classD amplifier transition, */\
+{ 0x8530, "cs_inn_short"}, /* Short current sense negative to common mode , */\
+{ 0x8540, "cs_inp_short"}, /* Short current sense positive to common mode , */\
+{ 0x8550, "cs_ldo_bypass"}, /* Bypass current sense LDO , */\
+{ 0x8560, "cs_ldo_pulldown"}, /* Pull down current sense LDO, only valid if left_enbl_cs_ldo is high, */\
+{ 0x8574, "cs_ldo_voset"}, /* Current sense LDO voltage level setting (two's complement), */\
+{ 0x8700, "enbl_cs_adc"}, /* Enable current sense ADC , */\
+{ 0x8710, "enbl_cs_inn1"}, /* Enable connection of current sense negative1 , */\
+{ 0x8720, "enbl_cs_inn2"}, /* Enable connection of current sense negative2 , */\
+{ 0x8730, "enbl_cs_inp1"}, /* Enable connection of current sense positive1 , */\
+{ 0x8740, "enbl_cs_inp2"}, /* Enable connection of current sense positive2 , */\
+{ 0x8750, "enbl_cs_ldo"}, /* Enable current sense LDO , */\
+{ 0x8780, "enbl_cs_vbatldo"}, /* Enable of current sense LDO , */\
+{ 0x8790, "enbl_dc_filter"}, /* Control for enabling the DC blocking filter for voltage and current sense, */\
+{ 0x8801, "volsense_pwm_sel"}, /* Voltage sense source selection control , */\
+{ 0x8850, "vs_gain_control"}, /* Voltage sense gain control , */\
+{ 0x8860, "vs_bypass_gc"}, /* Bypasses the VS gain correction , */\
+{ 0x8870, "vs_igen_supply"}, /* Switch internal supply of current generator , */\
+{ 0x8887, "vs_gain"}, /* voltage sense gain , */\
+{ 0x8c00, "vs_adc_bsoinv"}, /* Bitstream inversion for voltage sense ADC , */\
+{ 0x8c40, "vs_adc_nortz"}, /* Return to zero for voltage sense ADC , */\
+{ 0x8c90, "vs_adc_slowdel"}, /* Select delay for voltage sense ADC (internal decision circuitry), */\
+{ 0x8d10, "vs_classd_tran_skip"}, /* Skip voltage sense connection during a classD amplifier transition, */\
+{ 0x8d30, "vs_inn_short"}, /* Short voltage sense negative to common mode , */\
+{ 0x8d40, "vs_inp_short"}, /* Short voltage sense positive to common mode , */\
+{ 0x8d50, "vs_ldo_bypass"}, /* Bypass voltage sense LDO , */\
+{ 0x8d60, "vs_ldo_pulldown"}, /* Pull down voltage sense LDO, only valid if left_enbl_cs_ldo is high, */\
+{ 0x8d74, "vs_ldo_voset"}, /* Voltage sense LDO voltage level setting (two's complement), */\
+{ 0x8f00, "enbl_vs_adc"}, /* Enable voltage sense ADC (Direct Control only only others done by manager), */\
+{ 0x8f10, "enbl_vs_inn1"}, /* Enable connection of voltage sense negative1 , */\
+{ 0x8f20, "enbl_vs_inn2"}, /* Enable connection of voltage sense negative2 , */\
+{ 0x8f30, "enbl_vs_inp1"}, /* Enable connection of voltage sense positive1 , */\
+{ 0x8f40, "enbl_vs_inp2"}, /* Enable connection of voltage sense positive2 , */\
+{ 0x8f50, "enbl_vs_ldo"}, /* Enable voltage sense LDO (Direct Control only only others done by manager), */\
+{ 0x8f80, "enbl_vs_vbatldo"}, /* Enable of voltage sense LDO (Direct Control only others done by manager), */\
+{ 0xa007, "mtpkey1"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
+{ 0xa107, "mtpkey2"}, /* MTP KEY2 register , */\
+{ 0xa200, "key01_locked"}, /* Indicates KEY1 is locked , */\
+{ 0xa210, "key02_locked"}, /* Indicates KEY2 is locked , */\
+{ 0xa302, "mtp_man_address_in"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
+{ 0xa330, "man_copy_mtp_to_iic"}, /* Start copying single word from mtp to I2C mtp register, */\
+{ 0xa340, "man_copy_iic_to_mtp"}, /* Start copying single word from I2C mtp register to mtp, */\
+{ 0xa350, "auto_copy_mtp_to_iic"}, /* Start copying all the data from mtp to I2C mtp registers, */\
+{ 0xa360, "auto_copy_iic_to_mtp"}, /* Start copying data from I2C mtp registers to mtp , */\
+{ 0xa400, "faim_set_clkws"}, /* Sets the faim controller clock wait state register, */\
+{ 0xa410, "faim_sel_evenrows"}, /* All even rows of the faim are selected, active high, */\
+{ 0xa420, "faim_sel_oddrows"}, /* All odd rows of the faim are selected, all rows in combination with sel_evenrows, */\
+{ 0xa430, "faim_program_only"}, /* Skip the erase access at wr_faim command (write-program-marginread), */\
+{ 0xa440, "faim_erase_only"}, /* Skip the program access at wr_faim command (write-erase-marginread), */\
+{ 0xa50f, "mtp_man_data_out_msb"}, /* MSB word of MTP manual read data , */\
+{ 0xa60f, "mtp_man_data_out_lsb"}, /* LSB word of MTP manual read data , */\
+{ 0xa70f, "mtp_man_data_in_msb"}, /* MSB word of write data for MTP manual write , */\
+{ 0xa80f, "mtp_man_data_in_lsb"}, /* LSB word of write data for MTP manual write , */\
+{ 0xb010, "bypass_ocpcounter"}, /* Bypass OCP Counter , */\
+{ 0xb020, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
+{ 0xb030, "bypass_ovp"}, /* Bypass OVP , */\
+{ 0xb040, "bypass_uvp"}, /* Bypass UVP , */\
+{ 0xb050, "bypass_otp"}, /* Bypass OTP , */\
+{ 0xb060, "bypass_lost_clk"}, /* Bypass lost clock detector , */\
+{ 0xb070, "ctrl_vpalarm"}, /* vpalarm (uvp ovp handling) , */\
+{ 0xb087, "ocp_threshold"}, /* OCP threshold level , */\
+{ 0xb108, "ext_temp"}, /* External temperature (C) , */\
+{ 0xb190, "ext_temp_sel"}, /* Select temp Speaker calibration , */\
+{ 0xc000, "use_direct_ctrls"}, /* Direct control to overrule several functions for testing, */\
+{ 0xc010, "rst_datapath"}, /* Direct control for datapath reset , */\
+{ 0xc020, "rst_cgu"}, /* Direct control for cgu reset , */\
+{ 0xc038, "enbl_ref"}, /* Switch on the analog references, each part of the references can be switched on/off individually, */\
+{ 0xc0c0, "use_direct_vs_ctrls"}, /* voltage sense Direct control to overrule several functions for testing, */\
+{ 0xc0d0, "enbl_ringo"}, /* Enable the ring oscillator for test purpose , */\
+{ 0xc0e0, "use_direct_clk_ctrl"}, /* Direct clock control to overrule several functions for testing, */\
+{ 0xc0f0, "use_direct_pll_ctrl"}, /* Direct PLL control to overrule several functions for testing, */\
+{ 0xc100, "enbl_tsense"}, /* Temperature sensor enable control - I2C direct mode, */\
+{ 0xc110, "tsense_hibias"}, /* Bit to set the biasing in temp sensor to high , */\
+{ 0xc120, "enbl_flag_vbg"}, /* Enable flagging of bandgap out of control , */\
+{ 0xc20f, "abist_offset"}, /* Offset control for ABIST testing (two's complement), */\
+{ 0xc300, "bypasslatch"}, /* Bypass latch , */\
+{ 0xc311, "sourcea"}, /* Set OUTA to , */\
+{ 0xc331, "sourceb"}, /* Set OUTB to , */\
+{ 0xc350, "inverta"}, /* Invert pwma test signal , */\
+{ 0xc360, "invertb"}, /* Invert pwmb test signal , */\
+{ 0xc374, "pulselength"}, /* Pulse length setting test input for amplifier (clock d - k*2048*fs), */\
+{ 0xc3c0, "tdm_enable_loopback"}, /* TDM loopback test , */\
+{ 0xc400, "bst_bypasslatch"}, /* Bypass latch in boost converter , */\
+{ 0xc411, "bst_source"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
+{ 0xc430, "bst_invertb"}, /* Invert pwmbst test signal , */\
+{ 0xc444, "bst_pulselength"}, /* Pulse length setting test input for boost converter , */\
+{ 0xc490, "test_bst_ctrlsthv"}, /* Test mode for boost control stage , */\
+{ 0xc4a0, "test_bst_iddq"}, /* IDDQ testing in power stage of boost converter , */\
+{ 0xc4b0, "test_bst_rdson"}, /* RDSON testing - boost power stage , */\
+{ 0xc4c0, "test_bst_cvi"}, /* CVI testing - boost power stage , */\
+{ 0xc4d0, "test_bst_ocp"}, /* Boost OCP. For old ocp (ctrl_reversebst is 0), For new ocp (ctrl_reversebst is 1), */\
+{ 0xc4e0, "test_bst_sense"}, /* Test option for the sense NMOS in booster for current mode control., */\
+{ 0xc500, "test_cvi"}, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */\
+{ 0xc510, "test_discrete"}, /* Test function noise measurement , */\
+{ 0xc520, "test_iddq"}, /* Set the power stages in iddq mode for gate stress., */\
+{ 0xc540, "test_rdson"}, /* Analog BIST, switch to enable Rdson measurement , */\
+{ 0xc550, "test_sdelta"}, /* Analog BIST, noise test , */\
+{ 0xc570, "test_enbl_cs"}, /* Enable for digimux mode of current sense , */\
+{ 0xc580, "test_enbl_vs"}, /* Enable for digimux mode of voltage sense , */\
+{ 0xc600, "enbl_pwm_dcc"}, /* Enables direct control of pwm duty cycle for DCDC power stage, */\
+{ 0xc613, "pwm_dcc_cnt"}, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */\
+{ 0xc650, "enbl_ldo_stress"}, /* Enable stress of internal supply voltages powerstages, */\
+{ 0xc707, "digimuxa_sel"}, /* DigimuxA input selection control routed to DATAO (see Digimux list for details), */\
+{ 0xc787, "digimuxb_sel"}, /* DigimuxB input selection control routed to INT (see Digimux list for details), */\
+{ 0xc807, "digimuxc_sel"}, /* DigimuxC input selection control routed to PDMDAT (see Digimux list for details), */\
+{ 0xc981, "int_ehs"}, /* Speed/load setting for INT IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
+{ 0xc9c0, "hs_mode"}, /* I2C high speed mode control , */\
+{ 0xca00, "enbl_anamux1"}, /* Enable anamux1 , */\
+{ 0xca10, "enbl_anamux2"}, /* Enable anamux2 , */\
+{ 0xca20, "enbl_anamux3"}, /* Enable anamux3 , */\
+{ 0xca30, "enbl_anamux4"}, /* Enable anamux4 , */\
+{ 0xca74, "anamux1"}, /* Anamux selection control - anamux on TEST1 , */\
+{ 0xcb04, "anamux2"}, /* Anamux selection control - anamux on TEST2 , */\
+{ 0xcb53, "anamux3"}, /* Anamux selection control - anamux on TEST3 , */\
+{ 0xcba3, "anamux4"}, /* Anamux selection control - anamux on TEST4 , */\
+{ 0xcd05, "pll_seli"}, /* PLL SELI - I2C direct PLL control mode only , */\
+{ 0xcd64, "pll_selp"}, /* PLL SELP - I2C direct PLL control mode only , */\
+{ 0xcdb3, "pll_selr"}, /* PLL SELR - I2C direct PLL control mode only , */\
+{ 0xcdf0, "pll_frm"}, /* PLL free running mode control; 1 in TCB direct control mode, else this control bit, */\
+{ 0xce09, "pll_ndec"}, /* PLL NDEC - I2C direct PLL control mode only , */\
+{ 0xcea0, "pll_mdec_msb"}, /* MSB of pll_mdec - I2C direct PLL control mode only, */\
+{ 0xceb0, "enbl_pll"}, /* Enables PLL in I2C direct PLL control mode only , */\
+{ 0xcec0, "enbl_osc"}, /* Enables OSC1M in I2C direct control mode only , */\
+{ 0xced0, "pll_bypass"}, /* PLL bypass control in I2C direct PLL control mode only, */\
+{ 0xcee0, "pll_directi"}, /* PLL directi control in I2C direct PLL control mode only, */\
+{ 0xcef0, "pll_directo"}, /* PLL directo control in I2C direct PLL control mode only, */\
+{ 0xcf0f, "pll_mdec_lsb"}, /* Bits 15..0 of PLL MDEC are I2C direct PLL control mode only, */\
+{ 0xd006, "pll_pdec"}, /* PLL PDEC - I2C direct PLL control mode only , */\
+{ 0xd10f, "tsig_freq_lsb"}, /* Internal sinus test generator frequency control , */\
+{ 0xd202, "tsig_freq_msb"}, /* Select internal sinus test generator, frequency control msb bits, */\
+{ 0xd230, "inject_tsig"}, /* Control bit to switch to internal sinus test generator, */\
+{ 0xd283, "tsig_gain"}, /* Test signal gain , */\
+{ 0xd300, "adc10_reset"}, /* Reset for ADC10 - I2C direct control mode , */\
+{ 0xd311, "adc10_test"}, /* Test mode selection signal for ADC10 - I2C direct control mode, */\
+{ 0xd332, "adc10_sel"}, /* Select the input to convert for ADC10 - I2C direct control mode, */\
+{ 0xd364, "adc10_prog_sample"}, /* ADC10 program sample setting - I2C direct control mode, */\
+{ 0xd3b0, "adc10_enbl"}, /* Enable ADC10 - I2C direct control mode , */\
+{ 0xd3c0, "bypass_lp_vbat"}, /* Bypass control for Low pass filter in batt sensor , */\
+{ 0xd409, "data_adc10_tempbat"}, /* ADC 10 data output data for testing , */\
+{ 0xd507, "ctrl_digtoana_hidden"}, /* Spare digital to analog control bits - Hidden , */\
+{ 0xd580, "enbl_clk_out_of_range"}, /* Clock out of range , */\
+{ 0xd621, "clkdiv_audio_sel"}, /* Audio clock divider selection in direct clock control mode, */\
+{ 0xd641, "clkdiv_muxa_sel"}, /* DCDC MUXA clock divider selection in direct clock control mode, */\
+{ 0xd661, "clkdiv_muxb_sel"}, /* DCDC MUXB clock divider selection in direct clock control mode, */\
+{ 0xd721, "datao_ehs"}, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
+{ 0xd740, "bck_ehs"}, /* High-speed and standard/fast mode selection for BCK IO cell (see IIC3V3 IO cell datasheet), */\
+{ 0xd750, "datai_ehs"}, /* High-speed and standard/fast mode selection for DATAI IO cell (see IIC3V3 IO cell datasheet), */\
+{ 0xd800, "source_in_testmode"}, /* tdm source in test mode (return only current and voltage sense), */\
+{ 0xd810, "gainatt_feedback"}, /* gainatt feedback to tdm , */\
+{ 0xd822, "test_parametric_io"}, /* test io parametric , */\
+{ 0xd850, "ctrl_bst_clk_lp1"}, /* boost clock control in low power mode1 , */\
+{ 0xd861, "test_spare_out1"}, /* test spare out 1 , */\
+{ 0xd880, "bst_dcmbst"}, /* dcm boost , */\
+{ 0xd8c3, "test_spare_out2"}, /* test spare out 1 , */\
+{ 0xee0f, "sw_profile"}, /* Software profile data , */\
+{ 0xef0f, "sw_vstep"}, /* Software vstep information , */\
+{ 0xf000, "calibration_onetime"}, /* Calibration schedule , */\
+{ 0xf010, "calibr_ron_done"}, /* Calibration Ron executed , */\
+{ 0xf020, "calibr_dcdc_api_calibrate"}, /* Calibration current limit DCDC , */\
+{ 0xf030, "calibr_dcdc_delta_sign"}, /* Sign bit for delta calibration current limit DCDC , */\
+{ 0xf042, "calibr_dcdc_delta"}, /* Calibration delta current limit DCDC , */\
+{ 0xf078, "calibr_speaker_info"}, /* Reserved space for allowing customer to store speaker information, */\
+{ 0xf105, "calibr_vout_offset"}, /* DCDC offset calibration 2's complement (key1 protected), */\
+{ 0xf169, "spare_mpt1_15_6"}, /* SPARE , */\
+{ 0xf203, "calibr_gain"}, /* HW gain module (2's complement) , */\
+{ 0xf245, "calibr_offset"}, /* Offset for amplifier, HW gain module (2's complement), */\
+{ 0xf2a5, "spare_mtp2_15_10"}, /* SPARE , */\
+{ 0xf307, "calibr_gain_vs"}, /* Voltage sense gain , */\
+{ 0xf387, "calibr_gain_cs"}, /* Current sense gain (signed two's complement format), */\
+{ 0xf407, "spare_mtp4_15_0"}, /* SPARE , */\
+{ 0xf487, "vs_trim"}, /* VS Trimming , */\
+{ 0xf50f, "calibr_R25C_R"}, /* Ron resistance of speaker coil , */\
+{ 0xf60f, "spare_mpt6_6_0"}, /* SPARE , */\
+{ 0xf706, "ctrl_offset_a"}, /* Offset of level shifter A , */\
+{ 0xf770, "spare_mtp7_07"}, /* SPARE , */\
+{ 0xf786, "ctrl_offset_b"}, /* Offset of amplifier level shifter B , */\
+{ 0xf7f0, "spare_mtp7_15"}, /* SPARE , */\
+{ 0xf806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
+{ 0xf870, "htol_iic_addr_en"}, /* HTOL I2C address enable control , */\
+{ 0xf884, "calibr_temp_offset"}, /* Temperature offset 2's compliment (key1 protected), */\
+{ 0xf8d2, "calibr_temp_gain"}, /* Temperature gain 2's compliment (key1 protected) , */\
+{ 0xf900, "mtp_lock_dcdcoff_mode"}, /* Disable function dcdcoff_mode , */\
+{ 0xf910, "spare_mtp9_1"}, /* SPARE , */\
+{ 0xf920, "mtp_lock_bypass_clipper"}, /* Disable function bypass_clipper , */\
+{ 0xf930, "mtp_lock_max_dcdc_voltage"}, /* Force Boost in follower mode , */\
+{ 0xf943, "calibr_vbg_trim"}, /* Bandgap trimming control , */\
+{ 0xf980, "spare_mtp9_8"}, /* SPARE , */\
+{ 0xf990, "mtp_enbl_pwm_delay_clock_gating"}, /* pwm delay clock auto gating , */\
+{ 0xf9a0, "mtp_enbl_ocp_clock_gating"}, /* ocpclock auto gating , */\
+{ 0xf9b0, "mtp_gate_cgu_clock_for_test"}, /* cgu test clock control , */\
+{ 0xf9c0, "mtp_tdm_pad_sel"}, /* tdm pad selection , */\
+{ 0xf9d2, "spare_mtp9_15_12"}, /* MTP-control FW - See Firmware I2C API document for details, */\
+{ 0xfa0f, "mtpdataA"}, /* MTPdataA (key1 protected) , */\
+{ 0xfb0f, "mtpdataB"}, /* MTPdataB (key1 protected) , */\
+{ 0xfc0f, "mtpdataC"}, /* MTPdataC (key1 protected) , */\
+{ 0xfd0f, "mtpdataD"}, /* MTPdataD (key1 protected) , */\
+{ 0xfe0f, "mtpdataE"}, /* MTPdataE (key1 protected) , */\
+{ 0xff07, "calibr_osc_delta_ndiv"}, /* Calibration data for OSC1M, signed number representation, */\
+{ 0xff87, "spare_mtp7_15_08"}, /* SPARE , */\
+{ 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+
+enum tfa9874_irq {
+ tfa9874_irq_stvdds = 0,
+ tfa9874_irq_stbstoc = 1,
+ tfa9874_irq_stotds = 2,
+ tfa9874_irq_stocpr = 3,
+ tfa9874_irq_stuvds = 4,
+ tfa9874_irq_stmanalarm = 5,
+ tfa9874_irq_sttdmer = 6,
+ tfa9874_irq_stnoclk = 7,
+ tfa9874_irq_max = 8,
+ tfa9874_irq_all = -1 /* all irqs */};
+
+#define TFA9874_IRQ_NAMETABLE static tfaIrqName_t Tfa9874IrqNames[] = {\
+ { 0, "STVDDS"},\
+ { 1, "STBSTOC"},\
+ { 2, "STOTDS"},\
+ { 3, "STOCPR"},\
+ { 4, "STUVDS"},\
+ { 5, "STMANALARM"},\
+ { 6, "STTDMER"},\
+ { 7, "STNOCLK"},\
+ { 8, "8"},\
+};
+#endif /* _TFA9874_TFAFIELDNAMES_H */
diff --git a/inc/tfa9878_tfafieldnames.h b/sound/soc/codecs/tfa9878_tfafieldnames.h
similarity index 84%
rename from inc/tfa9878_tfafieldnames.h
rename to sound/soc/codecs/tfa9878_tfafieldnames.h
index f11d2a3..f626372b 100644
--- a/inc/tfa9878_tfafieldnames.h
+++ b/sound/soc/codecs/tfa9878_tfafieldnames.h
@@ -19,169 +19,169 @@ typedef enum nxpTfa9878BfEnumList {
TFA9878_BF_AMPE = 0x0030, /*!< Activate Amplifier */
TFA9878_BF_DCA = 0x0040, /*!< Activate DC-to-DC converter */
TFA9878_BF_INTP = 0x0071, /*!< Interrupt config */
- TFA9878_BF_FSSSEL= 0x0090, /*!< Audio sample reference */
- TFA9878_BF_BYPOCP= 0x00b0, /*!< Bypass OCP */
- TFA9878_BF_TSTOCP= 0x00c0, /*!< OCP testing control */
- TFA9878_BF_AMPINSEL= 0x0101, /*!< Amplifier input selection */
- TFA9878_BF_MANSCONF= 0x0120, /*!< I2C configured */
- TFA9878_BF_DCINSEL= 0x0131, /*!< VAMP_OUT2 input selection */
- TFA9878_BF_MUTETO= 0x0160, /*!< Time out SB mute sequence */
- TFA9878_BF_MANROBOD= 0x0170, /*!< Reaction on BOD */
+ TFA9878_BF_FSSSEL = 0x0090, /*!< Audio sample reference */
+ TFA9878_BF_BYPOCP = 0x00b0, /*!< Bypass OCP */
+ TFA9878_BF_TSTOCP = 0x00c0, /*!< OCP testing control */
+ TFA9878_BF_AMPINSEL = 0x0101, /*!< Amplifier input selection */
+ TFA9878_BF_MANSCONF = 0x0120, /*!< I2C configured */
+ TFA9878_BF_DCINSEL = 0x0131, /*!< VAMP_OUT2 input selection */
+ TFA9878_BF_MUTETO = 0x0160, /*!< Time out SB mute sequence */
+ TFA9878_BF_MANROBOD = 0x0170, /*!< Reaction on BOD */
TFA9878_BF_BODE = 0x0180, /*!< Enable BOD (only in direct control mode) */
- TFA9878_BF_BODHYS= 0x0190, /*!< Enable Hysteresis of BOD */
- TFA9878_BF_BODFILT= 0x01a1, /*!< BOD filter */
- TFA9878_BF_BODTHLVL= 0x01c1, /*!< BOD threshold */
- TFA9878_BF_OPENMTP= 0x01e0, /*!< Control for FAIM protection */
- TFA9878_BF_DISFCRBST= 0x01f0, /*!< disable boost control with FRCBST */
+ TFA9878_BF_BODHYS = 0x0190, /*!< Enable Hysteresis of BOD */
+ TFA9878_BF_BODFILT = 0x01a1, /*!< BOD filter */
+ TFA9878_BF_BODTHLVL = 0x01c1, /*!< BOD threshold */
+ TFA9878_BF_OPENMTP = 0x01e0, /*!< Control for FAIM protection */
+ TFA9878_BF_DISFCRBST = 0x01f0, /*!< disable boost control with FRCBST */
TFA9878_BF_AUDFS = 0x0203, /*!< Sample rate (fs) */
- TFA9878_BF_INPLEV= 0x0240, /*!< TDM output attenuation */
- TFA9878_BF_FRACTDEL= 0x0255, /*!< V/I Fractional delay */
- TFA9878_BF_AMPINPSEL= 0x02b1, /*!< amp input selection */
- TFA9878_BF_PDMRATE= 0x02d0, /*!< Pdm rate */
+ TFA9878_BF_INPLEV = 0x0240, /*!< TDM output attenuation */
+ TFA9878_BF_FRACTDEL = 0x0255, /*!< V/I Fractional delay */
+ TFA9878_BF_AMPINPSEL = 0x02b1, /*!< amp input selection */
+ TFA9878_BF_PDMRATE = 0x02d0, /*!< Pdm rate */
TFA9878_BF_REV = 0x030f, /*!< Revision info */
- TFA9878_BF_REFCKEXT= 0x0401, /*!< PLL external ref clock */
- TFA9878_BF_REFCKSEL= 0x0420, /*!< PLL internal ref clock */
- TFA9878_BF_SWCLKSEL= 0x0432, /*!< Sound Wire clock frequnecy */
- TFA9878_BF_MANAOOSC= 0x0460, /*!< Internal osc off at PWDN */
- TFA9878_BF_FSSYNCEN= 0x0480, /*!< Enable FS synchronisation for clock divider */
- TFA9878_BF_CLKREFSYNCEN= 0x0490, /*!< Enable PLL reference clock synchronisation for clock divider */
- TFA9878_BF_AUTOFROSEL= 0x04a0, /*!< override automatic OSC selection mechanism */
- TFA9878_BF_SWFRSYNC= 0x04b0, /*!< Selection SW signal reference for Stream Synchronization */
- TFA9878_BF_CGUSYNCDCG= 0x0500, /*!< Clock gating control for CGU synchronisation module */
- TFA9878_BF_FRCCLKSPKR= 0x0510, /*!< force active the speaker sub-system clock when in idle power */
- TFA9878_BF_SSFAIME= 0x05c0, /*!< Sub-system FAIM */
- TFA9878_BF_CLKCHKLO= 0x0707, /*!< Clock check Low Threshold */
- TFA9878_BF_CLKCHKHI= 0x0787, /*!< Clock check Higher Threshold */
- TFA9878_BF_AMPOCRT= 0x0802, /*!< Amplifier on-off criteria for shutdown */
+ TFA9878_BF_REFCKEXT = 0x0401, /*!< PLL external ref clock */
+ TFA9878_BF_REFCKSEL = 0x0420, /*!< PLL internal ref clock */
+ TFA9878_BF_SWCLKSEL = 0x0432, /*!< Sound Wire clock frequnecy */
+ TFA9878_BF_MANAOOSC = 0x0460, /*!< Internal osc off at PWDN */
+ TFA9878_BF_FSSYNCEN = 0x0480, /*!< Enable FS synchronisation for clock divider */
+ TFA9878_BF_CLKREFSYNCEN = 0x0490, /*!< Enable PLL reference clock synchronisation for clock divider */
+ TFA9878_BF_AUTOFROSEL = 0x04a0, /*!< override automatic OSC selection mechanism */
+ TFA9878_BF_SWFRSYNC = 0x04b0, /*!< Selection SW signal reference for Stream Synchronization */
+ TFA9878_BF_CGUSYNCDCG = 0x0500, /*!< Clock gating control for CGU synchronisation module */
+ TFA9878_BF_FRCCLKSPKR = 0x0510, /*!< force active the speaker sub-system clock when in idle power */
+ TFA9878_BF_SSFAIME = 0x05c0, /*!< Sub-system FAIM */
+ TFA9878_BF_CLKCHKLO = 0x0707, /*!< Clock check Low Threshold */
+ TFA9878_BF_CLKCHKHI = 0x0787, /*!< Clock check Higher Threshold */
+ TFA9878_BF_AMPOCRT = 0x0802, /*!< Amplifier on-off criteria for shutdown */
TFA9878_BF_VDDS = 0x1000, /*!< POR */
- TFA9878_BF_DCOCPOK= 0x1010, /*!< DCDC OCP nmos (sticky register , clear on read) */
+ TFA9878_BF_DCOCPOK = 0x1010, /*!< DCDC OCP nmos (sticky register , clear on read) */
TFA9878_BF_OTDS = 0x1020, /*!< OTP alarm (sticky register , clear on read) */
TFA9878_BF_OCDS = 0x1030, /*!< OCP amplifier (sticky register , clear on read) */
TFA9878_BF_UVDS = 0x1040, /*!< UVP alarm (sticky register , clear on read) */
- TFA9878_BF_MANALARM= 0x1050, /*!< Alarm state */
+ TFA9878_BF_MANALARM = 0x1050, /*!< Alarm state */
TFA9878_BF_CLKS = 0x1060, /*!< Clocks stable */
TFA9878_BF_MTPB = 0x1070, /*!< MTP busy */
TFA9878_BF_NOCLK = 0x1080, /*!< Lost clock (sticky register , clear on read) */
- TFA9878_BF_BODNOK= 0x1090, /*!< BOD Flag - VDD NOT OK */
- TFA9878_BF_TDMERR= 0x10a0, /*!< TDM error */
+ TFA9878_BF_BODNOK = 0x1090, /*!< BOD Flag - VDD NOT OK */
+ TFA9878_BF_TDMERR = 0x10a0, /*!< TDM error */
TFA9878_BF_DCIL = 0x1100, /*!< DCDC current limiting */
TFA9878_BF_DCDCA = 0x1110, /*!< DCDC active (sticky register , clear on read) */
- TFA9878_BF_DCDCPC= 0x1120, /*!< Indicates current is max in DC-to-DC converter */
- TFA9878_BF_DCHVBAT= 0x1130, /*!< DCDC level 1x */
- TFA9878_BF_DCH114= 0x1140, /*!< DCDC level 1.14x */
- TFA9878_BF_DCH107= 0x1150, /*!< DCDC level 1.07x */
+ TFA9878_BF_DCDCPC = 0x1120, /*!< Indicates current is max in DC-to-DC converter */
+ TFA9878_BF_DCHVBAT = 0x1130, /*!< DCDC level 1x */
+ TFA9878_BF_DCH114 = 0x1140, /*!< DCDC level 1.14x */
+ TFA9878_BF_DCH107 = 0x1150, /*!< DCDC level 1.07x */
TFA9878_BF_PLLS = 0x1160, /*!< PLL lock */
- TFA9878_BF_TDMLUTER= 0x1180, /*!< TDM LUT error */
- TFA9878_BF_CLKOOR= 0x11c0, /*!< External clock status */
+ TFA9878_BF_TDMLUTER = 0x1180, /*!< TDM LUT error */
+ TFA9878_BF_CLKOOR = 0x11c0, /*!< External clock status */
TFA9878_BF_SWS = 0x11d0, /*!< Amplifier engage */
TFA9878_BF_AMPS = 0x11e0, /*!< Amplifier enable */
TFA9878_BF_AREFS = 0x11f0, /*!< References enable */
- TFA9878_BF_OCPOAP= 0x1300, /*!< OCPOK pmos B */
- TFA9878_BF_OCPOAN= 0x1310, /*!< OCPOK pmos A */
- TFA9878_BF_OCPOBP= 0x1320, /*!< OCPOK nmos B */
- TFA9878_BF_OCPOBN= 0x1330, /*!< OCPOK nmos A */
+ TFA9878_BF_OCPOAP = 0x1300, /*!< OCPOK pmos B */
+ TFA9878_BF_OCPOAN = 0x1310, /*!< OCPOK pmos A */
+ TFA9878_BF_OCPOBP = 0x1320, /*!< OCPOK nmos B */
+ TFA9878_BF_OCPOBN = 0x1330, /*!< OCPOK nmos A */
TFA9878_BF_OVDS = 0x1380, /*!< OVP alarm */
TFA9878_BF_CLIPS = 0x1390, /*!< Amplifier clipping */
TFA9878_BF_ADCCR = 0x13a0, /*!< Control ADC */
- TFA9878_BF_MANWAIT1= 0x13c0, /*!< Wait HW I2C settings */
- TFA9878_BF_MANMUTE= 0x13e0, /*!< Audio mute sequence */
- TFA9878_BF_MANOPER= 0x13f0, /*!< Operating state */
- TFA9878_BF_TDMSTAT= 0x1402, /*!< TDM status bits */
- TFA9878_BF_MANSTATE= 0x1433, /*!< Device manager status */
- TFA9878_BF_AMPSTE= 0x1473, /*!< Amplifier control status */
- TFA9878_BF_DCMODE= 0x14b1, /*!< DCDC mode status bits */
+ TFA9878_BF_MANWAIT1 = 0x13c0, /*!< Wait HW I2C settings */
+ TFA9878_BF_MANMUTE = 0x13e0, /*!< Audio mute sequence */
+ TFA9878_BF_MANOPER = 0x13f0, /*!< Operating state */
+ TFA9878_BF_TDMSTAT = 0x1402, /*!< TDM status bits */
+ TFA9878_BF_MANSTATE = 0x1433, /*!< Device manager status */
+ TFA9878_BF_AMPSTE = 0x1473, /*!< Amplifier control status */
+ TFA9878_BF_DCMODE = 0x14b1, /*!< DCDC mode status bits */
TFA9878_BF_BATS = 0x1509, /*!< Battery voltage (V) */
TFA9878_BF_TEMPS = 0x1608, /*!< IC Temperature (C) */
TFA9878_BF_VDDPS = 0x1709, /*!< IC VDDP voltage ( 1023*VDDP/13 V) */
TFA9878_BF_TDME = 0x2000, /*!< Enable interface */
- TFA9878_BF_TDMSLOTS= 0x2013, /*!< N-slots in Frame */
- TFA9878_BF_TDMCLINV= 0x2060, /*!< Reception data to BCK clock */
- TFA9878_BF_TDMFSLN= 0x2073, /*!< FS length */
- TFA9878_BF_TDMFSPOL= 0x20b0, /*!< FS polarity */
- TFA9878_BF_TDMNBCK= 0x20c3, /*!< N-BCK's in FS */
- TFA9878_BF_TDMSLLN= 0x2144, /*!< N-bits in slot */
- TFA9878_BF_TDMBRMG= 0x2194, /*!< N-bits remaining */
- TFA9878_BF_TDMDEL= 0x21e0, /*!< data delay to FS */
- TFA9878_BF_TDMADJ= 0x21f0, /*!< data adjustment */
- TFA9878_BF_TDMOOMP= 0x2201, /*!< Received audio compression */
- TFA9878_BF_TDMSSIZE= 0x2224, /*!< Sample size per slot */
- TFA9878_BF_TDMTXDFO= 0x2271, /*!< Format unused bits */
- TFA9878_BF_TDMTXUS0= 0x2291, /*!< Format unused slots DATAO */
- TFA9878_BF_TDMSPKE= 0x2300, /*!< Control audio tdm channel in 0 */
- TFA9878_BF_TDMDCE= 0x2310, /*!< Control audio tdm channel in 1 */
- TFA9878_BF_TDMCSE= 0x2330, /*!< current sense vbat temperature and vddp feedback */
- TFA9878_BF_TDMVSE= 0x2340, /*!< Voltage sense vbat temperature and vddp feedback */
- TFA9878_BF_TDMSPKS= 0x2603, /*!< tdm slot for sink 0 */
- TFA9878_BF_TDMDCS= 0x2643, /*!< tdm slot for sink 1 */
- TFA9878_BF_TDMCSS= 0x26c3, /*!< Slot Position of current sense vbat temperature and vddp feedback */
- TFA9878_BF_TDMVSS= 0x2703, /*!< Slot Position of Voltage sense vbat temperature and vddp feedback */
- TFA9878_BF_ISTVDDS= 0x4000, /*!< Status POR */
- TFA9878_BF_ISTBSTOC= 0x4010, /*!< Status DCDC OCP */
- TFA9878_BF_ISTOTDS= 0x4020, /*!< Status OTP alarm */
- TFA9878_BF_ISTOCPR= 0x4030, /*!< Status ocp alarm */
- TFA9878_BF_ISTUVDS= 0x4040, /*!< Status UVP alarm */
- TFA9878_BF_ISTMANALARM= 0x4050, /*!< Status nanager Alarm state */
- TFA9878_BF_ISTTDMER= 0x4060, /*!< Status tdm error */
- TFA9878_BF_ISTNOCLK= 0x4070, /*!< Status lost clock */
- TFA9878_BF_ISTBODNOK= 0x4080, /*!< Status BOD event */
- TFA9878_BF_ICLVDDS= 0x4400, /*!< Clear POR */
- TFA9878_BF_ICLBSTOC= 0x4410, /*!< Clear DCDC OCP */
- TFA9878_BF_ICLOTDS= 0x4420, /*!< Clear OTP alarm */
- TFA9878_BF_ICLOCPR= 0x4430, /*!< Clear ocp alarm */
- TFA9878_BF_ICLUVDS= 0x4440, /*!< Clear UVP alarm */
- TFA9878_BF_ICLMANALARM= 0x4450, /*!< Clear manager Alarm state */
- TFA9878_BF_ICLTDMER= 0x4460, /*!< Clear tdm error */
- TFA9878_BF_ICLNOCLK= 0x4470, /*!< Clear lost clk */
- TFA9878_BF_ICLBODNOK= 0x4480, /*!< Clear BOD event */
- TFA9878_BF_IEVDDS= 0x4800, /*!< Enable por */
- TFA9878_BF_IEBSTOC= 0x4810, /*!< Enable DCDC OCP */
- TFA9878_BF_IEOTDS= 0x4820, /*!< Enable OTP alarm */
- TFA9878_BF_IEOCPR= 0x4830, /*!< Enable ocp alarm */
- TFA9878_BF_IEUVDS= 0x4840, /*!< Enable UVP alarm */
- TFA9878_BF_IEMANALARM= 0x4850, /*!< Enable nanager Alarm state */
- TFA9878_BF_IETDMER= 0x4860, /*!< Enable tdm error */
- TFA9878_BF_IENOCLK= 0x4870, /*!< Enable lost clk */
- TFA9878_BF_IEBODNOK= 0x4880, /*!< Enable BOD trigger */
- TFA9878_BF_IPOVDDS= 0x4c00, /*!< Polarity por */
- TFA9878_BF_IPOBSTOC= 0x4c10, /*!< Polarity DCDC OCP */
- TFA9878_BF_IPOOTDS= 0x4c20, /*!< Polarity OTP alarm */
- TFA9878_BF_IPOOCPR= 0x4c30, /*!< Polarity ocp alarm */
- TFA9878_BF_IPOUVDS= 0x4c40, /*!< Polarity UVP alarm */
- TFA9878_BF_IPOMANALARM= 0x4c50, /*!< Polarity nanager Alarm state */
- TFA9878_BF_IPOTDMER= 0x4c60, /*!< Polarity tdm error */
- TFA9878_BF_IPONOCLK= 0x4c70, /*!< Polarity lost clk */
- TFA9878_BF_IPOBODNOK= 0x4c80, /*!< Polarity BOD trigger */
+ TFA9878_BF_TDMSLOTS = 0x2013, /*!< N-slots in Frame */
+ TFA9878_BF_TDMCLINV = 0x2060, /*!< Reception data to BCK clock */
+ TFA9878_BF_TDMFSLN = 0x2073, /*!< FS length */
+ TFA9878_BF_TDMFSPOL = 0x20b0, /*!< FS polarity */
+ TFA9878_BF_TDMNBCK = 0x20c3, /*!< N-BCK's in FS */
+ TFA9878_BF_TDMSLLN = 0x2144, /*!< N-bits in slot */
+ TFA9878_BF_TDMBRMG = 0x2194, /*!< N-bits remaining */
+ TFA9878_BF_TDMDEL = 0x21e0, /*!< data delay to FS */
+ TFA9878_BF_TDMADJ = 0x21f0, /*!< data adjustment */
+ TFA9878_BF_TDMOOMP = 0x2201, /*!< Received audio compression */
+ TFA9878_BF_TDMSSIZE = 0x2224, /*!< Sample size per slot */
+ TFA9878_BF_TDMTXDFO = 0x2271, /*!< Format unused bits */
+ TFA9878_BF_TDMTXUS0 = 0x2291, /*!< Format unused slots DATAO */
+ TFA9878_BF_TDMSPKE = 0x2300, /*!< Control audio tdm channel in 0 */
+ TFA9878_BF_TDMDCE = 0x2310, /*!< Control audio tdm channel in 1 */
+ TFA9878_BF_TDMCSE = 0x2330, /*!< current sense vbat temperature and vddp feedback */
+ TFA9878_BF_TDMVSE = 0x2340, /*!< Voltage sense vbat temperature and vddp feedback */
+ TFA9878_BF_TDMSPKS = 0x2603, /*!< tdm slot for sink 0 */
+ TFA9878_BF_TDMDCS = 0x2643, /*!< tdm slot for sink 1 */
+ TFA9878_BF_TDMCSS = 0x26c3, /*!< Slot Position of current sense vbat temperature and vddp feedback */
+ TFA9878_BF_TDMVSS = 0x2703, /*!< Slot Position of Voltage sense vbat temperature and vddp feedback */
+ TFA9878_BF_ISTVDDS = 0x4000, /*!< Status POR */
+ TFA9878_BF_ISTBSTOC = 0x4010, /*!< Status DCDC OCP */
+ TFA9878_BF_ISTOTDS = 0x4020, /*!< Status OTP alarm */
+ TFA9878_BF_ISTOCPR = 0x4030, /*!< Status ocp alarm */
+ TFA9878_BF_ISTUVDS = 0x4040, /*!< Status UVP alarm */
+ TFA9878_BF_ISTMANALARM = 0x4050, /*!< Status nanager Alarm state */
+ TFA9878_BF_ISTTDMER = 0x4060, /*!< Status tdm error */
+ TFA9878_BF_ISTNOCLK = 0x4070, /*!< Status lost clock */
+ TFA9878_BF_ISTBODNOK = 0x4080, /*!< Status BOD event */
+ TFA9878_BF_ICLVDDS = 0x4400, /*!< Clear POR */
+ TFA9878_BF_ICLBSTOC = 0x4410, /*!< Clear DCDC OCP */
+ TFA9878_BF_ICLOTDS = 0x4420, /*!< Clear OTP alarm */
+ TFA9878_BF_ICLOCPR = 0x4430, /*!< Clear ocp alarm */
+ TFA9878_BF_ICLUVDS = 0x4440, /*!< Clear UVP alarm */
+ TFA9878_BF_ICLMANALARM = 0x4450, /*!< Clear manager Alarm state */
+ TFA9878_BF_ICLTDMER = 0x4460, /*!< Clear tdm error */
+ TFA9878_BF_ICLNOCLK = 0x4470, /*!< Clear lost clk */
+ TFA9878_BF_ICLBODNOK = 0x4480, /*!< Clear BOD event */
+ TFA9878_BF_IEVDDS = 0x4800, /*!< Enable por */
+ TFA9878_BF_IEBSTOC = 0x4810, /*!< Enable DCDC OCP */
+ TFA9878_BF_IEOTDS = 0x4820, /*!< Enable OTP alarm */
+ TFA9878_BF_IEOCPR = 0x4830, /*!< Enable ocp alarm */
+ TFA9878_BF_IEUVDS = 0x4840, /*!< Enable UVP alarm */
+ TFA9878_BF_IEMANALARM = 0x4850, /*!< Enable nanager Alarm state */
+ TFA9878_BF_IETDMER = 0x4860, /*!< Enable tdm error */
+ TFA9878_BF_IENOCLK = 0x4870, /*!< Enable lost clk */
+ TFA9878_BF_IEBODNOK = 0x4880, /*!< Enable BOD trigger */
+ TFA9878_BF_IPOVDDS = 0x4c00, /*!< Polarity por */
+ TFA9878_BF_IPOBSTOC = 0x4c10, /*!< Polarity DCDC OCP */
+ TFA9878_BF_IPOOTDS = 0x4c20, /*!< Polarity OTP alarm */
+ TFA9878_BF_IPOOCPR = 0x4c30, /*!< Polarity ocp alarm */
+ TFA9878_BF_IPOUVDS = 0x4c40, /*!< Polarity UVP alarm */
+ TFA9878_BF_IPOMANALARM = 0x4c50, /*!< Polarity nanager Alarm state */
+ TFA9878_BF_IPOTDMER = 0x4c60, /*!< Polarity tdm error */
+ TFA9878_BF_IPONOCLK = 0x4c70, /*!< Polarity lost clk */
+ TFA9878_BF_IPOBODNOK = 0x4c80, /*!< Polarity BOD trigger */
TFA9878_BF_BSSCR = 0x5001, /*!< Battery Safeguard attack time (with K = 1 at sample rate fs of 32kHz, 44,1 kHz or 48kHz ; with K = 2 at sample rate fs 16 kHz . With K =0.5 at sample rate of 96 kHz) */
TFA9878_BF_BSST = 0x5023, /*!< Battery Safeguard threshold voltage level */
TFA9878_BF_BSSRL = 0x5061, /*!< Battery Safeguard maximum reduction */
TFA9878_BF_BSSR = 0x50e0, /*!< Battery voltage read out */
TFA9878_BF_BSSBY = 0x50f0, /*!< Bypass battery safeguard */
TFA9878_BF_BSSS = 0x5100, /*!< Vbat prot steepness */
- TFA9878_BF_HPFBYP= 0x5150, /*!< Bypass HPF */
+ TFA9878_BF_HPFBYP = 0x5150, /*!< Bypass HPF */
TFA9878_BF_DPSA = 0x5170, /*!< Enable DPSA */
- TFA9878_BF_CLIPCTRL= 0x5222, /*!< Clip control setting */
- TFA9878_BF_AMPGAIN= 0x5257, /*!< Amplifier gain */
- TFA9878_BF_SLOPEE= 0x52d0, /*!< Enables slope control */
- TFA9878_BF_SLOPESET= 0x52e0, /*!< Slope speed setting (bin. coded) */
- TFA9878_BF_BYPDLYLINE= 0x52f0, /*!< Bypass the interpolator delay line */
- TFA9878_BF_TDMDCG= 0x5f23, /*!< Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE) */
- TFA9878_BF_TDMSPKG= 0x5f63, /*!< Total gain depending on INPLEV setting (channel 0) */
+ TFA9878_BF_CLIPCTRL = 0x5222, /*!< Clip control setting */
+ TFA9878_BF_AMPGAIN = 0x5257, /*!< Amplifier gain */
+ TFA9878_BF_SLOPEE = 0x52d0, /*!< Enables slope control */
+ TFA9878_BF_SLOPESET = 0x52e0, /*!< Slope speed setting (bin. coded) */
+ TFA9878_BF_BYPDLYLINE = 0x52f0, /*!< Bypass the interpolator delay line */
+ TFA9878_BF_TDMDCG = 0x5f23, /*!< Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE) */
+ TFA9878_BF_TDMSPKG = 0x5f63, /*!< Total gain depending on INPLEV setting (channel 0) */
TFA9878_BF_IPM = 0x60e1, /*!< Idle power mode control */
- TFA9878_BF_LNMODE= 0x62e1, /*!< ctrl select mode */
- TFA9878_BF_LPM1MODE= 0x64e1, /*!< low power mode control */
- TFA9878_BF_TDMSRCMAP= 0x6802, /*!< tdm source mapping */
- TFA9878_BF_TDMSRCAS= 0x6831, /*!< Sensed value A */
- TFA9878_BF_TDMSRCBS= 0x6851, /*!< Sensed value B */
- TFA9878_BF_TDMSRCACLIP= 0x6871, /*!< clip information (analog /digital) for source0 */
- TFA9878_BF_TDMSRCBCLIP= 0x6891, /*!< clip information (analog /digital) for source1 */
+ TFA9878_BF_LNMODE = 0x62e1, /*!< ctrl select mode */
+ TFA9878_BF_LPM1MODE = 0x64e1, /*!< low power mode control */
+ TFA9878_BF_TDMSRCMAP = 0x6802, /*!< tdm source mapping */
+ TFA9878_BF_TDMSRCAS = 0x6831, /*!< Sensed value A */
+ TFA9878_BF_TDMSRCBS = 0x6851, /*!< Sensed value B */
+ TFA9878_BF_TDMSRCACLIP = 0x6871, /*!< clip information (analog /digital) for source0 */
+ TFA9878_BF_TDMSRCBCLIP = 0x6891, /*!< clip information (analog /digital) for source1 */
TFA9878_BF_LP0 = 0x6e00, /*!< Idle power mode */
TFA9878_BF_LP1 = 0x6e10, /*!< low power mode 1 detection */
TFA9878_BF_LA = 0x6e20, /*!< low amplitude detection */
TFA9878_BF_VDDPH = 0x6e30, /*!< vddp greater than vbat */
- TFA9878_BF_DELCURCOMP= 0x6f02, /*!< delay to allign compensation signal with current sense signal */
- TFA9878_BF_SIGCURCOMP= 0x6f40, /*!< polarity of compensation for current sense */
- TFA9878_BF_ENCURCOMP= 0x6f50, /*!< enable current sense compensation */
- TFA9878_BF_LVLCLPPWM= 0x6f72, /*!< set the amount of pwm pulse that may be skipped before clip-flag is triggered */
+ TFA9878_BF_DELCURCOMP = 0x6f02, /*!< delay to allign compensation signal with current sense signal */
+ TFA9878_BF_SIGCURCOMP = 0x6f40, /*!< polarity of compensation for current sense */
+ TFA9878_BF_ENCURCOMP = 0x6f50, /*!< enable current sense compensation */
+ TFA9878_BF_LVLCLPPWM = 0x6f72, /*!< set the amount of pwm pulse that may be skipped before clip-flag is triggered */
TFA9878_BF_DCMCC = 0x7003, /*!< Max coil current */
TFA9878_BF_DCCV = 0x7041, /*!< Slope compensation current, represents LxF (inductance x frequency) value */
TFA9878_BF_DCIE = 0x7060, /*!< Adaptive boost mode */
@@ -189,52 +189,52 @@ typedef enum nxpTfa9878BfEnumList {
TFA9878_BF_DCOVL = 0x7085, /*!< Threshold level to activate active overshoot control */
TFA9878_BF_DCDIS = 0x70e0, /*!< DCDC on/off */
TFA9878_BF_DCPWM = 0x70f0, /*!< DCDC PWM only mode */
- TFA9878_BF_DCTRACK= 0x7430, /*!< Boost algorithm selection, effective only when boost_intelligent is set to 1 */
- TFA9878_BF_DCTRIP= 0x7444, /*!< 1st Adaptive boost trip levels, effective only when DCIE is set to 1 */
- TFA9878_BF_DCHOLD= 0x7494, /*!< Hold time for DCDC booster, effective only when boost_intelligent is set to 1 */
+ TFA9878_BF_DCTRACK = 0x7430, /*!< Boost algorithm selection, effective only when boost_intelligent is set to 1 */
+ TFA9878_BF_DCTRIP = 0x7444, /*!< 1st Adaptive boost trip levels, effective only when DCIE is set to 1 */
+ TFA9878_BF_DCHOLD = 0x7494, /*!< Hold time for DCDC booster, effective only when boost_intelligent is set to 1 */
TFA9878_BF_DCINT = 0x74e0, /*!< Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1 */
- TFA9878_BF_DCTRIP2= 0x7534, /*!< 2nd Adaptive boost trip levels, effective only when DCIE is set to 1 */
- TFA9878_BF_DCTRIPT= 0x7584, /*!< Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1 */
- TFA9878_BF_DCTRIPHYSTE= 0x75f0, /*!< Enable hysteresis on booster trip levels */
+ TFA9878_BF_DCTRIP2 = 0x7534, /*!< 2nd Adaptive boost trip levels, effective only when DCIE is set to 1 */
+ TFA9878_BF_DCTRIPT = 0x7584, /*!< Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1 */
+ TFA9878_BF_DCTRIPHYSTE = 0x75f0, /*!< Enable hysteresis on booster trip levels */
TFA9878_BF_DCVOF = 0x7635, /*!< First boost voltage level */
TFA9878_BF_DCVOS = 0x7695, /*!< Second boost voltage level */
TFA9878_BF_MTPK = 0xa107, /*!< MTP KEY2 register */
- TFA9878_BF_KEY1LOCKED= 0xa200, /*!< Indicates KEY1 is locked */
- TFA9878_BF_KEY2LOCKED= 0xa210, /*!< Indicates KEY2 is locked */
- TFA9878_BF_MTPADDR= 0xa302, /*!< MTP address from I2C register for read/writing mtp in manual single word mode */
- TFA9878_BF_MTPRDMSB= 0xa50f, /*!< MSB word of MTP manual read data */
- TFA9878_BF_MTPRDLSB= 0xa60f, /*!< LSB word of MTP manual read data */
- TFA9878_BF_MTPWRMSB= 0xa70f, /*!< MSB word of write data for MTP manual write */
- TFA9878_BF_MTPWRLSB= 0xa80f, /*!< LSB word of write data for MTP manual write */
+ TFA9878_BF_KEY1LOCKED = 0xa200, /*!< Indicates KEY1 is locked */
+ TFA9878_BF_KEY2LOCKED = 0xa210, /*!< Indicates KEY2 is locked */
+ TFA9878_BF_MTPADDR = 0xa302, /*!< MTP address from I2C register for read/writing mtp in manual single word mode */
+ TFA9878_BF_MTPRDMSB = 0xa50f, /*!< MSB word of MTP manual read data */
+ TFA9878_BF_MTPRDLSB = 0xa60f, /*!< LSB word of MTP manual read data */
+ TFA9878_BF_MTPWRMSB = 0xa70f, /*!< MSB word of write data for MTP manual write */
+ TFA9878_BF_MTPWRLSB = 0xa80f, /*!< LSB word of write data for MTP manual write */
TFA9878_BF_EXTTS = 0xb108, /*!< External temperature (C) */
TFA9878_BF_TROS = 0xb190, /*!< Select temp Speaker calibration */
- TFA9878_BF_PLLINSI= 0xcd05, /*!< PLL INSELI - PLL direct bandwidth control mode only with pll_bandsel set to 1 */
- TFA9878_BF_PLLINSP= 0xcd64, /*!< PLL INSELP - PLL direct bandwidth control mode only with pll_bandsel set to 1 */
- TFA9878_BF_PLLINSR= 0xcdb3, /*!< PLL INSELR - PLL direct bandwidth control mode only with pll_bandsel set to 1 */
- TFA9878_BF_PLLBDSEL= 0xcdf0, /*!< PLL bandwidth selection control, USE WITH CAUTION */
- TFA9878_BF_PLLNDEC= 0xce09, /*!< PLL NDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
- TFA9878_BF_PLLMDECM= 0xcea0, /*!< MSB of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
+ TFA9878_BF_PLLINSI = 0xcd05, /*!< PLL INSELI - PLL direct bandwidth control mode only with pll_bandsel set to 1 */
+ TFA9878_BF_PLLINSP = 0xcd64, /*!< PLL INSELP - PLL direct bandwidth control mode only with pll_bandsel set to 1 */
+ TFA9878_BF_PLLINSR = 0xcdb3, /*!< PLL INSELR - PLL direct bandwidth control mode only with pll_bandsel set to 1 */
+ TFA9878_BF_PLLBDSEL = 0xcdf0, /*!< PLL bandwidth selection control, USE WITH CAUTION */
+ TFA9878_BF_PLLNDEC = 0xce09, /*!< PLL NDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
+ TFA9878_BF_PLLMDECM = 0xcea0, /*!< MSB of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
TFA9878_BF_PLLBP = 0xceb0, /*!< PLL bypass control during functional mode */
TFA9878_BF_PLLDI = 0xcec0, /*!< PLL directi control in direct control mode only, use_direct_pll_ctrl set to 1 */
TFA9878_BF_PLLDO = 0xced0, /*!< PLL directo control in direct control mode only, use_direct_pll_ctrl set to 1 */
- TFA9878_BF_PLLCLKSTB= 0xcee0, /*!< PLL FRM clock stable control in direct control mode only, use_direct_pll_ctrl set to 1 */
- TFA9878_BF_PLLFRM= 0xcef0, /*!< PLL free running mode control in functional mode */
- TFA9878_BF_PLLMDECL= 0xcf0f, /*!< Bits 15..0 of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
- TFA9878_BF_PLLPDEC= 0xd006, /*!< PLL PDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
- TFA9878_BF_PLLDCTRL= 0xd070, /*!< Enabled PLL direct control mode, overrules the PLL LUT with I2C register values */
- TFA9878_BF_PLLLIMOFF= 0xd090, /*!< PLL up limiter control in PLL direct bandwidth control mode, pll_bandsel set to 1 */
- TFA9878_BF_PLLSTRTM= 0xd0a2, /*!< PLL startup time selection control */
- TFA9878_BF_SWPROFIL= 0xe00f, /*!< Software profile data */
- TFA9878_BF_SWVSTEP= 0xe10f, /*!< Software vstep information */
- TFA9878_BF_MTPOTC= 0xf000, /*!< Calibration schedule */
+ TFA9878_BF_PLLCLKSTB = 0xcee0, /*!< PLL FRM clock stable control in direct control mode only, use_direct_pll_ctrl set to 1 */
+ TFA9878_BF_PLLFRM = 0xcef0, /*!< PLL free running mode control in functional mode */
+ TFA9878_BF_PLLMDECL = 0xcf0f, /*!< Bits 15..0 of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
+ TFA9878_BF_PLLPDEC = 0xd006, /*!< PLL PDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
+ TFA9878_BF_PLLDCTRL = 0xd070, /*!< Enabled PLL direct control mode, overrules the PLL LUT with I2C register values */
+ TFA9878_BF_PLLLIMOFF = 0xd090, /*!< PLL up limiter control in PLL direct bandwidth control mode, pll_bandsel set to 1 */
+ TFA9878_BF_PLLSTRTM = 0xd0a2, /*!< PLL startup time selection control */
+ TFA9878_BF_SWPROFIL = 0xe00f, /*!< Software profile data */
+ TFA9878_BF_SWVSTEP = 0xe10f, /*!< Software vstep information */
+ TFA9878_BF_MTPOTC = 0xf000, /*!< Calibration schedule */
TFA9878_BF_MTPEX = 0xf010, /*!< Calibration Ron executed */
- TFA9878_BF_DCMCCAPI= 0xf020, /*!< Calibration current limit DCDC */
- TFA9878_BF_DCMCCSB= 0xf030, /*!< Sign bit for delta calibration current limit DCDC */
- TFA9878_BF_USERDEF= 0xf042, /*!< Calibration delta current limit DCDC */
- TFA9878_BF_CUSTINFO= 0xf078, /*!< Reserved space for allowing customer to store speaker information */
+ TFA9878_BF_DCMCCAPI = 0xf020, /*!< Calibration current limit DCDC */
+ TFA9878_BF_DCMCCSB = 0xf030, /*!< Sign bit for delta calibration current limit DCDC */
+ TFA9878_BF_USERDEF = 0xf042, /*!< Calibration delta current limit DCDC */
+ TFA9878_BF_CUSTINFO = 0xf078, /*!< Reserved space for allowing customer to store speaker information */
TFA9878_BF_R25C = 0xf50f, /*!< Ron resistance of speaker coil */
} nxpTfa9878BfEnumList_t;
-#define TFA9878_NAMETABLE static tfaBfName_t Tfa9878DatasheetNames[]= {\
+#define TFA9878_NAMETABLE static tfaBfName_t Tfa9878DatasheetNames[] = {\
{ 0x0, "PWDN"}, /* Powerdown selection , */\
{ 0x10, "I2CR"}, /* I2C Reset - Auto clear , */\
{ 0x30, "AMPE"}, /* Activate Amplifier , */\
@@ -454,10 +454,10 @@ typedef enum nxpTfa9878BfEnumList {
{ 0xf042, "USERDEF"}, /* Calibration delta current limit DCDC , */\
{ 0xf078, "CUSTINFO"}, /* Reserved space for allowing customer to store speaker information, */\
{ 0xf50f, "R25C"}, /* Ron resistance of speaker coil , */\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
+ { 0xffff, "Unknown bitfield enum" } /* not found */\
};
-#define TFA9878_BITNAMETABLE static tfaBfName_t Tfa9878BitNames[]= {\
+#define TFA9878_BITNAMETABLE static tfaBfName_t Tfa9878BitNames[] = {\
{ 0x0, "powerdown"}, /* Powerdown selection , */\
{ 0x10, "reset"}, /* I2C Reset - Auto clear , */\
{ 0x30, "enbl_amplifier"}, /* Activate Amplifier , */\
@@ -942,7 +942,7 @@ typedef enum nxpTfa9878BfEnumList {
{ 0xff61, "fro_shortnwell"}, /* Short 4 or 6 n-well resistors , */\
{ 0xff81, "fro_boost"}, /* Self bias current selection , */\
{ 0xffa4, "calibr_iref_trim"}, /* Trimming control of reference current for OCP , */\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
+ { 0xffff, "Unknown bitfield enum" } /* not found */\
};
enum tfa9878_irq {
@@ -958,7 +958,7 @@ enum tfa9878_irq {
tfa9878_irq_max = 9,
tfa9878_irq_all = -1 /* all irqs */};
-#define TFA9878_IRQ_NAMETABLE static tfaIrqName_t Tfa9878IrqNames[]= {\
+#define TFA9878_IRQ_NAMETABLE static tfaIrqName_t Tfa9878IrqNames[] = {\
{ 0, "STVDDS"},\
{ 1, "STBSTOC"},\
{ 2, "STOTDS"},\
diff --git a/inc/tfa9887_tfafieldnames.h b/sound/soc/codecs/tfa9887_tfafieldnames.h
similarity index 96%
rename from inc/tfa9887_tfafieldnames.h
rename to sound/soc/codecs/tfa9887_tfafieldnames.h
index cd30524..b85ca5b 100644
--- a/inc/tfa9887_tfafieldnames.h
+++ b/sound/soc/codecs/tfa9887_tfafieldnames.h
@@ -1,65 +1,65 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#define TFA9887_I2CVERSION 34
-#define TFA9895_I2CVERSION 34
-#define TFA9887_NAMETABLE static tfaBfName_t Tfa9887DatasheetNames[]= {\
- { 0x402, "I2SF"}, /* I2SFormat data 1 input: , */\
- { 0x431, "CHS12"}, /* ChannelSelection data1 input (In CoolFlux) , */\
- { 0x450, "CHS3"}, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */\
- { 0x461, "CHSA"}, /* Input selection for amplifier , */\
- { 0x4b0, "I2SDOE"}, /* Enable data output , */\
- { 0x4c3, "I2SSR"}, /* sample rate setting , */\
- { 0x500, "BSSBY"}, /* , */\
- { 0x511, "BSSCR"}, /* 00 = 0.56 dB/Sample , */\
- { 0x532, "BSST"}, /* 000 = 2.92V , */\
- { 0x5f0, "I2SDOC"}, /* selection data out , */\
- { 0xa02, "DOLS"}, /* Output selection dataout left channel , */\
- { 0xa32, "DORS"}, /* Output selection dataout right channel , */\
- { 0xa62, "SPKL"}, /* Selection speaker induction , */\
- { 0xa91, "SPKR"}, /* Selection speaker impedance , */\
- { 0xab3, "DCFG"}, /* DCDC speaker current compensation gain , */\
- { 0x4134, "PWMDEL"}, /* PWM DelayBits to set the delay , */\
- { 0x4180, "PWMSH"}, /* PWM Shape , */\
- { 0x4190, "PWMRE"}, /* PWM Bitlength in noise shaper , */\
- { 0x48e1, "TCC"}, /* sample & hold track time: , */\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-
-#define TFA9887_BITNAMETABLE static tfaBfName_t Tfa9887BitNames[]= {\
- { 0x402, "i2s_seti"}, /* I2SFormat data 1 input: , */\
- { 0x431, "chan_sel1"}, /* ChannelSelection data1 input (In CoolFlux) , */\
- { 0x450, "lr_sw_i2si2"}, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */\
- { 0x461, "input_sel"}, /* Input selection for amplifier , */\
- { 0x4b0, "enbl_datao"}, /* Enable data output , */\
- { 0x4c3, "i2s_fs"}, /* sample rate setting , */\
- { 0x500, "bypass_clipper"}, /* , */\
- { 0x511, "vbat_prot_attacktime[1:0]"}, /* 00 = 0.56 dB/Sample , */\
- { 0x532, "vbat_prot_thlevel[2:0]"}, /* 000 = 2.92V , */\
- { 0x5d0, "reset_min_vbat"}, /* to reset the clipper via I2C in case the CF is bypassed, */\
- { 0x5f0, "datao_sel"}, /* selection data out , */\
- { 0xa02, "sel_i2so_l"}, /* Output selection dataout left channel , */\
- { 0xa32, "sel_i2so_r"}, /* Output selection dataout right channel , */\
- { 0xa62, "ctrl_spkr_coil"}, /* Selection speaker induction , */\
- { 0xa91, "ctrl_spr_res"}, /* Selection speaker impedance , */\
- { 0xab3, "ctrl_dcdc_spkr_i_comp_gain"}, /* DCDC speaker current compensation gain , */\
- { 0xaf0, "ctrl_dcdc_spkr_i_comp_sign"}, /* DCDC speaker current compensation sign , */\
- { 0x4100, "bypass_hp"}, /* bypass_hp, to bypass the hp filter byhind the CoolFlux, */\
- { 0x4110, "hard_mute"}, /* hard mute setting in HW , */\
- { 0x4120, "soft_mute"}, /* Soft mute setting in HW , */\
- { 0x4134, "PWM_Delay[4:0]"}, /* PWM DelayBits to set the delay , */\
- { 0x4180, "PWM_Shape"}, /* PWM Shape , */\
- { 0x4190, "PWM_BitLength"}, /* PWM Bitlength in noise shaper , */\
- { 0x4800, "ctrl_negin"}, /* , */\
- { 0x4810, "ctrl_cs_sein"}, /* , */\
- { 0x4820, "ctrl_coincidencecs"}, /* HIGH => Prevent dcdc switching during clk_cs_clksh, */\
- { 0x4876, "delay_se_neg[6:0]"}, /* delayshiftse2 , */\
- { 0x48e1, "ctrl_cs_ttrack[1:0]"}, /* sample & hold track time: , */\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#define TFA9887_I2CVERSION 34
+#define TFA9895_I2CVERSION 34
+#define TFA9887_NAMETABLE static tfaBfName_t Tfa9887DatasheetNames[] = {\
+ { 0x402, "I2SF"}, /* I2SFormat data 1 input: , */\
+ { 0x431, "CHS12"}, /* ChannelSelection data1 input (In CoolFlux) , */\
+ { 0x450, "CHS3"}, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */\
+ { 0x461, "CHSA"}, /* Input selection for amplifier , */\
+ { 0x4b0, "I2SDOE"}, /* Enable data output , */\
+ { 0x4c3, "I2SSR"}, /* sample rate setting , */\
+ { 0x500, "BSSBY"}, /* , */\
+ { 0x511, "BSSCR"}, /* 00 = 0.56 dB/Sample , */\
+ { 0x532, "BSST"}, /* 000 = 2.92V , */\
+ { 0x5f0, "I2SDOC"}, /* selection data out , */\
+ { 0xa02, "DOLS"}, /* Output selection dataout left channel , */\
+ { 0xa32, "DORS"}, /* Output selection dataout right channel , */\
+ { 0xa62, "SPKL"}, /* Selection speaker induction , */\
+ { 0xa91, "SPKR"}, /* Selection speaker impedance , */\
+ { 0xab3, "DCFG"}, /* DCDC speaker current compensation gain , */\
+ { 0x4134, "PWMDEL"}, /* PWM DelayBits to set the delay , */\
+ { 0x4180, "PWMSH"}, /* PWM Shape , */\
+ { 0x4190, "PWMRE"}, /* PWM Bitlength in noise shaper , */\
+ { 0x48e1, "TCC"}, /* sample & hold track time: , */\
+ { 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+
+#define TFA9887_BITNAMETABLE static tfaBfName_t Tfa9887BitNames[] = {\
+ { 0x402, "i2s_seti"}, /* I2SFormat data 1 input: , */\
+ { 0x431, "chan_sel1"}, /* ChannelSelection data1 input (In CoolFlux) , */\
+ { 0x450, "lr_sw_i2si2"}, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */\
+ { 0x461, "input_sel"}, /* Input selection for amplifier , */\
+ { 0x4b0, "enbl_datao"}, /* Enable data output , */\
+ { 0x4c3, "i2s_fs"}, /* sample rate setting , */\
+ { 0x500, "bypass_clipper"}, /* , */\
+ { 0x511, "vbat_prot_attacktime[1:0]"}, /* 00 = 0.56 dB/Sample , */\
+ { 0x532, "vbat_prot_thlevel[2:0]"}, /* 000 = 2.92V , */\
+ { 0x5d0, "reset_min_vbat"}, /* to reset the clipper via I2C in case the CF is bypassed, */\
+ { 0x5f0, "datao_sel"}, /* selection data out , */\
+ { 0xa02, "sel_i2so_l"}, /* Output selection dataout left channel , */\
+ { 0xa32, "sel_i2so_r"}, /* Output selection dataout right channel , */\
+ { 0xa62, "ctrl_spkr_coil"}, /* Selection speaker induction , */\
+ { 0xa91, "ctrl_spr_res"}, /* Selection speaker impedance , */\
+ { 0xab3, "ctrl_dcdc_spkr_i_comp_gain"}, /* DCDC speaker current compensation gain , */\
+ { 0xaf0, "ctrl_dcdc_spkr_i_comp_sign"}, /* DCDC speaker current compensation sign , */\
+ { 0x4100, "bypass_hp"}, /* bypass_hp, to bypass the hp filter byhind the CoolFlux, */\
+ { 0x4110, "hard_mute"}, /* hard mute setting in HW , */\
+ { 0x4120, "soft_mute"}, /* Soft mute setting in HW , */\
+ { 0x4134, "PWM_Delay[4:0]"}, /* PWM DelayBits to set the delay , */\
+ { 0x4180, "PWM_Shape"}, /* PWM Shape , */\
+ { 0x4190, "PWM_BitLength"}, /* PWM Bitlength in noise shaper , */\
+ { 0x4800, "ctrl_negin"}, /* , */\
+ { 0x4810, "ctrl_cs_sein"}, /* , */\
+ { 0x4820, "ctrl_coincidencecs"}, /* HIGH => Prevent dcdc switching during clk_cs_clksh, */\
+ { 0x4876, "delay_se_neg[6:0]"}, /* delayshiftse2 , */\
+ { 0x48e1, "ctrl_cs_ttrack[1:0]"}, /* sample & hold track time: , */\
+ { 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+
diff --git a/inc/tfa9890_tfafieldnames.h b/sound/soc/codecs/tfa9890_tfafieldnames.h
similarity index 97%
rename from inc/tfa9890_tfafieldnames.h
rename to sound/soc/codecs/tfa9890_tfafieldnames.h
index 2b42c35..ad043bc 100644
--- a/inc/tfa9890_tfafieldnames.h
+++ b/sound/soc/codecs/tfa9890_tfafieldnames.h
@@ -1,80 +1,80 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#define TFA9890_I2CVERSION 34
-#define TFA9890_NAMETABLE static tfaBfName_t Tfa9890DatasheetNames[]= {\
- { 0x402, "I2SF"}, /* I2SFormat data 1 input: , */\
- { 0x431, "CHS12"}, /* ChannelSelection data1 input (In CoolFlux) , */\
- { 0x450, "CHS3"}, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */\
- { 0x461, "CHSA"}, /* Input selection for amplifier , */\
- { 0x481, "I2SDOC"}, /* selection data out , */\
- { 0x4a0, "DISP"}, /* idp protection , */\
- { 0x4b0, "I2SDOE"}, /* Enable data output , */\
- { 0x4c3, "I2SSR"}, /* sample rate setting , */\
- { 0x732, "DCMCC"}, /* Max boost coil current - step of 500 mA , */\
- { 0x9c0, "CCFD"}, /* Selection CoolFlux Clock , */\
- { 0x9d0, "ISEL"}, /* selection input 1 or 2 , */\
- { 0xa02, "DOLS"}, /* Output selection dataout left channel , */\
- { 0xa32, "DORS"}, /* Output selection dataout right channel , */\
- { 0xa62, "SPKL"}, /* Selection speaker induction , */\
- { 0xa91, "SPKR"}, /* Selection speaker impedance , */\
- { 0xab3, "DCFG"}, /* DCDC speaker current compensation gain , */\
- { 0xf00, "VDDD"}, /* mask flag_por for interupt generation , */\
- { 0xf10, "OTDD"}, /* mask flag_otpok for interupt generation , */\
- { 0xf20, "OVDD"}, /* mask flag_ovpok for interupt generation , */\
- { 0xf30, "UVDD"}, /* mask flag_uvpok for interupt generation , */\
- { 0xf40, "OCDD"}, /* mask flag_ocp_alarm for interupt generation , */\
- { 0xf50, "CLKD"}, /* mask flag_clocks_stable for interupt generation , */\
- { 0xf60, "DCCD"}, /* mask flag_pwrokbst for interupt generation , */\
- { 0xf70, "SPKD"}, /* mask flag_cf_speakererror for interupt generation , */\
- { 0xf80, "WDD"}, /* mask flag_watchdog_reset for interupt generation , */\
- { 0xf90, "LCLK"}, /* mask flag_lost_clk for interupt generation , */\
- { 0xfe0, "INT"}, /* enabling interrupt , */\
- { 0xff0, "INTP"}, /* Setting polarity interupt , */\
- { 0x8f0f, "VERSION"}, /* (key1 protected) , */\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-
-#define TFA9890_BITNAMETABLE static tfaBfName_t Tfa9890BitNames[]= {\
- { 0x402, "i2s_seti"}, /* I2SFormat data 1 input: , */\
- { 0x431, "chan_sel1"}, /* ChannelSelection data1 input (In CoolFlux) , */\
- { 0x450, "lr_sw_i2si2"}, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */\
- { 0x461, "input_sel"}, /* Input selection for amplifier , */\
- { 0x481, "datao_sel"}, /* selection data out , */\
- { 0x4a0, "disable_idp"}, /* idp protection , */\
- { 0x4b0, "enbl_datao"}, /* Enable data output , */\
- { 0x4c3, "i2s_fs"}, /* sample rate setting , */\
- { 0x732, "ctrl_bstcur"}, /* Max boost coil current - step of 500 mA , */\
- { 0x9c0, "sel_cf_clk"}, /* Selection CoolFlux Clock , */\
- { 0x9d0, "intf_sel"}, /* selection input 1 or 2 , */\
- { 0xa02, "sel_i2so_l"}, /* Output selection dataout left channel , */\
- { 0xa32, "sel_i2so_r"}, /* Output selection dataout right channel , */\
- { 0xa62, "ctrl_spkr_coil"}, /* Selection speaker induction , */\
- { 0xa91, "ctrl_spr_res"}, /* Selection speaker impedance , */\
- { 0xab3, "ctrl_dcdc_spkr_i_comp_gain"}, /* DCDC speaker current compensation gain , */\
- { 0xaf0, "ctrl_dcdc_spkr_i_comp_sign"}, /* DCDC speaker current compensation sign , */\
- { 0xf00, "flag_por_mask"}, /* mask flag_por for interupt generation , */\
- { 0xf10, "flag_otpok_mask"}, /* mask flag_otpok for interupt generation , */\
- { 0xf20, "flag_ovpok_mask"}, /* mask flag_ovpok for interupt generation , */\
- { 0xf30, "flag_uvpok_mask"}, /* mask flag_uvpok for interupt generation , */\
- { 0xf40, "flag_ocp_alarm_mask"}, /* mask flag_ocp_alarm for interupt generation , */\
- { 0xf50, "flag_clocks_stable_mask"}, /* mask flag_clocks_stable for interupt generation , */\
- { 0xf60, "flag_pwrokbst_mask"}, /* mask flag_pwrokbst for interupt generation , */\
- { 0xf70, "flag_cf_speakererror_mask"}, /* mask flag_cf_speakererror for interupt generation , */\
- { 0xf80, "flag_watchdog_reset_mask"}, /* mask flag_watchdog_reset for interupt generation , */\
- { 0xf90, "flag_lost_clk_mask"}, /* mask flag_lost_clk for interupt generation , */\
- { 0xfe0, "enable_interrupt"}, /* enabling interrupt , */\
- { 0xff0, "invert_int_polarity"}, /* Setting polarity interupt , */\
- { 0x4700, "switch_fb"}, /* switch_fb , */\
- { 0x4713, "se_hyst"}, /* se_hyst , */\
- { 0x4754, "se_level"}, /* se_level , */\
- { 0x47a5, "ktemp"}, /* temperature compensation trimming , */\
- { 0x8f0f, "production_data6"}, /* (key1 protected) , */\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#define TFA9890_I2CVERSION 34
+#define TFA9890_NAMETABLE static tfaBfName_t Tfa9890DatasheetNames[] = {\
+ { 0x402, "I2SF"}, /* I2SFormat data 1 input: , */\
+ { 0x431, "CHS12"}, /* ChannelSelection data1 input (In CoolFlux) , */\
+ { 0x450, "CHS3"}, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */\
+ { 0x461, "CHSA"}, /* Input selection for amplifier , */\
+ { 0x481, "I2SDOC"}, /* selection data out , */\
+ { 0x4a0, "DISP"}, /* idp protection , */\
+ { 0x4b0, "I2SDOE"}, /* Enable data output , */\
+ { 0x4c3, "I2SSR"}, /* sample rate setting , */\
+ { 0x732, "DCMCC"}, /* Max boost coil current - step of 500 mA , */\
+ { 0x9c0, "CCFD"}, /* Selection CoolFlux Clock , */\
+ { 0x9d0, "ISEL"}, /* selection input 1 or 2 , */\
+ { 0xa02, "DOLS"}, /* Output selection dataout left channel , */\
+ { 0xa32, "DORS"}, /* Output selection dataout right channel , */\
+ { 0xa62, "SPKL"}, /* Selection speaker induction , */\
+ { 0xa91, "SPKR"}, /* Selection speaker impedance , */\
+ { 0xab3, "DCFG"}, /* DCDC speaker current compensation gain , */\
+ { 0xf00, "VDDD"}, /* mask flag_por for interupt generation , */\
+ { 0xf10, "OTDD"}, /* mask flag_otpok for interupt generation , */\
+ { 0xf20, "OVDD"}, /* mask flag_ovpok for interupt generation , */\
+ { 0xf30, "UVDD"}, /* mask flag_uvpok for interupt generation , */\
+ { 0xf40, "OCDD"}, /* mask flag_ocp_alarm for interupt generation , */\
+ { 0xf50, "CLKD"}, /* mask flag_clocks_stable for interupt generation , */\
+ { 0xf60, "DCCD"}, /* mask flag_pwrokbst for interupt generation , */\
+ { 0xf70, "SPKD"}, /* mask flag_cf_speakererror for interupt generation , */\
+ { 0xf80, "WDD"}, /* mask flag_watchdog_reset for interupt generation , */\
+ { 0xf90, "LCLK"}, /* mask flag_lost_clk for interupt generation , */\
+ { 0xfe0, "INT"}, /* enabling interrupt , */\
+ { 0xff0, "INTP"}, /* Setting polarity interupt , */\
+ { 0x8f0f, "VERSION"}, /* (key1 protected) , */\
+ { 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+
+#define TFA9890_BITNAMETABLE static tfaBfName_t Tfa9890BitNames[] = {\
+ { 0x402, "i2s_seti"}, /* I2SFormat data 1 input: , */\
+ { 0x431, "chan_sel1"}, /* ChannelSelection data1 input (In CoolFlux) , */\
+ { 0x450, "lr_sw_i2si2"}, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */\
+ { 0x461, "input_sel"}, /* Input selection for amplifier , */\
+ { 0x481, "datao_sel"}, /* selection data out , */\
+ { 0x4a0, "disable_idp"}, /* idp protection , */\
+ { 0x4b0, "enbl_datao"}, /* Enable data output , */\
+ { 0x4c3, "i2s_fs"}, /* sample rate setting , */\
+ { 0x732, "ctrl_bstcur"}, /* Max boost coil current - step of 500 mA , */\
+ { 0x9c0, "sel_cf_clk"}, /* Selection CoolFlux Clock , */\
+ { 0x9d0, "intf_sel"}, /* selection input 1 or 2 , */\
+ { 0xa02, "sel_i2so_l"}, /* Output selection dataout left channel , */\
+ { 0xa32, "sel_i2so_r"}, /* Output selection dataout right channel , */\
+ { 0xa62, "ctrl_spkr_coil"}, /* Selection speaker induction , */\
+ { 0xa91, "ctrl_spr_res"}, /* Selection speaker impedance , */\
+ { 0xab3, "ctrl_dcdc_spkr_i_comp_gain"}, /* DCDC speaker current compensation gain , */\
+ { 0xaf0, "ctrl_dcdc_spkr_i_comp_sign"}, /* DCDC speaker current compensation sign , */\
+ { 0xf00, "flag_por_mask"}, /* mask flag_por for interupt generation , */\
+ { 0xf10, "flag_otpok_mask"}, /* mask flag_otpok for interupt generation , */\
+ { 0xf20, "flag_ovpok_mask"}, /* mask flag_ovpok for interupt generation , */\
+ { 0xf30, "flag_uvpok_mask"}, /* mask flag_uvpok for interupt generation , */\
+ { 0xf40, "flag_ocp_alarm_mask"}, /* mask flag_ocp_alarm for interupt generation , */\
+ { 0xf50, "flag_clocks_stable_mask"}, /* mask flag_clocks_stable for interupt generation , */\
+ { 0xf60, "flag_pwrokbst_mask"}, /* mask flag_pwrokbst for interupt generation , */\
+ { 0xf70, "flag_cf_speakererror_mask"}, /* mask flag_cf_speakererror for interupt generation , */\
+ { 0xf80, "flag_watchdog_reset_mask"}, /* mask flag_watchdog_reset for interupt generation , */\
+ { 0xf90, "flag_lost_clk_mask"}, /* mask flag_lost_clk for interupt generation , */\
+ { 0xfe0, "enable_interrupt"}, /* enabling interrupt , */\
+ { 0xff0, "invert_int_polarity"}, /* Setting polarity interupt , */\
+ { 0x4700, "switch_fb"}, /* switch_fb , */\
+ { 0x4713, "se_hyst"}, /* se_hyst , */\
+ { 0x4754, "se_level"}, /* se_level , */\
+ { 0x47a5, "ktemp"}, /* temperature compensation trimming , */\
+ { 0x8f0f, "production_data6"}, /* (key1 protected) , */\
+ { 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+
diff --git a/inc/tfa9891_tfafieldnames.h b/sound/soc/codecs/tfa9891_tfafieldnames.h
similarity index 99%
rename from inc/tfa9891_tfafieldnames.h
rename to sound/soc/codecs/tfa9891_tfafieldnames.h
index d18683a..8aa691f 100644
--- a/inc/tfa9891_tfafieldnames.h
+++ b/sound/soc/codecs/tfa9891_tfafieldnames.h
@@ -1,512 +1,512 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef TFA_INC_TFA9891_TFAFIELDNAMES_H_
-#define TFA_INC_TFA9891_TFAFIELDNAMES_H_
-
-#define TFA9891_I2CVERSION 13
-
-
-#define TFA9891_NAMETABLE static tfaBfName_t Tfa9891DatasheetNames[]= {\
- { 0x0, "VDDS"}, /* POR , */\
- { 0x10, "PLLS"}, /* PLL , */\
- { 0x20, "OTDS"}, /* OTP , */\
- { 0x30, "OVDS"}, /* OVP , */\
- { 0x40, "UVDS"}, /* UVP , */\
- { 0x50, "OCDS"}, /* OCP , */\
- { 0x60, "CLKS"}, /* Clocks , */\
- { 0x70, "CLIPS"}, /* CLIP , */\
- { 0x80, "MTPB"}, /* MTP , */\
- { 0x90, "DCCS"}, /* BOOST , */\
- { 0xa0, "SPKS"}, /* Speaker , */\
- { 0xb0, "ACS"}, /* cold start flag , */\
- { 0xc0, "SWS"}, /* flag engage , */\
- { 0xd0, "WDS"}, /* flag watchdog reset , */\
- { 0xe0, "AMPS"}, /* amplifier is enabled by manager , */\
- { 0xf0, "AREFS"}, /* references are enabled by manager , */\
- { 0x109, "BATS"}, /* Battery voltage readout; 0[V]..5.5[V] , */\
- { 0x208, "TEMPS"}, /* Temperature readout , */\
- { 0x307, "REV"}, /* Device Revision , */\
- { 0x402, "I2SF"}, /* I2SFormat data 1 input , */\
- { 0x431, "CHS12"}, /* ChannelSelection data1 input (In CoolFlux) , */\
- { 0x450, "CHS3"}, /* Channel Selection data 2 input (coolflux input, the DCDC converter gets the other signal), */\
- { 0x461, "CHSA"}, /* Input selection for amplifier , */\
- { 0x481, "I2SDOC"}, /* Selection for I2S data out , */\
- { 0x4a0, "DISP"}, /* idp protection , */\
- { 0x4b0, "I2SDOE"}, /* Enable data output , */\
- { 0x4c3, "I2SSR"}, /* sample rate setting , */\
- { 0x501, "BSSCR"}, /* ProtectionAttackTime , */\
- { 0x523, "BSST"}, /* ProtectionThreshold , */\
- { 0x561, "BSSRL"}, /* ProtectionMaximumReduction , */\
- { 0x582, "BSSRR"}, /* Protection Release Timer , */\
- { 0x5b1, "BSSHY"}, /* ProtectionHysterese , */\
- { 0x5e0, "BSSR"}, /* battery voltage for I2C read out only , */\
- { 0x5f0, "BSSBY"}, /* bypass clipper battery protection , */\
- { 0x600, "DPSA"}, /* Enable dynamic powerstage activation , */\
- { 0x613, "AMPSL"}, /* control slope , */\
- { 0x650, "CFSM"}, /* Soft mute in CoolFlux , */\
- { 0x670, "BSSS"}, /* batsensesteepness , */\
- { 0x687, "VOL"}, /* volume control (in CoolFlux) , */\
- { 0x702, "DCVO"}, /* Boost voltage , */\
- { 0x732, "DCMCC"}, /* Max boost coil current , */\
- { 0x7a0, "DCIE"}, /* Adaptive boost mode , */\
- { 0x7b0, "DCSR"}, /* Soft RampUp/Down mode for DCDC controller , */\
- { 0x800, "TROS"}, /* select external temperature also the ext_temp will be put on the temp read out , */\
- { 0x818, "EXTTS"}, /* external temperature setting to be given by host , */\
- { 0x900, "PWDN"}, /* ON/OFF , */\
- { 0x910, "I2CR"}, /* I2CReset , */\
- { 0x920, "CFE"}, /* EnableCoolFlux , */\
- { 0x930, "AMPE"}, /* EnableAmplifier , */\
- { 0x940, "DCA"}, /* EnableBoost , */\
- { 0x950, "SBSL"}, /* Coolflux configured , */\
- { 0x960, "AMPC"}, /* Selection on how AmplifierEnabling , */\
- { 0x970, "DCDIS"}, /* DCDC not connected , */\
- { 0x980, "PSDR"}, /* Iddq test amplifier , */\
- { 0x991, "DCCV"}, /* Coil Value , */\
- { 0x9b1, "CCFD"}, /* Selection CoolFluxClock , */\
- { 0x9d0, "ISEL"}, /* Interface Selection , */\
- { 0x9e0, "IPLL"}, /* selection input PLL for lock , */\
- { 0xa02, "DOLS"}, /* Output selection dataout left channel , */\
- { 0xa32, "DORS"}, /* Output selection dataout right channel , */\
- { 0xa62, "SPKL"}, /* Selection speaker induction , */\
- { 0xa91, "SPKR"}, /* Selection speaker impedance , */\
- { 0xab3, "DCFG"}, /* DCDC speaker current compensation gain , */\
- { 0xb07, "MTPK"}, /* MTP KEY2 register , */\
- { 0xf00, "VDDD"}, /* mask flag_por for interupt generation , */\
- { 0xf10, "OTDD"}, /* mask flag_otpok for interupt generation , */\
- { 0xf20, "OVDD"}, /* mask flag_ovpok for interupt generation , */\
- { 0xf30, "UVDD"}, /* mask flag_uvpok for interupt generation , */\
- { 0xf40, "OCDD"}, /* mask flag_ocp_alarm for interupt generation , */\
- { 0xf50, "CLKD"}, /* mask flag_clocks_stable for interupt generation , */\
- { 0xf60, "DCCD"}, /* mask flag_pwrokbst for interupt generation , */\
- { 0xf70, "SPKD"}, /* mask flag_cf_speakererror for interupt generation , */\
- { 0xf80, "WDD"}, /* mask flag_watchdog_reset for interupt generation , */\
- { 0xfe0, "INT"}, /* enabling interrupt , */\
- { 0xff0, "INTP"}, /* Setting polarity interupt , */\
- { 0x1000, "PDMSEL"}, /* Audio input interface mode , */\
- { 0x1010, "I2SMOUTEN"}, /* I2S Master enable (CLK and WS pads) , */\
- { 0x1021, "PDMORSEL"}, /* PDM Output right channel source selection , */\
- { 0x1041, "PDMOLSEL"}, /* PDM Output Left/Mono channel source selection , */\
- { 0x1061, "PADSEL"}, /* Output interface mode and ball selection , */\
- { 0x1100, "PDMOSDEN"}, /* Secure delay Cell , */\
- { 0x1110, "PDMOSDCF"}, /* Rising Falling Resync control Mux , */\
- { 0x1140, "SAAMEN"}, /* Speaker As a Mic feature ON/OFF , */\
- { 0x1150, "SAAMLPEN"}, /* speaker_as_mic low power mode (only in PDM_out mode), */\
- { 0x1160, "PDMOINTEN"}, /* PDM output interpolation ratio , */\
- { 0x1203, "PDMORG1"}, /* PDM Interpolator Right Channel DS4 G1 Gain Value , */\
- { 0x1243, "PDMORG2"}, /* PDM Interpolator Right Channel DS4 G2 Gain Value , */\
- { 0x1303, "PDMOLG1"}, /* PDM Interpolator Left Channel DS4 G1 Gain Value , */\
- { 0x1343, "PDMOLG2"}, /* PDM Interpolator Left Channel DS4 G2 Gain Value , */\
- { 0x2202, "SAAMGAIN"}, /* pga gain , */\
- { 0x2250, "SAAMPGACTRL"}, /* 0 = active input common mode voltage source at the attenuator/PGA level, */\
- { 0x2500, "PLLCCOSEL"}, /* pll cco frequency , */\
- { 0x4600, "CSBYPGC"}, /* bypass_gc, bypasses the CS gain correction , */\
- { 0x4900, "CLIP"}, /* Bypass clip control (function depending on digimux clip_x), */\
- { 0x4910, "CLIP2"}, /* Bypass clip control (function depending on digimux clip_x), */\
- { 0x62b0, "CIMTP"}, /* start copying all the data from i2cregs_mtp to mtp [Key 2 protected], */\
- { 0x7000, "RST"}, /* Reset CoolFlux DSP , */\
- { 0x7011, "DMEM"}, /* Target memory for access , */\
- { 0x7030, "AIF"}, /* Autoincrement-flag for memory-address , */\
- { 0x7040, "CFINT"}, /* Interrupt CoolFlux DSP , */\
- { 0x7087, "REQ"}, /* request for access (8 channels) , */\
- { 0x710f, "MADD"}, /* memory-address to be accessed , */\
- { 0x720f, "MEMA"}, /* activate memory access (24- or 32-bits data is written/read to/from memory, */\
- { 0x7307, "ERR"}, /* cf error Flags , */\
- { 0x7387, "ACK"}, /* acknowledge of requests (8 channels")" , */\
- { 0x8000, "MTPOTC"}, /* Calibration schedule (key2 protected) , */\
- { 0x8010, "MTPEX"}, /* (key2 protected) calibration of Ron has been executed, */\
- { 0x8045, "SWPROFIL" },\
- { 0x80a5, "SWVSTEP" },\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-
-#define TFA9891_BITNAMETABLE static tfaBfName_t Tfa9891BitNames[]= {\
- { 0x0, "POR"}, /* POR , */\
- { 0x10, "PLL_LOCK"}, /* PLL , */\
- { 0x20, "flag_otpok"}, /* OTP , */\
- { 0x30, "flag_ovpok"}, /* OVP , */\
- { 0x40, "flag_uvpok"}, /* UVP , */\
- { 0x50, "flag_OCP_alarm"}, /* OCP , */\
- { 0x60, "flag_clocks_stable"}, /* Clocks , */\
- { 0x70, "CLIP"}, /* CLIP , */\
- { 0x80, "mtp_busy"}, /* MTP , */\
- { 0x90, "flag_pwrokbst"}, /* BOOST , */\
- { 0xa0, "flag_cf_speakererror"}, /* Speaker , */\
- { 0xb0, "flag_cold_started"}, /* cold start flag , */\
- { 0xc0, "flag_engage"}, /* flag engage , */\
- { 0xd0, "flag_watchdog_reset"}, /* flag watchdog reset , */\
- { 0xe0, "flag_enbl_amp"}, /* amplifier is enabled by manager , */\
- { 0xf0, "flag_enbl_ref"}, /* references are enabled by manager , */\
- { 0x109, "bat_adc"}, /* Battery voltage readout; 0[V]..5.5[V] , */\
- { 0x208, "temp_adc"}, /* Temperature readout , */\
- { 0x307, "rev_reg"}, /* Device Revision , */\
- { 0x402, "i2s_seti"}, /* I2SFormat data 1 input , */\
- { 0x431, "chan_sel1"}, /* ChannelSelection data1 input (In CoolFlux) , */\
- { 0x450, "lr_sw_i2si2"}, /* Channel Selection data 2 input (coolflux input, the DCDC converter gets the other signal), */\
- { 0x461, "input_sel"}, /* Input selection for amplifier , */\
- { 0x481, "datao_sel"}, /* Selection for I2S data out , */\
- { 0x4a0, "disable_idp"}, /* idp protection , */\
- { 0x4b0, "enbl_datao"}, /* Enable data output , */\
- { 0x4c3, "i2s_fs"}, /* sample rate setting , */\
- { 0x501, "vbat_prot_attacktime"}, /* ProtectionAttackTime , */\
- { 0x523, "vbat_prot_thlevel"}, /* ProtectionThreshold , */\
- { 0x561, "vbat_prot_max_reduct"}, /* ProtectionMaximumReduction , */\
- { 0x582, "vbat_prot_release_t"}, /* Protection Release Timer , */\
- { 0x5b1, "vbat_prot_hysterese"}, /* ProtectionHysterese , */\
- { 0x5d0, "reset_min_vbat"}, /* reset clipper , */\
- { 0x5e0, "sel_vbat"}, /* battery voltage for I2C read out only , */\
- { 0x5f0, "bypass_clipper"}, /* bypass clipper battery protection , */\
- { 0x600, "dpsa"}, /* Enable dynamic powerstage activation , */\
- { 0x613, "ctrl_slope"}, /* control slope , */\
- { 0x650, "cf_mute"}, /* Soft mute in CoolFlux , */\
- { 0x660, "sel_other_vamp"}, /* Input selection for the second channel of the DCDC inteligent mode detector, */\
- { 0x670, "ctrl_batsensesteepness"}, /* batsensesteepness , */\
- { 0x687, "vol"}, /* volume control (in CoolFlux) , */\
- { 0x702, "ctrl_bstvolt"}, /* Boost voltage , */\
- { 0x732, "ctrl_bstcur"}, /* Max boost coil current , */\
- { 0x761, "ctrl_slopebst_1_0"}, /* Setting for the slope of the boost converter power stage, */\
- { 0x781, "ctrl_slopebst_3_2"}, /* Setting for the part of the power transistor voltage to be used in peak current mode control, */\
- { 0x7a0, "boost_intel"}, /* Adaptive boost mode , */\
- { 0x7b0, "boost_speed"}, /* Soft RampUp/Down mode for DCDC controller , */\
- { 0x7c1, "ctrl_delay_comp_dcdc"}, /* delay compensation in current patg compared to delay in the audio path (relative) , */\
- { 0x7e0, "boost_input"}, /* Selection intelligent boost detector input , */\
- { 0x7f0, "ctrl_supplysense"}, /* ADC10 input selection , */\
- { 0x800, "ext_temp_sel"}, /* select external temperature also the ext_temp will be put on the temp read out , */\
- { 0x818, "ext_temp"}, /* external temperature setting to be given by host , */\
- { 0x8a0, "ctrl_spk_coilpvp_bst"}, /* Peak voltage protection boost converter , */\
- { 0x8b2, "ctrl_dcdc_synchronisation"}, /* DCDC synchronisation off + 7 positions , */\
- { 0x8e0, "ctrl_cs_samplevalid"}, /* sample valid moment for CS in single sample moment mode, */\
- { 0x900, "PowerDown"}, /* ON/OFF , */\
- { 0x910, "reset"}, /* I2CReset , */\
- { 0x920, "enbl_coolflux"}, /* EnableCoolFlux , */\
- { 0x930, "enbl_amplifier"}, /* EnableAmplifier , */\
- { 0x940, "enbl_boost"}, /* EnableBoost , */\
- { 0x950, "cf_configured"}, /* Coolflux configured , */\
- { 0x960, "sel_enbl_amplifier"}, /* Selection on how AmplifierEnabling , */\
- { 0x970, "dcdcoff_mode"}, /* DCDC not connected , */\
- { 0x980, "cttr_iddqtest"}, /* Iddq test amplifier , */\
- { 0x991, "ctrl_coil_value"}, /* Coil Value , */\
- { 0x9b1, "ctrl_sel_cf_clock"}, /* Selection CoolFluxClock , */\
- { 0x9d0, "intf_sel"}, /* Interface Selection , */\
- { 0x9e0, "sel_ws_bck"}, /* selection input PLL for lock , */\
- { 0xa02, "sel_i2so_l"}, /* Output selection dataout left channel , */\
- { 0xa32, "sel_i2so_r"}, /* Output selection dataout right channel , */\
- { 0xa62, "ctrl_spkr_coil"}, /* Selection speaker induction , */\
- { 0xa91, "ctrl_spr_res"}, /* Selection speaker impedance , */\
- { 0xab3, "ctrl_dcdc_spkr_i_comp_gain"}, /* DCDC speaker current compensation gain , */\
- { 0xaf0, "ctrl_dcdc_spkr_i_comp_sign"}, /* DCDC speaker current compensation sign , */\
- { 0xb07, "MTP_key2"}, /* MTP KEY2 register , */\
- { 0xc0c, "clk_sync_delay"}, /* Delay count for clock synchronisation , */\
- { 0xcf0, "enbl_clk_sync"}, /* Enable CGU clock synchronisation , */\
- { 0xd0c, "adc_sync_delay"}, /* Delay count for ADC synchronisation , */\
- { 0xdf0, "enable_adc_sync"}, /* Enable ADC synchronisation , */\
- { 0xe00, "bypass_dcdc_curr_prot"}, /* to switch off dcdc reduction with bat prot , */\
- { 0xe24, "ctrl_digtoana6_2"}, /* for extra connections digital to analog , */\
- { 0xe70, "switch_on_icomp"}, /* icomp dem switch , */\
- { 0xe87, "reserve_reg_1_7_0"}, /* reserved , */\
- { 0xf00, "flag_por_mask"}, /* mask flag_por for interupt generation , */\
- { 0xf10, "flag_otpok_mask"}, /* mask flag_otpok for interupt generation , */\
- { 0xf20, "flag_ovpok_mask"}, /* mask flag_ovpok for interupt generation , */\
- { 0xf30, "flag_uvpok_mask"}, /* mask flag_uvpok for interupt generation , */\
- { 0xf40, "flag_ocp_alarm_mask"}, /* mask flag_ocp_alarm for interupt generation , */\
- { 0xf50, "flag_clocks_stable_mask"}, /* mask flag_clocks_stable for interupt generation , */\
- { 0xf60, "flag_pwrokbst_mask"}, /* mask flag_pwrokbst for interupt generation , */\
- { 0xf70, "flag_cf_speakererror_mask"}, /* mask flag_cf_speakererror for interupt generation , */\
- { 0xf80, "flag_watchdog_reset_mask"}, /* mask flag_watchdog_reset for interupt generation , */\
- { 0xf90, "flag_lost_clk_mask"}, /* mask flag_lost_clk for interupt generation , */\
- { 0xfe0, "enable_interrupt"}, /* enabling interrupt , */\
- { 0xff0, "invert_int_polarity"}, /* Setting polarity interupt , */\
- { 0x1000, "pdm_i2s_input"}, /* Audio input interface mode , */\
- { 0x1010, "I2S_master_ena"}, /* I2S Master enable (CLK and WS pads) , */\
- { 0x1021, "pdm_out_sel_r"}, /* PDM Output right channel source selection , */\
- { 0x1041, "pdm_out_sel_l"}, /* PDM Output Left/Mono channel source selection , */\
- { 0x1061, "micdat_out_sel"}, /* Output interface mode and ball selection , */\
- { 0x1100, "secure_dly"}, /* Secure delay Cell , */\
- { 0x1110, "d_out_valid_rf_mux"}, /* Rising Falling Resync control Mux , */\
- { 0x1140, "Speak_As_Mic_en"}, /* Speaker As a Mic feature ON/OFF , */\
- { 0x1150, "speak_as_mic_lp_mode"}, /* speaker_as_mic low power mode (only in PDM_out mode), */\
- { 0x1160, "pdm_out_rate"}, /* PDM output interpolation ratio , */\
- { 0x1203, "ds4_g1_r"}, /* PDM Interpolator Right Channel DS4 G1 Gain Value , */\
- { 0x1243, "ds4_g2_r"}, /* PDM Interpolator Right Channel DS4 G2 Gain Value , */\
- { 0x1303, "ds4_g1_l"}, /* PDM Interpolator Left Channel DS4 G1 Gain Value , */\
- { 0x1343, "ds4_g2_l"}, /* PDM Interpolator Left Channel DS4 G2 Gain Value , */\
- { 0x1400, "clk_secure_dly"}, /* Secure delay Cell on clock path , */\
- { 0x1410, "data_secure_dly"}, /* Secure delay Cell enable on PDM data path , */\
- { 0x2202, "Ctrl_saam_pga_gain"}, /* pga gain , */\
- { 0x2250, "ctrl_saam_pga_src"}, /* 0 = active input common mode voltage source at the attenuator/PGA level, */\
- { 0x2300, "flag_saam_spare"}, /* spare flag , */\
- { 0x2400, "ctrl_saam_pga_tm"}, /* enables PGA test mode , */\
- { 0x2500, "pll_fcco"}, /* pll cco frequency , */\
- { 0x3000, "flag_hi_small"}, /* positive small window dcdc converter , */\
- { 0x3010, "flag_hi_large"}, /* positive large window dcdc converter , */\
- { 0x3020, "flag_lo_small"}, /* negative small window dcdc converter , */\
- { 0x3030, "flag_lo_large"}, /* negative large window dcdc converter , */\
- { 0x3040, "flag_voutcomp"}, /* flag_voutcomp, indication Vset is larger than Vbat, */\
- { 0x3050, "flag_voutcomp93"}, /* flag_voutcomp93, indication Vset is larger than 1.07* Vbat , */\
- { 0x3060, "flag_voutcomp86"}, /* flag_voutcomp86, indication Vset is larger than 1.14* Vbat , */\
- { 0x3070, "flag_hiz"}, /* flag_hiz, indication Vbst is larger than Vbat , */\
- { 0x3080, "flag_hi_peak"}, /* flag_hi_peak, indication hi_peak , */\
- { 0x3090, "flag_ocpokbst"}, /* flag_ocpokbst, indication no over current in boost converter pmos switch, */\
- { 0x30a0, "flag_peakcur"}, /* flag_peakcur, indication current is max in dcdc converter, */\
- { 0x30b0, "flag_ocpokap"}, /* flag_ocpokap, indication no over current in amplifier "a" pmos output stage, */\
- { 0x30c0, "flag_ocpokan"}, /* flag_ocpokan, indication no over current in amplifier "a" nmos output stage, */\
- { 0x30d0, "flag_ocpokbp"}, /* flag_ocpokbp, indication no over current in amplifier "b" pmos output stage, */\
- { 0x30e0, "flag_ocpokbn"}, /* flag_ocpokbn, indication no over current in amplifier"b" nmos output stage, */\
- { 0x30f0, "lost_clk"}, /* lost_clk, lost clock indication CGU , */\
- { 0x310f, "mtp_man_data_out"}, /* single word read from MTP (manual copy) , */\
- { 0x3200, "key01_locked"}, /* key01_locked, indication key 1 is locked , */\
- { 0x3210, "key02_locked"}, /* key02_locked, indication key 2 is locked , */\
- { 0x3225, "mtp_ecc_tcout"}, /* mtp_ecc_tcout , */\
- { 0x3280, "mtpctrl_valid_test_rd"}, /* mtp test readout for read , */\
- { 0x3290, "mtpctrl_valid_test_wr"}, /* mtp test readout for write , */\
- { 0x32a0, "flag_in_alarm_state"}, /* alarm state , */\
- { 0x32b0, "mtp_ecc_err2"}, /* two or more bit errors detected in MTP, can not reconstruct value, */\
- { 0x32c0, "mtp_ecc_err1"}, /* one bit error detected in MTP, reconstructed value, */\
- { 0x32d0, "mtp_mtp_hvf"}, /* high voltage ready flag for MTP , */\
- { 0x32f0, "mtp_zero_check_fail"}, /* zero check failed (tbd) for MTP , */\
- { 0x3300, "flag_adc10_ready"}, /* flag_adc10_ready, indication adc10 is ready , */\
- { 0x3310, "flag_clipa_high"}, /* flag_clipa_high, indication pmos amplifier "a" is clipping, */\
- { 0x3320, "flag_clipa_low"}, /* flag_clipa_low, indication nmos amplifier "a" is clipping, */\
- { 0x3330, "flag_clipb_high"}, /* flag_clipb_high, indication pmos amplifier "b" is clipping, */\
- { 0x3340, "flag_clipb_low"}, /* flag_clipb_low, indication nmos amplifier "b" is clipping, */\
- { 0x3359, "data_adc10_tempbat"}, /* adc 10 data output for testing , */\
- { 0x33f0, "flag_vddd_comp_nok"}, /* power switch flag 2 for testing , */\
- { 0x400f, "hid_code"}, /* hidden code , */\
- { 0x4100, "bypass_hp"}, /* Bypass_High Pass Filter , */\
- { 0x4110, "hard_mute"}, /* Hard Mute , */\
- { 0x4120, "soft_mute"}, /* Soft Mute , */\
- { 0x4134, "PWM_Delay"}, /* PWM DelayBits to set the delay , */\
- { 0x4180, "PWM_Shape"}, /* PWM Shape , */\
- { 0x4190, "PWM_BitLength"}, /* PWM Bitlength in noise shaper , */\
- { 0x4207, "ctrl_drive"}, /* drive bits to select amount of power stages amplifier, */\
- { 0x4281, "dpsalevel"}, /* DPSA Threshold level , */\
- { 0x42a1, "dpsa_release"}, /* DPSA Release time , */\
- { 0x42c0, "ctrl_coincidence"}, /* Prevent simultaneously switching of output stage , */\
- { 0x42d0, "ctrl_kickback"}, /* Prevent double pulses of output stage , */\
- { 0x42e0, "ctrl_test_sdeltaoffset"}, /* ctrl_test_sdeltaoffset , */\
- { 0x42f0, "ctrl_test_sdeltaclk"}, /* ctrl_test_sdeltaclk , */\
- { 0x4309, "ctrl_drivebst"}, /* Drive bits to select the powertransistor sections boost converter, */\
- { 0x43a0, "ctrl_ocptestbst"}, /* Boost OCP. , */\
- { 0x43c0, "enbl_hi_peak"}, /* enable for high peak comparator , */\
- { 0x43d0, "test_abistfft_enbl"}, /* FFT coolflux , */\
- { 0x43e0, "ctrl_sensetest_amp"}, /* sensetest amplifier , */\
- { 0x43f0, "test_bcontrol"}, /* test _bcontrol , */\
- { 0x4400, "ctrl_reversebst"}, /* OverCurrent Protection selection of power stage boost converter, */\
- { 0x4410, "ctrl_sensetest"}, /* Test option for the sense NMOS in booster for current mode control., */\
- { 0x4420, "enbl_engagebst"}, /* Enable power stage dcdc controller , */\
- { 0x4430, "enbl_hi_small"}, /* Enable bit of hi (small) comparator , */\
- { 0x4440, "enbl_hi_large"}, /* Enable bit of hi (large) comparator , */\
- { 0x4450, "enbl_lo_small"}, /* Enable bit of lo (small) comparator , */\
- { 0x4460, "enbl_lo_large"}, /* Enable bit of lo (large) comparator , */\
- { 0x4470, "enbl_slopecur"}, /* Enable bit of max-current dac , */\
- { 0x4480, "enbl_voutcomp"}, /* Enable vout comparators , */\
- { 0x4490, "enbl_voutcomp93"}, /* Enable vout-93 comparators , */\
- { 0x44a0, "enbl_voutcomp86"}, /* Enable vout-86 comparators , */\
- { 0x44b0, "enbl_hizcom"}, /* Enable hiz comparator , */\
- { 0x44c0, "enbl_pcdac"}, /* Enable peak current dac , */\
- { 0x44d0, "enbl_pccomp"}, /* Enable peak current comparator , */\
- { 0x44e0, "enbl_windac"}, /* Enable window dac , */\
- { 0x44f0, "enbl_powerbst"}, /* Enable line of the powerstage , */\
- { 0x4507, "ocp_thr"}, /* ocp_thr threshold level for OCP , */\
- { 0x4580, "bypass_glitchfilter"}, /* Bypass glitchfilter , */\
- { 0x4590, "bypass_ovp"}, /* Bypass OVP , */\
- { 0x45a0, "bypass_uvp"}, /* Bypass UVP , */\
- { 0x45b0, "bypass_otp"}, /* Bypass OTP , */\
- { 0x45c0, "bypass_ocp"}, /* Bypass OCP , */\
- { 0x45d0, "bypass_ocpcounter"}, /* BypassOCPCounter , */\
- { 0x45e0, "bypass_lost_clk"}, /* Bypasslost_clk detector , */\
- { 0x45f0, "vpalarm"}, /* vpalarm (uvp ovp handling) , */\
- { 0x4600, "bypass_gc"}, /* bypass_gc, bypasses the CS gain correction , */\
- { 0x4610, "cs_gain_control"}, /* gain control by means of MTP or i2c , */\
- { 0x4627, "cs_gain"}, /* + / - 128 steps in steps of 1/4 % 2's compliment , */\
- { 0x46a0, "bypass_lp"}, /* bypass Low-Pass filter in temperature sensor , */\
- { 0x46b0, "bypass_pwmcounter"}, /* bypass_pwmcounter , */\
- { 0x46c0, "ctrl_cs_negfixed"}, /* does not switch to neg , */\
- { 0x46d2, "ctrl_cs_neghyst"}, /* switches to neg depending on level , */\
- { 0x4700, "switch_fb"}, /* switch_fb , */\
- { 0x4713, "se_hyst"}, /* se_hyst , */\
- { 0x4754, "se_level"}, /* se_level , */\
- { 0x47a5, "ktemp"}, /* temperature compensation trimming , */\
- { 0x4800, "ctrl_negin"}, /* negin , */\
- { 0x4810, "ctrl_cs_sein"}, /* cs_sein , */\
- { 0x4820, "ctrl_coincidencecs"}, /* Coincidence current sense , */\
- { 0x4830, "ctrl_iddqtestbst"}, /* for iddq testing in powerstage of boost convertor , */\
- { 0x4840, "ctrl_coincidencebst"}, /* Switch protection on to prevent simultaniously switching power stages bst and amp, */\
- { 0x4851, "clock_sh_sel"}, /* Clock SH selection , */\
- { 0x4876, "delay_se_neg"}, /* delay of se and neg , */\
- { 0x48e1, "ctrl_cs_ttrack"}, /* sample & hold track time , */\
- { 0x4900, "ctrl_bypassclip"}, /* Bypass clip control (function depending on digimux clip_x), */\
- { 0x4910, "ctrl_bypassclip2"}, /* Bypass clip control (function depending on digimux clip_x), */\
- { 0x4920, "ctrl_clkgateCFoff"}, /* to disable clock gating in the coolflux , */\
- { 0x4930, "ctrl_testabst"}, /* testabst , */\
- { 0x4940, "ctrl_clipfast"}, /* clock switch for battery protection clipper, it switches back to old frequency, */\
- { 0x4950, "ctrl_cs_8ohm"}, /* 8 ohm mode for current sense (gain mode) , */\
- { 0x4960, "reserved"}, /* reserved , */\
- { 0x4974, "delay_clock_sh"}, /* delay_sh, tunes S7H delay , */\
- { 0x49c0, "inv_clksh"}, /* Invert the sample/hold clock for current sense ADC, */\
- { 0x49d0, "inv_neg"}, /* Invert neg signal , */\
- { 0x49e0, "inv_se"}, /* Invert se signal , */\
- { 0x49f0, "setse"}, /* switches between Single Ende and differentail mode, */\
- { 0x4a12, "ctrl_adc10_sel"}, /* select the input to convert the 10b ADC , */\
- { 0x4a60, "ctrl_adc10_reset"}, /* Global asynchronous reset (active HIGH) 10 bit ADC, */\
- { 0x4a81, "ctrl_adc10_test"}, /* Test mode selection signal 10 bit ADC , */\
- { 0x4aa0, "ctrl_bypass_lp_vbat"}, /* lp filter in batt sensor , */\
- { 0x4ae0, "ctrl_dc_offset"}, /* switch offset control on/off, is decimator offset control, */\
- { 0x4af0, "ctrl_tsense_hibias"}, /* bit to set the biasing in temp sensor to high , */\
- { 0x4b00, "ctrl_adc13_iset"}, /* Micadc Setting of current consumption. Debug use only, */\
- { 0x4b14, "ctrl_adc13_gain"}, /* Micadc gain setting (2-compl) , */\
- { 0x4b61, "ctrl_adc13_slowdel"}, /* Micadc Delay setting for internal clock. Debug use only, */\
- { 0x4b83, "ctrl_adc13_offset"}, /* Micadc ADC offset setting , */\
- { 0x4bc0, "ctrl_adc13_bsoinv"}, /* Micadc bit stream output invert mode for test , */\
- { 0x4bd0, "ctrl_adc13_resonator_enable"}, /* Micadc Give extra SNR with less stability. Debug use only, */\
- { 0x4be0, "ctrl_testmicadc"}, /* Mux at input of MICADC for test purpose , */\
- { 0x4c0f, "ctrl_offset"}, /* offset control for ABIST testing , */\
- { 0x4d05, "ctrl_windac"}, /* for testing direct control windac , */\
- { 0x4d65, "ctrl_peakcur"}, /* Control peakcur , */\
- { 0x4dc3, "pwm_dcc_cnt"}, /* control pwm duty cycle when enbl_pwm_dcc is 1 , */\
- { 0x4e04, "ctrl_slopecur"}, /* for testing direct control slopecur , */\
- { 0x4e53, "ctrl_dem"}, /* dyn element matching control, rest of codes are optional, */\
- { 0x4e93, "ctrl_demmismatch"}, /* dyn element matching add offset , */\
- { 0x4ed0, "enbl_pwm_dcc"}, /* to enable direct control of pwm duty cycle , */\
- { 0x5007, "gain"}, /* gain setting of the gain multiplier gain need to increase with factor 1.41 (3dB), */\
- { 0x5081, "ctrl_sourceb"}, /* Set OUTB to , */\
- { 0x50a1, "ctrl_sourcea"}, /* Set OUTA to , */\
- { 0x50c1, "ctrl_sourcebst"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
- { 0x50e1, "ctrl_test_mono"}, /* ABIST mode to add both amplifier halfs as stereo or one amplifier half as mono, */\
- { 0x5104, "pulselengthbst"}, /* pulselength setting test input for boost converter , */\
- { 0x5150, "ctrl_bypasslatchbst"}, /* bypass_latch in boost converter , */\
- { 0x5160, "invertbst"}, /* invert pwmbst test signal , */\
- { 0x5174, "pulselength"}, /* pulselength setting test input for amplifier , */\
- { 0x51c0, "ctrl_bypasslatch"}, /* bypass_latch in boost convert , */\
- { 0x51d0, "invertb"}, /* invert pwmb test signal , */\
- { 0x51e0, "inverta"}, /* invert pwma test signal , */\
- { 0x51f0, "ctrl_bypass_ctrlloop"}, /* bypass_ctrlloop bypasses the control loop of the amplifier, */\
- { 0x5200, "ctrl_test_discrete"}, /* tbd for rdson testing , */\
- { 0x5210, "ctrl_test_rdsona"}, /* tbd for rdson testing , */\
- { 0x5220, "ctrl_test_rdsonb"}, /* tbd for rdson testing , */\
- { 0x5230, "ctrl_test_rdsonbst"}, /* tbd for rdson testing , */\
- { 0x5240, "ctrl_test_cvia"}, /* tbd for rdson testing , */\
- { 0x5250, "ctrl_test_cvib"}, /* tbd for rdson testing , */\
- { 0x5260, "ctrl_test_cvibst"}, /* tbd for rdson testing , */\
- { 0x5290, "test_bypass_pwmdiscretea"}, /* for testing ( ABIST) , */\
- { 0x52a0, "test_bypass_pwmdiscreteb"}, /* for testing ( ABIST) , */\
- { 0x52b0, "ctrl_clipc_forcehigh"}, /* test signal for clipcontrol , */\
- { 0x52c0, "ctrl_clipc_forcelow"}, /* test signal for clipcontrol , */\
- { 0x52d0, "ctrl_test_sdelta"}, /* for testing ( ABIST) , */\
- { 0x52e0, "ctrl_test_swhvp"}, /* for testing ( ABIST) , */\
- { 0x52f0, "test_gain_reduction"}, /* test gain reduction , */\
- { 0x5303, "ctrl_digimux_out_test1"}, /* Digimux TEST1 out , */\
- { 0x5343, "ctrl_digimux_out_test2"}, /* Digimux TEST2 out. output flag_clipa_low depending on cntr_bypassclip setting, */\
- { 0x5383, "ctrl_digimux_out_data1"}, /* Digimux DATA1 out (output flag_clipb_high depending on cntr_bypassclip setting), */\
- { 0x53c3, "ctrl_digimux_out_data3"}, /* Digimux DATA3 out (output flag_clipx_x depending on cntr_bypassclip setting), */\
- { 0x5400, "hs_mode"}, /* hs_mode, high speed mode I2C bus , */\
- { 0x5412, "test_parametric_io"}, /* test_parametric_io for testing pads , */\
- { 0x5440, "enbl_ringo"}, /* enbl_ringo, for test purpose to check with ringo , */\
- { 0x5480, "ctrl_cliplevel"}, /* Clip level , */\
- { 0x5491, "ctrl_anamux_sel"}, /* anamux selection , */\
- { 0x54b0, "test_vdddsw_dio"}, /* to overrule the power switches for memory , */\
- { 0x54c0, "ctrl_bypass_diosw_ovp"}, /* To disable the overvoltage protection of vddd_dio_sw, */\
- { 0x54d0, "test_vddd_sw"}, /* test vdd sw , */\
- { 0x54e0, "test_vddd_sw_comp"}, /* test vdd sw comp , */\
- { 0x550e, "enbl_amp"}, /* enbl_amp for testing to enable all analoge blocks in amplifier, */\
- { 0x55f0, "fr_fsp"}, /* extr free running clock mode for testing , */\
- { 0x5600, "use_direct_ctrls"}, /* use_direct_ctrls, to overrule several functions direct for testing, */\
- { 0x5610, "rst_datapath"}, /* rst_datapath, datapath reset , */\
- { 0x5620, "rst_cgu"}, /* rst_cgu, cgu reset , */\
- { 0x5637, "enbl_ref"}, /* for testing to enable all analoge blocks in references, */\
- { 0x56b0, "enbl_engage"}, /* Enable output stage amplifier , */\
- { 0x56c0, "use_direct_clk_ctrl"}, /* use_direct_clk_ctrl, to overrule several functions direct for testing, */\
- { 0x56d0, "use_direct_pll_ctrl"}, /* use_direct_pll_ctrl, to overrule several functions direct for test, */\
- { 0x56e0, "use_direct_ctrls_2"}, /* use_direct_sourseamp_ctrls, to overrule several functions direct for testing, */\
- { 0x5707, "ctrl_anamux_out_test1"}, /* Anamux control , */\
- { 0x5782, "ctrl_zero"}, /* Bandwith control feedbackloop , */\
- { 0x57b0, "enbl_ldo_stress"}, /* LDO stress function frinch capacitors , */\
- { 0x57c0, "ctrl_ocptest"}, /* ctrl_ocptest, deactivates the over current protection in the power stages of the amplifier. The ocp flag signals stay active., */\
- { 0x57e0, "ctrl_otptest"}, /* otptest, test mode otp amplifier , */\
- { 0x57f0, "ctrl_reverse"}, /* CTRL revers , */\
- { 0x5802, "pll_mdec_msb"}, /* most significant bits pll_mdec , */\
- { 0x5833, "pll_selr"}, /* pll_selr , */\
- { 0x5874, "pll_selp"}, /* pll_selp , */\
- { 0x58c3, "pll_seli"}, /* pll_seli , */\
- { 0x5900, "pll_psel"}, /* pll_psel , */\
- { 0x5910, "use_direct_pll_psel"}, /* use_direct_pll_psel , */\
- { 0x5923, "nbck"}, /* NBCK , */\
- { 0x5960, "auto_nbck"}, /* AUTO_NBCK , */\
- { 0x5970, "pll_frm"}, /* pll_frm , */\
- { 0x5980, "pll_directi"}, /* pll_directi , */\
- { 0x5990, "pll_directo"}, /* pll_directo , */\
- { 0x59a0, "enbl_PLL"}, /* enbl_PLL , */\
- { 0x59b0, "sel_clkout"}, /* SEL_CLKOUT , */\
- { 0x59e0, "fr_lost_clk"}, /* fr_lost_clk , */\
- { 0x59f0, "pll_bypass"}, /* pll_bypass , */\
- { 0x5a0f, "tsig_freq"}, /* tsig_freq, internal sinus test generator, frequency control, */\
- { 0x5b02, "tsig_freq_msb"}, /* select internal sinus test generator, frequency control msb bits, */\
- { 0x5b30, "inject_tsig"}, /* inject_tsig, control bit to switch to internal sinus test generator, */\
- { 0x5b44, "ctrl_adc10_prog_sample"}, /* control ADC10 , */\
- { 0x5c01, "pll_ndec_msb"}, /* most significant bits of pll_ndec , */\
- { 0x5c2d, "pll_mdec"}, /* bits 13..0 of pll_mdec , */\
- { 0x5d06, "pll_pdec"}, /* pll_pdec , */\
- { 0x5d87, "pll_ndec"}, /* bits 7..0 of pll_ndec , */\
- { 0x5e00, "pdm_ch_sel_reg"}, /* PDM channel selection , */\
- { 0x5e10, "pdm_iis_rst_reg"}, /* PDM Interface reset , */\
- { 0x5e20, "clk_src_sel_reg"}, /* WS Source Selection , */\
- { 0x5e70, "pdm_resync_bypass"}, /* PDM resynchronization bypass , */\
- { 0x6007, "MTP_key1"}, /* MTP Key1 , */\
- { 0x6185, "mtp_ecc_tcin"}, /* Mtp_ecc_tcin , */\
- { 0x6203, "mtp_man_address_in"}, /* address from i2cregs for writing one word single mtp, */\
- { 0x6260, "mtp_ecc_eeb"}, /* enable code bit generation (active low!) , */\
- { 0x6270, "mtp_ecc_ecb"}, /* enable correction signal (active low!) , */\
- { 0x6280, "man_copy_mtp_to_iic"}, /* start copying single word from mtp to i2cregs_mtp , */\
- { 0x6290, "man_copy_iic_to_mtp"}, /* start copying single word from i2cregs_mtp to mtp [Key 1 protected], */\
- { 0x62a0, "auto_copy_mtp_to_iic"}, /* start copying all the data from mtp to i2cregs_mtp, */\
- { 0x62b0, "auto_copy_iic_to_mtp"}, /* start copying all the data from i2cregs_mtp to mtp [Key 2 protected], */\
- { 0x62d2, "mtp_speed_mode"}, /* Speed mode , */\
- { 0x6340, "mtp_dircet_enable"}, /* mtp_direct_enable (key1 protected) , */\
- { 0x6350, "mtp_direct_wr"}, /* mtp_direct_wr (key1 protected) direct value for mtp pin wr. To be enabled via iic2mtp_mtp_direct_enable, */\
- { 0x6360, "mtp_direct_rd"}, /* mtp_direct_rd (key1 protected) direct value for mtp pin rd. To be enabled via iic2mtp_mtp_direct_enable, */\
- { 0x6370, "mtp_direct_rst"}, /* mtp_direct_rst (key1 protected) direct value for mtp pin rst. To be enabled via iic2mtp_mtp_direct_enable, */\
- { 0x6380, "mtp_direct_ers"}, /* mtp_direct_ers (key1 protected) direct value for mtp pin ers. To be enabled via iic2mtp_mtp_direct_enable, */\
- { 0x6390, "mtp_direct_prg"}, /* mtp_direct_prg (key1 protected) direct value for mtp pin prg. To be enabled via iic2mtp_mtp_direct_enable, */\
- { 0x63a0, "mtp_direct_epp"}, /* mtp_direct_epp (key1 protected) direct value for mtp pin epp. To be enabled via iic2mtp_mtp_direct_enable, */\
- { 0x63b4, "mtp_direct_test"}, /* mtp_direct_test (key1 protected) , */\
- { 0x640f, "mtp_man_data_in"}, /* single wordt be written to MTP (manual copy) , */\
- { 0x7000, "cf_rst_dsp"}, /* Reset CoolFlux DSP , */\
- { 0x7011, "cf_dmem"}, /* Target memory for access , */\
- { 0x7030, "cf_aif"}, /* Autoincrement-flag for memory-address , */\
- { 0x7040, "cf_int"}, /* Interrupt CoolFlux DSP , */\
- { 0x7087, "cf_req"}, /* request for access (8 channels) , */\
- { 0x710f, "cf_madd"}, /* memory-address to be accessed , */\
- { 0x720f, "cf_mema"}, /* activate memory access (24- or 32-bits data is written/read to/from memory, */\
- { 0x7307, "cf_err"}, /* cf error Flags , */\
- { 0x7387, "cf_ack"}, /* acknowledge of requests (8 channels")" , */\
- { 0x8000, "calibration_onetime"}, /* Calibration schedule (key2 protected) , */\
- { 0x8010, "calibr_ron_done"}, /* (key2 protected) calibration of Ron has been executed, */\
- { 0x8105, "calibr_vout_offset"}, /* calibr_vout_offset (DCDCoffset) 2's compliment (key1 protected), */\
- { 0x8163, "calibr_delta_gain"}, /* delta gain for vamp (alpha) 2's compliment (key1 protected), */\
- { 0x81a5, "calibr_offs_amp"}, /* offset for vamp (Ampoffset) 2's compliment (key1 protected), */\
- { 0x8207, "calibr_gain_cs"}, /* gain current sense (Imeasalpha) 2's compliment (key1 protected), */\
- { 0x8284, "calibr_temp_offset"}, /* temperature offset 2's compliment (key1 protected), */\
- { 0x82d2, "calibr_temp_gain"}, /* temperature gain 2's compliment (key1 protected) , */\
- { 0x830f, "calibr_ron"}, /* Ron resistance of coil (key1 protected) , */\
- { 0x8406, "ctrl_offset_a"}, /* Offset of amplifier level shifter , */\
- { 0x8486, "ctrl_offset_b"}, /* Offset of amplifier level shifter , */\
- { 0x850f, "type_bits_HW"}, /* HW Bits , */\
- { 0x860f, "type_bits1_SW"}, /* MTP-control SW1 , */\
- { 0x870f, "type_bits2_SW"}, /* MTP-control SW2 , */\
- { 0x8a0f, "production_data1"}, /* (key1 protected) , */\
- { 0x8b0f, "production_data2"}, /* (key1 protected) , */\
- { 0x8c0f, "production_data3"}, /* (key1 protected) , */\
- { 0x8d0f, "production_data4"}, /* (key1 protected) , */\
- { 0x8e0f, "production_data5"}, /* (key1 protected) , */\
- { 0x8f0f, "production_data6"}, /* (key1 protected) , */\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-
-
-#endif /* TFA_INC_TFA9891_TFAFIELDNAMES_H_ */
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef TFA_INC_TFA9891_TFAFIELDNAMES_H_
+#define TFA_INC_TFA9891_TFAFIELDNAMES_H_
+
+#define TFA9891_I2CVERSION 13
+
+
+#define TFA9891_NAMETABLE static tfaBfName_t Tfa9891DatasheetNames[] = {\
+ { 0x0, "VDDS"}, /* POR , */\
+ { 0x10, "PLLS"}, /* PLL , */\
+ { 0x20, "OTDS"}, /* OTP , */\
+ { 0x30, "OVDS"}, /* OVP , */\
+ { 0x40, "UVDS"}, /* UVP , */\
+ { 0x50, "OCDS"}, /* OCP , */\
+ { 0x60, "CLKS"}, /* Clocks , */\
+ { 0x70, "CLIPS"}, /* CLIP , */\
+ { 0x80, "MTPB"}, /* MTP , */\
+ { 0x90, "DCCS"}, /* BOOST , */\
+ { 0xa0, "SPKS"}, /* Speaker , */\
+ { 0xb0, "ACS"}, /* cold start flag , */\
+ { 0xc0, "SWS"}, /* flag engage , */\
+ { 0xd0, "WDS"}, /* flag watchdog reset , */\
+ { 0xe0, "AMPS"}, /* amplifier is enabled by manager , */\
+ { 0xf0, "AREFS"}, /* references are enabled by manager , */\
+ { 0x109, "BATS"}, /* Battery voltage readout; 0[V]..5.5[V] , */\
+ { 0x208, "TEMPS"}, /* Temperature readout , */\
+ { 0x307, "REV"}, /* Device Revision , */\
+ { 0x402, "I2SF"}, /* I2SFormat data 1 input , */\
+ { 0x431, "CHS12"}, /* ChannelSelection data1 input (In CoolFlux) , */\
+ { 0x450, "CHS3"}, /* Channel Selection data 2 input (coolflux input, the DCDC converter gets the other signal), */\
+ { 0x461, "CHSA"}, /* Input selection for amplifier , */\
+ { 0x481, "I2SDOC"}, /* Selection for I2S data out , */\
+ { 0x4a0, "DISP"}, /* idp protection , */\
+ { 0x4b0, "I2SDOE"}, /* Enable data output , */\
+ { 0x4c3, "I2SSR"}, /* sample rate setting , */\
+ { 0x501, "BSSCR"}, /* ProtectionAttackTime , */\
+ { 0x523, "BSST"}, /* ProtectionThreshold , */\
+ { 0x561, "BSSRL"}, /* ProtectionMaximumReduction , */\
+ { 0x582, "BSSRR"}, /* Protection Release Timer , */\
+ { 0x5b1, "BSSHY"}, /* ProtectionHysterese , */\
+ { 0x5e0, "BSSR"}, /* battery voltage for I2C read out only , */\
+ { 0x5f0, "BSSBY"}, /* bypass clipper battery protection , */\
+ { 0x600, "DPSA"}, /* Enable dynamic powerstage activation , */\
+ { 0x613, "AMPSL"}, /* control slope , */\
+ { 0x650, "CFSM"}, /* Soft mute in CoolFlux , */\
+ { 0x670, "BSSS"}, /* batsensesteepness , */\
+ { 0x687, "VOL"}, /* volume control (in CoolFlux) , */\
+ { 0x702, "DCVO"}, /* Boost voltage , */\
+ { 0x732, "DCMCC"}, /* Max boost coil current , */\
+ { 0x7a0, "DCIE"}, /* Adaptive boost mode , */\
+ { 0x7b0, "DCSR"}, /* Soft RampUp/Down mode for DCDC controller , */\
+ { 0x800, "TROS"}, /* select external temperature also the ext_temp will be put on the temp read out , */\
+ { 0x818, "EXTTS"}, /* external temperature setting to be given by host , */\
+ { 0x900, "PWDN"}, /* ON/OFF , */\
+ { 0x910, "I2CR"}, /* I2CReset , */\
+ { 0x920, "CFE"}, /* EnableCoolFlux , */\
+ { 0x930, "AMPE"}, /* EnableAmplifier , */\
+ { 0x940, "DCA"}, /* EnableBoost , */\
+ { 0x950, "SBSL"}, /* Coolflux configured , */\
+ { 0x960, "AMPC"}, /* Selection on how AmplifierEnabling , */\
+ { 0x970, "DCDIS"}, /* DCDC not connected , */\
+ { 0x980, "PSDR"}, /* Iddq test amplifier , */\
+ { 0x991, "DCCV"}, /* Coil Value , */\
+ { 0x9b1, "CCFD"}, /* Selection CoolFluxClock , */\
+ { 0x9d0, "ISEL"}, /* Interface Selection , */\
+ { 0x9e0, "IPLL"}, /* selection input PLL for lock , */\
+ { 0xa02, "DOLS"}, /* Output selection dataout left channel , */\
+ { 0xa32, "DORS"}, /* Output selection dataout right channel , */\
+ { 0xa62, "SPKL"}, /* Selection speaker induction , */\
+ { 0xa91, "SPKR"}, /* Selection speaker impedance , */\
+ { 0xab3, "DCFG"}, /* DCDC speaker current compensation gain , */\
+ { 0xb07, "MTPK"}, /* MTP KEY2 register , */\
+ { 0xf00, "VDDD"}, /* mask flag_por for interupt generation , */\
+ { 0xf10, "OTDD"}, /* mask flag_otpok for interupt generation , */\
+ { 0xf20, "OVDD"}, /* mask flag_ovpok for interupt generation , */\
+ { 0xf30, "UVDD"}, /* mask flag_uvpok for interupt generation , */\
+ { 0xf40, "OCDD"}, /* mask flag_ocp_alarm for interupt generation , */\
+ { 0xf50, "CLKD"}, /* mask flag_clocks_stable for interupt generation , */\
+ { 0xf60, "DCCD"}, /* mask flag_pwrokbst for interupt generation , */\
+ { 0xf70, "SPKD"}, /* mask flag_cf_speakererror for interupt generation , */\
+ { 0xf80, "WDD"}, /* mask flag_watchdog_reset for interupt generation , */\
+ { 0xfe0, "INT"}, /* enabling interrupt , */\
+ { 0xff0, "INTP"}, /* Setting polarity interupt , */\
+ { 0x1000, "PDMSEL"}, /* Audio input interface mode , */\
+ { 0x1010, "I2SMOUTEN"}, /* I2S Master enable (CLK and WS pads) , */\
+ { 0x1021, "PDMORSEL"}, /* PDM Output right channel source selection , */\
+ { 0x1041, "PDMOLSEL"}, /* PDM Output Left/Mono channel source selection , */\
+ { 0x1061, "PADSEL"}, /* Output interface mode and ball selection , */\
+ { 0x1100, "PDMOSDEN"}, /* Secure delay Cell , */\
+ { 0x1110, "PDMOSDCF"}, /* Rising Falling Resync control Mux , */\
+ { 0x1140, "SAAMEN"}, /* Speaker As a Mic feature ON/OFF , */\
+ { 0x1150, "SAAMLPEN"}, /* speaker_as_mic low power mode (only in PDM_out mode), */\
+ { 0x1160, "PDMOINTEN"}, /* PDM output interpolation ratio , */\
+ { 0x1203, "PDMORG1"}, /* PDM Interpolator Right Channel DS4 G1 Gain Value , */\
+ { 0x1243, "PDMORG2"}, /* PDM Interpolator Right Channel DS4 G2 Gain Value , */\
+ { 0x1303, "PDMOLG1"}, /* PDM Interpolator Left Channel DS4 G1 Gain Value , */\
+ { 0x1343, "PDMOLG2"}, /* PDM Interpolator Left Channel DS4 G2 Gain Value , */\
+ { 0x2202, "SAAMGAIN"}, /* pga gain , */\
+ { 0x2250, "SAAMPGACTRL"}, /* 0 = active input common mode voltage source at the attenuator/PGA level, */\
+ { 0x2500, "PLLCCOSEL"}, /* pll cco frequency , */\
+ { 0x4600, "CSBYPGC"}, /* bypass_gc, bypasses the CS gain correction , */\
+ { 0x4900, "CLIP"}, /* Bypass clip control (function depending on digimux clip_x), */\
+ { 0x4910, "CLIP2"}, /* Bypass clip control (function depending on digimux clip_x), */\
+ { 0x62b0, "CIMTP"}, /* start copying all the data from i2cregs_mtp to mtp [Key 2 protected], */\
+ { 0x7000, "RST"}, /* Reset CoolFlux DSP , */\
+ { 0x7011, "DMEM"}, /* Target memory for access , */\
+ { 0x7030, "AIF"}, /* Autoincrement-flag for memory-address , */\
+ { 0x7040, "CFINT"}, /* Interrupt CoolFlux DSP , */\
+ { 0x7087, "REQ"}, /* request for access (8 channels) , */\
+ { 0x710f, "MADD"}, /* memory-address to be accessed , */\
+ { 0x720f, "MEMA"}, /* activate memory access (24- or 32-bits data is written/read to/from memory, */\
+ { 0x7307, "ERR"}, /* cf error Flags , */\
+ { 0x7387, "ACK"}, /* acknowledge of requests (8 channels")" , */\
+ { 0x8000, "MTPOTC"}, /* Calibration schedule (key2 protected) , */\
+ { 0x8010, "MTPEX"}, /* (key2 protected) calibration of Ron has been executed, */\
+ { 0x8045, "SWPROFIL" },\
+ { 0x80a5, "SWVSTEP" },\
+ { 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+
+#define TFA9891_BITNAMETABLE static tfaBfName_t Tfa9891BitNames[] = {\
+ { 0x0, "POR"}, /* POR , */\
+ { 0x10, "PLL_LOCK"}, /* PLL , */\
+ { 0x20, "flag_otpok"}, /* OTP , */\
+ { 0x30, "flag_ovpok"}, /* OVP , */\
+ { 0x40, "flag_uvpok"}, /* UVP , */\
+ { 0x50, "flag_OCP_alarm"}, /* OCP , */\
+ { 0x60, "flag_clocks_stable"}, /* Clocks , */\
+ { 0x70, "CLIP"}, /* CLIP , */\
+ { 0x80, "mtp_busy"}, /* MTP , */\
+ { 0x90, "flag_pwrokbst"}, /* BOOST , */\
+ { 0xa0, "flag_cf_speakererror"}, /* Speaker , */\
+ { 0xb0, "flag_cold_started"}, /* cold start flag , */\
+ { 0xc0, "flag_engage"}, /* flag engage , */\
+ { 0xd0, "flag_watchdog_reset"}, /* flag watchdog reset , */\
+ { 0xe0, "flag_enbl_amp"}, /* amplifier is enabled by manager , */\
+ { 0xf0, "flag_enbl_ref"}, /* references are enabled by manager , */\
+ { 0x109, "bat_adc"}, /* Battery voltage readout; 0[V]..5.5[V] , */\
+ { 0x208, "temp_adc"}, /* Temperature readout , */\
+ { 0x307, "rev_reg"}, /* Device Revision , */\
+ { 0x402, "i2s_seti"}, /* I2SFormat data 1 input , */\
+ { 0x431, "chan_sel1"}, /* ChannelSelection data1 input (In CoolFlux) , */\
+ { 0x450, "lr_sw_i2si2"}, /* Channel Selection data 2 input (coolflux input, the DCDC converter gets the other signal), */\
+ { 0x461, "input_sel"}, /* Input selection for amplifier , */\
+ { 0x481, "datao_sel"}, /* Selection for I2S data out , */\
+ { 0x4a0, "disable_idp"}, /* idp protection , */\
+ { 0x4b0, "enbl_datao"}, /* Enable data output , */\
+ { 0x4c3, "i2s_fs"}, /* sample rate setting , */\
+ { 0x501, "vbat_prot_attacktime"}, /* ProtectionAttackTime , */\
+ { 0x523, "vbat_prot_thlevel"}, /* ProtectionThreshold , */\
+ { 0x561, "vbat_prot_max_reduct"}, /* ProtectionMaximumReduction , */\
+ { 0x582, "vbat_prot_release_t"}, /* Protection Release Timer , */\
+ { 0x5b1, "vbat_prot_hysterese"}, /* ProtectionHysterese , */\
+ { 0x5d0, "reset_min_vbat"}, /* reset clipper , */\
+ { 0x5e0, "sel_vbat"}, /* battery voltage for I2C read out only , */\
+ { 0x5f0, "bypass_clipper"}, /* bypass clipper battery protection , */\
+ { 0x600, "dpsa"}, /* Enable dynamic powerstage activation , */\
+ { 0x613, "ctrl_slope"}, /* control slope , */\
+ { 0x650, "cf_mute"}, /* Soft mute in CoolFlux , */\
+ { 0x660, "sel_other_vamp"}, /* Input selection for the second channel of the DCDC inteligent mode detector, */\
+ { 0x670, "ctrl_batsensesteepness"}, /* batsensesteepness , */\
+ { 0x687, "vol"}, /* volume control (in CoolFlux) , */\
+ { 0x702, "ctrl_bstvolt"}, /* Boost voltage , */\
+ { 0x732, "ctrl_bstcur"}, /* Max boost coil current , */\
+ { 0x761, "ctrl_slopebst_1_0"}, /* Setting for the slope of the boost converter power stage, */\
+ { 0x781, "ctrl_slopebst_3_2"}, /* Setting for the part of the power transistor voltage to be used in peak current mode control, */\
+ { 0x7a0, "boost_intel"}, /* Adaptive boost mode , */\
+ { 0x7b0, "boost_speed"}, /* Soft RampUp/Down mode for DCDC controller , */\
+ { 0x7c1, "ctrl_delay_comp_dcdc"}, /* delay compensation in current patg compared to delay in the audio path (relative) , */\
+ { 0x7e0, "boost_input"}, /* Selection intelligent boost detector input , */\
+ { 0x7f0, "ctrl_supplysense"}, /* ADC10 input selection , */\
+ { 0x800, "ext_temp_sel"}, /* select external temperature also the ext_temp will be put on the temp read out , */\
+ { 0x818, "ext_temp"}, /* external temperature setting to be given by host , */\
+ { 0x8a0, "ctrl_spk_coilpvp_bst"}, /* Peak voltage protection boost converter , */\
+ { 0x8b2, "ctrl_dcdc_synchronisation"}, /* DCDC synchronisation off + 7 positions , */\
+ { 0x8e0, "ctrl_cs_samplevalid"}, /* sample valid moment for CS in single sample moment mode, */\
+ { 0x900, "PowerDown"}, /* ON/OFF , */\
+ { 0x910, "reset"}, /* I2CReset , */\
+ { 0x920, "enbl_coolflux"}, /* EnableCoolFlux , */\
+ { 0x930, "enbl_amplifier"}, /* EnableAmplifier , */\
+ { 0x940, "enbl_boost"}, /* EnableBoost , */\
+ { 0x950, "cf_configured"}, /* Coolflux configured , */\
+ { 0x960, "sel_enbl_amplifier"}, /* Selection on how AmplifierEnabling , */\
+ { 0x970, "dcdcoff_mode"}, /* DCDC not connected , */\
+ { 0x980, "cttr_iddqtest"}, /* Iddq test amplifier , */\
+ { 0x991, "ctrl_coil_value"}, /* Coil Value , */\
+ { 0x9b1, "ctrl_sel_cf_clock"}, /* Selection CoolFluxClock , */\
+ { 0x9d0, "intf_sel"}, /* Interface Selection , */\
+ { 0x9e0, "sel_ws_bck"}, /* selection input PLL for lock , */\
+ { 0xa02, "sel_i2so_l"}, /* Output selection dataout left channel , */\
+ { 0xa32, "sel_i2so_r"}, /* Output selection dataout right channel , */\
+ { 0xa62, "ctrl_spkr_coil"}, /* Selection speaker induction , */\
+ { 0xa91, "ctrl_spr_res"}, /* Selection speaker impedance , */\
+ { 0xab3, "ctrl_dcdc_spkr_i_comp_gain"}, /* DCDC speaker current compensation gain , */\
+ { 0xaf0, "ctrl_dcdc_spkr_i_comp_sign"}, /* DCDC speaker current compensation sign , */\
+ { 0xb07, "MTP_key2"}, /* MTP KEY2 register , */\
+ { 0xc0c, "clk_sync_delay"}, /* Delay count for clock synchronisation , */\
+ { 0xcf0, "enbl_clk_sync"}, /* Enable CGU clock synchronisation , */\
+ { 0xd0c, "adc_sync_delay"}, /* Delay count for ADC synchronisation , */\
+ { 0xdf0, "enable_adc_sync"}, /* Enable ADC synchronisation , */\
+ { 0xe00, "bypass_dcdc_curr_prot"}, /* to switch off dcdc reduction with bat prot , */\
+ { 0xe24, "ctrl_digtoana6_2"}, /* for extra connections digital to analog , */\
+ { 0xe70, "switch_on_icomp"}, /* icomp dem switch , */\
+ { 0xe87, "reserve_reg_1_7_0"}, /* reserved , */\
+ { 0xf00, "flag_por_mask"}, /* mask flag_por for interupt generation , */\
+ { 0xf10, "flag_otpok_mask"}, /* mask flag_otpok for interupt generation , */\
+ { 0xf20, "flag_ovpok_mask"}, /* mask flag_ovpok for interupt generation , */\
+ { 0xf30, "flag_uvpok_mask"}, /* mask flag_uvpok for interupt generation , */\
+ { 0xf40, "flag_ocp_alarm_mask"}, /* mask flag_ocp_alarm for interupt generation , */\
+ { 0xf50, "flag_clocks_stable_mask"}, /* mask flag_clocks_stable for interupt generation , */\
+ { 0xf60, "flag_pwrokbst_mask"}, /* mask flag_pwrokbst for interupt generation , */\
+ { 0xf70, "flag_cf_speakererror_mask"}, /* mask flag_cf_speakererror for interupt generation , */\
+ { 0xf80, "flag_watchdog_reset_mask"}, /* mask flag_watchdog_reset for interupt generation , */\
+ { 0xf90, "flag_lost_clk_mask"}, /* mask flag_lost_clk for interupt generation , */\
+ { 0xfe0, "enable_interrupt"}, /* enabling interrupt , */\
+ { 0xff0, "invert_int_polarity"}, /* Setting polarity interupt , */\
+ { 0x1000, "pdm_i2s_input"}, /* Audio input interface mode , */\
+ { 0x1010, "I2S_master_ena"}, /* I2S Master enable (CLK and WS pads) , */\
+ { 0x1021, "pdm_out_sel_r"}, /* PDM Output right channel source selection , */\
+ { 0x1041, "pdm_out_sel_l"}, /* PDM Output Left/Mono channel source selection , */\
+ { 0x1061, "micdat_out_sel"}, /* Output interface mode and ball selection , */\
+ { 0x1100, "secure_dly"}, /* Secure delay Cell , */\
+ { 0x1110, "d_out_valid_rf_mux"}, /* Rising Falling Resync control Mux , */\
+ { 0x1140, "Speak_As_Mic_en"}, /* Speaker As a Mic feature ON/OFF , */\
+ { 0x1150, "speak_as_mic_lp_mode"}, /* speaker_as_mic low power mode (only in PDM_out mode), */\
+ { 0x1160, "pdm_out_rate"}, /* PDM output interpolation ratio , */\
+ { 0x1203, "ds4_g1_r"}, /* PDM Interpolator Right Channel DS4 G1 Gain Value , */\
+ { 0x1243, "ds4_g2_r"}, /* PDM Interpolator Right Channel DS4 G2 Gain Value , */\
+ { 0x1303, "ds4_g1_l"}, /* PDM Interpolator Left Channel DS4 G1 Gain Value , */\
+ { 0x1343, "ds4_g2_l"}, /* PDM Interpolator Left Channel DS4 G2 Gain Value , */\
+ { 0x1400, "clk_secure_dly"}, /* Secure delay Cell on clock path , */\
+ { 0x1410, "data_secure_dly"}, /* Secure delay Cell enable on PDM data path , */\
+ { 0x2202, "Ctrl_saam_pga_gain"}, /* pga gain , */\
+ { 0x2250, "ctrl_saam_pga_src"}, /* 0 = active input common mode voltage source at the attenuator/PGA level, */\
+ { 0x2300, "flag_saam_spare"}, /* spare flag , */\
+ { 0x2400, "ctrl_saam_pga_tm"}, /* enables PGA test mode , */\
+ { 0x2500, "pll_fcco"}, /* pll cco frequency , */\
+ { 0x3000, "flag_hi_small"}, /* positive small window dcdc converter , */\
+ { 0x3010, "flag_hi_large"}, /* positive large window dcdc converter , */\
+ { 0x3020, "flag_lo_small"}, /* negative small window dcdc converter , */\
+ { 0x3030, "flag_lo_large"}, /* negative large window dcdc converter , */\
+ { 0x3040, "flag_voutcomp"}, /* flag_voutcomp, indication Vset is larger than Vbat, */\
+ { 0x3050, "flag_voutcomp93"}, /* flag_voutcomp93, indication Vset is larger than 1.07* Vbat , */\
+ { 0x3060, "flag_voutcomp86"}, /* flag_voutcomp86, indication Vset is larger than 1.14* Vbat , */\
+ { 0x3070, "flag_hiz"}, /* flag_hiz, indication Vbst is larger than Vbat , */\
+ { 0x3080, "flag_hi_peak"}, /* flag_hi_peak, indication hi_peak , */\
+ { 0x3090, "flag_ocpokbst"}, /* flag_ocpokbst, indication no over current in boost converter pmos switch, */\
+ { 0x30a0, "flag_peakcur"}, /* flag_peakcur, indication current is max in dcdc converter, */\
+ { 0x30b0, "flag_ocpokap"}, /* flag_ocpokap, indication no over current in amplifier "a" pmos output stage, */\
+ { 0x30c0, "flag_ocpokan"}, /* flag_ocpokan, indication no over current in amplifier "a" nmos output stage, */\
+ { 0x30d0, "flag_ocpokbp"}, /* flag_ocpokbp, indication no over current in amplifier "b" pmos output stage, */\
+ { 0x30e0, "flag_ocpokbn"}, /* flag_ocpokbn, indication no over current in amplifier"b" nmos output stage, */\
+ { 0x30f0, "lost_clk"}, /* lost_clk, lost clock indication CGU , */\
+ { 0x310f, "mtp_man_data_out"}, /* single word read from MTP (manual copy) , */\
+ { 0x3200, "key01_locked"}, /* key01_locked, indication key 1 is locked , */\
+ { 0x3210, "key02_locked"}, /* key02_locked, indication key 2 is locked , */\
+ { 0x3225, "mtp_ecc_tcout"}, /* mtp_ecc_tcout , */\
+ { 0x3280, "mtpctrl_valid_test_rd"}, /* mtp test readout for read , */\
+ { 0x3290, "mtpctrl_valid_test_wr"}, /* mtp test readout for write , */\
+ { 0x32a0, "flag_in_alarm_state"}, /* alarm state , */\
+ { 0x32b0, "mtp_ecc_err2"}, /* two or more bit errors detected in MTP, can not reconstruct value, */\
+ { 0x32c0, "mtp_ecc_err1"}, /* one bit error detected in MTP, reconstructed value, */\
+ { 0x32d0, "mtp_mtp_hvf"}, /* high voltage ready flag for MTP , */\
+ { 0x32f0, "mtp_zero_check_fail"}, /* zero check failed (tbd) for MTP , */\
+ { 0x3300, "flag_adc10_ready"}, /* flag_adc10_ready, indication adc10 is ready , */\
+ { 0x3310, "flag_clipa_high"}, /* flag_clipa_high, indication pmos amplifier "a" is clipping, */\
+ { 0x3320, "flag_clipa_low"}, /* flag_clipa_low, indication nmos amplifier "a" is clipping, */\
+ { 0x3330, "flag_clipb_high"}, /* flag_clipb_high, indication pmos amplifier "b" is clipping, */\
+ { 0x3340, "flag_clipb_low"}, /* flag_clipb_low, indication nmos amplifier "b" is clipping, */\
+ { 0x3359, "data_adc10_tempbat"}, /* adc 10 data output for testing , */\
+ { 0x33f0, "flag_vddd_comp_nok"}, /* power switch flag 2 for testing , */\
+ { 0x400f, "hid_code"}, /* hidden code , */\
+ { 0x4100, "bypass_hp"}, /* Bypass_High Pass Filter , */\
+ { 0x4110, "hard_mute"}, /* Hard Mute , */\
+ { 0x4120, "soft_mute"}, /* Soft Mute , */\
+ { 0x4134, "PWM_Delay"}, /* PWM DelayBits to set the delay , */\
+ { 0x4180, "PWM_Shape"}, /* PWM Shape , */\
+ { 0x4190, "PWM_BitLength"}, /* PWM Bitlength in noise shaper , */\
+ { 0x4207, "ctrl_drive"}, /* drive bits to select amount of power stages amplifier, */\
+ { 0x4281, "dpsalevel"}, /* DPSA Threshold level , */\
+ { 0x42a1, "dpsa_release"}, /* DPSA Release time , */\
+ { 0x42c0, "ctrl_coincidence"}, /* Prevent simultaneously switching of output stage , */\
+ { 0x42d0, "ctrl_kickback"}, /* Prevent double pulses of output stage , */\
+ { 0x42e0, "ctrl_test_sdeltaoffset"}, /* ctrl_test_sdeltaoffset , */\
+ { 0x42f0, "ctrl_test_sdeltaclk"}, /* ctrl_test_sdeltaclk , */\
+ { 0x4309, "ctrl_drivebst"}, /* Drive bits to select the powertransistor sections boost converter, */\
+ { 0x43a0, "ctrl_ocptestbst"}, /* Boost OCP. , */\
+ { 0x43c0, "enbl_hi_peak"}, /* enable for high peak comparator , */\
+ { 0x43d0, "test_abistfft_enbl"}, /* FFT coolflux , */\
+ { 0x43e0, "ctrl_sensetest_amp"}, /* sensetest amplifier , */\
+ { 0x43f0, "test_bcontrol"}, /* test _bcontrol , */\
+ { 0x4400, "ctrl_reversebst"}, /* OverCurrent Protection selection of power stage boost converter, */\
+ { 0x4410, "ctrl_sensetest"}, /* Test option for the sense NMOS in booster for current mode control., */\
+ { 0x4420, "enbl_engagebst"}, /* Enable power stage dcdc controller , */\
+ { 0x4430, "enbl_hi_small"}, /* Enable bit of hi (small) comparator , */\
+ { 0x4440, "enbl_hi_large"}, /* Enable bit of hi (large) comparator , */\
+ { 0x4450, "enbl_lo_small"}, /* Enable bit of lo (small) comparator , */\
+ { 0x4460, "enbl_lo_large"}, /* Enable bit of lo (large) comparator , */\
+ { 0x4470, "enbl_slopecur"}, /* Enable bit of max-current dac , */\
+ { 0x4480, "enbl_voutcomp"}, /* Enable vout comparators , */\
+ { 0x4490, "enbl_voutcomp93"}, /* Enable vout-93 comparators , */\
+ { 0x44a0, "enbl_voutcomp86"}, /* Enable vout-86 comparators , */\
+ { 0x44b0, "enbl_hizcom"}, /* Enable hiz comparator , */\
+ { 0x44c0, "enbl_pcdac"}, /* Enable peak current dac , */\
+ { 0x44d0, "enbl_pccomp"}, /* Enable peak current comparator , */\
+ { 0x44e0, "enbl_windac"}, /* Enable window dac , */\
+ { 0x44f0, "enbl_powerbst"}, /* Enable line of the powerstage , */\
+ { 0x4507, "ocp_thr"}, /* ocp_thr threshold level for OCP , */\
+ { 0x4580, "bypass_glitchfilter"}, /* Bypass glitchfilter , */\
+ { 0x4590, "bypass_ovp"}, /* Bypass OVP , */\
+ { 0x45a0, "bypass_uvp"}, /* Bypass UVP , */\
+ { 0x45b0, "bypass_otp"}, /* Bypass OTP , */\
+ { 0x45c0, "bypass_ocp"}, /* Bypass OCP , */\
+ { 0x45d0, "bypass_ocpcounter"}, /* BypassOCPCounter , */\
+ { 0x45e0, "bypass_lost_clk"}, /* Bypasslost_clk detector , */\
+ { 0x45f0, "vpalarm"}, /* vpalarm (uvp ovp handling) , */\
+ { 0x4600, "bypass_gc"}, /* bypass_gc, bypasses the CS gain correction , */\
+ { 0x4610, "cs_gain_control"}, /* gain control by means of MTP or i2c , */\
+ { 0x4627, "cs_gain"}, /* + / - 128 steps in steps of 1/4 % 2's compliment , */\
+ { 0x46a0, "bypass_lp"}, /* bypass Low-Pass filter in temperature sensor , */\
+ { 0x46b0, "bypass_pwmcounter"}, /* bypass_pwmcounter , */\
+ { 0x46c0, "ctrl_cs_negfixed"}, /* does not switch to neg , */\
+ { 0x46d2, "ctrl_cs_neghyst"}, /* switches to neg depending on level , */\
+ { 0x4700, "switch_fb"}, /* switch_fb , */\
+ { 0x4713, "se_hyst"}, /* se_hyst , */\
+ { 0x4754, "se_level"}, /* se_level , */\
+ { 0x47a5, "ktemp"}, /* temperature compensation trimming , */\
+ { 0x4800, "ctrl_negin"}, /* negin , */\
+ { 0x4810, "ctrl_cs_sein"}, /* cs_sein , */\
+ { 0x4820, "ctrl_coincidencecs"}, /* Coincidence current sense , */\
+ { 0x4830, "ctrl_iddqtestbst"}, /* for iddq testing in powerstage of boost convertor , */\
+ { 0x4840, "ctrl_coincidencebst"}, /* Switch protection on to prevent simultaniously switching power stages bst and amp, */\
+ { 0x4851, "clock_sh_sel"}, /* Clock SH selection , */\
+ { 0x4876, "delay_se_neg"}, /* delay of se and neg , */\
+ { 0x48e1, "ctrl_cs_ttrack"}, /* sample & hold track time , */\
+ { 0x4900, "ctrl_bypassclip"}, /* Bypass clip control (function depending on digimux clip_x), */\
+ { 0x4910, "ctrl_bypassclip2"}, /* Bypass clip control (function depending on digimux clip_x), */\
+ { 0x4920, "ctrl_clkgateCFoff"}, /* to disable clock gating in the coolflux , */\
+ { 0x4930, "ctrl_testabst"}, /* testabst , */\
+ { 0x4940, "ctrl_clipfast"}, /* clock switch for battery protection clipper, it switches back to old frequency, */\
+ { 0x4950, "ctrl_cs_8ohm"}, /* 8 ohm mode for current sense (gain mode) , */\
+ { 0x4960, "reserved"}, /* reserved , */\
+ { 0x4974, "delay_clock_sh"}, /* delay_sh, tunes S7H delay , */\
+ { 0x49c0, "inv_clksh"}, /* Invert the sample/hold clock for current sense ADC, */\
+ { 0x49d0, "inv_neg"}, /* Invert neg signal , */\
+ { 0x49e0, "inv_se"}, /* Invert se signal , */\
+ { 0x49f0, "setse"}, /* switches between Single Ende and differentail mode, */\
+ { 0x4a12, "ctrl_adc10_sel"}, /* select the input to convert the 10b ADC , */\
+ { 0x4a60, "ctrl_adc10_reset"}, /* Global asynchronous reset (active HIGH) 10 bit ADC, */\
+ { 0x4a81, "ctrl_adc10_test"}, /* Test mode selection signal 10 bit ADC , */\
+ { 0x4aa0, "ctrl_bypass_lp_vbat"}, /* lp filter in batt sensor , */\
+ { 0x4ae0, "ctrl_dc_offset"}, /* switch offset control on/off, is decimator offset control, */\
+ { 0x4af0, "ctrl_tsense_hibias"}, /* bit to set the biasing in temp sensor to high , */\
+ { 0x4b00, "ctrl_adc13_iset"}, /* Micadc Setting of current consumption. Debug use only, */\
+ { 0x4b14, "ctrl_adc13_gain"}, /* Micadc gain setting (2-compl) , */\
+ { 0x4b61, "ctrl_adc13_slowdel"}, /* Micadc Delay setting for internal clock. Debug use only, */\
+ { 0x4b83, "ctrl_adc13_offset"}, /* Micadc ADC offset setting , */\
+ { 0x4bc0, "ctrl_adc13_bsoinv"}, /* Micadc bit stream output invert mode for test , */\
+ { 0x4bd0, "ctrl_adc13_resonator_enable"}, /* Micadc Give extra SNR with less stability. Debug use only, */\
+ { 0x4be0, "ctrl_testmicadc"}, /* Mux at input of MICADC for test purpose , */\
+ { 0x4c0f, "ctrl_offset"}, /* offset control for ABIST testing , */\
+ { 0x4d05, "ctrl_windac"}, /* for testing direct control windac , */\
+ { 0x4d65, "ctrl_peakcur"}, /* Control peakcur , */\
+ { 0x4dc3, "pwm_dcc_cnt"}, /* control pwm duty cycle when enbl_pwm_dcc is 1 , */\
+ { 0x4e04, "ctrl_slopecur"}, /* for testing direct control slopecur , */\
+ { 0x4e53, "ctrl_dem"}, /* dyn element matching control, rest of codes are optional, */\
+ { 0x4e93, "ctrl_demmismatch"}, /* dyn element matching add offset , */\
+ { 0x4ed0, "enbl_pwm_dcc"}, /* to enable direct control of pwm duty cycle , */\
+ { 0x5007, "gain"}, /* gain setting of the gain multiplier gain need to increase with factor 1.41 (3dB), */\
+ { 0x5081, "ctrl_sourceb"}, /* Set OUTB to , */\
+ { 0x50a1, "ctrl_sourcea"}, /* Set OUTA to , */\
+ { 0x50c1, "ctrl_sourcebst"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
+ { 0x50e1, "ctrl_test_mono"}, /* ABIST mode to add both amplifier halfs as stereo or one amplifier half as mono, */\
+ { 0x5104, "pulselengthbst"}, /* pulselength setting test input for boost converter , */\
+ { 0x5150, "ctrl_bypasslatchbst"}, /* bypass_latch in boost converter , */\
+ { 0x5160, "invertbst"}, /* invert pwmbst test signal , */\
+ { 0x5174, "pulselength"}, /* pulselength setting test input for amplifier , */\
+ { 0x51c0, "ctrl_bypasslatch"}, /* bypass_latch in boost convert , */\
+ { 0x51d0, "invertb"}, /* invert pwmb test signal , */\
+ { 0x51e0, "inverta"}, /* invert pwma test signal , */\
+ { 0x51f0, "ctrl_bypass_ctrlloop"}, /* bypass_ctrlloop bypasses the control loop of the amplifier, */\
+ { 0x5200, "ctrl_test_discrete"}, /* tbd for rdson testing , */\
+ { 0x5210, "ctrl_test_rdsona"}, /* tbd for rdson testing , */\
+ { 0x5220, "ctrl_test_rdsonb"}, /* tbd for rdson testing , */\
+ { 0x5230, "ctrl_test_rdsonbst"}, /* tbd for rdson testing , */\
+ { 0x5240, "ctrl_test_cvia"}, /* tbd for rdson testing , */\
+ { 0x5250, "ctrl_test_cvib"}, /* tbd for rdson testing , */\
+ { 0x5260, "ctrl_test_cvibst"}, /* tbd for rdson testing , */\
+ { 0x5290, "test_bypass_pwmdiscretea"}, /* for testing ( ABIST) , */\
+ { 0x52a0, "test_bypass_pwmdiscreteb"}, /* for testing ( ABIST) , */\
+ { 0x52b0, "ctrl_clipc_forcehigh"}, /* test signal for clipcontrol , */\
+ { 0x52c0, "ctrl_clipc_forcelow"}, /* test signal for clipcontrol , */\
+ { 0x52d0, "ctrl_test_sdelta"}, /* for testing ( ABIST) , */\
+ { 0x52e0, "ctrl_test_swhvp"}, /* for testing ( ABIST) , */\
+ { 0x52f0, "test_gain_reduction"}, /* test gain reduction , */\
+ { 0x5303, "ctrl_digimux_out_test1"}, /* Digimux TEST1 out , */\
+ { 0x5343, "ctrl_digimux_out_test2"}, /* Digimux TEST2 out. output flag_clipa_low depending on cntr_bypassclip setting, */\
+ { 0x5383, "ctrl_digimux_out_data1"}, /* Digimux DATA1 out (output flag_clipb_high depending on cntr_bypassclip setting), */\
+ { 0x53c3, "ctrl_digimux_out_data3"}, /* Digimux DATA3 out (output flag_clipx_x depending on cntr_bypassclip setting), */\
+ { 0x5400, "hs_mode"}, /* hs_mode, high speed mode I2C bus , */\
+ { 0x5412, "test_parametric_io"}, /* test_parametric_io for testing pads , */\
+ { 0x5440, "enbl_ringo"}, /* enbl_ringo, for test purpose to check with ringo , */\
+ { 0x5480, "ctrl_cliplevel"}, /* Clip level , */\
+ { 0x5491, "ctrl_anamux_sel"}, /* anamux selection , */\
+ { 0x54b0, "test_vdddsw_dio"}, /* to overrule the power switches for memory , */\
+ { 0x54c0, "ctrl_bypass_diosw_ovp"}, /* To disable the overvoltage protection of vddd_dio_sw, */\
+ { 0x54d0, "test_vddd_sw"}, /* test vdd sw , */\
+ { 0x54e0, "test_vddd_sw_comp"}, /* test vdd sw comp , */\
+ { 0x550e, "enbl_amp"}, /* enbl_amp for testing to enable all analoge blocks in amplifier, */\
+ { 0x55f0, "fr_fsp"}, /* extr free running clock mode for testing , */\
+ { 0x5600, "use_direct_ctrls"}, /* use_direct_ctrls, to overrule several functions direct for testing, */\
+ { 0x5610, "rst_datapath"}, /* rst_datapath, datapath reset , */\
+ { 0x5620, "rst_cgu"}, /* rst_cgu, cgu reset , */\
+ { 0x5637, "enbl_ref"}, /* for testing to enable all analoge blocks in references, */\
+ { 0x56b0, "enbl_engage"}, /* Enable output stage amplifier , */\
+ { 0x56c0, "use_direct_clk_ctrl"}, /* use_direct_clk_ctrl, to overrule several functions direct for testing, */\
+ { 0x56d0, "use_direct_pll_ctrl"}, /* use_direct_pll_ctrl, to overrule several functions direct for test, */\
+ { 0x56e0, "use_direct_ctrls_2"}, /* use_direct_sourseamp_ctrls, to overrule several functions direct for testing, */\
+ { 0x5707, "ctrl_anamux_out_test1"}, /* Anamux control , */\
+ { 0x5782, "ctrl_zero"}, /* Bandwith control feedbackloop , */\
+ { 0x57b0, "enbl_ldo_stress"}, /* LDO stress function frinch capacitors , */\
+ { 0x57c0, "ctrl_ocptest"}, /* ctrl_ocptest, deactivates the over current protection in the power stages of the amplifier. The ocp flag signals stay active., */\
+ { 0x57e0, "ctrl_otptest"}, /* otptest, test mode otp amplifier , */\
+ { 0x57f0, "ctrl_reverse"}, /* CTRL revers , */\
+ { 0x5802, "pll_mdec_msb"}, /* most significant bits pll_mdec , */\
+ { 0x5833, "pll_selr"}, /* pll_selr , */\
+ { 0x5874, "pll_selp"}, /* pll_selp , */\
+ { 0x58c3, "pll_seli"}, /* pll_seli , */\
+ { 0x5900, "pll_psel"}, /* pll_psel , */\
+ { 0x5910, "use_direct_pll_psel"}, /* use_direct_pll_psel , */\
+ { 0x5923, "nbck"}, /* NBCK , */\
+ { 0x5960, "auto_nbck"}, /* AUTO_NBCK , */\
+ { 0x5970, "pll_frm"}, /* pll_frm , */\
+ { 0x5980, "pll_directi"}, /* pll_directi , */\
+ { 0x5990, "pll_directo"}, /* pll_directo , */\
+ { 0x59a0, "enbl_PLL"}, /* enbl_PLL , */\
+ { 0x59b0, "sel_clkout"}, /* SEL_CLKOUT , */\
+ { 0x59e0, "fr_lost_clk"}, /* fr_lost_clk , */\
+ { 0x59f0, "pll_bypass"}, /* pll_bypass , */\
+ { 0x5a0f, "tsig_freq"}, /* tsig_freq, internal sinus test generator, frequency control, */\
+ { 0x5b02, "tsig_freq_msb"}, /* select internal sinus test generator, frequency control msb bits, */\
+ { 0x5b30, "inject_tsig"}, /* inject_tsig, control bit to switch to internal sinus test generator, */\
+ { 0x5b44, "ctrl_adc10_prog_sample"}, /* control ADC10 , */\
+ { 0x5c01, "pll_ndec_msb"}, /* most significant bits of pll_ndec , */\
+ { 0x5c2d, "pll_mdec"}, /* bits 13..0 of pll_mdec , */\
+ { 0x5d06, "pll_pdec"}, /* pll_pdec , */\
+ { 0x5d87, "pll_ndec"}, /* bits 7..0 of pll_ndec , */\
+ { 0x5e00, "pdm_ch_sel_reg"}, /* PDM channel selection , */\
+ { 0x5e10, "pdm_iis_rst_reg"}, /* PDM Interface reset , */\
+ { 0x5e20, "clk_src_sel_reg"}, /* WS Source Selection , */\
+ { 0x5e70, "pdm_resync_bypass"}, /* PDM resynchronization bypass , */\
+ { 0x6007, "MTP_key1"}, /* MTP Key1 , */\
+ { 0x6185, "mtp_ecc_tcin"}, /* Mtp_ecc_tcin , */\
+ { 0x6203, "mtp_man_address_in"}, /* address from i2cregs for writing one word single mtp, */\
+ { 0x6260, "mtp_ecc_eeb"}, /* enable code bit generation (active low!) , */\
+ { 0x6270, "mtp_ecc_ecb"}, /* enable correction signal (active low!) , */\
+ { 0x6280, "man_copy_mtp_to_iic"}, /* start copying single word from mtp to i2cregs_mtp , */\
+ { 0x6290, "man_copy_iic_to_mtp"}, /* start copying single word from i2cregs_mtp to mtp [Key 1 protected], */\
+ { 0x62a0, "auto_copy_mtp_to_iic"}, /* start copying all the data from mtp to i2cregs_mtp, */\
+ { 0x62b0, "auto_copy_iic_to_mtp"}, /* start copying all the data from i2cregs_mtp to mtp [Key 2 protected], */\
+ { 0x62d2, "mtp_speed_mode"}, /* Speed mode , */\
+ { 0x6340, "mtp_dircet_enable"}, /* mtp_direct_enable (key1 protected) , */\
+ { 0x6350, "mtp_direct_wr"}, /* mtp_direct_wr (key1 protected) direct value for mtp pin wr. To be enabled via iic2mtp_mtp_direct_enable, */\
+ { 0x6360, "mtp_direct_rd"}, /* mtp_direct_rd (key1 protected) direct value for mtp pin rd. To be enabled via iic2mtp_mtp_direct_enable, */\
+ { 0x6370, "mtp_direct_rst"}, /* mtp_direct_rst (key1 protected) direct value for mtp pin rst. To be enabled via iic2mtp_mtp_direct_enable, */\
+ { 0x6380, "mtp_direct_ers"}, /* mtp_direct_ers (key1 protected) direct value for mtp pin ers. To be enabled via iic2mtp_mtp_direct_enable, */\
+ { 0x6390, "mtp_direct_prg"}, /* mtp_direct_prg (key1 protected) direct value for mtp pin prg. To be enabled via iic2mtp_mtp_direct_enable, */\
+ { 0x63a0, "mtp_direct_epp"}, /* mtp_direct_epp (key1 protected) direct value for mtp pin epp. To be enabled via iic2mtp_mtp_direct_enable, */\
+ { 0x63b4, "mtp_direct_test"}, /* mtp_direct_test (key1 protected) , */\
+ { 0x640f, "mtp_man_data_in"}, /* single wordt be written to MTP (manual copy) , */\
+ { 0x7000, "cf_rst_dsp"}, /* Reset CoolFlux DSP , */\
+ { 0x7011, "cf_dmem"}, /* Target memory for access , */\
+ { 0x7030, "cf_aif"}, /* Autoincrement-flag for memory-address , */\
+ { 0x7040, "cf_int"}, /* Interrupt CoolFlux DSP , */\
+ { 0x7087, "cf_req"}, /* request for access (8 channels) , */\
+ { 0x710f, "cf_madd"}, /* memory-address to be accessed , */\
+ { 0x720f, "cf_mema"}, /* activate memory access (24- or 32-bits data is written/read to/from memory, */\
+ { 0x7307, "cf_err"}, /* cf error Flags , */\
+ { 0x7387, "cf_ack"}, /* acknowledge of requests (8 channels")" , */\
+ { 0x8000, "calibration_onetime"}, /* Calibration schedule (key2 protected) , */\
+ { 0x8010, "calibr_ron_done"}, /* (key2 protected) calibration of Ron has been executed, */\
+ { 0x8105, "calibr_vout_offset"}, /* calibr_vout_offset (DCDCoffset) 2's compliment (key1 protected), */\
+ { 0x8163, "calibr_delta_gain"}, /* delta gain for vamp (alpha) 2's compliment (key1 protected), */\
+ { 0x81a5, "calibr_offs_amp"}, /* offset for vamp (Ampoffset) 2's compliment (key1 protected), */\
+ { 0x8207, "calibr_gain_cs"}, /* gain current sense (Imeasalpha) 2's compliment (key1 protected), */\
+ { 0x8284, "calibr_temp_offset"}, /* temperature offset 2's compliment (key1 protected), */\
+ { 0x82d2, "calibr_temp_gain"}, /* temperature gain 2's compliment (key1 protected) , */\
+ { 0x830f, "calibr_ron"}, /* Ron resistance of coil (key1 protected) , */\
+ { 0x8406, "ctrl_offset_a"}, /* Offset of amplifier level shifter , */\
+ { 0x8486, "ctrl_offset_b"}, /* Offset of amplifier level shifter , */\
+ { 0x850f, "type_bits_HW"}, /* HW Bits , */\
+ { 0x860f, "type_bits1_SW"}, /* MTP-control SW1 , */\
+ { 0x870f, "type_bits2_SW"}, /* MTP-control SW2 , */\
+ { 0x8a0f, "production_data1"}, /* (key1 protected) , */\
+ { 0x8b0f, "production_data2"}, /* (key1 protected) , */\
+ { 0x8c0f, "production_data3"}, /* (key1 protected) , */\
+ { 0x8d0f, "production_data4"}, /* (key1 protected) , */\
+ { 0x8e0f, "production_data5"}, /* (key1 protected) , */\
+ { 0x8f0f, "production_data6"}, /* (key1 protected) , */\
+ { 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+
+
+#endif /* TFA_INC_TFA9891_TFAFIELDNAMES_H_ */
diff --git a/inc/tfa9894_tfafieldnames.h b/sound/soc/codecs/tfa9894_tfafieldnames.h
similarity index 83%
rename from inc/tfa9894_tfafieldnames.h
rename to sound/soc/codecs/tfa9894_tfafieldnames.h
index ee676b7..327c15e 100644
--- a/inc/tfa9894_tfafieldnames.h
+++ b/sound/soc/codecs/tfa9894_tfafieldnames.h
@@ -1,1072 +1,1072 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _TFA9894_TFAFIELDNAMES_H
-#define _TFA9894_TFAFIELDNAMES_H
-
-
-#define TFA9894_I2CVERSION 17.0
-
-typedef enum nxpTfa9894BfEnumList {
- TFA9894_BF_PWDN = 0x0000, /*!< Powerdown control */
- TFA9894_BF_I2CR = 0x0010, /*!< I2C Reset - Auto clear */
- TFA9894_BF_CFE = 0x0020, /*!< Enable CoolFlux DSP */
- TFA9894_BF_AMPE = 0x0030, /*!< Enable Amplifier */
- TFA9894_BF_DCA = 0x0040, /*!< Enable DCDC Boost converter */
- TFA9894_BF_SBSL = 0x0050, /*!< Coolflux configured */
- TFA9894_BF_AMPC = 0x0060, /*!< CoolFlux control over amplifier */
- TFA9894_BF_INTP = 0x0071, /*!< Interrupt config */
- TFA9894_BF_FSSSEL= 0x0090, /*!< Audio sample reference */
- TFA9894_BF_BYPOCP= 0x00a0, /*!< Bypass OCP */
- TFA9894_BF_TSTOCP= 0x00b0, /*!< OCP testing control */
- TFA9894_BF_BSSS = 0x00c0, /*!< Vbat protection steepness */
- TFA9894_BF_HPFBYP= 0x00d0, /*!< Bypass High Pass Filter */
- TFA9894_BF_DPSA = 0x00e0, /*!< Enable DPSA */
- TFA9894_BF_AMPINSEL= 0x0101, /*!< Amplifier input selection */
- TFA9894_BF_MANSCONF= 0x0120, /*!< Device I2C settings configured */
- TFA9894_BF_MANCOLD= 0x0130, /*!< Execute cold start */
- TFA9894_BF_MANROBOD= 0x0140, /*!< Reaction on BOD */
- TFA9894_BF_BODE = 0x0150, /*!< Enable BOD (only in direct control mode) */
- TFA9894_BF_BODHYS= 0x0160, /*!< Enable Hysteresis of BOD */
- TFA9894_BF_BODFILT= 0x0171, /*!< BOD filter */
- TFA9894_BF_BODTHLVL= 0x0191, /*!< BOD threshold */
- TFA9894_BF_MUTETO= 0x01b0, /*!< Time out SB mute sequence */
- TFA9894_BF_MANWDE= 0x01c0, /*!< Watchdog enable */
- TFA9894_BF_OPENMTP= 0x01e0, /*!< Control for FAIM protection */
- TFA9894_BF_FAIMVBGOVRRL= 0x01f0, /*!< Overrule the enabling of VBG for faim erase/write access */
- TFA9894_BF_AUDFS = 0x0203, /*!< Audio sample rate Fs */
- TFA9894_BF_INPLEV= 0x0240, /*!< TDM output attenuation */
- TFA9894_BF_FRACTDEL= 0x0255, /*!< Current sense fractional delay */
- TFA9894_BF_TDMPRES= 0x02b1, /*!< Control for HW manager */
- TFA9894_BF_AMPOCRT= 0x02d2, /*!< Amplifier on-off criteria for shutdown */
- TFA9894_BF_REV = 0x030f, /*!< Revision info */
- TFA9894_BF_REFCKEXT= 0x0401, /*!< PLL external reference clock */
- TFA9894_BF_REFCKSEL= 0x0420, /*!< PLL internal reference clock */
- TFA9894_BF_MCLKSEL= 0x0432, /*!< Master Clock Selection */
- TFA9894_BF_MANAOOSC= 0x0460, /*!< Internal OSC1M off at PWDN */
- TFA9894_BF_ACKCLDDIS= 0x0470, /*!< Automatic PLL reference clock selection for cold start */
- TFA9894_BF_SPKSSEN= 0x0510, /*!< Enable speaker sub-system */
- TFA9894_BF_MTPSSEN= 0x0520, /*!< Enable FAIM sub-system */
- TFA9894_BF_WDTCLKEN= 0x0530, /*!< Enable Coolflux watchdog clock */
- TFA9894_BF_VDDS = 0x1000, /*!< POR */
- TFA9894_BF_PLLS = 0x1010, /*!< PLL Lock */
- TFA9894_BF_OTDS = 0x1020, /*!< OTP alarm */
- TFA9894_BF_OVDS = 0x1030, /*!< OVP alarm */
- TFA9894_BF_UVDS = 0x1040, /*!< UVP alarm */
- TFA9894_BF_OCDS = 0x1050, /*!< OCP amplifier (sticky register, clear on read) */
- TFA9894_BF_CLKS = 0x1060, /*!< Clocks stable */
- TFA9894_BF_MTPB = 0x1070, /*!< MTP busy */
- TFA9894_BF_NOCLK = 0x1080, /*!< Lost clock */
- TFA9894_BF_ACS = 0x1090, /*!< Cold Start */
- TFA9894_BF_WDS = 0x10a0, /*!< Watchdog */
- TFA9894_BF_SWS = 0x10b0, /*!< Amplifier engage */
- TFA9894_BF_AMPS = 0x10c0, /*!< Amplifier enable */
- TFA9894_BF_AREFS = 0x10d0, /*!< References enable */
- TFA9894_BF_ADCCR = 0x10e0, /*!< Control ADC */
- TFA9894_BF_BODNOK= 0x10f0, /*!< BOD Flag - VDD NOT OK */
- TFA9894_BF_DCIL = 0x1100, /*!< DCDC current limiting */
- TFA9894_BF_DCDCA = 0x1110, /*!< DCDC active (sticky register, clear on read) */
- TFA9894_BF_DCOCPOK= 0x1120, /*!< DCDC OCP nmos (sticky register, clear on read) */
- TFA9894_BF_DCHVBAT= 0x1140, /*!< DCDC level 1x */
- TFA9894_BF_DCH114= 0x1150, /*!< DCDC level 1.14x */
- TFA9894_BF_DCH107= 0x1160, /*!< DCDC level 1.07x */
- TFA9894_BF_SPKS = 0x1170, /*!< Speaker status */
- TFA9894_BF_CLKOOR= 0x1180, /*!< External clock status */
- TFA9894_BF_MANALARM= 0x1190, /*!< Alarm state */
- TFA9894_BF_TDMERR= 0x11a0, /*!< TDM error */
- TFA9894_BF_TDMLUTER= 0x11b0, /*!< TDM lookup table error */
- TFA9894_BF_OCPOAP= 0x1200, /*!< OCPOK pmos A */
- TFA9894_BF_OCPOAN= 0x1210, /*!< OCPOK nmos A */
- TFA9894_BF_OCPOBP= 0x1220, /*!< OCPOK pmos B */
- TFA9894_BF_OCPOBN= 0x1230, /*!< OCPOK nmos B */
- TFA9894_BF_CLIPS = 0x1240, /*!< Amplifier clipping */
- TFA9894_BF_MANMUTE= 0x1250, /*!< Audio mute sequence */
- TFA9894_BF_MANOPER= 0x1260, /*!< Device in Operating state */
- TFA9894_BF_LP1 = 0x1270, /*!< Low power MODE1 detection */
- TFA9894_BF_LA = 0x1280, /*!< Low amplitude detection */
- TFA9894_BF_VDDPH = 0x1290, /*!< VDDP greater than VBAT flag */
- TFA9894_BF_TDMSTAT= 0x1402, /*!< TDM Status bits */
- TFA9894_BF_MANSTATE= 0x1433, /*!< Device Manager status */
- TFA9894_BF_DCMODE= 0x14b1, /*!< DCDC mode status bits */
- TFA9894_BF_BATS = 0x1509, /*!< Battery voltage (V) */
- TFA9894_BF_TEMPS = 0x1608, /*!< IC Temperature (C) */
- TFA9894_BF_VDDPS = 0x1709, /*!< IC VDDP voltage (1023*VDDP/13V) */
- TFA9894_BF_TDME = 0x2000, /*!< Enable interface */
- TFA9894_BF_TDMSPKE= 0x2010, /*!< Control audio tdm channel in sink0 */
- TFA9894_BF_TDMDCE= 0x2020, /*!< Control audio tdm channel in sink1 */
- TFA9894_BF_TDMCSE= 0x2030, /*!< Source 0 enable */
- TFA9894_BF_TDMVSE= 0x2040, /*!< Source 1 enable */
- TFA9894_BF_TDMCFE= 0x2050, /*!< Source 2 enable */
- TFA9894_BF_TDMCF2E= 0x2060, /*!< Source 3 enable */
- TFA9894_BF_TDMCLINV= 0x2070, /*!< Reception data to BCK clock */
- TFA9894_BF_TDMFSPOL= 0x2080, /*!< FS polarity */
- TFA9894_BF_TDMDEL= 0x2090, /*!< Data delay to FS */
- TFA9894_BF_TDMADJ= 0x20a0, /*!< Data adjustment */
- TFA9894_BF_TDMOOMP= 0x20b1, /*!< Received audio compression */
- TFA9894_BF_TDMNBCK= 0x2103, /*!< TDM NBCK - Bit clock to FS ratio */
- TFA9894_BF_TDMFSLN= 0x2143, /*!< FS length (master mode only) */
- TFA9894_BF_TDMSLOTS= 0x2183, /*!< N-slots in Frame */
- TFA9894_BF_TDMTXDFO= 0x21c1, /*!< Format unused bits */
- TFA9894_BF_TDMTXUS0= 0x21e1, /*!< Format unused slots DATAO */
- TFA9894_BF_TDMSLLN= 0x2204, /*!< N-bits in slot */
- TFA9894_BF_TDMBRMG= 0x2254, /*!< N-bits remaining */
- TFA9894_BF_TDMSSIZE= 0x22a4, /*!< Sample size per slot */
- TFA9894_BF_TDMSPKS= 0x2303, /*!< TDM slot for sink 0 */
- TFA9894_BF_TDMDCS= 0x2343, /*!< TDM slot for sink 1 */
- TFA9894_BF_TDMCFSEL= 0x2381, /*!< TDM Source 2 data selection */
- TFA9894_BF_TDMCF2SEL= 0x23a1, /*!< TDM Source 3 data selection */
- TFA9894_BF_TDMCSS= 0x2403, /*!< Slot Position of source 0 data */
- TFA9894_BF_TDMVSS= 0x2443, /*!< Slot Position of source 1 data */
- TFA9894_BF_TDMCFS= 0x2483, /*!< Slot Position of source 2 data */
- TFA9894_BF_TDMCF2S= 0x24c3, /*!< Slot Position of source 3 data */
- TFA9894_BF_ISTVDDS= 0x4000, /*!< Status POR */
- TFA9894_BF_ISTBSTOC= 0x4010, /*!< Status DCDC OCP */
- TFA9894_BF_ISTOTDS= 0x4020, /*!< Status OTP alarm */
- TFA9894_BF_ISTOCPR= 0x4030, /*!< Status OCP alarm */
- TFA9894_BF_ISTUVDS= 0x4040, /*!< Status UVP alarm */
- TFA9894_BF_ISTMANALARM= 0x4050, /*!< Status manager alarm state */
- TFA9894_BF_ISTTDMER= 0x4060, /*!< Status TDM error */
- TFA9894_BF_ISTNOCLK= 0x4070, /*!< Status lost clock */
- TFA9894_BF_ISTCFMER= 0x4080, /*!< Status cfma error */
- TFA9894_BF_ISTCFMAC= 0x4090, /*!< Status cfma ack */
- TFA9894_BF_ISTSPKS= 0x40a0, /*!< Status coolflux speaker error */
- TFA9894_BF_ISTACS= 0x40b0, /*!< Status cold started */
- TFA9894_BF_ISTWDS= 0x40c0, /*!< Status watchdog reset */
- TFA9894_BF_ISTBODNOK= 0x40d0, /*!< Status brown out detect */
- TFA9894_BF_ISTLP1= 0x40e0, /*!< Status low power mode1 detect */
- TFA9894_BF_ISTCLKOOR= 0x40f0, /*!< Status clock out of range */
- TFA9894_BF_ICLVDDS= 0x4400, /*!< Clear POR */
- TFA9894_BF_ICLBSTOC= 0x4410, /*!< Clear DCDC OCP */
- TFA9894_BF_ICLOTDS= 0x4420, /*!< Clear OTP alarm */
- TFA9894_BF_ICLOCPR= 0x4430, /*!< Clear OCP alarm */
- TFA9894_BF_ICLUVDS= 0x4440, /*!< Clear UVP alarm */
- TFA9894_BF_ICLMANALARM= 0x4450, /*!< Clear manager alarm state */
- TFA9894_BF_ICLTDMER= 0x4460, /*!< Clear TDM error */
- TFA9894_BF_ICLNOCLK= 0x4470, /*!< Clear lost clk */
- TFA9894_BF_ICLCFMER= 0x4480, /*!< Clear cfma err */
- TFA9894_BF_ICLCFMAC= 0x4490, /*!< Clear cfma ack */
- TFA9894_BF_ICLSPKS= 0x44a0, /*!< Clear coolflux speaker error */
- TFA9894_BF_ICLACS= 0x44b0, /*!< Clear cold started */
- TFA9894_BF_ICLWDS= 0x44c0, /*!< Clear watchdog reset */
- TFA9894_BF_ICLBODNOK= 0x44d0, /*!< Clear brown out detect */
- TFA9894_BF_ICLLP1= 0x44e0, /*!< Clear low power mode1 detect */
- TFA9894_BF_ICLCLKOOR= 0x44f0, /*!< Clear clock out of range */
- TFA9894_BF_IEVDDS= 0x4800, /*!< Enable POR */
- TFA9894_BF_IEBSTOC= 0x4810, /*!< Enable DCDC OCP */
- TFA9894_BF_IEOTDS= 0x4820, /*!< Enable OTP alarm */
- TFA9894_BF_IEOCPR= 0x4830, /*!< Enable OCP alarm */
- TFA9894_BF_IEUVDS= 0x4840, /*!< Enable UVP alarm */
- TFA9894_BF_IEMANALARM= 0x4850, /*!< Enable Manager Alarm state */
- TFA9894_BF_IETDMER= 0x4860, /*!< Enable TDM error */
- TFA9894_BF_IENOCLK= 0x4870, /*!< Enable lost clk */
- TFA9894_BF_IECFMER= 0x4880, /*!< Enable cfma err */
- TFA9894_BF_IECFMAC= 0x4890, /*!< Enable cfma ack */
- TFA9894_BF_IESPKS= 0x48a0, /*!< Enable coolflux speaker error */
- TFA9894_BF_IEACS = 0x48b0, /*!< Enable cold started */
- TFA9894_BF_IEWDS = 0x48c0, /*!< Enable watchdog reset */
- TFA9894_BF_IEBODNOK= 0x48d0, /*!< Enable brown out detect */
- TFA9894_BF_IELP1 = 0x48e0, /*!< Enable low power mode1 detect */
- TFA9894_BF_IECLKOOR= 0x48f0, /*!< Enable clock out of range */
- TFA9894_BF_IPOVDDS= 0x4c00, /*!< Polarity POR */
- TFA9894_BF_IPOBSTOC= 0x4c10, /*!< Polarity DCDC OCP */
- TFA9894_BF_IPOOTDS= 0x4c20, /*!< Polarity OTP alarm */
- TFA9894_BF_IPOOCPR= 0x4c30, /*!< Polarity ocp alarm */
- TFA9894_BF_IPOUVDS= 0x4c40, /*!< Polarity UVP alarm */
- TFA9894_BF_IPOMANALARM= 0x4c50, /*!< Polarity manager alarm state */
- TFA9894_BF_IPOTDMER= 0x4c60, /*!< Polarity TDM error */
- TFA9894_BF_IPONOCLK= 0x4c70, /*!< Polarity lost clk */
- TFA9894_BF_IPOCFMER= 0x4c80, /*!< Polarity cfma err */
- TFA9894_BF_IPOCFMAC= 0x4c90, /*!< Polarity cfma ack */
- TFA9894_BF_IPOSPKS= 0x4ca0, /*!< Polarity coolflux speaker error */
- TFA9894_BF_IPOACS= 0x4cb0, /*!< Polarity cold started */
- TFA9894_BF_IPOWDS= 0x4cc0, /*!< Polarity watchdog reset */
- TFA9894_BF_IPOBODNOK= 0x4cd0, /*!< Polarity brown out detect */
- TFA9894_BF_IPOLP1= 0x4ce0, /*!< Polarity low power mode1 detect */
- TFA9894_BF_IPOCLKOOR= 0x4cf0, /*!< Polarity clock out of range */
- TFA9894_BF_BSSCR = 0x5001, /*!< Battery safeguard attack time */
- TFA9894_BF_BSST = 0x5023, /*!< Battery safeguard threshold voltage level */
- TFA9894_BF_BSSRL = 0x5061, /*!< Battery safeguard maximum reduction */
- TFA9894_BF_BSSRR = 0x5082, /*!< Battery safeguard release time */
- TFA9894_BF_BSSHY = 0x50b1, /*!< Battery Safeguard hysteresis */
- TFA9894_BF_BSSR = 0x50e0, /*!< Battery voltage read out */
- TFA9894_BF_BSSBY = 0x50f0, /*!< Bypass HW clipper */
- TFA9894_BF_CFSM = 0x5130, /*!< Coolflux firmware soft mute control */
- TFA9894_BF_VOL = 0x5187, /*!< CF firmware volume control */
- TFA9894_BF_CLIPCTRL= 0x5202, /*!< Clip control setting */
- TFA9894_BF_SLOPEE= 0x5230, /*!< Enables slope control */
- TFA9894_BF_SLOPESET= 0x5240, /*!< Slope speed setting (binary coded) */
- TFA9894_BF_AMPGAIN= 0x5287, /*!< Amplifier gain */
- TFA9894_BF_TDMDCG= 0x5703, /*!< Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE) */
- TFA9894_BF_TDMSPKG= 0x5743, /*!< Total gain depending on INPLEV setting (channel 0) */
- TFA9894_BF_DCINSEL= 0x5781, /*!< VAMP_OUT2 input selection */
- TFA9894_BF_LNMODE= 0x5881, /*!< Low noise gain mode control */
- TFA9894_BF_LPM1MODE= 0x5ac1, /*!< Low power mode control */
- TFA9894_BF_TDMSRCMAP= 0x5d02, /*!< TDM source mapping */
- TFA9894_BF_TDMSRCAS= 0x5d31, /*!< Sensed value A */
- TFA9894_BF_TDMSRCBS= 0x5d51, /*!< Sensed value B */
- TFA9894_BF_TDMSRCACLIP= 0x5d71, /*!< Clip information (analog /digital) for source0 */
- TFA9894_BF_TDMSRCBCLIP= 0x5d91, /*!< Clip information (analog /digital) for source1 */
- TFA9894_BF_DELCURCOMP= 0x6102, /*!< Delay to allign compensation signal with current sense signal */
- TFA9894_BF_SIGCURCOMP= 0x6130, /*!< Polarity of compensation for current sense */
- TFA9894_BF_ENCURCOMP= 0x6140, /*!< Enable current sense compensation */
- TFA9894_BF_LVLCLPPWM= 0x6152, /*!< Set the amount of pwm pulse that may be skipped before clip-flag is triggered */
- TFA9894_BF_DCVOF = 0x7005, /*!< First Boost Voltage Level */
- TFA9894_BF_DCVOS = 0x7065, /*!< Second Boost Voltage Level */
- TFA9894_BF_DCMCC = 0x70c3, /*!< Max Coil Current */
- TFA9894_BF_DCCV = 0x7101, /*!< Slope compensation current, represents LxF (inductance x frequency) value */
- TFA9894_BF_DCIE = 0x7120, /*!< Adaptive boost mode */
- TFA9894_BF_DCSR = 0x7130, /*!< Soft ramp up/down */
- TFA9894_BF_DCDIS = 0x7140, /*!< DCDC on/off */
- TFA9894_BF_DCPWM = 0x7150, /*!< DCDC PWM only mode */
- TFA9894_BF_DCTRACK= 0x7160, /*!< Boost algorithm selection, effective only when boost_intelligent is set to 1 */
- TFA9894_BF_DCENVSEL= 0x7170, /*!< Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1 */
- TFA9894_BF_DCTRIP= 0x7204, /*!< 1st adaptive boost trip levels, effective only when DCIE is set to 1 */
- TFA9894_BF_DCTRIP2= 0x7254, /*!< 2nd adaptive boost trip levels, effective only when DCIE is set to 1 */
- TFA9894_BF_DCTRIPT= 0x72a4, /*!< Track adaptive boost trip levels, effective only when boost_intelligent is set to 1 */
- TFA9894_BF_DCTRIPHYSTE= 0x72f0, /*!< Enable hysteresis on booster trip levels */
- TFA9894_BF_DCHOLD= 0x7304, /*!< Hold time for DCDC booster, effective only when boost_intelligent is set to 1 */
- TFA9894_BF_RST = 0x9000, /*!< Reset for Coolflux DSP */
- TFA9894_BF_DMEM = 0x9011, /*!< Target memory for CFMA using I2C interface */
- TFA9894_BF_AIF = 0x9030, /*!< Auto increment */
- TFA9894_BF_CFINT = 0x9040, /*!< Coolflux Interrupt - auto clear */
- TFA9894_BF_CFCGATE= 0x9050, /*!< Coolflux clock gating disabling control */
- TFA9894_BF_REQCMD= 0x9080, /*!< Firmware event request rpc command */
- TFA9894_BF_REQRST= 0x9090, /*!< Firmware event request reset restart */
- TFA9894_BF_REQMIPS= 0x90a0, /*!< Firmware event request short on mips */
- TFA9894_BF_REQMUTED= 0x90b0, /*!< Firmware event request mute sequence ready */
- TFA9894_BF_REQVOL= 0x90c0, /*!< Firmware event request volume ready */
- TFA9894_BF_REQDMG= 0x90d0, /*!< Firmware event request speaker damage detected */
- TFA9894_BF_REQCAL= 0x90e0, /*!< Firmware event request calibration completed */
- TFA9894_BF_REQRSV= 0x90f0, /*!< Firmware event request reserved */
- TFA9894_BF_MADD = 0x910f, /*!< CF memory address */
- TFA9894_BF_MEMA = 0x920f, /*!< Activate memory access */
- TFA9894_BF_ERR = 0x9307, /*!< CF error flags */
- TFA9894_BF_ACKCMD= 0x9380, /*!< Firmware event acknowledge rpc command */
- TFA9894_BF_ACKRST= 0x9390, /*!< Firmware event acknowledge reset restart */
- TFA9894_BF_ACKMIPS= 0x93a0, /*!< Firmware event acknowledge short on mips */
- TFA9894_BF_ACKMUTED= 0x93b0, /*!< Firmware event acknowledge mute sequence ready */
- TFA9894_BF_ACKVOL= 0x93c0, /*!< Firmware event acknowledge volume ready */
- TFA9894_BF_ACKDMG= 0x93d0, /*!< Firmware event acknowledge speaker damage detected */
- TFA9894_BF_ACKCAL= 0x93e0, /*!< Firmware event acknowledge calibration completed */
- TFA9894_BF_ACKRSV= 0x93f0, /*!< Firmware event acknowledge reserved */
- TFA9894_BF_MTPK = 0xa107, /*!< KEY2 to access KEY2 protected registers, customer key */
- TFA9894_BF_KEY1LOCKED= 0xa200, /*!< Indicates KEY1 is locked */
- TFA9894_BF_KEY2LOCKED= 0xa210, /*!< Indicates KEY2 is locked */
- TFA9894_BF_CMTPI = 0xa350, /*!< Start copying all the data from mtp to I2C mtp registers - auto clear */
- TFA9894_BF_CIMTP = 0xa360, /*!< Start copying data from I2C mtp registers to mtp - auto clear */
- TFA9894_BF_MTPRDMSB= 0xa50f, /*!< MSB word of MTP manual read data */
- TFA9894_BF_MTPRDLSB= 0xa60f, /*!< LSB word of MTP manual read data */
- TFA9894_BF_EXTTS = 0xb108, /*!< External temperature (C) */
- TFA9894_BF_TROS = 0xb190, /*!< Select temp Speaker calibration */
- TFA9894_BF_SWPROFIL= 0xe00f, /*!< Software profile data */
- TFA9894_BF_SWVSTEP= 0xe10f, /*!< Software vstep information */
- TFA9894_BF_MTPOTC= 0xf000, /*!< Calibration schedule */
- TFA9894_BF_MTPEX = 0xf010, /*!< Calibration Ron executed */
- TFA9894_BF_DCMCCAPI= 0xf020, /*!< Calibration current limit DCDC */
- TFA9894_BF_DCMCCSB= 0xf030, /*!< Sign bit for delta calibration current limit DCDC */
- TFA9894_BF_USERDEF= 0xf042, /*!< Calibration delta current limit DCDC */
- TFA9894_BF_CUSTINFO= 0xf078, /*!< Reserved space for allowing customer to store speaker information */
- TFA9894_BF_R25C = 0xf50f, /*!< Ron resistance of speaker coil */
-} nxpTfa9894BfEnumList_t;
-#define TFA9894_NAMETABLE static tfaBfName_t Tfa9894DatasheetNames[]= {\
- { 0x0, "PWDN"}, /* Powerdown control , */\
- { 0x10, "I2CR"}, /* I2C Reset - Auto clear , */\
- { 0x20, "CFE"}, /* Enable CoolFlux DSP , */\
- { 0x30, "AMPE"}, /* Enable Amplifier , */\
- { 0x40, "DCA"}, /* Enable DCDC Boost converter , */\
- { 0x50, "SBSL"}, /* Coolflux configured , */\
- { 0x60, "AMPC"}, /* CoolFlux control over amplifier , */\
- { 0x71, "INTP"}, /* Interrupt config , */\
- { 0x90, "FSSSEL"}, /* Audio sample reference , */\
- { 0xa0, "BYPOCP"}, /* Bypass OCP , */\
- { 0xb0, "TSTOCP"}, /* OCP testing control , */\
- { 0xc0, "BSSS"}, /* Vbat protection steepness , */\
- { 0xd0, "HPFBYP"}, /* Bypass High Pass Filter , */\
- { 0xe0, "DPSA"}, /* Enable DPSA , */\
- { 0x101, "AMPINSEL"}, /* Amplifier input selection , */\
- { 0x120, "MANSCONF"}, /* Device I2C settings configured , */\
- { 0x130, "MANCOLD"}, /* Execute cold start , */\
- { 0x140, "MANROBOD"}, /* Reaction on BOD , */\
- { 0x150, "BODE"}, /* Enable BOD (only in direct control mode) , */\
- { 0x160, "BODHYS"}, /* Enable Hysteresis of BOD , */\
- { 0x171, "BODFILT"}, /* BOD filter , */\
- { 0x191, "BODTHLVL"}, /* BOD threshold , */\
- { 0x1b0, "MUTETO"}, /* Time out SB mute sequence , */\
- { 0x1c0, "MANWDE"}, /* Watchdog enable , */\
- { 0x1e0, "OPENMTP"}, /* Control for FAIM protection , */\
- { 0x1f0, "FAIMVBGOVRRL"}, /* Overrule the enabling of VBG for faim erase/write access, */\
- { 0x203, "AUDFS"}, /* Audio sample rate Fs , */\
- { 0x240, "INPLEV"}, /* TDM output attenuation , */\
- { 0x255, "FRACTDEL"}, /* Current sense fractional delay , */\
- { 0x2b1, "TDMPRES"}, /* Control for HW manager , */\
- { 0x2d2, "AMPOCRT"}, /* Amplifier on-off criteria for shutdown , */\
- { 0x30f, "REV"}, /* Revision info , */\
- { 0x401, "REFCKEXT"}, /* PLL external reference clock , */\
- { 0x420, "REFCKSEL"}, /* PLL internal reference clock , */\
- { 0x432, "MCLKSEL"}, /* Master Clock Selection , */\
- { 0x460, "MANAOOSC"}, /* Internal OSC1M off at PWDN , */\
- { 0x470, "ACKCLDDIS"}, /* Automatic PLL reference clock selection for cold start, */\
- { 0x510, "SPKSSEN"}, /* Enable speaker sub-system , */\
- { 0x520, "MTPSSEN"}, /* Enable FAIM sub-system , */\
- { 0x530, "WDTCLKEN"}, /* Enable Coolflux watchdog clock , */\
- { 0x1000, "VDDS"}, /* POR , */\
- { 0x1010, "PLLS"}, /* PLL Lock , */\
- { 0x1020, "OTDS"}, /* OTP alarm , */\
- { 0x1030, "OVDS"}, /* OVP alarm , */\
- { 0x1040, "UVDS"}, /* UVP alarm , */\
- { 0x1050, "OCDS"}, /* OCP amplifier (sticky register, clear on read) , */\
- { 0x1060, "CLKS"}, /* Clocks stable , */\
- { 0x1070, "MTPB"}, /* MTP busy , */\
- { 0x1080, "NOCLK"}, /* Lost clock , */\
- { 0x1090, "ACS"}, /* Cold Start , */\
- { 0x10a0, "WDS"}, /* Watchdog , */\
- { 0x10b0, "SWS"}, /* Amplifier engage , */\
- { 0x10c0, "AMPS"}, /* Amplifier enable , */\
- { 0x10d0, "AREFS"}, /* References enable , */\
- { 0x10e0, "ADCCR"}, /* Control ADC , */\
- { 0x10f0, "BODNOK"}, /* BOD Flag - VDD NOT OK , */\
- { 0x1100, "DCIL"}, /* DCDC current limiting , */\
- { 0x1110, "DCDCA"}, /* DCDC active (sticky register, clear on read) , */\
- { 0x1120, "DCOCPOK"}, /* DCDC OCP nmos (sticky register, clear on read) , */\
- { 0x1140, "DCHVBAT"}, /* DCDC level 1x , */\
- { 0x1150, "DCH114"}, /* DCDC level 1.14x , */\
- { 0x1160, "DCH107"}, /* DCDC level 1.07x , */\
- { 0x1170, "SPKS"}, /* Speaker status , */\
- { 0x1180, "CLKOOR"}, /* External clock status , */\
- { 0x1190, "MANALARM"}, /* Alarm state , */\
- { 0x11a0, "TDMERR"}, /* TDM error , */\
- { 0x11b0, "TDMLUTER"}, /* TDM lookup table error , */\
- { 0x1200, "OCPOAP"}, /* OCPOK pmos A , */\
- { 0x1210, "OCPOAN"}, /* OCPOK nmos A , */\
- { 0x1220, "OCPOBP"}, /* OCPOK pmos B , */\
- { 0x1230, "OCPOBN"}, /* OCPOK nmos B , */\
- { 0x1240, "CLIPS"}, /* Amplifier clipping , */\
- { 0x1250, "MANMUTE"}, /* Audio mute sequence , */\
- { 0x1260, "MANOPER"}, /* Device in Operating state , */\
- { 0x1270, "LP1"}, /* Low power MODE1 detection , */\
- { 0x1280, "LA"}, /* Low amplitude detection , */\
- { 0x1290, "VDDPH"}, /* VDDP greater than VBAT flag , */\
- { 0x1402, "TDMSTAT"}, /* TDM Status bits , */\
- { 0x1433, "MANSTATE"}, /* Device Manager status , */\
- { 0x14b1, "DCMODE"}, /* DCDC mode status bits , */\
- { 0x1509, "BATS"}, /* Battery voltage (V) , */\
- { 0x1608, "TEMPS"}, /* IC Temperature (C) , */\
- { 0x1709, "VDDPS"}, /* IC VDDP voltage (1023*VDDP/13V) , */\
- { 0x2000, "TDME"}, /* Enable interface , */\
- { 0x2010, "TDMSPKE"}, /* Control audio tdm channel in sink0 , */\
- { 0x2020, "TDMDCE"}, /* Control audio tdm channel in sink1 , */\
- { 0x2030, "TDMCSE"}, /* Source 0 enable , */\
- { 0x2040, "TDMVSE"}, /* Source 1 enable , */\
- { 0x2050, "TDMCFE"}, /* Source 2 enable , */\
- { 0x2060, "TDMCF2E"}, /* Source 3 enable , */\
- { 0x2070, "TDMCLINV"}, /* Reception data to BCK clock , */\
- { 0x2080, "TDMFSPOL"}, /* FS polarity , */\
- { 0x2090, "TDMDEL"}, /* Data delay to FS , */\
- { 0x20a0, "TDMADJ"}, /* Data adjustment , */\
- { 0x20b1, "TDMOOMP"}, /* Received audio compression , */\
- { 0x2103, "TDMNBCK"}, /* TDM NBCK - Bit clock to FS ratio , */\
- { 0x2143, "TDMFSLN"}, /* FS length (master mode only) , */\
- { 0x2183, "TDMSLOTS"}, /* N-slots in Frame , */\
- { 0x21c1, "TDMTXDFO"}, /* Format unused bits , */\
- { 0x21e1, "TDMTXUS0"}, /* Format unused slots DATAO , */\
- { 0x2204, "TDMSLLN"}, /* N-bits in slot , */\
- { 0x2254, "TDMBRMG"}, /* N-bits remaining , */\
- { 0x22a4, "TDMSSIZE"}, /* Sample size per slot , */\
- { 0x2303, "TDMSPKS"}, /* TDM slot for sink 0 , */\
- { 0x2343, "TDMDCS"}, /* TDM slot for sink 1 , */\
- { 0x2381, "TDMCFSEL"}, /* TDM Source 2 data selection , */\
- { 0x23a1, "TDMCF2SEL"}, /* TDM Source 3 data selection , */\
- { 0x2403, "TDMCSS"}, /* Slot Position of source 0 data , */\
- { 0x2443, "TDMVSS"}, /* Slot Position of source 1 data , */\
- { 0x2483, "TDMCFS"}, /* Slot Position of source 2 data , */\
- { 0x24c3, "TDMCF2S"}, /* Slot Position of source 3 data , */\
- { 0x4000, "ISTVDDS"}, /* Status POR , */\
- { 0x4010, "ISTBSTOC"}, /* Status DCDC OCP , */\
- { 0x4020, "ISTOTDS"}, /* Status OTP alarm , */\
- { 0x4030, "ISTOCPR"}, /* Status OCP alarm , */\
- { 0x4040, "ISTUVDS"}, /* Status UVP alarm , */\
- { 0x4050, "ISTMANALARM"}, /* Status manager alarm state , */\
- { 0x4060, "ISTTDMER"}, /* Status TDM error , */\
- { 0x4070, "ISTNOCLK"}, /* Status lost clock , */\
- { 0x4080, "ISTCFMER"}, /* Status cfma error , */\
- { 0x4090, "ISTCFMAC"}, /* Status cfma ack , */\
- { 0x40a0, "ISTSPKS"}, /* Status coolflux speaker error , */\
- { 0x40b0, "ISTACS"}, /* Status cold started , */\
- { 0x40c0, "ISTWDS"}, /* Status watchdog reset , */\
- { 0x40d0, "ISTBODNOK"}, /* Status brown out detect , */\
- { 0x40e0, "ISTLP1"}, /* Status low power mode1 detect , */\
- { 0x40f0, "ISTCLKOOR"}, /* Status clock out of range , */\
- { 0x4400, "ICLVDDS"}, /* Clear POR , */\
- { 0x4410, "ICLBSTOC"}, /* Clear DCDC OCP , */\
- { 0x4420, "ICLOTDS"}, /* Clear OTP alarm , */\
- { 0x4430, "ICLOCPR"}, /* Clear OCP alarm , */\
- { 0x4440, "ICLUVDS"}, /* Clear UVP alarm , */\
- { 0x4450, "ICLMANALARM"}, /* Clear manager alarm state , */\
- { 0x4460, "ICLTDMER"}, /* Clear TDM error , */\
- { 0x4470, "ICLNOCLK"}, /* Clear lost clk , */\
- { 0x4480, "ICLCFMER"}, /* Clear cfma err , */\
- { 0x4490, "ICLCFMAC"}, /* Clear cfma ack , */\
- { 0x44a0, "ICLSPKS"}, /* Clear coolflux speaker error , */\
- { 0x44b0, "ICLACS"}, /* Clear cold started , */\
- { 0x44c0, "ICLWDS"}, /* Clear watchdog reset , */\
- { 0x44d0, "ICLBODNOK"}, /* Clear brown out detect , */\
- { 0x44e0, "ICLLP1"}, /* Clear low power mode1 detect , */\
- { 0x44f0, "ICLCLKOOR"}, /* Clear clock out of range , */\
- { 0x4800, "IEVDDS"}, /* Enable POR , */\
- { 0x4810, "IEBSTOC"}, /* Enable DCDC OCP , */\
- { 0x4820, "IEOTDS"}, /* Enable OTP alarm , */\
- { 0x4830, "IEOCPR"}, /* Enable OCP alarm , */\
- { 0x4840, "IEUVDS"}, /* Enable UVP alarm , */\
- { 0x4850, "IEMANALARM"}, /* Enable Manager Alarm state , */\
- { 0x4860, "IETDMER"}, /* Enable TDM error , */\
- { 0x4870, "IENOCLK"}, /* Enable lost clk , */\
- { 0x4880, "IECFMER"}, /* Enable cfma err , */\
- { 0x4890, "IECFMAC"}, /* Enable cfma ack , */\
- { 0x48a0, "IESPKS"}, /* Enable coolflux speaker error , */\
- { 0x48b0, "IEACS"}, /* Enable cold started , */\
- { 0x48c0, "IEWDS"}, /* Enable watchdog reset , */\
- { 0x48d0, "IEBODNOK"}, /* Enable brown out detect , */\
- { 0x48e0, "IELP1"}, /* Enable low power mode1 detect , */\
- { 0x48f0, "IECLKOOR"}, /* Enable clock out of range , */\
- { 0x4c00, "IPOVDDS"}, /* Polarity POR , */\
- { 0x4c10, "IPOBSTOC"}, /* Polarity DCDC OCP , */\
- { 0x4c20, "IPOOTDS"}, /* Polarity OTP alarm , */\
- { 0x4c30, "IPOOCPR"}, /* Polarity ocp alarm , */\
- { 0x4c40, "IPOUVDS"}, /* Polarity UVP alarm , */\
- { 0x4c50, "IPOMANALARM"}, /* Polarity manager alarm state , */\
- { 0x4c60, "IPOTDMER"}, /* Polarity TDM error , */\
- { 0x4c70, "IPONOCLK"}, /* Polarity lost clk , */\
- { 0x4c80, "IPOCFMER"}, /* Polarity cfma err , */\
- { 0x4c90, "IPOCFMAC"}, /* Polarity cfma ack , */\
- { 0x4ca0, "IPOSPKS"}, /* Polarity coolflux speaker error , */\
- { 0x4cb0, "IPOACS"}, /* Polarity cold started , */\
- { 0x4cc0, "IPOWDS"}, /* Polarity watchdog reset , */\
- { 0x4cd0, "IPOBODNOK"}, /* Polarity brown out detect , */\
- { 0x4ce0, "IPOLP1"}, /* Polarity low power mode1 detect , */\
- { 0x4cf0, "IPOCLKOOR"}, /* Polarity clock out of range , */\
- { 0x5001, "BSSCR"}, /* Battery safeguard attack time , */\
- { 0x5023, "BSST"}, /* Battery safeguard threshold voltage level , */\
- { 0x5061, "BSSRL"}, /* Battery safeguard maximum reduction , */\
- { 0x5082, "BSSRR"}, /* Battery safeguard release time , */\
- { 0x50b1, "BSSHY"}, /* Battery Safeguard hysteresis , */\
- { 0x50e0, "BSSR"}, /* Battery voltage read out , */\
- { 0x50f0, "BSSBY"}, /* Bypass HW clipper , */\
- { 0x5130, "CFSM"}, /* Coolflux firmware soft mute control , */\
- { 0x5187, "VOL"}, /* CF firmware volume control , */\
- { 0x5202, "CLIPCTRL"}, /* Clip control setting , */\
- { 0x5230, "SLOPEE"}, /* Enables slope control , */\
- { 0x5240, "SLOPESET"}, /* Slope speed setting (binary coded) , */\
- { 0x5287, "AMPGAIN"}, /* Amplifier gain , */\
- { 0x5703, "TDMDCG"}, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */\
- { 0x5743, "TDMSPKG"}, /* Total gain depending on INPLEV setting (channel 0), */\
- { 0x5781, "DCINSEL"}, /* VAMP_OUT2 input selection , */\
- { 0x5881, "LNMODE"}, /* Low noise gain mode control , */\
- { 0x5ac1, "LPM1MODE"}, /* Low power mode control , */\
- { 0x5d02, "TDMSRCMAP"}, /* TDM source mapping , */\
- { 0x5d31, "TDMSRCAS"}, /* Sensed value A , */\
- { 0x5d51, "TDMSRCBS"}, /* Sensed value B , */\
- { 0x5d71, "TDMSRCACLIP"}, /* Clip information (analog /digital) for source0 , */\
- { 0x5d91, "TDMSRCBCLIP"}, /* Clip information (analog /digital) for source1 , */\
- { 0x6102, "DELCURCOMP"}, /* Delay to allign compensation signal with current sense signal, */\
- { 0x6130, "SIGCURCOMP"}, /* Polarity of compensation for current sense , */\
- { 0x6140, "ENCURCOMP"}, /* Enable current sense compensation , */\
- { 0x6152, "LVLCLPPWM"}, /* Set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
- { 0x7005, "DCVOF"}, /* First Boost Voltage Level , */\
- { 0x7065, "DCVOS"}, /* Second Boost Voltage Level , */\
- { 0x70c3, "DCMCC"}, /* Max Coil Current , */\
- { 0x7101, "DCCV"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
- { 0x7120, "DCIE"}, /* Adaptive boost mode , */\
- { 0x7130, "DCSR"}, /* Soft ramp up/down , */\
- { 0x7140, "DCDIS"}, /* DCDC on/off , */\
- { 0x7150, "DCPWM"}, /* DCDC PWM only mode , */\
- { 0x7160, "DCTRACK"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
- { 0x7170, "DCENVSEL"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
- { 0x7204, "DCTRIP"}, /* 1st adaptive boost trip levels, effective only when DCIE is set to 1, */\
- { 0x7254, "DCTRIP2"}, /* 2nd adaptive boost trip levels, effective only when DCIE is set to 1, */\
- { 0x72a4, "DCTRIPT"}, /* Track adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
- { 0x72f0, "DCTRIPHYSTE"}, /* Enable hysteresis on booster trip levels , */\
- { 0x7304, "DCHOLD"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
- { 0x9000, "RST"}, /* Reset for Coolflux DSP , */\
- { 0x9011, "DMEM"}, /* Target memory for CFMA using I2C interface , */\
- { 0x9030, "AIF"}, /* Auto increment , */\
- { 0x9040, "CFINT"}, /* Coolflux Interrupt - auto clear , */\
- { 0x9050, "CFCGATE"}, /* Coolflux clock gating disabling control , */\
- { 0x9080, "REQCMD"}, /* Firmware event request rpc command , */\
- { 0x9090, "REQRST"}, /* Firmware event request reset restart , */\
- { 0x90a0, "REQMIPS"}, /* Firmware event request short on mips , */\
- { 0x90b0, "REQMUTED"}, /* Firmware event request mute sequence ready , */\
- { 0x90c0, "REQVOL"}, /* Firmware event request volume ready , */\
- { 0x90d0, "REQDMG"}, /* Firmware event request speaker damage detected , */\
- { 0x90e0, "REQCAL"}, /* Firmware event request calibration completed , */\
- { 0x90f0, "REQRSV"}, /* Firmware event request reserved , */\
- { 0x910f, "MADD"}, /* CF memory address , */\
- { 0x920f, "MEMA"}, /* Activate memory access , */\
- { 0x9307, "ERR"}, /* CF error flags , */\
- { 0x9380, "ACKCMD"}, /* Firmware event acknowledge rpc command , */\
- { 0x9390, "ACKRST"}, /* Firmware event acknowledge reset restart , */\
- { 0x93a0, "ACKMIPS"}, /* Firmware event acknowledge short on mips , */\
- { 0x93b0, "ACKMUTED"}, /* Firmware event acknowledge mute sequence ready , */\
- { 0x93c0, "ACKVOL"}, /* Firmware event acknowledge volume ready , */\
- { 0x93d0, "ACKDMG"}, /* Firmware event acknowledge speaker damage detected, */\
- { 0x93e0, "ACKCAL"}, /* Firmware event acknowledge calibration completed , */\
- { 0x93f0, "ACKRSV"}, /* Firmware event acknowledge reserved , */\
- { 0xa107, "MTPK"}, /* KEY2 to access KEY2 protected registers, customer key, */\
- { 0xa200, "KEY1LOCKED"}, /* Indicates KEY1 is locked , */\
- { 0xa210, "KEY2LOCKED"}, /* Indicates KEY2 is locked , */\
- { 0xa350, "CMTPI"}, /* Start copying all the data from mtp to I2C mtp registers - auto clear, */\
- { 0xa360, "CIMTP"}, /* Start copying data from I2C mtp registers to mtp - auto clear, */\
- { 0xa50f, "MTPRDMSB"}, /* MSB word of MTP manual read data , */\
- { 0xa60f, "MTPRDLSB"}, /* LSB word of MTP manual read data , */\
- { 0xb108, "EXTTS"}, /* External temperature (C) , */\
- { 0xb190, "TROS"}, /* Select temp Speaker calibration , */\
- { 0xe00f, "SWPROFIL"}, /* Software profile data , */\
- { 0xe10f, "SWVSTEP"}, /* Software vstep information , */\
- { 0xf000, "MTPOTC"}, /* Calibration schedule , */\
- { 0xf010, "MTPEX"}, /* Calibration Ron executed , */\
- { 0xf020, "DCMCCAPI"}, /* Calibration current limit DCDC , */\
- { 0xf030, "DCMCCSB"}, /* Sign bit for delta calibration current limit DCDC , */\
- { 0xf042, "USERDEF"}, /* Calibration delta current limit DCDC , */\
- { 0xf078, "CUSTINFO"}, /* Reserved space for allowing customer to store speaker information, */\
- { 0xf50f, "R25C"}, /* Ron resistance of speaker coil , */\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-
-#define TFA9894_BITNAMETABLE static tfaBfName_t Tfa9894BitNames[]= {\
- { 0x0, "powerdown"}, /* Powerdown control , */\
- { 0x10, "reset"}, /* I2C Reset - Auto clear , */\
- { 0x20, "enbl_coolflux"}, /* Enable CoolFlux DSP , */\
- { 0x30, "enbl_amplifier"}, /* Enable Amplifier , */\
- { 0x40, "enbl_boost"}, /* Enable DCDC Boost converter , */\
- { 0x50, "coolflux_configured"}, /* Coolflux configured , */\
- { 0x60, "sel_enbl_amplifier"}, /* CoolFlux control over amplifier , */\
- { 0x71, "int_pad_io"}, /* Interrupt config , */\
- { 0x90, "fs_pulse_sel"}, /* Audio sample reference , */\
- { 0xa0, "bypass_ocp"}, /* Bypass OCP , */\
- { 0xb0, "test_ocp"}, /* OCP testing control , */\
- { 0xc0, "batsense_steepness"}, /* Vbat protection steepness , */\
- { 0xd0, "bypass_hp"}, /* Bypass High Pass Filter , */\
- { 0xe0, "enbl_dpsa"}, /* Enable DPSA , */\
- { 0xf0, "sel_hysteresis"}, /* Select hysteresis for clock range detector , */\
- { 0x101, "vamp_sel1"}, /* Amplifier input selection , */\
- { 0x120, "src_set_configured"}, /* Device I2C settings configured , */\
- { 0x130, "execute_cold_start"}, /* Execute cold start , */\
- { 0x140, "man_enbl_brown_out"}, /* Reaction on BOD , */\
- { 0x150, "bod_enbl"}, /* Enable BOD (only in direct control mode) , */\
- { 0x160, "bod_hyst_enbl"}, /* Enable Hysteresis of BOD , */\
- { 0x171, "bod_delay_set"}, /* BOD filter , */\
- { 0x191, "bod_lvl_set"}, /* BOD threshold , */\
- { 0x1b0, "disable_mute_time_out"}, /* Time out SB mute sequence , */\
- { 0x1c0, "man_enbl_watchdog"}, /* Watchdog enable , */\
- { 0x1d0, "disable_engage"}, /* Disable Engage , */\
- { 0x1e0, "unprotect_faim"}, /* Control for FAIM protection , */\
- { 0x1f0, "faim_enable_vbg"}, /* Overrule the enabling of VBG for faim erase/write access, */\
- { 0x203, "audio_fs"}, /* Audio sample rate Fs , */\
- { 0x240, "input_level"}, /* TDM output attenuation , */\
- { 0x255, "cs_frac_delay"}, /* Current sense fractional delay , */\
- { 0x2b1, "use_tdm_presence"}, /* Control for HW manager , */\
- { 0x2d2, "ctrl_on2off_criterion"}, /* Amplifier on-off criteria for shutdown , */\
- { 0x30f, "device_rev"}, /* Revision info , */\
- { 0x401, "pll_clkin_sel"}, /* PLL external reference clock , */\
- { 0x420, "pll_clkin_sel_osc"}, /* PLL internal reference clock , */\
- { 0x432, "mclk_sel"}, /* Master Clock Selection , */\
- { 0x460, "enbl_osc1m_auto_off"}, /* Internal OSC1M off at PWDN , */\
- { 0x470, "disable_auto_sel_refclk"}, /* Automatic PLL reference clock selection for cold start, */\
- { 0x510, "enbl_spkr_ss"}, /* Enable speaker sub-system , */\
- { 0x520, "enbl_faim_ss"}, /* Enable FAIM sub-system , */\
- { 0x530, "enbl_wdt_clk"}, /* Enable Coolflux watchdog clock , */\
- { 0xe07, "ctrl_digtoana"}, /* Spare control from digital to analog , */\
- { 0xf0f, "hidden_code"}, /* Hidden code to enable access to hidden register. (0x5A6B/23147 default for engineering), */\
- { 0x1000, "flag_por"}, /* POR , */\
- { 0x1010, "flag_pll_lock"}, /* PLL Lock , */\
- { 0x1020, "flag_otpok"}, /* OTP alarm , */\
- { 0x1030, "flag_ovpok"}, /* OVP alarm , */\
- { 0x1040, "flag_uvpok"}, /* UVP alarm , */\
- { 0x1050, "flag_ocp_alarm"}, /* OCP amplifier (sticky register, clear on read) , */\
- { 0x1060, "flag_clocks_stable"}, /* Clocks stable , */\
- { 0x1070, "flag_mtp_busy"}, /* MTP busy , */\
- { 0x1080, "flag_lost_clk"}, /* Lost clock , */\
- { 0x1090, "flag_cold_started"}, /* Cold Start , */\
- { 0x10a0, "flag_watchdog_reset"}, /* Watchdog , */\
- { 0x10b0, "flag_engage"}, /* Amplifier engage , */\
- { 0x10c0, "flag_enbl_amp"}, /* Amplifier enable , */\
- { 0x10d0, "flag_enbl_ref"}, /* References enable , */\
- { 0x10e0, "flag_adc10_ready"}, /* Control ADC , */\
- { 0x10f0, "flag_bod_vddd_nok"}, /* BOD Flag - VDD NOT OK , */\
- { 0x1100, "flag_bst_bstcur"}, /* DCDC current limiting , */\
- { 0x1110, "flag_bst_hiz"}, /* DCDC active (sticky register, clear on read) , */\
- { 0x1120, "flag_bst_ocpok"}, /* DCDC OCP nmos (sticky register, clear on read) , */\
- { 0x1130, "flag_bst_peakcur"}, /* Indicates current is max in DC-to-DC converter , */\
- { 0x1140, "flag_bst_voutcomp"}, /* DCDC level 1x , */\
- { 0x1150, "flag_bst_voutcomp86"}, /* DCDC level 1.14x , */\
- { 0x1160, "flag_bst_voutcomp93"}, /* DCDC level 1.07x , */\
- { 0x1170, "flag_cf_speakererror"}, /* Speaker status , */\
- { 0x1180, "flag_clk_out_of_range"}, /* External clock status , */\
- { 0x1190, "flag_man_alarm_state"}, /* Alarm state , */\
- { 0x11a0, "flag_tdm_error"}, /* TDM error , */\
- { 0x11b0, "flag_tdm_lut_error"}, /* TDM lookup table error , */\
- { 0x1200, "flag_ocpokap"}, /* OCPOK pmos A , */\
- { 0x1210, "flag_ocpokan"}, /* OCPOK nmos A , */\
- { 0x1220, "flag_ocpokbp"}, /* OCPOK pmos B , */\
- { 0x1230, "flag_ocpokbn"}, /* OCPOK nmos B , */\
- { 0x1240, "flag_clip"}, /* Amplifier clipping , */\
- { 0x1250, "flag_man_start_mute_audio"}, /* Audio mute sequence , */\
- { 0x1260, "flag_man_operating_state"}, /* Device in Operating state , */\
- { 0x1270, "flag_lp_detect_mode1"}, /* Low power MODE1 detection , */\
- { 0x1280, "flag_low_amplitude"}, /* Low amplitude detection , */\
- { 0x1290, "flag_vddp_gt_vbat"}, /* VDDP greater than VBAT flag , */\
- { 0x1402, "tdm_status"}, /* TDM Status bits , */\
- { 0x1433, "man_state"}, /* Device Manager status , */\
- { 0x1473, "amp_ctrl_state"}, /* Amplifier control status , */\
- { 0x14b1, "status_bst_mode"}, /* DCDC mode status bits , */\
- { 0x1509, "bat_adc"}, /* Battery voltage (V) , */\
- { 0x1608, "temp_adc"}, /* IC Temperature (C) , */\
- { 0x1709, "vddp_adc"}, /* IC VDDP voltage (1023*VDDP/13V) , */\
- { 0x2000, "tdm_enable"}, /* Enable interface , */\
- { 0x2010, "tdm_sink0_enable"}, /* Control audio tdm channel in sink0 , */\
- { 0x2020, "tdm_sink1_enable"}, /* Control audio tdm channel in sink1 , */\
- { 0x2030, "tdm_source0_enable"}, /* Source 0 enable , */\
- { 0x2040, "tdm_source1_enable"}, /* Source 1 enable , */\
- { 0x2050, "tdm_source2_enable"}, /* Source 2 enable , */\
- { 0x2060, "tdm_source3_enable"}, /* Source 3 enable , */\
- { 0x2070, "tdm_clk_inversion"}, /* Reception data to BCK clock , */\
- { 0x2080, "tdm_fs_ws_polarity"}, /* FS polarity , */\
- { 0x2090, "tdm_data_delay"}, /* Data delay to FS , */\
- { 0x20a0, "tdm_data_adjustment"}, /* Data adjustment , */\
- { 0x20b1, "tdm_audio_sample_compression"}, /* Received audio compression , */\
- { 0x2103, "tdm_nbck"}, /* TDM NBCK - Bit clock to FS ratio , */\
- { 0x2143, "tdm_fs_ws_length"}, /* FS length (master mode only) , */\
- { 0x2183, "tdm_nb_of_slots"}, /* N-slots in Frame , */\
- { 0x21c1, "tdm_txdata_format"}, /* Format unused bits , */\
- { 0x21e1, "tdm_txdata_format_unused_slot"}, /* Format unused slots DATAO , */\
- { 0x2204, "tdm_slot_length"}, /* N-bits in slot , */\
- { 0x2254, "tdm_bits_remaining"}, /* N-bits remaining , */\
- { 0x22a4, "tdm_sample_size"}, /* Sample size per slot , */\
- { 0x2303, "tdm_sink0_slot"}, /* TDM slot for sink 0 , */\
- { 0x2343, "tdm_sink1_slot"}, /* TDM slot for sink 1 , */\
- { 0x2381, "tdm_source2_sel"}, /* TDM Source 2 data selection , */\
- { 0x23a1, "tdm_source3_sel"}, /* TDM Source 3 data selection , */\
- { 0x2403, "tdm_source0_slot"}, /* Slot Position of source 0 data , */\
- { 0x2443, "tdm_source1_slot"}, /* Slot Position of source 1 data , */\
- { 0x2483, "tdm_source2_slot"}, /* Slot Position of source 2 data , */\
- { 0x24c3, "tdm_source3_slot"}, /* Slot Position of source 3 data , */\
- { 0x4000, "int_out_flag_por"}, /* Status POR , */\
- { 0x4010, "int_out_flag_bst_ocpok"}, /* Status DCDC OCP , */\
- { 0x4020, "int_out_flag_otpok"}, /* Status OTP alarm , */\
- { 0x4030, "int_out_flag_ocp_alarm"}, /* Status OCP alarm , */\
- { 0x4040, "int_out_flag_uvpok"}, /* Status UVP alarm , */\
- { 0x4050, "int_out_flag_man_alarm_state"}, /* Status manager alarm state , */\
- { 0x4060, "int_out_flag_tdm_error"}, /* Status TDM error , */\
- { 0x4070, "int_out_flag_lost_clk"}, /* Status lost clock , */\
- { 0x4080, "int_out_flag_cfma_err"}, /* Status cfma error , */\
- { 0x4090, "int_out_flag_cfma_ack"}, /* Status cfma ack , */\
- { 0x40a0, "int_out_flag_cf_speakererror"}, /* Status coolflux speaker error , */\
- { 0x40b0, "int_out_flag_cold_started"}, /* Status cold started , */\
- { 0x40c0, "int_out_flag_watchdog_reset"}, /* Status watchdog reset , */\
- { 0x40d0, "int_out_flag_bod_vddd_nok"}, /* Status brown out detect , */\
- { 0x40e0, "int_out_flag_lp_detect_mode1"}, /* Status low power mode1 detect , */\
- { 0x40f0, "int_out_flag_clk_out_of_range"}, /* Status clock out of range , */\
- { 0x4400, "int_in_flag_por"}, /* Clear POR , */\
- { 0x4410, "int_in_flag_bst_ocpok"}, /* Clear DCDC OCP , */\
- { 0x4420, "int_in_flag_otpok"}, /* Clear OTP alarm , */\
- { 0x4430, "int_in_flag_ocp_alarm"}, /* Clear OCP alarm , */\
- { 0x4440, "int_in_flag_uvpok"}, /* Clear UVP alarm , */\
- { 0x4450, "int_in_flag_man_alarm_state"}, /* Clear manager alarm state , */\
- { 0x4460, "int_in_flag_tdm_error"}, /* Clear TDM error , */\
- { 0x4470, "int_in_flag_lost_clk"}, /* Clear lost clk , */\
- { 0x4480, "int_in_flag_cfma_err"}, /* Clear cfma err , */\
- { 0x4490, "int_in_flag_cfma_ack"}, /* Clear cfma ack , */\
- { 0x44a0, "int_in_flag_cf_speakererror"}, /* Clear coolflux speaker error , */\
- { 0x44b0, "int_in_flag_cold_started"}, /* Clear cold started , */\
- { 0x44c0, "int_in_flag_watchdog_reset"}, /* Clear watchdog reset , */\
- { 0x44d0, "int_in_flag_bod_vddd_nok"}, /* Clear brown out detect , */\
- { 0x44e0, "int_in_flag_lp_detect_mode1"}, /* Clear low power mode1 detect , */\
- { 0x44f0, "int_in_flag_clk_out_of_range"}, /* Clear clock out of range , */\
- { 0x4800, "int_enable_flag_por"}, /* Enable POR , */\
- { 0x4810, "int_enable_flag_bst_ocpok"}, /* Enable DCDC OCP , */\
- { 0x4820, "int_enable_flag_otpok"}, /* Enable OTP alarm , */\
- { 0x4830, "int_enable_flag_ocp_alarm"}, /* Enable OCP alarm , */\
- { 0x4840, "int_enable_flag_uvpok"}, /* Enable UVP alarm , */\
- { 0x4850, "int_enable_flag_man_alarm_state"}, /* Enable Manager Alarm state , */\
- { 0x4860, "int_enable_flag_tdm_error"}, /* Enable TDM error , */\
- { 0x4870, "int_enable_flag_lost_clk"}, /* Enable lost clk , */\
- { 0x4880, "int_enable_flag_cfma_err"}, /* Enable cfma err , */\
- { 0x4890, "int_enable_flag_cfma_ack"}, /* Enable cfma ack , */\
- { 0x48a0, "int_enable_flag_cf_speakererror"}, /* Enable coolflux speaker error , */\
- { 0x48b0, "int_enable_flag_cold_started"}, /* Enable cold started , */\
- { 0x48c0, "int_enable_flag_watchdog_reset"}, /* Enable watchdog reset , */\
- { 0x48d0, "int_enable_flag_bod_vddd_nok"}, /* Enable brown out detect , */\
- { 0x48e0, "int_enable_flag_lp_detect_mode1"}, /* Enable low power mode1 detect , */\
- { 0x48f0, "int_enable_flag_clk_out_of_range"}, /* Enable clock out of range , */\
- { 0x4c00, "int_polarity_flag_por"}, /* Polarity POR , */\
- { 0x4c10, "int_polarity_flag_bst_ocpok"}, /* Polarity DCDC OCP , */\
- { 0x4c20, "int_polarity_flag_otpok"}, /* Polarity OTP alarm , */\
- { 0x4c30, "int_polarity_flag_ocp_alarm"}, /* Polarity ocp alarm , */\
- { 0x4c40, "int_polarity_flag_uvpok"}, /* Polarity UVP alarm , */\
- { 0x4c50, "int_polarity_flag_man_alarm_state"}, /* Polarity manager alarm state , */\
- { 0x4c60, "int_polarity_flag_tdm_error"}, /* Polarity TDM error , */\
- { 0x4c70, "int_polarity_flag_lost_clk"}, /* Polarity lost clk , */\
- { 0x4c80, "int_polarity_flag_cfma_err"}, /* Polarity cfma err , */\
- { 0x4c90, "int_polarity_flag_cfma_ack"}, /* Polarity cfma ack , */\
- { 0x4ca0, "int_polarity_flag_cf_speakererror"}, /* Polarity coolflux speaker error , */\
- { 0x4cb0, "int_polarity_flag_cold_started"}, /* Polarity cold started , */\
- { 0x4cc0, "int_polarity_flag_watchdog_reset"}, /* Polarity watchdog reset , */\
- { 0x4cd0, "int_polarity_flag_bod_vddd_nok"}, /* Polarity brown out detect , */\
- { 0x4ce0, "int_polarity_flag_lp_detect_mode1"}, /* Polarity low power mode1 detect , */\
- { 0x4cf0, "int_polarity_flag_clk_out_of_range"}, /* Polarity clock out of range , */\
- { 0x5001, "vbat_prot_attack_time"}, /* Battery safeguard attack time , */\
- { 0x5023, "vbat_prot_thlevel"}, /* Battery safeguard threshold voltage level , */\
- { 0x5061, "vbat_prot_max_reduct"}, /* Battery safeguard maximum reduction , */\
- { 0x5082, "vbat_prot_release_time"}, /* Battery safeguard release time , */\
- { 0x50b1, "vbat_prot_hysterese"}, /* Battery Safeguard hysteresis , */\
- { 0x50d0, "rst_min_vbat"}, /* Reset clipper - auto clear , */\
- { 0x50e0, "sel_vbat"}, /* Battery voltage read out , */\
- { 0x50f0, "bypass_clipper"}, /* Bypass HW clipper , */\
- { 0x5130, "cf_mute"}, /* Coolflux firmware soft mute control , */\
- { 0x5187, "cf_volume"}, /* CF firmware volume control , */\
- { 0x5202, "ctrl_cc"}, /* Clip control setting , */\
- { 0x5230, "ctrl_slopectrl"}, /* Enables slope control , */\
- { 0x5240, "ctrl_slope"}, /* Slope speed setting (binary coded) , */\
- { 0x5287, "gain"}, /* Amplifier gain , */\
- { 0x5301, "dpsa_level"}, /* DPSA threshold levels , */\
- { 0x5321, "dpsa_release"}, /* DPSA Release time , */\
- { 0x5340, "clipfast"}, /* Clock selection for HW clipper for battery safeguard, */\
- { 0x5350, "bypass_lp"}, /* Bypass the low power filter inside temperature sensor, */\
- { 0x5360, "first_order_mode"}, /* Overrule to 1st order mode of control stage when clipping, */\
- { 0x5370, "icomp_engage"}, /* Engage of icomp , */\
- { 0x5380, "ctrl_kickback"}, /* Prevent double pulses of output stage , */\
- { 0x5390, "icomp_engage_overrule"}, /* To overrule the functional icomp_engage signal during validation, */\
- { 0x53a3, "ctrl_dem"}, /* Enable DEM icomp and DEM one bit dac , */\
- { 0x5400, "bypass_ctrlloop"}, /* Switch amplifier into open loop configuration , */\
- { 0x5413, "ctrl_dem_mismatch"}, /* Enable DEM icomp mismatch for testing , */\
- { 0x5452, "dpsa_drive"}, /* Drive setting (binary coded) , */\
- { 0x550a, "enbl_amp"}, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually, */\
- { 0x55b0, "enbl_engage"}, /* Enables/engage power stage and control loop , */\
- { 0x55c0, "enbl_engage_pst"}, /* Enables/engage power stage and control loop , */\
- { 0x5600, "pwm_shape"}, /* PWM shape , */\
- { 0x5614, "pwm_delay"}, /* PWM delay bits to set the delay, clockd is 1/(k*2048*fs), */\
- { 0x5660, "reclock_pwm"}, /* Reclock the PWM signal inside analog , */\
- { 0x5670, "reclock_voltsense"}, /* Reclock the voltage sense PWM signal , */\
- { 0x5680, "enbl_pwm_phase_shift"}, /* Control for PWM phase shift , */\
- { 0x5690, "sel_pwm_delay_src"}, /* Control for selection for PWM delay line source , */\
- { 0x56a1, "enbl_odd_up_even_down"}, /* Control for PWM reference sawtooth generartion , */\
- { 0x5703, "ctrl_att_dcdc"}, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */\
- { 0x5743, "ctrl_att_spkr"}, /* Total gain depending on INPLEV setting (channel 0), */\
- { 0x5781, "vamp_sel2"}, /* VAMP_OUT2 input selection , */\
- { 0x5805, "zero_lvl"}, /* Low noise gain switch zero trigger level , */\
- { 0x5861, "ctrl_fb_resistor"}, /* Select amplifier feedback resistor connection , */\
- { 0x5881, "lownoisegain_mode"}, /* Low noise gain mode control , */\
- { 0x5905, "threshold_lvl"}, /* Low noise gain switch trigger level , */\
- { 0x5965, "hold_time"}, /* Low noise mode hold time before entering into low noise mode, */\
- { 0x5a05, "lpm1_cal_offset"}, /* Low power mode1 detector ctrl cal_offset from gain module , */\
- { 0x5a65, "lpm1_zero_lvl"}, /* Low power mode1 zero crossing detection level , */\
- { 0x5ac1, "lpm1_mode"}, /* Low power mode control , */\
- { 0x5b05, "lpm1_threshold_lvl"}, /* Low power mode1 amplitude trigger level , */\
- { 0x5b65, "lpm1_hold_time"}, /* Low power mode hold time before entering into low power mode, */\
- { 0x5bc0, "disable_low_power_mode"}, /* Low power mode1 detector control , */\
- { 0x5c00, "enbl_minion"}, /* Enables minion (small) power stage , */\
- { 0x5c13, "vth_vddpvbat"}, /* Select vddp-vbat threshold signal , */\
- { 0x5c50, "lpen_vddpvbat"}, /* Select vddp-vbat filtred vs unfiltered compare , */\
- { 0x5c61, "ctrl_rfb"}, /* Feedback resistor selection - I2C direct mode , */\
- { 0x5d02, "tdm_source_mapping"}, /* TDM source mapping , */\
- { 0x5d31, "tdm_sourcea_frame_sel"}, /* Sensed value A , */\
- { 0x5d51, "tdm_sourceb_frame_sel"}, /* Sensed value B , */\
- { 0x5d71, "tdm_source0_clip_sel"}, /* Clip information (analog /digital) for source0 , */\
- { 0x5d91, "tdm_source1_clip_sel"}, /* Clip information (analog /digital) for source1 , */\
- { 0x5e02, "rst_min_vbat_delay"}, /* Delay for reseting the min_vbat value inside HW Clipper (number of Fs pulses), */\
- { 0x5e30, "rst_min_vbat_sel"}, /* Control for selecting reset signal for min_bat , */\
- { 0x5f00, "hard_mute"}, /* Hard mute - PWM , */\
- { 0x5f12, "ns_hp2ln_criterion"}, /* 0..7 zeroes at ns as threshold to swap from high_power to low_noise, */\
- { 0x5f42, "ns_ln2hp_criterion"}, /* 0..7 zeroes at ns as threshold to swap from low_noise to high_power, */\
- { 0x5f78, "spare_out"}, /* Spare out register , */\
- { 0x600f, "spare_in"}, /* Spare IN , */\
- { 0x6102, "cursense_comp_delay"}, /* Delay to allign compensation signal with current sense signal, */\
- { 0x6130, "cursense_comp_sign"}, /* Polarity of compensation for current sense , */\
- { 0x6140, "enbl_cursense_comp"}, /* Enable current sense compensation , */\
- { 0x6152, "pwms_clip_lvl"}, /* Set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
- { 0x7005, "frst_boost_voltage"}, /* First Boost Voltage Level , */\
- { 0x7065, "scnd_boost_voltage"}, /* Second Boost Voltage Level , */\
- { 0x70c3, "boost_cur"}, /* Max Coil Current , */\
- { 0x7101, "bst_slpcmplvl"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
- { 0x7120, "boost_intel"}, /* Adaptive boost mode , */\
- { 0x7130, "boost_speed"}, /* Soft ramp up/down , */\
- { 0x7140, "dcdcoff_mode"}, /* DCDC on/off , */\
- { 0x7150, "dcdc_pwmonly"}, /* DCDC PWM only mode , */\
- { 0x7160, "boost_track"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
- { 0x7170, "sel_dcdc_envelope_8fs"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
- { 0x7180, "ignore_flag_voutcomp86"}, /* Determines the maximum PWM frequency be the most efficient in relation to the Booster inductor value, */\
- { 0x7204, "boost_trip_lvl_1st"}, /* 1st adaptive boost trip levels, effective only when DCIE is set to 1, */\
- { 0x7254, "boost_trip_lvl_2nd"}, /* 2nd adaptive boost trip levels, effective only when DCIE is set to 1, */\
- { 0x72a4, "boost_trip_lvl_track"}, /* Track adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
- { 0x72f0, "enbl_trip_hyst"}, /* Enable hysteresis on booster trip levels , */\
- { 0x7304, "boost_hold_time"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
- { 0x7350, "dcdc_pfm20khz_limit"}, /* DCDC in PFM mode pwm mode is activated each 50us to force a pwm pulse, */\
- { 0x7361, "dcdc_ctrl_maxzercnt"}, /* Number of zero current flags to count before going to pfm mode, */\
- { 0x7386, "dcdc_vbat_delta_detect"}, /* Threshold before booster is reacting on a delta Vbat (in PFM mode) by temporarily switching to PWM mode, */\
- { 0x73f0, "dcdc_ignore_vbat"}, /* Ignore an increase on Vbat , */\
- { 0x7404, "bst_drive"}, /* Binary coded drive setting for boost converter power stage, */\
- { 0x7451, "bst_scalecur"}, /* For testing direct control scale current , */\
- { 0x7474, "bst_slopecur"}, /* For testing direct control slope current , */\
- { 0x74c1, "bst_slope"}, /* Boost slope speed , */\
- { 0x74e0, "bst_bypass_bstcur"}, /* Bypass control for boost current settings , */\
- { 0x74f0, "bst_bypass_bstfoldback"}, /* Bypass control for boost foldback , */\
- { 0x7500, "enbl_bst_engage"}, /* Enable power stage dcdc controller , */\
- { 0x7510, "enbl_bst_hizcom"}, /* Enable hiz comparator , */\
- { 0x7520, "enbl_bst_peakcur"}, /* Enable peak current , */\
- { 0x7530, "enbl_bst_power"}, /* Enable line of the powerstage , */\
- { 0x7540, "enbl_bst_slopecur"}, /* Enable bit of max-current dac , */\
- { 0x7550, "enbl_bst_voutcomp"}, /* Enable vout comparators , */\
- { 0x7560, "enbl_bst_voutcomp86"}, /* Enable vout-86 comparators , */\
- { 0x7570, "enbl_bst_voutcomp93"}, /* Enable vout-93 comparators , */\
- { 0x7580, "enbl_bst_windac"}, /* Enable window dac , */\
- { 0x7595, "bst_windac"}, /* For testing direct control windac , */\
- { 0x7600, "boost_alg"}, /* Control for boost adaptive loop gain , */\
- { 0x7611, "boost_loopgain"}, /* DCDC boost loopgain setting , */\
- { 0x7631, "bst_freq"}, /* DCDC boost frequency control , */\
- { 0x7650, "enbl_bst_peak2avg"}, /* Enable boost peak2avg functionality , */\
- { 0x7660, "bst_use_new_zercur_detect"}, /* Enable new zero current detection for boost control, */\
- { 0x8001, "sel_clk_cs"}, /* Current sense clock duty cycle control , */\
- { 0x8021, "micadc_speed"}, /* Current sense clock for MiCADC selection - 32/44.1/48 KHz Fs band only, */\
- { 0x8040, "cs_gain_control"}, /* Current sense gain control , */\
- { 0x8050, "cs_bypass_gc"}, /* Bypasses the CS gain correction , */\
- { 0x8060, "invertpwm"}, /* Current sense common mode feedback pwm invert control, */\
- { 0x8087, "cs_gain"}, /* Current sense gain , */\
- { 0x8105, "cs_ktemp"}, /* Current sense temperature compensation trimming (1 - VALUE*TEMP) * signal, */\
- { 0x8164, "cs_ktemp2"}, /* Second order temperature compensation coefficient , */\
- { 0x81b0, "enbl_cs_adc"}, /* Enable current sense ADC , */\
- { 0x81c0, "enbl_cs_inn1"}, /* Enable connection of current sense negative1 , */\
- { 0x81d0, "enbl_cs_inn2"}, /* Enable connection of current sense negative2 , */\
- { 0x81e0, "enbl_cs_inp1"}, /* Enable connection of current sense positive1 , */\
- { 0x81f0, "enbl_cs_inp2"}, /* Enable connection of current sense positive2 , */\
- { 0x8200, "enbl_cs_ldo"}, /* Enable current sense LDO , */\
- { 0x8210, "enbl_cs_vbatldo"}, /* Enable of current sense LDO , */\
- { 0x8220, "cs_adc_bsoinv"}, /* Bitstream inversion for current sense ADC , */\
- { 0x8231, "cs_adc_hifreq"}, /* Frequency mode current sense ADC , */\
- { 0x8250, "cs_adc_nortz"}, /* Return to zero for current sense ADC , */\
- { 0x8263, "cs_adc_offset"}, /* Micadc ADC offset setting , */\
- { 0x82a0, "cs_adc_slowdel"}, /* Select delay for current sense ADC (internal decision circuitry), */\
- { 0x82b4, "cs_adc_gain"}, /* Gain setting for current sense ADC (two's complement), */\
- { 0x8300, "cs_resonator_enable"}, /* Enable for resonator to improve SRN , */\
- { 0x8310, "cs_classd_tran_skip"}, /* Skip current sense connection during a classD amplifier transition, */\
- { 0x8320, "cs_inn_short"}, /* Short current sense negative to common mode , */\
- { 0x8330, "cs_inp_short"}, /* Short current sense positive to common mode , */\
- { 0x8340, "cs_ldo_bypass"}, /* Bypass current sense LDO , */\
- { 0x8350, "cs_ldo_pulldown"}, /* Pull down current sense LDO, only valid if enbl_cs_ldo is high, */\
- { 0x8364, "cs_ldo_voset"}, /* Current sense LDO voltage level setting (two's complement), */\
- { 0x8800, "ctrl_vs_igen_supply"}, /* Control for selecting supply for VS current generator, */\
- { 0x8810, "ctrl_vs_force_div2"}, /* Select input resistive divider gain , */\
- { 0x8820, "enbl_dc_filter"}, /* Control for enabling the DC blocking filter for voltage and current sense, */\
- { 0x8901, "volsense_pwm_sel"}, /* Voltage sense source selection control , */\
- { 0x8920, "vs_gain_control"}, /* Voltage sense gain control , */\
- { 0x8930, "vs_bypass_gc"}, /* Bypasses the VS gain correction , */\
- { 0x8940, "vs_adc_bsoinv"}, /* Bitstream inversion for voltage sense ADC , */\
- { 0x8950, "vs_adc_nortz"}, /* Return to zero for voltage sense ADC , */\
- { 0x8960, "vs_adc_slowdel"}, /* Select delay for voltage sense ADC (internal decision circuitry), */\
- { 0x8970, "vs_classd_tran_skip"}, /* Skip voltage sense connection during a classD amplifier transition, */\
- { 0x8987, "vs_gain"}, /* Voltage sense gain , */\
- { 0x8a00, "vs_inn_short"}, /* Short voltage sense negative to common mode , */\
- { 0x8a10, "vs_inp_short"}, /* Short voltage sense positive to common mode , */\
- { 0x8a20, "vs_ldo_bypass"}, /* Bypass voltage sense LDO , */\
- { 0x8a30, "vs_ldo_pulldown"}, /* Pull down voltage sense LDO, only valid if enbl_cs_ldo is high, */\
- { 0x8a44, "vs_ldo_voset"}, /* Voltage sense LDO voltage level setting (two's complement), */\
- { 0x8a90, "enbl_vs_adc"}, /* Enable voltage sense ADC , */\
- { 0x8aa0, "enbl_vs_inn1"}, /* Enable connection of voltage sense negative1 , */\
- { 0x8ab0, "enbl_vs_inn2"}, /* Enable connection of voltage sense negative2 , */\
- { 0x8ac0, "enbl_vs_inp1"}, /* Enable connection of voltage sense positive1 , */\
- { 0x8ad0, "enbl_vs_inp2"}, /* Enable connection of voltage sense positive2 , */\
- { 0x8ae0, "enbl_vs_ldo"}, /* Enable voltage sense LDO , */\
- { 0x8af0, "enbl_vs_vbatldo"}, /* Enable of voltage sense LDO , */\
- { 0x9000, "cf_rst_dsp"}, /* Reset for Coolflux DSP , */\
- { 0x9011, "cf_dmem"}, /* Target memory for CFMA using I2C interface , */\
- { 0x9030, "cf_aif"}, /* Auto increment , */\
- { 0x9040, "cf_int"}, /* Coolflux Interrupt - auto clear , */\
- { 0x9050, "cf_cgate_off"}, /* Coolflux clock gating disabling control , */\
- { 0x9080, "cf_req_cmd"}, /* Firmware event request rpc command , */\
- { 0x9090, "cf_req_reset"}, /* Firmware event request reset restart , */\
- { 0x90a0, "cf_req_mips"}, /* Firmware event request short on mips , */\
- { 0x90b0, "cf_req_mute_ready"}, /* Firmware event request mute sequence ready , */\
- { 0x90c0, "cf_req_volume_ready"}, /* Firmware event request volume ready , */\
- { 0x90d0, "cf_req_damage"}, /* Firmware event request speaker damage detected , */\
- { 0x90e0, "cf_req_calibrate_ready"}, /* Firmware event request calibration completed , */\
- { 0x90f0, "cf_req_reserved"}, /* Firmware event request reserved , */\
- { 0x910f, "cf_madd"}, /* CF memory address , */\
- { 0x920f, "cf_mema"}, /* Activate memory access , */\
- { 0x9307, "cf_err"}, /* CF error flags , */\
- { 0x9380, "cf_ack_cmd"}, /* Firmware event acknowledge rpc command , */\
- { 0x9390, "cf_ack_reset"}, /* Firmware event acknowledge reset restart , */\
- { 0x93a0, "cf_ack_mips"}, /* Firmware event acknowledge short on mips , */\
- { 0x93b0, "cf_ack_mute_ready"}, /* Firmware event acknowledge mute sequence ready , */\
- { 0x93c0, "cf_ack_volume_ready"}, /* Firmware event acknowledge volume ready , */\
- { 0x93d0, "cf_ack_damage"}, /* Firmware event acknowledge speaker damage detected, */\
- { 0x93e0, "cf_ack_calibrate_ready"}, /* Firmware event acknowledge calibration completed , */\
- { 0x93f0, "cf_ack_reserved"}, /* Firmware event acknowledge reserved , */\
- { 0xa007, "mtpkey1"}, /* KEY1 To access KEY1 protected registers 0x5A/90d (default for engineering), */\
- { 0xa107, "mtpkey2"}, /* KEY2 to access KEY2 protected registers, customer key, */\
- { 0xa200, "key01_locked"}, /* Indicates KEY1 is locked , */\
- { 0xa210, "key02_locked"}, /* Indicates KEY2 is locked , */\
- { 0xa302, "mtp_man_address_in"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
- { 0xa330, "man_copy_mtp_to_iic"}, /* Start copying single word from MTP to I2C mtp register - auto clear, */\
- { 0xa340, "man_copy_iic_to_mtp"}, /* Start copying single word from I2C mtp register to mtp - auto clear, */\
- { 0xa350, "auto_copy_mtp_to_iic"}, /* Start copying all the data from mtp to I2C mtp registers - auto clear, */\
- { 0xa360, "auto_copy_iic_to_mtp"}, /* Start copying data from I2C mtp registers to mtp - auto clear, */\
- { 0xa400, "faim_set_clkws"}, /* Sets the FaIM controller clock wait state register, */\
- { 0xa410, "faim_sel_evenrows"}, /* All even rows of the FaIM are selected, active high, */\
- { 0xa420, "faim_sel_oddrows"}, /* All odd rows of the FaIM are selected, all rows in combination with sel_evenrows, */\
- { 0xa430, "faim_program_only"}, /* Skip the erase access at wr_faim command (write-program-marginread), */\
- { 0xa440, "faim_erase_only"}, /* Skip the program access at wr_faim command (write-erase-marginread), */\
- { 0xa50f, "mtp_man_data_out_msb"}, /* MSB word of MTP manual read data , */\
- { 0xa60f, "mtp_man_data_out_lsb"}, /* LSB word of MTP manual read data , */\
- { 0xa70f, "mtp_man_data_in_msb"}, /* MSB word of write data for MTP manual write , */\
- { 0xa80f, "mtp_man_data_in_lsb"}, /* LSB word of write data for MTP manual write , */\
- { 0xb000, "bypass_ocpcounter"}, /* Bypass OCP Counter , */\
- { 0xb010, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
- { 0xb020, "bypass_ovp"}, /* Bypass OVP , */\
- { 0xb030, "bypass_uvp"}, /* Bypass UVP , */\
- { 0xb040, "bypass_otp"}, /* Bypass OTP , */\
- { 0xb050, "bypass_lost_clk"}, /* Bypass lost clock detector , */\
- { 0xb060, "ctrl_vpalarm"}, /* vpalarm (uvp ovp handling) , */\
- { 0xb070, "disable_main_ctrl_change_prot"}, /* Disable main control change protection , */\
- { 0xb087, "ocp_threshold"}, /* OCP threshold level , */\
- { 0xb108, "ext_temp"}, /* External temperature (C) , */\
- { 0xb190, "ext_temp_sel"}, /* Select temp Speaker calibration , */\
- { 0xc000, "use_direct_ctrls"}, /* Direct control to overrule several functions for testing, */\
- { 0xc010, "rst_datapath"}, /* Direct control for datapath reset , */\
- { 0xc020, "rst_cgu"}, /* Direct control for cgu reset , */\
- { 0xc038, "enbl_ref"}, /* Switch on the analog references, each part of the references can be switched on/off individually, */\
- { 0xc0c0, "use_direct_vs_ctrls"}, /* Voltage sense direct control to overrule several functions for testing, */\
- { 0xc0d0, "enbl_ringo"}, /* Enable the ring oscillator for test purpose , */\
- { 0xc0e0, "use_direct_clk_ctrl"}, /* Direct clock control to overrule several functions for testing, */\
- { 0xc0f0, "use_direct_pll_ctrl"}, /* Direct PLL control to overrule several functions for testing, */\
- { 0xc100, "enbl_tsense"}, /* Temperature sensor enable control - I2C direct mode, */\
- { 0xc110, "tsense_hibias"}, /* Bit to set the biasing in temp sensor to high , */\
- { 0xc120, "enbl_flag_vbg"}, /* Enable flagging of bandgap out of control , */\
- { 0xc20f, "abist_offset"}, /* Offset control for ABIST testing (two's complement), */\
- { 0xc300, "bypasslatch"}, /* Bypass latch , */\
- { 0xc311, "sourcea"}, /* Set OUTA to , */\
- { 0xc331, "sourceb"}, /* Set OUTB to , */\
- { 0xc350, "inverta"}, /* Invert pwma test signal , */\
- { 0xc360, "invertb"}, /* Invert pwmb test signal , */\
- { 0xc374, "pulselength"}, /* Pulse length setting test input for amplifier (clock d - k*2048*fs), */\
- { 0xc3d0, "test_abistfft_enbl"}, /* Enable ABIST with FFT on Coolflux DSP , */\
- { 0xc400, "bst_bypasslatch"}, /* Bypass latch in boost converter , */\
- { 0xc411, "bst_source"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
- { 0xc430, "bst_invertb"}, /* Invert pwmbst test signal , */\
- { 0xc444, "bst_pulselength"}, /* Pulse length setting test input for boost converter , */\
- { 0xc490, "test_bst_ctrlsthv"}, /* Test mode for boost control stage , */\
- { 0xc4a0, "test_bst_iddq"}, /* IDDQ testing in power stage of boost converter , */\
- { 0xc4b0, "test_bst_rdson"}, /* RDSON testing - boost power stage , */\
- { 0xc4c0, "test_bst_cvi"}, /* CVI testing - boost power stage , */\
- { 0xc4d0, "test_bst_ocp"}, /* Boost OCP. For old ocp (ctrl_reversebst is 0), For new ocp (ctrl_reversebst is 1), */\
- { 0xc4e0, "test_bst_sense"}, /* Test option for the sense NMOS in booster for current mode control., */\
- { 0xc500, "test_cvi"}, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */\
- { 0xc510, "test_discrete"}, /* Test function noise measurement , */\
- { 0xc520, "test_iddq"}, /* Set the power stages in iddq mode for gate stress., */\
- { 0xc530, "test_rdson"}, /* Analog BIST, switch to enable Rdson measurement , */\
- { 0xc540, "test_sdelta"}, /* Analog BIST, noise test , */\
- { 0xc550, "test_enbl_cs"}, /* Enable for digimux mode of current sense , */\
- { 0xc560, "test_enbl_vs"}, /* Enable for digimux mode of voltage sense , */\
- { 0xc570, "enbl_pwm_dcc"}, /* Enables direct control of pwm duty cycle for DCDC power stage, */\
- { 0xc583, "pwm_dcc_cnt"}, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */\
- { 0xc5c0, "enbl_ldo_stress"}, /* Enable stress of internal supply voltages powerstages, */\
- { 0xc607, "digimuxa_sel"}, /* DigimuxA input selection control routed to DATAO , */\
- { 0xc687, "digimuxb_sel"}, /* DigimuxB input selection control routed to INT , */\
- { 0xc707, "digimuxc_sel"}, /* DigimuxC input selection control routed to ADS1 , */\
- { 0xc800, "enbl_anamux1"}, /* Enable anamux1 , */\
- { 0xc810, "enbl_anamux2"}, /* Enable anamux2 , */\
- { 0xc820, "enbl_anamux3"}, /* Enable anamux3 , */\
- { 0xc830, "enbl_anamux4"}, /* Enable anamux4 , */\
- { 0xc844, "anamux1"}, /* Anamux selection control - anamux on TEST1 , */\
- { 0xc894, "anamux2"}, /* Anamux selection control - anamux on TEST2 , */\
- { 0xc903, "anamux3"}, /* Anamux selection control - anamux on TEST3 , */\
- { 0xc943, "anamux4"}, /* Anamux selection control - anamux on TEST4 , */\
- { 0xca05, "pll_seli"}, /* PLL SELI - I2C direct PLL control mode only , */\
- { 0xca64, "pll_selp"}, /* PLL SELP - I2C direct PLL control mode only , */\
- { 0xcab3, "pll_selr"}, /* PLL SELR - I2C direct PLL control mode only , */\
- { 0xcaf0, "pll_frm"}, /* PLL free running mode control; 1 in TCB direct control mode, else this control bit, */\
- { 0xcb09, "pll_ndec"}, /* PLL NDEC - I2C direct PLL control mode only , */\
- { 0xcba0, "pll_mdec_msb"}, /* MSB of PLL_mdec - I2C direct PLL control mode only, */\
- { 0xcbb0, "enbl_pll"}, /* Enables PLL in I2C direct PLL control mode only , */\
- { 0xcbc0, "enbl_osc"}, /* Enables OSC1M in I2C direct control mode only , */\
- { 0xcbd0, "pll_bypass"}, /* PLL bypass control in I2C direct PLL control mode only, */\
- { 0xcbe0, "pll_directi"}, /* PLL directi control in I2C direct PLL control mode only, */\
- { 0xcbf0, "pll_directo"}, /* PLL directo control in I2C direct PLL control mode only, */\
- { 0xcc0f, "pll_mdec_lsb"}, /* Bits 15..0 of PLL MDEC are I2C direct PLL control mode only, */\
- { 0xcd06, "pll_pdec"}, /* PLL PDEC - I2C direct PLL control mode only , */\
- { 0xce0f, "tsig_freq_lsb"}, /* Internal sinus test generator frequency control , */\
- { 0xcf02, "tsig_freq_msb"}, /* Select internal sinus test generator, frequency control msb bits, */\
- { 0xcf33, "tsig_gain"}, /* Test signal gain , */\
- { 0xd000, "adc10_reset"}, /* Reset for ADC10 - I2C direct control mode , */\
- { 0xd011, "adc10_test"}, /* Test mode selection signal for ADC10 - I2C direct control mode, */\
- { 0xd032, "adc10_sel"}, /* Select the input to convert for ADC10 - I2C direct control mode, */\
- { 0xd064, "adc10_prog_sample"}, /* ADC10 program sample setting - I2C direct control mode, */\
- { 0xd0b0, "adc10_enbl"}, /* Enable ADC10 - I2C direct control mode , */\
- { 0xd0c0, "bypass_lp_vbat"}, /* Bypass control for Low pass filter in batt sensor , */\
- { 0xd109, "data_adc10_tempbat"}, /* ADC 10 data output data for testing , */\
- { 0xd201, "clkdiv_audio_sel"}, /* Audio clock divider selection in direct clock control mode, */\
- { 0xd221, "clkdiv_muxa_sel"}, /* DCDC MUXA clock divider selection in direct clock control mode, */\
- { 0xd241, "clkdiv_muxb_sel"}, /* DCDC MUXB clock divider selection in direct clock control mode, */\
- { 0xd301, "int_ehs"}, /* Speed/load setting for INT IO cell, clk or data mode range (see SLIMMF IO datasheet), */\
- { 0xd321, "datao_ehs"}, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO datasheet), */\
- { 0xd340, "hs_mode"}, /* I2C high speed mode control , */\
- { 0xd407, "ctrl_digtoana_hidden"}, /* Spare digital to analog control bits - Hidden , */\
- { 0xd480, "enbl_clk_out_of_range"}, /* Clock out of range , */\
- { 0xd491, "sel_wdt_clk"}, /* Watch dog clock divider settings , */\
- { 0xd4b0, "inject_tsig"}, /* Control bit to switch to internal sinus test generator, */\
- { 0xd500, "source_in_testmode"}, /* TDM source in test mode (return only current and voltage sense), */\
- { 0xd510, "gainatt_feedback"}, /* Gainatt feedback to tdm , */\
- { 0xd522, "test_parametric_io"}, /* Test IO parametric , */\
- { 0xd550, "ctrl_bst_clk_lp1"}, /* Boost clock control in low power mode1 , */\
- { 0xd561, "test_spare_out1"}, /* Test spare out 1 , */\
- { 0xd580, "bst_dcmbst"}, /* DCM boost , */\
- { 0xd593, "test_spare_out2"}, /* Test spare out 2 , */\
- { 0xe00f, "sw_profile"}, /* Software profile data , */\
- { 0xe10f, "sw_vstep"}, /* Software vstep information , */\
- { 0xf000, "calibration_onetime"}, /* Calibration schedule , */\
- { 0xf010, "calibr_ron_done"}, /* Calibration Ron executed , */\
- { 0xf020, "calibr_dcdc_api_calibrate"}, /* Calibration current limit DCDC , */\
- { 0xf030, "calibr_dcdc_delta_sign"}, /* Sign bit for delta calibration current limit DCDC , */\
- { 0xf042, "calibr_dcdc_delta"}, /* Calibration delta current limit DCDC , */\
- { 0xf078, "calibr_speaker_info"}, /* Reserved space for allowing customer to store speaker information, */\
- { 0xf105, "calibr_vout_offset"}, /* DCDC offset calibration 2's complement (key1 protected), */\
- { 0xf163, "calibr_vbg_trim"}, /* Bandgap trimming control , */\
- { 0xf203, "calibr_gain"}, /* HW gain module (2's complement) , */\
- { 0xf245, "calibr_offset"}, /* Offset for amplifier, HW gain module (2's complement), */\
- { 0xf307, "calibr_gain_vs"}, /* Voltage sense gain , */\
- { 0xf387, "calibr_gain_cs"}, /* Current sense gain (signed two's complement format), */\
- { 0xf40f, "mtpdata4"}, /* MTP4 data , */\
- { 0xf50f, "calibr_R25C"}, /* Ron resistance of speaker coil , */\
- { 0xf60f, "mtpdata6"}, /* MTP6 data , */\
- { 0xf706, "ctrl_offset_a"}, /* Offset of level shifter A , */\
- { 0xf786, "ctrl_offset_b"}, /* Offset of amplifier level shifter B , */\
- { 0xf806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
- { 0xf870, "htol_iic_addr_en"}, /* HTOL I2C address enable control , */\
- { 0xf884, "calibr_temp_offset"}, /* Temperature offset 2's compliment (key1 protected), */\
- { 0xf8d2, "calibr_temp_gain"}, /* Temperature gain 2's compliment (key1 protected) , */\
- { 0xf900, "mtp_lock_dcdcoff_mode"}, /* Disable functionality of dcdcoff_mode bit , */\
- { 0xf910, "mtp_lock_enbl_coolflux"}, /* Disable functionality of enbl_coolflux bit , */\
- { 0xf920, "mtp_lock_bypass_clipper"}, /* Disable function bypass_clipper , */\
- { 0xf930, "mtp_enbl_pwm_delay_clock_gating"}, /* PWM delay clock auto gating , */\
- { 0xf940, "mtp_enbl_ocp_clock_gating"}, /* OCP clock auto gating , */\
- { 0xf950, "mtp_gate_cgu_clock_for_test"}, /* CGU test clock control , */\
- { 0xf987, "type_bits_fw"}, /* MTP control for firmware features - See Firmware I2C API document for details, */\
- { 0xfa0f, "mtpdataA"}, /* MTPdataA , */\
- { 0xfb0f, "mtpdataB"}, /* MTPdataB , */\
- { 0xfc0f, "mtpdataC"}, /* MTPdataC , */\
- { 0xfd0f, "mtpdataD"}, /* MTPdataD , */\
- { 0xfe0f, "mtpdataE"}, /* MTPdataE , */\
- { 0xff07, "calibr_osc_delta_ndiv"}, /* Calibration data for OSC1M, signed number representation, */\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-
-enum tfa9894_irq {
- tfa9894_irq_max = -1,
- tfa9894_irq_all = -1 /* all irqs */};
-
-#define TFA9894_IRQ_NAMETABLE static tfaIrqName_t Tfa9894IrqNames[]= {\
-};
-#endif /* _TFA9894_TFAFIELDNAMES_H */
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _TFA9894_TFAFIELDNAMES_H
+#define _TFA9894_TFAFIELDNAMES_H
+
+
+#define TFA9894_I2CVERSION 17.0
+
+typedef enum nxpTfa9894BfEnumList {
+ TFA9894_BF_PWDN = 0x0000, /*!< Powerdown control */
+ TFA9894_BF_I2CR = 0x0010, /*!< I2C Reset - Auto clear */
+ TFA9894_BF_CFE = 0x0020, /*!< Enable CoolFlux DSP */
+ TFA9894_BF_AMPE = 0x0030, /*!< Enable Amplifier */
+ TFA9894_BF_DCA = 0x0040, /*!< Enable DCDC Boost converter */
+ TFA9894_BF_SBSL = 0x0050, /*!< Coolflux configured */
+ TFA9894_BF_AMPC = 0x0060, /*!< CoolFlux control over amplifier */
+ TFA9894_BF_INTP = 0x0071, /*!< Interrupt config */
+ TFA9894_BF_FSSSEL = 0x0090, /*!< Audio sample reference */
+ TFA9894_BF_BYPOCP = 0x00a0, /*!< Bypass OCP */
+ TFA9894_BF_TSTOCP = 0x00b0, /*!< OCP testing control */
+ TFA9894_BF_BSSS = 0x00c0, /*!< Vbat protection steepness */
+ TFA9894_BF_HPFBYP = 0x00d0, /*!< Bypass High Pass Filter */
+ TFA9894_BF_DPSA = 0x00e0, /*!< Enable DPSA */
+ TFA9894_BF_AMPINSEL = 0x0101, /*!< Amplifier input selection */
+ TFA9894_BF_MANSCONF = 0x0120, /*!< Device I2C settings configured */
+ TFA9894_BF_MANCOLD = 0x0130, /*!< Execute cold start */
+ TFA9894_BF_MANROBOD = 0x0140, /*!< Reaction on BOD */
+ TFA9894_BF_BODE = 0x0150, /*!< Enable BOD (only in direct control mode) */
+ TFA9894_BF_BODHYS = 0x0160, /*!< Enable Hysteresis of BOD */
+ TFA9894_BF_BODFILT = 0x0171, /*!< BOD filter */
+ TFA9894_BF_BODTHLVL = 0x0191, /*!< BOD threshold */
+ TFA9894_BF_MUTETO = 0x01b0, /*!< Time out SB mute sequence */
+ TFA9894_BF_MANWDE = 0x01c0, /*!< Watchdog enable */
+ TFA9894_BF_OPENMTP = 0x01e0, /*!< Control for FAIM protection */
+ TFA9894_BF_FAIMVBGOVRRL = 0x01f0, /*!< Overrule the enabling of VBG for faim erase/write access */
+ TFA9894_BF_AUDFS = 0x0203, /*!< Audio sample rate Fs */
+ TFA9894_BF_INPLEV = 0x0240, /*!< TDM output attenuation */
+ TFA9894_BF_FRACTDEL = 0x0255, /*!< Current sense fractional delay */
+ TFA9894_BF_TDMPRES = 0x02b1, /*!< Control for HW manager */
+ TFA9894_BF_AMPOCRT = 0x02d2, /*!< Amplifier on-off criteria for shutdown */
+ TFA9894_BF_REV = 0x030f, /*!< Revision info */
+ TFA9894_BF_REFCKEXT = 0x0401, /*!< PLL external reference clock */
+ TFA9894_BF_REFCKSEL = 0x0420, /*!< PLL internal reference clock */
+ TFA9894_BF_MCLKSEL = 0x0432, /*!< Master Clock Selection */
+ TFA9894_BF_MANAOOSC = 0x0460, /*!< Internal OSC1M off at PWDN */
+ TFA9894_BF_ACKCLDDIS = 0x0470, /*!< Automatic PLL reference clock selection for cold start */
+ TFA9894_BF_SPKSSEN = 0x0510, /*!< Enable speaker sub-system */
+ TFA9894_BF_MTPSSEN = 0x0520, /*!< Enable FAIM sub-system */
+ TFA9894_BF_WDTCLKEN = 0x0530, /*!< Enable Coolflux watchdog clock */
+ TFA9894_BF_VDDS = 0x1000, /*!< POR */
+ TFA9894_BF_PLLS = 0x1010, /*!< PLL Lock */
+ TFA9894_BF_OTDS = 0x1020, /*!< OTP alarm */
+ TFA9894_BF_OVDS = 0x1030, /*!< OVP alarm */
+ TFA9894_BF_UVDS = 0x1040, /*!< UVP alarm */
+ TFA9894_BF_OCDS = 0x1050, /*!< OCP amplifier (sticky register, clear on read) */
+ TFA9894_BF_CLKS = 0x1060, /*!< Clocks stable */
+ TFA9894_BF_MTPB = 0x1070, /*!< MTP busy */
+ TFA9894_BF_NOCLK = 0x1080, /*!< Lost clock */
+ TFA9894_BF_ACS = 0x1090, /*!< Cold Start */
+ TFA9894_BF_WDS = 0x10a0, /*!< Watchdog */
+ TFA9894_BF_SWS = 0x10b0, /*!< Amplifier engage */
+ TFA9894_BF_AMPS = 0x10c0, /*!< Amplifier enable */
+ TFA9894_BF_AREFS = 0x10d0, /*!< References enable */
+ TFA9894_BF_ADCCR = 0x10e0, /*!< Control ADC */
+ TFA9894_BF_BODNOK = 0x10f0, /*!< BOD Flag - VDD NOT OK */
+ TFA9894_BF_DCIL = 0x1100, /*!< DCDC current limiting */
+ TFA9894_BF_DCDCA = 0x1110, /*!< DCDC active (sticky register, clear on read) */
+ TFA9894_BF_DCOCPOK = 0x1120, /*!< DCDC OCP nmos (sticky register, clear on read) */
+ TFA9894_BF_DCHVBAT = 0x1140, /*!< DCDC level 1x */
+ TFA9894_BF_DCH114 = 0x1150, /*!< DCDC level 1.14x */
+ TFA9894_BF_DCH107 = 0x1160, /*!< DCDC level 1.07x */
+ TFA9894_BF_SPKS = 0x1170, /*!< Speaker status */
+ TFA9894_BF_CLKOOR = 0x1180, /*!< External clock status */
+ TFA9894_BF_MANALARM = 0x1190, /*!< Alarm state */
+ TFA9894_BF_TDMERR = 0x11a0, /*!< TDM error */
+ TFA9894_BF_TDMLUTER = 0x11b0, /*!< TDM lookup table error */
+ TFA9894_BF_OCPOAP = 0x1200, /*!< OCPOK pmos A */
+ TFA9894_BF_OCPOAN = 0x1210, /*!< OCPOK nmos A */
+ TFA9894_BF_OCPOBP = 0x1220, /*!< OCPOK pmos B */
+ TFA9894_BF_OCPOBN = 0x1230, /*!< OCPOK nmos B */
+ TFA9894_BF_CLIPS = 0x1240, /*!< Amplifier clipping */
+ TFA9894_BF_MANMUTE = 0x1250, /*!< Audio mute sequence */
+ TFA9894_BF_MANOPER = 0x1260, /*!< Device in Operating state */
+ TFA9894_BF_LP1 = 0x1270, /*!< Low power MODE1 detection */
+ TFA9894_BF_LA = 0x1280, /*!< Low amplitude detection */
+ TFA9894_BF_VDDPH = 0x1290, /*!< VDDP greater than VBAT flag */
+ TFA9894_BF_TDMSTAT = 0x1402, /*!< TDM Status bits */
+ TFA9894_BF_MANSTATE = 0x1433, /*!< Device Manager status */
+ TFA9894_BF_DCMODE = 0x14b1, /*!< DCDC mode status bits */
+ TFA9894_BF_BATS = 0x1509, /*!< Battery voltage (V) */
+ TFA9894_BF_TEMPS = 0x1608, /*!< IC Temperature (C) */
+ TFA9894_BF_VDDPS = 0x1709, /*!< IC VDDP voltage (1023*VDDP/13V) */
+ TFA9894_BF_TDME = 0x2000, /*!< Enable interface */
+ TFA9894_BF_TDMSPKE = 0x2010, /*!< Control audio tdm channel in sink0 */
+ TFA9894_BF_TDMDCE = 0x2020, /*!< Control audio tdm channel in sink1 */
+ TFA9894_BF_TDMCSE = 0x2030, /*!< Source 0 enable */
+ TFA9894_BF_TDMVSE = 0x2040, /*!< Source 1 enable */
+ TFA9894_BF_TDMCFE = 0x2050, /*!< Source 2 enable */
+ TFA9894_BF_TDMCF2E = 0x2060, /*!< Source 3 enable */
+ TFA9894_BF_TDMCLINV = 0x2070, /*!< Reception data to BCK clock */
+ TFA9894_BF_TDMFSPOL = 0x2080, /*!< FS polarity */
+ TFA9894_BF_TDMDEL = 0x2090, /*!< Data delay to FS */
+ TFA9894_BF_TDMADJ = 0x20a0, /*!< Data adjustment */
+ TFA9894_BF_TDMOOMP = 0x20b1, /*!< Received audio compression */
+ TFA9894_BF_TDMNBCK = 0x2103, /*!< TDM NBCK - Bit clock to FS ratio */
+ TFA9894_BF_TDMFSLN = 0x2143, /*!< FS length (master mode only) */
+ TFA9894_BF_TDMSLOTS = 0x2183, /*!< N-slots in Frame */
+ TFA9894_BF_TDMTXDFO = 0x21c1, /*!< Format unused bits */
+ TFA9894_BF_TDMTXUS = 0x21e1, /*!< Format unused slots DATAO */
+ TFA9894_BF_TDMSLLN = 0x2204, /*!< N-bits in slot */
+ TFA9894_BF_TDMBRMG = 0x2254, /*!< N-bits remaining */
+ TFA9894_BF_TDMSSIZE = 0x22a4, /*!< Sample size per slot */
+ TFA9894_BF_TDMSPKS = 0x2303, /*!< TDM slot for sink 0 */
+ TFA9894_BF_TDMDCS = 0x2343, /*!< TDM slot for sink 1 */
+ TFA9894_BF_TDMCFSEL = 0x2381, /*!< TDM Source 2 data selection */
+ TFA9894_BF_TDMCF2SEL = 0x23a1, /*!< TDM Source 3 data selection */
+ TFA9894_BF_TDMCSS = 0x2403, /*!< Slot Position of source 0 data */
+ TFA9894_BF_TDMVSS = 0x2443, /*!< Slot Position of source 1 data */
+ TFA9894_BF_TDMCFS = 0x2483, /*!< Slot Position of source 2 data */
+ TFA9894_BF_TDMCF2S = 0x24c3, /*!< Slot Position of source 3 data */
+ TFA9894_BF_ISTVDDS = 0x4000, /*!< Status POR */
+ TFA9894_BF_ISTBSTOC = 0x4010, /*!< Status DCDC OCP */
+ TFA9894_BF_ISTOTDS = 0x4020, /*!< Status OTP alarm */
+ TFA9894_BF_ISTOCPR = 0x4030, /*!< Status OCP alarm */
+ TFA9894_BF_ISTUVDS = 0x4040, /*!< Status UVP alarm */
+ TFA9894_BF_ISTMANALARM = 0x4050, /*!< Status manager alarm state */
+ TFA9894_BF_ISTTDMER = 0x4060, /*!< Status TDM error */
+ TFA9894_BF_ISTNOCLK = 0x4070, /*!< Status lost clock */
+ TFA9894_BF_ISTCFMER = 0x4080, /*!< Status cfma error */
+ TFA9894_BF_ISTCFMAC = 0x4090, /*!< Status cfma ack */
+ TFA9894_BF_ISTSPKS = 0x40a0, /*!< Status coolflux speaker error */
+ TFA9894_BF_ISTACS = 0x40b0, /*!< Status cold started */
+ TFA9894_BF_ISTWDS = 0x40c0, /*!< Status watchdog reset */
+ TFA9894_BF_ISTBODNOK = 0x40d0, /*!< Status brown out detect */
+ TFA9894_BF_ISTLP1 = 0x40e0, /*!< Status low power mode1 detect */
+ TFA9894_BF_ISTCLKOOR = 0x40f0, /*!< Status clock out of range */
+ TFA9894_BF_ICLVDDS = 0x4400, /*!< Clear POR */
+ TFA9894_BF_ICLBSTOC = 0x4410, /*!< Clear DCDC OCP */
+ TFA9894_BF_ICLOTDS = 0x4420, /*!< Clear OTP alarm */
+ TFA9894_BF_ICLOCPR = 0x4430, /*!< Clear OCP alarm */
+ TFA9894_BF_ICLUVDS = 0x4440, /*!< Clear UVP alarm */
+ TFA9894_BF_ICLMANALARM = 0x4450, /*!< Clear manager alarm state */
+ TFA9894_BF_ICLTDMER = 0x4460, /*!< Clear TDM error */
+ TFA9894_BF_ICLNOCLK = 0x4470, /*!< Clear lost clk */
+ TFA9894_BF_ICLCFMER = 0x4480, /*!< Clear cfma err */
+ TFA9894_BF_ICLCFMAC = 0x4490, /*!< Clear cfma ack */
+ TFA9894_BF_ICLSPKS = 0x44a0, /*!< Clear coolflux speaker error */
+ TFA9894_BF_ICLACS = 0x44b0, /*!< Clear cold started */
+ TFA9894_BF_ICLWDS = 0x44c0, /*!< Clear watchdog reset */
+ TFA9894_BF_ICLBODNOK = 0x44d0, /*!< Clear brown out detect */
+ TFA9894_BF_ICLLP1 = 0x44e0, /*!< Clear low power mode1 detect */
+ TFA9894_BF_ICLCLKOOR = 0x44f0, /*!< Clear clock out of range */
+ TFA9894_BF_IEVDDS = 0x4800, /*!< Enable POR */
+ TFA9894_BF_IEBSTOC = 0x4810, /*!< Enable DCDC OCP */
+ TFA9894_BF_IEOTDS = 0x4820, /*!< Enable OTP alarm */
+ TFA9894_BF_IEOCPR = 0x4830, /*!< Enable OCP alarm */
+ TFA9894_BF_IEUVDS = 0x4840, /*!< Enable UVP alarm */
+ TFA9894_BF_IEMANALARM = 0x4850, /*!< Enable Manager Alarm state */
+ TFA9894_BF_IETDMER = 0x4860, /*!< Enable TDM error */
+ TFA9894_BF_IENOCLK = 0x4870, /*!< Enable lost clk */
+ TFA9894_BF_IECFMER = 0x4880, /*!< Enable cfma err */
+ TFA9894_BF_IECFMAC = 0x4890, /*!< Enable cfma ack */
+ TFA9894_BF_IESPKS = 0x48a0, /*!< Enable coolflux speaker error */
+ TFA9894_BF_IEACS = 0x48b0, /*!< Enable cold started */
+ TFA9894_BF_IEWDS = 0x48c0, /*!< Enable watchdog reset */
+ TFA9894_BF_IEBODNOK = 0x48d0, /*!< Enable brown out detect */
+ TFA9894_BF_IELP1 = 0x48e0, /*!< Enable low power mode1 detect */
+ TFA9894_BF_IECLKOOR = 0x48f0, /*!< Enable clock out of range */
+ TFA9894_BF_IPOVDDS = 0x4c00, /*!< Polarity POR */
+ TFA9894_BF_IPOBSTOC = 0x4c10, /*!< Polarity DCDC OCP */
+ TFA9894_BF_IPOOTDS = 0x4c20, /*!< Polarity OTP alarm */
+ TFA9894_BF_IPOOCPR = 0x4c30, /*!< Polarity ocp alarm */
+ TFA9894_BF_IPOUVDS = 0x4c40, /*!< Polarity UVP alarm */
+ TFA9894_BF_IPOMANALARM = 0x4c50, /*!< Polarity manager alarm state */
+ TFA9894_BF_IPOTDMER = 0x4c60, /*!< Polarity TDM error */
+ TFA9894_BF_IPONOCLK = 0x4c70, /*!< Polarity lost clk */
+ TFA9894_BF_IPOCFMER = 0x4c80, /*!< Polarity cfma err */
+ TFA9894_BF_IPOCFMAC = 0x4c90, /*!< Polarity cfma ack */
+ TFA9894_BF_IPOSPKS = 0x4ca0, /*!< Polarity coolflux speaker error */
+ TFA9894_BF_IPOACS = 0x4cb0, /*!< Polarity cold started */
+ TFA9894_BF_IPOWDS = 0x4cc0, /*!< Polarity watchdog reset */
+ TFA9894_BF_IPOBODNOK = 0x4cd0, /*!< Polarity brown out detect */
+ TFA9894_BF_IPOLP1 = 0x4ce0, /*!< Polarity low power mode1 detect */
+ TFA9894_BF_IPOCLKOOR = 0x4cf0, /*!< Polarity clock out of range */
+ TFA9894_BF_BSSCR = 0x5001, /*!< Battery safeguard attack time */
+ TFA9894_BF_BSST = 0x5023, /*!< Battery safeguard threshold voltage level */
+ TFA9894_BF_BSSRL = 0x5061, /*!< Battery safeguard maximum reduction */
+ TFA9894_BF_BSSRR = 0x5082, /*!< Battery safeguard release time */
+ TFA9894_BF_BSSHY = 0x50b1, /*!< Battery Safeguard hysteresis */
+ TFA9894_BF_BSSR = 0x50e0, /*!< Battery voltage read out */
+ TFA9894_BF_BSSBY = 0x50f0, /*!< Bypass HW clipper */
+ TFA9894_BF_CFSM = 0x5130, /*!< Coolflux firmware soft mute control */
+ TFA9894_BF_VOL = 0x5187, /*!< CF firmware volume control */
+ TFA9894_BF_CLIPCTRL = 0x5202, /*!< Clip control setting */
+ TFA9894_BF_SLOPEE = 0x5230, /*!< Enables slope control */
+ TFA9894_BF_SLOPESET = 0x5240, /*!< Slope speed setting (binary coded) */
+ TFA9894_BF_AMPGAIN = 0x5287, /*!< Amplifier gain */
+ TFA9894_BF_TDMDCG = 0x5703, /*!< Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE) */
+ TFA9894_BF_TDMSPKG = 0x5743, /*!< Total gain depending on INPLEV setting (channel 0) */
+ TFA9894_BF_DCINSEL = 0x5781, /*!< VAMP_OUT2 input selection */
+ TFA9894_BF_LNMODE = 0x5881, /*!< Low noise gain mode control */
+ TFA9894_BF_LPM1MODE = 0x5ac1, /*!< Low power mode control */
+ TFA9894_BF_TDMSRCMAP = 0x5d02, /*!< TDM source mapping */
+ TFA9894_BF_TDMSRCAS = 0x5d31, /*!< Sensed value A */
+ TFA9894_BF_TDMSRCBS = 0x5d51, /*!< Sensed value B */
+ TFA9894_BF_TDMSRCACLIP = 0x5d71, /*!< Clip information (analog /digital) for source0 */
+ TFA9894_BF_TDMSRCBCLIP = 0x5d91, /*!< Clip information (analog /digital) for source1 */
+ TFA9894_BF_DELCURCOMP = 0x6102, /*!< Delay to allign compensation signal with current sense signal */
+ TFA9894_BF_SIGCURCOMP = 0x6130, /*!< Polarity of compensation for current sense */
+ TFA9894_BF_ENCURCOMP = 0x6140, /*!< Enable current sense compensation */
+ TFA9894_BF_LVLCLPPWM = 0x6152, /*!< Set the amount of pwm pulse that may be skipped before clip-flag is triggered */
+ TFA9894_BF_DCVOF = 0x7005, /*!< First Boost Voltage Level */
+ TFA9894_BF_DCVOS = 0x7065, /*!< Second Boost Voltage Level */
+ TFA9894_BF_DCMCC = 0x70c3, /*!< Max Coil Current */
+ TFA9894_BF_DCCV = 0x7101, /*!< Slope compensation current, represents LxF (inductance x frequency) value */
+ TFA9894_BF_DCIE = 0x7120, /*!< Adaptive boost mode */
+ TFA9894_BF_DCSR = 0x7130, /*!< Soft ramp up/down */
+ TFA9894_BF_DCDIS = 0x7140, /*!< DCDC on/off */
+ TFA9894_BF_DCPWM = 0x7150, /*!< DCDC PWM only mode */
+ TFA9894_BF_DCTRACK = 0x7160, /*!< Boost algorithm selection, effective only when boost_intelligent is set to 1 */
+ TFA9894_BF_DCENVSEL = 0x7170, /*!< Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1 */
+ TFA9894_BF_DCTRIP = 0x7204, /*!< 1st adaptive boost trip levels, effective only when DCIE is set to 1 */
+ TFA9894_BF_DCTRIP2 = 0x7254, /*!< 2nd adaptive boost trip levels, effective only when DCIE is set to 1 */
+ TFA9894_BF_DCTRIPT = 0x72a4, /*!< Track adaptive boost trip levels, effective only when boost_intelligent is set to 1 */
+ TFA9894_BF_DCTRIPHYSTE = 0x72f0, /*!< Enable hysteresis on booster trip levels */
+ TFA9894_BF_DCHOLD = 0x7304, /*!< Hold time for DCDC booster, effective only when boost_intelligent is set to 1 */
+ TFA9894_BF_RST = 0x9000, /*!< Reset for Coolflux DSP */
+ TFA9894_BF_DMEM = 0x9011, /*!< Target memory for CFMA using I2C interface */
+ TFA9894_BF_AIF = 0x9030, /*!< Auto increment */
+ TFA9894_BF_CFINT = 0x9040, /*!< Coolflux Interrupt - auto clear */
+ TFA9894_BF_CFCGATE = 0x9050, /*!< Coolflux clock gating disabling control */
+ TFA9894_BF_REQCMD = 0x9080, /*!< Firmware event request rpc command */
+ TFA9894_BF_REQRST = 0x9090, /*!< Firmware event request reset restart */
+ TFA9894_BF_REQMIPS = 0x90a0, /*!< Firmware event request short on mips */
+ TFA9894_BF_REQMUTED = 0x90b0, /*!< Firmware event request mute sequence ready */
+ TFA9894_BF_REQVOL = 0x90c0, /*!< Firmware event request volume ready */
+ TFA9894_BF_REQDMG = 0x90d0, /*!< Firmware event request speaker damage detected */
+ TFA9894_BF_REQCAL = 0x90e0, /*!< Firmware event request calibration completed */
+ TFA9894_BF_REQRSV = 0x90f0, /*!< Firmware event request reserved */
+ TFA9894_BF_MADD = 0x910f, /*!< CF memory address */
+ TFA9894_BF_MEMA = 0x920f, /*!< Activate memory access */
+ TFA9894_BF_ERR = 0x9307, /*!< CF error flags */
+ TFA9894_BF_ACKCMD = 0x9380, /*!< Firmware event acknowledge rpc command */
+ TFA9894_BF_ACKRST = 0x9390, /*!< Firmware event acknowledge reset restart */
+ TFA9894_BF_ACKMIPS = 0x93a0, /*!< Firmware event acknowledge short on mips */
+ TFA9894_BF_ACKMUTED = 0x93b0, /*!< Firmware event acknowledge mute sequence ready */
+ TFA9894_BF_ACKVOL = 0x93c0, /*!< Firmware event acknowledge volume ready */
+ TFA9894_BF_ACKDMG = 0x93d0, /*!< Firmware event acknowledge speaker damage detected */
+ TFA9894_BF_ACKCAL = 0x93e0, /*!< Firmware event acknowledge calibration completed */
+ TFA9894_BF_ACKRSV = 0x93f0, /*!< Firmware event acknowledge reserved */
+ TFA9894_BF_MTPK = 0xa107, /*!< KEY2 to access KEY2 protected registers, customer key */
+ TFA9894_BF_KEY1LOCKED = 0xa200, /*!< Indicates KEY1 is locked */
+ TFA9894_BF_KEY2LOCKED = 0xa210, /*!< Indicates KEY2 is locked */
+ TFA9894_BF_CMTPI = 0xa350, /*!< Start copying all the data from mtp to I2C mtp registers - auto clear */
+ TFA9894_BF_CIMTP = 0xa360, /*!< Start copying data from I2C mtp registers to mtp - auto clear */
+ TFA9894_BF_MTPRDMSB = 0xa50f, /*!< MSB word of MTP manual read data */
+ TFA9894_BF_MTPRDLSB = 0xa60f, /*!< LSB word of MTP manual read data */
+ TFA9894_BF_EXTTS = 0xb108, /*!< External temperature (C) */
+ TFA9894_BF_TROS = 0xb190, /*!< Select temp Speaker calibration */
+ TFA9894_BF_SWPROFIL = 0xe00f, /*!< Software profile data */
+ TFA9894_BF_SWVSTEP = 0xe10f, /*!< Software vstep information */
+ TFA9894_BF_MTPOTC = 0xf000, /*!< Calibration schedule */
+ TFA9894_BF_MTPEX = 0xf010, /*!< Calibration Ron executed */
+ TFA9894_BF_DCMCCAPI = 0xf020, /*!< Calibration current limit DCDC */
+ TFA9894_BF_DCMCCSB = 0xf030, /*!< Sign bit for delta calibration current limit DCDC */
+ TFA9894_BF_USERDEF = 0xf042, /*!< Calibration delta current limit DCDC */
+ TFA9894_BF_CUSTINFO = 0xf078, /*!< Reserved space for allowing customer to store speaker information */
+ TFA9894_BF_R25C = 0xf50f, /*!< Ron resistance of speaker coil */
+} nxpTfa9894BfEnumList_t;
+#define TFA9894_NAMETABLE static tfaBfName_t Tfa9894DatasheetNames[] = {\
+ { 0x0, "PWDN"}, /* Powerdown control , */\
+ { 0x10, "I2CR"}, /* I2C Reset - Auto clear , */\
+ { 0x20, "CFE"}, /* Enable CoolFlux DSP , */\
+ { 0x30, "AMPE"}, /* Enable Amplifier , */\
+ { 0x40, "DCA"}, /* Enable DCDC Boost converter , */\
+ { 0x50, "SBSL"}, /* Coolflux configured , */\
+ { 0x60, "AMPC"}, /* CoolFlux control over amplifier , */\
+ { 0x71, "INTP"}, /* Interrupt config , */\
+ { 0x90, "FSSSEL"}, /* Audio sample reference , */\
+ { 0xa0, "BYPOCP"}, /* Bypass OCP , */\
+ { 0xb0, "TSTOCP"}, /* OCP testing control , */\
+ { 0xc0, "BSSS"}, /* Vbat protection steepness , */\
+ { 0xd0, "HPFBYP"}, /* Bypass High Pass Filter , */\
+ { 0xe0, "DPSA"}, /* Enable DPSA , */\
+ { 0x101, "AMPINSEL"}, /* Amplifier input selection , */\
+ { 0x120, "MANSCONF"}, /* Device I2C settings configured , */\
+ { 0x130, "MANCOLD"}, /* Execute cold start , */\
+ { 0x140, "MANROBOD"}, /* Reaction on BOD , */\
+ { 0x150, "BODE"}, /* Enable BOD (only in direct control mode) , */\
+ { 0x160, "BODHYS"}, /* Enable Hysteresis of BOD , */\
+ { 0x171, "BODFILT"}, /* BOD filter , */\
+ { 0x191, "BODTHLVL"}, /* BOD threshold , */\
+ { 0x1b0, "MUTETO"}, /* Time out SB mute sequence , */\
+ { 0x1c0, "MANWDE"}, /* Watchdog enable , */\
+ { 0x1e0, "OPENMTP"}, /* Control for FAIM protection , */\
+ { 0x1f0, "FAIMVBGOVRRL"}, /* Overrule the enabling of VBG for faim erase/write access, */\
+ { 0x203, "AUDFS"}, /* Audio sample rate Fs , */\
+ { 0x240, "INPLEV"}, /* TDM output attenuation , */\
+ { 0x255, "FRACTDEL"}, /* Current sense fractional delay , */\
+ { 0x2b1, "TDMPRES"}, /* Control for HW manager , */\
+ { 0x2d2, "AMPOCRT"}, /* Amplifier on-off criteria for shutdown , */\
+ { 0x30f, "REV"}, /* Revision info , */\
+ { 0x401, "REFCKEXT"}, /* PLL external reference clock , */\
+ { 0x420, "REFCKSEL"}, /* PLL internal reference clock , */\
+ { 0x432, "MCLKSEL"}, /* Master Clock Selection , */\
+ { 0x460, "MANAOOSC"}, /* Internal OSC1M off at PWDN , */\
+ { 0x470, "ACKCLDDIS"}, /* Automatic PLL reference clock selection for cold start, */\
+ { 0x510, "SPKSSEN"}, /* Enable speaker sub-system , */\
+ { 0x520, "MTPSSEN"}, /* Enable FAIM sub-system , */\
+ { 0x530, "WDTCLKEN"}, /* Enable Coolflux watchdog clock , */\
+ { 0x1000, "VDDS"}, /* POR , */\
+ { 0x1010, "PLLS"}, /* PLL Lock , */\
+ { 0x1020, "OTDS"}, /* OTP alarm , */\
+ { 0x1030, "OVDS"}, /* OVP alarm , */\
+ { 0x1040, "UVDS"}, /* UVP alarm , */\
+ { 0x1050, "OCDS"}, /* OCP amplifier (sticky register, clear on read) , */\
+ { 0x1060, "CLKS"}, /* Clocks stable , */\
+ { 0x1070, "MTPB"}, /* MTP busy , */\
+ { 0x1080, "NOCLK"}, /* Lost clock , */\
+ { 0x1090, "ACS"}, /* Cold Start , */\
+ { 0x10a0, "WDS"}, /* Watchdog , */\
+ { 0x10b0, "SWS"}, /* Amplifier engage , */\
+ { 0x10c0, "AMPS"}, /* Amplifier enable , */\
+ { 0x10d0, "AREFS"}, /* References enable , */\
+ { 0x10e0, "ADCCR"}, /* Control ADC , */\
+ { 0x10f0, "BODNOK"}, /* BOD Flag - VDD NOT OK , */\
+ { 0x1100, "DCIL"}, /* DCDC current limiting , */\
+ { 0x1110, "DCDCA"}, /* DCDC active (sticky register, clear on read) , */\
+ { 0x1120, "DCOCPOK"}, /* DCDC OCP nmos (sticky register, clear on read) , */\
+ { 0x1140, "DCHVBAT"}, /* DCDC level 1x , */\
+ { 0x1150, "DCH114"}, /* DCDC level 1.14x , */\
+ { 0x1160, "DCH107"}, /* DCDC level 1.07x , */\
+ { 0x1170, "SPKS"}, /* Speaker status , */\
+ { 0x1180, "CLKOOR"}, /* External clock status , */\
+ { 0x1190, "MANALARM"}, /* Alarm state , */\
+ { 0x11a0, "TDMERR"}, /* TDM error , */\
+ { 0x11b0, "TDMLUTER"}, /* TDM lookup table error , */\
+ { 0x1200, "OCPOAP"}, /* OCPOK pmos A , */\
+ { 0x1210, "OCPOAN"}, /* OCPOK nmos A , */\
+ { 0x1220, "OCPOBP"}, /* OCPOK pmos B , */\
+ { 0x1230, "OCPOBN"}, /* OCPOK nmos B , */\
+ { 0x1240, "CLIPS"}, /* Amplifier clipping , */\
+ { 0x1250, "MANMUTE"}, /* Audio mute sequence , */\
+ { 0x1260, "MANOPER"}, /* Device in Operating state , */\
+ { 0x1270, "LP1"}, /* Low power MODE1 detection , */\
+ { 0x1280, "LA"}, /* Low amplitude detection , */\
+ { 0x1290, "VDDPH"}, /* VDDP greater than VBAT flag , */\
+ { 0x1402, "TDMSTAT"}, /* TDM Status bits , */\
+ { 0x1433, "MANSTATE"}, /* Device Manager status , */\
+ { 0x14b1, "DCMODE"}, /* DCDC mode status bits , */\
+ { 0x1509, "BATS"}, /* Battery voltage (V) , */\
+ { 0x1608, "TEMPS"}, /* IC Temperature (C) , */\
+ { 0x1709, "VDDPS"}, /* IC VDDP voltage (1023*VDDP/13V) , */\
+ { 0x2000, "TDME"}, /* Enable interface , */\
+ { 0x2010, "TDMSPKE"}, /* Control audio tdm channel in sink0 , */\
+ { 0x2020, "TDMDCE"}, /* Control audio tdm channel in sink1 , */\
+ { 0x2030, "TDMCSE"}, /* Source 0 enable , */\
+ { 0x2040, "TDMVSE"}, /* Source 1 enable , */\
+ { 0x2050, "TDMCFE"}, /* Source 2 enable , */\
+ { 0x2060, "TDMCF2E"}, /* Source 3 enable , */\
+ { 0x2070, "TDMCLINV"}, /* Reception data to BCK clock , */\
+ { 0x2080, "TDMFSPOL"}, /* FS polarity , */\
+ { 0x2090, "TDMDEL"}, /* Data delay to FS , */\
+ { 0x20a0, "TDMADJ"}, /* Data adjustment , */\
+ { 0x20b1, "TDMOOMP"}, /* Received audio compression , */\
+ { 0x2103, "TDMNBCK"}, /* TDM NBCK - Bit clock to FS ratio , */\
+ { 0x2143, "TDMFSLN"}, /* FS length (master mode only) , */\
+ { 0x2183, "TDMSLOTS"}, /* N-slots in Frame , */\
+ { 0x21c1, "TDMTXDFO"}, /* Format unused bits , */\
+ { 0x21e1, "TDMTXUS0"}, /* Format unused slots DATAO , */\
+ { 0x2204, "TDMSLLN"}, /* N-bits in slot , */\
+ { 0x2254, "TDMBRMG"}, /* N-bits remaining , */\
+ { 0x22a4, "TDMSSIZE"}, /* Sample size per slot , */\
+ { 0x2303, "TDMSPKS"}, /* TDM slot for sink 0 , */\
+ { 0x2343, "TDMDCS"}, /* TDM slot for sink 1 , */\
+ { 0x2381, "TDMCFSEL"}, /* TDM Source 2 data selection , */\
+ { 0x23a1, "TDMCF2SEL"}, /* TDM Source 3 data selection , */\
+ { 0x2403, "TDMCSS"}, /* Slot Position of source 0 data , */\
+ { 0x2443, "TDMVSS"}, /* Slot Position of source 1 data , */\
+ { 0x2483, "TDMCFS"}, /* Slot Position of source 2 data , */\
+ { 0x24c3, "TDMCF2S"}, /* Slot Position of source 3 data , */\
+ { 0x4000, "ISTVDDS"}, /* Status POR , */\
+ { 0x4010, "ISTBSTOC"}, /* Status DCDC OCP , */\
+ { 0x4020, "ISTOTDS"}, /* Status OTP alarm , */\
+ { 0x4030, "ISTOCPR"}, /* Status OCP alarm , */\
+ { 0x4040, "ISTUVDS"}, /* Status UVP alarm , */\
+ { 0x4050, "ISTMANALARM"}, /* Status manager alarm state , */\
+ { 0x4060, "ISTTDMER"}, /* Status TDM error , */\
+ { 0x4070, "ISTNOCLK"}, /* Status lost clock , */\
+ { 0x4080, "ISTCFMER"}, /* Status cfma error , */\
+ { 0x4090, "ISTCFMAC"}, /* Status cfma ack , */\
+ { 0x40a0, "ISTSPKS"}, /* Status coolflux speaker error , */\
+ { 0x40b0, "ISTACS"}, /* Status cold started , */\
+ { 0x40c0, "ISTWDS"}, /* Status watchdog reset , */\
+ { 0x40d0, "ISTBODNOK"}, /* Status brown out detect , */\
+ { 0x40e0, "ISTLP1"}, /* Status low power mode1 detect , */\
+ { 0x40f0, "ISTCLKOOR"}, /* Status clock out of range , */\
+ { 0x4400, "ICLVDDS"}, /* Clear POR , */\
+ { 0x4410, "ICLBSTOC"}, /* Clear DCDC OCP , */\
+ { 0x4420, "ICLOTDS"}, /* Clear OTP alarm , */\
+ { 0x4430, "ICLOCPR"}, /* Clear OCP alarm , */\
+ { 0x4440, "ICLUVDS"}, /* Clear UVP alarm , */\
+ { 0x4450, "ICLMANALARM"}, /* Clear manager alarm state , */\
+ { 0x4460, "ICLTDMER"}, /* Clear TDM error , */\
+ { 0x4470, "ICLNOCLK"}, /* Clear lost clk , */\
+ { 0x4480, "ICLCFMER"}, /* Clear cfma err , */\
+ { 0x4490, "ICLCFMAC"}, /* Clear cfma ack , */\
+ { 0x44a0, "ICLSPKS"}, /* Clear coolflux speaker error , */\
+ { 0x44b0, "ICLACS"}, /* Clear cold started , */\
+ { 0x44c0, "ICLWDS"}, /* Clear watchdog reset , */\
+ { 0x44d0, "ICLBODNOK"}, /* Clear brown out detect , */\
+ { 0x44e0, "ICLLP1"}, /* Clear low power mode1 detect , */\
+ { 0x44f0, "ICLCLKOOR"}, /* Clear clock out of range , */\
+ { 0x4800, "IEVDDS"}, /* Enable POR , */\
+ { 0x4810, "IEBSTOC"}, /* Enable DCDC OCP , */\
+ { 0x4820, "IEOTDS"}, /* Enable OTP alarm , */\
+ { 0x4830, "IEOCPR"}, /* Enable OCP alarm , */\
+ { 0x4840, "IEUVDS"}, /* Enable UVP alarm , */\
+ { 0x4850, "IEMANALARM"}, /* Enable Manager Alarm state , */\
+ { 0x4860, "IETDMER"}, /* Enable TDM error , */\
+ { 0x4870, "IENOCLK"}, /* Enable lost clk , */\
+ { 0x4880, "IECFMER"}, /* Enable cfma err , */\
+ { 0x4890, "IECFMAC"}, /* Enable cfma ack , */\
+ { 0x48a0, "IESPKS"}, /* Enable coolflux speaker error , */\
+ { 0x48b0, "IEACS"}, /* Enable cold started , */\
+ { 0x48c0, "IEWDS"}, /* Enable watchdog reset , */\
+ { 0x48d0, "IEBODNOK"}, /* Enable brown out detect , */\
+ { 0x48e0, "IELP1"}, /* Enable low power mode1 detect , */\
+ { 0x48f0, "IECLKOOR"}, /* Enable clock out of range , */\
+ { 0x4c00, "IPOVDDS"}, /* Polarity POR , */\
+ { 0x4c10, "IPOBSTOC"}, /* Polarity DCDC OCP , */\
+ { 0x4c20, "IPOOTDS"}, /* Polarity OTP alarm , */\
+ { 0x4c30, "IPOOCPR"}, /* Polarity ocp alarm , */\
+ { 0x4c40, "IPOUVDS"}, /* Polarity UVP alarm , */\
+ { 0x4c50, "IPOMANALARM"}, /* Polarity manager alarm state , */\
+ { 0x4c60, "IPOTDMER"}, /* Polarity TDM error , */\
+ { 0x4c70, "IPONOCLK"}, /* Polarity lost clk , */\
+ { 0x4c80, "IPOCFMER"}, /* Polarity cfma err , */\
+ { 0x4c90, "IPOCFMAC"}, /* Polarity cfma ack , */\
+ { 0x4ca0, "IPOSPKS"}, /* Polarity coolflux speaker error , */\
+ { 0x4cb0, "IPOACS"}, /* Polarity cold started , */\
+ { 0x4cc0, "IPOWDS"}, /* Polarity watchdog reset , */\
+ { 0x4cd0, "IPOBODNOK"}, /* Polarity brown out detect , */\
+ { 0x4ce0, "IPOLP1"}, /* Polarity low power mode1 detect , */\
+ { 0x4cf0, "IPOCLKOOR"}, /* Polarity clock out of range , */\
+ { 0x5001, "BSSCR"}, /* Battery safeguard attack time , */\
+ { 0x5023, "BSST"}, /* Battery safeguard threshold voltage level , */\
+ { 0x5061, "BSSRL"}, /* Battery safeguard maximum reduction , */\
+ { 0x5082, "BSSRR"}, /* Battery safeguard release time , */\
+ { 0x50b1, "BSSHY"}, /* Battery Safeguard hysteresis , */\
+ { 0x50e0, "BSSR"}, /* Battery voltage read out , */\
+ { 0x50f0, "BSSBY"}, /* Bypass HW clipper , */\
+ { 0x5130, "CFSM"}, /* Coolflux firmware soft mute control , */\
+ { 0x5187, "VOL"}, /* CF firmware volume control , */\
+ { 0x5202, "CLIPCTRL"}, /* Clip control setting , */\
+ { 0x5230, "SLOPEE"}, /* Enables slope control , */\
+ { 0x5240, "SLOPESET"}, /* Slope speed setting (binary coded) , */\
+ { 0x5287, "AMPGAIN"}, /* Amplifier gain , */\
+ { 0x5703, "TDMDCG"}, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */\
+ { 0x5743, "TDMSPKG"}, /* Total gain depending on INPLEV setting (channel 0), */\
+ { 0x5781, "DCINSEL"}, /* VAMP_OUT2 input selection , */\
+ { 0x5881, "LNMODE"}, /* Low noise gain mode control , */\
+ { 0x5ac1, "LPM1MODE"}, /* Low power mode control , */\
+ { 0x5d02, "TDMSRCMAP"}, /* TDM source mapping , */\
+ { 0x5d31, "TDMSRCAS"}, /* Sensed value A , */\
+ { 0x5d51, "TDMSRCBS"}, /* Sensed value B , */\
+ { 0x5d71, "TDMSRCACLIP"}, /* Clip information (analog /digital) for source0 , */\
+ { 0x5d91, "TDMSRCBCLIP"}, /* Clip information (analog /digital) for source1 , */\
+ { 0x6102, "DELCURCOMP"}, /* Delay to allign compensation signal with current sense signal, */\
+ { 0x6130, "SIGCURCOMP"}, /* Polarity of compensation for current sense , */\
+ { 0x6140, "ENCURCOMP"}, /* Enable current sense compensation , */\
+ { 0x6152, "LVLCLPPWM"}, /* Set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
+ { 0x7005, "DCVOF"}, /* First Boost Voltage Level , */\
+ { 0x7065, "DCVOS"}, /* Second Boost Voltage Level , */\
+ { 0x70c3, "DCMCC"}, /* Max Coil Current , */\
+ { 0x7101, "DCCV"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
+ { 0x7120, "DCIE"}, /* Adaptive boost mode , */\
+ { 0x7130, "DCSR"}, /* Soft ramp up/down , */\
+ { 0x7140, "DCDIS"}, /* DCDC on/off , */\
+ { 0x7150, "DCPWM"}, /* DCDC PWM only mode , */\
+ { 0x7160, "DCTRACK"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
+ { 0x7170, "DCENVSEL"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
+ { 0x7204, "DCTRIP"}, /* 1st adaptive boost trip levels, effective only when DCIE is set to 1, */\
+ { 0x7254, "DCTRIP2"}, /* 2nd adaptive boost trip levels, effective only when DCIE is set to 1, */\
+ { 0x72a4, "DCTRIPT"}, /* Track adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
+ { 0x72f0, "DCTRIPHYSTE"}, /* Enable hysteresis on booster trip levels , */\
+ { 0x7304, "DCHOLD"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
+ { 0x9000, "RST"}, /* Reset for Coolflux DSP , */\
+ { 0x9011, "DMEM"}, /* Target memory for CFMA using I2C interface , */\
+ { 0x9030, "AIF"}, /* Auto increment , */\
+ { 0x9040, "CFINT"}, /* Coolflux Interrupt - auto clear , */\
+ { 0x9050, "CFCGATE"}, /* Coolflux clock gating disabling control , */\
+ { 0x9080, "REQCMD"}, /* Firmware event request rpc command , */\
+ { 0x9090, "REQRST"}, /* Firmware event request reset restart , */\
+ { 0x90a0, "REQMIPS"}, /* Firmware event request short on mips , */\
+ { 0x90b0, "REQMUTED"}, /* Firmware event request mute sequence ready , */\
+ { 0x90c0, "REQVOL"}, /* Firmware event request volume ready , */\
+ { 0x90d0, "REQDMG"}, /* Firmware event request speaker damage detected , */\
+ { 0x90e0, "REQCAL"}, /* Firmware event request calibration completed , */\
+ { 0x90f0, "REQRSV"}, /* Firmware event request reserved , */\
+ { 0x910f, "MADD"}, /* CF memory address , */\
+ { 0x920f, "MEMA"}, /* Activate memory access , */\
+ { 0x9307, "ERR"}, /* CF error flags , */\
+ { 0x9380, "ACKCMD"}, /* Firmware event acknowledge rpc command , */\
+ { 0x9390, "ACKRST"}, /* Firmware event acknowledge reset restart , */\
+ { 0x93a0, "ACKMIPS"}, /* Firmware event acknowledge short on mips , */\
+ { 0x93b0, "ACKMUTED"}, /* Firmware event acknowledge mute sequence ready , */\
+ { 0x93c0, "ACKVOL"}, /* Firmware event acknowledge volume ready , */\
+ { 0x93d0, "ACKDMG"}, /* Firmware event acknowledge speaker damage detected, */\
+ { 0x93e0, "ACKCAL"}, /* Firmware event acknowledge calibration completed , */\
+ { 0x93f0, "ACKRSV"}, /* Firmware event acknowledge reserved , */\
+ { 0xa107, "MTPK"}, /* KEY2 to access KEY2 protected registers, customer key, */\
+ { 0xa200, "KEY1LOCKED"}, /* Indicates KEY1 is locked , */\
+ { 0xa210, "KEY2LOCKED"}, /* Indicates KEY2 is locked , */\
+ { 0xa350, "CMTPI"}, /* Start copying all the data from mtp to I2C mtp registers - auto clear, */\
+ { 0xa360, "CIMTP"}, /* Start copying data from I2C mtp registers to mtp - auto clear, */\
+ { 0xa50f, "MTPRDMSB"}, /* MSB word of MTP manual read data , */\
+ { 0xa60f, "MTPRDLSB"}, /* LSB word of MTP manual read data , */\
+ { 0xb108, "EXTTS"}, /* External temperature (C) , */\
+ { 0xb190, "TROS"}, /* Select temp Speaker calibration , */\
+ { 0xe00f, "SWPROFIL"}, /* Software profile data , */\
+ { 0xe10f, "SWVSTEP"}, /* Software vstep information , */\
+ { 0xf000, "MTPOTC"}, /* Calibration schedule , */\
+ { 0xf010, "MTPEX"}, /* Calibration Ron executed , */\
+ { 0xf020, "DCMCCAPI"}, /* Calibration current limit DCDC , */\
+ { 0xf030, "DCMCCSB"}, /* Sign bit for delta calibration current limit DCDC , */\
+ { 0xf042, "USERDEF"}, /* Calibration delta current limit DCDC , */\
+ { 0xf078, "CUSTINFO"}, /* Reserved space for allowing customer to store speaker information, */\
+ { 0xf50f, "R25C"}, /* Ron resistance of speaker coil , */\
+ { 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+
+#define TFA9894_BITNAMETABLE static tfaBfName_t Tfa9894BitNames[] = {\
+ { 0x0, "powerdown"}, /* Powerdown control , */\
+ { 0x10, "reset"}, /* I2C Reset - Auto clear , */\
+ { 0x20, "enbl_coolflux"}, /* Enable CoolFlux DSP , */\
+ { 0x30, "enbl_amplifier"}, /* Enable Amplifier , */\
+ { 0x40, "enbl_boost"}, /* Enable DCDC Boost converter , */\
+ { 0x50, "coolflux_configured"}, /* Coolflux configured , */\
+ { 0x60, "sel_enbl_amplifier"}, /* CoolFlux control over amplifier , */\
+ { 0x71, "int_pad_io"}, /* Interrupt config , */\
+ { 0x90, "fs_pulse_sel"}, /* Audio sample reference , */\
+ { 0xa0, "bypass_ocp"}, /* Bypass OCP , */\
+ { 0xb0, "test_ocp"}, /* OCP testing control , */\
+ { 0xc0, "batsense_steepness"}, /* Vbat protection steepness , */\
+ { 0xd0, "bypass_hp"}, /* Bypass High Pass Filter , */\
+ { 0xe0, "enbl_dpsa"}, /* Enable DPSA , */\
+ { 0xf0, "sel_hysteresis"}, /* Select hysteresis for clock range detector , */\
+ { 0x101, "vamp_sel1"}, /* Amplifier input selection , */\
+ { 0x120, "src_set_configured"}, /* Device I2C settings configured , */\
+ { 0x130, "execute_cold_start"}, /* Execute cold start , */\
+ { 0x140, "man_enbl_brown_out"}, /* Reaction on BOD , */\
+ { 0x150, "bod_enbl"}, /* Enable BOD (only in direct control mode) , */\
+ { 0x160, "bod_hyst_enbl"}, /* Enable Hysteresis of BOD , */\
+ { 0x171, "bod_delay_set"}, /* BOD filter , */\
+ { 0x191, "bod_lvl_set"}, /* BOD threshold , */\
+ { 0x1b0, "disable_mute_time_out"}, /* Time out SB mute sequence , */\
+ { 0x1c0, "man_enbl_watchdog"}, /* Watchdog enable , */\
+ { 0x1d0, "disable_engage"}, /* Disable Engage , */\
+ { 0x1e0, "unprotect_faim"}, /* Control for FAIM protection , */\
+ { 0x1f0, "faim_enable_vbg"}, /* Overrule the enabling of VBG for faim erase/write access, */\
+ { 0x203, "audio_fs"}, /* Audio sample rate Fs , */\
+ { 0x240, "input_level"}, /* TDM output attenuation , */\
+ { 0x255, "cs_frac_delay"}, /* Current sense fractional delay , */\
+ { 0x2b1, "use_tdm_presence"}, /* Control for HW manager , */\
+ { 0x2d2, "ctrl_on2off_criterion"}, /* Amplifier on-off criteria for shutdown , */\
+ { 0x30f, "device_rev"}, /* Revision info , */\
+ { 0x401, "pll_clkin_sel"}, /* PLL external reference clock , */\
+ { 0x420, "pll_clkin_sel_osc"}, /* PLL internal reference clock , */\
+ { 0x432, "mclk_sel"}, /* Master Clock Selection , */\
+ { 0x460, "enbl_osc1m_auto_off"}, /* Internal OSC1M off at PWDN , */\
+ { 0x470, "disable_auto_sel_refclk"}, /* Automatic PLL reference clock selection for cold start, */\
+ { 0x510, "enbl_spkr_ss"}, /* Enable speaker sub-system , */\
+ { 0x520, "enbl_faim_ss"}, /* Enable FAIM sub-system , */\
+ { 0x530, "enbl_wdt_clk"}, /* Enable Coolflux watchdog clock , */\
+ { 0xe07, "ctrl_digtoana"}, /* Spare control from digital to analog , */\
+ { 0xf0f, "hidden_code"}, /* Hidden code to enable access to hidden register. (0x5A6B/23147 default for engineering), */\
+ { 0x1000, "flag_por"}, /* POR , */\
+ { 0x1010, "flag_pll_lock"}, /* PLL Lock , */\
+ { 0x1020, "flag_otpok"}, /* OTP alarm , */\
+ { 0x1030, "flag_ovpok"}, /* OVP alarm , */\
+ { 0x1040, "flag_uvpok"}, /* UVP alarm , */\
+ { 0x1050, "flag_ocp_alarm"}, /* OCP amplifier (sticky register, clear on read) , */\
+ { 0x1060, "flag_clocks_stable"}, /* Clocks stable , */\
+ { 0x1070, "flag_mtp_busy"}, /* MTP busy , */\
+ { 0x1080, "flag_lost_clk"}, /* Lost clock , */\
+ { 0x1090, "flag_cold_started"}, /* Cold Start , */\
+ { 0x10a0, "flag_watchdog_reset"}, /* Watchdog , */\
+ { 0x10b0, "flag_engage"}, /* Amplifier engage , */\
+ { 0x10c0, "flag_enbl_amp"}, /* Amplifier enable , */\
+ { 0x10d0, "flag_enbl_ref"}, /* References enable , */\
+ { 0x10e0, "flag_adc10_ready"}, /* Control ADC , */\
+ { 0x10f0, "flag_bod_vddd_nok"}, /* BOD Flag - VDD NOT OK , */\
+ { 0x1100, "flag_bst_bstcur"}, /* DCDC current limiting , */\
+ { 0x1110, "flag_bst_hiz"}, /* DCDC active (sticky register, clear on read) , */\
+ { 0x1120, "flag_bst_ocpok"}, /* DCDC OCP nmos (sticky register, clear on read) , */\
+ { 0x1130, "flag_bst_peakcur"}, /* Indicates current is max in DC-to-DC converter , */\
+ { 0x1140, "flag_bst_voutcomp"}, /* DCDC level 1x , */\
+ { 0x1150, "flag_bst_voutcomp86"}, /* DCDC level 1.14x , */\
+ { 0x1160, "flag_bst_voutcomp93"}, /* DCDC level 1.07x , */\
+ { 0x1170, "flag_cf_speakererror"}, /* Speaker status , */\
+ { 0x1180, "flag_clk_out_of_range"}, /* External clock status , */\
+ { 0x1190, "flag_man_alarm_state"}, /* Alarm state , */\
+ { 0x11a0, "flag_tdm_error"}, /* TDM error , */\
+ { 0x11b0, "flag_tdm_lut_error"}, /* TDM lookup table error , */\
+ { 0x1200, "flag_ocpokap"}, /* OCPOK pmos A , */\
+ { 0x1210, "flag_ocpokan"}, /* OCPOK nmos A , */\
+ { 0x1220, "flag_ocpokbp"}, /* OCPOK pmos B , */\
+ { 0x1230, "flag_ocpokbn"}, /* OCPOK nmos B , */\
+ { 0x1240, "flag_clip"}, /* Amplifier clipping , */\
+ { 0x1250, "flag_man_start_mute_audio"}, /* Audio mute sequence , */\
+ { 0x1260, "flag_man_operating_state"}, /* Device in Operating state , */\
+ { 0x1270, "flag_lp_detect_mode1"}, /* Low power MODE1 detection , */\
+ { 0x1280, "flag_low_amplitude"}, /* Low amplitude detection , */\
+ { 0x1290, "flag_vddp_gt_vbat"}, /* VDDP greater than VBAT flag , */\
+ { 0x1402, "tdm_status"}, /* TDM Status bits , */\
+ { 0x1433, "man_state"}, /* Device Manager status , */\
+ { 0x1473, "amp_ctrl_state"}, /* Amplifier control status , */\
+ { 0x14b1, "status_bst_mode"}, /* DCDC mode status bits , */\
+ { 0x1509, "bat_adc"}, /* Battery voltage (V) , */\
+ { 0x1608, "temp_adc"}, /* IC Temperature (C) , */\
+ { 0x1709, "vddp_adc"}, /* IC VDDP voltage (1023*VDDP/13V) , */\
+ { 0x2000, "tdm_enable"}, /* Enable interface , */\
+ { 0x2010, "tdm_sink0_enable"}, /* Control audio tdm channel in sink0 , */\
+ { 0x2020, "tdm_sink1_enable"}, /* Control audio tdm channel in sink1 , */\
+ { 0x2030, "tdm_source0_enable"}, /* Source 0 enable , */\
+ { 0x2040, "tdm_source1_enable"}, /* Source 1 enable , */\
+ { 0x2050, "tdm_source2_enable"}, /* Source 2 enable , */\
+ { 0x2060, "tdm_source3_enable"}, /* Source 3 enable , */\
+ { 0x2070, "tdm_clk_inversion"}, /* Reception data to BCK clock , */\
+ { 0x2080, "tdm_fs_ws_polarity"}, /* FS polarity , */\
+ { 0x2090, "tdm_data_delay"}, /* Data delay to FS , */\
+ { 0x20a0, "tdm_data_adjustment"}, /* Data adjustment , */\
+ { 0x20b1, "tdm_audio_sample_compression"}, /* Received audio compression , */\
+ { 0x2103, "tdm_nbck"}, /* TDM NBCK - Bit clock to FS ratio , */\
+ { 0x2143, "tdm_fs_ws_length"}, /* FS length (master mode only) , */\
+ { 0x2183, "tdm_nb_of_slots"}, /* N-slots in Frame , */\
+ { 0x21c1, "tdm_txdata_format"}, /* Format unused bits , */\
+ { 0x21e1, "tdm_txdata_format_unused_slot"}, /* Format unused slots DATAO , */\
+ { 0x2204, "tdm_slot_length"}, /* N-bits in slot , */\
+ { 0x2254, "tdm_bits_remaining"}, /* N-bits remaining , */\
+ { 0x22a4, "tdm_sample_size"}, /* Sample size per slot , */\
+ { 0x2303, "tdm_sink0_slot"}, /* TDM slot for sink 0 , */\
+ { 0x2343, "tdm_sink1_slot"}, /* TDM slot for sink 1 , */\
+ { 0x2381, "tdm_source2_sel"}, /* TDM Source 2 data selection , */\
+ { 0x23a1, "tdm_source3_sel"}, /* TDM Source 3 data selection , */\
+ { 0x2403, "tdm_source0_slot"}, /* Slot Position of source 0 data , */\
+ { 0x2443, "tdm_source1_slot"}, /* Slot Position of source 1 data , */\
+ { 0x2483, "tdm_source2_slot"}, /* Slot Position of source 2 data , */\
+ { 0x24c3, "tdm_source3_slot"}, /* Slot Position of source 3 data , */\
+ { 0x4000, "int_out_flag_por"}, /* Status POR , */\
+ { 0x4010, "int_out_flag_bst_ocpok"}, /* Status DCDC OCP , */\
+ { 0x4020, "int_out_flag_otpok"}, /* Status OTP alarm , */\
+ { 0x4030, "int_out_flag_ocp_alarm"}, /* Status OCP alarm , */\
+ { 0x4040, "int_out_flag_uvpok"}, /* Status UVP alarm , */\
+ { 0x4050, "int_out_flag_man_alarm_state"}, /* Status manager alarm state , */\
+ { 0x4060, "int_out_flag_tdm_error"}, /* Status TDM error , */\
+ { 0x4070, "int_out_flag_lost_clk"}, /* Status lost clock , */\
+ { 0x4080, "int_out_flag_cfma_err"}, /* Status cfma error , */\
+ { 0x4090, "int_out_flag_cfma_ack"}, /* Status cfma ack , */\
+ { 0x40a0, "int_out_flag_cf_speakererror"}, /* Status coolflux speaker error , */\
+ { 0x40b0, "int_out_flag_cold_started"}, /* Status cold started , */\
+ { 0x40c0, "int_out_flag_watchdog_reset"}, /* Status watchdog reset , */\
+ { 0x40d0, "int_out_flag_bod_vddd_nok"}, /* Status brown out detect , */\
+ { 0x40e0, "int_out_flag_lp_detect_mode1"}, /* Status low power mode1 detect , */\
+ { 0x40f0, "int_out_flag_clk_out_of_range"}, /* Status clock out of range , */\
+ { 0x4400, "int_in_flag_por"}, /* Clear POR , */\
+ { 0x4410, "int_in_flag_bst_ocpok"}, /* Clear DCDC OCP , */\
+ { 0x4420, "int_in_flag_otpok"}, /* Clear OTP alarm , */\
+ { 0x4430, "int_in_flag_ocp_alarm"}, /* Clear OCP alarm , */\
+ { 0x4440, "int_in_flag_uvpok"}, /* Clear UVP alarm , */\
+ { 0x4450, "int_in_flag_man_alarm_state"}, /* Clear manager alarm state , */\
+ { 0x4460, "int_in_flag_tdm_error"}, /* Clear TDM error , */\
+ { 0x4470, "int_in_flag_lost_clk"}, /* Clear lost clk , */\
+ { 0x4480, "int_in_flag_cfma_err"}, /* Clear cfma err , */\
+ { 0x4490, "int_in_flag_cfma_ack"}, /* Clear cfma ack , */\
+ { 0x44a0, "int_in_flag_cf_speakererror"}, /* Clear coolflux speaker error , */\
+ { 0x44b0, "int_in_flag_cold_started"}, /* Clear cold started , */\
+ { 0x44c0, "int_in_flag_watchdog_reset"}, /* Clear watchdog reset , */\
+ { 0x44d0, "int_in_flag_bod_vddd_nok"}, /* Clear brown out detect , */\
+ { 0x44e0, "int_in_flag_lp_detect_mode1"}, /* Clear low power mode1 detect , */\
+ { 0x44f0, "int_in_flag_clk_out_of_range"}, /* Clear clock out of range , */\
+ { 0x4800, "int_enable_flag_por"}, /* Enable POR , */\
+ { 0x4810, "int_enable_flag_bst_ocpok"}, /* Enable DCDC OCP , */\
+ { 0x4820, "int_enable_flag_otpok"}, /* Enable OTP alarm , */\
+ { 0x4830, "int_enable_flag_ocp_alarm"}, /* Enable OCP alarm , */\
+ { 0x4840, "int_enable_flag_uvpok"}, /* Enable UVP alarm , */\
+ { 0x4850, "int_enable_flag_man_alarm_state"}, /* Enable Manager Alarm state , */\
+ { 0x4860, "int_enable_flag_tdm_error"}, /* Enable TDM error , */\
+ { 0x4870, "int_enable_flag_lost_clk"}, /* Enable lost clk , */\
+ { 0x4880, "int_enable_flag_cfma_err"}, /* Enable cfma err , */\
+ { 0x4890, "int_enable_flag_cfma_ack"}, /* Enable cfma ack , */\
+ { 0x48a0, "int_enable_flag_cf_speakererror"}, /* Enable coolflux speaker error , */\
+ { 0x48b0, "int_enable_flag_cold_started"}, /* Enable cold started , */\
+ { 0x48c0, "int_enable_flag_watchdog_reset"}, /* Enable watchdog reset , */\
+ { 0x48d0, "int_enable_flag_bod_vddd_nok"}, /* Enable brown out detect , */\
+ { 0x48e0, "int_enable_flag_lp_detect_mode1"}, /* Enable low power mode1 detect , */\
+ { 0x48f0, "int_enable_flag_clk_out_of_range"}, /* Enable clock out of range , */\
+ { 0x4c00, "int_polarity_flag_por"}, /* Polarity POR , */\
+ { 0x4c10, "int_polarity_flag_bst_ocpok"}, /* Polarity DCDC OCP , */\
+ { 0x4c20, "int_polarity_flag_otpok"}, /* Polarity OTP alarm , */\
+ { 0x4c30, "int_polarity_flag_ocp_alarm"}, /* Polarity ocp alarm , */\
+ { 0x4c40, "int_polarity_flag_uvpok"}, /* Polarity UVP alarm , */\
+ { 0x4c50, "int_polarity_flag_man_alarm_state"}, /* Polarity manager alarm state , */\
+ { 0x4c60, "int_polarity_flag_tdm_error"}, /* Polarity TDM error , */\
+ { 0x4c70, "int_polarity_flag_lost_clk"}, /* Polarity lost clk , */\
+ { 0x4c80, "int_polarity_flag_cfma_err"}, /* Polarity cfma err , */\
+ { 0x4c90, "int_polarity_flag_cfma_ack"}, /* Polarity cfma ack , */\
+ { 0x4ca0, "int_polarity_flag_cf_speakererror"}, /* Polarity coolflux speaker error , */\
+ { 0x4cb0, "int_polarity_flag_cold_started"}, /* Polarity cold started , */\
+ { 0x4cc0, "int_polarity_flag_watchdog_reset"}, /* Polarity watchdog reset , */\
+ { 0x4cd0, "int_polarity_flag_bod_vddd_nok"}, /* Polarity brown out detect , */\
+ { 0x4ce0, "int_polarity_flag_lp_detect_mode1"}, /* Polarity low power mode1 detect , */\
+ { 0x4cf0, "int_polarity_flag_clk_out_of_range"}, /* Polarity clock out of range , */\
+ { 0x5001, "vbat_prot_attack_time"}, /* Battery safeguard attack time , */\
+ { 0x5023, "vbat_prot_thlevel"}, /* Battery safeguard threshold voltage level , */\
+ { 0x5061, "vbat_prot_max_reduct"}, /* Battery safeguard maximum reduction , */\
+ { 0x5082, "vbat_prot_release_time"}, /* Battery safeguard release time , */\
+ { 0x50b1, "vbat_prot_hysterese"}, /* Battery Safeguard hysteresis , */\
+ { 0x50d0, "rst_min_vbat"}, /* Reset clipper - auto clear , */\
+ { 0x50e0, "sel_vbat"}, /* Battery voltage read out , */\
+ { 0x50f0, "bypass_clipper"}, /* Bypass HW clipper , */\
+ { 0x5130, "cf_mute"}, /* Coolflux firmware soft mute control , */\
+ { 0x5187, "cf_volume"}, /* CF firmware volume control , */\
+ { 0x5202, "ctrl_cc"}, /* Clip control setting , */\
+ { 0x5230, "ctrl_slopectrl"}, /* Enables slope control , */\
+ { 0x5240, "ctrl_slope"}, /* Slope speed setting (binary coded) , */\
+ { 0x5287, "gain"}, /* Amplifier gain , */\
+ { 0x5301, "dpsa_level"}, /* DPSA threshold levels , */\
+ { 0x5321, "dpsa_release"}, /* DPSA Release time , */\
+ { 0x5340, "clipfast"}, /* Clock selection for HW clipper for battery safeguard, */\
+ { 0x5350, "bypass_lp"}, /* Bypass the low power filter inside temperature sensor, */\
+ { 0x5360, "first_order_mode"}, /* Overrule to 1st order mode of control stage when clipping, */\
+ { 0x5370, "icomp_engage"}, /* Engage of icomp , */\
+ { 0x5380, "ctrl_kickback"}, /* Prevent double pulses of output stage , */\
+ { 0x5390, "icomp_engage_overrule"}, /* To overrule the functional icomp_engage signal during validation, */\
+ { 0x53a3, "ctrl_dem"}, /* Enable DEM icomp and DEM one bit dac , */\
+ { 0x5400, "bypass_ctrlloop"}, /* Switch amplifier into open loop configuration , */\
+ { 0x5413, "ctrl_dem_mismatch"}, /* Enable DEM icomp mismatch for testing , */\
+ { 0x5452, "dpsa_drive"}, /* Drive setting (binary coded) , */\
+ { 0x550a, "enbl_amp"}, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually, */\
+ { 0x55b0, "enbl_engage"}, /* Enables/engage power stage and control loop , */\
+ { 0x55c0, "enbl_engage_pst"}, /* Enables/engage power stage and control loop , */\
+ { 0x5600, "pwm_shape"}, /* PWM shape , */\
+ { 0x5614, "pwm_delay"}, /* PWM delay bits to set the delay, clockd is 1/(k*2048*fs), */\
+ { 0x5660, "reclock_pwm"}, /* Reclock the PWM signal inside analog , */\
+ { 0x5670, "reclock_voltsense"}, /* Reclock the voltage sense PWM signal , */\
+ { 0x5680, "enbl_pwm_phase_shift"}, /* Control for PWM phase shift , */\
+ { 0x5690, "sel_pwm_delay_src"}, /* Control for selection for PWM delay line source , */\
+ { 0x56a1, "enbl_odd_up_even_down"}, /* Control for PWM reference sawtooth generartion , */\
+ { 0x5703, "ctrl_att_dcdc"}, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */\
+ { 0x5743, "ctrl_att_spkr"}, /* Total gain depending on INPLEV setting (channel 0), */\
+ { 0x5781, "vamp_sel2"}, /* VAMP_OUT2 input selection , */\
+ { 0x5805, "zero_lvl"}, /* Low noise gain switch zero trigger level , */\
+ { 0x5861, "ctrl_fb_resistor"}, /* Select amplifier feedback resistor connection , */\
+ { 0x5881, "lownoisegain_mode"}, /* Low noise gain mode control , */\
+ { 0x5905, "threshold_lvl"}, /* Low noise gain switch trigger level , */\
+ { 0x5965, "hold_time"}, /* Low noise mode hold time before entering into low noise mode, */\
+ { 0x5a05, "lpm1_cal_offset"}, /* Low power mode1 detector ctrl cal_offset from gain module , */\
+ { 0x5a65, "lpm1_zero_lvl"}, /* Low power mode1 zero crossing detection level , */\
+ { 0x5ac1, "lpm1_mode"}, /* Low power mode control , */\
+ { 0x5b05, "lpm1_threshold_lvl"}, /* Low power mode1 amplitude trigger level , */\
+ { 0x5b65, "lpm1_hold_time"}, /* Low power mode hold time before entering into low power mode, */\
+ { 0x5bc0, "disable_low_power_mode"}, /* Low power mode1 detector control , */\
+ { 0x5c00, "enbl_minion"}, /* Enables minion (small) power stage , */\
+ { 0x5c13, "vth_vddpvbat"}, /* Select vddp-vbat threshold signal , */\
+ { 0x5c50, "lpen_vddpvbat"}, /* Select vddp-vbat filtred vs unfiltered compare , */\
+ { 0x5c61, "ctrl_rfb"}, /* Feedback resistor selection - I2C direct mode , */\
+ { 0x5d02, "tdm_source_mapping"}, /* TDM source mapping , */\
+ { 0x5d31, "tdm_sourcea_frame_sel"}, /* Sensed value A , */\
+ { 0x5d51, "tdm_sourceb_frame_sel"}, /* Sensed value B , */\
+ { 0x5d71, "tdm_source0_clip_sel"}, /* Clip information (analog /digital) for source0 , */\
+ { 0x5d91, "tdm_source1_clip_sel"}, /* Clip information (analog /digital) for source1 , */\
+ { 0x5e02, "rst_min_vbat_delay"}, /* Delay for reseting the min_vbat value inside HW Clipper (number of Fs pulses), */\
+ { 0x5e30, "rst_min_vbat_sel"}, /* Control for selecting reset signal for min_bat , */\
+ { 0x5f00, "hard_mute"}, /* Hard mute - PWM , */\
+ { 0x5f12, "ns_hp2ln_criterion"}, /* 0..7 zeroes at ns as threshold to swap from high_power to low_noise, */\
+ { 0x5f42, "ns_ln2hp_criterion"}, /* 0..7 zeroes at ns as threshold to swap from low_noise to high_power, */\
+ { 0x5f78, "spare_out"}, /* Spare out register , */\
+ { 0x600f, "spare_in"}, /* Spare IN , */\
+ { 0x6102, "cursense_comp_delay"}, /* Delay to allign compensation signal with current sense signal, */\
+ { 0x6130, "cursense_comp_sign"}, /* Polarity of compensation for current sense , */\
+ { 0x6140, "enbl_cursense_comp"}, /* Enable current sense compensation , */\
+ { 0x6152, "pwms_clip_lvl"}, /* Set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
+ { 0x7005, "frst_boost_voltage"}, /* First Boost Voltage Level , */\
+ { 0x7065, "scnd_boost_voltage"}, /* Second Boost Voltage Level , */\
+ { 0x70c3, "boost_cur"}, /* Max Coil Current , */\
+ { 0x7101, "bst_slpcmplvl"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
+ { 0x7120, "boost_intel"}, /* Adaptive boost mode , */\
+ { 0x7130, "boost_speed"}, /* Soft ramp up/down , */\
+ { 0x7140, "dcdcoff_mode"}, /* DCDC on/off , */\
+ { 0x7150, "dcdc_pwmonly"}, /* DCDC PWM only mode , */\
+ { 0x7160, "boost_track"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
+ { 0x7170, "sel_dcdc_envelope_8fs"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
+ { 0x7180, "ignore_flag_voutcomp86"}, /* Determines the maximum PWM frequency be the most efficient in relation to the Booster inductor value, */\
+ { 0x7204, "boost_trip_lvl_1st"}, /* 1st adaptive boost trip levels, effective only when DCIE is set to 1, */\
+ { 0x7254, "boost_trip_lvl_2nd"}, /* 2nd adaptive boost trip levels, effective only when DCIE is set to 1, */\
+ { 0x72a4, "boost_trip_lvl_track"}, /* Track adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
+ { 0x72f0, "enbl_trip_hyst"}, /* Enable hysteresis on booster trip levels , */\
+ { 0x7304, "boost_hold_time"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
+ { 0x7350, "dcdc_pfm20khz_limit"}, /* DCDC in PFM mode pwm mode is activated each 50us to force a pwm pulse, */\
+ { 0x7361, "dcdc_ctrl_maxzercnt"}, /* Number of zero current flags to count before going to pfm mode, */\
+ { 0x7386, "dcdc_vbat_delta_detect"}, /* Threshold before booster is reacting on a delta Vbat (in PFM mode) by temporarily switching to PWM mode, */\
+ { 0x73f0, "dcdc_ignore_vbat"}, /* Ignore an increase on Vbat , */\
+ { 0x7404, "bst_drive"}, /* Binary coded drive setting for boost converter power stage, */\
+ { 0x7451, "bst_scalecur"}, /* For testing direct control scale current , */\
+ { 0x7474, "bst_slopecur"}, /* For testing direct control slope current , */\
+ { 0x74c1, "bst_slope"}, /* Boost slope speed , */\
+ { 0x74e0, "bst_bypass_bstcur"}, /* Bypass control for boost current settings , */\
+ { 0x74f0, "bst_bypass_bstfoldback"}, /* Bypass control for boost foldback , */\
+ { 0x7500, "enbl_bst_engage"}, /* Enable power stage dcdc controller , */\
+ { 0x7510, "enbl_bst_hizcom"}, /* Enable hiz comparator , */\
+ { 0x7520, "enbl_bst_peakcur"}, /* Enable peak current , */\
+ { 0x7530, "enbl_bst_power"}, /* Enable line of the powerstage , */\
+ { 0x7540, "enbl_bst_slopecur"}, /* Enable bit of max-current dac , */\
+ { 0x7550, "enbl_bst_voutcomp"}, /* Enable vout comparators , */\
+ { 0x7560, "enbl_bst_voutcomp86"}, /* Enable vout-86 comparators , */\
+ { 0x7570, "enbl_bst_voutcomp93"}, /* Enable vout-93 comparators , */\
+ { 0x7580, "enbl_bst_windac"}, /* Enable window dac , */\
+ { 0x7595, "bst_windac"}, /* For testing direct control windac , */\
+ { 0x7600, "boost_alg"}, /* Control for boost adaptive loop gain , */\
+ { 0x7611, "boost_loopgain"}, /* DCDC boost loopgain setting , */\
+ { 0x7631, "bst_freq"}, /* DCDC boost frequency control , */\
+ { 0x7650, "enbl_bst_peak2avg"}, /* Enable boost peak2avg functionality , */\
+ { 0x7660, "bst_use_new_zercur_detect"}, /* Enable new zero current detection for boost control, */\
+ { 0x8001, "sel_clk_cs"}, /* Current sense clock duty cycle control , */\
+ { 0x8021, "micadc_speed"}, /* Current sense clock for MiCADC selection - 32/44.1/48 KHz Fs band only, */\
+ { 0x8040, "cs_gain_control"}, /* Current sense gain control , */\
+ { 0x8050, "cs_bypass_gc"}, /* Bypasses the CS gain correction , */\
+ { 0x8060, "invertpwm"}, /* Current sense common mode feedback pwm invert control, */\
+ { 0x8087, "cs_gain"}, /* Current sense gain , */\
+ { 0x8105, "cs_ktemp"}, /* Current sense temperature compensation trimming (1 - VALUE*TEMP) * signal, */\
+ { 0x8164, "cs_ktemp2"}, /* Second order temperature compensation coefficient , */\
+ { 0x81b0, "enbl_cs_adc"}, /* Enable current sense ADC , */\
+ { 0x81c0, "enbl_cs_inn1"}, /* Enable connection of current sense negative1 , */\
+ { 0x81d0, "enbl_cs_inn2"}, /* Enable connection of current sense negative2 , */\
+ { 0x81e0, "enbl_cs_inp1"}, /* Enable connection of current sense positive1 , */\
+ { 0x81f0, "enbl_cs_inp2"}, /* Enable connection of current sense positive2 , */\
+ { 0x8200, "enbl_cs_ldo"}, /* Enable current sense LDO , */\
+ { 0x8210, "enbl_cs_vbatldo"}, /* Enable of current sense LDO , */\
+ { 0x8220, "cs_adc_bsoinv"}, /* Bitstream inversion for current sense ADC , */\
+ { 0x8231, "cs_adc_hifreq"}, /* Frequency mode current sense ADC , */\
+ { 0x8250, "cs_adc_nortz"}, /* Return to zero for current sense ADC , */\
+ { 0x8263, "cs_adc_offset"}, /* Micadc ADC offset setting , */\
+ { 0x82a0, "cs_adc_slowdel"}, /* Select delay for current sense ADC (internal decision circuitry), */\
+ { 0x82b4, "cs_adc_gain"}, /* Gain setting for current sense ADC (two's complement), */\
+ { 0x8300, "cs_resonator_enable"}, /* Enable for resonator to improve SRN , */\
+ { 0x8310, "cs_classd_tran_skip"}, /* Skip current sense connection during a classD amplifier transition, */\
+ { 0x8320, "cs_inn_short"}, /* Short current sense negative to common mode , */\
+ { 0x8330, "cs_inp_short"}, /* Short current sense positive to common mode , */\
+ { 0x8340, "cs_ldo_bypass"}, /* Bypass current sense LDO , */\
+ { 0x8350, "cs_ldo_pulldown"}, /* Pull down current sense LDO, only valid if enbl_cs_ldo is high, */\
+ { 0x8364, "cs_ldo_voset"}, /* Current sense LDO voltage level setting (two's complement), */\
+ { 0x8800, "ctrl_vs_igen_supply"}, /* Control for selecting supply for VS current generator, */\
+ { 0x8810, "ctrl_vs_force_div2"}, /* Select input resistive divider gain , */\
+ { 0x8820, "enbl_dc_filter"}, /* Control for enabling the DC blocking filter for voltage and current sense, */\
+ { 0x8901, "volsense_pwm_sel"}, /* Voltage sense source selection control , */\
+ { 0x8920, "vs_gain_control"}, /* Voltage sense gain control , */\
+ { 0x8930, "vs_bypass_gc"}, /* Bypasses the VS gain correction , */\
+ { 0x8940, "vs_adc_bsoinv"}, /* Bitstream inversion for voltage sense ADC , */\
+ { 0x8950, "vs_adc_nortz"}, /* Return to zero for voltage sense ADC , */\
+ { 0x8960, "vs_adc_slowdel"}, /* Select delay for voltage sense ADC (internal decision circuitry), */\
+ { 0x8970, "vs_classd_tran_skip"}, /* Skip voltage sense connection during a classD amplifier transition, */\
+ { 0x8987, "vs_gain"}, /* Voltage sense gain , */\
+ { 0x8a00, "vs_inn_short"}, /* Short voltage sense negative to common mode , */\
+ { 0x8a10, "vs_inp_short"}, /* Short voltage sense positive to common mode , */\
+ { 0x8a20, "vs_ldo_bypass"}, /* Bypass voltage sense LDO , */\
+ { 0x8a30, "vs_ldo_pulldown"}, /* Pull down voltage sense LDO, only valid if enbl_cs_ldo is high, */\
+ { 0x8a44, "vs_ldo_voset"}, /* Voltage sense LDO voltage level setting (two's complement), */\
+ { 0x8a90, "enbl_vs_adc"}, /* Enable voltage sense ADC , */\
+ { 0x8aa0, "enbl_vs_inn1"}, /* Enable connection of voltage sense negative1 , */\
+ { 0x8ab0, "enbl_vs_inn2"}, /* Enable connection of voltage sense negative2 , */\
+ { 0x8ac0, "enbl_vs_inp1"}, /* Enable connection of voltage sense positive1 , */\
+ { 0x8ad0, "enbl_vs_inp2"}, /* Enable connection of voltage sense positive2 , */\
+ { 0x8ae0, "enbl_vs_ldo"}, /* Enable voltage sense LDO , */\
+ { 0x8af0, "enbl_vs_vbatldo"}, /* Enable of voltage sense LDO , */\
+ { 0x9000, "cf_rst_dsp"}, /* Reset for Coolflux DSP , */\
+ { 0x9011, "cf_dmem"}, /* Target memory for CFMA using I2C interface , */\
+ { 0x9030, "cf_aif"}, /* Auto increment , */\
+ { 0x9040, "cf_int"}, /* Coolflux Interrupt - auto clear , */\
+ { 0x9050, "cf_cgate_off"}, /* Coolflux clock gating disabling control , */\
+ { 0x9080, "cf_req_cmd"}, /* Firmware event request rpc command , */\
+ { 0x9090, "cf_req_reset"}, /* Firmware event request reset restart , */\
+ { 0x90a0, "cf_req_mips"}, /* Firmware event request short on mips , */\
+ { 0x90b0, "cf_req_mute_ready"}, /* Firmware event request mute sequence ready , */\
+ { 0x90c0, "cf_req_volume_ready"}, /* Firmware event request volume ready , */\
+ { 0x90d0, "cf_req_damage"}, /* Firmware event request speaker damage detected , */\
+ { 0x90e0, "cf_req_calibrate_ready"}, /* Firmware event request calibration completed , */\
+ { 0x90f0, "cf_req_reserved"}, /* Firmware event request reserved , */\
+ { 0x910f, "cf_madd"}, /* CF memory address , */\
+ { 0x920f, "cf_mema"}, /* Activate memory access , */\
+ { 0x9307, "cf_err"}, /* CF error flags , */\
+ { 0x9380, "cf_ack_cmd"}, /* Firmware event acknowledge rpc command , */\
+ { 0x9390, "cf_ack_reset"}, /* Firmware event acknowledge reset restart , */\
+ { 0x93a0, "cf_ack_mips"}, /* Firmware event acknowledge short on mips , */\
+ { 0x93b0, "cf_ack_mute_ready"}, /* Firmware event acknowledge mute sequence ready , */\
+ { 0x93c0, "cf_ack_volume_ready"}, /* Firmware event acknowledge volume ready , */\
+ { 0x93d0, "cf_ack_damage"}, /* Firmware event acknowledge speaker damage detected, */\
+ { 0x93e0, "cf_ack_calibrate_ready"}, /* Firmware event acknowledge calibration completed , */\
+ { 0x93f0, "cf_ack_reserved"}, /* Firmware event acknowledge reserved , */\
+ { 0xa007, "mtpkey1"}, /* KEY1 To access KEY1 protected registers 0x5A/90d (default for engineering), */\
+ { 0xa107, "mtpkey2"}, /* KEY2 to access KEY2 protected registers, customer key, */\
+ { 0xa200, "key01_locked"}, /* Indicates KEY1 is locked , */\
+ { 0xa210, "key02_locked"}, /* Indicates KEY2 is locked , */\
+ { 0xa302, "mtp_man_address_in"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
+ { 0xa330, "man_copy_mtp_to_iic"}, /* Start copying single word from MTP to I2C mtp register - auto clear, */\
+ { 0xa340, "man_copy_iic_to_mtp"}, /* Start copying single word from I2C mtp register to mtp - auto clear, */\
+ { 0xa350, "auto_copy_mtp_to_iic"}, /* Start copying all the data from mtp to I2C mtp registers - auto clear, */\
+ { 0xa360, "auto_copy_iic_to_mtp"}, /* Start copying data from I2C mtp registers to mtp - auto clear, */\
+ { 0xa400, "faim_set_clkws"}, /* Sets the FaIM controller clock wait state register, */\
+ { 0xa410, "faim_sel_evenrows"}, /* All even rows of the FaIM are selected, active high, */\
+ { 0xa420, "faim_sel_oddrows"}, /* All odd rows of the FaIM are selected, all rows in combination with sel_evenrows, */\
+ { 0xa430, "faim_program_only"}, /* Skip the erase access at wr_faim command (write-program-marginread), */\
+ { 0xa440, "faim_erase_only"}, /* Skip the program access at wr_faim command (write-erase-marginread), */\
+ { 0xa50f, "mtp_man_data_out_msb"}, /* MSB word of MTP manual read data , */\
+ { 0xa60f, "mtp_man_data_out_lsb"}, /* LSB word of MTP manual read data , */\
+ { 0xa70f, "mtp_man_data_in_msb"}, /* MSB word of write data for MTP manual write , */\
+ { 0xa80f, "mtp_man_data_in_lsb"}, /* LSB word of write data for MTP manual write , */\
+ { 0xb000, "bypass_ocpcounter"}, /* Bypass OCP Counter , */\
+ { 0xb010, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
+ { 0xb020, "bypass_ovp"}, /* Bypass OVP , */\
+ { 0xb030, "bypass_uvp"}, /* Bypass UVP , */\
+ { 0xb040, "bypass_otp"}, /* Bypass OTP , */\
+ { 0xb050, "bypass_lost_clk"}, /* Bypass lost clock detector , */\
+ { 0xb060, "ctrl_vpalarm"}, /* vpalarm (uvp ovp handling) , */\
+ { 0xb070, "disable_main_ctrl_change_prot"}, /* Disable main control change protection , */\
+ { 0xb087, "ocp_threshold"}, /* OCP threshold level , */\
+ { 0xb108, "ext_temp"}, /* External temperature (C) , */\
+ { 0xb190, "ext_temp_sel"}, /* Select temp Speaker calibration , */\
+ { 0xc000, "use_direct_ctrls"}, /* Direct control to overrule several functions for testing, */\
+ { 0xc010, "rst_datapath"}, /* Direct control for datapath reset , */\
+ { 0xc020, "rst_cgu"}, /* Direct control for cgu reset , */\
+ { 0xc038, "enbl_ref"}, /* Switch on the analog references, each part of the references can be switched on/off individually, */\
+ { 0xc0c0, "use_direct_vs_ctrls"}, /* Voltage sense direct control to overrule several functions for testing, */\
+ { 0xc0d0, "enbl_ringo"}, /* Enable the ring oscillator for test purpose , */\
+ { 0xc0e0, "use_direct_clk_ctrl"}, /* Direct clock control to overrule several functions for testing, */\
+ { 0xc0f0, "use_direct_pll_ctrl"}, /* Direct PLL control to overrule several functions for testing, */\
+ { 0xc100, "enbl_tsense"}, /* Temperature sensor enable control - I2C direct mode, */\
+ { 0xc110, "tsense_hibias"}, /* Bit to set the biasing in temp sensor to high , */\
+ { 0xc120, "enbl_flag_vbg"}, /* Enable flagging of bandgap out of control , */\
+ { 0xc20f, "abist_offset"}, /* Offset control for ABIST testing (two's complement), */\
+ { 0xc300, "bypasslatch"}, /* Bypass latch , */\
+ { 0xc311, "sourcea"}, /* Set OUTA to , */\
+ { 0xc331, "sourceb"}, /* Set OUTB to , */\
+ { 0xc350, "inverta"}, /* Invert pwma test signal , */\
+ { 0xc360, "invertb"}, /* Invert pwmb test signal , */\
+ { 0xc374, "pulselength"}, /* Pulse length setting test input for amplifier (clock d - k*2048*fs), */\
+ { 0xc3d0, "test_abistfft_enbl"}, /* Enable ABIST with FFT on Coolflux DSP , */\
+ { 0xc400, "bst_bypasslatch"}, /* Bypass latch in boost converter , */\
+ { 0xc411, "bst_source"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
+ { 0xc430, "bst_invertb"}, /* Invert pwmbst test signal , */\
+ { 0xc444, "bst_pulselength"}, /* Pulse length setting test input for boost converter , */\
+ { 0xc490, "test_bst_ctrlsthv"}, /* Test mode for boost control stage , */\
+ { 0xc4a0, "test_bst_iddq"}, /* IDDQ testing in power stage of boost converter , */\
+ { 0xc4b0, "test_bst_rdson"}, /* RDSON testing - boost power stage , */\
+ { 0xc4c0, "test_bst_cvi"}, /* CVI testing - boost power stage , */\
+ { 0xc4d0, "test_bst_ocp"}, /* Boost OCP. For old ocp (ctrl_reversebst is 0), For new ocp (ctrl_reversebst is 1), */\
+ { 0xc4e0, "test_bst_sense"}, /* Test option for the sense NMOS in booster for current mode control., */\
+ { 0xc500, "test_cvi"}, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */\
+ { 0xc510, "test_discrete"}, /* Test function noise measurement , */\
+ { 0xc520, "test_iddq"}, /* Set the power stages in iddq mode for gate stress., */\
+ { 0xc530, "test_rdson"}, /* Analog BIST, switch to enable Rdson measurement , */\
+ { 0xc540, "test_sdelta"}, /* Analog BIST, noise test , */\
+ { 0xc550, "test_enbl_cs"}, /* Enable for digimux mode of current sense , */\
+ { 0xc560, "test_enbl_vs"}, /* Enable for digimux mode of voltage sense , */\
+ { 0xc570, "enbl_pwm_dcc"}, /* Enables direct control of pwm duty cycle for DCDC power stage, */\
+ { 0xc583, "pwm_dcc_cnt"}, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */\
+ { 0xc5c0, "enbl_ldo_stress"}, /* Enable stress of internal supply voltages powerstages, */\
+ { 0xc607, "digimuxa_sel"}, /* DigimuxA input selection control routed to DATAO , */\
+ { 0xc687, "digimuxb_sel"}, /* DigimuxB input selection control routed to INT , */\
+ { 0xc707, "digimuxc_sel"}, /* DigimuxC input selection control routed to ADS1 , */\
+ { 0xc800, "enbl_anamux1"}, /* Enable anamux1 , */\
+ { 0xc810, "enbl_anamux2"}, /* Enable anamux2 , */\
+ { 0xc820, "enbl_anamux3"}, /* Enable anamux3 , */\
+ { 0xc830, "enbl_anamux4"}, /* Enable anamux4 , */\
+ { 0xc844, "anamux1"}, /* Anamux selection control - anamux on TEST1 , */\
+ { 0xc894, "anamux2"}, /* Anamux selection control - anamux on TEST2 , */\
+ { 0xc903, "anamux3"}, /* Anamux selection control - anamux on TEST3 , */\
+ { 0xc943, "anamux4"}, /* Anamux selection control - anamux on TEST4 , */\
+ { 0xca05, "pll_seli"}, /* PLL SELI - I2C direct PLL control mode only , */\
+ { 0xca64, "pll_selp"}, /* PLL SELP - I2C direct PLL control mode only , */\
+ { 0xcab3, "pll_selr"}, /* PLL SELR - I2C direct PLL control mode only , */\
+ { 0xcaf0, "pll_frm"}, /* PLL free running mode control; 1 in TCB direct control mode, else this control bit, */\
+ { 0xcb09, "pll_ndec"}, /* PLL NDEC - I2C direct PLL control mode only , */\
+ { 0xcba0, "pll_mdec_msb"}, /* MSB of PLL_mdec - I2C direct PLL control mode only, */\
+ { 0xcbb0, "enbl_pll"}, /* Enables PLL in I2C direct PLL control mode only , */\
+ { 0xcbc0, "enbl_osc"}, /* Enables OSC1M in I2C direct control mode only , */\
+ { 0xcbd0, "pll_bypass"}, /* PLL bypass control in I2C direct PLL control mode only, */\
+ { 0xcbe0, "pll_directi"}, /* PLL directi control in I2C direct PLL control mode only, */\
+ { 0xcbf0, "pll_directo"}, /* PLL directo control in I2C direct PLL control mode only, */\
+ { 0xcc0f, "pll_mdec_lsb"}, /* Bits 15..0 of PLL MDEC are I2C direct PLL control mode only, */\
+ { 0xcd06, "pll_pdec"}, /* PLL PDEC - I2C direct PLL control mode only , */\
+ { 0xce0f, "tsig_freq_lsb"}, /* Internal sinus test generator frequency control , */\
+ { 0xcf02, "tsig_freq_msb"}, /* Select internal sinus test generator, frequency control msb bits, */\
+ { 0xcf33, "tsig_gain"}, /* Test signal gain , */\
+ { 0xd000, "adc10_reset"}, /* Reset for ADC10 - I2C direct control mode , */\
+ { 0xd011, "adc10_test"}, /* Test mode selection signal for ADC10 - I2C direct control mode, */\
+ { 0xd032, "adc10_sel"}, /* Select the input to convert for ADC10 - I2C direct control mode, */\
+ { 0xd064, "adc10_prog_sample"}, /* ADC10 program sample setting - I2C direct control mode, */\
+ { 0xd0b0, "adc10_enbl"}, /* Enable ADC10 - I2C direct control mode , */\
+ { 0xd0c0, "bypass_lp_vbat"}, /* Bypass control for Low pass filter in batt sensor , */\
+ { 0xd109, "data_adc10_tempbat"}, /* ADC 10 data output data for testing , */\
+ { 0xd201, "clkdiv_audio_sel"}, /* Audio clock divider selection in direct clock control mode, */\
+ { 0xd221, "clkdiv_muxa_sel"}, /* DCDC MUXA clock divider selection in direct clock control mode, */\
+ { 0xd241, "clkdiv_muxb_sel"}, /* DCDC MUXB clock divider selection in direct clock control mode, */\
+ { 0xd301, "int_ehs"}, /* Speed/load setting for INT IO cell, clk or data mode range (see SLIMMF IO datasheet), */\
+ { 0xd321, "datao_ehs"}, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO datasheet), */\
+ { 0xd340, "hs_mode"}, /* I2C high speed mode control , */\
+ { 0xd407, "ctrl_digtoana_hidden"}, /* Spare digital to analog control bits - Hidden , */\
+ { 0xd480, "enbl_clk_out_of_range"}, /* Clock out of range , */\
+ { 0xd491, "sel_wdt_clk"}, /* Watch dog clock divider settings , */\
+ { 0xd4b0, "inject_tsig"}, /* Control bit to switch to internal sinus test generator, */\
+ { 0xd500, "source_in_testmode"}, /* TDM source in test mode (return only current and voltage sense), */\
+ { 0xd510, "gainatt_feedback"}, /* Gainatt feedback to tdm , */\
+ { 0xd522, "test_parametric_io"}, /* Test IO parametric , */\
+ { 0xd550, "ctrl_bst_clk_lp1"}, /* Boost clock control in low power mode1 , */\
+ { 0xd561, "test_spare_out1"}, /* Test spare out 1 , */\
+ { 0xd580, "bst_dcmbst"}, /* DCM boost , */\
+ { 0xd593, "test_spare_out2"}, /* Test spare out 2 , */\
+ { 0xe00f, "sw_profile"}, /* Software profile data , */\
+ { 0xe10f, "sw_vstep"}, /* Software vstep information , */\
+ { 0xf000, "calibration_onetime"}, /* Calibration schedule , */\
+ { 0xf010, "calibr_ron_done"}, /* Calibration Ron executed , */\
+ { 0xf020, "calibr_dcdc_api_calibrate"}, /* Calibration current limit DCDC , */\
+ { 0xf030, "calibr_dcdc_delta_sign"}, /* Sign bit for delta calibration current limit DCDC , */\
+ { 0xf042, "calibr_dcdc_delta"}, /* Calibration delta current limit DCDC , */\
+ { 0xf078, "calibr_speaker_info"}, /* Reserved space for allowing customer to store speaker information, */\
+ { 0xf105, "calibr_vout_offset"}, /* DCDC offset calibration 2's complement (key1 protected), */\
+ { 0xf163, "calibr_vbg_trim"}, /* Bandgap trimming control , */\
+ { 0xf203, "calibr_gain"}, /* HW gain module (2's complement) , */\
+ { 0xf245, "calibr_offset"}, /* Offset for amplifier, HW gain module (2's complement), */\
+ { 0xf307, "calibr_gain_vs"}, /* Voltage sense gain , */\
+ { 0xf387, "calibr_gain_cs"}, /* Current sense gain (signed two's complement format), */\
+ { 0xf40f, "mtpdata4"}, /* MTP4 data , */\
+ { 0xf50f, "calibr_R25C"}, /* Ron resistance of speaker coil , */\
+ { 0xf60f, "mtpdata6"}, /* MTP6 data , */\
+ { 0xf706, "ctrl_offset_a"}, /* Offset of level shifter A , */\
+ { 0xf786, "ctrl_offset_b"}, /* Offset of amplifier level shifter B , */\
+ { 0xf806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
+ { 0xf870, "htol_iic_addr_en"}, /* HTOL I2C address enable control , */\
+ { 0xf884, "calibr_temp_offset"}, /* Temperature offset 2's compliment (key1 protected), */\
+ { 0xf8d2, "calibr_temp_gain"}, /* Temperature gain 2's compliment (key1 protected) , */\
+ { 0xf900, "mtp_lock_dcdcoff_mode"}, /* Disable functionality of dcdcoff_mode bit , */\
+ { 0xf910, "mtp_lock_enbl_coolflux"}, /* Disable functionality of enbl_coolflux bit , */\
+ { 0xf920, "mtp_lock_bypass_clipper"}, /* Disable function bypass_clipper , */\
+ { 0xf930, "mtp_enbl_pwm_delay_clock_gating"}, /* PWM delay clock auto gating , */\
+ { 0xf940, "mtp_enbl_ocp_clock_gating"}, /* OCP clock auto gating , */\
+ { 0xf950, "mtp_gate_cgu_clock_for_test"}, /* CGU test clock control , */\
+ { 0xf987, "type_bits_fw"}, /* MTP control for firmware features - See Firmware I2C API document for details, */\
+ { 0xfa0f, "mtpdataA"}, /* MTPdataA , */\
+ { 0xfb0f, "mtpdataB"}, /* MTPdataB , */\
+ { 0xfc0f, "mtpdataC"}, /* MTPdataC , */\
+ { 0xfd0f, "mtpdataD"}, /* MTPdataD , */\
+ { 0xfe0f, "mtpdataE"}, /* MTPdataE , */\
+ { 0xff07, "calibr_osc_delta_ndiv"}, /* Calibration data for OSC1M, signed number representation, */\
+ { 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+
+enum tfa9894_irq {
+ tfa9894_irq_max = -1,
+ tfa9894_irq_all = -1 /* all irqs */};
+
+#define TFA9894_IRQ_NAMETABLE static tfaIrqName_t Tfa9894IrqNames[] = {\
+};
+#endif /* _TFA9894_TFAFIELDNAMES_H */
diff --git a/inc/tfa9894_tfafieldnames_N2.h b/sound/soc/codecs/tfa9894_tfafieldnames_N2.h
similarity index 81%
rename from inc/tfa9894_tfafieldnames_N2.h
rename to sound/soc/codecs/tfa9894_tfafieldnames_N2.h
index f4ff8af..22ac3ae 100644
--- a/inc/tfa9894_tfafieldnames_N2.h
+++ b/sound/soc/codecs/tfa9894_tfafieldnames_N2.h
@@ -1,1123 +1,1123 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _TFA9894_TFAFIELDNAMES_N2_H
-#define _TFA9894_TFAFIELDNAMES_N2_H
-
-
-#define TFA9894N2_I2CVERSION 25.0
-
-typedef enum nxpTfa9894N2BfEnumList {
- TFA9894N2_BF_PWDN = 0x0000, /*!< Powerdown control */
- TFA9894N2_BF_I2CR = 0x0010, /*!< I2C Reset - Auto clear */
- TFA9894N2_BF_CFE = 0x0020, /*!< Enable CoolFlux DSP */
- TFA9894N2_BF_AMPE = 0x0030, /*!< Enable Amplifier */
- TFA9894N2_BF_DCA = 0x0040, /*!< Enable DCDC Boost converter */
- TFA9894N2_BF_SBSL = 0x0050, /*!< Coolflux configured */
- TFA9894N2_BF_AMPC = 0x0060, /*!< CoolFlux control over amplifier */
- TFA9894N2_BF_INTP = 0x0071, /*!< Interrupt config */
- TFA9894N2_BF_FSSSEL= 0x0090, /*!< Audio sample reference */
- TFA9894N2_BF_BYPOCP= 0x00a0, /*!< Bypass OCP */
- TFA9894N2_BF_TSTOCP= 0x00b0, /*!< OCP testing control */
- TFA9894N2_BF_BSSS = 0x00c0, /*!< Vbat protection steepness */
- TFA9894N2_BF_HPFBYP= 0x00d0, /*!< Bypass High Pass Filter */
- TFA9894N2_BF_DPSA = 0x00e0, /*!< Enable DPSA */
- TFA9894N2_BF_AMPINSEL= 0x0101, /*!< Amplifier input selection */
- TFA9894N2_BF_MANSCONF= 0x0120, /*!< Device I2C settings configured */
- TFA9894N2_BF_MANCOLD= 0x0130, /*!< Execute cold start */
- TFA9894N2_BF_MANROBOD= 0x0140, /*!< Reaction on BOD */
- TFA9894N2_BF_BODE = 0x0150, /*!< Enable BOD (only in direct control mode) */
- TFA9894N2_BF_BODHYS= 0x0160, /*!< Enable Hysteresis of BOD */
- TFA9894N2_BF_BODFILT= 0x0171, /*!< BOD filter */
- TFA9894N2_BF_BODTHLVL= 0x0191, /*!< BOD threshold */
- TFA9894N2_BF_MUTETO= 0x01b0, /*!< Time out SB mute sequence */
- TFA9894N2_BF_MANWDE= 0x01c0, /*!< Watchdog enable */
- TFA9894N2_BF_OPENMTP= 0x01e0, /*!< Control for FAIM protection */
- TFA9894N2_BF_FAIMVBGOVRRL= 0x01f0, /*!< Overrule the enabling of VBG for faim erase/write access */
- TFA9894N2_BF_AUDFS = 0x0203, /*!< Audio sample rate Fs */
- TFA9894N2_BF_INPLEV= 0x0240, /*!< TDM output attenuation */
- TFA9894N2_BF_FRACTDEL= 0x0255, /*!< Current sense fractional delay */
- TFA9894N2_BF_TDMPRES= 0x02b1, /*!< Control for HW manager */
- TFA9894N2_BF_AMPOCRT= 0x02d2, /*!< Amplifier on-off criteria for shutdown */
- TFA9894N2_BF_REV = 0x030f, /*!< Revision info */
- TFA9894N2_BF_REFCKEXT= 0x0401, /*!< PLL external reference clock */
- TFA9894N2_BF_REFCKSEL= 0x0420, /*!< PLL internal reference clock */
- TFA9894N2_BF_MCLKSEL= 0x0432, /*!< Master Clock Selection */
- TFA9894N2_BF_MANAOOSC= 0x0460, /*!< Internal OSC1M off at PWDN */
- TFA9894N2_BF_ACKCLDDIS= 0x0470, /*!< Automatic PLL reference clock selection for cold start */
- TFA9894N2_BF_FSSYNCEN= 0x0480, /*!< Enable FS synchronisation for clock divider */
- TFA9894N2_BF_CLKREFSYNCEN= 0x0490, /*!< Enable PLL reference clock synchronisation for clock divider */
- TFA9894N2_BF_PLLSTUP= 0x04a0, /*!< PLL startup time configuration */
- TFA9894N2_BF_CGUSYNCDCG= 0x0500, /*!< Clock gating control for CGU synchronisation module */
- TFA9894N2_BF_SPKSSEN= 0x0510, /*!< Enable speaker sub-system */
- TFA9894N2_BF_MTPSSEN= 0x0520, /*!< Enable FAIM sub-system */
- TFA9894N2_BF_WDTCLKEN= 0x0530, /*!< Enable Coolflux watchdog clock */
- TFA9894N2_BF_VDDS = 0x1000, /*!< POR */
- TFA9894N2_BF_PLLS = 0x1010, /*!< PLL Lock */
- TFA9894N2_BF_OTDS = 0x1020, /*!< OTP alarm */
- TFA9894N2_BF_OVDS = 0x1030, /*!< OVP alarm */
- TFA9894N2_BF_UVDS = 0x1040, /*!< UVP alarm */
- TFA9894N2_BF_OCDS = 0x1050, /*!< OCP amplifier (sticky register, clear on read) */
- TFA9894N2_BF_CLKS = 0x1060, /*!< Clocks stable */
- TFA9894N2_BF_MTPB = 0x1070, /*!< MTP busy */
- TFA9894N2_BF_NOCLK = 0x1080, /*!< Lost clock */
- TFA9894N2_BF_ACS = 0x1090, /*!< Cold Start */
- TFA9894N2_BF_WDS = 0x10a0, /*!< Watchdog */
- TFA9894N2_BF_SWS = 0x10b0, /*!< Amplifier engage */
- TFA9894N2_BF_AMPS = 0x10c0, /*!< Amplifier enable */
- TFA9894N2_BF_AREFS = 0x10d0, /*!< References enable */
- TFA9894N2_BF_ADCCR = 0x10e0, /*!< Control ADC */
- TFA9894N2_BF_BODNOK= 0x10f0, /*!< BOD Flag - VDD NOT OK */
- TFA9894N2_BF_DCIL = 0x1100, /*!< DCDC current limiting */
- TFA9894N2_BF_DCDCA = 0x1110, /*!< DCDC active (sticky register, clear on read) */
- TFA9894N2_BF_DCOCPOK= 0x1120, /*!< DCDC OCP nmos (sticky register, clear on read) */
- TFA9894N2_BF_DCHVBAT= 0x1140, /*!< DCDC level 1x */
- TFA9894N2_BF_DCH114= 0x1150, /*!< DCDC level 1.14x */
- TFA9894N2_BF_DCH107= 0x1160, /*!< DCDC level 1.07x */
- TFA9894N2_BF_SPKS = 0x1170, /*!< Speaker status */
- TFA9894N2_BF_CLKOOR= 0x1180, /*!< External clock status */
- TFA9894N2_BF_MANALARM= 0x1190, /*!< Alarm state */
- TFA9894N2_BF_TDMERR= 0x11a0, /*!< TDM error */
- TFA9894N2_BF_TDMLUTER= 0x11b0, /*!< TDM lookup table error */
- TFA9894N2_BF_NOAUDCLK= 0x11c0, /*!< Lost Audio clock */
- TFA9894N2_BF_OCPOAP= 0x1200, /*!< OCPOK pmos A */
- TFA9894N2_BF_OCPOAN= 0x1210, /*!< OCPOK nmos A */
- TFA9894N2_BF_OCPOBP= 0x1220, /*!< OCPOK pmos B */
- TFA9894N2_BF_OCPOBN= 0x1230, /*!< OCPOK nmos B */
- TFA9894N2_BF_CLIPS = 0x1240, /*!< Amplifier clipping */
- TFA9894N2_BF_MANMUTE= 0x1250, /*!< Audio mute sequence */
- TFA9894N2_BF_MANOPER= 0x1260, /*!< Device in Operating state */
- TFA9894N2_BF_LP1 = 0x1270, /*!< Low power MODE1 detection */
- TFA9894N2_BF_LA = 0x1280, /*!< Low amplitude detection */
- TFA9894N2_BF_VDDPH = 0x1290, /*!< VDDP greater than VBAT flag */
- TFA9894N2_BF_TDMSTAT= 0x1302, /*!< TDM Status bits */
- TFA9894N2_BF_MANSTATE= 0x1333, /*!< Device Manager status */
- TFA9894N2_BF_DCMODE= 0x13b1, /*!< DCDC mode status bits */
- TFA9894N2_BF_BATS = 0x1509, /*!< Battery voltage (V) */
- TFA9894N2_BF_TEMPS = 0x1608, /*!< IC Temperature (C) */
- TFA9894N2_BF_VDDPS = 0x1709, /*!< IC VDDP voltage (1023*VDDP/13V) */
- TFA9894N2_BF_TDME = 0x2000, /*!< Enable interface */
- TFA9894N2_BF_TDMSPKE= 0x2010, /*!< Control audio tdm channel in sink0 */
- TFA9894N2_BF_TDMDCE= 0x2020, /*!< Control audio tdm channel in sink1 */
- TFA9894N2_BF_TDMCSE= 0x2030, /*!< Source 0 enable */
- TFA9894N2_BF_TDMVSE= 0x2040, /*!< Source 1 enable */
- TFA9894N2_BF_TDMCFE= 0x2050, /*!< Source 2 enable */
- TFA9894N2_BF_TDMCF2E= 0x2060, /*!< Source 3 enable */
- TFA9894N2_BF_TDMCLINV= 0x2070, /*!< Reception data to BCK clock */
- TFA9894N2_BF_TDMFSPOL= 0x2080, /*!< FS polarity */
- TFA9894N2_BF_TDMDEL= 0x2090, /*!< Data delay to FS */
- TFA9894N2_BF_TDMADJ= 0x20a0, /*!< Data adjustment */
- TFA9894N2_BF_TDMOOMP= 0x20b1, /*!< Received audio compression */
- TFA9894N2_BF_TDMNBCK= 0x2103, /*!< TDM NBCK - Bit clock to FS ratio */
- TFA9894N2_BF_TDMFSLN= 0x2143, /*!< FS length (master mode only) */
- TFA9894N2_BF_TDMSLOTS= 0x2183, /*!< N-slots in Frame */
- TFA9894N2_BF_TDMTXDFO= 0x21c1, /*!< Format unused bits */
- TFA9894N2_BF_TDMTXUS0= 0x21e1, /*!< Format unused slots DATAO */
- TFA9894N2_BF_TDMSLLN= 0x2204, /*!< N-bits in slot */
- TFA9894N2_BF_TDMBRMG= 0x2254, /*!< N-bits remaining */
- TFA9894N2_BF_TDMSSIZE= 0x22a4, /*!< Sample size per slot */
- TFA9894N2_BF_TDMSPKS= 0x2303, /*!< TDM slot for sink 0 */
- TFA9894N2_BF_TDMDCS= 0x2343, /*!< TDM slot for sink 1 */
- TFA9894N2_BF_TDMCFSEL= 0x2381, /*!< TDM Source 2 data selection */
- TFA9894N2_BF_TDMCF2SEL= 0x23a1, /*!< TDM Source 3 data selection */
- TFA9894N2_BF_TDMCSS= 0x2403, /*!< Slot position of source 0 data */
- TFA9894N2_BF_TDMVSS= 0x2443, /*!< Slot position of source 1 data */
- TFA9894N2_BF_TDMCFS= 0x2483, /*!< Slot position of source 2 data */
- TFA9894N2_BF_TDMCF2S= 0x24c3, /*!< Slot position of source 3 data */
- TFA9894N2_BF_ISTVDDS= 0x4000, /*!< Status POR */
- TFA9894N2_BF_ISTBSTOC= 0x4010, /*!< Status DCDC OCP */
- TFA9894N2_BF_ISTOTDS= 0x4020, /*!< Status OTP alarm */
- TFA9894N2_BF_ISTOCPR= 0x4030, /*!< Status OCP alarm */
- TFA9894N2_BF_ISTUVDS= 0x4040, /*!< Status UVP alarm */
- TFA9894N2_BF_ISTMANALARM= 0x4050, /*!< Status manager alarm state */
- TFA9894N2_BF_ISTTDMER= 0x4060, /*!< Status TDM error */
- TFA9894N2_BF_ISTNOCLK= 0x4070, /*!< Status lost clock */
- TFA9894N2_BF_ISTCFMER= 0x4080, /*!< Status cfma error */
- TFA9894N2_BF_ISTCFMAC= 0x4090, /*!< Status cfma ack */
- TFA9894N2_BF_ISTSPKS= 0x40a0, /*!< Status coolflux speaker error */
- TFA9894N2_BF_ISTACS= 0x40b0, /*!< Status cold started */
- TFA9894N2_BF_ISTWDS= 0x40c0, /*!< Status watchdog reset */
- TFA9894N2_BF_ISTBODNOK= 0x40d0, /*!< Status brown out detect */
- TFA9894N2_BF_ISTLP1= 0x40e0, /*!< Status low power mode1 detect */
- TFA9894N2_BF_ISTCLKOOR= 0x40f0, /*!< Status clock out of range */
- TFA9894N2_BF_ICLVDDS= 0x4400, /*!< Clear POR */
- TFA9894N2_BF_ICLBSTOC= 0x4410, /*!< Clear DCDC OCP */
- TFA9894N2_BF_ICLOTDS= 0x4420, /*!< Clear OTP alarm */
- TFA9894N2_BF_ICLOCPR= 0x4430, /*!< Clear OCP alarm */
- TFA9894N2_BF_ICLUVDS= 0x4440, /*!< Clear UVP alarm */
- TFA9894N2_BF_ICLMANALARM= 0x4450, /*!< Clear manager alarm state */
- TFA9894N2_BF_ICLTDMER= 0x4460, /*!< Clear TDM error */
- TFA9894N2_BF_ICLNOCLK= 0x4470, /*!< Clear lost clk */
- TFA9894N2_BF_ICLCFMER= 0x4480, /*!< Clear cfma err */
- TFA9894N2_BF_ICLCFMAC= 0x4490, /*!< Clear cfma ack */
- TFA9894N2_BF_ICLSPKS= 0x44a0, /*!< Clear coolflux speaker error */
- TFA9894N2_BF_ICLACS= 0x44b0, /*!< Clear cold started */
- TFA9894N2_BF_ICLWDS= 0x44c0, /*!< Clear watchdog reset */
- TFA9894N2_BF_ICLBODNOK= 0x44d0, /*!< Clear brown out detect */
- TFA9894N2_BF_ICLLP1= 0x44e0, /*!< Clear low power mode1 detect */
- TFA9894N2_BF_ICLCLKOOR= 0x44f0, /*!< Clear clock out of range */
- TFA9894N2_BF_IEVDDS= 0x4800, /*!< Enable POR */
- TFA9894N2_BF_IEBSTOC= 0x4810, /*!< Enable DCDC OCP */
- TFA9894N2_BF_IEOTDS= 0x4820, /*!< Enable OTP alarm */
- TFA9894N2_BF_IEOCPR= 0x4830, /*!< Enable OCP alarm */
- TFA9894N2_BF_IEUVDS= 0x4840, /*!< Enable UVP alarm */
- TFA9894N2_BF_IEMANALARM= 0x4850, /*!< Enable Manager Alarm state */
- TFA9894N2_BF_IETDMER= 0x4860, /*!< Enable TDM error */
- TFA9894N2_BF_IENOCLK= 0x4870, /*!< Enable lost clk */
- TFA9894N2_BF_IECFMER= 0x4880, /*!< Enable cfma err */
- TFA9894N2_BF_IECFMAC= 0x4890, /*!< Enable cfma ack */
- TFA9894N2_BF_IESPKS= 0x48a0, /*!< Enable coolflux speaker error */
- TFA9894N2_BF_IEACS = 0x48b0, /*!< Enable cold started */
- TFA9894N2_BF_IEWDS = 0x48c0, /*!< Enable watchdog reset */
- TFA9894N2_BF_IEBODNOK= 0x48d0, /*!< Enable brown out detect */
- TFA9894N2_BF_IELP1 = 0x48e0, /*!< Enable low power mode1 detect */
- TFA9894N2_BF_IECLKOOR= 0x48f0, /*!< Enable clock out of range */
- TFA9894N2_BF_IPOVDDS= 0x4c00, /*!< Polarity POR */
- TFA9894N2_BF_IPOBSTOC= 0x4c10, /*!< Polarity DCDC OCP */
- TFA9894N2_BF_IPOOTDS= 0x4c20, /*!< Polarity OTP alarm */
- TFA9894N2_BF_IPOOCPR= 0x4c30, /*!< Polarity ocp alarm */
- TFA9894N2_BF_IPOUVDS= 0x4c40, /*!< Polarity UVP alarm */
- TFA9894N2_BF_IPOMANALARM= 0x4c50, /*!< Polarity manager alarm state */
- TFA9894N2_BF_IPOTDMER= 0x4c60, /*!< Polarity TDM error */
- TFA9894N2_BF_IPONOCLK= 0x4c70, /*!< Polarity lost clk */
- TFA9894N2_BF_IPOCFMER= 0x4c80, /*!< Polarity cfma err */
- TFA9894N2_BF_IPOCFMAC= 0x4c90, /*!< Polarity cfma ack */
- TFA9894N2_BF_IPOSPKS= 0x4ca0, /*!< Polarity coolflux speaker error */
- TFA9894N2_BF_IPOACS= 0x4cb0, /*!< Polarity cold started */
- TFA9894N2_BF_IPOWDS= 0x4cc0, /*!< Polarity watchdog reset */
- TFA9894N2_BF_IPOBODNOK= 0x4cd0, /*!< Polarity brown out detect */
- TFA9894N2_BF_IPOLP1= 0x4ce0, /*!< Polarity low power mode1 detect */
- TFA9894N2_BF_IPOCLKOOR= 0x4cf0, /*!< Polarity clock out of range */
- TFA9894N2_BF_BSSCR = 0x5001, /*!< Battery safeguard attack time */
- TFA9894N2_BF_BSST = 0x5023, /*!< Battery safeguard threshold voltage level */
- TFA9894N2_BF_BSSRL = 0x5061, /*!< Battery safeguard maximum reduction */
- TFA9894N2_BF_BSSRR = 0x5082, /*!< Battery safeguard release time */
- TFA9894N2_BF_BSSHY = 0x50b1, /*!< Battery Safeguard hysteresis */
- TFA9894N2_BF_BSSR = 0x50e0, /*!< Battery voltage read out */
- TFA9894N2_BF_BSSBY = 0x50f0, /*!< Bypass HW clipper */
- TFA9894N2_BF_CFSM = 0x5130, /*!< Coolflux firmware soft mute control */
- TFA9894N2_BF_VOL = 0x5187, /*!< CF firmware volume control */
- TFA9894N2_BF_CLIPCTRL= 0x5202, /*!< Clip control setting */
- TFA9894N2_BF_SLOPEE= 0x5230, /*!< Enables slope control */
- TFA9894N2_BF_SLOPESET= 0x5240, /*!< Slope speed setting (binary coded) */
- TFA9894N2_BF_BYPDLYLINE= 0x5250, /*!< Bypass the interpolator delay line */
- TFA9894N2_BF_AMPGAIN= 0x5287, /*!< Amplifier gain */
- TFA9894N2_BF_TDMDCG= 0x5703, /*!< Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE) */
- TFA9894N2_BF_TDMSPKG= 0x5743, /*!< Total gain depending on INPLEV setting (channel 0) */
- TFA9894N2_BF_DCINSEL= 0x5781, /*!< VAMP_OUT2 input selection */
- TFA9894N2_BF_LNMODE= 0x5881, /*!< Low noise gain mode control */
- TFA9894N2_BF_LPM1MODE= 0x5ac1, /*!< Low power mode control */
- TFA9894N2_BF_TDMSRCMAP= 0x5d02, /*!< TDM source mapping */
- TFA9894N2_BF_TDMSRCAS= 0x5d31, /*!< Sensed value A */
- TFA9894N2_BF_TDMSRCBS= 0x5d51, /*!< Sensed value B */
- TFA9894N2_BF_TDMSRCACLIP= 0x5d71, /*!< Clip information (analog /digital) for source0 */
- TFA9894N2_BF_TDMSRCBCLIP= 0x5d91, /*!< Clip information (analog /digital) for source1 */
- TFA9894N2_BF_DELCURCOMP= 0x6102, /*!< Delay to allign compensation signal with current sense signal */
- TFA9894N2_BF_SIGCURCOMP= 0x6130, /*!< Polarity of compensation for current sense */
- TFA9894N2_BF_ENCURCOMP= 0x6140, /*!< Enable current sense compensation */
- TFA9894N2_BF_LVLCLPPWM= 0x6152, /*!< Set the amount of pwm pulse that may be skipped before clip-flag is triggered */
- TFA9894N2_BF_DCVOF = 0x7005, /*!< First Boost Voltage Level */
- TFA9894N2_BF_DCVOS = 0x7065, /*!< Second Boost Voltage Level */
- TFA9894N2_BF_DCMCC = 0x70c3, /*!< Max Coil Current */
- TFA9894N2_BF_DCCV = 0x7101, /*!< Slope compensation current, represents LxF (inductance x frequency) value */
- TFA9894N2_BF_DCIE = 0x7120, /*!< Adaptive boost mode */
- TFA9894N2_BF_DCSR = 0x7130, /*!< Soft ramp up/down */
- TFA9894N2_BF_DCDIS = 0x7140, /*!< DCDC on/off */
- TFA9894N2_BF_DCPWM = 0x7150, /*!< DCDC PWM only mode */
- TFA9894N2_BF_DCTRACK= 0x7160, /*!< Boost algorithm selection, effective only when boost_intelligent is set to 1 */
- TFA9894N2_BF_DCENVSEL= 0x7170, /*!< Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1 */
- TFA9894N2_BF_OVSCTLVL= 0x7195, /*!< Threshold level to activate active overshoot control */
- TFA9894N2_BF_DCTRIP= 0x7204, /*!< 1st adaptive boost trip levels, effective only when DCIE is set to 1 */
- TFA9894N2_BF_DCTRIP2= 0x7254, /*!< 2nd adaptive boost trip levels, effective only when DCIE is set to 1 */
- TFA9894N2_BF_DCTRIPT= 0x72a4, /*!< Track adaptive boost trip levels, effective only when boost_intelligent is set to 1 */
- TFA9894N2_BF_DCTRIPHYSTE= 0x72f0, /*!< Enable hysteresis on booster trip levels */
- TFA9894N2_BF_DCHOLD= 0x7304, /*!< Hold time / Hysteresis for DCDC booster, effective only when boost_intelligent is set to 1 */
- TFA9894N2_BF_RST = 0x9000, /*!< Reset for Coolflux DSP */
- TFA9894N2_BF_DMEM = 0x9011, /*!< Target memory for CFMA using I2C interface */
- TFA9894N2_BF_AIF = 0x9030, /*!< Auto increment */
- TFA9894N2_BF_CFINT = 0x9040, /*!< Coolflux Interrupt - auto clear */
- TFA9894N2_BF_CFCGATE= 0x9050, /*!< Coolflux clock gating disabling control */
- TFA9894N2_BF_REQCMD= 0x9080, /*!< Firmware event request rpc command */
- TFA9894N2_BF_REQRST= 0x9090, /*!< Firmware event request reset restart */
- TFA9894N2_BF_REQMIPS= 0x90a0, /*!< Firmware event request short on mips */
- TFA9894N2_BF_REQMUTED= 0x90b0, /*!< Firmware event request mute sequence ready */
- TFA9894N2_BF_REQVOL= 0x90c0, /*!< Firmware event request volume ready */
- TFA9894N2_BF_REQDMG= 0x90d0, /*!< Firmware event request speaker damage detected */
- TFA9894N2_BF_REQCAL= 0x90e0, /*!< Firmware event request calibration completed */
- TFA9894N2_BF_REQRSV= 0x90f0, /*!< Firmware event request reserved */
- TFA9894N2_BF_MADD = 0x910f, /*!< CF memory address */
- TFA9894N2_BF_MEMA = 0x920f, /*!< Activate memory access */
- TFA9894N2_BF_ERR = 0x9307, /*!< CF error flags */
- TFA9894N2_BF_ACKCMD= 0x9380, /*!< Firmware event acknowledge rpc command */
- TFA9894N2_BF_ACKRST= 0x9390, /*!< Firmware event acknowledge reset restart */
- TFA9894N2_BF_ACKMIPS= 0x93a0, /*!< Firmware event acknowledge short on mips */
- TFA9894N2_BF_ACKMUTED= 0x93b0, /*!< Firmware event acknowledge mute sequence ready */
- TFA9894N2_BF_ACKVOL= 0x93c0, /*!< Firmware event acknowledge volume ready */
- TFA9894N2_BF_ACKDMG= 0x93d0, /*!< Firmware event acknowledge speaker damage detected */
- TFA9894N2_BF_ACKCAL= 0x93e0, /*!< Firmware event acknowledge calibration completed */
- TFA9894N2_BF_ACKRSV= 0x93f0, /*!< Firmware event acknowledge reserved */
- TFA9894N2_BF_MTPK = 0xa107, /*!< KEY2 to access KEY2 protected registers, customer key */
- TFA9894N2_BF_KEY1LOCKED= 0xa200, /*!< Indicates KEY1 is locked */
- TFA9894N2_BF_KEY2LOCKED= 0xa210, /*!< Indicates KEY2 is locked */
- TFA9894N2_BF_CMTPI = 0xa350, /*!< Start copying all the data from mtp to I2C mtp registers - auto clear */
- TFA9894N2_BF_CIMTP = 0xa360, /*!< Start copying data from I2C mtp registers to mtp - auto clear */
- TFA9894N2_BF_MTPRDMSB= 0xa50f, /*!< MSB word of MTP manual read data */
- TFA9894N2_BF_MTPRDLSB= 0xa60f, /*!< LSB word of MTP manual read data */
- TFA9894N2_BF_EXTTS = 0xb108, /*!< External temperature (C) */
- TFA9894N2_BF_TROS = 0xb190, /*!< Select temp Speaker calibration */
- TFA9894N2_BF_PLLINSELI= 0xca05, /*!< PLL INSELI - PLL direct bandwidth control mode only with pll_bandsel set to 1 */
- TFA9894N2_BF_PLLINSELP= 0xca64, /*!< PLL INSELP - PLL direct bandwidth control mode only with pll_bandsel set to 1 */
- TFA9894N2_BF_PLLINSELR= 0xcab3, /*!< PLL INSELR - PLL direct bandwidth control mode only with pll_bandsel set to 1 */
- TFA9894N2_BF_PLLNDEC= 0xcb09, /*!< PLL NDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
- TFA9894N2_BF_PLLMDECMSB= 0xcba0, /*!< MSB of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
- TFA9894N2_BF_PLLBYPASS= 0xcbb0, /*!< PLL bypass control during functional mode */
- TFA9894N2_BF_PLLDIRECTI= 0xcbc0, /*!< PLL directi control in direct control mode only, use_direct_pll_ctrl set to 1 */
- TFA9894N2_BF_PLLDIRECTO= 0xcbd0, /*!< PLL directo control in direct control mode only, use_direct_pll_ctrl set to 1 */
- TFA9894N2_BF_PLLFRMSTBL= 0xcbe0, /*!< PLL FRM clock stable control in direct control mode only, use_direct_pll_ctrl set to 1 */
- TFA9894N2_BF_PLLFRM= 0xcbf0, /*!< PLL free running mode control in functional mode */
- TFA9894N2_BF_PLLMDECLSB= 0xcc0f, /*!< Bits 15..0 of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
- TFA9894N2_BF_PLLPDEC= 0xcd06, /*!< PLL PDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
- TFA9894N2_BF_DIRECTPLL= 0xcd70, /*!< Enabled PLL direct control mode, overrules the PLL LUT with I2C register values */
- TFA9894N2_BF_DIRECTCLK= 0xcd80, /*!< Enabled CGU clock divider direct control mode */
- TFA9894N2_BF_PLLLIM= 0xcd90, /*!< PLL up limiter control in PLL direct bandwidth control mode, pll_bandsel set to 1 */
- TFA9894N2_BF_SWPROFIL= 0xe00f, /*!< Software profile data */
- TFA9894N2_BF_SWVSTEP= 0xe10f, /*!< Software vstep information */
- TFA9894N2_BF_MTPOTC= 0xf000, /*!< Calibration schedule */
- TFA9894N2_BF_MTPEX = 0xf010, /*!< Calibration Ron executed */
- TFA9894N2_BF_DCMCCAPI= 0xf020, /*!< Calibration current limit DCDC */
- TFA9894N2_BF_DCMCCSB= 0xf030, /*!< Sign bit for delta calibration current limit DCDC */
- TFA9894N2_BF_USERDEF= 0xf042, /*!< Calibration delta current limit DCDC */
- TFA9894N2_BF_CUSTINFO= 0xf078, /*!< Reserved space for allowing customer to store speaker information */
- TFA9894N2_BF_R25C = 0xf50f, /*!< Ron resistance of speaker coil */
-} nxpTfa9894N2BfEnumList_t;
-#define TFA9894N2_NAMETABLE static tfaBfName_t Tfa9894N2DatasheetNames[]= {\
- { 0x0, "PWDN"}, /* Powerdown control , */\
- { 0x10, "I2CR"}, /* I2C Reset - Auto clear , */\
- { 0x20, "CFE"}, /* Enable CoolFlux DSP , */\
- { 0x30, "AMPE"}, /* Enable Amplifier , */\
- { 0x40, "DCA"}, /* Enable DCDC Boost converter , */\
- { 0x50, "SBSL"}, /* Coolflux configured , */\
- { 0x60, "AMPC"}, /* CoolFlux control over amplifier , */\
- { 0x71, "INTP"}, /* Interrupt config , */\
- { 0x90, "FSSSEL"}, /* Audio sample reference , */\
- { 0xa0, "BYPOCP"}, /* Bypass OCP , */\
- { 0xb0, "TSTOCP"}, /* OCP testing control , */\
- { 0xc0, "BSSS"}, /* Vbat protection steepness , */\
- { 0xd0, "HPFBYP"}, /* Bypass High Pass Filter , */\
- { 0xe0, "DPSA"}, /* Enable DPSA , */\
- { 0x101, "AMPINSEL"}, /* Amplifier input selection , */\
- { 0x120, "MANSCONF"}, /* Device I2C settings configured , */\
- { 0x130, "MANCOLD"}, /* Execute cold start , */\
- { 0x140, "MANROBOD"}, /* Reaction on BOD , */\
- { 0x150, "BODE"}, /* Enable BOD (only in direct control mode) , */\
- { 0x160, "BODHYS"}, /* Enable Hysteresis of BOD , */\
- { 0x171, "BODFILT"}, /* BOD filter , */\
- { 0x191, "BODTHLVL"}, /* BOD threshold , */\
- { 0x1b0, "MUTETO"}, /* Time out SB mute sequence , */\
- { 0x1c0, "MANWDE"}, /* Watchdog enable , */\
- { 0x1e0, "OPENMTP"}, /* Control for FAIM protection , */\
- { 0x1f0, "FAIMVBGOVRRL"}, /* Overrule the enabling of VBG for faim erase/write access, */\
- { 0x203, "AUDFS"}, /* Audio sample rate Fs , */\
- { 0x240, "INPLEV"}, /* TDM output attenuation , */\
- { 0x255, "FRACTDEL"}, /* Current sense fractional delay , */\
- { 0x2b1, "TDMPRES"}, /* Control for HW manager , */\
- { 0x2d2, "AMPOCRT"}, /* Amplifier on-off criteria for shutdown , */\
- { 0x30f, "REV"}, /* Revision info , */\
- { 0x401, "REFCKEXT"}, /* PLL external reference clock , */\
- { 0x420, "REFCKSEL"}, /* PLL internal reference clock , */\
- { 0x432, "MCLKSEL"}, /* Master Clock Selection , */\
- { 0x460, "MANAOOSC"}, /* Internal OSC1M off at PWDN , */\
- { 0x470, "ACKCLDDIS"}, /* Automatic PLL reference clock selection for cold start, */\
- { 0x480, "FSSYNCEN"}, /* Enable FS synchronisation for clock divider , */\
- { 0x490, "CLKREFSYNCEN"}, /* Enable PLL reference clock synchronisation for clock divider, */\
- { 0x4a0, "PLLSTUP"}, /* PLL startup time configuration , */\
- { 0x500, "CGUSYNCDCG"}, /* Clock gating control for CGU synchronisation module, */\
- { 0x510, "SPKSSEN"}, /* Enable speaker sub-system , */\
- { 0x520, "MTPSSEN"}, /* Enable FAIM sub-system , */\
- { 0x530, "WDTCLKEN"}, /* Enable Coolflux watchdog clock , */\
- { 0x1000, "VDDS"}, /* POR , */\
- { 0x1010, "PLLS"}, /* PLL Lock , */\
- { 0x1020, "OTDS"}, /* OTP alarm , */\
- { 0x1030, "OVDS"}, /* OVP alarm , */\
- { 0x1040, "UVDS"}, /* UVP alarm , */\
- { 0x1050, "OCDS"}, /* OCP amplifier (sticky register, clear on read) , */\
- { 0x1060, "CLKS"}, /* Clocks stable , */\
- { 0x1070, "MTPB"}, /* MTP busy , */\
- { 0x1080, "NOCLK"}, /* Lost clock , */\
- { 0x1090, "ACS"}, /* Cold Start , */\
- { 0x10a0, "WDS"}, /* Watchdog , */\
- { 0x10b0, "SWS"}, /* Amplifier engage , */\
- { 0x10c0, "AMPS"}, /* Amplifier enable , */\
- { 0x10d0, "AREFS"}, /* References enable , */\
- { 0x10e0, "ADCCR"}, /* Control ADC , */\
- { 0x10f0, "BODNOK"}, /* BOD Flag - VDD NOT OK , */\
- { 0x1100, "DCIL"}, /* DCDC current limiting , */\
- { 0x1110, "DCDCA"}, /* DCDC active (sticky register, clear on read) , */\
- { 0x1120, "DCOCPOK"}, /* DCDC OCP nmos (sticky register, clear on read) , */\
- { 0x1140, "DCHVBAT"}, /* DCDC level 1x , */\
- { 0x1150, "DCH114"}, /* DCDC level 1.14x , */\
- { 0x1160, "DCH107"}, /* DCDC level 1.07x , */\
- { 0x1170, "SPKS"}, /* Speaker status , */\
- { 0x1180, "CLKOOR"}, /* External clock status , */\
- { 0x1190, "MANALARM"}, /* Alarm state , */\
- { 0x11a0, "TDMERR"}, /* TDM error , */\
- { 0x11b0, "TDMLUTER"}, /* TDM lookup table error , */\
- { 0x11c0, "NOAUDCLK"}, /* Lost Audio clock , */\
- { 0x1200, "OCPOAP"}, /* OCPOK pmos A , */\
- { 0x1210, "OCPOAN"}, /* OCPOK nmos A , */\
- { 0x1220, "OCPOBP"}, /* OCPOK pmos B , */\
- { 0x1230, "OCPOBN"}, /* OCPOK nmos B , */\
- { 0x1240, "CLIPS"}, /* Amplifier clipping , */\
- { 0x1250, "MANMUTE"}, /* Audio mute sequence , */\
- { 0x1260, "MANOPER"}, /* Device in Operating state , */\
- { 0x1270, "LP1"}, /* Low power MODE1 detection , */\
- { 0x1280, "LA"}, /* Low amplitude detection , */\
- { 0x1290, "VDDPH"}, /* VDDP greater than VBAT flag , */\
- { 0x1302, "TDMSTAT"}, /* TDM Status bits , */\
- { 0x1333, "MANSTATE"}, /* Device Manager status , */\
- { 0x13b1, "DCMODE"}, /* DCDC mode status bits , */\
- { 0x1509, "BATS"}, /* Battery voltage (V) , */\
- { 0x1608, "TEMPS"}, /* IC Temperature (C) , */\
- { 0x1709, "VDDPS"}, /* IC VDDP voltage (1023*VDDP/13V) , */\
- { 0x2000, "TDME"}, /* Enable interface , */\
- { 0x2010, "TDMSPKE"}, /* Control audio tdm channel in sink0 , */\
- { 0x2020, "TDMDCE"}, /* Control audio tdm channel in sink1 , */\
- { 0x2030, "TDMCSE"}, /* Source 0 enable , */\
- { 0x2040, "TDMVSE"}, /* Source 1 enable , */\
- { 0x2050, "TDMCFE"}, /* Source 2 enable , */\
- { 0x2060, "TDMCF2E"}, /* Source 3 enable , */\
- { 0x2070, "TDMCLINV"}, /* Reception data to BCK clock , */\
- { 0x2080, "TDMFSPOL"}, /* FS polarity , */\
- { 0x2090, "TDMDEL"}, /* Data delay to FS , */\
- { 0x20a0, "TDMADJ"}, /* Data adjustment , */\
- { 0x20b1, "TDMOOMP"}, /* Received audio compression , */\
- { 0x2103, "TDMNBCK"}, /* TDM NBCK - Bit clock to FS ratio , */\
- { 0x2143, "TDMFSLN"}, /* FS length (master mode only) , */\
- { 0x2183, "TDMSLOTS"}, /* N-slots in Frame , */\
- { 0x21c1, "TDMTXDFO"}, /* Format unused bits , */\
- { 0x21e1, "TDMTXUS0"}, /* Format unused slots DATAO , */\
- { 0x2204, "TDMSLLN"}, /* N-bits in slot , */\
- { 0x2254, "TDMBRMG"}, /* N-bits remaining , */\
- { 0x22a4, "TDMSSIZE"}, /* Sample size per slot , */\
- { 0x2303, "TDMSPKS"}, /* TDM slot for sink 0 , */\
- { 0x2343, "TDMDCS"}, /* TDM slot for sink 1 , */\
- { 0x2381, "TDMCFSEL"}, /* TDM Source 2 data selection , */\
- { 0x23a1, "TDMCF2SEL"}, /* TDM Source 3 data selection , */\
- { 0x2403, "TDMCSS"}, /* Slot position of source 0 data , */\
- { 0x2443, "TDMVSS"}, /* Slot position of source 1 data , */\
- { 0x2483, "TDMCFS"}, /* Slot position of source 2 data , */\
- { 0x24c3, "TDMCF2S"}, /* Slot position of source 3 data , */\
- { 0x4000, "ISTVDDS"}, /* Status POR , */\
- { 0x4010, "ISTBSTOC"}, /* Status DCDC OCP , */\
- { 0x4020, "ISTOTDS"}, /* Status OTP alarm , */\
- { 0x4030, "ISTOCPR"}, /* Status OCP alarm , */\
- { 0x4040, "ISTUVDS"}, /* Status UVP alarm , */\
- { 0x4050, "ISTMANALARM"}, /* Status manager alarm state , */\
- { 0x4060, "ISTTDMER"}, /* Status TDM error , */\
- { 0x4070, "ISTNOCLK"}, /* Status lost clock , */\
- { 0x4080, "ISTCFMER"}, /* Status cfma error , */\
- { 0x4090, "ISTCFMAC"}, /* Status cfma ack , */\
- { 0x40a0, "ISTSPKS"}, /* Status coolflux speaker error , */\
- { 0x40b0, "ISTACS"}, /* Status cold started , */\
- { 0x40c0, "ISTWDS"}, /* Status watchdog reset , */\
- { 0x40d0, "ISTBODNOK"}, /* Status brown out detect , */\
- { 0x40e0, "ISTLP1"}, /* Status low power mode1 detect , */\
- { 0x40f0, "ISTCLKOOR"}, /* Status clock out of range , */\
- { 0x4400, "ICLVDDS"}, /* Clear POR , */\
- { 0x4410, "ICLBSTOC"}, /* Clear DCDC OCP , */\
- { 0x4420, "ICLOTDS"}, /* Clear OTP alarm , */\
- { 0x4430, "ICLOCPR"}, /* Clear OCP alarm , */\
- { 0x4440, "ICLUVDS"}, /* Clear UVP alarm , */\
- { 0x4450, "ICLMANALARM"}, /* Clear manager alarm state , */\
- { 0x4460, "ICLTDMER"}, /* Clear TDM error , */\
- { 0x4470, "ICLNOCLK"}, /* Clear lost clk , */\
- { 0x4480, "ICLCFMER"}, /* Clear cfma err , */\
- { 0x4490, "ICLCFMAC"}, /* Clear cfma ack , */\
- { 0x44a0, "ICLSPKS"}, /* Clear coolflux speaker error , */\
- { 0x44b0, "ICLACS"}, /* Clear cold started , */\
- { 0x44c0, "ICLWDS"}, /* Clear watchdog reset , */\
- { 0x44d0, "ICLBODNOK"}, /* Clear brown out detect , */\
- { 0x44e0, "ICLLP1"}, /* Clear low power mode1 detect , */\
- { 0x44f0, "ICLCLKOOR"}, /* Clear clock out of range , */\
- { 0x4800, "IEVDDS"}, /* Enable POR , */\
- { 0x4810, "IEBSTOC"}, /* Enable DCDC OCP , */\
- { 0x4820, "IEOTDS"}, /* Enable OTP alarm , */\
- { 0x4830, "IEOCPR"}, /* Enable OCP alarm , */\
- { 0x4840, "IEUVDS"}, /* Enable UVP alarm , */\
- { 0x4850, "IEMANALARM"}, /* Enable Manager Alarm state , */\
- { 0x4860, "IETDMER"}, /* Enable TDM error , */\
- { 0x4870, "IENOCLK"}, /* Enable lost clk , */\
- { 0x4880, "IECFMER"}, /* Enable cfma err , */\
- { 0x4890, "IECFMAC"}, /* Enable cfma ack , */\
- { 0x48a0, "IESPKS"}, /* Enable coolflux speaker error , */\
- { 0x48b0, "IEACS"}, /* Enable cold started , */\
- { 0x48c0, "IEWDS"}, /* Enable watchdog reset , */\
- { 0x48d0, "IEBODNOK"}, /* Enable brown out detect , */\
- { 0x48e0, "IELP1"}, /* Enable low power mode1 detect , */\
- { 0x48f0, "IECLKOOR"}, /* Enable clock out of range , */\
- { 0x4c00, "IPOVDDS"}, /* Polarity POR , */\
- { 0x4c10, "IPOBSTOC"}, /* Polarity DCDC OCP , */\
- { 0x4c20, "IPOOTDS"}, /* Polarity OTP alarm , */\
- { 0x4c30, "IPOOCPR"}, /* Polarity ocp alarm , */\
- { 0x4c40, "IPOUVDS"}, /* Polarity UVP alarm , */\
- { 0x4c50, "IPOMANALARM"}, /* Polarity manager alarm state , */\
- { 0x4c60, "IPOTDMER"}, /* Polarity TDM error , */\
- { 0x4c70, "IPONOCLK"}, /* Polarity lost clk , */\
- { 0x4c80, "IPOCFMER"}, /* Polarity cfma err , */\
- { 0x4c90, "IPOCFMAC"}, /* Polarity cfma ack , */\
- { 0x4ca0, "IPOSPKS"}, /* Polarity coolflux speaker error , */\
- { 0x4cb0, "IPOACS"}, /* Polarity cold started , */\
- { 0x4cc0, "IPOWDS"}, /* Polarity watchdog reset , */\
- { 0x4cd0, "IPOBODNOK"}, /* Polarity brown out detect , */\
- { 0x4ce0, "IPOLP1"}, /* Polarity low power mode1 detect , */\
- { 0x4cf0, "IPOCLKOOR"}, /* Polarity clock out of range , */\
- { 0x5001, "BSSCR"}, /* Battery safeguard attack time , */\
- { 0x5023, "BSST"}, /* Battery safeguard threshold voltage level , */\
- { 0x5061, "BSSRL"}, /* Battery safeguard maximum reduction , */\
- { 0x5082, "BSSRR"}, /* Battery safeguard release time , */\
- { 0x50b1, "BSSHY"}, /* Battery Safeguard hysteresis , */\
- { 0x50e0, "BSSR"}, /* Battery voltage read out , */\
- { 0x50f0, "BSSBY"}, /* Bypass HW clipper , */\
- { 0x5130, "CFSM"}, /* Coolflux firmware soft mute control , */\
- { 0x5187, "VOL"}, /* CF firmware volume control , */\
- { 0x5202, "CLIPCTRL"}, /* Clip control setting , */\
- { 0x5230, "SLOPEE"}, /* Enables slope control , */\
- { 0x5240, "SLOPESET"}, /* Slope speed setting (binary coded) , */\
- { 0x5250, "BYPDLYLINE"}, /* Bypass the interpolator delay line , */\
- { 0x5287, "AMPGAIN"}, /* Amplifier gain , */\
- { 0x5703, "TDMDCG"}, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */\
- { 0x5743, "TDMSPKG"}, /* Total gain depending on INPLEV setting (channel 0), */\
- { 0x5781, "DCINSEL"}, /* VAMP_OUT2 input selection , */\
- { 0x5881, "LNMODE"}, /* Low noise gain mode control , */\
- { 0x5ac1, "LPM1MODE"}, /* Low power mode control , */\
- { 0x5d02, "TDMSRCMAP"}, /* TDM source mapping , */\
- { 0x5d31, "TDMSRCAS"}, /* Sensed value A , */\
- { 0x5d51, "TDMSRCBS"}, /* Sensed value B , */\
- { 0x5d71, "TDMSRCACLIP"}, /* Clip information (analog /digital) for source0 , */\
- { 0x5d91, "TDMSRCBCLIP"}, /* Clip information (analog /digital) for source1 , */\
- { 0x6102, "DELCURCOMP"}, /* Delay to allign compensation signal with current sense signal, */\
- { 0x6130, "SIGCURCOMP"}, /* Polarity of compensation for current sense , */\
- { 0x6140, "ENCURCOMP"}, /* Enable current sense compensation , */\
- { 0x6152, "LVLCLPPWM"}, /* Set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
- { 0x7005, "DCVOF"}, /* First Boost Voltage Level , */\
- { 0x7065, "DCVOS"}, /* Second Boost Voltage Level , */\
- { 0x70c3, "DCMCC"}, /* Max Coil Current , */\
- { 0x7101, "DCCV"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
- { 0x7120, "DCIE"}, /* Adaptive boost mode , */\
- { 0x7130, "DCSR"}, /* Soft ramp up/down , */\
- { 0x7140, "DCDIS"}, /* DCDC on/off , */\
- { 0x7150, "DCPWM"}, /* DCDC PWM only mode , */\
- { 0x7160, "DCTRACK"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
- { 0x7170, "DCENVSEL"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
- { 0x7195, "OVSCTLVL"}, /* Threshold level to activate active overshoot control, */\
- { 0x7204, "DCTRIP"}, /* 1st adaptive boost trip levels, effective only when DCIE is set to 1, */\
- { 0x7254, "DCTRIP2"}, /* 2nd adaptive boost trip levels, effective only when DCIE is set to 1, */\
- { 0x72a4, "DCTRIPT"}, /* Track adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
- { 0x72f0, "DCTRIPHYSTE"}, /* Enable hysteresis on booster trip levels , */\
- { 0x7304, "DCHOLD"}, /* Hold time / Hysteresis for DCDC booster, effective only when boost_intelligent is set to 1, */\
- { 0x9000, "RST"}, /* Reset for Coolflux DSP , */\
- { 0x9011, "DMEM"}, /* Target memory for CFMA using I2C interface , */\
- { 0x9030, "AIF"}, /* Auto increment , */\
- { 0x9040, "CFINT"}, /* Coolflux Interrupt - auto clear , */\
- { 0x9050, "CFCGATE"}, /* Coolflux clock gating disabling control , */\
- { 0x9080, "REQCMD"}, /* Firmware event request rpc command , */\
- { 0x9090, "REQRST"}, /* Firmware event request reset restart , */\
- { 0x90a0, "REQMIPS"}, /* Firmware event request short on mips , */\
- { 0x90b0, "REQMUTED"}, /* Firmware event request mute sequence ready , */\
- { 0x90c0, "REQVOL"}, /* Firmware event request volume ready , */\
- { 0x90d0, "REQDMG"}, /* Firmware event request speaker damage detected , */\
- { 0x90e0, "REQCAL"}, /* Firmware event request calibration completed , */\
- { 0x90f0, "REQRSV"}, /* Firmware event request reserved , */\
- { 0x910f, "MADD"}, /* CF memory address , */\
- { 0x920f, "MEMA"}, /* Activate memory access , */\
- { 0x9307, "ERR"}, /* CF error flags , */\
- { 0x9380, "ACKCMD"}, /* Firmware event acknowledge rpc command , */\
- { 0x9390, "ACKRST"}, /* Firmware event acknowledge reset restart , */\
- { 0x93a0, "ACKMIPS"}, /* Firmware event acknowledge short on mips , */\
- { 0x93b0, "ACKMUTED"}, /* Firmware event acknowledge mute sequence ready , */\
- { 0x93c0, "ACKVOL"}, /* Firmware event acknowledge volume ready , */\
- { 0x93d0, "ACKDMG"}, /* Firmware event acknowledge speaker damage detected, */\
- { 0x93e0, "ACKCAL"}, /* Firmware event acknowledge calibration completed , */\
- { 0x93f0, "ACKRSV"}, /* Firmware event acknowledge reserved , */\
- { 0xa107, "MTPK"}, /* KEY2 to access KEY2 protected registers, customer key, */\
- { 0xa200, "KEY1LOCKED"}, /* Indicates KEY1 is locked , */\
- { 0xa210, "KEY2LOCKED"}, /* Indicates KEY2 is locked , */\
- { 0xa350, "CMTPI"}, /* Start copying all the data from mtp to I2C mtp registers - auto clear, */\
- { 0xa360, "CIMTP"}, /* Start copying data from I2C mtp registers to mtp - auto clear, */\
- { 0xa50f, "MTPRDMSB"}, /* MSB word of MTP manual read data , */\
- { 0xa60f, "MTPRDLSB"}, /* LSB word of MTP manual read data , */\
- { 0xb108, "EXTTS"}, /* External temperature (C) , */\
- { 0xb190, "TROS"}, /* Select temp Speaker calibration , */\
- { 0xca05, "PLLINSELI"}, /* PLL INSELI - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
- { 0xca64, "PLLINSELP"}, /* PLL INSELP - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
- { 0xcab3, "PLLINSELR"}, /* PLL INSELR - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
- { 0xcb09, "PLLNDEC"}, /* PLL NDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
- { 0xcba0, "PLLMDECMSB"}, /* MSB of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
- { 0xcbb0, "PLLBYPASS"}, /* PLL bypass control during functional mode , */\
- { 0xcbc0, "PLLDIRECTI"}, /* PLL directi control in direct control mode only, use_direct_pll_ctrl set to 1, */\
- { 0xcbd0, "PLLDIRECTO"}, /* PLL directo control in direct control mode only, use_direct_pll_ctrl set to 1, */\
- { 0xcbe0, "PLLFRMSTBL"}, /* PLL FRM clock stable control in direct control mode only, use_direct_pll_ctrl set to 1, */\
- { 0xcbf0, "PLLFRM"}, /* PLL free running mode control in functional mode , */\
- { 0xcc0f, "PLLMDECLSB"}, /* Bits 15..0 of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
- { 0xcd06, "PLLPDEC"}, /* PLL PDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
- { 0xcd70, "DIRECTPLL"}, /* Enabled PLL direct control mode, overrules the PLL LUT with I2C register values, */\
- { 0xcd80, "DIRECTCLK"}, /* Enabled CGU clock divider direct control mode , */\
- { 0xcd90, "PLLLIM"}, /* PLL up limiter control in PLL direct bandwidth control mode, pll_bandsel set to 1, */\
- { 0xe00f, "SWPROFIL"}, /* Software profile data , */\
- { 0xe10f, "SWVSTEP"}, /* Software vstep information , */\
- { 0xf000, "MTPOTC"}, /* Calibration schedule , */\
- { 0xf010, "MTPEX"}, /* Calibration Ron executed , */\
- { 0xf020, "DCMCCAPI"}, /* Calibration current limit DCDC , */\
- { 0xf030, "DCMCCSB"}, /* Sign bit for delta calibration current limit DCDC , */\
- { 0xf042, "USERDEF"}, /* Calibration delta current limit DCDC , */\
- { 0xf078, "CUSTINFO"}, /* Reserved space for allowing customer to store speaker information, */\
- { 0xf50f, "R25C"}, /* Ron resistance of speaker coil , */\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-
-#define TFA9894N2_BITNAMETABLE static tfaBfName_t Tfa9894N2BitNames[]= {\
- { 0x0, "powerdown"}, /* Powerdown control , */\
- { 0x10, "reset"}, /* I2C Reset - Auto clear , */\
- { 0x20, "enbl_coolflux"}, /* Enable CoolFlux DSP , */\
- { 0x30, "enbl_amplifier"}, /* Enable Amplifier , */\
- { 0x40, "enbl_boost"}, /* Enable DCDC Boost converter , */\
- { 0x50, "coolflux_configured"}, /* Coolflux configured , */\
- { 0x60, "sel_enbl_amplifier"}, /* CoolFlux control over amplifier , */\
- { 0x71, "int_pad_io"}, /* Interrupt config , */\
- { 0x90, "fs_pulse_sel"}, /* Audio sample reference , */\
- { 0xa0, "bypass_ocp"}, /* Bypass OCP , */\
- { 0xb0, "test_ocp"}, /* OCP testing control , */\
- { 0xc0, "batsense_steepness"}, /* Vbat protection steepness , */\
- { 0xd0, "bypass_hp"}, /* Bypass High Pass Filter , */\
- { 0xe0, "enbl_dpsa"}, /* Enable DPSA , */\
- { 0xf0, "sel_hysteresis"}, /* Select hysteresis for clock range detector , */\
- { 0x101, "vamp_sel1"}, /* Amplifier input selection , */\
- { 0x120, "src_set_configured"}, /* Device I2C settings configured , */\
- { 0x130, "execute_cold_start"}, /* Execute cold start , */\
- { 0x140, "man_enbl_brown_out"}, /* Reaction on BOD , */\
- { 0x150, "bod_enbl"}, /* Enable BOD (only in direct control mode) , */\
- { 0x160, "bod_hyst_enbl"}, /* Enable Hysteresis of BOD , */\
- { 0x171, "bod_delay_set"}, /* BOD filter , */\
- { 0x191, "bod_lvl_set"}, /* BOD threshold , */\
- { 0x1b0, "disable_mute_time_out"}, /* Time out SB mute sequence , */\
- { 0x1c0, "man_enbl_watchdog"}, /* Watchdog enable , */\
- { 0x1d0, "disable_engage"}, /* Disable Engage , */\
- { 0x1e0, "unprotect_faim"}, /* Control for FAIM protection , */\
- { 0x1f0, "faim_enable_vbg"}, /* Overrule the enabling of VBG for faim erase/write access, */\
- { 0x203, "audio_fs"}, /* Audio sample rate Fs , */\
- { 0x240, "input_level"}, /* TDM output attenuation , */\
- { 0x255, "cs_frac_delay"}, /* Current sense fractional delay , */\
- { 0x2b1, "use_tdm_presence"}, /* Control for HW manager , */\
- { 0x2d2, "ctrl_on2off_criterion"}, /* Amplifier on-off criteria for shutdown , */\
- { 0x30f, "device_rev"}, /* Revision info , */\
- { 0x401, "pll_clkin_sel"}, /* PLL external reference clock , */\
- { 0x420, "pll_clkin_sel_osc"}, /* PLL internal reference clock , */\
- { 0x432, "mclk_sel"}, /* Master Clock Selection , */\
- { 0x460, "enbl_osc1m_auto_off"}, /* Internal OSC1M off at PWDN , */\
- { 0x470, "disable_auto_sel_refclk"}, /* Automatic PLL reference clock selection for cold start, */\
- { 0x480, "enbl_fs_sync"}, /* Enable FS synchronisation for clock divider , */\
- { 0x490, "enbl_clkref_sync"}, /* Enable PLL reference clock synchronisation for clock divider, */\
- { 0x4a0, "pll_slow_startup"}, /* PLL startup time configuration , */\
- { 0x500, "disable_cgu_sync_cgate"}, /* Clock gating control for CGU synchronisation module, */\
- { 0x510, "enbl_spkr_ss"}, /* Enable speaker sub-system , */\
- { 0x520, "enbl_faim_ss"}, /* Enable FAIM sub-system , */\
- { 0x530, "enbl_wdt_clk"}, /* Enable Coolflux watchdog clock , */\
- { 0xe07, "ctrl_digtoana"}, /* Spare control from digital to analog , */\
- { 0xf0f, "hidden_code"}, /* Hidden code to enable access to hidden register. (0x5A6B/23147 default for engineering), */\
- { 0x1000, "flag_por"}, /* POR , */\
- { 0x1010, "flag_pll_lock"}, /* PLL Lock , */\
- { 0x1020, "flag_otpok"}, /* OTP alarm , */\
- { 0x1030, "flag_ovpok"}, /* OVP alarm , */\
- { 0x1040, "flag_uvpok"}, /* UVP alarm , */\
- { 0x1050, "flag_ocp_alarm"}, /* OCP amplifier (sticky register, clear on read) , */\
- { 0x1060, "flag_clocks_stable"}, /* Clocks stable , */\
- { 0x1070, "flag_mtp_busy"}, /* MTP busy , */\
- { 0x1080, "flag_lost_clk"}, /* Lost clock , */\
- { 0x1090, "flag_cold_started"}, /* Cold Start , */\
- { 0x10a0, "flag_watchdog_reset"}, /* Watchdog , */\
- { 0x10b0, "flag_engage"}, /* Amplifier engage , */\
- { 0x10c0, "flag_enbl_amp"}, /* Amplifier enable , */\
- { 0x10d0, "flag_enbl_ref"}, /* References enable , */\
- { 0x10e0, "flag_adc10_ready"}, /* Control ADC , */\
- { 0x10f0, "flag_bod_vddd_nok"}, /* BOD Flag - VDD NOT OK , */\
- { 0x1100, "flag_bst_bstcur"}, /* DCDC current limiting , */\
- { 0x1110, "flag_bst_hiz"}, /* DCDC active (sticky register, clear on read) , */\
- { 0x1120, "flag_bst_ocpok"}, /* DCDC OCP nmos (sticky register, clear on read) , */\
- { 0x1130, "flag_bst_peakcur"}, /* Indicates current is max in DC-to-DC converter , */\
- { 0x1140, "flag_bst_voutcomp"}, /* DCDC level 1x , */\
- { 0x1150, "flag_bst_voutcomp86"}, /* DCDC level 1.14x , */\
- { 0x1160, "flag_bst_voutcomp93"}, /* DCDC level 1.07x , */\
- { 0x1170, "flag_cf_speakererror"}, /* Speaker status , */\
- { 0x1180, "flag_clk_out_of_range"}, /* External clock status , */\
- { 0x1190, "flag_man_alarm_state"}, /* Alarm state , */\
- { 0x11a0, "flag_tdm_error"}, /* TDM error , */\
- { 0x11b0, "flag_tdm_lut_error"}, /* TDM lookup table error , */\
- { 0x11c0, "flag_lost_audio_clk"}, /* Lost Audio clock , */\
- { 0x1200, "flag_ocpokap"}, /* OCPOK pmos A , */\
- { 0x1210, "flag_ocpokan"}, /* OCPOK nmos A , */\
- { 0x1220, "flag_ocpokbp"}, /* OCPOK pmos B , */\
- { 0x1230, "flag_ocpokbn"}, /* OCPOK nmos B , */\
- { 0x1240, "flag_clip"}, /* Amplifier clipping , */\
- { 0x1250, "flag_man_start_mute_audio"}, /* Audio mute sequence , */\
- { 0x1260, "flag_man_operating_state"}, /* Device in Operating state , */\
- { 0x1270, "flag_lp_detect_mode1"}, /* Low power MODE1 detection , */\
- { 0x1280, "flag_low_amplitude"}, /* Low amplitude detection , */\
- { 0x1290, "flag_vddp_gt_vbat"}, /* VDDP greater than VBAT flag , */\
- { 0x1302, "tdm_status"}, /* TDM Status bits , */\
- { 0x1333, "man_state"}, /* Device Manager status , */\
- { 0x1373, "amp_ctrl_state"}, /* Amplifier control status , */\
- { 0x13b1, "status_bst_mode"}, /* DCDC mode status bits , */\
- { 0x1509, "bat_adc"}, /* Battery voltage (V) , */\
- { 0x1608, "temp_adc"}, /* IC Temperature (C) , */\
- { 0x1709, "vddp_adc"}, /* IC VDDP voltage (1023*VDDP/13V) , */\
- { 0x2000, "tdm_enable"}, /* Enable interface , */\
- { 0x2010, "tdm_sink0_enable"}, /* Control audio tdm channel in sink0 , */\
- { 0x2020, "tdm_sink1_enable"}, /* Control audio tdm channel in sink1 , */\
- { 0x2030, "tdm_source0_enable"}, /* Source 0 enable , */\
- { 0x2040, "tdm_source1_enable"}, /* Source 1 enable , */\
- { 0x2050, "tdm_source2_enable"}, /* Source 2 enable , */\
- { 0x2060, "tdm_source3_enable"}, /* Source 3 enable , */\
- { 0x2070, "tdm_clk_inversion"}, /* Reception data to BCK clock , */\
- { 0x2080, "tdm_fs_ws_polarity"}, /* FS polarity , */\
- { 0x2090, "tdm_data_delay"}, /* Data delay to FS , */\
- { 0x20a0, "tdm_data_adjustment"}, /* Data adjustment , */\
- { 0x20b1, "tdm_audio_sample_compression"}, /* Received audio compression , */\
- { 0x2103, "tdm_nbck"}, /* TDM NBCK - Bit clock to FS ratio , */\
- { 0x2143, "tdm_fs_ws_length"}, /* FS length (master mode only) , */\
- { 0x2183, "tdm_nb_of_slots"}, /* N-slots in Frame , */\
- { 0x21c1, "tdm_txdata_format"}, /* Format unused bits , */\
- { 0x21e1, "tdm_txdata_format_unused_slot"}, /* Format unused slots DATAO , */\
- { 0x2204, "tdm_slot_length"}, /* N-bits in slot , */\
- { 0x2254, "tdm_bits_remaining"}, /* N-bits remaining , */\
- { 0x22a4, "tdm_sample_size"}, /* Sample size per slot , */\
- { 0x2303, "tdm_sink0_slot"}, /* TDM slot for sink 0 , */\
- { 0x2343, "tdm_sink1_slot"}, /* TDM slot for sink 1 , */\
- { 0x2381, "tdm_source2_sel"}, /* TDM Source 2 data selection , */\
- { 0x23a1, "tdm_source3_sel"}, /* TDM Source 3 data selection , */\
- { 0x2403, "tdm_source0_slot"}, /* Slot position of source 0 data , */\
- { 0x2443, "tdm_source1_slot"}, /* Slot position of source 1 data , */\
- { 0x2483, "tdm_source2_slot"}, /* Slot position of source 2 data , */\
- { 0x24c3, "tdm_source3_slot"}, /* Slot position of source 3 data , */\
- { 0x4000, "int_out_flag_por"}, /* Status POR , */\
- { 0x4010, "int_out_flag_bst_ocpok"}, /* Status DCDC OCP , */\
- { 0x4020, "int_out_flag_otpok"}, /* Status OTP alarm , */\
- { 0x4030, "int_out_flag_ocp_alarm"}, /* Status OCP alarm , */\
- { 0x4040, "int_out_flag_uvpok"}, /* Status UVP alarm , */\
- { 0x4050, "int_out_flag_man_alarm_state"}, /* Status manager alarm state , */\
- { 0x4060, "int_out_flag_tdm_error"}, /* Status TDM error , */\
- { 0x4070, "int_out_flag_lost_clk"}, /* Status lost clock , */\
- { 0x4080, "int_out_flag_cfma_err"}, /* Status cfma error , */\
- { 0x4090, "int_out_flag_cfma_ack"}, /* Status cfma ack , */\
- { 0x40a0, "int_out_flag_cf_speakererror"}, /* Status coolflux speaker error , */\
- { 0x40b0, "int_out_flag_cold_started"}, /* Status cold started , */\
- { 0x40c0, "int_out_flag_watchdog_reset"}, /* Status watchdog reset , */\
- { 0x40d0, "int_out_flag_bod_vddd_nok"}, /* Status brown out detect , */\
- { 0x40e0, "int_out_flag_lp_detect_mode1"}, /* Status low power mode1 detect , */\
- { 0x40f0, "int_out_flag_clk_out_of_range"}, /* Status clock out of range , */\
- { 0x4400, "int_in_flag_por"}, /* Clear POR , */\
- { 0x4410, "int_in_flag_bst_ocpok"}, /* Clear DCDC OCP , */\
- { 0x4420, "int_in_flag_otpok"}, /* Clear OTP alarm , */\
- { 0x4430, "int_in_flag_ocp_alarm"}, /* Clear OCP alarm , */\
- { 0x4440, "int_in_flag_uvpok"}, /* Clear UVP alarm , */\
- { 0x4450, "int_in_flag_man_alarm_state"}, /* Clear manager alarm state , */\
- { 0x4460, "int_in_flag_tdm_error"}, /* Clear TDM error , */\
- { 0x4470, "int_in_flag_lost_clk"}, /* Clear lost clk , */\
- { 0x4480, "int_in_flag_cfma_err"}, /* Clear cfma err , */\
- { 0x4490, "int_in_flag_cfma_ack"}, /* Clear cfma ack , */\
- { 0x44a0, "int_in_flag_cf_speakererror"}, /* Clear coolflux speaker error , */\
- { 0x44b0, "int_in_flag_cold_started"}, /* Clear cold started , */\
- { 0x44c0, "int_in_flag_watchdog_reset"}, /* Clear watchdog reset , */\
- { 0x44d0, "int_in_flag_bod_vddd_nok"}, /* Clear brown out detect , */\
- { 0x44e0, "int_in_flag_lp_detect_mode1"}, /* Clear low power mode1 detect , */\
- { 0x44f0, "int_in_flag_clk_out_of_range"}, /* Clear clock out of range , */\
- { 0x4800, "int_enable_flag_por"}, /* Enable POR , */\
- { 0x4810, "int_enable_flag_bst_ocpok"}, /* Enable DCDC OCP , */\
- { 0x4820, "int_enable_flag_otpok"}, /* Enable OTP alarm , */\
- { 0x4830, "int_enable_flag_ocp_alarm"}, /* Enable OCP alarm , */\
- { 0x4840, "int_enable_flag_uvpok"}, /* Enable UVP alarm , */\
- { 0x4850, "int_enable_flag_man_alarm_state"}, /* Enable Manager Alarm state , */\
- { 0x4860, "int_enable_flag_tdm_error"}, /* Enable TDM error , */\
- { 0x4870, "int_enable_flag_lost_clk"}, /* Enable lost clk , */\
- { 0x4880, "int_enable_flag_cfma_err"}, /* Enable cfma err , */\
- { 0x4890, "int_enable_flag_cfma_ack"}, /* Enable cfma ack , */\
- { 0x48a0, "int_enable_flag_cf_speakererror"}, /* Enable coolflux speaker error , */\
- { 0x48b0, "int_enable_flag_cold_started"}, /* Enable cold started , */\
- { 0x48c0, "int_enable_flag_watchdog_reset"}, /* Enable watchdog reset , */\
- { 0x48d0, "int_enable_flag_bod_vddd_nok"}, /* Enable brown out detect , */\
- { 0x48e0, "int_enable_flag_lp_detect_mode1"}, /* Enable low power mode1 detect , */\
- { 0x48f0, "int_enable_flag_clk_out_of_range"}, /* Enable clock out of range , */\
- { 0x4c00, "int_polarity_flag_por"}, /* Polarity POR , */\
- { 0x4c10, "int_polarity_flag_bst_ocpok"}, /* Polarity DCDC OCP , */\
- { 0x4c20, "int_polarity_flag_otpok"}, /* Polarity OTP alarm , */\
- { 0x4c30, "int_polarity_flag_ocp_alarm"}, /* Polarity ocp alarm , */\
- { 0x4c40, "int_polarity_flag_uvpok"}, /* Polarity UVP alarm , */\
- { 0x4c50, "int_polarity_flag_man_alarm_state"}, /* Polarity manager alarm state , */\
- { 0x4c60, "int_polarity_flag_tdm_error"}, /* Polarity TDM error , */\
- { 0x4c70, "int_polarity_flag_lost_clk"}, /* Polarity lost clk , */\
- { 0x4c80, "int_polarity_flag_cfma_err"}, /* Polarity cfma err , */\
- { 0x4c90, "int_polarity_flag_cfma_ack"}, /* Polarity cfma ack , */\
- { 0x4ca0, "int_polarity_flag_cf_speakererror"}, /* Polarity coolflux speaker error , */\
- { 0x4cb0, "int_polarity_flag_cold_started"}, /* Polarity cold started , */\
- { 0x4cc0, "int_polarity_flag_watchdog_reset"}, /* Polarity watchdog reset , */\
- { 0x4cd0, "int_polarity_flag_bod_vddd_nok"}, /* Polarity brown out detect , */\
- { 0x4ce0, "int_polarity_flag_lp_detect_mode1"}, /* Polarity low power mode1 detect , */\
- { 0x4cf0, "int_polarity_flag_clk_out_of_range"}, /* Polarity clock out of range , */\
- { 0x5001, "vbat_prot_attack_time"}, /* Battery safeguard attack time , */\
- { 0x5023, "vbat_prot_thlevel"}, /* Battery safeguard threshold voltage level , */\
- { 0x5061, "vbat_prot_max_reduct"}, /* Battery safeguard maximum reduction , */\
- { 0x5082, "vbat_prot_release_time"}, /* Battery safeguard release time , */\
- { 0x50b1, "vbat_prot_hysterese"}, /* Battery Safeguard hysteresis , */\
- { 0x50d0, "rst_min_vbat"}, /* Reset clipper - auto clear , */\
- { 0x50e0, "sel_vbat"}, /* Battery voltage read out , */\
- { 0x50f0, "bypass_clipper"}, /* Bypass HW clipper , */\
- { 0x5130, "cf_mute"}, /* Coolflux firmware soft mute control , */\
- { 0x5187, "cf_volume"}, /* CF firmware volume control , */\
- { 0x5202, "ctrl_cc"}, /* Clip control setting , */\
- { 0x5230, "ctrl_slopectrl"}, /* Enables slope control , */\
- { 0x5240, "ctrl_slope"}, /* Slope speed setting (binary coded) , */\
- { 0x5250, "bypass_dly_line"}, /* Bypass the interpolator delay line , */\
- { 0x5287, "gain"}, /* Amplifier gain , */\
- { 0x5301, "dpsa_level"}, /* DPSA threshold levels , */\
- { 0x5321, "dpsa_release"}, /* DPSA Release time , */\
- { 0x5340, "clipfast"}, /* Clock selection for HW clipper for battery safeguard, */\
- { 0x5350, "bypass_lp"}, /* Bypass the low power filter inside temperature sensor, */\
- { 0x5360, "first_order_mode"}, /* Overrule to 1st order mode of control stage when clipping, */\
- { 0x5370, "icomp_engage"}, /* Engage of icomp , */\
- { 0x5380, "ctrl_kickback"}, /* Prevent double pulses of output stage , */\
- { 0x5390, "icomp_engage_overrule"}, /* To overrule the functional icomp_engage signal during validation, */\
- { 0x53a3, "ctrl_dem"}, /* Enable DEM icomp and DEM one bit dac , */\
- { 0x5400, "bypass_ctrlloop"}, /* Switch amplifier into open loop configuration , */\
- { 0x5413, "ctrl_dem_mismatch"}, /* Enable DEM icomp mismatch for testing , */\
- { 0x5452, "dpsa_drive"}, /* Drive setting (binary coded) , */\
- { 0x550a, "enbl_amp"}, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually, */\
- { 0x55b0, "enbl_engage"}, /* Enables/engage power stage and control loop , */\
- { 0x55c0, "enbl_engage_pst"}, /* Enables/engage power stage and control loop , */\
- { 0x5600, "pwm_shape"}, /* PWM shape , */\
- { 0x5614, "pwm_delay"}, /* PWM delay bits to set the delay, clockd is 1/(k*2048*fs), */\
- { 0x5660, "reclock_pwm"}, /* Reclock the PWM signal inside analog , */\
- { 0x5670, "reclock_voltsense"}, /* Reclock the voltage sense PWM signal , */\
- { 0x5680, "enbl_pwm_phase_shift"}, /* Control for PWM phase shift , */\
- { 0x5690, "sel_pwm_delay_src"}, /* Control for selection for PWM delay line source , */\
- { 0x56a1, "enbl_odd_up_even_down"}, /* Control for PWM reference sawtooth generartion , */\
- { 0x5703, "ctrl_att_dcdc"}, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */\
- { 0x5743, "ctrl_att_spkr"}, /* Total gain depending on INPLEV setting (channel 0), */\
- { 0x5781, "vamp_sel2"}, /* VAMP_OUT2 input selection , */\
- { 0x5805, "zero_lvl"}, /* Low noise gain switch zero trigger level , */\
- { 0x5861, "ctrl_fb_resistor"}, /* Select amplifier feedback resistor connection , */\
- { 0x5881, "lownoisegain_mode"}, /* Low noise gain mode control , */\
- { 0x5905, "threshold_lvl"}, /* Low noise gain switch trigger level , */\
- { 0x5965, "hold_time"}, /* Low noise mode hold time before entering into low noise mode, */\
- { 0x5a05, "lpm1_cal_offset"}, /* Low power mode1 detector ctrl cal_offset from gain module , */\
- { 0x5a65, "lpm1_zero_lvl"}, /* Low power mode1 zero crossing detection level , */\
- { 0x5ac1, "lpm1_mode"}, /* Low power mode control , */\
- { 0x5b05, "lpm1_threshold_lvl"}, /* Low power mode1 amplitude trigger level , */\
- { 0x5b65, "lpm1_hold_time"}, /* Low power mode hold time before entering into low power mode, */\
- { 0x5bc0, "disable_low_power_mode"}, /* Low power mode1 detector control , */\
- { 0x5c00, "enbl_minion"}, /* Enables minion (small) power stage , */\
- { 0x5c13, "vth_vddpvbat"}, /* Select vddp-vbat threshold signal , */\
- { 0x5c50, "lpen_vddpvbat"}, /* Select vddp-vbat filtred vs unfiltered compare , */\
- { 0x5c61, "ctrl_rfb"}, /* Feedback resistor selection - I2C direct mode , */\
- { 0x5d02, "tdm_source_mapping"}, /* TDM source mapping , */\
- { 0x5d31, "tdm_sourcea_frame_sel"}, /* Sensed value A , */\
- { 0x5d51, "tdm_sourceb_frame_sel"}, /* Sensed value B , */\
- { 0x5d71, "tdm_source0_clip_sel"}, /* Clip information (analog /digital) for source0 , */\
- { 0x5d91, "tdm_source1_clip_sel"}, /* Clip information (analog /digital) for source1 , */\
- { 0x5e02, "rst_min_vbat_delay"}, /* Delay for reseting the min_vbat value inside HW Clipper (number of Fs pulses), */\
- { 0x5e30, "rst_min_vbat_sel"}, /* Control for selecting reset signal for min_bat , */\
- { 0x5f00, "hard_mute"}, /* Hard mute - PWM , */\
- { 0x5f12, "ns_hp2ln_criterion"}, /* 0..7 zeroes at ns as threshold to swap from high_power to low_noise, */\
- { 0x5f42, "ns_ln2hp_criterion"}, /* 0..7 zeroes at ns as threshold to swap from low_noise to high_power, */\
- { 0x5f78, "spare_out"}, /* Spare out register , */\
- { 0x600f, "spare_in"}, /* Spare IN , */\
- { 0x6102, "cursense_comp_delay"}, /* Delay to allign compensation signal with current sense signal, */\
- { 0x6130, "cursense_comp_sign"}, /* Polarity of compensation for current sense , */\
- { 0x6140, "enbl_cursense_comp"}, /* Enable current sense compensation , */\
- { 0x6152, "pwms_clip_lvl"}, /* Set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
- { 0x7005, "frst_boost_voltage"}, /* First Boost Voltage Level , */\
- { 0x7065, "scnd_boost_voltage"}, /* Second Boost Voltage Level , */\
- { 0x70c3, "boost_cur"}, /* Max Coil Current , */\
- { 0x7101, "bst_slpcmplvl"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
- { 0x7120, "boost_intel"}, /* Adaptive boost mode , */\
- { 0x7130, "boost_speed"}, /* Soft ramp up/down , */\
- { 0x7140, "dcdcoff_mode"}, /* DCDC on/off , */\
- { 0x7150, "dcdc_pwmonly"}, /* DCDC PWM only mode , */\
- { 0x7160, "boost_track"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
- { 0x7170, "sel_dcdc_envelope_8fs"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
- { 0x7180, "ignore_flag_voutcomp86"}, /* Determines the maximum PWM frequency be the most efficient in relation to the Booster inductor value, */\
- { 0x7195, "overshoot_correction_lvl"}, /* Threshold level to activate active overshoot control, */\
- { 0x7204, "boost_trip_lvl_1st"}, /* 1st adaptive boost trip levels, effective only when DCIE is set to 1, */\
- { 0x7254, "boost_trip_lvl_2nd"}, /* 2nd adaptive boost trip levels, effective only when DCIE is set to 1, */\
- { 0x72a4, "boost_trip_lvl_track"}, /* Track adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
- { 0x72f0, "enbl_trip_hyst"}, /* Enable hysteresis on booster trip levels , */\
- { 0x7304, "boost_hold_time"}, /* Hold time / Hysteresis for DCDC booster, effective only when boost_intelligent is set to 1, */\
- { 0x7350, "dcdc_pfm20khz_limit"}, /* DCDC in PFM mode pwm mode is activated each 50us to force a pwm pulse, */\
- { 0x7361, "dcdc_ctrl_maxzercnt"}, /* Number of zero current flags to count before going to pfm mode, */\
- { 0x7386, "dcdc_vbat_delta_detect"}, /* Threshold before booster is reacting on a delta Vbat (in PFM mode) by temporarily switching to PWM mode, */\
- { 0x73f0, "dcdc_ignore_vbat"}, /* Ignore an increase on Vbat , */\
- { 0x7404, "bst_drive"}, /* Binary coded drive setting for boost converter power stage, */\
- { 0x7451, "bst_scalecur"}, /* For testing direct control scale current , */\
- { 0x7474, "bst_slopecur"}, /* For testing direct control slope current , */\
- { 0x74c1, "bst_slope"}, /* Boost slope speed , */\
- { 0x74e0, "bst_bypass_bstcur"}, /* Bypass control for boost current settings , */\
- { 0x74f0, "bst_bypass_bstfoldback"}, /* Bypass control for boost foldback , */\
- { 0x7500, "enbl_bst_engage"}, /* Enable power stage dcdc controller , */\
- { 0x7510, "enbl_bst_hizcom"}, /* Enable hiz comparator , */\
- { 0x7520, "enbl_bst_peakcur"}, /* Enable peak current , */\
- { 0x7530, "enbl_bst_power"}, /* Enable line of the powerstage , */\
- { 0x7540, "enbl_bst_slopecur"}, /* Enable bit of max-current dac , */\
- { 0x7550, "enbl_bst_voutcomp"}, /* Enable vout comparators , */\
- { 0x7560, "enbl_bst_voutcomp86"}, /* Enable vout-86 comparators , */\
- { 0x7570, "enbl_bst_voutcomp93"}, /* Enable vout-93 comparators , */\
- { 0x7580, "enbl_bst_windac"}, /* Enable window dac , */\
- { 0x7595, "bst_windac"}, /* For testing direct control windac , */\
- { 0x7600, "boost_alg"}, /* Control for boost adaptive loop gain , */\
- { 0x7611, "boost_loopgain"}, /* DCDC boost loopgain setting , */\
- { 0x7631, "bst_freq"}, /* DCDC boost frequency control , */\
- { 0x7650, "enbl_bst_peak2avg"}, /* Enable boost peak2avg functionality , */\
- { 0x7660, "bst_use_new_zercur_detect"}, /* Enable new zero current detection for boost control, */\
- { 0x8001, "sel_clk_cs"}, /* Current sense clock duty cycle control , */\
- { 0x8021, "micadc_speed"}, /* Current sense clock for MiCADC selection - 32/44.1/48 KHz Fs band only, */\
- { 0x8040, "cs_gain_control"}, /* Current sense gain control , */\
- { 0x8050, "cs_bypass_gc"}, /* Bypasses the CS gain correction , */\
- { 0x8060, "invertpwm"}, /* Current sense common mode feedback pwm invert control, */\
- { 0x8087, "cs_gain"}, /* Current sense gain , */\
- { 0x8105, "cs_ktemp"}, /* Current sense temperature compensation trimming (1 - VALUE*TEMP) * signal, */\
- { 0x8164, "cs_ktemp2"}, /* Second order temperature compensation coefficient , */\
- { 0x81b0, "enbl_cs_adc"}, /* Enable current sense ADC , */\
- { 0x81c0, "enbl_cs_inn1"}, /* Enable connection of current sense negative1 , */\
- { 0x81d0, "enbl_cs_inn2"}, /* Enable connection of current sense negative2 , */\
- { 0x81e0, "enbl_cs_inp1"}, /* Enable connection of current sense positive1 , */\
- { 0x81f0, "enbl_cs_inp2"}, /* Enable connection of current sense positive2 , */\
- { 0x8200, "enbl_cs_ldo"}, /* Enable current sense LDO , */\
- { 0x8210, "enbl_cs_vbatldo"}, /* Enable of current sense LDO , */\
- { 0x8220, "cs_adc_bsoinv"}, /* Bitstream inversion for current sense ADC , */\
- { 0x8231, "cs_adc_hifreq"}, /* Frequency mode current sense ADC , */\
- { 0x8250, "cs_adc_nortz"}, /* Return to zero for current sense ADC , */\
- { 0x8263, "cs_adc_offset"}, /* Micadc ADC offset setting , */\
- { 0x82a0, "cs_adc_slowdel"}, /* Select delay for current sense ADC (internal decision circuitry), */\
- { 0x82b4, "cs_adc_gain"}, /* Gain setting for current sense ADC (two's complement), */\
- { 0x8300, "cs_resonator_enable"}, /* Enable for resonator to improve SRN , */\
- { 0x8310, "cs_classd_tran_skip"}, /* Skip current sense connection during a classD amplifier transition, */\
- { 0x8320, "cs_inn_short"}, /* Short current sense negative to common mode , */\
- { 0x8330, "cs_inp_short"}, /* Short current sense positive to common mode , */\
- { 0x8340, "cs_ldo_bypass"}, /* Bypass current sense LDO , */\
- { 0x8350, "cs_ldo_pulldown"}, /* Pull down current sense LDO, only valid if enbl_cs_ldo is high, */\
- { 0x8364, "cs_ldo_voset"}, /* Current sense LDO voltage level setting (two's complement), */\
- { 0x8800, "ctrl_vs_igen_supply"}, /* Control for selecting supply for VS current generator, */\
- { 0x8810, "ctrl_vs_force_div2"}, /* Select input resistive divider gain , */\
- { 0x8820, "enbl_dc_filter"}, /* Control for enabling the DC blocking filter for voltage and current sense, */\
- { 0x8901, "volsense_pwm_sel"}, /* Voltage sense source selection control , */\
- { 0x8920, "vs_gain_control"}, /* Voltage sense gain control , */\
- { 0x8930, "vs_bypass_gc"}, /* Bypasses the VS gain correction , */\
- { 0x8940, "vs_adc_bsoinv"}, /* Bitstream inversion for voltage sense ADC , */\
- { 0x8950, "vs_adc_nortz"}, /* Return to zero for voltage sense ADC , */\
- { 0x8960, "vs_adc_slowdel"}, /* Select delay for voltage sense ADC (internal decision circuitry), */\
- { 0x8970, "vs_classd_tran_skip"}, /* Skip voltage sense connection during a classD amplifier transition, */\
- { 0x8987, "vs_gain"}, /* Voltage sense gain , */\
- { 0x8a00, "vs_inn_short"}, /* Short voltage sense negative to common mode , */\
- { 0x8a10, "vs_inp_short"}, /* Short voltage sense positive to common mode , */\
- { 0x8a20, "vs_ldo_bypass"}, /* Bypass voltage sense LDO , */\
- { 0x8a30, "vs_ldo_pulldown"}, /* Pull down voltage sense LDO, only valid if enbl_cs_ldo is high, */\
- { 0x8a44, "vs_ldo_voset"}, /* Voltage sense LDO voltage level setting (two's complement), */\
- { 0x8a90, "enbl_vs_adc"}, /* Enable voltage sense ADC , */\
- { 0x8aa0, "enbl_vs_inn1"}, /* Enable connection of voltage sense negative1 , */\
- { 0x8ab0, "enbl_vs_inn2"}, /* Enable connection of voltage sense negative2 , */\
- { 0x8ac0, "enbl_vs_inp1"}, /* Enable connection of voltage sense positive1 , */\
- { 0x8ad0, "enbl_vs_inp2"}, /* Enable connection of voltage sense positive2 , */\
- { 0x8ae0, "enbl_vs_ldo"}, /* Enable voltage sense LDO , */\
- { 0x8af0, "enbl_vs_vbatldo"}, /* Enable of voltage sense LDO , */\
- { 0x9000, "cf_rst_dsp"}, /* Reset for Coolflux DSP , */\
- { 0x9011, "cf_dmem"}, /* Target memory for CFMA using I2C interface , */\
- { 0x9030, "cf_aif"}, /* Auto increment , */\
- { 0x9040, "cf_int"}, /* Coolflux Interrupt - auto clear , */\
- { 0x9050, "cf_cgate_off"}, /* Coolflux clock gating disabling control , */\
- { 0x9080, "cf_req_cmd"}, /* Firmware event request rpc command , */\
- { 0x9090, "cf_req_reset"}, /* Firmware event request reset restart , */\
- { 0x90a0, "cf_req_mips"}, /* Firmware event request short on mips , */\
- { 0x90b0, "cf_req_mute_ready"}, /* Firmware event request mute sequence ready , */\
- { 0x90c0, "cf_req_volume_ready"}, /* Firmware event request volume ready , */\
- { 0x90d0, "cf_req_damage"}, /* Firmware event request speaker damage detected , */\
- { 0x90e0, "cf_req_calibrate_ready"}, /* Firmware event request calibration completed , */\
- { 0x90f0, "cf_req_reserved"}, /* Firmware event request reserved , */\
- { 0x910f, "cf_madd"}, /* CF memory address , */\
- { 0x920f, "cf_mema"}, /* Activate memory access , */\
- { 0x9307, "cf_err"}, /* CF error flags , */\
- { 0x9380, "cf_ack_cmd"}, /* Firmware event acknowledge rpc command , */\
- { 0x9390, "cf_ack_reset"}, /* Firmware event acknowledge reset restart , */\
- { 0x93a0, "cf_ack_mips"}, /* Firmware event acknowledge short on mips , */\
- { 0x93b0, "cf_ack_mute_ready"}, /* Firmware event acknowledge mute sequence ready , */\
- { 0x93c0, "cf_ack_volume_ready"}, /* Firmware event acknowledge volume ready , */\
- { 0x93d0, "cf_ack_damage"}, /* Firmware event acknowledge speaker damage detected, */\
- { 0x93e0, "cf_ack_calibrate_ready"}, /* Firmware event acknowledge calibration completed , */\
- { 0x93f0, "cf_ack_reserved"}, /* Firmware event acknowledge reserved , */\
- { 0xa007, "mtpkey1"}, /* KEY1 To access KEY1 protected registers 0x5A/90d (default for engineering), */\
- { 0xa107, "mtpkey2"}, /* KEY2 to access KEY2 protected registers, customer key, */\
- { 0xa200, "key01_locked"}, /* Indicates KEY1 is locked , */\
- { 0xa210, "key02_locked"}, /* Indicates KEY2 is locked , */\
- { 0xa302, "mtp_man_address_in"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
- { 0xa330, "man_copy_mtp_to_iic"}, /* Start copying single word from MTP to I2C mtp register - auto clear, */\
- { 0xa340, "man_copy_iic_to_mtp"}, /* Start copying single word from I2C mtp register to mtp - auto clear, */\
- { 0xa350, "auto_copy_mtp_to_iic"}, /* Start copying all the data from mtp to I2C mtp registers - auto clear, */\
- { 0xa360, "auto_copy_iic_to_mtp"}, /* Start copying data from I2C mtp registers to mtp - auto clear, */\
- { 0xa400, "faim_set_clkws"}, /* Sets the FaIM controller clock wait state register, */\
- { 0xa410, "faim_sel_evenrows"}, /* All even rows of the FaIM are selected, active high, */\
- { 0xa420, "faim_sel_oddrows"}, /* All odd rows of the FaIM are selected, all rows in combination with sel_evenrows, */\
- { 0xa430, "faim_program_only"}, /* Skip the erase access at wr_faim command (write-program-marginread), */\
- { 0xa440, "faim_erase_only"}, /* Skip the program access at wr_faim command (write-erase-marginread), */\
- { 0xa50f, "mtp_man_data_out_msb"}, /* MSB word of MTP manual read data , */\
- { 0xa60f, "mtp_man_data_out_lsb"}, /* LSB word of MTP manual read data , */\
- { 0xa70f, "mtp_man_data_in_msb"}, /* MSB word of write data for MTP manual write , */\
- { 0xa80f, "mtp_man_data_in_lsb"}, /* LSB word of write data for MTP manual write , */\
- { 0xb000, "bypass_ocpcounter"}, /* Bypass OCP Counter , */\
- { 0xb010, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
- { 0xb020, "bypass_ovp"}, /* Bypass OVP , */\
- { 0xb030, "bypass_uvp"}, /* Bypass UVP , */\
- { 0xb040, "bypass_otp"}, /* Bypass OTP , */\
- { 0xb050, "bypass_lost_clk"}, /* Bypass lost clock detector , */\
- { 0xb060, "ctrl_vpalarm"}, /* vpalarm (uvp ovp handling) , */\
- { 0xb070, "disable_main_ctrl_change_prot"}, /* Disable main control change protection , */\
- { 0xb087, "ocp_threshold"}, /* OCP threshold level , */\
- { 0xb108, "ext_temp"}, /* External temperature (C) , */\
- { 0xb190, "ext_temp_sel"}, /* Select temp Speaker calibration , */\
- { 0xc000, "use_direct_ctrls"}, /* Direct control to overrule several functions for testing, */\
- { 0xc010, "rst_datapath"}, /* Direct control for datapath reset , */\
- { 0xc020, "rst_cgu"}, /* Direct control for cgu reset , */\
- { 0xc038, "enbl_ref"}, /* Switch on the analog references, each part of the references can be switched on/off individually, */\
- { 0xc0c0, "use_direct_vs_ctrls"}, /* Voltage sense direct control to overrule several functions for testing, */\
- { 0xc0d0, "enbl_ringo"}, /* Enable the ring oscillator for test purpose , */\
- { 0xc0e0, "enbl_pll"}, /* Enables PLL in I2C direct control mode only , */\
- { 0xc0f0, "enbl_osc"}, /* Enables OSC in I2C direct control mode only , */\
- { 0xc100, "enbl_tsense"}, /* Temperature sensor enable control - I2C direct mode, */\
- { 0xc110, "tsense_hibias"}, /* Bit to set the biasing in temp sensor to high , */\
- { 0xc120, "enbl_flag_vbg"}, /* Enable flagging of bandgap out of control , */\
- { 0xc20f, "abist_offset"}, /* Offset control for ABIST testing (two's complement), */\
- { 0xc300, "bypasslatch"}, /* Bypass latch , */\
- { 0xc311, "sourcea"}, /* Set OUTA to , */\
- { 0xc331, "sourceb"}, /* Set OUTB to , */\
- { 0xc350, "inverta"}, /* Invert pwma test signal , */\
- { 0xc360, "invertb"}, /* Invert pwmb test signal , */\
- { 0xc374, "pulselength"}, /* Pulse length setting test input for amplifier (clock d - k*2048*fs), */\
- { 0xc3d0, "test_abistfft_enbl"}, /* Enable ABIST with FFT on Coolflux DSP , */\
- { 0xc400, "bst_bypasslatch"}, /* Bypass latch in boost converter , */\
- { 0xc411, "bst_source"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
- { 0xc430, "bst_invertb"}, /* Invert pwmbst test signal , */\
- { 0xc444, "bst_pulselength"}, /* Pulse length setting test input for boost converter , */\
- { 0xc490, "test_bst_ctrlsthv"}, /* Test mode for boost control stage , */\
- { 0xc4a0, "test_bst_iddq"}, /* IDDQ testing in power stage of boost converter , */\
- { 0xc4b0, "test_bst_rdson"}, /* RDSON testing - boost power stage , */\
- { 0xc4c0, "test_bst_cvi"}, /* CVI testing - boost power stage , */\
- { 0xc4d0, "test_bst_ocp"}, /* Boost Converter Over Current Protection , */\
- { 0xc4e0, "test_bst_sense"}, /* Test option for the sense NMOS in booster for current mode control., */\
- { 0xc500, "test_cvi"}, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */\
- { 0xc510, "test_discrete"}, /* Test function noise measurement , */\
- { 0xc520, "test_iddq"}, /* Set the power stages in iddq mode for gate stress., */\
- { 0xc530, "test_rdson"}, /* Analog BIST, switch to enable Rdson measurement , */\
- { 0xc540, "test_sdelta"}, /* Analog BIST, noise test , */\
- { 0xc550, "test_enbl_cs"}, /* Enable for digimux mode of current sense , */\
- { 0xc560, "test_enbl_vs"}, /* Enable for digimux mode of voltage sense , */\
- { 0xc570, "enbl_pwm_dcc"}, /* Enables direct control of pwm duty cycle for DCDC power stage, */\
- { 0xc583, "pwm_dcc_cnt"}, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */\
- { 0xc5c0, "enbl_ldo_stress"}, /* Enable stress of internal supply voltages powerstages, */\
- { 0xc607, "digimuxa_sel"}, /* DigimuxA input selection control routed to DATAO , */\
- { 0xc687, "digimuxb_sel"}, /* DigimuxB input selection control routed to INT , */\
- { 0xc707, "digimuxc_sel"}, /* DigimuxC input selection control routed to ADS1 , */\
- { 0xc800, "enbl_anamux1"}, /* Enable anamux1 , */\
- { 0xc810, "enbl_anamux2"}, /* Enable anamux2 , */\
- { 0xc820, "enbl_anamux3"}, /* Enable anamux3 , */\
- { 0xc830, "enbl_anamux4"}, /* Enable anamux4 , */\
- { 0xc844, "anamux1"}, /* Anamux selection control - anamux on TEST1 , */\
- { 0xc894, "anamux2"}, /* Anamux selection control - anamux on TEST2 , */\
- { 0xc903, "anamux3"}, /* Anamux selection control - anamux on TEST3 , */\
- { 0xc943, "anamux4"}, /* Anamux selection control - anamux on TEST4 , */\
- { 0xca05, "pll_inseli"}, /* PLL INSELI - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
- { 0xca64, "pll_inselp"}, /* PLL INSELP - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
- { 0xcab3, "pll_inselr"}, /* PLL INSELR - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
- { 0xcaf0, "pll_bandsel"}, /* PLL bandwidth selection control, USE WITH CAUTION , */\
- { 0xcb09, "pll_ndec"}, /* PLL NDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
- { 0xcba0, "pll_mdec_msb"}, /* MSB of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
- { 0xcbb0, "pll_bypass"}, /* PLL bypass control during functional mode , */\
- { 0xcbc0, "pll_directi"}, /* PLL directi control in direct control mode only, use_direct_pll_ctrl set to 1, */\
- { 0xcbd0, "pll_directo"}, /* PLL directo control in direct control mode only, use_direct_pll_ctrl set to 1, */\
- { 0xcbe0, "pll_frm_clockstable"}, /* PLL FRM clock stable control in direct control mode only, use_direct_pll_ctrl set to 1, */\
- { 0xcbf0, "pll_frm"}, /* PLL free running mode control in functional mode , */\
- { 0xcc0f, "pll_mdec_lsb"}, /* Bits 15..0 of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
- { 0xcd06, "pll_pdec"}, /* PLL PDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
- { 0xcd70, "use_direct_pll_ctrl"}, /* Enabled PLL direct control mode, overrules the PLL LUT with I2C register values, */\
- { 0xcd80, "use_direct_clk_ctrl"}, /* Enabled CGU clock divider direct control mode , */\
- { 0xcd90, "pll_limup_off"}, /* PLL up limiter control in PLL direct bandwidth control mode, pll_bandsel set to 1, */\
- { 0xce0f, "tsig_freq_lsb"}, /* Internal sinus test generator frequency control , */\
- { 0xcf02, "tsig_freq_msb"}, /* Select internal sinus test generator, frequency control msb bits, */\
- { 0xcf33, "tsig_gain"}, /* Test signal gain , */\
- { 0xd000, "adc10_reset"}, /* Reset for ADC10 - I2C direct control mode , */\
- { 0xd011, "adc10_test"}, /* Test mode selection signal for ADC10 - I2C direct control mode, */\
- { 0xd032, "adc10_sel"}, /* Select the input to convert for ADC10 - I2C direct control mode, */\
- { 0xd064, "adc10_prog_sample"}, /* ADC10 program sample setting - I2C direct control mode, */\
- { 0xd0b0, "adc10_enbl"}, /* Enable ADC10 - I2C direct control mode , */\
- { 0xd0c0, "bypass_lp_vbat"}, /* Bypass control for Low pass filter in batt sensor , */\
- { 0xd109, "data_adc10_tempbat"}, /* ADC 10 data output data for testing , */\
- { 0xd201, "clkdiv_audio_sel"}, /* Audio clock divider selection in direct clock control mode, */\
- { 0xd301, "int_ehs"}, /* Speed/load setting for INT IO cell, clk or data mode range (see SLIMMF IO datasheet), */\
- { 0xd321, "datao_ehs"}, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO datasheet), */\
- { 0xd340, "hs_mode"}, /* I2C high speed mode control , */\
- { 0xd407, "ctrl_digtoana_hidden"}, /* Spare digital to analog control bits - Hidden , */\
- { 0xd480, "enbl_clk_out_of_range"}, /* Clock out of range , */\
- { 0xd491, "sel_wdt_clk"}, /* Watch dog clock divider settings , */\
- { 0xd4b0, "inject_tsig"}, /* Control bit to switch to internal sinus test generator, */\
- { 0xd500, "source_in_testmode"}, /* TDM source in test mode (return only current and voltage sense), */\
- { 0xd510, "gainatt_feedback"}, /* Gainatt feedback to tdm , */\
- { 0xd522, "test_parametric_io"}, /* Test IO parametric , */\
- { 0xd550, "ctrl_bst_clk_lp1"}, /* Boost clock control in low power mode1 , */\
- { 0xd561, "test_spare_out1"}, /* Test spare out 1 , */\
- { 0xd580, "bst_dcmbst"}, /* DCM boost , */\
- { 0xd593, "test_spare_out2"}, /* Test spare out 2 , */\
- { 0xe00f, "sw_profile"}, /* Software profile data , */\
- { 0xe10f, "sw_vstep"}, /* Software vstep information , */\
- { 0xf000, "calibration_onetime"}, /* Calibration schedule , */\
- { 0xf010, "calibr_ron_done"}, /* Calibration Ron executed , */\
- { 0xf020, "calibr_dcdc_api_calibrate"}, /* Calibration current limit DCDC , */\
- { 0xf030, "calibr_dcdc_delta_sign"}, /* Sign bit for delta calibration current limit DCDC , */\
- { 0xf042, "calibr_dcdc_delta"}, /* Calibration delta current limit DCDC , */\
- { 0xf078, "calibr_speaker_info"}, /* Reserved space for allowing customer to store speaker information, */\
- { 0xf105, "calibr_vout_offset"}, /* DCDC offset calibration 2's complement (key1 protected), */\
- { 0xf163, "calibr_vbg_trim"}, /* Bandgap trimming control , */\
- { 0xf203, "calibr_gain"}, /* HW gain module (2's complement) , */\
- { 0xf245, "calibr_offset"}, /* Offset for amplifier, HW gain module (2's complement), */\
- { 0xf307, "calibr_gain_vs"}, /* Voltage sense gain , */\
- { 0xf387, "calibr_gain_cs"}, /* Current sense gain (signed two's complement format), */\
- { 0xf40f, "mtpdata4"}, /* MTP4 data , */\
- { 0xf50f, "calibr_R25C"}, /* Ron resistance of speaker coil , */\
- { 0xf60f, "mtpdata6"}, /* MTP6 data , */\
- { 0xf706, "ctrl_offset_a"}, /* Offset of level shifter A , */\
- { 0xf786, "ctrl_offset_b"}, /* Offset of amplifier level shifter B , */\
- { 0xf806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
- { 0xf870, "htol_iic_addr_en"}, /* HTOL I2C address enable control , */\
- { 0xf884, "calibr_temp_offset"}, /* Temperature offset 2's compliment (key1 protected), */\
- { 0xf8d2, "calibr_temp_gain"}, /* Temperature gain 2's compliment (key1 protected) , */\
- { 0xf900, "mtp_lock_dcdcoff_mode"}, /* Disable functionality of dcdcoff_mode bit , */\
- { 0xf910, "mtp_lock_enbl_coolflux"}, /* Disable functionality of enbl_coolflux bit , */\
- { 0xf920, "mtp_lock_bypass_clipper"}, /* Disable function bypass_clipper , */\
- { 0xf930, "mtp_enbl_pwm_delay_clock_gating"}, /* PWM delay clock auto gating , */\
- { 0xf940, "mtp_enbl_ocp_clock_gating"}, /* OCP clock auto gating , */\
- { 0xf987, "type_bits_fw"}, /* MTP control for firmware features - See Firmware I2C API document for details, */\
- { 0xfa0f, "mtpdataA"}, /* MTPdataA , */\
- { 0xfb0f, "mtpdataB"}, /* MTPdataB , */\
- { 0xfc0f, "mtpdataC"}, /* MTPdataC , */\
- { 0xfd0f, "mtpdataD"}, /* MTPdataD , */\
- { 0xfe0f, "mtpdataE"}, /* MTPdataE , */\
- { 0xff07, "calibr_osc_delta_ndiv"}, /* Calibration data for OSC1M, signed number representation, */\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-#if 0
-enum tfa9894_irq {
- tfa9894_irq_max = -1,
- tfa9894_irq_all = -1 /* all irqs */};
-#endif//
-#define TFA9894_IRQ_NAMETABLE static tfaIrqName_t Tfa9894IrqNames[]= {\
-};
-#endif /* _TFA9894_TFAFIELDNAMES_H */
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _TFA9894_TFAFIELDNAMES_N2_H
+#define _TFA9894_TFAFIELDNAMES_N2_H
+
+
+#define TFA9894N2_I2CVERSION 25.0
+
+typedef enum nxpTfa9894N2BfEnumList {
+ TFA9894N2_BF_PWDN = 0x0000, /*!< Powerdown control */
+ TFA9894N2_BF_I2CR = 0x0010, /*!< I2C Reset - Auto clear */
+ TFA9894N2_BF_CFE = 0x0020, /*!< Enable CoolFlux DSP */
+ TFA9894N2_BF_AMPE = 0x0030, /*!< Enable Amplifier */
+ TFA9894N2_BF_DCA = 0x0040, /*!< Enable DCDC Boost converter */
+ TFA9894N2_BF_SBSL = 0x0050, /*!< Coolflux configured */
+ TFA9894N2_BF_AMPC = 0x0060, /*!< CoolFlux control over amplifier */
+ TFA9894N2_BF_INTP = 0x0071, /*!< Interrupt config */
+ TFA9894N2_BF_FSSSEL = 0x0090, /*!< Audio sample reference */
+ TFA9894N2_BF_BYPOCP = 0x00a0, /*!< Bypass OCP */
+ TFA9894N2_BF_TSTOCP = 0x00b0, /*!< OCP testing control */
+ TFA9894N2_BF_BSSS = 0x00c0, /*!< Vbat protection steepness */
+ TFA9894N2_BF_HPFBYP = 0x00d0, /*!< Bypass High Pass Filter */
+ TFA9894N2_BF_DPSA = 0x00e0, /*!< Enable DPSA */
+ TFA9894N2_BF_AMPINSEL = 0x0101, /*!< Amplifier input selection */
+ TFA9894N2_BF_MANSCONF = 0x0120, /*!< Device I2C settings configured */
+ TFA9894N2_BF_MANCOLD = 0x0130, /*!< Execute cold start */
+ TFA9894N2_BF_MANROBOD = 0x0140, /*!< Reaction on BOD */
+ TFA9894N2_BF_BODE = 0x0150, /*!< Enable BOD (only in direct control mode) */
+ TFA9894N2_BF_BODHYS = 0x0160, /*!< Enable Hysteresis of BOD */
+ TFA9894N2_BF_BODFILT = 0x0171, /*!< BOD filter */
+ TFA9894N2_BF_BODTHLVL = 0x0191, /*!< BOD threshold */
+ TFA9894N2_BF_MUTETO = 0x01b0, /*!< Time out SB mute sequence */
+ TFA9894N2_BF_MANWDE = 0x01c0, /*!< Watchdog enable */
+ TFA9894N2_BF_OPENMTP = 0x01e0, /*!< Control for FAIM protection */
+ TFA9894N2_BF_FAIMVBGOVRRL = 0x01f0, /*!< Overrule the enabling of VBG for faim erase/write access */
+ TFA9894N2_BF_AUDFS = 0x0203, /*!< Audio sample rate Fs */
+ TFA9894N2_BF_INPLEV = 0x0240, /*!< TDM output attenuation */
+ TFA9894N2_BF_FRACTDEL = 0x0255, /*!< Current sense fractional delay */
+ TFA9894N2_BF_TDMPRES = 0x02b1, /*!< Control for HW manager */
+ TFA9894N2_BF_AMPOCRT = 0x02d2, /*!< Amplifier on-off criteria for shutdown */
+ TFA9894N2_BF_REV = 0x030f, /*!< Revision info */
+ TFA9894N2_BF_REFCKEXT = 0x0401, /*!< PLL external reference clock */
+ TFA9894N2_BF_REFCKSEL = 0x0420, /*!< PLL internal reference clock */
+ TFA9894N2_BF_MCLKSEL = 0x0432, /*!< Master Clock Selection */
+ TFA9894N2_BF_MANAOOSC = 0x0460, /*!< Internal OSC1M off at PWDN */
+ TFA9894N2_BF_ACKCLDDIS = 0x0470, /*!< Automatic PLL reference clock selection for cold start */
+ TFA9894N2_BF_FSSYNCEN = 0x0480, /*!< Enable FS synchronisation for clock divider */
+ TFA9894N2_BF_CLKREFSYNCEN = 0x0490, /*!< Enable PLL reference clock synchronisation for clock divider */
+ TFA9894N2_BF_PLLSTUP = 0x04a0, /*!< PLL startup time configuration */
+ TFA9894N2_BF_CGUSYNCDCG = 0x0500, /*!< Clock gating control for CGU synchronisation module */
+ TFA9894N2_BF_SPKSSEN = 0x0510, /*!< Enable speaker sub-system */
+ TFA9894N2_BF_MTPSSEN = 0x0520, /*!< Enable FAIM sub-system */
+ TFA9894N2_BF_WDTCLKEN = 0x0530, /*!< Enable Coolflux watchdog clock */
+ TFA9894N2_BF_VDDS = 0x1000, /*!< POR */
+ TFA9894N2_BF_PLLS = 0x1010, /*!< PLL Lock */
+ TFA9894N2_BF_OTDS = 0x1020, /*!< OTP alarm */
+ TFA9894N2_BF_OVDS = 0x1030, /*!< OVP alarm */
+ TFA9894N2_BF_UVDS = 0x1040, /*!< UVP alarm */
+ TFA9894N2_BF_OCDS = 0x1050, /*!< OCP amplifier (sticky register, clear on read) */
+ TFA9894N2_BF_CLKS = 0x1060, /*!< Clocks stable */
+ TFA9894N2_BF_MTPB = 0x1070, /*!< MTP busy */
+ TFA9894N2_BF_NOCLK = 0x1080, /*!< Lost clock */
+ TFA9894N2_BF_ACS = 0x1090, /*!< Cold Start */
+ TFA9894N2_BF_WDS = 0x10a0, /*!< Watchdog */
+ TFA9894N2_BF_SWS = 0x10b0, /*!< Amplifier engage */
+ TFA9894N2_BF_AMPS = 0x10c0, /*!< Amplifier enable */
+ TFA9894N2_BF_AREFS = 0x10d0, /*!< References enable */
+ TFA9894N2_BF_ADCCR = 0x10e0, /*!< Control ADC */
+ TFA9894N2_BF_BODNOK = 0x10f0, /*!< BOD Flag - VDD NOT OK */
+ TFA9894N2_BF_DCIL = 0x1100, /*!< DCDC current limiting */
+ TFA9894N2_BF_DCDCA = 0x1110, /*!< DCDC active (sticky register, clear on read) */
+ TFA9894N2_BF_DCOCPOK = 0x1120, /*!< DCDC OCP nmos (sticky register, clear on read) */
+ TFA9894N2_BF_DCHVBAT = 0x1140, /*!< DCDC level 1x */
+ TFA9894N2_BF_DCH114 = 0x1150, /*!< DCDC level 1.14x */
+ TFA9894N2_BF_DCH107 = 0x1160, /*!< DCDC level 1.07x */
+ TFA9894N2_BF_SPKS = 0x1170, /*!< Speaker status */
+ TFA9894N2_BF_CLKOOR = 0x1180, /*!< External clock status */
+ TFA9894N2_BF_MANALARM = 0x1190, /*!< Alarm state */
+ TFA9894N2_BF_TDMERR = 0x11a0, /*!< TDM error */
+ TFA9894N2_BF_TDMLUTER = 0x11b0, /*!< TDM lookup table error */
+ TFA9894N2_BF_NOAUDCLK = 0x11c0, /*!< Lost Audio clock */
+ TFA9894N2_BF_OCPOAP = 0x1200, /*!< OCPOK pmos A */
+ TFA9894N2_BF_OCPOAN = 0x1210, /*!< OCPOK nmos A */
+ TFA9894N2_BF_OCPOBP = 0x1220, /*!< OCPOK pmos B */
+ TFA9894N2_BF_OCPOBN = 0x1230, /*!< OCPOK nmos B */
+ TFA9894N2_BF_CLIPS = 0x1240, /*!< Amplifier clipping */
+ TFA9894N2_BF_MANMUTE = 0x1250, /*!< Audio mute sequence */
+ TFA9894N2_BF_MANOPER = 0x1260, /*!< Device in Operating state */
+ TFA9894N2_BF_LP1 = 0x1270, /*!< Low power MODE1 detection */
+ TFA9894N2_BF_LA = 0x1280, /*!< Low amplitude detection */
+ TFA9894N2_BF_VDDPH = 0x1290, /*!< VDDP greater than VBAT flag */
+ TFA9894N2_BF_TDMSTAT = 0x1302, /*!< TDM Status bits */
+ TFA9894N2_BF_MANSTATE = 0x1333, /*!< Device Manager status */
+ TFA9894N2_BF_DCMODE = 0x13b1, /*!< DCDC mode status bits */
+ TFA9894N2_BF_BATS = 0x1509, /*!< Battery voltage (V) */
+ TFA9894N2_BF_TEMPS = 0x1608, /*!< IC Temperature (C) */
+ TFA9894N2_BF_VDDPS = 0x1709, /*!< IC VDDP voltage (1023*VDDP/13V) */
+ TFA9894N2_BF_TDME = 0x2000, /*!< Enable interface */
+ TFA9894N2_BF_TDMSPKE = 0x2010, /*!< Control audio tdm channel in sink0 */
+ TFA9894N2_BF_TDMDCE = 0x2020, /*!< Control audio tdm channel in sink1 */
+ TFA9894N2_BF_TDMCSE = 0x2030, /*!< Source 0 enable */
+ TFA9894N2_BF_TDMVSE = 0x2040, /*!< Source 1 enable */
+ TFA9894N2_BF_TDMCFE = 0x2050, /*!< Source 2 enable */
+ TFA9894N2_BF_TDMCF2E = 0x2060, /*!< Source 3 enable */
+ TFA9894N2_BF_TDMCLINV = 0x2070, /*!< Reception data to BCK clock */
+ TFA9894N2_BF_TDMFSPOL = 0x2080, /*!< FS polarity */
+ TFA9894N2_BF_TDMDEL = 0x2090, /*!< Data delay to FS */
+ TFA9894N2_BF_TDMADJ = 0x20a0, /*!< Data adjustment */
+ TFA9894N2_BF_TDMOOMP = 0x20b1, /*!< Received audio compression */
+ TFA9894N2_BF_TDMNBCK = 0x2103, /*!< TDM NBCK - Bit clock to FS ratio */
+ TFA9894N2_BF_TDMFSLN = 0x2143, /*!< FS length (master mode only) */
+ TFA9894N2_BF_TDMSLOTS = 0x2183, /*!< N-slots in Frame */
+ TFA9894N2_BF_TDMTXDFO = 0x21c1, /*!< Format unused bits */
+ TFA9894N2_BF_TDMTXUS0 = 0x21e1, /*!< Format unused slots DATAO */
+ TFA9894N2_BF_TDMSLLN = 0x2204, /*!< N-bits in slot */
+ TFA9894N2_BF_TDMBRMG = 0x2254, /*!< N-bits remaining */
+ TFA9894N2_BF_TDMSSIZE = 0x22a4, /*!< Sample size per slot */
+ TFA9894N2_BF_TDMSPKS = 0x2303, /*!< TDM slot for sink 0 */
+ TFA9894N2_BF_TDMDCS = 0x2343, /*!< TDM slot for sink 1 */
+ TFA9894N2_BF_TDMCFSEL = 0x2381, /*!< TDM Source 2 data selection */
+ TFA9894N2_BF_TDMCF2SEL = 0x23a1, /*!< TDM Source 3 data selection */
+ TFA9894N2_BF_TDMCSS = 0x2403, /*!< Slot position of source 0 data */
+ TFA9894N2_BF_TDMVSS = 0x2443, /*!< Slot position of source 1 data */
+ TFA9894N2_BF_TDMCFS = 0x2483, /*!< Slot position of source 2 data */
+ TFA9894N2_BF_TDMCF2S = 0x24c3, /*!< Slot position of source 3 data */
+ TFA9894N2_BF_ISTVDDS = 0x4000, /*!< Status POR */
+ TFA9894N2_BF_ISTBSTOC = 0x4010, /*!< Status DCDC OCP */
+ TFA9894N2_BF_ISTOTDS = 0x4020, /*!< Status OTP alarm */
+ TFA9894N2_BF_ISTOCPR = 0x4030, /*!< Status OCP alarm */
+ TFA9894N2_BF_ISTUVDS = 0x4040, /*!< Status UVP alarm */
+ TFA9894N2_BF_ISTMANALARM = 0x4050, /*!< Status manager alarm state */
+ TFA9894N2_BF_ISTTDMER = 0x4060, /*!< Status TDM error */
+ TFA9894N2_BF_ISTNOCLK = 0x4070, /*!< Status lost clock */
+ TFA9894N2_BF_ISTCFMER = 0x4080, /*!< Status cfma error */
+ TFA9894N2_BF_ISTCFMAC = 0x4090, /*!< Status cfma ack */
+ TFA9894N2_BF_ISTSPKS = 0x40a0, /*!< Status coolflux speaker error */
+ TFA9894N2_BF_ISTACS = 0x40b0, /*!< Status cold started */
+ TFA9894N2_BF_ISTWDS = 0x40c0, /*!< Status watchdog reset */
+ TFA9894N2_BF_ISTBODNOK = 0x40d0, /*!< Status brown out detect */
+ TFA9894N2_BF_ISTLP1 = 0x40e0, /*!< Status low power mode1 detect */
+ TFA9894N2_BF_ISTCLKOOR = 0x40f0, /*!< Status clock out of range */
+ TFA9894N2_BF_ICLVDDS = 0x4400, /*!< Clear POR */
+ TFA9894N2_BF_ICLBSTOC = 0x4410, /*!< Clear DCDC OCP */
+ TFA9894N2_BF_ICLOTDS = 0x4420, /*!< Clear OTP alarm */
+ TFA9894N2_BF_ICLOCPR = 0x4430, /*!< Clear OCP alarm */
+ TFA9894N2_BF_ICLUVDS = 0x4440, /*!< Clear UVP alarm */
+ TFA9894N2_BF_ICLMANALARM = 0x4450, /*!< Clear manager alarm state */
+ TFA9894N2_BF_ICLTDMER = 0x4460, /*!< Clear TDM error */
+ TFA9894N2_BF_ICLNOCLK = 0x4470, /*!< Clear lost clk */
+ TFA9894N2_BF_ICLCFMER = 0x4480, /*!< Clear cfma err */
+ TFA9894N2_BF_ICLCFMAC = 0x4490, /*!< Clear cfma ack */
+ TFA9894N2_BF_ICLSPKS = 0x44a0, /*!< Clear coolflux speaker error */
+ TFA9894N2_BF_ICLACS = 0x44b0, /*!< Clear cold started */
+ TFA9894N2_BF_ICLWDS = 0x44c0, /*!< Clear watchdog reset */
+ TFA9894N2_BF_ICLBODNOK = 0x44d0, /*!< Clear brown out detect */
+ TFA9894N2_BF_ICLLP1 = 0x44e0, /*!< Clear low power mode1 detect */
+ TFA9894N2_BF_ICLCLKOOR = 0x44f0, /*!< Clear clock out of range */
+ TFA9894N2_BF_IEVDDS = 0x4800, /*!< Enable POR */
+ TFA9894N2_BF_IEBSTOC = 0x4810, /*!< Enable DCDC OCP */
+ TFA9894N2_BF_IEOTDS = 0x4820, /*!< Enable OTP alarm */
+ TFA9894N2_BF_IEOCPR = 0x4830, /*!< Enable OCP alarm */
+ TFA9894N2_BF_IEUVDS = 0x4840, /*!< Enable UVP alarm */
+ TFA9894N2_BF_IEMANALARM = 0x4850, /*!< Enable Manager Alarm state */
+ TFA9894N2_BF_IETDMER = 0x4860, /*!< Enable TDM error */
+ TFA9894N2_BF_IENOCLK = 0x4870, /*!< Enable lost clk */
+ TFA9894N2_BF_IECFMER = 0x4880, /*!< Enable cfma err */
+ TFA9894N2_BF_IECFMAC = 0x4890, /*!< Enable cfma ack */
+ TFA9894N2_BF_IESPKS = 0x48a0, /*!< Enable coolflux speaker error */
+ TFA9894N2_BF_IEACS = 0x48b0, /*!< Enable cold started */
+ TFA9894N2_BF_IEWDS = 0x48c0, /*!< Enable watchdog reset */
+ TFA9894N2_BF_IEBODNOK = 0x48d0, /*!< Enable brown out detect */
+ TFA9894N2_BF_IELP1 = 0x48e0, /*!< Enable low power mode1 detect */
+ TFA9894N2_BF_IECLKOOR = 0x48f0, /*!< Enable clock out of range */
+ TFA9894N2_BF_IPOVDDS = 0x4c00, /*!< Polarity POR */
+ TFA9894N2_BF_IPOBSTOC = 0x4c10, /*!< Polarity DCDC OCP */
+ TFA9894N2_BF_IPOOTDS = 0x4c20, /*!< Polarity OTP alarm */
+ TFA9894N2_BF_IPOOCPR = 0x4c30, /*!< Polarity ocp alarm */
+ TFA9894N2_BF_IPOUVDS = 0x4c40, /*!< Polarity UVP alarm */
+ TFA9894N2_BF_IPOMANALARM = 0x4c50, /*!< Polarity manager alarm state */
+ TFA9894N2_BF_IPOTDMER = 0x4c60, /*!< Polarity TDM error */
+ TFA9894N2_BF_IPONOCLK = 0x4c70, /*!< Polarity lost clk */
+ TFA9894N2_BF_IPOCFMER = 0x4c80, /*!< Polarity cfma err */
+ TFA9894N2_BF_IPOCFMAC = 0x4c90, /*!< Polarity cfma ack */
+ TFA9894N2_BF_IPOSPKS = 0x4ca0, /*!< Polarity coolflux speaker error */
+ TFA9894N2_BF_IPOACS = 0x4cb0, /*!< Polarity cold started */
+ TFA9894N2_BF_IPOWDS = 0x4cc0, /*!< Polarity watchdog reset */
+ TFA9894N2_BF_IPOBODNOK = 0x4cd0, /*!< Polarity brown out detect */
+ TFA9894N2_BF_IPOLP1 = 0x4ce0, /*!< Polarity low power mode1 detect */
+ TFA9894N2_BF_IPOCLKOOR = 0x4cf0, /*!< Polarity clock out of range */
+ TFA9894N2_BF_BSSCR = 0x5001, /*!< Battery safeguard attack time */
+ TFA9894N2_BF_BSST = 0x5023, /*!< Battery safeguard threshold voltage level */
+ TFA9894N2_BF_BSSRL = 0x5061, /*!< Battery safeguard maximum reduction */
+ TFA9894N2_BF_BSSRR = 0x5082, /*!< Battery safeguard release time */
+ TFA9894N2_BF_BSSHY = 0x50b1, /*!< Battery Safeguard hysteresis */
+ TFA9894N2_BF_BSSR = 0x50e0, /*!< Battery voltage read out */
+ TFA9894N2_BF_BSSBY = 0x50f0, /*!< Bypass HW clipper */
+ TFA9894N2_BF_CFSM = 0x5130, /*!< Coolflux firmware soft mute control */
+ TFA9894N2_BF_VOL = 0x5187, /*!< CF firmware volume control */
+ TFA9894N2_BF_CLIPCTRL = 0x5202, /*!< Clip control setting */
+ TFA9894N2_BF_SLOPEE = 0x5230, /*!< Enables slope control */
+ TFA9894N2_BF_SLOPESET = 0x5240, /*!< Slope speed setting (binary coded) */
+ TFA9894N2_BF_BYPDLYLINE = 0x5250, /*!< Bypass the interpolator delay line */
+ TFA9894N2_BF_AMPGAIN = 0x5287, /*!< Amplifier gain */
+ TFA9894N2_BF_TDMDCG = 0x5703, /*!< Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE) */
+ TFA9894N2_BF_TDMSPKG = 0x5743, /*!< Total gain depending on INPLEV setting (channel 0) */
+ TFA9894N2_BF_DCINSEL = 0x5781, /*!< VAMP_OUT2 input selection */
+ TFA9894N2_BF_LNMODE = 0x5881, /*!< Low noise gain mode control */
+ TFA9894N2_BF_LPM1MODE = 0x5ac1, /*!< Low power mode control */
+ TFA9894N2_BF_TDMSRCMAP = 0x5d02, /*!< TDM source mapping */
+ TFA9894N2_BF_TDMSRCAS = 0x5d31, /*!< Sensed value A */
+ TFA9894N2_BF_TDMSRCBS = 0x5d51, /*!< Sensed value B */
+ TFA9894N2_BF_TDMSRCACLIP = 0x5d71, /*!< Clip information (analog /digital) for source0 */
+ TFA9894N2_BF_TDMSRCBCLIP = 0x5d91, /*!< Clip information (analog /digital) for source1 */
+ TFA9894N2_BF_DELCURCOMP = 0x6102, /*!< Delay to allign compensation signal with current sense signal */
+ TFA9894N2_BF_SIGCURCOMP = 0x6130, /*!< Polarity of compensation for current sense */
+ TFA9894N2_BF_ENCURCOMP = 0x6140, /*!< Enable current sense compensation */
+ TFA9894N2_BF_LVLCLPPWM = 0x6152, /*!< Set the amount of pwm pulse that may be skipped before clip-flag is triggered */
+ TFA9894N2_BF_DCVOF = 0x7005, /*!< First Boost Voltage Level */
+ TFA9894N2_BF_DCVOS = 0x7065, /*!< Second Boost Voltage Level */
+ TFA9894N2_BF_DCMCC = 0x70c3, /*!< Max Coil Current */
+ TFA9894N2_BF_DCCV = 0x7101, /*!< Slope compensation current, represents LxF (inductance x frequency) value */
+ TFA9894N2_BF_DCIE = 0x7120, /*!< Adaptive boost mode */
+ TFA9894N2_BF_DCSR = 0x7130, /*!< Soft ramp up/down */
+ TFA9894N2_BF_DCDIS = 0x7140, /*!< DCDC on/off */
+ TFA9894N2_BF_DCPWM = 0x7150, /*!< DCDC PWM only mode */
+ TFA9894N2_BF_DCTRACK = 0x7160, /*!< Boost algorithm selection, effective only when boost_intelligent is set to 1 */
+ TFA9894N2_BF_DCENVSEL = 0x7170, /*!< Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1 */
+ TFA9894N2_BF_OVSCTLVL = 0x7195, /*!< Threshold level to activate active overshoot control */
+ TFA9894N2_BF_DCTRIP = 0x7204, /*!< 1st adaptive boost trip levels, effective only when DCIE is set to 1 */
+ TFA9894N2_BF_DCTRIP2 = 0x7254, /*!< 2nd adaptive boost trip levels, effective only when DCIE is set to 1 */
+ TFA9894N2_BF_DCTRIPT = 0x72a4, /*!< Track adaptive boost trip levels, effective only when boost_intelligent is set to 1 */
+ TFA9894N2_BF_DCTRIPHYSTE = 0x72f0, /*!< Enable hysteresis on booster trip levels */
+ TFA9894N2_BF_DCHOLD = 0x7304, /*!< Hold time / Hysteresis for DCDC booster, effective only when boost_intelligent is set to 1 */
+ TFA9894N2_BF_RST = 0x9000, /*!< Reset for Coolflux DSP */
+ TFA9894N2_BF_DMEM = 0x9011, /*!< Target memory for CFMA using I2C interface */
+ TFA9894N2_BF_AIF = 0x9030, /*!< Auto increment */
+ TFA9894N2_BF_CFINT = 0x9040, /*!< Coolflux Interrupt - auto clear */
+ TFA9894N2_BF_CFCGATE = 0x9050, /*!< Coolflux clock gating disabling control */
+ TFA9894N2_BF_REQCMD = 0x9080, /*!< Firmware event request rpc command */
+ TFA9894N2_BF_REQRST = 0x9090, /*!< Firmware event request reset restart */
+ TFA9894N2_BF_REQMIPS = 0x90a0, /*!< Firmware event request short on mips */
+ TFA9894N2_BF_REQMUTED = 0x90b0, /*!< Firmware event request mute sequence ready */
+ TFA9894N2_BF_REQVOL = 0x90c0, /*!< Firmware event request volume ready */
+ TFA9894N2_BF_REQDMG = 0x90d0, /*!< Firmware event request speaker damage detected */
+ TFA9894N2_BF_REQCAL = 0x90e0, /*!< Firmware event request calibration completed */
+ TFA9894N2_BF_REQRSV = 0x90f0, /*!< Firmware event request reserved */
+ TFA9894N2_BF_MADD = 0x910f, /*!< CF memory address */
+ TFA9894N2_BF_MEMA = 0x920f, /*!< Activate memory access */
+ TFA9894N2_BF_ERR = 0x9307, /*!< CF error flags */
+ TFA9894N2_BF_ACKCMD = 0x9380, /*!< Firmware event acknowledge rpc command */
+ TFA9894N2_BF_ACKRST = 0x9390, /*!< Firmware event acknowledge reset restart */
+ TFA9894N2_BF_ACKMIPS = 0x93a0, /*!< Firmware event acknowledge short on mips */
+ TFA9894N2_BF_ACKMUTED = 0x93b0, /*!< Firmware event acknowledge mute sequence ready */
+ TFA9894N2_BF_ACKVOL = 0x93c0, /*!< Firmware event acknowledge volume ready */
+ TFA9894N2_BF_ACKDMG = 0x93d0, /*!< Firmware event acknowledge speaker damage detected */
+ TFA9894N2_BF_ACKCAL = 0x93e0, /*!< Firmware event acknowledge calibration completed */
+ TFA9894N2_BF_ACKRSV = 0x93f0, /*!< Firmware event acknowledge reserved */
+ TFA9894N2_BF_MTPK = 0xa107, /*!< KEY2 to access KEY2 protected registers, customer key */
+ TFA9894N2_BF_KEY1LOCKED = 0xa200, /*!< Indicates KEY1 is locked */
+ TFA9894N2_BF_KEY2LOCKED = 0xa210, /*!< Indicates KEY2 is locked */
+ TFA9894N2_BF_CMTPI = 0xa350, /*!< Start copying all the data from mtp to I2C mtp registers - auto clear */
+ TFA9894N2_BF_CIMTP = 0xa360, /*!< Start copying data from I2C mtp registers to mtp - auto clear */
+ TFA9894N2_BF_MTPRDMSB = 0xa50f, /*!< MSB word of MTP manual read data */
+ TFA9894N2_BF_MTPRDLSB = 0xa60f, /*!< LSB word of MTP manual read data */
+ TFA9894N2_BF_EXTTS = 0xb108, /*!< External temperature (C) */
+ TFA9894N2_BF_TROS = 0xb190, /*!< Select temp Speaker calibration */
+ TFA9894N2_BF_PLLINSELI = 0xca05, /*!< PLL INSELI - PLL direct bandwidth control mode only with pll_bandsel set to 1 */
+ TFA9894N2_BF_PLLINSELP = 0xca64, /*!< PLL INSELP - PLL direct bandwidth control mode only with pll_bandsel set to 1 */
+ TFA9894N2_BF_PLLINSELR = 0xcab3, /*!< PLL INSELR - PLL direct bandwidth control mode only with pll_bandsel set to 1 */
+ TFA9894N2_BF_PLLNDEC = 0xcb09, /*!< PLL NDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
+ TFA9894N2_BF_PLLMDECMSB = 0xcba0, /*!< MSB of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
+ TFA9894N2_BF_PLLBYPASS = 0xcbb0, /*!< PLL bypass control during functional mode */
+ TFA9894N2_BF_PLLDIRECTI = 0xcbc0, /*!< PLL directi control in direct control mode only, use_direct_pll_ctrl set to 1 */
+ TFA9894N2_BF_PLLDIRECTO = 0xcbd0, /*!< PLL directo control in direct control mode only, use_direct_pll_ctrl set to 1 */
+ TFA9894N2_BF_PLLFRMSTBL = 0xcbe0, /*!< PLL FRM clock stable control in direct control mode only, use_direct_pll_ctrl set to 1 */
+ TFA9894N2_BF_PLLFRM = 0xcbf0, /*!< PLL free running mode control in functional mode */
+ TFA9894N2_BF_PLLMDECLSB = 0xcc0f, /*!< Bits 15..0 of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
+ TFA9894N2_BF_PLLPDEC = 0xcd06, /*!< PLL PDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
+ TFA9894N2_BF_DIRECTPLL = 0xcd70, /*!< Enabled PLL direct control mode, overrules the PLL LUT with I2C register values */
+ TFA9894N2_BF_DIRECTCLK = 0xcd80, /*!< Enabled CGU clock divider direct control mode */
+ TFA9894N2_BF_PLLLIM = 0xcd90, /*!< PLL up limiter control in PLL direct bandwidth control mode, pll_bandsel set to 1 */
+ TFA9894N2_BF_SWPROFIL = 0xe00f, /*!< Software profile data */
+ TFA9894N2_BF_SWVSTEP = 0xe10f, /*!< Software vstep information */
+ TFA9894N2_BF_MTPOTC = 0xf000, /*!< Calibration schedule */
+ TFA9894N2_BF_MTPEX = 0xf010, /*!< Calibration Ron executed */
+ TFA9894N2_BF_DCMCCAPI = 0xf020, /*!< Calibration current limit DCDC */
+ TFA9894N2_BF_DCMCCSB = 0xf030, /*!< Sign bit for delta calibration current limit DCDC */
+ TFA9894N2_BF_USERDEF = 0xf042, /*!< Calibration delta current limit DCDC */
+ TFA9894N2_BF_CUSTINFO = 0xf078, /*!< Reserved space for allowing customer to store speaker information */
+ TFA9894N2_BF_R25C = 0xf50f, /*!< Ron resistance of speaker coil */
+} nxpTfa9894N2BfEnumList_t;
+#define TFA9894N2_NAMETABLE static tfaBfName_t Tfa9894N2DatasheetNames[] = {\
+ { 0x0, "PWDN"}, /* Powerdown control , */\
+ { 0x10, "I2CR"}, /* I2C Reset - Auto clear , */\
+ { 0x20, "CFE"}, /* Enable CoolFlux DSP , */\
+ { 0x30, "AMPE"}, /* Enable Amplifier , */\
+ { 0x40, "DCA"}, /* Enable DCDC Boost converter , */\
+ { 0x50, "SBSL"}, /* Coolflux configured , */\
+ { 0x60, "AMPC"}, /* CoolFlux control over amplifier , */\
+ { 0x71, "INTP"}, /* Interrupt config , */\
+ { 0x90, "FSSSEL"}, /* Audio sample reference , */\
+ { 0xa0, "BYPOCP"}, /* Bypass OCP , */\
+ { 0xb0, "TSTOCP"}, /* OCP testing control , */\
+ { 0xc0, "BSSS"}, /* Vbat protection steepness , */\
+ { 0xd0, "HPFBYP"}, /* Bypass High Pass Filter , */\
+ { 0xe0, "DPSA"}, /* Enable DPSA , */\
+ { 0x101, "AMPINSEL"}, /* Amplifier input selection , */\
+ { 0x120, "MANSCONF"}, /* Device I2C settings configured , */\
+ { 0x130, "MANCOLD"}, /* Execute cold start , */\
+ { 0x140, "MANROBOD"}, /* Reaction on BOD , */\
+ { 0x150, "BODE"}, /* Enable BOD (only in direct control mode) , */\
+ { 0x160, "BODHYS"}, /* Enable Hysteresis of BOD , */\
+ { 0x171, "BODFILT"}, /* BOD filter , */\
+ { 0x191, "BODTHLVL"}, /* BOD threshold , */\
+ { 0x1b0, "MUTETO"}, /* Time out SB mute sequence , */\
+ { 0x1c0, "MANWDE"}, /* Watchdog enable , */\
+ { 0x1e0, "OPENMTP"}, /* Control for FAIM protection , */\
+ { 0x1f0, "FAIMVBGOVRRL"}, /* Overrule the enabling of VBG for faim erase/write access, */\
+ { 0x203, "AUDFS"}, /* Audio sample rate Fs , */\
+ { 0x240, "INPLEV"}, /* TDM output attenuation , */\
+ { 0x255, "FRACTDEL"}, /* Current sense fractional delay , */\
+ { 0x2b1, "TDMPRES"}, /* Control for HW manager , */\
+ { 0x2d2, "AMPOCRT"}, /* Amplifier on-off criteria for shutdown , */\
+ { 0x30f, "REV"}, /* Revision info , */\
+ { 0x401, "REFCKEXT"}, /* PLL external reference clock , */\
+ { 0x420, "REFCKSEL"}, /* PLL internal reference clock , */\
+ { 0x432, "MCLKSEL"}, /* Master Clock Selection , */\
+ { 0x460, "MANAOOSC"}, /* Internal OSC1M off at PWDN , */\
+ { 0x470, "ACKCLDDIS"}, /* Automatic PLL reference clock selection for cold start, */\
+ { 0x480, "FSSYNCEN"}, /* Enable FS synchronisation for clock divider , */\
+ { 0x490, "CLKREFSYNCEN"}, /* Enable PLL reference clock synchronisation for clock divider, */\
+ { 0x4a0, "PLLSTUP"}, /* PLL startup time configuration , */\
+ { 0x500, "CGUSYNCDCG"}, /* Clock gating control for CGU synchronisation module, */\
+ { 0x510, "SPKSSEN"}, /* Enable speaker sub-system , */\
+ { 0x520, "MTPSSEN"}, /* Enable FAIM sub-system , */\
+ { 0x530, "WDTCLKEN"}, /* Enable Coolflux watchdog clock , */\
+ { 0x1000, "VDDS"}, /* POR , */\
+ { 0x1010, "PLLS"}, /* PLL Lock , */\
+ { 0x1020, "OTDS"}, /* OTP alarm , */\
+ { 0x1030, "OVDS"}, /* OVP alarm , */\
+ { 0x1040, "UVDS"}, /* UVP alarm , */\
+ { 0x1050, "OCDS"}, /* OCP amplifier (sticky register, clear on read) , */\
+ { 0x1060, "CLKS"}, /* Clocks stable , */\
+ { 0x1070, "MTPB"}, /* MTP busy , */\
+ { 0x1080, "NOCLK"}, /* Lost clock , */\
+ { 0x1090, "ACS"}, /* Cold Start , */\
+ { 0x10a0, "WDS"}, /* Watchdog , */\
+ { 0x10b0, "SWS"}, /* Amplifier engage , */\
+ { 0x10c0, "AMPS"}, /* Amplifier enable , */\
+ { 0x10d0, "AREFS"}, /* References enable , */\
+ { 0x10e0, "ADCCR"}, /* Control ADC , */\
+ { 0x10f0, "BODNOK"}, /* BOD Flag - VDD NOT OK , */\
+ { 0x1100, "DCIL"}, /* DCDC current limiting , */\
+ { 0x1110, "DCDCA"}, /* DCDC active (sticky register, clear on read) , */\
+ { 0x1120, "DCOCPOK"}, /* DCDC OCP nmos (sticky register, clear on read) , */\
+ { 0x1140, "DCHVBAT"}, /* DCDC level 1x , */\
+ { 0x1150, "DCH114"}, /* DCDC level 1.14x , */\
+ { 0x1160, "DCH107"}, /* DCDC level 1.07x , */\
+ { 0x1170, "SPKS"}, /* Speaker status , */\
+ { 0x1180, "CLKOOR"}, /* External clock status , */\
+ { 0x1190, "MANALARM"}, /* Alarm state , */\
+ { 0x11a0, "TDMERR"}, /* TDM error , */\
+ { 0x11b0, "TDMLUTER"}, /* TDM lookup table error , */\
+ { 0x11c0, "NOAUDCLK"}, /* Lost Audio clock , */\
+ { 0x1200, "OCPOAP"}, /* OCPOK pmos A , */\
+ { 0x1210, "OCPOAN"}, /* OCPOK nmos A , */\
+ { 0x1220, "OCPOBP"}, /* OCPOK pmos B , */\
+ { 0x1230, "OCPOBN"}, /* OCPOK nmos B , */\
+ { 0x1240, "CLIPS"}, /* Amplifier clipping , */\
+ { 0x1250, "MANMUTE"}, /* Audio mute sequence , */\
+ { 0x1260, "MANOPER"}, /* Device in Operating state , */\
+ { 0x1270, "LP1"}, /* Low power MODE1 detection , */\
+ { 0x1280, "LA"}, /* Low amplitude detection , */\
+ { 0x1290, "VDDPH"}, /* VDDP greater than VBAT flag , */\
+ { 0x1302, "TDMSTAT"}, /* TDM Status bits , */\
+ { 0x1333, "MANSTATE"}, /* Device Manager status , */\
+ { 0x13b1, "DCMODE"}, /* DCDC mode status bits , */\
+ { 0x1509, "BATS"}, /* Battery voltage (V) , */\
+ { 0x1608, "TEMPS"}, /* IC Temperature (C) , */\
+ { 0x1709, "VDDPS"}, /* IC VDDP voltage (1023*VDDP/13V) , */\
+ { 0x2000, "TDME"}, /* Enable interface , */\
+ { 0x2010, "TDMSPKE"}, /* Control audio tdm channel in sink0 , */\
+ { 0x2020, "TDMDCE"}, /* Control audio tdm channel in sink1 , */\
+ { 0x2030, "TDMCSE"}, /* Source 0 enable , */\
+ { 0x2040, "TDMVSE"}, /* Source 1 enable , */\
+ { 0x2050, "TDMCFE"}, /* Source 2 enable , */\
+ { 0x2060, "TDMCF2E"}, /* Source 3 enable , */\
+ { 0x2070, "TDMCLINV"}, /* Reception data to BCK clock , */\
+ { 0x2080, "TDMFSPOL"}, /* FS polarity , */\
+ { 0x2090, "TDMDEL"}, /* Data delay to FS , */\
+ { 0x20a0, "TDMADJ"}, /* Data adjustment , */\
+ { 0x20b1, "TDMOOMP"}, /* Received audio compression , */\
+ { 0x2103, "TDMNBCK"}, /* TDM NBCK - Bit clock to FS ratio , */\
+ { 0x2143, "TDMFSLN"}, /* FS length (master mode only) , */\
+ { 0x2183, "TDMSLOTS"}, /* N-slots in Frame , */\
+ { 0x21c1, "TDMTXDFO"}, /* Format unused bits , */\
+ { 0x21e1, "TDMTXUS0"}, /* Format unused slots DATAO , */\
+ { 0x2204, "TDMSLLN"}, /* N-bits in slot , */\
+ { 0x2254, "TDMBRMG"}, /* N-bits remaining , */\
+ { 0x22a4, "TDMSSIZE"}, /* Sample size per slot , */\
+ { 0x2303, "TDMSPKS"}, /* TDM slot for sink 0 , */\
+ { 0x2343, "TDMDCS"}, /* TDM slot for sink 1 , */\
+ { 0x2381, "TDMCFSEL"}, /* TDM Source 2 data selection , */\
+ { 0x23a1, "TDMCF2SEL"}, /* TDM Source 3 data selection , */\
+ { 0x2403, "TDMCSS"}, /* Slot position of source 0 data , */\
+ { 0x2443, "TDMVSS"}, /* Slot position of source 1 data , */\
+ { 0x2483, "TDMCFS"}, /* Slot position of source 2 data , */\
+ { 0x24c3, "TDMCF2S"}, /* Slot position of source 3 data , */\
+ { 0x4000, "ISTVDDS"}, /* Status POR , */\
+ { 0x4010, "ISTBSTOC"}, /* Status DCDC OCP , */\
+ { 0x4020, "ISTOTDS"}, /* Status OTP alarm , */\
+ { 0x4030, "ISTOCPR"}, /* Status OCP alarm , */\
+ { 0x4040, "ISTUVDS"}, /* Status UVP alarm , */\
+ { 0x4050, "ISTMANALARM"}, /* Status manager alarm state , */\
+ { 0x4060, "ISTTDMER"}, /* Status TDM error , */\
+ { 0x4070, "ISTNOCLK"}, /* Status lost clock , */\
+ { 0x4080, "ISTCFMER"}, /* Status cfma error , */\
+ { 0x4090, "ISTCFMAC"}, /* Status cfma ack , */\
+ { 0x40a0, "ISTSPKS"}, /* Status coolflux speaker error , */\
+ { 0x40b0, "ISTACS"}, /* Status cold started , */\
+ { 0x40c0, "ISTWDS"}, /* Status watchdog reset , */\
+ { 0x40d0, "ISTBODNOK"}, /* Status brown out detect , */\
+ { 0x40e0, "ISTLP1"}, /* Status low power mode1 detect , */\
+ { 0x40f0, "ISTCLKOOR"}, /* Status clock out of range , */\
+ { 0x4400, "ICLVDDS"}, /* Clear POR , */\
+ { 0x4410, "ICLBSTOC"}, /* Clear DCDC OCP , */\
+ { 0x4420, "ICLOTDS"}, /* Clear OTP alarm , */\
+ { 0x4430, "ICLOCPR"}, /* Clear OCP alarm , */\
+ { 0x4440, "ICLUVDS"}, /* Clear UVP alarm , */\
+ { 0x4450, "ICLMANALARM"}, /* Clear manager alarm state , */\
+ { 0x4460, "ICLTDMER"}, /* Clear TDM error , */\
+ { 0x4470, "ICLNOCLK"}, /* Clear lost clk , */\
+ { 0x4480, "ICLCFMER"}, /* Clear cfma err , */\
+ { 0x4490, "ICLCFMAC"}, /* Clear cfma ack , */\
+ { 0x44a0, "ICLSPKS"}, /* Clear coolflux speaker error , */\
+ { 0x44b0, "ICLACS"}, /* Clear cold started , */\
+ { 0x44c0, "ICLWDS"}, /* Clear watchdog reset , */\
+ { 0x44d0, "ICLBODNOK"}, /* Clear brown out detect , */\
+ { 0x44e0, "ICLLP1"}, /* Clear low power mode1 detect , */\
+ { 0x44f0, "ICLCLKOOR"}, /* Clear clock out of range , */\
+ { 0x4800, "IEVDDS"}, /* Enable POR , */\
+ { 0x4810, "IEBSTOC"}, /* Enable DCDC OCP , */\
+ { 0x4820, "IEOTDS"}, /* Enable OTP alarm , */\
+ { 0x4830, "IEOCPR"}, /* Enable OCP alarm , */\
+ { 0x4840, "IEUVDS"}, /* Enable UVP alarm , */\
+ { 0x4850, "IEMANALARM"}, /* Enable Manager Alarm state , */\
+ { 0x4860, "IETDMER"}, /* Enable TDM error , */\
+ { 0x4870, "IENOCLK"}, /* Enable lost clk , */\
+ { 0x4880, "IECFMER"}, /* Enable cfma err , */\
+ { 0x4890, "IECFMAC"}, /* Enable cfma ack , */\
+ { 0x48a0, "IESPKS"}, /* Enable coolflux speaker error , */\
+ { 0x48b0, "IEACS"}, /* Enable cold started , */\
+ { 0x48c0, "IEWDS"}, /* Enable watchdog reset , */\
+ { 0x48d0, "IEBODNOK"}, /* Enable brown out detect , */\
+ { 0x48e0, "IELP1"}, /* Enable low power mode1 detect , */\
+ { 0x48f0, "IECLKOOR"}, /* Enable clock out of range , */\
+ { 0x4c00, "IPOVDDS"}, /* Polarity POR , */\
+ { 0x4c10, "IPOBSTOC"}, /* Polarity DCDC OCP , */\
+ { 0x4c20, "IPOOTDS"}, /* Polarity OTP alarm , */\
+ { 0x4c30, "IPOOCPR"}, /* Polarity ocp alarm , */\
+ { 0x4c40, "IPOUVDS"}, /* Polarity UVP alarm , */\
+ { 0x4c50, "IPOMANALARM"}, /* Polarity manager alarm state , */\
+ { 0x4c60, "IPOTDMER"}, /* Polarity TDM error , */\
+ { 0x4c70, "IPONOCLK"}, /* Polarity lost clk , */\
+ { 0x4c80, "IPOCFMER"}, /* Polarity cfma err , */\
+ { 0x4c90, "IPOCFMAC"}, /* Polarity cfma ack , */\
+ { 0x4ca0, "IPOSPKS"}, /* Polarity coolflux speaker error , */\
+ { 0x4cb0, "IPOACS"}, /* Polarity cold started , */\
+ { 0x4cc0, "IPOWDS"}, /* Polarity watchdog reset , */\
+ { 0x4cd0, "IPOBODNOK"}, /* Polarity brown out detect , */\
+ { 0x4ce0, "IPOLP1"}, /* Polarity low power mode1 detect , */\
+ { 0x4cf0, "IPOCLKOOR"}, /* Polarity clock out of range , */\
+ { 0x5001, "BSSCR"}, /* Battery safeguard attack time , */\
+ { 0x5023, "BSST"}, /* Battery safeguard threshold voltage level , */\
+ { 0x5061, "BSSRL"}, /* Battery safeguard maximum reduction , */\
+ { 0x5082, "BSSRR"}, /* Battery safeguard release time , */\
+ { 0x50b1, "BSSHY"}, /* Battery Safeguard hysteresis , */\
+ { 0x50e0, "BSSR"}, /* Battery voltage read out , */\
+ { 0x50f0, "BSSBY"}, /* Bypass HW clipper , */\
+ { 0x5130, "CFSM"}, /* Coolflux firmware soft mute control , */\
+ { 0x5187, "VOL"}, /* CF firmware volume control , */\
+ { 0x5202, "CLIPCTRL"}, /* Clip control setting , */\
+ { 0x5230, "SLOPEE"}, /* Enables slope control , */\
+ { 0x5240, "SLOPESET"}, /* Slope speed setting (binary coded) , */\
+ { 0x5250, "BYPDLYLINE"}, /* Bypass the interpolator delay line , */\
+ { 0x5287, "AMPGAIN"}, /* Amplifier gain , */\
+ { 0x5703, "TDMDCG"}, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */\
+ { 0x5743, "TDMSPKG"}, /* Total gain depending on INPLEV setting (channel 0), */\
+ { 0x5781, "DCINSEL"}, /* VAMP_OUT2 input selection , */\
+ { 0x5881, "LNMODE"}, /* Low noise gain mode control , */\
+ { 0x5ac1, "LPM1MODE"}, /* Low power mode control , */\
+ { 0x5d02, "TDMSRCMAP"}, /* TDM source mapping , */\
+ { 0x5d31, "TDMSRCAS"}, /* Sensed value A , */\
+ { 0x5d51, "TDMSRCBS"}, /* Sensed value B , */\
+ { 0x5d71, "TDMSRCACLIP"}, /* Clip information (analog /digital) for source0 , */\
+ { 0x5d91, "TDMSRCBCLIP"}, /* Clip information (analog /digital) for source1 , */\
+ { 0x6102, "DELCURCOMP"}, /* Delay to allign compensation signal with current sense signal, */\
+ { 0x6130, "SIGCURCOMP"}, /* Polarity of compensation for current sense , */\
+ { 0x6140, "ENCURCOMP"}, /* Enable current sense compensation , */\
+ { 0x6152, "LVLCLPPWM"}, /* Set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
+ { 0x7005, "DCVOF"}, /* First Boost Voltage Level , */\
+ { 0x7065, "DCVOS"}, /* Second Boost Voltage Level , */\
+ { 0x70c3, "DCMCC"}, /* Max Coil Current , */\
+ { 0x7101, "DCCV"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
+ { 0x7120, "DCIE"}, /* Adaptive boost mode , */\
+ { 0x7130, "DCSR"}, /* Soft ramp up/down , */\
+ { 0x7140, "DCDIS"}, /* DCDC on/off , */\
+ { 0x7150, "DCPWM"}, /* DCDC PWM only mode , */\
+ { 0x7160, "DCTRACK"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
+ { 0x7170, "DCENVSEL"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
+ { 0x7195, "OVSCTLVL"}, /* Threshold level to activate active overshoot control, */\
+ { 0x7204, "DCTRIP"}, /* 1st adaptive boost trip levels, effective only when DCIE is set to 1, */\
+ { 0x7254, "DCTRIP2"}, /* 2nd adaptive boost trip levels, effective only when DCIE is set to 1, */\
+ { 0x72a4, "DCTRIPT"}, /* Track adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
+ { 0x72f0, "DCTRIPHYSTE"}, /* Enable hysteresis on booster trip levels , */\
+ { 0x7304, "DCHOLD"}, /* Hold time / Hysteresis for DCDC booster, effective only when boost_intelligent is set to 1, */\
+ { 0x9000, "RST"}, /* Reset for Coolflux DSP , */\
+ { 0x9011, "DMEM"}, /* Target memory for CFMA using I2C interface , */\
+ { 0x9030, "AIF"}, /* Auto increment , */\
+ { 0x9040, "CFINT"}, /* Coolflux Interrupt - auto clear , */\
+ { 0x9050, "CFCGATE"}, /* Coolflux clock gating disabling control , */\
+ { 0x9080, "REQCMD"}, /* Firmware event request rpc command , */\
+ { 0x9090, "REQRST"}, /* Firmware event request reset restart , */\
+ { 0x90a0, "REQMIPS"}, /* Firmware event request short on mips , */\
+ { 0x90b0, "REQMUTED"}, /* Firmware event request mute sequence ready , */\
+ { 0x90c0, "REQVOL"}, /* Firmware event request volume ready , */\
+ { 0x90d0, "REQDMG"}, /* Firmware event request speaker damage detected , */\
+ { 0x90e0, "REQCAL"}, /* Firmware event request calibration completed , */\
+ { 0x90f0, "REQRSV"}, /* Firmware event request reserved , */\
+ { 0x910f, "MADD"}, /* CF memory address , */\
+ { 0x920f, "MEMA"}, /* Activate memory access , */\
+ { 0x9307, "ERR"}, /* CF error flags , */\
+ { 0x9380, "ACKCMD"}, /* Firmware event acknowledge rpc command , */\
+ { 0x9390, "ACKRST"}, /* Firmware event acknowledge reset restart , */\
+ { 0x93a0, "ACKMIPS"}, /* Firmware event acknowledge short on mips , */\
+ { 0x93b0, "ACKMUTED"}, /* Firmware event acknowledge mute sequence ready , */\
+ { 0x93c0, "ACKVOL"}, /* Firmware event acknowledge volume ready , */\
+ { 0x93d0, "ACKDMG"}, /* Firmware event acknowledge speaker damage detected, */\
+ { 0x93e0, "ACKCAL"}, /* Firmware event acknowledge calibration completed , */\
+ { 0x93f0, "ACKRSV"}, /* Firmware event acknowledge reserved , */\
+ { 0xa107, "MTPK"}, /* KEY2 to access KEY2 protected registers, customer key, */\
+ { 0xa200, "KEY1LOCKED"}, /* Indicates KEY1 is locked , */\
+ { 0xa210, "KEY2LOCKED"}, /* Indicates KEY2 is locked , */\
+ { 0xa350, "CMTPI"}, /* Start copying all the data from mtp to I2C mtp registers - auto clear, */\
+ { 0xa360, "CIMTP"}, /* Start copying data from I2C mtp registers to mtp - auto clear, */\
+ { 0xa50f, "MTPRDMSB"}, /* MSB word of MTP manual read data , */\
+ { 0xa60f, "MTPRDLSB"}, /* LSB word of MTP manual read data , */\
+ { 0xb108, "EXTTS"}, /* External temperature (C) , */\
+ { 0xb190, "TROS"}, /* Select temp Speaker calibration , */\
+ { 0xca05, "PLLINSELI"}, /* PLL INSELI - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
+ { 0xca64, "PLLINSELP"}, /* PLL INSELP - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
+ { 0xcab3, "PLLINSELR"}, /* PLL INSELR - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
+ { 0xcb09, "PLLNDEC"}, /* PLL NDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
+ { 0xcba0, "PLLMDECMSB"}, /* MSB of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
+ { 0xcbb0, "PLLBYPASS"}, /* PLL bypass control during functional mode , */\
+ { 0xcbc0, "PLLDIRECTI"}, /* PLL directi control in direct control mode only, use_direct_pll_ctrl set to 1, */\
+ { 0xcbd0, "PLLDIRECTO"}, /* PLL directo control in direct control mode only, use_direct_pll_ctrl set to 1, */\
+ { 0xcbe0, "PLLFRMSTBL"}, /* PLL FRM clock stable control in direct control mode only, use_direct_pll_ctrl set to 1, */\
+ { 0xcbf0, "PLLFRM"}, /* PLL free running mode control in functional mode , */\
+ { 0xcc0f, "PLLMDECLSB"}, /* Bits 15..0 of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
+ { 0xcd06, "PLLPDEC"}, /* PLL PDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
+ { 0xcd70, "DIRECTPLL"}, /* Enabled PLL direct control mode, overrules the PLL LUT with I2C register values, */\
+ { 0xcd80, "DIRECTCLK"}, /* Enabled CGU clock divider direct control mode , */\
+ { 0xcd90, "PLLLIM"}, /* PLL up limiter control in PLL direct bandwidth control mode, pll_bandsel set to 1, */\
+ { 0xe00f, "SWPROFIL"}, /* Software profile data , */\
+ { 0xe10f, "SWVSTEP"}, /* Software vstep information , */\
+ { 0xf000, "MTPOTC"}, /* Calibration schedule , */\
+ { 0xf010, "MTPEX"}, /* Calibration Ron executed , */\
+ { 0xf020, "DCMCCAPI"}, /* Calibration current limit DCDC , */\
+ { 0xf030, "DCMCCSB"}, /* Sign bit for delta calibration current limit DCDC , */\
+ { 0xf042, "USERDEF"}, /* Calibration delta current limit DCDC , */\
+ { 0xf078, "CUSTINFO"}, /* Reserved space for allowing customer to store speaker information, */\
+ { 0xf50f, "R25C"}, /* Ron resistance of speaker coil , */\
+ { 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+
+#define TFA9894N2_BITNAMETABLE static tfaBfName_t Tfa9894N2BitNames[] = {\
+ { 0x0, "powerdown"}, /* Powerdown control , */\
+ { 0x10, "reset"}, /* I2C Reset - Auto clear , */\
+ { 0x20, "enbl_coolflux"}, /* Enable CoolFlux DSP , */\
+ { 0x30, "enbl_amplifier"}, /* Enable Amplifier , */\
+ { 0x40, "enbl_boost"}, /* Enable DCDC Boost converter , */\
+ { 0x50, "coolflux_configured"}, /* Coolflux configured , */\
+ { 0x60, "sel_enbl_amplifier"}, /* CoolFlux control over amplifier , */\
+ { 0x71, "int_pad_io"}, /* Interrupt config , */\
+ { 0x90, "fs_pulse_sel"}, /* Audio sample reference , */\
+ { 0xa0, "bypass_ocp"}, /* Bypass OCP , */\
+ { 0xb0, "test_ocp"}, /* OCP testing control , */\
+ { 0xc0, "batsense_steepness"}, /* Vbat protection steepness , */\
+ { 0xd0, "bypass_hp"}, /* Bypass High Pass Filter , */\
+ { 0xe0, "enbl_dpsa"}, /* Enable DPSA , */\
+ { 0xf0, "sel_hysteresis"}, /* Select hysteresis for clock range detector , */\
+ { 0x101, "vamp_sel1"}, /* Amplifier input selection , */\
+ { 0x120, "src_set_configured"}, /* Device I2C settings configured , */\
+ { 0x130, "execute_cold_start"}, /* Execute cold start , */\
+ { 0x140, "man_enbl_brown_out"}, /* Reaction on BOD , */\
+ { 0x150, "bod_enbl"}, /* Enable BOD (only in direct control mode) , */\
+ { 0x160, "bod_hyst_enbl"}, /* Enable Hysteresis of BOD , */\
+ { 0x171, "bod_delay_set"}, /* BOD filter , */\
+ { 0x191, "bod_lvl_set"}, /* BOD threshold , */\
+ { 0x1b0, "disable_mute_time_out"}, /* Time out SB mute sequence , */\
+ { 0x1c0, "man_enbl_watchdog"}, /* Watchdog enable , */\
+ { 0x1d0, "disable_engage"}, /* Disable Engage , */\
+ { 0x1e0, "unprotect_faim"}, /* Control for FAIM protection , */\
+ { 0x1f0, "faim_enable_vbg"}, /* Overrule the enabling of VBG for faim erase/write access, */\
+ { 0x203, "audio_fs"}, /* Audio sample rate Fs , */\
+ { 0x240, "input_level"}, /* TDM output attenuation , */\
+ { 0x255, "cs_frac_delay"}, /* Current sense fractional delay , */\
+ { 0x2b1, "use_tdm_presence"}, /* Control for HW manager , */\
+ { 0x2d2, "ctrl_on2off_criterion"}, /* Amplifier on-off criteria for shutdown , */\
+ { 0x30f, "device_rev"}, /* Revision info , */\
+ { 0x401, "pll_clkin_sel"}, /* PLL external reference clock , */\
+ { 0x420, "pll_clkin_sel_osc"}, /* PLL internal reference clock , */\
+ { 0x432, "mclk_sel"}, /* Master Clock Selection , */\
+ { 0x460, "enbl_osc1m_auto_off"}, /* Internal OSC1M off at PWDN , */\
+ { 0x470, "disable_auto_sel_refclk"}, /* Automatic PLL reference clock selection for cold start, */\
+ { 0x480, "enbl_fs_sync"}, /* Enable FS synchronisation for clock divider , */\
+ { 0x490, "enbl_clkref_sync"}, /* Enable PLL reference clock synchronisation for clock divider, */\
+ { 0x4a0, "pll_slow_startup"}, /* PLL startup time configuration , */\
+ { 0x500, "disable_cgu_sync_cgate"}, /* Clock gating control for CGU synchronisation module, */\
+ { 0x510, "enbl_spkr_ss"}, /* Enable speaker sub-system , */\
+ { 0x520, "enbl_faim_ss"}, /* Enable FAIM sub-system , */\
+ { 0x530, "enbl_wdt_clk"}, /* Enable Coolflux watchdog clock , */\
+ { 0xe07, "ctrl_digtoana"}, /* Spare control from digital to analog , */\
+ { 0xf0f, "hidden_code"}, /* Hidden code to enable access to hidden register. (0x5A6B/23147 default for engineering), */\
+ { 0x1000, "flag_por"}, /* POR , */\
+ { 0x1010, "flag_pll_lock"}, /* PLL Lock , */\
+ { 0x1020, "flag_otpok"}, /* OTP alarm , */\
+ { 0x1030, "flag_ovpok"}, /* OVP alarm , */\
+ { 0x1040, "flag_uvpok"}, /* UVP alarm , */\
+ { 0x1050, "flag_ocp_alarm"}, /* OCP amplifier (sticky register, clear on read) , */\
+ { 0x1060, "flag_clocks_stable"}, /* Clocks stable , */\
+ { 0x1070, "flag_mtp_busy"}, /* MTP busy , */\
+ { 0x1080, "flag_lost_clk"}, /* Lost clock , */\
+ { 0x1090, "flag_cold_started"}, /* Cold Start , */\
+ { 0x10a0, "flag_watchdog_reset"}, /* Watchdog , */\
+ { 0x10b0, "flag_engage"}, /* Amplifier engage , */\
+ { 0x10c0, "flag_enbl_amp"}, /* Amplifier enable , */\
+ { 0x10d0, "flag_enbl_ref"}, /* References enable , */\
+ { 0x10e0, "flag_adc10_ready"}, /* Control ADC , */\
+ { 0x10f0, "flag_bod_vddd_nok"}, /* BOD Flag - VDD NOT OK , */\
+ { 0x1100, "flag_bst_bstcur"}, /* DCDC current limiting , */\
+ { 0x1110, "flag_bst_hiz"}, /* DCDC active (sticky register, clear on read) , */\
+ { 0x1120, "flag_bst_ocpok"}, /* DCDC OCP nmos (sticky register, clear on read) , */\
+ { 0x1130, "flag_bst_peakcur"}, /* Indicates current is max in DC-to-DC converter , */\
+ { 0x1140, "flag_bst_voutcomp"}, /* DCDC level 1x , */\
+ { 0x1150, "flag_bst_voutcomp86"}, /* DCDC level 1.14x , */\
+ { 0x1160, "flag_bst_voutcomp93"}, /* DCDC level 1.07x , */\
+ { 0x1170, "flag_cf_speakererror"}, /* Speaker status , */\
+ { 0x1180, "flag_clk_out_of_range"}, /* External clock status , */\
+ { 0x1190, "flag_man_alarm_state"}, /* Alarm state , */\
+ { 0x11a0, "flag_tdm_error"}, /* TDM error , */\
+ { 0x11b0, "flag_tdm_lut_error"}, /* TDM lookup table error , */\
+ { 0x11c0, "flag_lost_audio_clk"}, /* Lost Audio clock , */\
+ { 0x1200, "flag_ocpokap"}, /* OCPOK pmos A , */\
+ { 0x1210, "flag_ocpokan"}, /* OCPOK nmos A , */\
+ { 0x1220, "flag_ocpokbp"}, /* OCPOK pmos B , */\
+ { 0x1230, "flag_ocpokbn"}, /* OCPOK nmos B , */\
+ { 0x1240, "flag_clip"}, /* Amplifier clipping , */\
+ { 0x1250, "flag_man_start_mute_audio"}, /* Audio mute sequence , */\
+ { 0x1260, "flag_man_operating_state"}, /* Device in Operating state , */\
+ { 0x1270, "flag_lp_detect_mode1"}, /* Low power MODE1 detection , */\
+ { 0x1280, "flag_low_amplitude"}, /* Low amplitude detection , */\
+ { 0x1290, "flag_vddp_gt_vbat"}, /* VDDP greater than VBAT flag , */\
+ { 0x1302, "tdm_status"}, /* TDM Status bits , */\
+ { 0x1333, "man_state"}, /* Device Manager status , */\
+ { 0x1373, "amp_ctrl_state"}, /* Amplifier control status , */\
+ { 0x13b1, "status_bst_mode"}, /* DCDC mode status bits , */\
+ { 0x1509, "bat_adc"}, /* Battery voltage (V) , */\
+ { 0x1608, "temp_adc"}, /* IC Temperature (C) , */\
+ { 0x1709, "vddp_adc"}, /* IC VDDP voltage (1023*VDDP/13V) , */\
+ { 0x2000, "tdm_enable"}, /* Enable interface , */\
+ { 0x2010, "tdm_sink0_enable"}, /* Control audio tdm channel in sink0 , */\
+ { 0x2020, "tdm_sink1_enable"}, /* Control audio tdm channel in sink1 , */\
+ { 0x2030, "tdm_source0_enable"}, /* Source 0 enable , */\
+ { 0x2040, "tdm_source1_enable"}, /* Source 1 enable , */\
+ { 0x2050, "tdm_source2_enable"}, /* Source 2 enable , */\
+ { 0x2060, "tdm_source3_enable"}, /* Source 3 enable , */\
+ { 0x2070, "tdm_clk_inversion"}, /* Reception data to BCK clock , */\
+ { 0x2080, "tdm_fs_ws_polarity"}, /* FS polarity , */\
+ { 0x2090, "tdm_data_delay"}, /* Data delay to FS , */\
+ { 0x20a0, "tdm_data_adjustment"}, /* Data adjustment , */\
+ { 0x20b1, "tdm_audio_sample_compression"}, /* Received audio compression , */\
+ { 0x2103, "tdm_nbck"}, /* TDM NBCK - Bit clock to FS ratio , */\
+ { 0x2143, "tdm_fs_ws_length"}, /* FS length (master mode only) , */\
+ { 0x2183, "tdm_nb_of_slots"}, /* N-slots in Frame , */\
+ { 0x21c1, "tdm_txdata_format"}, /* Format unused bits , */\
+ { 0x21e1, "tdm_txdata_format_unused_slot"}, /* Format unused slots DATAO , */\
+ { 0x2204, "tdm_slot_length"}, /* N-bits in slot , */\
+ { 0x2254, "tdm_bits_remaining"}, /* N-bits remaining , */\
+ { 0x22a4, "tdm_sample_size"}, /* Sample size per slot , */\
+ { 0x2303, "tdm_sink0_slot"}, /* TDM slot for sink 0 , */\
+ { 0x2343, "tdm_sink1_slot"}, /* TDM slot for sink 1 , */\
+ { 0x2381, "tdm_source2_sel"}, /* TDM Source 2 data selection , */\
+ { 0x23a1, "tdm_source3_sel"}, /* TDM Source 3 data selection , */\
+ { 0x2403, "tdm_source0_slot"}, /* Slot position of source 0 data , */\
+ { 0x2443, "tdm_source1_slot"}, /* Slot position of source 1 data , */\
+ { 0x2483, "tdm_source2_slot"}, /* Slot position of source 2 data , */\
+ { 0x24c3, "tdm_source3_slot"}, /* Slot position of source 3 data , */\
+ { 0x4000, "int_out_flag_por"}, /* Status POR , */\
+ { 0x4010, "int_out_flag_bst_ocpok"}, /* Status DCDC OCP , */\
+ { 0x4020, "int_out_flag_otpok"}, /* Status OTP alarm , */\
+ { 0x4030, "int_out_flag_ocp_alarm"}, /* Status OCP alarm , */\
+ { 0x4040, "int_out_flag_uvpok"}, /* Status UVP alarm , */\
+ { 0x4050, "int_out_flag_man_alarm_state"}, /* Status manager alarm state , */\
+ { 0x4060, "int_out_flag_tdm_error"}, /* Status TDM error , */\
+ { 0x4070, "int_out_flag_lost_clk"}, /* Status lost clock , */\
+ { 0x4080, "int_out_flag_cfma_err"}, /* Status cfma error , */\
+ { 0x4090, "int_out_flag_cfma_ack"}, /* Status cfma ack , */\
+ { 0x40a0, "int_out_flag_cf_speakererror"}, /* Status coolflux speaker error , */\
+ { 0x40b0, "int_out_flag_cold_started"}, /* Status cold started , */\
+ { 0x40c0, "int_out_flag_watchdog_reset"}, /* Status watchdog reset , */\
+ { 0x40d0, "int_out_flag_bod_vddd_nok"}, /* Status brown out detect , */\
+ { 0x40e0, "int_out_flag_lp_detect_mode1"}, /* Status low power mode1 detect , */\
+ { 0x40f0, "int_out_flag_clk_out_of_range"}, /* Status clock out of range , */\
+ { 0x4400, "int_in_flag_por"}, /* Clear POR , */\
+ { 0x4410, "int_in_flag_bst_ocpok"}, /* Clear DCDC OCP , */\
+ { 0x4420, "int_in_flag_otpok"}, /* Clear OTP alarm , */\
+ { 0x4430, "int_in_flag_ocp_alarm"}, /* Clear OCP alarm , */\
+ { 0x4440, "int_in_flag_uvpok"}, /* Clear UVP alarm , */\
+ { 0x4450, "int_in_flag_man_alarm_state"}, /* Clear manager alarm state , */\
+ { 0x4460, "int_in_flag_tdm_error"}, /* Clear TDM error , */\
+ { 0x4470, "int_in_flag_lost_clk"}, /* Clear lost clk , */\
+ { 0x4480, "int_in_flag_cfma_err"}, /* Clear cfma err , */\
+ { 0x4490, "int_in_flag_cfma_ack"}, /* Clear cfma ack , */\
+ { 0x44a0, "int_in_flag_cf_speakererror"}, /* Clear coolflux speaker error , */\
+ { 0x44b0, "int_in_flag_cold_started"}, /* Clear cold started , */\
+ { 0x44c0, "int_in_flag_watchdog_reset"}, /* Clear watchdog reset , */\
+ { 0x44d0, "int_in_flag_bod_vddd_nok"}, /* Clear brown out detect , */\
+ { 0x44e0, "int_in_flag_lp_detect_mode1"}, /* Clear low power mode1 detect , */\
+ { 0x44f0, "int_in_flag_clk_out_of_range"}, /* Clear clock out of range , */\
+ { 0x4800, "int_enable_flag_por"}, /* Enable POR , */\
+ { 0x4810, "int_enable_flag_bst_ocpok"}, /* Enable DCDC OCP , */\
+ { 0x4820, "int_enable_flag_otpok"}, /* Enable OTP alarm , */\
+ { 0x4830, "int_enable_flag_ocp_alarm"}, /* Enable OCP alarm , */\
+ { 0x4840, "int_enable_flag_uvpok"}, /* Enable UVP alarm , */\
+ { 0x4850, "int_enable_flag_man_alarm_state"}, /* Enable Manager Alarm state , */\
+ { 0x4860, "int_enable_flag_tdm_error"}, /* Enable TDM error , */\
+ { 0x4870, "int_enable_flag_lost_clk"}, /* Enable lost clk , */\
+ { 0x4880, "int_enable_flag_cfma_err"}, /* Enable cfma err , */\
+ { 0x4890, "int_enable_flag_cfma_ack"}, /* Enable cfma ack , */\
+ { 0x48a0, "int_enable_flag_cf_speakererror"}, /* Enable coolflux speaker error , */\
+ { 0x48b0, "int_enable_flag_cold_started"}, /* Enable cold started , */\
+ { 0x48c0, "int_enable_flag_watchdog_reset"}, /* Enable watchdog reset , */\
+ { 0x48d0, "int_enable_flag_bod_vddd_nok"}, /* Enable brown out detect , */\
+ { 0x48e0, "int_enable_flag_lp_detect_mode1"}, /* Enable low power mode1 detect , */\
+ { 0x48f0, "int_enable_flag_clk_out_of_range"}, /* Enable clock out of range , */\
+ { 0x4c00, "int_polarity_flag_por"}, /* Polarity POR , */\
+ { 0x4c10, "int_polarity_flag_bst_ocpok"}, /* Polarity DCDC OCP , */\
+ { 0x4c20, "int_polarity_flag_otpok"}, /* Polarity OTP alarm , */\
+ { 0x4c30, "int_polarity_flag_ocp_alarm"}, /* Polarity ocp alarm , */\
+ { 0x4c40, "int_polarity_flag_uvpok"}, /* Polarity UVP alarm , */\
+ { 0x4c50, "int_polarity_flag_man_alarm_state"}, /* Polarity manager alarm state , */\
+ { 0x4c60, "int_polarity_flag_tdm_error"}, /* Polarity TDM error , */\
+ { 0x4c70, "int_polarity_flag_lost_clk"}, /* Polarity lost clk , */\
+ { 0x4c80, "int_polarity_flag_cfma_err"}, /* Polarity cfma err , */\
+ { 0x4c90, "int_polarity_flag_cfma_ack"}, /* Polarity cfma ack , */\
+ { 0x4ca0, "int_polarity_flag_cf_speakererror"}, /* Polarity coolflux speaker error , */\
+ { 0x4cb0, "int_polarity_flag_cold_started"}, /* Polarity cold started , */\
+ { 0x4cc0, "int_polarity_flag_watchdog_reset"}, /* Polarity watchdog reset , */\
+ { 0x4cd0, "int_polarity_flag_bod_vddd_nok"}, /* Polarity brown out detect , */\
+ { 0x4ce0, "int_polarity_flag_lp_detect_mode1"}, /* Polarity low power mode1 detect , */\
+ { 0x4cf0, "int_polarity_flag_clk_out_of_range"}, /* Polarity clock out of range , */\
+ { 0x5001, "vbat_prot_attack_time"}, /* Battery safeguard attack time , */\
+ { 0x5023, "vbat_prot_thlevel"}, /* Battery safeguard threshold voltage level , */\
+ { 0x5061, "vbat_prot_max_reduct"}, /* Battery safeguard maximum reduction , */\
+ { 0x5082, "vbat_prot_release_time"}, /* Battery safeguard release time , */\
+ { 0x50b1, "vbat_prot_hysterese"}, /* Battery Safeguard hysteresis , */\
+ { 0x50d0, "rst_min_vbat"}, /* Reset clipper - auto clear , */\
+ { 0x50e0, "sel_vbat"}, /* Battery voltage read out , */\
+ { 0x50f0, "bypass_clipper"}, /* Bypass HW clipper , */\
+ { 0x5130, "cf_mute"}, /* Coolflux firmware soft mute control , */\
+ { 0x5187, "cf_volume"}, /* CF firmware volume control , */\
+ { 0x5202, "ctrl_cc"}, /* Clip control setting , */\
+ { 0x5230, "ctrl_slopectrl"}, /* Enables slope control , */\
+ { 0x5240, "ctrl_slope"}, /* Slope speed setting (binary coded) , */\
+ { 0x5250, "bypass_dly_line"}, /* Bypass the interpolator delay line , */\
+ { 0x5287, "gain"}, /* Amplifier gain , */\
+ { 0x5301, "dpsa_level"}, /* DPSA threshold levels , */\
+ { 0x5321, "dpsa_release"}, /* DPSA Release time , */\
+ { 0x5340, "clipfast"}, /* Clock selection for HW clipper for battery safeguard, */\
+ { 0x5350, "bypass_lp"}, /* Bypass the low power filter inside temperature sensor, */\
+ { 0x5360, "first_order_mode"}, /* Overrule to 1st order mode of control stage when clipping, */\
+ { 0x5370, "icomp_engage"}, /* Engage of icomp , */\
+ { 0x5380, "ctrl_kickback"}, /* Prevent double pulses of output stage , */\
+ { 0x5390, "icomp_engage_overrule"}, /* To overrule the functional icomp_engage signal during validation, */\
+ { 0x53a3, "ctrl_dem"}, /* Enable DEM icomp and DEM one bit dac , */\
+ { 0x5400, "bypass_ctrlloop"}, /* Switch amplifier into open loop configuration , */\
+ { 0x5413, "ctrl_dem_mismatch"}, /* Enable DEM icomp mismatch for testing , */\
+ { 0x5452, "dpsa_drive"}, /* Drive setting (binary coded) , */\
+ { 0x550a, "enbl_amp"}, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually, */\
+ { 0x55b0, "enbl_engage"}, /* Enables/engage power stage and control loop , */\
+ { 0x55c0, "enbl_engage_pst"}, /* Enables/engage power stage and control loop , */\
+ { 0x5600, "pwm_shape"}, /* PWM shape , */\
+ { 0x5614, "pwm_delay"}, /* PWM delay bits to set the delay, clockd is 1/(k*2048*fs), */\
+ { 0x5660, "reclock_pwm"}, /* Reclock the PWM signal inside analog , */\
+ { 0x5670, "reclock_voltsense"}, /* Reclock the voltage sense PWM signal , */\
+ { 0x5680, "enbl_pwm_phase_shift"}, /* Control for PWM phase shift , */\
+ { 0x5690, "sel_pwm_delay_src"}, /* Control for selection for PWM delay line source , */\
+ { 0x56a1, "enbl_odd_up_even_down"}, /* Control for PWM reference sawtooth generartion , */\
+ { 0x5703, "ctrl_att_dcdc"}, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */\
+ { 0x5743, "ctrl_att_spkr"}, /* Total gain depending on INPLEV setting (channel 0), */\
+ { 0x5781, "vamp_sel2"}, /* VAMP_OUT2 input selection , */\
+ { 0x5805, "zero_lvl"}, /* Low noise gain switch zero trigger level , */\
+ { 0x5861, "ctrl_fb_resistor"}, /* Select amplifier feedback resistor connection , */\
+ { 0x5881, "lownoisegain_mode"}, /* Low noise gain mode control , */\
+ { 0x5905, "threshold_lvl"}, /* Low noise gain switch trigger level , */\
+ { 0x5965, "hold_time"}, /* Low noise mode hold time before entering into low noise mode, */\
+ { 0x5a05, "lpm1_cal_offset"}, /* Low power mode1 detector ctrl cal_offset from gain module , */\
+ { 0x5a65, "lpm1_zero_lvl"}, /* Low power mode1 zero crossing detection level , */\
+ { 0x5ac1, "lpm1_mode"}, /* Low power mode control , */\
+ { 0x5b05, "lpm1_threshold_lvl"}, /* Low power mode1 amplitude trigger level , */\
+ { 0x5b65, "lpm1_hold_time"}, /* Low power mode hold time before entering into low power mode, */\
+ { 0x5bc0, "disable_low_power_mode"}, /* Low power mode1 detector control , */\
+ { 0x5c00, "enbl_minion"}, /* Enables minion (small) power stage , */\
+ { 0x5c13, "vth_vddpvbat"}, /* Select vddp-vbat threshold signal , */\
+ { 0x5c50, "lpen_vddpvbat"}, /* Select vddp-vbat filtred vs unfiltered compare , */\
+ { 0x5c61, "ctrl_rfb"}, /* Feedback resistor selection - I2C direct mode , */\
+ { 0x5d02, "tdm_source_mapping"}, /* TDM source mapping , */\
+ { 0x5d31, "tdm_sourcea_frame_sel"}, /* Sensed value A , */\
+ { 0x5d51, "tdm_sourceb_frame_sel"}, /* Sensed value B , */\
+ { 0x5d71, "tdm_source0_clip_sel"}, /* Clip information (analog /digital) for source0 , */\
+ { 0x5d91, "tdm_source1_clip_sel"}, /* Clip information (analog /digital) for source1 , */\
+ { 0x5e02, "rst_min_vbat_delay"}, /* Delay for reseting the min_vbat value inside HW Clipper (number of Fs pulses), */\
+ { 0x5e30, "rst_min_vbat_sel"}, /* Control for selecting reset signal for min_bat , */\
+ { 0x5f00, "hard_mute"}, /* Hard mute - PWM , */\
+ { 0x5f12, "ns_hp2ln_criterion"}, /* 0..7 zeroes at ns as threshold to swap from high_power to low_noise, */\
+ { 0x5f42, "ns_ln2hp_criterion"}, /* 0..7 zeroes at ns as threshold to swap from low_noise to high_power, */\
+ { 0x5f78, "spare_out"}, /* Spare out register , */\
+ { 0x600f, "spare_in"}, /* Spare IN , */\
+ { 0x6102, "cursense_comp_delay"}, /* Delay to allign compensation signal with current sense signal, */\
+ { 0x6130, "cursense_comp_sign"}, /* Polarity of compensation for current sense , */\
+ { 0x6140, "enbl_cursense_comp"}, /* Enable current sense compensation , */\
+ { 0x6152, "pwms_clip_lvl"}, /* Set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
+ { 0x7005, "frst_boost_voltage"}, /* First Boost Voltage Level , */\
+ { 0x7065, "scnd_boost_voltage"}, /* Second Boost Voltage Level , */\
+ { 0x70c3, "boost_cur"}, /* Max Coil Current , */\
+ { 0x7101, "bst_slpcmplvl"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
+ { 0x7120, "boost_intel"}, /* Adaptive boost mode , */\
+ { 0x7130, "boost_speed"}, /* Soft ramp up/down , */\
+ { 0x7140, "dcdcoff_mode"}, /* DCDC on/off , */\
+ { 0x7150, "dcdc_pwmonly"}, /* DCDC PWM only mode , */\
+ { 0x7160, "boost_track"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
+ { 0x7170, "sel_dcdc_envelope_8fs"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
+ { 0x7180, "ignore_flag_voutcomp86"}, /* Determines the maximum PWM frequency be the most efficient in relation to the Booster inductor value, */\
+ { 0x7195, "overshoot_correction_lvl"}, /* Threshold level to activate active overshoot control, */\
+ { 0x7204, "boost_trip_lvl_1st"}, /* 1st adaptive boost trip levels, effective only when DCIE is set to 1, */\
+ { 0x7254, "boost_trip_lvl_2nd"}, /* 2nd adaptive boost trip levels, effective only when DCIE is set to 1, */\
+ { 0x72a4, "boost_trip_lvl_track"}, /* Track adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
+ { 0x72f0, "enbl_trip_hyst"}, /* Enable hysteresis on booster trip levels , */\
+ { 0x7304, "boost_hold_time"}, /* Hold time / Hysteresis for DCDC booster, effective only when boost_intelligent is set to 1, */\
+ { 0x7350, "dcdc_pfm20khz_limit"}, /* DCDC in PFM mode pwm mode is activated each 50us to force a pwm pulse, */\
+ { 0x7361, "dcdc_ctrl_maxzercnt"}, /* Number of zero current flags to count before going to pfm mode, */\
+ { 0x7386, "dcdc_vbat_delta_detect"}, /* Threshold before booster is reacting on a delta Vbat (in PFM mode) by temporarily switching to PWM mode, */\
+ { 0x73f0, "dcdc_ignore_vbat"}, /* Ignore an increase on Vbat , */\
+ { 0x7404, "bst_drive"}, /* Binary coded drive setting for boost converter power stage, */\
+ { 0x7451, "bst_scalecur"}, /* For testing direct control scale current , */\
+ { 0x7474, "bst_slopecur"}, /* For testing direct control slope current , */\
+ { 0x74c1, "bst_slope"}, /* Boost slope speed , */\
+ { 0x74e0, "bst_bypass_bstcur"}, /* Bypass control for boost current settings , */\
+ { 0x74f0, "bst_bypass_bstfoldback"}, /* Bypass control for boost foldback , */\
+ { 0x7500, "enbl_bst_engage"}, /* Enable power stage dcdc controller , */\
+ { 0x7510, "enbl_bst_hizcom"}, /* Enable hiz comparator , */\
+ { 0x7520, "enbl_bst_peakcur"}, /* Enable peak current , */\
+ { 0x7530, "enbl_bst_power"}, /* Enable line of the powerstage , */\
+ { 0x7540, "enbl_bst_slopecur"}, /* Enable bit of max-current dac , */\
+ { 0x7550, "enbl_bst_voutcomp"}, /* Enable vout comparators , */\
+ { 0x7560, "enbl_bst_voutcomp86"}, /* Enable vout-86 comparators , */\
+ { 0x7570, "enbl_bst_voutcomp93"}, /* Enable vout-93 comparators , */\
+ { 0x7580, "enbl_bst_windac"}, /* Enable window dac , */\
+ { 0x7595, "bst_windac"}, /* For testing direct control windac , */\
+ { 0x7600, "boost_alg"}, /* Control for boost adaptive loop gain , */\
+ { 0x7611, "boost_loopgain"}, /* DCDC boost loopgain setting , */\
+ { 0x7631, "bst_freq"}, /* DCDC boost frequency control , */\
+ { 0x7650, "enbl_bst_peak2avg"}, /* Enable boost peak2avg functionality , */\
+ { 0x7660, "bst_use_new_zercur_detect"}, /* Enable new zero current detection for boost control, */\
+ { 0x8001, "sel_clk_cs"}, /* Current sense clock duty cycle control , */\
+ { 0x8021, "micadc_speed"}, /* Current sense clock for MiCADC selection - 32/44.1/48 KHz Fs band only, */\
+ { 0x8040, "cs_gain_control"}, /* Current sense gain control , */\
+ { 0x8050, "cs_bypass_gc"}, /* Bypasses the CS gain correction , */\
+ { 0x8060, "invertpwm"}, /* Current sense common mode feedback pwm invert control, */\
+ { 0x8087, "cs_gain"}, /* Current sense gain , */\
+ { 0x8105, "cs_ktemp"}, /* Current sense temperature compensation trimming (1 - VALUE*TEMP) * signal, */\
+ { 0x8164, "cs_ktemp2"}, /* Second order temperature compensation coefficient , */\
+ { 0x81b0, "enbl_cs_adc"}, /* Enable current sense ADC , */\
+ { 0x81c0, "enbl_cs_inn1"}, /* Enable connection of current sense negative1 , */\
+ { 0x81d0, "enbl_cs_inn2"}, /* Enable connection of current sense negative2 , */\
+ { 0x81e0, "enbl_cs_inp1"}, /* Enable connection of current sense positive1 , */\
+ { 0x81f0, "enbl_cs_inp2"}, /* Enable connection of current sense positive2 , */\
+ { 0x8200, "enbl_cs_ldo"}, /* Enable current sense LDO , */\
+ { 0x8210, "enbl_cs_vbatldo"}, /* Enable of current sense LDO , */\
+ { 0x8220, "cs_adc_bsoinv"}, /* Bitstream inversion for current sense ADC , */\
+ { 0x8231, "cs_adc_hifreq"}, /* Frequency mode current sense ADC , */\
+ { 0x8250, "cs_adc_nortz"}, /* Return to zero for current sense ADC , */\
+ { 0x8263, "cs_adc_offset"}, /* Micadc ADC offset setting , */\
+ { 0x82a0, "cs_adc_slowdel"}, /* Select delay for current sense ADC (internal decision circuitry), */\
+ { 0x82b4, "cs_adc_gain"}, /* Gain setting for current sense ADC (two's complement), */\
+ { 0x8300, "cs_resonator_enable"}, /* Enable for resonator to improve SRN , */\
+ { 0x8310, "cs_classd_tran_skip"}, /* Skip current sense connection during a classD amplifier transition, */\
+ { 0x8320, "cs_inn_short"}, /* Short current sense negative to common mode , */\
+ { 0x8330, "cs_inp_short"}, /* Short current sense positive to common mode , */\
+ { 0x8340, "cs_ldo_bypass"}, /* Bypass current sense LDO , */\
+ { 0x8350, "cs_ldo_pulldown"}, /* Pull down current sense LDO, only valid if enbl_cs_ldo is high, */\
+ { 0x8364, "cs_ldo_voset"}, /* Current sense LDO voltage level setting (two's complement), */\
+ { 0x8800, "ctrl_vs_igen_supply"}, /* Control for selecting supply for VS current generator, */\
+ { 0x8810, "ctrl_vs_force_div2"}, /* Select input resistive divider gain , */\
+ { 0x8820, "enbl_dc_filter"}, /* Control for enabling the DC blocking filter for voltage and current sense, */\
+ { 0x8901, "volsense_pwm_sel"}, /* Voltage sense source selection control , */\
+ { 0x8920, "vs_gain_control"}, /* Voltage sense gain control , */\
+ { 0x8930, "vs_bypass_gc"}, /* Bypasses the VS gain correction , */\
+ { 0x8940, "vs_adc_bsoinv"}, /* Bitstream inversion for voltage sense ADC , */\
+ { 0x8950, "vs_adc_nortz"}, /* Return to zero for voltage sense ADC , */\
+ { 0x8960, "vs_adc_slowdel"}, /* Select delay for voltage sense ADC (internal decision circuitry), */\
+ { 0x8970, "vs_classd_tran_skip"}, /* Skip voltage sense connection during a classD amplifier transition, */\
+ { 0x8987, "vs_gain"}, /* Voltage sense gain , */\
+ { 0x8a00, "vs_inn_short"}, /* Short voltage sense negative to common mode , */\
+ { 0x8a10, "vs_inp_short"}, /* Short voltage sense positive to common mode , */\
+ { 0x8a20, "vs_ldo_bypass"}, /* Bypass voltage sense LDO , */\
+ { 0x8a30, "vs_ldo_pulldown"}, /* Pull down voltage sense LDO, only valid if enbl_cs_ldo is high, */\
+ { 0x8a44, "vs_ldo_voset"}, /* Voltage sense LDO voltage level setting (two's complement), */\
+ { 0x8a90, "enbl_vs_adc"}, /* Enable voltage sense ADC , */\
+ { 0x8aa0, "enbl_vs_inn1"}, /* Enable connection of voltage sense negative1 , */\
+ { 0x8ab0, "enbl_vs_inn2"}, /* Enable connection of voltage sense negative2 , */\
+ { 0x8ac0, "enbl_vs_inp1"}, /* Enable connection of voltage sense positive1 , */\
+ { 0x8ad0, "enbl_vs_inp2"}, /* Enable connection of voltage sense positive2 , */\
+ { 0x8ae0, "enbl_vs_ldo"}, /* Enable voltage sense LDO , */\
+ { 0x8af0, "enbl_vs_vbatldo"}, /* Enable of voltage sense LDO , */\
+ { 0x9000, "cf_rst_dsp"}, /* Reset for Coolflux DSP , */\
+ { 0x9011, "cf_dmem"}, /* Target memory for CFMA using I2C interface , */\
+ { 0x9030, "cf_aif"}, /* Auto increment , */\
+ { 0x9040, "cf_int"}, /* Coolflux Interrupt - auto clear , */\
+ { 0x9050, "cf_cgate_off"}, /* Coolflux clock gating disabling control , */\
+ { 0x9080, "cf_req_cmd"}, /* Firmware event request rpc command , */\
+ { 0x9090, "cf_req_reset"}, /* Firmware event request reset restart , */\
+ { 0x90a0, "cf_req_mips"}, /* Firmware event request short on mips , */\
+ { 0x90b0, "cf_req_mute_ready"}, /* Firmware event request mute sequence ready , */\
+ { 0x90c0, "cf_req_volume_ready"}, /* Firmware event request volume ready , */\
+ { 0x90d0, "cf_req_damage"}, /* Firmware event request speaker damage detected , */\
+ { 0x90e0, "cf_req_calibrate_ready"}, /* Firmware event request calibration completed , */\
+ { 0x90f0, "cf_req_reserved"}, /* Firmware event request reserved , */\
+ { 0x910f, "cf_madd"}, /* CF memory address , */\
+ { 0x920f, "cf_mema"}, /* Activate memory access , */\
+ { 0x9307, "cf_err"}, /* CF error flags , */\
+ { 0x9380, "cf_ack_cmd"}, /* Firmware event acknowledge rpc command , */\
+ { 0x9390, "cf_ack_reset"}, /* Firmware event acknowledge reset restart , */\
+ { 0x93a0, "cf_ack_mips"}, /* Firmware event acknowledge short on mips , */\
+ { 0x93b0, "cf_ack_mute_ready"}, /* Firmware event acknowledge mute sequence ready , */\
+ { 0x93c0, "cf_ack_volume_ready"}, /* Firmware event acknowledge volume ready , */\
+ { 0x93d0, "cf_ack_damage"}, /* Firmware event acknowledge speaker damage detected, */\
+ { 0x93e0, "cf_ack_calibrate_ready"}, /* Firmware event acknowledge calibration completed , */\
+ { 0x93f0, "cf_ack_reserved"}, /* Firmware event acknowledge reserved , */\
+ { 0xa007, "mtpkey1"}, /* KEY1 To access KEY1 protected registers 0x5A/90d (default for engineering), */\
+ { 0xa107, "mtpkey2"}, /* KEY2 to access KEY2 protected registers, customer key, */\
+ { 0xa200, "key01_locked"}, /* Indicates KEY1 is locked , */\
+ { 0xa210, "key02_locked"}, /* Indicates KEY2 is locked , */\
+ { 0xa302, "mtp_man_address_in"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
+ { 0xa330, "man_copy_mtp_to_iic"}, /* Start copying single word from MTP to I2C mtp register - auto clear, */\
+ { 0xa340, "man_copy_iic_to_mtp"}, /* Start copying single word from I2C mtp register to mtp - auto clear, */\
+ { 0xa350, "auto_copy_mtp_to_iic"}, /* Start copying all the data from mtp to I2C mtp registers - auto clear, */\
+ { 0xa360, "auto_copy_iic_to_mtp"}, /* Start copying data from I2C mtp registers to mtp - auto clear, */\
+ { 0xa400, "faim_set_clkws"}, /* Sets the FaIM controller clock wait state register, */\
+ { 0xa410, "faim_sel_evenrows"}, /* All even rows of the FaIM are selected, active high, */\
+ { 0xa420, "faim_sel_oddrows"}, /* All odd rows of the FaIM are selected, all rows in combination with sel_evenrows, */\
+ { 0xa430, "faim_program_only"}, /* Skip the erase access at wr_faim command (write-program-marginread), */\
+ { 0xa440, "faim_erase_only"}, /* Skip the program access at wr_faim command (write-erase-marginread), */\
+ { 0xa50f, "mtp_man_data_out_msb"}, /* MSB word of MTP manual read data , */\
+ { 0xa60f, "mtp_man_data_out_lsb"}, /* LSB word of MTP manual read data , */\
+ { 0xa70f, "mtp_man_data_in_msb"}, /* MSB word of write data for MTP manual write , */\
+ { 0xa80f, "mtp_man_data_in_lsb"}, /* LSB word of write data for MTP manual write , */\
+ { 0xb000, "bypass_ocpcounter"}, /* Bypass OCP Counter , */\
+ { 0xb010, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
+ { 0xb020, "bypass_ovp"}, /* Bypass OVP , */\
+ { 0xb030, "bypass_uvp"}, /* Bypass UVP , */\
+ { 0xb040, "bypass_otp"}, /* Bypass OTP , */\
+ { 0xb050, "bypass_lost_clk"}, /* Bypass lost clock detector , */\
+ { 0xb060, "ctrl_vpalarm"}, /* vpalarm (uvp ovp handling) , */\
+ { 0xb070, "disable_main_ctrl_change_prot"}, /* Disable main control change protection , */\
+ { 0xb087, "ocp_threshold"}, /* OCP threshold level , */\
+ { 0xb108, "ext_temp"}, /* External temperature (C) , */\
+ { 0xb190, "ext_temp_sel"}, /* Select temp Speaker calibration , */\
+ { 0xc000, "use_direct_ctrls"}, /* Direct control to overrule several functions for testing, */\
+ { 0xc010, "rst_datapath"}, /* Direct control for datapath reset , */\
+ { 0xc020, "rst_cgu"}, /* Direct control for cgu reset , */\
+ { 0xc038, "enbl_ref"}, /* Switch on the analog references, each part of the references can be switched on/off individually, */\
+ { 0xc0c0, "use_direct_vs_ctrls"}, /* Voltage sense direct control to overrule several functions for testing, */\
+ { 0xc0d0, "enbl_ringo"}, /* Enable the ring oscillator for test purpose , */\
+ { 0xc0e0, "enbl_pll"}, /* Enables PLL in I2C direct control mode only , */\
+ { 0xc0f0, "enbl_osc"}, /* Enables OSC in I2C direct control mode only , */\
+ { 0xc100, "enbl_tsense"}, /* Temperature sensor enable control - I2C direct mode, */\
+ { 0xc110, "tsense_hibias"}, /* Bit to set the biasing in temp sensor to high , */\
+ { 0xc120, "enbl_flag_vbg"}, /* Enable flagging of bandgap out of control , */\
+ { 0xc20f, "abist_offset"}, /* Offset control for ABIST testing (two's complement), */\
+ { 0xc300, "bypasslatch"}, /* Bypass latch , */\
+ { 0xc311, "sourcea"}, /* Set OUTA to , */\
+ { 0xc331, "sourceb"}, /* Set OUTB to , */\
+ { 0xc350, "inverta"}, /* Invert pwma test signal , */\
+ { 0xc360, "invertb"}, /* Invert pwmb test signal , */\
+ { 0xc374, "pulselength"}, /* Pulse length setting test input for amplifier (clock d - k*2048*fs), */\
+ { 0xc3d0, "test_abistfft_enbl"}, /* Enable ABIST with FFT on Coolflux DSP , */\
+ { 0xc400, "bst_bypasslatch"}, /* Bypass latch in boost converter , */\
+ { 0xc411, "bst_source"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
+ { 0xc430, "bst_invertb"}, /* Invert pwmbst test signal , */\
+ { 0xc444, "bst_pulselength"}, /* Pulse length setting test input for boost converter , */\
+ { 0xc490, "test_bst_ctrlsthv"}, /* Test mode for boost control stage , */\
+ { 0xc4a0, "test_bst_iddq"}, /* IDDQ testing in power stage of boost converter , */\
+ { 0xc4b0, "test_bst_rdson"}, /* RDSON testing - boost power stage , */\
+ { 0xc4c0, "test_bst_cvi"}, /* CVI testing - boost power stage , */\
+ { 0xc4d0, "test_bst_ocp"}, /* Boost Converter Over Current Protection , */\
+ { 0xc4e0, "test_bst_sense"}, /* Test option for the sense NMOS in booster for current mode control., */\
+ { 0xc500, "test_cvi"}, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */\
+ { 0xc510, "test_discrete"}, /* Test function noise measurement , */\
+ { 0xc520, "test_iddq"}, /* Set the power stages in iddq mode for gate stress., */\
+ { 0xc530, "test_rdson"}, /* Analog BIST, switch to enable Rdson measurement , */\
+ { 0xc540, "test_sdelta"}, /* Analog BIST, noise test , */\
+ { 0xc550, "test_enbl_cs"}, /* Enable for digimux mode of current sense , */\
+ { 0xc560, "test_enbl_vs"}, /* Enable for digimux mode of voltage sense , */\
+ { 0xc570, "enbl_pwm_dcc"}, /* Enables direct control of pwm duty cycle for DCDC power stage, */\
+ { 0xc583, "pwm_dcc_cnt"}, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */\
+ { 0xc5c0, "enbl_ldo_stress"}, /* Enable stress of internal supply voltages powerstages, */\
+ { 0xc607, "digimuxa_sel"}, /* DigimuxA input selection control routed to DATAO , */\
+ { 0xc687, "digimuxb_sel"}, /* DigimuxB input selection control routed to INT , */\
+ { 0xc707, "digimuxc_sel"}, /* DigimuxC input selection control routed to ADS1 , */\
+ { 0xc800, "enbl_anamux1"}, /* Enable anamux1 , */\
+ { 0xc810, "enbl_anamux2"}, /* Enable anamux2 , */\
+ { 0xc820, "enbl_anamux3"}, /* Enable anamux3 , */\
+ { 0xc830, "enbl_anamux4"}, /* Enable anamux4 , */\
+ { 0xc844, "anamux1"}, /* Anamux selection control - anamux on TEST1 , */\
+ { 0xc894, "anamux2"}, /* Anamux selection control - anamux on TEST2 , */\
+ { 0xc903, "anamux3"}, /* Anamux selection control - anamux on TEST3 , */\
+ { 0xc943, "anamux4"}, /* Anamux selection control - anamux on TEST4 , */\
+ { 0xca05, "pll_inseli"}, /* PLL INSELI - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
+ { 0xca64, "pll_inselp"}, /* PLL INSELP - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
+ { 0xcab3, "pll_inselr"}, /* PLL INSELR - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
+ { 0xcaf0, "pll_bandsel"}, /* PLL bandwidth selection control, USE WITH CAUTION , */\
+ { 0xcb09, "pll_ndec"}, /* PLL NDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
+ { 0xcba0, "pll_mdec_msb"}, /* MSB of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
+ { 0xcbb0, "pll_bypass"}, /* PLL bypass control during functional mode , */\
+ { 0xcbc0, "pll_directi"}, /* PLL directi control in direct control mode only, use_direct_pll_ctrl set to 1, */\
+ { 0xcbd0, "pll_directo"}, /* PLL directo control in direct control mode only, use_direct_pll_ctrl set to 1, */\
+ { 0xcbe0, "pll_frm_clockstable"}, /* PLL FRM clock stable control in direct control mode only, use_direct_pll_ctrl set to 1, */\
+ { 0xcbf0, "pll_frm"}, /* PLL free running mode control in functional mode , */\
+ { 0xcc0f, "pll_mdec_lsb"}, /* Bits 15..0 of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
+ { 0xcd06, "pll_pdec"}, /* PLL PDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
+ { 0xcd70, "use_direct_pll_ctrl"}, /* Enabled PLL direct control mode, overrules the PLL LUT with I2C register values, */\
+ { 0xcd80, "use_direct_clk_ctrl"}, /* Enabled CGU clock divider direct control mode , */\
+ { 0xcd90, "pll_limup_off"}, /* PLL up limiter control in PLL direct bandwidth control mode, pll_bandsel set to 1, */\
+ { 0xce0f, "tsig_freq_lsb"}, /* Internal sinus test generator frequency control , */\
+ { 0xcf02, "tsig_freq_msb"}, /* Select internal sinus test generator, frequency control msb bits, */\
+ { 0xcf33, "tsig_gain"}, /* Test signal gain , */\
+ { 0xd000, "adc10_reset"}, /* Reset for ADC10 - I2C direct control mode , */\
+ { 0xd011, "adc10_test"}, /* Test mode selection signal for ADC10 - I2C direct control mode, */\
+ { 0xd032, "adc10_sel"}, /* Select the input to convert for ADC10 - I2C direct control mode, */\
+ { 0xd064, "adc10_prog_sample"}, /* ADC10 program sample setting - I2C direct control mode, */\
+ { 0xd0b0, "adc10_enbl"}, /* Enable ADC10 - I2C direct control mode , */\
+ { 0xd0c0, "bypass_lp_vbat"}, /* Bypass control for Low pass filter in batt sensor , */\
+ { 0xd109, "data_adc10_tempbat"}, /* ADC 10 data output data for testing , */\
+ { 0xd201, "clkdiv_audio_sel"}, /* Audio clock divider selection in direct clock control mode, */\
+ { 0xd301, "int_ehs"}, /* Speed/load setting for INT IO cell, clk or data mode range (see SLIMMF IO datasheet), */\
+ { 0xd321, "datao_ehs"}, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO datasheet), */\
+ { 0xd340, "hs_mode"}, /* I2C high speed mode control , */\
+ { 0xd407, "ctrl_digtoana_hidden"}, /* Spare digital to analog control bits - Hidden , */\
+ { 0xd480, "enbl_clk_out_of_range"}, /* Clock out of range , */\
+ { 0xd491, "sel_wdt_clk"}, /* Watch dog clock divider settings , */\
+ { 0xd4b0, "inject_tsig"}, /* Control bit to switch to internal sinus test generator, */\
+ { 0xd500, "source_in_testmode"}, /* TDM source in test mode (return only current and voltage sense), */\
+ { 0xd510, "gainatt_feedback"}, /* Gainatt feedback to tdm , */\
+ { 0xd522, "test_parametric_io"}, /* Test IO parametric , */\
+ { 0xd550, "ctrl_bst_clk_lp1"}, /* Boost clock control in low power mode1 , */\
+ { 0xd561, "test_spare_out1"}, /* Test spare out 1 , */\
+ { 0xd580, "bst_dcmbst"}, /* DCM boost , */\
+ { 0xd593, "test_spare_out2"}, /* Test spare out 2 , */\
+ { 0xe00f, "sw_profile"}, /* Software profile data , */\
+ { 0xe10f, "sw_vstep"}, /* Software vstep information , */\
+ { 0xf000, "calibration_onetime"}, /* Calibration schedule , */\
+ { 0xf010, "calibr_ron_done"}, /* Calibration Ron executed , */\
+ { 0xf020, "calibr_dcdc_api_calibrate"}, /* Calibration current limit DCDC , */\
+ { 0xf030, "calibr_dcdc_delta_sign"}, /* Sign bit for delta calibration current limit DCDC , */\
+ { 0xf042, "calibr_dcdc_delta"}, /* Calibration delta current limit DCDC , */\
+ { 0xf078, "calibr_speaker_info"}, /* Reserved space for allowing customer to store speaker information, */\
+ { 0xf105, "calibr_vout_offset"}, /* DCDC offset calibration 2's complement (key1 protected), */\
+ { 0xf163, "calibr_vbg_trim"}, /* Bandgap trimming control , */\
+ { 0xf203, "calibr_gain"}, /* HW gain module (2's complement) , */\
+ { 0xf245, "calibr_offset"}, /* Offset for amplifier, HW gain module (2's complement), */\
+ { 0xf307, "calibr_gain_vs"}, /* Voltage sense gain , */\
+ { 0xf387, "calibr_gain_cs"}, /* Current sense gain (signed two's complement format), */\
+ { 0xf40f, "mtpdata4"}, /* MTP4 data , */\
+ { 0xf50f, "calibr_R25C"}, /* Ron resistance of speaker coil , */\
+ { 0xf60f, "mtpdata6"}, /* MTP6 data , */\
+ { 0xf706, "ctrl_offset_a"}, /* Offset of level shifter A , */\
+ { 0xf786, "ctrl_offset_b"}, /* Offset of amplifier level shifter B , */\
+ { 0xf806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
+ { 0xf870, "htol_iic_addr_en"}, /* HTOL I2C address enable control , */\
+ { 0xf884, "calibr_temp_offset"}, /* Temperature offset 2's compliment (key1 protected), */\
+ { 0xf8d2, "calibr_temp_gain"}, /* Temperature gain 2's compliment (key1 protected) , */\
+ { 0xf900, "mtp_lock_dcdcoff_mode"}, /* Disable functionality of dcdcoff_mode bit , */\
+ { 0xf910, "mtp_lock_enbl_coolflux"}, /* Disable functionality of enbl_coolflux bit , */\
+ { 0xf920, "mtp_lock_bypass_clipper"}, /* Disable function bypass_clipper , */\
+ { 0xf930, "mtp_enbl_pwm_delay_clock_gating"}, /* PWM delay clock auto gating , */\
+ { 0xf940, "mtp_enbl_ocp_clock_gating"}, /* OCP clock auto gating , */\
+ { 0xf987, "type_bits_fw"}, /* MTP control for firmware features - See Firmware I2C API document for details, */\
+ { 0xfa0f, "mtpdataA"}, /* MTPdataA , */\
+ { 0xfb0f, "mtpdataB"}, /* MTPdataB , */\
+ { 0xfc0f, "mtpdataC"}, /* MTPdataC , */\
+ { 0xfd0f, "mtpdataD"}, /* MTPdataD , */\
+ { 0xfe0f, "mtpdataE"}, /* MTPdataE , */\
+ { 0xff07, "calibr_osc_delta_ndiv"}, /* Calibration data for OSC1M, signed number representation, */\
+ { 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+#if 0
+enum tfa9894_irq {
+ tfa9894_irq_max = -1,
+ tfa9894_irq_all = -1 /* all irqs */};
+#endif//
+#define TFA9894_IRQ_NAMETABLE static tfaIrqName_t Tfa9894IrqNames[] = {\
+};
+#endif /* _TFA9894_TFAFIELDNAMES_H */
diff --git a/inc/tfa9896_tfafieldnames.h b/sound/soc/codecs/tfa9896_tfafieldnames.h
similarity index 87%
rename from inc/tfa9896_tfafieldnames.h
rename to sound/soc/codecs/tfa9896_tfafieldnames.h
index dc5e461..db708b4 100644
--- a/inc/tfa9896_tfafieldnames.h
+++ b/sound/soc/codecs/tfa9896_tfafieldnames.h
@@ -1,923 +1,923 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _TFA9896_TFAFIELDNAMES_H
-#define _TFA9896_TFAFIELDNAMES_H
-
-
-#define TFA9896_I2CVERSION 16
-
-typedef enum nxpTFA9896BfEnumList {
- TFA9896_BF_VDDS = 0x0000, /*!< Power-on-reset flag (auto clear by reading) */
- TFA9896_BF_PLLS = 0x0010, /*!< PLL lock to programmed frequency */
- TFA9896_BF_OTDS = 0x0020, /*!< Over Temperature Protection alarm */
- TFA9896_BF_OVDS = 0x0030, /*!< Over Voltage Protection alarm */
- TFA9896_BF_UVDS = 0x0040, /*!< Under Voltage Protection alarm */
- TFA9896_BF_OCDS = 0x0050, /*!< Over Current Protection alarm */
- TFA9896_BF_CLKS = 0x0060, /*!< Clocks stable flag */
- TFA9896_BF_CLIPS = 0x0070, /*!< Amplifier clipping */
- TFA9896_BF_MTPB = 0x0080, /*!< MTP busy copying data to/from I2C registers */
- TFA9896_BF_NOCLK = 0x0090, /*!< lost clock detection (reference input clock) */
- TFA9896_BF_SPKS = 0x00a0, /*!< Speaker error */
- TFA9896_BF_ACS = 0x00b0, /*!< Cold Start required */
- TFA9896_BF_SWS = 0x00c0, /*!< Amplifier engage (Amp Switching) */
- TFA9896_BF_WDS = 0x00d0, /*!< watchdog reset (activates reset) */
- TFA9896_BF_AMPS = 0x00e0, /*!< Amplifier is enabled by manager */
- TFA9896_BF_AREFS = 0x00f0, /*!< References are enabled by manager */
- TFA9896_BF_BATS = 0x0109, /*!< Battery voltage from ADC readout */
- TFA9896_BF_TEMPS = 0x0208, /*!< Temperature readout from the temperature sensor ( C) */
- TFA9896_BF_REV = 0x030f, /*!< Device revision information */
- TFA9896_BF_RCV = 0x0420, /*!< Enable receiver mode */
- TFA9896_BF_CHS12 = 0x0431, /*!< Channel Selection TDM input for Coolflux */
- TFA9896_BF_INPLVL= 0x0450, /*!< Input level selection attenuator ( */
- TFA9896_BF_CHSA = 0x0461, /*!< Input selection for amplifier */
- TFA9896_BF_AUDFS = 0x04c3, /*!< Audio sample rate setting */
- TFA9896_BF_BSSCR = 0x0501, /*!< Batteery protection attack time */
- TFA9896_BF_BSST = 0x0523, /*!< Battery protection threshold level */
- TFA9896_BF_BSSRL = 0x0561, /*!< Battery protection maximum reduction */
- TFA9896_BF_BSSRR = 0x0582, /*!< Battery protection release time */
- TFA9896_BF_BSSHY = 0x05b1, /*!< Battery Protection Hysteresis */
- TFA9896_BF_BSSR = 0x05e0, /*!< Battery voltage value for read out (only) */
- TFA9896_BF_BSSBY = 0x05f0, /*!< Bypass clipper battery protection */
- TFA9896_BF_DPSA = 0x0600, /*!< Enable dynamic powerstage activation (DPSA) */
- TFA9896_BF_ATTEN = 0x0613, /*!< Gain attenuation setting */
- TFA9896_BF_CFSM = 0x0650, /*!< Soft mute in CoolFlux */
- TFA9896_BF_BSSS = 0x0670, /*!< Battery sense steepness */
- TFA9896_BF_VOL = 0x0687, /*!< Coolflux volume control */
- TFA9896_BF_DCVO2 = 0x0702, /*!< Second Boost Voltage */
- TFA9896_BF_DCMCC = 0x0733, /*!< Max boost coil current - step of 175 mA */
- TFA9896_BF_DCVO1 = 0x0772, /*!< First Boost Voltage */
- TFA9896_BF_DCIE = 0x07a0, /*!< Adaptive boost mode */
- TFA9896_BF_DCSR = 0x07b0, /*!< Soft Rampup/down mode for DCDC controller */
- TFA9896_BF_DCPAVG= 0x07c0, /*!< ctrl_peak2avg for analog part of DCDC */
- TFA9896_BF_DCPWM = 0x07d0, /*!< DCDC PWM only mode */
- TFA9896_BF_TROS = 0x0800, /*!< Selection ambient temperature for speaker calibration */
- TFA9896_BF_EXTTS = 0x0818, /*!< External temperature for speaker calibration (C) */
- TFA9896_BF_PWDN = 0x0900, /*!< powerdown selection */
- TFA9896_BF_I2CR = 0x0910, /*!< All I2C registers reset to default */
- TFA9896_BF_CFE = 0x0920, /*!< Enable CoolFlux */
- TFA9896_BF_AMPE = 0x0930, /*!< Enable Amplifier */
- TFA9896_BF_DCA = 0x0940, /*!< Enable DCDC Boost converter */
- TFA9896_BF_SBSL = 0x0950, /*!< Coolflux configured */
- TFA9896_BF_AMPC = 0x0960, /*!< Selection if Coolflux enables amplifier */
- TFA9896_BF_DCDIS = 0x0970, /*!< DCDC boost converter not connected */
- TFA9896_BF_PSDR = 0x0980, /*!< IDDQ amplifier test selection */
- TFA9896_BF_INTPAD= 0x09c1, /*!< INT pad (interrupt bump output) configuration */
- TFA9896_BF_IPLL = 0x09e0, /*!< PLL input reference clock selection */
- TFA9896_BF_DCTRIP= 0x0a04, /*!< Adaptive boost trip levels (effective only when boost_intel is set to 1) */
- TFA9896_BF_DCHOLD= 0x0a54, /*!< Hold time for DCDC booster (effective only when boost_intel is set to 1) */
- TFA9896_BF_MTPK = 0x0b07, /*!< KEY2 to access key2 protected registers (default for engineering) */
- TFA9896_BF_CVFDLY= 0x0c25, /*!< Fractional delay adjustment between current and voltage sense */
- TFA9896_BF_OPENMTP= 0x0ec0, /*!< Enable programming of the MTP memory */
- TFA9896_BF_TDMPRF= 0x1011, /*!< TDM usecase selection control */
- TFA9896_BF_TDMEN = 0x1030, /*!< TDM interface enable */
- TFA9896_BF_TDMCKINV= 0x1040, /*!< TDM clock inversion, receive on */
- TFA9896_BF_TDMFSLN= 0x1053, /*!< TDM FS length */
- TFA9896_BF_TDMFSPOL= 0x1090, /*!< TDM FS polarity (start frame) */
- TFA9896_BF_TDMSAMSZ= 0x10a4, /*!< TDM sample size for all TDM sinks and sources */
- TFA9896_BF_TDMSLOTS= 0x1103, /*!< TDM number of slots */
- TFA9896_BF_TDMSLLN= 0x1144, /*!< TDM slot length */
- TFA9896_BF_TDMBRMG= 0x1194, /*!< TDM bits remaining after the last slot */
- TFA9896_BF_TDMDDEL= 0x11e0, /*!< TDM data delay */
- TFA9896_BF_TDMDADJ= 0x11f0, /*!< TDM data adjustment */
- TFA9896_BF_TDMTXFRM= 0x1201, /*!< TDM TXDATA format */
- TFA9896_BF_TDMUUS0= 0x1221, /*!< TDM TXDATA format unused slot SD0 */
- TFA9896_BF_TDMUUS1= 0x1241, /*!< TDM TXDATA format unused slot SD1 */
- TFA9896_BF_TDMSI0EN= 0x1270, /*!< TDM sink0 enable */
- TFA9896_BF_TDMSI1EN= 0x1280, /*!< TDM sink1 enable */
- TFA9896_BF_TDMSI2EN= 0x1290, /*!< TDM sink2 enable */
- TFA9896_BF_TDMSO0EN= 0x12a0, /*!< TDM source0 enable */
- TFA9896_BF_TDMSO1EN= 0x12b0, /*!< TDM source1 enable */
- TFA9896_BF_TDMSO2EN= 0x12c0, /*!< TDM source2 enable */
- TFA9896_BF_TDMSI0IO= 0x12d0, /*!< TDM sink0 IO selection */
- TFA9896_BF_TDMSI1IO= 0x12e0, /*!< TDM sink1 IO selection */
- TFA9896_BF_TDMSI2IO= 0x12f0, /*!< TDM sink2 IO selection */
- TFA9896_BF_TDMSO0IO= 0x1300, /*!< TDM source0 IO selection */
- TFA9896_BF_TDMSO1IO= 0x1310, /*!< TDM source1 IO selection */
- TFA9896_BF_TDMSO2IO= 0x1320, /*!< TDM source2 IO selection */
- TFA9896_BF_TDMSI0SL= 0x1333, /*!< TDM sink0 slot position [GAIN IN] */
- TFA9896_BF_TDMSI1SL= 0x1373, /*!< TDM sink1 slot position [CH1 IN] */
- TFA9896_BF_TDMSI2SL= 0x13b3, /*!< TDM sink2 slot position [CH2 IN] */
- TFA9896_BF_TDMSO0SL= 0x1403, /*!< TDM source0 slot position [GAIN OUT] */
- TFA9896_BF_TDMSO1SL= 0x1443, /*!< TDM source1 slot position [Voltage Sense] */
- TFA9896_BF_TDMSO2SL= 0x1483, /*!< TDM source2 slot position [Current Sense] */
- TFA9896_BF_NBCK = 0x14c3, /*!< TDM NBCK bit clock ratio */
- TFA9896_BF_INTOVDDS= 0x2000, /*!< flag_por_int_out */
- TFA9896_BF_INTOPLLS= 0x2010, /*!< flag_pll_lock_int_out */
- TFA9896_BF_INTOOTDS= 0x2020, /*!< flag_otpok_int_out */
- TFA9896_BF_INTOOVDS= 0x2030, /*!< flag_ovpok_int_out */
- TFA9896_BF_INTOUVDS= 0x2040, /*!< flag_uvpok_int_out */
- TFA9896_BF_INTOOCDS= 0x2050, /*!< flag_ocp_alarm_int_out */
- TFA9896_BF_INTOCLKS= 0x2060, /*!< flag_clocks_stable_int_out */
- TFA9896_BF_INTOCLIPS= 0x2070, /*!< flag_clip_int_out */
- TFA9896_BF_INTOMTPB= 0x2080, /*!< mtp_busy_int_out */
- TFA9896_BF_INTONOCLK= 0x2090, /*!< flag_lost_clk_int_out */
- TFA9896_BF_INTOSPKS= 0x20a0, /*!< flag_cf_speakererror_int_out */
- TFA9896_BF_INTOACS= 0x20b0, /*!< flag_cold_started_int_out */
- TFA9896_BF_INTOSWS= 0x20c0, /*!< flag_engage_int_out */
- TFA9896_BF_INTOWDS= 0x20d0, /*!< flag_watchdog_reset_int_out */
- TFA9896_BF_INTOAMPS= 0x20e0, /*!< flag_enbl_amp_int_out */
- TFA9896_BF_INTOAREFS= 0x20f0, /*!< flag_enbl_ref_int_out */
- TFA9896_BF_INTOERR= 0x2200, /*!< flag_cfma_err_int_out */
- TFA9896_BF_INTOACK= 0x2210, /*!< flag_cfma_ack_int_out */
- TFA9896_BF_INTIVDDS= 0x2300, /*!< flag_por_int_in */
- TFA9896_BF_INTIPLLS= 0x2310, /*!< flag_pll_lock_int_in */
- TFA9896_BF_INTIOTDS= 0x2320, /*!< flag_otpok_int_in */
- TFA9896_BF_INTIOVDS= 0x2330, /*!< flag_ovpok_int_in */
- TFA9896_BF_INTIUVDS= 0x2340, /*!< flag_uvpok_int_in */
- TFA9896_BF_INTIOCDS= 0x2350, /*!< flag_ocp_alarm_int_in */
- TFA9896_BF_INTICLKS= 0x2360, /*!< flag_clocks_stable_int_in */
- TFA9896_BF_INTICLIPS= 0x2370, /*!< flag_clip_int_in */
- TFA9896_BF_INTIMTPB= 0x2380, /*!< mtp_busy_int_in */
- TFA9896_BF_INTINOCLK= 0x2390, /*!< flag_lost_clk_int_in */
- TFA9896_BF_INTISPKS= 0x23a0, /*!< flag_cf_speakererror_int_in */
- TFA9896_BF_INTIACS= 0x23b0, /*!< flag_cold_started_int_in */
- TFA9896_BF_INTISWS= 0x23c0, /*!< flag_engage_int_in */
- TFA9896_BF_INTIWDS= 0x23d0, /*!< flag_watchdog_reset_int_in */
- TFA9896_BF_INTIAMPS= 0x23e0, /*!< flag_enbl_amp_int_in */
- TFA9896_BF_INTIAREFS= 0x23f0, /*!< flag_enbl_ref_int_in */
- TFA9896_BF_INTIERR= 0x2500, /*!< flag_cfma_err_int_in */
- TFA9896_BF_INTIACK= 0x2510, /*!< flag_cfma_ack_int_in */
- TFA9896_BF_INTENVDDS= 0x2600, /*!< flag_por_int_enable */
- TFA9896_BF_INTENPLLS= 0x2610, /*!< flag_pll_lock_int_enable */
- TFA9896_BF_INTENOTDS= 0x2620, /*!< flag_otpok_int_enable */
- TFA9896_BF_INTENOVDS= 0x2630, /*!< flag_ovpok_int_enable */
- TFA9896_BF_INTENUVDS= 0x2640, /*!< flag_uvpok_int_enable */
- TFA9896_BF_INTENOCDS= 0x2650, /*!< flag_ocp_alarm_int_enable */
- TFA9896_BF_INTENCLKS= 0x2660, /*!< flag_clocks_stable_int_enable */
- TFA9896_BF_INTENCLIPS= 0x2670, /*!< flag_clip_int_enable */
- TFA9896_BF_INTENMTPB= 0x2680, /*!< mtp_busy_int_enable */
- TFA9896_BF_INTENNOCLK= 0x2690, /*!< flag_lost_clk_int_enable */
- TFA9896_BF_INTENSPKS= 0x26a0, /*!< flag_cf_speakererror_int_enable */
- TFA9896_BF_INTENACS= 0x26b0, /*!< flag_cold_started_int_enable */
- TFA9896_BF_INTENSWS= 0x26c0, /*!< flag_engage_int_enable */
- TFA9896_BF_INTENWDS= 0x26d0, /*!< flag_watchdog_reset_int_enable */
- TFA9896_BF_INTENAMPS= 0x26e0, /*!< flag_enbl_amp_int_enable */
- TFA9896_BF_INTENAREFS= 0x26f0, /*!< flag_enbl_ref_int_enable */
- TFA9896_BF_INTENERR= 0x2800, /*!< flag_cfma_err_int_enable */
- TFA9896_BF_INTENACK= 0x2810, /*!< flag_cfma_ack_int_enable */
- TFA9896_BF_INTPOLVDDS= 0x2900, /*!< flag_por_int_pol */
- TFA9896_BF_INTPOLPLLS= 0x2910, /*!< flag_pll_lock_int_pol */
- TFA9896_BF_INTPOLOTDS= 0x2920, /*!< flag_otpok_int_pol */
- TFA9896_BF_INTPOLOVDS= 0x2930, /*!< flag_ovpok_int_pol */
- TFA9896_BF_INTPOLUVDS= 0x2940, /*!< flag_uvpok_int_pol */
- TFA9896_BF_INTPOLOCDS= 0x2950, /*!< flag_ocp_alarm_int_pol */
- TFA9896_BF_INTPOLCLKS= 0x2960, /*!< flag_clocks_stable_int_pol */
- TFA9896_BF_INTPOLCLIPS= 0x2970, /*!< flag_clip_int_pol */
- TFA9896_BF_INTPOLMTPB= 0x2980, /*!< mtp_busy_int_pol */
- TFA9896_BF_INTPOLNOCLK= 0x2990, /*!< flag_lost_clk_int_pol */
- TFA9896_BF_INTPOLSPKS= 0x29a0, /*!< flag_cf_speakererror_int_pol */
- TFA9896_BF_INTPOLACS= 0x29b0, /*!< flag_cold_started_int_pol */
- TFA9896_BF_INTPOLSWS= 0x29c0, /*!< flag_engage_int_pol */
- TFA9896_BF_INTPOLWDS= 0x29d0, /*!< flag_watchdog_reset_int_pol */
- TFA9896_BF_INTPOLAMPS= 0x29e0, /*!< flag_enbl_amp_int_pol */
- TFA9896_BF_INTPOLAREFS= 0x29f0, /*!< flag_enbl_ref_int_pol */
- TFA9896_BF_INTPOLERR= 0x2b00, /*!< flag_cfma_err_int_pol */
- TFA9896_BF_INTPOLACK= 0x2b10, /*!< flag_cfma_ack_int_pol */
- TFA9896_BF_CLIP = 0x4900, /*!< Bypass clip control */
- TFA9896_BF_CIMTP = 0x62b0, /*!< Start copying data from I2C mtp registers to mtp */
- TFA9896_BF_RST = 0x7000, /*!< Reset CoolFlux DSP */
- TFA9896_BF_DMEM = 0x7011, /*!< Target memory for access */
- TFA9896_BF_AIF = 0x7030, /*!< Auto increment flag for memory-address */
- TFA9896_BF_CFINT = 0x7040, /*!< CF Interrupt - auto clear */
- TFA9896_BF_REQ = 0x7087, /*!< CF request for accessing the 8 channels */
- TFA9896_BF_MADD = 0x710f, /*!< Memory address */
- TFA9896_BF_MEMA = 0x720f, /*!< Activate memory access */
- TFA9896_BF_ERR = 0x7307, /*!< CF error flags */
- TFA9896_BF_ACK = 0x7387, /*!< CF acknowledgement of the requests channels */
- TFA9896_BF_MTPOTC= 0x8000, /*!< Calibration schedule selection */
- TFA9896_BF_MTPEX = 0x8010, /*!< Calibration of RON status bit */
-} nxpTFA9896BfEnumList_t;
-#define TFA9896_NAMETABLE static tfaBfName_t Tfa9896DatasheetNames[]= {\
- { 0x0, "VDDS"}, /* Power-on-reset flag (auto clear by reading) , */\
- { 0x10, "PLLS"}, /* PLL lock to programmed frequency , */\
- { 0x20, "OTDS"}, /* Over Temperature Protection alarm , */\
- { 0x30, "OVDS"}, /* Over Voltage Protection alarm , */\
- { 0x40, "UVDS"}, /* Under Voltage Protection alarm , */\
- { 0x50, "OCDS"}, /* Over Current Protection alarm , */\
- { 0x60, "CLKS"}, /* Clocks stable flag , */\
- { 0x70, "CLIPS"}, /* Amplifier clipping , */\
- { 0x80, "MTPB"}, /* MTP busy copying data to/from I2C registers , */\
- { 0x90, "NOCLK"}, /* lost clock detection (reference input clock) , */\
- { 0xa0, "SPKS"}, /* Speaker error , */\
- { 0xb0, "ACS"}, /* Cold Start required , */\
- { 0xc0, "SWS"}, /* Amplifier engage (Amp Switching) , */\
- { 0xd0, "WDS"}, /* watchdog reset (activates reset) , */\
- { 0xe0, "AMPS"}, /* Amplifier is enabled by manager , */\
- { 0xf0, "AREFS"}, /* References are enabled by manager , */\
- { 0x109, "BATS"}, /* Battery voltage from ADC readout , */\
- { 0x208, "TEMPS"}, /* Temperature readout from the temperature sensor ( C), */\
- { 0x30f, "REV"}, /* Device revision information , */\
- { 0x420, "RCV"}, /* Enable receiver mode , */\
- { 0x431, "CHS12"}, /* Channel Selection TDM input for Coolflux , */\
- { 0x450, "INPLVL"}, /* Input level selection attenuator ( , */\
- { 0x461, "CHSA"}, /* Input selection for amplifier , */\
- { 0x4c3, "AUDFS"}, /* Audio sample rate setting , */\
- { 0x501, "BSSCR"}, /* Batteery protection attack time , */\
- { 0x523, "BSST"}, /* Battery protection threshold level , */\
- { 0x561, "BSSRL"}, /* Battery protection maximum reduction , */\
- { 0x582, "BSSRR"}, /* Battery protection release time , */\
- { 0x5b1, "BSSHY"}, /* Battery Protection Hysteresis , */\
- { 0x5e0, "BSSR"}, /* Battery voltage value for read out (only) , */\
- { 0x5f0, "BSSBY"}, /* Bypass clipper battery protection , */\
- { 0x600, "DPSA"}, /* Enable dynamic powerstage activation (DPSA) , */\
- { 0x613, "ATTEN"}, /* Gain attenuation setting , */\
- { 0x650, "CFSM"}, /* Soft mute in CoolFlux , */\
- { 0x670, "BSSS"}, /* Battery sense steepness , */\
- { 0x687, "VOL"}, /* Coolflux volume control , */\
- { 0x702, "DCVO2"}, /* Second Boost Voltage , */\
- { 0x733, "DCMCC"}, /* Max boost coil current - step of 175 mA , */\
- { 0x772, "DCVO1"}, /* First Boost Voltage , */\
- { 0x7a0, "DCIE"}, /* Adaptive boost mode , */\
- { 0x7b0, "DCSR"}, /* Soft Rampup/down mode for DCDC controller , */\
- { 0x7c0, "DCPAVG"}, /* ctrl_peak2avg for analog part of DCDC , */\
- { 0x7d0, "DCPWM"}, /* DCDC PWM only mode , */\
- { 0x800, "TROS"}, /* Selection ambient temperature for speaker calibration , */\
- { 0x818, "EXTTS"}, /* External temperature for speaker calibration (C) , */\
- { 0x900, "PWDN"}, /* powerdown selection , */\
- { 0x910, "I2CR"}, /* All I2C registers reset to default , */\
- { 0x920, "CFE"}, /* Enable CoolFlux , */\
- { 0x930, "AMPE"}, /* Enable Amplifier , */\
- { 0x940, "DCA"}, /* Enable DCDC Boost converter , */\
- { 0x950, "SBSL"}, /* Coolflux configured , */\
- { 0x960, "AMPC"}, /* Selection if Coolflux enables amplifier , */\
- { 0x970, "DCDIS"}, /* DCDC boost converter not connected , */\
- { 0x980, "PSDR"}, /* IDDQ amplifier test selection , */\
- { 0x9c1, "INTPAD"}, /* INT pad (interrupt bump output) configuration , */\
- { 0x9e0, "IPLL"}, /* PLL input reference clock selection , */\
- { 0xa04, "DCTRIP"}, /* Adaptive boost trip levels (effective only when boost_intel is set to 1), */\
- { 0xa54, "DCHOLD"}, /* Hold time for DCDC booster (effective only when boost_intel is set to 1), */\
- { 0xb07, "MTPK"}, /* KEY2 to access key2 protected registers (default for engineering), */\
- { 0xc25, "CVFDLY"}, /* Fractional delay adjustment between current and voltage sense, */\
- { 0xec0, "OPENMTP"}, /* Enable programming of the MTP memory , */\
- { 0x1011, "TDMPRF"}, /* TDM usecase selection control , */\
- { 0x1030, "TDMEN"}, /* TDM interface enable , */\
- { 0x1040, "TDMCKINV"}, /* TDM clock inversion, receive on , */\
- { 0x1053, "TDMFSLN"}, /* TDM FS length , */\
- { 0x1090, "TDMFSPOL"}, /* TDM FS polarity (start frame) , */\
- { 0x10a4, "TDMSAMSZ"}, /* TDM sample size for all TDM sinks and sources , */\
- { 0x1103, "TDMSLOTS"}, /* TDM number of slots , */\
- { 0x1144, "TDMSLLN"}, /* TDM slot length , */\
- { 0x1194, "TDMBRMG"}, /* TDM bits remaining after the last slot , */\
- { 0x11e0, "TDMDDEL"}, /* TDM data delay , */\
- { 0x11f0, "TDMDADJ"}, /* TDM data adjustment , */\
- { 0x1201, "TDMTXFRM"}, /* TDM TXDATA format , */\
- { 0x1221, "TDMUUS0"}, /* TDM TXDATA format unused slot SD0 , */\
- { 0x1241, "TDMUUS1"}, /* TDM TXDATA format unused slot SD1 , */\
- { 0x1270, "TDMSI0EN"}, /* TDM sink0 enable , */\
- { 0x1280, "TDMSI1EN"}, /* TDM sink1 enable , */\
- { 0x1290, "TDMSI2EN"}, /* TDM sink2 enable , */\
- { 0x12a0, "TDMSO0EN"}, /* TDM source0 enable , */\
- { 0x12b0, "TDMSO1EN"}, /* TDM source1 enable , */\
- { 0x12c0, "TDMSO2EN"}, /* TDM source2 enable , */\
- { 0x12d0, "TDMSI0IO"}, /* TDM sink0 IO selection , */\
- { 0x12e0, "TDMSI1IO"}, /* TDM sink1 IO selection , */\
- { 0x12f0, "TDMSI2IO"}, /* TDM sink2 IO selection , */\
- { 0x1300, "TDMSO0IO"}, /* TDM source0 IO selection , */\
- { 0x1310, "TDMSO1IO"}, /* TDM source1 IO selection , */\
- { 0x1320, "TDMSO2IO"}, /* TDM source2 IO selection , */\
- { 0x1333, "TDMSI0SL"}, /* TDM sink0 slot position [GAIN IN] , */\
- { 0x1373, "TDMSI1SL"}, /* TDM sink1 slot position [CH1 IN] , */\
- { 0x13b3, "TDMSI2SL"}, /* TDM sink2 slot position [CH2 IN] , */\
- { 0x1403, "TDMSO0SL"}, /* TDM source0 slot position [GAIN OUT] , */\
- { 0x1443, "TDMSO1SL"}, /* TDM source1 slot position [Voltage Sense] , */\
- { 0x1483, "TDMSO2SL"}, /* TDM source2 slot position [Current Sense] , */\
- { 0x14c3, "NBCK"}, /* TDM NBCK bit clock ratio , */\
- { 0x2000, "INTOVDDS"}, /* flag_por_int_out , */\
- { 0x2010, "INTOPLLS"}, /* flag_pll_lock_int_out , */\
- { 0x2020, "INTOOTDS"}, /* flag_otpok_int_out , */\
- { 0x2030, "INTOOVDS"}, /* flag_ovpok_int_out , */\
- { 0x2040, "INTOUVDS"}, /* flag_uvpok_int_out , */\
- { 0x2050, "INTOOCDS"}, /* flag_ocp_alarm_int_out , */\
- { 0x2060, "INTOCLKS"}, /* flag_clocks_stable_int_out , */\
- { 0x2070, "INTOCLIPS"}, /* flag_clip_int_out , */\
- { 0x2080, "INTOMTPB"}, /* mtp_busy_int_out , */\
- { 0x2090, "INTONOCLK"}, /* flag_lost_clk_int_out , */\
- { 0x20a0, "INTOSPKS"}, /* flag_cf_speakererror_int_out , */\
- { 0x20b0, "INTOACS"}, /* flag_cold_started_int_out , */\
- { 0x20c0, "INTOSWS"}, /* flag_engage_int_out , */\
- { 0x20d0, "INTOWDS"}, /* flag_watchdog_reset_int_out , */\
- { 0x20e0, "INTOAMPS"}, /* flag_enbl_amp_int_out , */\
- { 0x20f0, "INTOAREFS"}, /* flag_enbl_ref_int_out , */\
- { 0x2200, "INTOERR"}, /* flag_cfma_err_int_out , */\
- { 0x2210, "INTOACK"}, /* flag_cfma_ack_int_out , */\
- { 0x2300, "INTIVDDS"}, /* flag_por_int_in , */\
- { 0x2310, "INTIPLLS"}, /* flag_pll_lock_int_in , */\
- { 0x2320, "INTIOTDS"}, /* flag_otpok_int_in , */\
- { 0x2330, "INTIOVDS"}, /* flag_ovpok_int_in , */\
- { 0x2340, "INTIUVDS"}, /* flag_uvpok_int_in , */\
- { 0x2350, "INTIOCDS"}, /* flag_ocp_alarm_int_in , */\
- { 0x2360, "INTICLKS"}, /* flag_clocks_stable_int_in , */\
- { 0x2370, "INTICLIPS"}, /* flag_clip_int_in , */\
- { 0x2380, "INTIMTPB"}, /* mtp_busy_int_in , */\
- { 0x2390, "INTINOCLK"}, /* flag_lost_clk_int_in , */\
- { 0x23a0, "INTISPKS"}, /* flag_cf_speakererror_int_in , */\
- { 0x23b0, "INTIACS"}, /* flag_cold_started_int_in , */\
- { 0x23c0, "INTISWS"}, /* flag_engage_int_in , */\
- { 0x23d0, "INTIWDS"}, /* flag_watchdog_reset_int_in , */\
- { 0x23e0, "INTIAMPS"}, /* flag_enbl_amp_int_in , */\
- { 0x23f0, "INTIAREFS"}, /* flag_enbl_ref_int_in , */\
- { 0x2500, "INTIERR"}, /* flag_cfma_err_int_in , */\
- { 0x2510, "INTIACK"}, /* flag_cfma_ack_int_in , */\
- { 0x2600, "INTENVDDS"}, /* flag_por_int_enable , */\
- { 0x2610, "INTENPLLS"}, /* flag_pll_lock_int_enable , */\
- { 0x2620, "INTENOTDS"}, /* flag_otpok_int_enable , */\
- { 0x2630, "INTENOVDS"}, /* flag_ovpok_int_enable , */\
- { 0x2640, "INTENUVDS"}, /* flag_uvpok_int_enable , */\
- { 0x2650, "INTENOCDS"}, /* flag_ocp_alarm_int_enable , */\
- { 0x2660, "INTENCLKS"}, /* flag_clocks_stable_int_enable , */\
- { 0x2670, "INTENCLIPS"}, /* flag_clip_int_enable , */\
- { 0x2680, "INTENMTPB"}, /* mtp_busy_int_enable , */\
- { 0x2690, "INTENNOCLK"}, /* flag_lost_clk_int_enable , */\
- { 0x26a0, "INTENSPKS"}, /* flag_cf_speakererror_int_enable , */\
- { 0x26b0, "INTENACS"}, /* flag_cold_started_int_enable , */\
- { 0x26c0, "INTENSWS"}, /* flag_engage_int_enable , */\
- { 0x26d0, "INTENWDS"}, /* flag_watchdog_reset_int_enable , */\
- { 0x26e0, "INTENAMPS"}, /* flag_enbl_amp_int_enable , */\
- { 0x26f0, "INTENAREFS"}, /* flag_enbl_ref_int_enable , */\
- { 0x2800, "INTENERR"}, /* flag_cfma_err_int_enable , */\
- { 0x2810, "INTENACK"}, /* flag_cfma_ack_int_enable , */\
- { 0x2900, "INTPOLVDDS"}, /* flag_por_int_pol , */\
- { 0x2910, "INTPOLPLLS"}, /* flag_pll_lock_int_pol , */\
- { 0x2920, "INTPOLOTDS"}, /* flag_otpok_int_pol , */\
- { 0x2930, "INTPOLOVDS"}, /* flag_ovpok_int_pol , */\
- { 0x2940, "INTPOLUVDS"}, /* flag_uvpok_int_pol , */\
- { 0x2950, "INTPOLOCDS"}, /* flag_ocp_alarm_int_pol , */\
- { 0x2960, "INTPOLCLKS"}, /* flag_clocks_stable_int_pol , */\
- { 0x2970, "INTPOLCLIPS"}, /* flag_clip_int_pol , */\
- { 0x2980, "INTPOLMTPB"}, /* mtp_busy_int_pol , */\
- { 0x2990, "INTPOLNOCLK"}, /* flag_lost_clk_int_pol , */\
- { 0x29a0, "INTPOLSPKS"}, /* flag_cf_speakererror_int_pol , */\
- { 0x29b0, "INTPOLACS"}, /* flag_cold_started_int_pol , */\
- { 0x29c0, "INTPOLSWS"}, /* flag_engage_int_pol , */\
- { 0x29d0, "INTPOLWDS"}, /* flag_watchdog_reset_int_pol , */\
- { 0x29e0, "INTPOLAMPS"}, /* flag_enbl_amp_int_pol , */\
- { 0x29f0, "INTPOLAREFS"}, /* flag_enbl_ref_int_pol , */\
- { 0x2b00, "INTPOLERR"}, /* flag_cfma_err_int_pol , */\
- { 0x2b10, "INTPOLACK"}, /* flag_cfma_ack_int_pol , */\
- { 0x4900, "CLIP"}, /* Bypass clip control , */\
- { 0x62b0, "CIMTP"}, /* Start copying data from I2C mtp registers to mtp , */\
- { 0x7000, "RST"}, /* Reset CoolFlux DSP , */\
- { 0x7011, "DMEM"}, /* Target memory for access , */\
- { 0x7030, "AIF"}, /* Auto increment flag for memory-address , */\
- { 0x7040, "CFINT"}, /* CF Interrupt - auto clear , */\
- { 0x7087, "REQ"}, /* CF request for accessing the 8 channels , */\
- { 0x710f, "MADD"}, /* Memory address , */\
- { 0x720f, "MEMA"}, /* Activate memory access , */\
- { 0x7307, "ERR"}, /* CF error flags , */\
- { 0x7387, "ACK"}, /* CF acknowledgement of the requests channels , */\
- { 0x8000, "MTPOTC"}, /* Calibration schedule selection , */\
- { 0x8010, "MTPEX"}, /* Calibration of RON status bit , */\
- { 0x8045, "SWPROFIL" },\
- { 0x80a5, "SWVSTEP" },\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-
-#define TFA9896_BITNAMETABLE static tfaBfName_t Tfa9896BitNames[]= {\
- { 0x0, "flag_por"}, /* Power-on-reset flag (auto clear by reading) , */\
- { 0x10, "flag_pll_lock"}, /* PLL lock to programmed frequency , */\
- { 0x20, "flag_otpok"}, /* Over Temperature Protection alarm , */\
- { 0x30, "flag_ovpok"}, /* Over Voltage Protection alarm , */\
- { 0x40, "flag_uvpok"}, /* Under Voltage Protection alarm , */\
- { 0x50, "flag_ocp_alarm"}, /* Over Current Protection alarm , */\
- { 0x60, "flag_clocks_stable"}, /* Clocks stable flag , */\
- { 0x70, "flag_clip"}, /* Amplifier clipping , */\
- { 0x80, "mtp_busy"}, /* MTP busy copying data to/from I2C registers , */\
- { 0x90, "flag_lost_clk"}, /* lost clock detection (reference input clock) , */\
- { 0xa0, "flag_cf_speakererror"}, /* Speaker error , */\
- { 0xb0, "flag_cold_started"}, /* Cold Start required , */\
- { 0xc0, "flag_engage"}, /* Amplifier engage (Amp Switching) , */\
- { 0xd0, "flag_watchdog_reset"}, /* watchdog reset (activates reset) , */\
- { 0xe0, "flag_enbl_amp"}, /* Amplifier is enabled by manager , */\
- { 0xf0, "flag_enbl_ref"}, /* References are enabled by manager , */\
- { 0x109, "bat_adc"}, /* Battery voltage from ADC readout , */\
- { 0x208, "temp_adc"}, /* Temperature readout from the temperature sensor ( C), */\
- { 0x30f, "device_rev"}, /* Device revision information , */\
- { 0x420, "ctrl_rcv"}, /* Enable receiver mode , */\
- { 0x431, "chan_sel"}, /* Channel Selection TDM input for Coolflux , */\
- { 0x450, "input_level"}, /* Input level selection attenuator ( , */\
- { 0x461, "vamp_sel"}, /* Input selection for amplifier , */\
- { 0x4c3, "audio_fs"}, /* Audio sample rate setting , */\
- { 0x501, "vbat_prot_attacktime"}, /* Batteery protection attack time , */\
- { 0x523, "vbat_prot_thlevel"}, /* Battery protection threshold level , */\
- { 0x561, "vbat_prot_max_reduct"}, /* Battery protection maximum reduction , */\
- { 0x582, "vbat_prot_release_t"}, /* Battery protection release time , */\
- { 0x5b1, "vbat_prot_hysterese"}, /* Battery Protection Hysteresis , */\
- { 0x5d0, "reset_min_vbat"}, /* Battery supply safeguard clipper reset ( if CF_DSP is bypassed), */\
- { 0x5e0, "sel_vbat"}, /* Battery voltage value for read out (only) , */\
- { 0x5f0, "bypass_clipper"}, /* Bypass clipper battery protection , */\
- { 0x600, "dpsa"}, /* Enable dynamic powerstage activation (DPSA) , */\
- { 0x613, "ctrl_att"}, /* Gain attenuation setting , */\
- { 0x650, "cf_mute"}, /* Soft mute in CoolFlux , */\
- { 0x670, "batsense_steepness"}, /* Battery sense steepness , */\
- { 0x687, "vol"}, /* Coolflux volume control , */\
- { 0x702, "scnd_boost_voltage"}, /* Second Boost Voltage , */\
- { 0x733, "boost_cur"}, /* Max boost coil current - step of 175 mA , */\
- { 0x772, "frst_boost_voltage"}, /* First Boost Voltage , */\
- { 0x7a0, "boost_intel"}, /* Adaptive boost mode , */\
- { 0x7b0, "boost_speed"}, /* Soft Rampup/down mode for DCDC controller , */\
- { 0x7c0, "boost_peak2avg"}, /* ctrl_peak2avg for analog part of DCDC , */\
- { 0x7d0, "dcdc_pwmonly"}, /* DCDC PWM only mode , */\
- { 0x7e0, "ignore_flag_voutcomp86"}, /* Ignore flag_voutcomp86 (flag from analog) , */\
- { 0x800, "ext_temp_sel"}, /* Selection ambient temperature for speaker calibration , */\
- { 0x818, "ext_temp"}, /* External temperature for speaker calibration (C) , */\
- { 0x900, "powerdown"}, /* powerdown selection , */\
- { 0x910, "reset"}, /* All I2C registers reset to default , */\
- { 0x920, "enbl_coolflux"}, /* Enable CoolFlux , */\
- { 0x930, "enbl_amplifier"}, /* Enable Amplifier , */\
- { 0x940, "enbl_boost"}, /* Enable DCDC Boost converter , */\
- { 0x950, "coolflux_configured"}, /* Coolflux configured , */\
- { 0x960, "sel_enbl_amplifier"}, /* Selection if Coolflux enables amplifier , */\
- { 0x970, "dcdcoff_mode"}, /* DCDC boost converter not connected , */\
- { 0x980, "iddqtest"}, /* IDDQ amplifier test selection , */\
- { 0x9c1, "int_pad_io"}, /* INT pad (interrupt bump output) configuration , */\
- { 0x9e0, "sel_fs_bck"}, /* PLL input reference clock selection , */\
- { 0x9f0, "sel_scl_cf_clock"}, /* Coolflux sub-system clock selection , */\
- { 0xa04, "boost_trip_lvl"}, /* Adaptive boost trip levels (effective only when boost_intel is set to 1), */\
- { 0xa54, "boost_hold_time"}, /* Hold time for DCDC booster (effective only when boost_intel is set to 1), */\
- { 0xaa1, "bst_slpcmplvl"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
- { 0xb07, "mtpkey2"}, /* KEY2 to access key2 protected registers (default for engineering), */\
- { 0xc00, "enbl_volt_sense"}, /* Voltage sense enabling control bit , */\
- { 0xc10, "vsense_pwm_sel"}, /* Voltage sense source selection , */\
- { 0xc25, "vi_frac_delay"}, /* Fractional delay adjustment between current and voltage sense, */\
- { 0xc80, "sel_voltsense_out"}, /* TDM output data selection for AEC , */\
- { 0xc90, "vsense_bypass_avg"}, /* Voltage sense average block bypass , */\
- { 0xd05, "cf_frac_delay"}, /* Fractional delay adjustment between current and voltage sense by firmware, */\
- { 0xe00, "bypass_dcdc_curr_prot"}, /* Control to switch off dcdc current reduction with bat protection, */\
- { 0xe10, "bypass_ocp"}, /* Bypass OCP (digital IP block) , */\
- { 0xe20, "ocptest"}, /* ocptest (analog IP block) enable , */\
- { 0xe80, "disable_clock_sh_prot"}, /* Disable clock_sh protection , */\
- { 0xe92, "reserve_reg_15_09"}, /* Spare control bits for future usage , */\
- { 0xec0, "unprotect_mtp"}, /* Enable programming of the MTP memory , */\
- { 0xed2, "reserve_reg_15_13"}, /* Spare control bits for future usage , */\
- { 0xf00, "dcdc_pfm20khz_limit"}, /* DCDC in PFM mode forcing each 50us a pwm pulse , */\
- { 0xf11, "dcdc_ctrl_maxzercnt"}, /* DCDC number of zero current flags required to go to pfm mode, */\
- { 0xf36, "dcdc_vbat_delta_detect"}, /* DCDC threshold required on a delta Vbat (in PFM mode) switching to PWM mode, */\
- { 0xfa0, "dcdc_ignore_vbat"}, /* Ignore an increase on Vbat , */\
- { 0x1011, "tdm_usecase"}, /* TDM usecase selection control , */\
- { 0x1030, "tdm_enable"}, /* TDM interface enable , */\
- { 0x1040, "tdm_clk_inversion"}, /* TDM clock inversion, receive on , */\
- { 0x1053, "tdm_fs_ws_length"}, /* TDM FS length , */\
- { 0x1090, "tdm_fs_ws_polarity"}, /* TDM FS polarity (start frame) , */\
- { 0x10a4, "tdm_sample_size"}, /* TDM sample size for all TDM sinks and sources , */\
- { 0x1103, "tdm_nb_of_slots"}, /* TDM number of slots , */\
- { 0x1144, "tdm_slot_length"}, /* TDM slot length , */\
- { 0x1194, "tdm_bits_remaining"}, /* TDM bits remaining after the last slot , */\
- { 0x11e0, "tdm_data_delay"}, /* TDM data delay , */\
- { 0x11f0, "tdm_data_adjustment"}, /* TDM data adjustment , */\
- { 0x1201, "tdm_txdata_format"}, /* TDM TXDATA format , */\
- { 0x1221, "tdm_txdata_format_unused_slot_sd0"}, /* TDM TXDATA format unused slot SD0 , */\
- { 0x1241, "tdm_txdata_format_unused_slot_sd1"}, /* TDM TXDATA format unused slot SD1 , */\
- { 0x1270, "tdm_sink0_enable"}, /* TDM sink0 enable , */\
- { 0x1280, "tdm_sink1_enable"}, /* TDM sink1 enable , */\
- { 0x1290, "tdm_sink2_enable"}, /* TDM sink2 enable , */\
- { 0x12a0, "tdm_source0_enable"}, /* TDM source0 enable , */\
- { 0x12b0, "tdm_source1_enable"}, /* TDM source1 enable , */\
- { 0x12c0, "tdm_source2_enable"}, /* TDM source2 enable , */\
- { 0x12d0, "tdm_sink0_io"}, /* TDM sink0 IO selection , */\
- { 0x12e0, "tdm_sink1_io"}, /* TDM sink1 IO selection , */\
- { 0x12f0, "tdm_sink2_io"}, /* TDM sink2 IO selection , */\
- { 0x1300, "tdm_source0_io"}, /* TDM source0 IO selection , */\
- { 0x1310, "tdm_source1_io"}, /* TDM source1 IO selection , */\
- { 0x1320, "tdm_source2_io"}, /* TDM source2 IO selection , */\
- { 0x1333, "tdm_sink0_slot"}, /* TDM sink0 slot position [GAIN IN] , */\
- { 0x1373, "tdm_sink1_slot"}, /* TDM sink1 slot position [CH1 IN] , */\
- { 0x13b3, "tdm_sink2_slot"}, /* TDM sink2 slot position [CH2 IN] , */\
- { 0x1403, "tdm_source0_slot"}, /* TDM source0 slot position [GAIN OUT] , */\
- { 0x1443, "tdm_source1_slot"}, /* TDM source1 slot position [Voltage Sense] , */\
- { 0x1483, "tdm_source2_slot"}, /* TDM source2 slot position [Current Sense] , */\
- { 0x14c3, "tdm_nbck"}, /* TDM NBCK bit clock ratio , */\
- { 0x1500, "flag_tdm_lut_error"}, /* TDM LUT error flag , */\
- { 0x1512, "flag_tdm_status"}, /* TDM interface status bits , */\
- { 0x1540, "flag_tdm_error"}, /* TDM interface error indicator , */\
- { 0x1551, "status_bst_mode"}, /* DCDC mode status bits , */\
- { 0x2000, "flag_por_int_out"}, /* flag_por_int_out , */\
- { 0x2010, "flag_pll_lock_int_out"}, /* flag_pll_lock_int_out , */\
- { 0x2020, "flag_otpok_int_out"}, /* flag_otpok_int_out , */\
- { 0x2030, "flag_ovpok_int_out"}, /* flag_ovpok_int_out , */\
- { 0x2040, "flag_uvpok_int_out"}, /* flag_uvpok_int_out , */\
- { 0x2050, "flag_ocp_alarm_int_out"}, /* flag_ocp_alarm_int_out , */\
- { 0x2060, "flag_clocks_stable_int_out"}, /* flag_clocks_stable_int_out , */\
- { 0x2070, "flag_clip_int_out"}, /* flag_clip_int_out , */\
- { 0x2080, "mtp_busy_int_out"}, /* mtp_busy_int_out , */\
- { 0x2090, "flag_lost_clk_int_out"}, /* flag_lost_clk_int_out , */\
- { 0x20a0, "flag_cf_speakererror_int_out"}, /* flag_cf_speakererror_int_out , */\
- { 0x20b0, "flag_cold_started_int_out"}, /* flag_cold_started_int_out , */\
- { 0x20c0, "flag_engage_int_out"}, /* flag_engage_int_out , */\
- { 0x20d0, "flag_watchdog_reset_int_out"}, /* flag_watchdog_reset_int_out , */\
- { 0x20e0, "flag_enbl_amp_int_out"}, /* flag_enbl_amp_int_out , */\
- { 0x20f0, "flag_enbl_ref_int_out"}, /* flag_enbl_ref_int_out , */\
- { 0x2100, "flag_voutcomp_int_out"}, /* flag_voutcomp_int_out , */\
- { 0x2110, "flag_voutcomp93_int_out"}, /* flag_voutcomp93_int_out , */\
- { 0x2120, "flag_voutcomp86_int_out"}, /* flag_voutcomp86_int_out , */\
- { 0x2130, "flag_hiz_int_out"}, /* flag_hiz_int_out , */\
- { 0x2140, "flag_ocpokbst_int_out"}, /* flag_ocpokbst_int_out , */\
- { 0x2150, "flag_peakcur_int_out"}, /* flag_peakcur_int_out , */\
- { 0x2160, "flag_ocpokap_int_out"}, /* flag_ocpokap_int_out , */\
- { 0x2170, "flag_ocpokan_int_out"}, /* flag_ocpokan_int_out , */\
- { 0x2180, "flag_ocpokbp_int_out"}, /* flag_ocpokbp_int_out , */\
- { 0x2190, "flag_ocpokbn_int_out"}, /* flag_ocpokbn_int_out , */\
- { 0x21a0, "flag_adc10_ready_int_out"}, /* flag_adc10_ready_int_out , */\
- { 0x21b0, "flag_clipa_high_int_out"}, /* flag_clipa_high_int_out , */\
- { 0x21c0, "flag_clipa_low_int_out"}, /* flag_clipa_low_int_out , */\
- { 0x21d0, "flag_clipb_high_int_out"}, /* flag_clipb_high_int_out , */\
- { 0x21e0, "flag_clipb_low_int_out"}, /* flag_clipb_low_int_out , */\
- { 0x21f0, "flag_tdm_error_int_out"}, /* flag_tdm_error_int_out , */\
- { 0x2200, "flag_cfma_err_int_out"}, /* flag_cfma_err_int_out , */\
- { 0x2210, "flag_cfma_ack_int_out"}, /* flag_cfma_ack_int_out , */\
- { 0x2300, "flag_por_int_in"}, /* flag_por_int_in , */\
- { 0x2310, "flag_pll_lock_int_in"}, /* flag_pll_lock_int_in , */\
- { 0x2320, "flag_otpok_int_in"}, /* flag_otpok_int_in , */\
- { 0x2330, "flag_ovpok_int_in"}, /* flag_ovpok_int_in , */\
- { 0x2340, "flag_uvpok_int_in"}, /* flag_uvpok_int_in , */\
- { 0x2350, "flag_ocp_alarm_int_in"}, /* flag_ocp_alarm_int_in , */\
- { 0x2360, "flag_clocks_stable_int_in"}, /* flag_clocks_stable_int_in , */\
- { 0x2370, "flag_clip_int_in"}, /* flag_clip_int_in , */\
- { 0x2380, "mtp_busy_int_in"}, /* mtp_busy_int_in , */\
- { 0x2390, "flag_lost_clk_int_in"}, /* flag_lost_clk_int_in , */\
- { 0x23a0, "flag_cf_speakererror_int_in"}, /* flag_cf_speakererror_int_in , */\
- { 0x23b0, "flag_cold_started_int_in"}, /* flag_cold_started_int_in , */\
- { 0x23c0, "flag_engage_int_in"}, /* flag_engage_int_in , */\
- { 0x23d0, "flag_watchdog_reset_int_in"}, /* flag_watchdog_reset_int_in , */\
- { 0x23e0, "flag_enbl_amp_int_in"}, /* flag_enbl_amp_int_in , */\
- { 0x23f0, "flag_enbl_ref_int_in"}, /* flag_enbl_ref_int_in , */\
- { 0x2400, "flag_voutcomp_int_in"}, /* flag_voutcomp_int_in , */\
- { 0x2410, "flag_voutcomp93_int_in"}, /* flag_voutcomp93_int_in , */\
- { 0x2420, "flag_voutcomp86_int_in"}, /* flag_voutcomp86_int_in , */\
- { 0x2430, "flag_hiz_int_in"}, /* flag_hiz_int_in , */\
- { 0x2440, "flag_ocpokbst_int_in"}, /* flag_ocpokbst_int_in , */\
- { 0x2450, "flag_peakcur_int_in"}, /* flag_peakcur_int_in , */\
- { 0x2460, "flag_ocpokap_int_in"}, /* flag_ocpokap_int_in , */\
- { 0x2470, "flag_ocpokan_int_in"}, /* flag_ocpokan_int_in , */\
- { 0x2480, "flag_ocpokbp_int_in"}, /* flag_ocpokbp_int_in , */\
- { 0x2490, "flag_ocpokbn_int_in"}, /* flag_ocpokbn_int_in , */\
- { 0x24a0, "flag_adc10_ready_int_in"}, /* flag_adc10_ready_int_in , */\
- { 0x24b0, "flag_clipa_high_int_in"}, /* flag_clipa_high_int_in , */\
- { 0x24c0, "flag_clipa_low_int_in"}, /* flag_clipa_low_int_in , */\
- { 0x24d0, "flag_clipb_high_int_in"}, /* flag_clipb_high_int_in , */\
- { 0x24e0, "flag_clipb_low_int_in"}, /* flag_clipb_low_int_in , */\
- { 0x24f0, "flag_tdm_error_int_in"}, /* flag_tdm_error_int_in , */\
- { 0x2500, "flag_cfma_err_int_in"}, /* flag_cfma_err_int_in , */\
- { 0x2510, "flag_cfma_ack_int_in"}, /* flag_cfma_ack_int_in , */\
- { 0x2600, "flag_por_int_enable"}, /* flag_por_int_enable , */\
- { 0x2610, "flag_pll_lock_int_enable"}, /* flag_pll_lock_int_enable , */\
- { 0x2620, "flag_otpok_int_enable"}, /* flag_otpok_int_enable , */\
- { 0x2630, "flag_ovpok_int_enable"}, /* flag_ovpok_int_enable , */\
- { 0x2640, "flag_uvpok_int_enable"}, /* flag_uvpok_int_enable , */\
- { 0x2650, "flag_ocp_alarm_int_enable"}, /* flag_ocp_alarm_int_enable , */\
- { 0x2660, "flag_clocks_stable_int_enable"}, /* flag_clocks_stable_int_enable , */\
- { 0x2670, "flag_clip_int_enable"}, /* flag_clip_int_enable , */\
- { 0x2680, "mtp_busy_int_enable"}, /* mtp_busy_int_enable , */\
- { 0x2690, "flag_lost_clk_int_enable"}, /* flag_lost_clk_int_enable , */\
- { 0x26a0, "flag_cf_speakererror_int_enable"}, /* flag_cf_speakererror_int_enable , */\
- { 0x26b0, "flag_cold_started_int_enable"}, /* flag_cold_started_int_enable , */\
- { 0x26c0, "flag_engage_int_enable"}, /* flag_engage_int_enable , */\
- { 0x26d0, "flag_watchdog_reset_int_enable"}, /* flag_watchdog_reset_int_enable , */\
- { 0x26e0, "flag_enbl_amp_int_enable"}, /* flag_enbl_amp_int_enable , */\
- { 0x26f0, "flag_enbl_ref_int_enable"}, /* flag_enbl_ref_int_enable , */\
- { 0x2700, "flag_voutcomp_int_enable"}, /* flag_voutcomp_int_enable , */\
- { 0x2710, "flag_voutcomp93_int_enable"}, /* flag_voutcomp93_int_enable , */\
- { 0x2720, "flag_voutcomp86_int_enable"}, /* flag_voutcomp86_int_enable , */\
- { 0x2730, "flag_hiz_int_enable"}, /* flag_hiz_int_enable , */\
- { 0x2740, "flag_ocpokbst_int_enable"}, /* flag_ocpokbst_int_enable , */\
- { 0x2750, "flag_peakcur_int_enable"}, /* flag_peakcur_int_enable , */\
- { 0x2760, "flag_ocpokap_int_enable"}, /* flag_ocpokap_int_enable , */\
- { 0x2770, "flag_ocpokan_int_enable"}, /* flag_ocpokan_int_enable , */\
- { 0x2780, "flag_ocpokbp_int_enable"}, /* flag_ocpokbp_int_enable , */\
- { 0x2790, "flag_ocpokbn_int_enable"}, /* flag_ocpokbn_int_enable , */\
- { 0x27a0, "flag_adc10_ready_int_enable"}, /* flag_adc10_ready_int_enable , */\
- { 0x27b0, "flag_clipa_high_int_enable"}, /* flag_clipa_high_int_enable , */\
- { 0x27c0, "flag_clipa_low_int_enable"}, /* flag_clipa_low_int_enable , */\
- { 0x27d0, "flag_clipb_high_int_enable"}, /* flag_clipb_high_int_enable , */\
- { 0x27e0, "flag_clipb_low_int_enable"}, /* flag_clipb_low_int_enable , */\
- { 0x27f0, "flag_tdm_error_int_enable"}, /* flag_tdm_error_int_enable , */\
- { 0x2800, "flag_cfma_err_int_enable"}, /* flag_cfma_err_int_enable , */\
- { 0x2810, "flag_cfma_ack_int_enable"}, /* flag_cfma_ack_int_enable , */\
- { 0x2900, "flag_por_int_pol"}, /* flag_por_int_pol , */\
- { 0x2910, "flag_pll_lock_int_pol"}, /* flag_pll_lock_int_pol , */\
- { 0x2920, "flag_otpok_int_pol"}, /* flag_otpok_int_pol , */\
- { 0x2930, "flag_ovpok_int_pol"}, /* flag_ovpok_int_pol , */\
- { 0x2940, "flag_uvpok_int_pol"}, /* flag_uvpok_int_pol , */\
- { 0x2950, "flag_ocp_alarm_int_pol"}, /* flag_ocp_alarm_int_pol , */\
- { 0x2960, "flag_clocks_stable_int_pol"}, /* flag_clocks_stable_int_pol , */\
- { 0x2970, "flag_clip_int_pol"}, /* flag_clip_int_pol , */\
- { 0x2980, "mtp_busy_int_pol"}, /* mtp_busy_int_pol , */\
- { 0x2990, "flag_lost_clk_int_pol"}, /* flag_lost_clk_int_pol , */\
- { 0x29a0, "flag_cf_speakererror_int_pol"}, /* flag_cf_speakererror_int_pol , */\
- { 0x29b0, "flag_cold_started_int_pol"}, /* flag_cold_started_int_pol , */\
- { 0x29c0, "flag_engage_int_pol"}, /* flag_engage_int_pol , */\
- { 0x29d0, "flag_watchdog_reset_int_pol"}, /* flag_watchdog_reset_int_pol , */\
- { 0x29e0, "flag_enbl_amp_int_pol"}, /* flag_enbl_amp_int_pol , */\
- { 0x29f0, "flag_enbl_ref_int_pol"}, /* flag_enbl_ref_int_pol , */\
- { 0x2a00, "flag_voutcomp_int_pol"}, /* flag_voutcomp_int_pol , */\
- { 0x2a10, "flag_voutcomp93_int_pol"}, /* flag_voutcomp93_int_pol , */\
- { 0x2a20, "flag_voutcomp86_int_pol"}, /* flag_voutcomp86_int_pol , */\
- { 0x2a30, "flag_hiz_int_pol"}, /* flag_hiz_int_pol , */\
- { 0x2a40, "flag_ocpokbst_int_pol"}, /* flag_ocpokbst_int_pol , */\
- { 0x2a50, "flag_peakcur_int_pol"}, /* flag_peakcur_int_pol , */\
- { 0x2a60, "flag_ocpokap_int_pol"}, /* flag_ocpokap_int_pol , */\
- { 0x2a70, "flag_ocpokan_int_pol"}, /* flag_ocpokan_int_pol , */\
- { 0x2a80, "flag_ocpokbp_int_pol"}, /* flag_ocpokbp_int_pol , */\
- { 0x2a90, "flag_ocpokbn_int_pol"}, /* flag_ocpokbn_int_pol , */\
- { 0x2aa0, "flag_adc10_ready_int_pol"}, /* flag_adc10_ready_int_pol , */\
- { 0x2ab0, "flag_clipa_high_int_pol"}, /* flag_clipa_high_int_pol , */\
- { 0x2ac0, "flag_clipa_low_int_pol"}, /* flag_clipa_low_int_pol , */\
- { 0x2ad0, "flag_clipb_high_int_pol"}, /* flag_clipb_high_int_pol , */\
- { 0x2ae0, "flag_clipb_low_int_pol"}, /* flag_clipb_low_int_pol , */\
- { 0x2af0, "flag_tdm_error_int_pol"}, /* flag_tdm_error_int_pol , */\
- { 0x2b00, "flag_cfma_err_int_pol"}, /* flag_cfma_err_int_pol , */\
- { 0x2b10, "flag_cfma_ack_int_pol"}, /* flag_cfma_ack_int_pol , */\
- { 0x3000, "flag_voutcomp"}, /* Status flag_voutcomp, indication Vset is larger than Vbat, */\
- { 0x3010, "flag_voutcomp93"}, /* Status flag_voutcomp93, indication Vset is larger than 1.07 x Vbat, */\
- { 0x3020, "flag_voutcomp86"}, /* Status flag voutcomp86, indication Vset is larger than 1.14 x Vbat, */\
- { 0x3030, "flag_hiz"}, /* Status flag_hiz, indication Vbst is larger than Vbat, */\
- { 0x3040, "flag_ocpokbst"}, /* Status flag_ocpokbst, indication no over current in boost converter PMOS switch, */\
- { 0x3050, "flag_peakcur"}, /* Status flag_peakcur, indication current is max in dcdc converter, */\
- { 0x3060, "flag_ocpokap"}, /* Status flag_ocpokap, indication no over current in amplifier A PMOS output stage, */\
- { 0x3070, "flag_ocpokan"}, /* Status flag_ocpokan, indication no over current in amplifier A NMOS output stage, */\
- { 0x3080, "flag_ocpokbp"}, /* Status flag_ocpokbp, indication no over current in amplifier B PMOS output stage, */\
- { 0x3090, "flag_ocpokbn"}, /* Status flag_ocpokbn, indication no over current in amplifier B NMOS output stage, */\
- { 0x30a0, "flag_adc10_ready"}, /* Status flag_adc10_ready, indication adc10 is ready, */\
- { 0x30b0, "flag_clipa_high"}, /* Status flag_clipa_high, indication pmos amplifier A is clipping, */\
- { 0x30c0, "flag_clipa_low"}, /* Status flag_clipa_low, indication nmos amplifier A is clipping, */\
- { 0x30d0, "flag_clipb_high"}, /* Status flag_clipb_high, indication pmos amplifier B is clipping, */\
- { 0x30e0, "flag_clipb_low"}, /* Status flag_clipb_low, indication nmos amplifier B is clipping, */\
- { 0x310f, "mtp_man_data_out"}, /* MTP manual read out data , */\
- { 0x3200, "key01_locked"}, /* Indicates KEY1 is locked , */\
- { 0x3210, "key02_locked"}, /* Indicates KEY2 is locked , */\
- { 0x3225, "mtp_ecc_tcout"}, /* MTP error correction test data out , */\
- { 0x3280, "mtpctrl_valid_test_rd"}, /* MTP test readout for read , */\
- { 0x3290, "mtpctrl_valid_test_wr"}, /* MTP test readout for write , */\
- { 0x32a0, "flag_in_alarm_state"}, /* Flag alarm state , */\
- { 0x32b0, "mtp_ecc_err2"}, /* Two or more bit errors detected in MTP, can not reconstruct value, */\
- { 0x32c0, "mtp_ecc_err1"}, /* One bit error detected in MTP, reconstructed value, */\
- { 0x32d0, "mtp_mtp_hvf"}, /* High voltage ready flag for MTP , */\
- { 0x32f0, "mtp_zero_check_fail"}, /* Zero check failed for MTP , */\
- { 0x3309, "data_adc10_tempbat"}, /* ADC10 data output for testing battery voltage and temperature, */\
- { 0x400f, "hid_code"}, /* 5A6Bh, 23147d to access hidden registers (default for engineering), */\
- { 0x4100, "bypass_hp"}, /* Bypass High Pass Filter , */\
- { 0x4110, "hard_mute"}, /* Hard Mute , */\
- { 0x4120, "soft_mute"}, /* Soft Mute , */\
- { 0x4134, "pwm_delay"}, /* PWM delay setting , */\
- { 0x4180, "pwm_shape"}, /* PWM Shape , */\
- { 0x4190, "pwm_bitlength"}, /* PWM Bitlength in noise shaper , */\
- { 0x4203, "drive"}, /* Drive bits to select number of amplifier power stages, */\
- { 0x4240, "reclock_pwm"}, /* Control for enabling reclocking of PWM signal , */\
- { 0x4250, "reclock_voltsense"}, /* Control for enabling reclocking of voltage sense signal, */\
- { 0x4281, "dpsalevel"}, /* DPSA threshold level , */\
- { 0x42a1, "dpsa_release"}, /* DPSA release time , */\
- { 0x42c0, "coincidence"}, /* Prevent simultaneously switching of output stage , */\
- { 0x42d0, "kickback"}, /* Prevent double pulses of output stage , */\
- { 0x4306, "drivebst"}, /* Drive bits to select the power transistor sections boost converter, */\
- { 0x4370, "boost_alg"}, /* Control for boost adaptive loop gain , */\
- { 0x4381, "boost_loopgain"}, /* DCDC boost loopgain setting , */\
- { 0x43a0, "ocptestbst"}, /* Boost OCP. For old ocp (ctrl_reversebst is 0); For new ocp (ctrl_reversebst is 1), */\
- { 0x43d0, "test_abistfft_enbl"}, /* FFT Coolflux , */\
- { 0x43e0, "bst_dcmbst"}, /* DCM mode control for DCDC during I2C direct control mode, */\
- { 0x43f0, "test_bcontrol"}, /* test_bcontrol , */\
- { 0x4400, "reversebst"}, /* OverCurrent Protection selection of power stage boost converter, */\
- { 0x4410, "sensetest"}, /* Test option for the sense NMOS in booster for current mode control., */\
- { 0x4420, "enbl_engagebst"}, /* Enable power stage of dcdc controller , */\
- { 0x4470, "enbl_slopecur"}, /* Enable bit of max-current dac , */\
- { 0x4480, "enbl_voutcomp"}, /* Enable vout comparators , */\
- { 0x4490, "enbl_voutcomp93"}, /* Enable vout-93 comparators , */\
- { 0x44a0, "enbl_voutcomp86"}, /* Enable vout-86 comparators , */\
- { 0x44b0, "enbl_hizcom"}, /* Enable hiz comparator , */\
- { 0x44c0, "enbl_peakcur"}, /* Enable peak current , */\
- { 0x44d0, "bypass_ovpglitch"}, /* Bypass OVP Glitch Filter , */\
- { 0x44e0, "enbl_windac"}, /* Enable window dac , */\
- { 0x44f0, "enbl_powerbst"}, /* Enable line of the powerstage , */\
- { 0x4507, "ocp_thr"}, /* OCP threshold level , */\
- { 0x4580, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
- { 0x4590, "bypass_ovp"}, /* Bypass OVP , */\
- { 0x45a0, "bypass_uvp"}, /* Bypass UVP , */\
- { 0x45b0, "bypass_otp"}, /* Bypass OTP , */\
- { 0x45d0, "bypass_ocpcounter"}, /* Bypass OCP counter , */\
- { 0x45e0, "bypass_lost_clk"}, /* Bypass lost clock detector , */\
- { 0x45f0, "vpalarm"}, /* vpalarm (UVP/OUP handling) , */\
- { 0x4600, "bypass_gc"}, /* Bypasses the CS gain correction , */\
- { 0x4610, "cs_gain_control"}, /* Current sense gain control , */\
- { 0x4627, "cs_gain"}, /* Current sense gain , */\
- { 0x46a0, "bypass_lp"}, /* Bypass the low power filter inside temperature sensor, */\
- { 0x46b0, "bypass_pwmcounter"}, /* Bypass PWM Counter , */\
- { 0x46c0, "cs_negfixed"}, /* Current sense does not switch to neg , */\
- { 0x46d2, "cs_neghyst"}, /* Current sense switches to neg depending on hyseteris level, */\
- { 0x4700, "switch_fb"}, /* Current sense control switch_fb , */\
- { 0x4713, "se_hyst"}, /* Current sense control se_hyst , */\
- { 0x4754, "se_level"}, /* Current sense control se_level , */\
- { 0x47a5, "ktemp"}, /* Current sense control temperature compensation trimming, */\
- { 0x4800, "cs_negin"}, /* Current sense control negin , */\
- { 0x4810, "cs_sein"}, /* Current sense control cs_sein , */\
- { 0x4820, "cs_coincidence"}, /* Coincidence current sense , */\
- { 0x4830, "iddqtestbst"}, /* IDDQ testing in powerstage of DCDC boost converter, */\
- { 0x4840, "coincidencebst"}, /* Switch protection on to prevent simultaneously switching power stages bst and amp, */\
- { 0x4876, "delay_se_neg"}, /* delay of se and neg , */\
- { 0x48e1, "cs_ttrack"}, /* Sample and hold track time , */\
- { 0x4900, "bypass_clip"}, /* Bypass clip control , */\
- { 0x4920, "cf_cgate_off"}, /* Disable clock gating in the coolflux , */\
- { 0x4940, "clipfast"}, /* Clock selection for HW clipper for battery safeguard, */\
- { 0x4950, "cs_8ohm"}, /* 8 ohm mode for current sense (gain mode) , */\
- { 0x4974, "delay_clock_sh"}, /* delay_sh, tunes S7H delay , */\
- { 0x49c0, "inv_clksh"}, /* Invert the sample/hold clock for current sense ADC, */\
- { 0x49d0, "inv_neg"}, /* Invert neg signal , */\
- { 0x49e0, "inv_se"}, /* Invert se signal , */\
- { 0x49f0, "setse"}, /* Switches between Single Ended and differential mode; 1 is single ended, */\
- { 0x4a12, "adc10_sel"}, /* Select the input to convert the 10b ADC , */\
- { 0x4a60, "adc10_reset"}, /* Reset for ADC10 - I2C direct control mode , */\
- { 0x4a81, "adc10_test"}, /* Test mode selection signal for ADC10 - I2C direct control mode, */\
- { 0x4aa0, "bypass_lp_vbat"}, /* LP filter in batt sensor , */\
- { 0x4ae0, "dc_offset"}, /* Current sense decimator offset control , */\
- { 0x4af0, "tsense_hibias"}, /* Bit to set the biasing in temp sensor to high , */\
- { 0x4b00, "adc13_iset"}, /* MICADC setting of current consumption (debug use only), */\
- { 0x4b14, "adc13_gain"}, /* MICADC gain setting (two's complement format) , */\
- { 0x4b61, "adc13_slowdel"}, /* MICADC delay setting for internal clock (debug use only), */\
- { 0x4b83, "adc13_offset"}, /* MICADC offset setting , */\
- { 0x4bc0, "adc13_bsoinv"}, /* MICADC bit stream output invert mode for test , */\
- { 0x4bd0, "adc13_resonator_enable"}, /* MICADC give extra SNR with less stability (debug use only), */\
- { 0x4be0, "testmicadc"}, /* Mux at input of MICADC for test purpose , */\
- { 0x4c0f, "abist_offset"}, /* Offset control for ABIST testing , */\
- { 0x4d05, "windac"}, /* For testing direct control windac , */\
- { 0x4dc3, "pwm_dcc_cnt"}, /* control pwm duty cycle when enbl_pwm_dcc is 1 , */\
- { 0x4e04, "slopecur"}, /* For testing direct control slopecur , */\
- { 0x4e50, "ctrl_dem"}, /* Dynamic element matching control, rest of codes are optional, */\
- { 0x4ed0, "enbl_pwm_dcc"}, /* Enable direct control of pwm duty cycle , */\
- { 0x4f00, "bst_bypass_bstcur"}, /* Bypass control for boost current settings , */\
- { 0x4f10, "bst_bypass_bstfoldback"}, /* Bypass control for boost foldback , */\
- { 0x4f20, "bst_ctrl_azbst"}, /* Control of auto-zeroing of zero current comparator, */\
- { 0x5007, "gain"}, /* Gain setting of the gain multiplier , */\
- { 0x5081, "sourceb"}, /* PWM OUTB selection control , */\
- { 0x50a1, "sourcea"}, /* PWM OUTA selection control , */\
- { 0x50c1, "sourcebst"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
- { 0x50e0, "tdm_enable_loopback"}, /* TDM loopback test , */\
- { 0x5104, "pulselengthbst"}, /* Pulse length setting test input for boost converter, */\
- { 0x5150, "bypasslatchbst"}, /* Bypass latch in boost converter , */\
- { 0x5160, "invertbst"}, /* Invert pwmbst test signal , */\
- { 0x5174, "pulselength"}, /* Pulse length setting test input for amplifier , */\
- { 0x51c0, "bypasslatch"}, /* Bypass latch in PWM source selection module , */\
- { 0x51d0, "invertb"}, /* invert pwmb test signal , */\
- { 0x51e0, "inverta"}, /* invert pwma test signal , */\
- { 0x51f0, "bypass_ctrlloop"}, /* bypass_ctrlloop bypasses the control loop of the amplifier, */\
- { 0x5210, "test_rdsona"}, /* tbd for rdson testing , */\
- { 0x5220, "test_rdsonb"}, /* tbd for rdson testing , */\
- { 0x5230, "test_rdsonbst"}, /* tbd for rdson testing , */\
- { 0x5240, "test_cvia"}, /* tbd for rdson testing , */\
- { 0x5250, "test_cvib"}, /* tbd for rdson testing , */\
- { 0x5260, "test_cvibst"}, /* tbd for rdson testing , */\
- { 0x5306, "digimuxa_sel"}, /* DigimuxA input selection control (see Digimux list for details), */\
- { 0x5376, "digimuxb_sel"}, /* DigimuxB input selection control (see Digimux list for details), */\
- { 0x5400, "hs_mode"}, /* I2C high speed mode selection control , */\
- { 0x5412, "test_parametric_io"}, /* Control for parametric tests of IO cells , */\
- { 0x5440, "enbl_ringo"}, /* Enable ring oscillator control, for test purpose to check with ringo, */\
- { 0x5456, "digimuxc_sel"}, /* DigimuxC input selection control (see Digimux list for details), */\
- { 0x54c0, "dio_ehs"}, /* Slew control for DIO in output mode , */\
- { 0x54d0, "gainio_ehs"}, /* Slew control for GAINIO in output mode , */\
- { 0x550d, "enbl_amp"}, /* enbl_amp for testing to enable all analoge blocks in amplifier, */\
- { 0x5600, "use_direct_ctrls"}, /* Use direct controls to overrule several functions for testing - I2C direct control mode, */\
- { 0x5610, "rst_datapath"}, /* Reset datapath during direct control mode , */\
- { 0x5620, "rst_cgu"}, /* Reset CGU during durect control mode , */\
- { 0x5637, "enbl_ref"}, /* For testing to enable all analoge blocks in references, */\
- { 0x56b0, "enbl_engage"}, /* Enable output stage amplifier , */\
- { 0x56c0, "use_direct_clk_ctrl"}, /* use_direct_clk_ctrl, to overrule several functions direct for testing, */\
- { 0x56d0, "use_direct_pll_ctrl"}, /* use_direct_pll_ctrl, to overrule several functions direct for testing, */\
- { 0x5707, "anamux"}, /* Anamux control , */\
- { 0x57e0, "otptest"}, /* otptest, test mode otp amplifier , */\
- { 0x57f0, "reverse"}, /* 1b = Normal mode, slope is controlled , */\
- { 0x5813, "pll_selr"}, /* PLL pll_selr , */\
- { 0x5854, "pll_selp"}, /* PLL pll_selp , */\
- { 0x58a5, "pll_seli"}, /* PLL pll_seli , */\
- { 0x5950, "pll_mdec_msb"}, /* Most significant bits of pll_mdec[16] , */\
- { 0x5960, "pll_ndec_msb"}, /* Most significant bits of pll_ndec[9] , */\
- { 0x5970, "pll_frm"}, /* PLL pll_frm , */\
- { 0x5980, "pll_directi"}, /* PLL pll_directi , */\
- { 0x5990, "pll_directo"}, /* PLL pll_directo , */\
- { 0x59a0, "enbl_pll"}, /* PLL enbl_pll , */\
- { 0x59f0, "pll_bypass"}, /* PLL bypass , */\
- { 0x5a0f, "tsig_freq"}, /* Internal sinus test generator frequency control LSB bits, */\
- { 0x5b02, "tsig_freq_msb"}, /* Select internal sine wave generator, frequency control MSB bits, */\
- { 0x5b30, "inject_tsig"}, /* Control bit to switch to internal sinus test generator, */\
- { 0x5b44, "adc10_prog_sample"}, /* ADC10 program sample setting - I2C direct control mode, */\
- { 0x5c0f, "pll_mdec"}, /* PLL MDEC - I2C direct PLL control mode only , */\
- { 0x5d06, "pll_pdec"}, /* PLL PDEC - I2C direct PLL control mode only , */\
- { 0x5d78, "pll_ndec"}, /* PLL NDEC - I2C direct PLL control mode only , */\
- { 0x6007, "mtpkey1"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
- { 0x6185, "mtp_ecc_tcin"}, /* MTP ECC TCIN data , */\
- { 0x6203, "mtp_man_address_in"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
- { 0x6260, "mtp_ecc_eeb"}, /* Enable code bit generation (active low!) , */\
- { 0x6270, "mtp_ecc_ecb"}, /* Enable correction signal (active low!) , */\
- { 0x6280, "man_copy_mtp_to_iic"}, /* Start copying single word from mtp to I2C mtp register, */\
- { 0x6290, "man_copy_iic_to_mtp"}, /* Start copying single word from I2C mtp register to mtp, */\
- { 0x62a0, "auto_copy_mtp_to_iic"}, /* Start copying all the data from mtp to I2C mtp registers, */\
- { 0x62b0, "auto_copy_iic_to_mtp"}, /* Start copying data from I2C mtp registers to mtp , */\
- { 0x62d2, "mtp_speed_mode"}, /* MTP speed mode , */\
- { 0x6340, "mtp_direct_enable"}, /* mtp_direct_enable , */\
- { 0x6350, "mtp_direct_wr"}, /* mtp_direct_wr , */\
- { 0x6360, "mtp_direct_rd"}, /* mtp_direct_rd , */\
- { 0x6370, "mtp_direct_rst"}, /* mtp_direct_rst , */\
- { 0x6380, "mtp_direct_ers"}, /* mtp_direct_ers , */\
- { 0x6390, "mtp_direct_prg"}, /* mtp_direct_prg , */\
- { 0x63a0, "mtp_direct_epp"}, /* mtp_direct_epp , */\
- { 0x63b4, "mtp_direct_test"}, /* mtp_direct_test , */\
- { 0x640f, "mtp_man_data_in"}, /* Write data for MTP manual write , */\
- { 0x7000, "cf_rst_dsp"}, /* Reset CoolFlux DSP , */\
- { 0x7011, "cf_dmem"}, /* Target memory for access , */\
- { 0x7030, "cf_aif"}, /* Auto increment flag for memory-address , */\
- { 0x7040, "cf_int"}, /* CF Interrupt - auto clear , */\
- { 0x7087, "cf_req"}, /* CF request for accessing the 8 channels , */\
- { 0x710f, "cf_madd"}, /* Memory address , */\
- { 0x720f, "cf_mema"}, /* Activate memory access , */\
- { 0x7307, "cf_err"}, /* CF error flags , */\
- { 0x7387, "cf_ack"}, /* CF acknowledgement of the requests channels , */\
- { 0x8000, "calibration_onetime"}, /* Calibration schedule selection , */\
- { 0x8010, "calibr_ron_done"}, /* Calibration of RON status bit , */\
- { 0x8105, "calibr_vout_offset"}, /* calibr_vout_offset (DCDCoffset) 2's compliment (key1 protected), */\
- { 0x8163, "calibr_delta_gain"}, /* delta gain for vamp (alpha) 2's compliment (key1 protected), */\
- { 0x81a5, "calibr_offs_amp"}, /* offset for vamp (Ampoffset) 2's compliment (key1 protected), */\
- { 0x8207, "calibr_gain_cs"}, /* gain current sense (Imeasalpha) 2's compliment (key1 protected), */\
- { 0x8284, "calibr_temp_offset"}, /* temperature offset 2's compliment (key1 protected), */\
- { 0x82d2, "calibr_temp_gain"}, /* temperature gain 2's compliment (key1 protected) , */\
- { 0x830f, "calibr_ron"}, /* calibration value of the RON resistance of the coil, */\
- { 0x8505, "type_bits_hw"}, /* bit0 = disable function dcdcoff_mode ($09[7]) , */\
- { 0x8601, "type_bits_1_0_sw"}, /* MTP control SW , */\
- { 0x8681, "type_bits_9_8_sw"}, /* MTP control SW , */\
- { 0x870f, "type_bits2_sw"}, /* MTP-control SW2 , */\
- { 0x8806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
- { 0x8870, "htol_iic_addr_en"}, /* HTOL I2C_Address_Enable , */\
- { 0x8881, "ctrl_ovp_response"}, /* OVP response control , */\
- { 0x88a0, "disable_ovp_alarm_state"}, /* OVP alarm state control , */\
- { 0x88b0, "enbl_stretch_ovp"}, /* OVP alram strech control , */\
- { 0x88c0, "cf_debug_mode"}, /* Coolflux debug mode , */\
- { 0x8a0f, "production_data1"}, /* production_data1 , */\
- { 0x8b0f, "production_data2"}, /* production_data2 , */\
- { 0x8c0f, "production_data3"}, /* production_data3 , */\
- { 0x8d0f, "production_data4"}, /* production_data4 , */\
- { 0x8e0f, "production_data5"}, /* production_data5 , */\
- { 0x8f0f, "production_data6"}, /* production_data6 , */\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-
-enum TFA9896_irq {
- TFA9896_irq_vdds = 0,
- TFA9896_irq_plls = 1,
- TFA9896_irq_ds = 2,
- TFA9896_irq_vds = 3,
- TFA9896_irq_uvds = 4,
- TFA9896_irq_cds = 5,
- TFA9896_irq_clks = 6,
- TFA9896_irq_clips = 7,
- TFA9896_irq_mtpb = 8,
- TFA9896_irq_clk = 9,
- TFA9896_irq_spks = 10,
- TFA9896_irq_acs = 11,
- TFA9896_irq_sws = 12,
- TFA9896_irq_wds = 13,
- TFA9896_irq_amps = 14,
- TFA9896_irq_arefs = 15,
- TFA9896_irq_err = 32,
- TFA9896_irq_ack = 33,
- TFA9896_irq_max = 34,
- TFA9896_irq_all = -1 /* all irqs */};
-
-#define TFA9896_IRQ_NAMETABLE static tfaIrqName_t TFA9896IrqNames[]= {\
- { 0, "VDDS"},\
- { 1, "PLLS"},\
- { 2, "DS"},\
- { 3, "VDS"},\
- { 4, "UVDS"},\
- { 5, "CDS"},\
- { 6, "CLKS"},\
- { 7, "CLIPS"},\
- { 8, "MTPB"},\
- { 9, "CLK"},\
- { 10, "SPKS"},\
- { 11, "ACS"},\
- { 12, "SWS"},\
- { 13, "WDS"},\
- { 14, "AMPS"},\
- { 15, "AREFS"},\
- { 16, "16"},\
- { 17, "17"},\
- { 18, "18"},\
- { 19, "19"},\
- { 20, "20"},\
- { 21, "21"},\
- { 22, "22"},\
- { 23, "23"},\
- { 24, "24"},\
- { 25, "25"},\
- { 26, "26"},\
- { 27, "27"},\
- { 28, "28"},\
- { 29, "29"},\
- { 30, "30"},\
- { 31, "31"},\
- { 32, "ERR"},\
- { 33, "ACK"},\
- { 34, "34"},\
-};
-#endif /* _TFA9896_TFAFIELDNAMES_H */
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _TFA9896_TFAFIELDNAMES_H
+#define _TFA9896_TFAFIELDNAMES_H
+
+
+#define TFA9896_I2CVERSION 16
+
+typedef enum nxpTFA9896BfEnumList {
+ TFA9896_BF_VDDS = 0x0000, /*!< Power-on-reset flag (auto clear by reading) */
+ TFA9896_BF_PLLS = 0x0010, /*!< PLL lock to programmed frequency */
+ TFA9896_BF_OTDS = 0x0020, /*!< Over Temperature Protection alarm */
+ TFA9896_BF_OVDS = 0x0030, /*!< Over Voltage Protection alarm */
+ TFA9896_BF_UVDS = 0x0040, /*!< Under Voltage Protection alarm */
+ TFA9896_BF_OCDS = 0x0050, /*!< Over Current Protection alarm */
+ TFA9896_BF_CLKS = 0x0060, /*!< Clocks stable flag */
+ TFA9896_BF_CLIPS = 0x0070, /*!< Amplifier clipping */
+ TFA9896_BF_MTPB = 0x0080, /*!< MTP busy copying data to/from I2C registers */
+ TFA9896_BF_NOCLK = 0x0090, /*!< lost clock detection (reference input clock) */
+ TFA9896_BF_SPKS = 0x00a0, /*!< Speaker error */
+ TFA9896_BF_ACS = 0x00b0, /*!< Cold Start required */
+ TFA9896_BF_SWS = 0x00c0, /*!< Amplifier engage (Amp Switching) */
+ TFA9896_BF_WDS = 0x00d0, /*!< watchdog reset (activates reset) */
+ TFA9896_BF_AMPS = 0x00e0, /*!< Amplifier is enabled by manager */
+ TFA9896_BF_AREFS = 0x00f0, /*!< References are enabled by manager */
+ TFA9896_BF_BATS = 0x0109, /*!< Battery voltage from ADC readout */
+ TFA9896_BF_TEMPS = 0x0208, /*!< Temperature readout from the temperature sensor ( C) */
+ TFA9896_BF_REV = 0x030f, /*!< Device revision information */
+ TFA9896_BF_RCV = 0x0420, /*!< Enable receiver mode */
+ TFA9896_BF_CHS12 = 0x0431, /*!< Channel Selection TDM input for Coolflux */
+ TFA9896_BF_INPLVL = 0x0450, /*!< Input level selection attenuator ( */
+ TFA9896_BF_CHSA = 0x0461, /*!< Input selection for amplifier */
+ TFA9896_BF_AUDFS = 0x04c3, /*!< Audio sample rate setting */
+ TFA9896_BF_BSSCR = 0x0501, /*!< Batteery protection attack time */
+ TFA9896_BF_BSST = 0x0523, /*!< Battery protection threshold level */
+ TFA9896_BF_BSSRL = 0x0561, /*!< Battery protection maximum reduction */
+ TFA9896_BF_BSSRR = 0x0582, /*!< Battery protection release time */
+ TFA9896_BF_BSSHY = 0x05b1, /*!< Battery Protection Hysteresis */
+ TFA9896_BF_BSSR = 0x05e0, /*!< Battery voltage value for read out (only) */
+ TFA9896_BF_BSSBY = 0x05f0, /*!< Bypass clipper battery protection */
+ TFA9896_BF_DPSA = 0x0600, /*!< Enable dynamic powerstage activation (DPSA) */
+ TFA9896_BF_ATTEN = 0x0613, /*!< Gain attenuation setting */
+ TFA9896_BF_CFSM = 0x0650, /*!< Soft mute in CoolFlux */
+ TFA9896_BF_BSSS = 0x0670, /*!< Battery sense steepness */
+ TFA9896_BF_VOL = 0x0687, /*!< Coolflux volume control */
+ TFA9896_BF_DCVO2 = 0x0702, /*!< Second Boost Voltage */
+ TFA9896_BF_DCMCC = 0x0733, /*!< Max boost coil current - step of 175 mA */
+ TFA9896_BF_DCVO1 = 0x0772, /*!< First Boost Voltage */
+ TFA9896_BF_DCIE = 0x07a0, /*!< Adaptive boost mode */
+ TFA9896_BF_DCSR = 0x07b0, /*!< Soft Rampup/down mode for DCDC controller */
+ TFA9896_BF_DCPAVG = 0x07c0, /*!< ctrl_peak2avg for analog part of DCDC */
+ TFA9896_BF_DCPWM = 0x07d0, /*!< DCDC PWM only mode */
+ TFA9896_BF_TROS = 0x0800, /*!< Selection ambient temperature for speaker calibration */
+ TFA9896_BF_EXTTS = 0x0818, /*!< External temperature for speaker calibration (C) */
+ TFA9896_BF_PWDN = 0x0900, /*!< powerdown selection */
+ TFA9896_BF_I2CR = 0x0910, /*!< All I2C registers reset to default */
+ TFA9896_BF_CFE = 0x0920, /*!< Enable CoolFlux */
+ TFA9896_BF_AMPE = 0x0930, /*!< Enable Amplifier */
+ TFA9896_BF_DCA = 0x0940, /*!< Enable DCDC Boost converter */
+ TFA9896_BF_SBSL = 0x0950, /*!< Coolflux configured */
+ TFA9896_BF_AMPC = 0x0960, /*!< Selection if Coolflux enables amplifier */
+ TFA9896_BF_DCDIS = 0x0970, /*!< DCDC boost converter not connected */
+ TFA9896_BF_PSDR = 0x0980, /*!< IDDQ amplifier test selection */
+ TFA9896_BF_INTPAD = 0x09c1, /*!< INT pad (interrupt bump output) configuration */
+ TFA9896_BF_IPLL = 0x09e0, /*!< PLL input reference clock selection */
+ TFA9896_BF_DCTRIP = 0x0a04, /*!< Adaptive boost trip levels (effective only when boost_intel is set to 1) */
+ TFA9896_BF_DCHOLD = 0x0a54, /*!< Hold time for DCDC booster (effective only when boost_intel is set to 1) */
+ TFA9896_BF_MTPK = 0x0b07, /*!< KEY2 to access key2 protected registers (default for engineering) */
+ TFA9896_BF_CVFDLY = 0x0c25, /*!< Fractional delay adjustment between current and voltage sense */
+ TFA9896_BF_OPENMTP = 0x0ec0, /*!< Enable programming of the MTP memory */
+ TFA9896_BF_TDMPRF = 0x1011, /*!< TDM usecase selection control */
+ TFA9896_BF_TDMEN = 0x1030, /*!< TDM interface enable */
+ TFA9896_BF_TDMCKINV = 0x1040, /*!< TDM clock inversion, receive on */
+ TFA9896_BF_TDMFSLN = 0x1053, /*!< TDM FS length */
+ TFA9896_BF_TDMFSPOL = 0x1090, /*!< TDM FS polarity (start frame) */
+ TFA9896_BF_TDMSAMSZ = 0x10a4, /*!< TDM sample size for all TDM sinks and sources */
+ TFA9896_BF_TDMSLOTS = 0x1103, /*!< TDM number of slots */
+ TFA9896_BF_TDMSLLN = 0x1144, /*!< TDM slot length */
+ TFA9896_BF_TDMBRMG = 0x1194, /*!< TDM bits remaining after the last slot */
+ TFA9896_BF_TDMDDEL = 0x11e0, /*!< TDM data delay */
+ TFA9896_BF_TDMDADJ = 0x11f0, /*!< TDM data adjustment */
+ TFA9896_BF_TDMTXFRM = 0x1201, /*!< TDM TXDATA format */
+ TFA9896_BF_TDMUUS0 = 0x1221, /*!< TDM TXDATA format unused slot SD0 */
+ TFA9896_BF_TDMUUS1 = 0x1241, /*!< TDM TXDATA format unused slot SD1 */
+ TFA9896_BF_TDMSI0EN = 0x1270, /*!< TDM sink0 enable */
+ TFA9896_BF_TDMSI1EN = 0x1280, /*!< TDM sink1 enable */
+ TFA9896_BF_TDMSI2EN = 0x1290, /*!< TDM sink2 enable */
+ TFA9896_BF_TDMSO0EN = 0x12a0, /*!< TDM source0 enable */
+ TFA9896_BF_TDMSO1EN = 0x12b0, /*!< TDM source1 enable */
+ TFA9896_BF_TDMSO2EN = 0x12c0, /*!< TDM source2 enable */
+ TFA9896_BF_TDMSI0IO = 0x12d0, /*!< TDM sink0 IO selection */
+ TFA9896_BF_TDMSI1IO = 0x12e0, /*!< TDM sink1 IO selection */
+ TFA9896_BF_TDMSI2IO = 0x12f0, /*!< TDM sink2 IO selection */
+ TFA9896_BF_TDMSO0IO = 0x1300, /*!< TDM source0 IO selection */
+ TFA9896_BF_TDMSO1IO = 0x1310, /*!< TDM source1 IO selection */
+ TFA9896_BF_TDMSO2IO = 0x1320, /*!< TDM source2 IO selection */
+ TFA9896_BF_TDMSI0SL = 0x1333, /*!< TDM sink0 slot position [GAIN IN] */
+ TFA9896_BF_TDMSI1SL = 0x1373, /*!< TDM sink1 slot position [CH1 IN] */
+ TFA9896_BF_TDMSI2SL = 0x13b3, /*!< TDM sink2 slot position [CH2 IN] */
+ TFA9896_BF_TDMSO0SL = 0x1403, /*!< TDM source0 slot position [GAIN OUT] */
+ TFA9896_BF_TDMSO1SL = 0x1443, /*!< TDM source1 slot position [Voltage Sense] */
+ TFA9896_BF_TDMSO2SL = 0x1483, /*!< TDM source2 slot position [Current Sense] */
+ TFA9896_BF_NBCK = 0x14c3, /*!< TDM NBCK bit clock ratio */
+ TFA9896_BF_INTOVDDS = 0x2000, /*!< flag_por_int_out */
+ TFA9896_BF_INTOPLLS = 0x2010, /*!< flag_pll_lock_int_out */
+ TFA9896_BF_INTOOTDS = 0x2020, /*!< flag_otpok_int_out */
+ TFA9896_BF_INTOOVDS = 0x2030, /*!< flag_ovpok_int_out */
+ TFA9896_BF_INTOUVDS = 0x2040, /*!< flag_uvpok_int_out */
+ TFA9896_BF_INTOOCDS = 0x2050, /*!< flag_ocp_alarm_int_out */
+ TFA9896_BF_INTOCLKS = 0x2060, /*!< flag_clocks_stable_int_out */
+ TFA9896_BF_INTOCLIPS = 0x2070, /*!< flag_clip_int_out */
+ TFA9896_BF_INTOMTPB = 0x2080, /*!< mtp_busy_int_out */
+ TFA9896_BF_INTONOCLK = 0x2090, /*!< flag_lost_clk_int_out */
+ TFA9896_BF_INTOSPKS = 0x20a0, /*!< flag_cf_speakererror_int_out */
+ TFA9896_BF_INTOACS = 0x20b0, /*!< flag_cold_started_int_out */
+ TFA9896_BF_INTOSWS = 0x20c0, /*!< flag_engage_int_out */
+ TFA9896_BF_INTOWDS = 0x20d0, /*!< flag_watchdog_reset_int_out */
+ TFA9896_BF_INTOAMPS = 0x20e0, /*!< flag_enbl_amp_int_out */
+ TFA9896_BF_INTOAREFS = 0x20f0, /*!< flag_enbl_ref_int_out */
+ TFA9896_BF_INTOERR = 0x2200, /*!< flag_cfma_err_int_out */
+ TFA9896_BF_INTOACK = 0x2210, /*!< flag_cfma_ack_int_out */
+ TFA9896_BF_INTIVDDS = 0x2300, /*!< flag_por_int_in */
+ TFA9896_BF_INTIPLLS = 0x2310, /*!< flag_pll_lock_int_in */
+ TFA9896_BF_INTIOTDS = 0x2320, /*!< flag_otpok_int_in */
+ TFA9896_BF_INTIOVDS = 0x2330, /*!< flag_ovpok_int_in */
+ TFA9896_BF_INTIUVDS = 0x2340, /*!< flag_uvpok_int_in */
+ TFA9896_BF_INTIOCDS = 0x2350, /*!< flag_ocp_alarm_int_in */
+ TFA9896_BF_INTICLKS = 0x2360, /*!< flag_clocks_stable_int_in */
+ TFA9896_BF_INTICLIPS = 0x2370, /*!< flag_clip_int_in */
+ TFA9896_BF_INTIMTPB = 0x2380, /*!< mtp_busy_int_in */
+ TFA9896_BF_INTINOCLK = 0x2390, /*!< flag_lost_clk_int_in */
+ TFA9896_BF_INTISPKS = 0x23a0, /*!< flag_cf_speakererror_int_in */
+ TFA9896_BF_INTIACS = 0x23b0, /*!< flag_cold_started_int_in */
+ TFA9896_BF_INTISWS = 0x23c0, /*!< flag_engage_int_in */
+ TFA9896_BF_INTIWDS = 0x23d0, /*!< flag_watchdog_reset_int_in */
+ TFA9896_BF_INTIAMPS = 0x23e0, /*!< flag_enbl_amp_int_in */
+ TFA9896_BF_INTIAREFS = 0x23f0, /*!< flag_enbl_ref_int_in */
+ TFA9896_BF_INTIERR = 0x2500, /*!< flag_cfma_err_int_in */
+ TFA9896_BF_INTIACK = 0x2510, /*!< flag_cfma_ack_int_in */
+ TFA9896_BF_INTENVDDS = 0x2600, /*!< flag_por_int_enable */
+ TFA9896_BF_INTENPLLS = 0x2610, /*!< flag_pll_lock_int_enable */
+ TFA9896_BF_INTENOTDS = 0x2620, /*!< flag_otpok_int_enable */
+ TFA9896_BF_INTENOVDS = 0x2630, /*!< flag_ovpok_int_enable */
+ TFA9896_BF_INTENUVDS = 0x2640, /*!< flag_uvpok_int_enable */
+ TFA9896_BF_INTENOCDS = 0x2650, /*!< flag_ocp_alarm_int_enable */
+ TFA9896_BF_INTENCLKS = 0x2660, /*!< flag_clocks_stable_int_enable */
+ TFA9896_BF_INTENCLIPS = 0x2670, /*!< flag_clip_int_enable */
+ TFA9896_BF_INTENMTPB = 0x2680, /*!< mtp_busy_int_enable */
+ TFA9896_BF_INTENNOCLK = 0x2690, /*!< flag_lost_clk_int_enable */
+ TFA9896_BF_INTENSPKS = 0x26a0, /*!< flag_cf_speakererror_int_enable */
+ TFA9896_BF_INTENACS = 0x26b0, /*!< flag_cold_started_int_enable */
+ TFA9896_BF_INTENSWS = 0x26c0, /*!< flag_engage_int_enable */
+ TFA9896_BF_INTENWDS = 0x26d0, /*!< flag_watchdog_reset_int_enable */
+ TFA9896_BF_INTENAMPS = 0x26e0, /*!< flag_enbl_amp_int_enable */
+ TFA9896_BF_INTENAREFS = 0x26f0, /*!< flag_enbl_ref_int_enable */
+ TFA9896_BF_INTENERR = 0x2800, /*!< flag_cfma_err_int_enable */
+ TFA9896_BF_INTENACK = 0x2810, /*!< flag_cfma_ack_int_enable */
+ TFA9896_BF_INTPOLVDDS = 0x2900, /*!< flag_por_int_pol */
+ TFA9896_BF_INTPOLPLLS = 0x2910, /*!< flag_pll_lock_int_pol */
+ TFA9896_BF_INTPOLOTDS = 0x2920, /*!< flag_otpok_int_pol */
+ TFA9896_BF_INTPOLOVDS = 0x2930, /*!< flag_ovpok_int_pol */
+ TFA9896_BF_INTPOLUVDS = 0x2940, /*!< flag_uvpok_int_pol */
+ TFA9896_BF_INTPOLOCDS = 0x2950, /*!< flag_ocp_alarm_int_pol */
+ TFA9896_BF_INTPOLCLKS = 0x2960, /*!< flag_clocks_stable_int_pol */
+ TFA9896_BF_INTPOLCLIPS = 0x2970, /*!< flag_clip_int_pol */
+ TFA9896_BF_INTPOLMTPB = 0x2980, /*!< mtp_busy_int_pol */
+ TFA9896_BF_INTPOLNOCLK = 0x2990, /*!< flag_lost_clk_int_pol */
+ TFA9896_BF_INTPOLSPKS = 0x29a0, /*!< flag_cf_speakererror_int_pol */
+ TFA9896_BF_INTPOLACS = 0x29b0, /*!< flag_cold_started_int_pol */
+ TFA9896_BF_INTPOLSWS = 0x29c0, /*!< flag_engage_int_pol */
+ TFA9896_BF_INTPOLWDS = 0x29d0, /*!< flag_watchdog_reset_int_pol */
+ TFA9896_BF_INTPOLAMPS = 0x29e0, /*!< flag_enbl_amp_int_pol */
+ TFA9896_BF_INTPOLAREFS = 0x29f0, /*!< flag_enbl_ref_int_pol */
+ TFA9896_BF_INTPOLERR = 0x2b00, /*!< flag_cfma_err_int_pol */
+ TFA9896_BF_INTPOLACK = 0x2b10, /*!< flag_cfma_ack_int_pol */
+ TFA9896_BF_CLIP = 0x4900, /*!< Bypass clip control */
+ TFA9896_BF_CIMTP = 0x62b0, /*!< Start copying data from I2C mtp registers to mtp */
+ TFA9896_BF_RST = 0x7000, /*!< Reset CoolFlux DSP */
+ TFA9896_BF_DMEM = 0x7011, /*!< Target memory for access */
+ TFA9896_BF_AIF = 0x7030, /*!< Auto increment flag for memory-address */
+ TFA9896_BF_CFINT = 0x7040, /*!< CF Interrupt - auto clear */
+ TFA9896_BF_REQ = 0x7087, /*!< CF request for accessing the 8 channels */
+ TFA9896_BF_MADD = 0x710f, /*!< Memory address */
+ TFA9896_BF_MEMA = 0x720f, /*!< Activate memory access */
+ TFA9896_BF_ERR = 0x7307, /*!< CF error flags */
+ TFA9896_BF_ACK = 0x7387, /*!< CF acknowledgement of the requests channels */
+ TFA9896_BF_MTPOTC = 0x8000, /*!< Calibration schedule selection */
+ TFA9896_BF_MTPEX = 0x8010, /*!< Calibration of RON status bit */
+} nxpTFA9896BfEnumList_t;
+#define TFA9896_NAMETABLE static tfaBfName_t Tfa9896DatasheetNames[] = {\
+ { 0x0, "VDDS"}, /* Power-on-reset flag (auto clear by reading) , */\
+ { 0x10, "PLLS"}, /* PLL lock to programmed frequency , */\
+ { 0x20, "OTDS"}, /* Over Temperature Protection alarm , */\
+ { 0x30, "OVDS"}, /* Over Voltage Protection alarm , */\
+ { 0x40, "UVDS"}, /* Under Voltage Protection alarm , */\
+ { 0x50, "OCDS"}, /* Over Current Protection alarm , */\
+ { 0x60, "CLKS"}, /* Clocks stable flag , */\
+ { 0x70, "CLIPS"}, /* Amplifier clipping , */\
+ { 0x80, "MTPB"}, /* MTP busy copying data to/from I2C registers , */\
+ { 0x90, "NOCLK"}, /* lost clock detection (reference input clock) , */\
+ { 0xa0, "SPKS"}, /* Speaker error , */\
+ { 0xb0, "ACS"}, /* Cold Start required , */\
+ { 0xc0, "SWS"}, /* Amplifier engage (Amp Switching) , */\
+ { 0xd0, "WDS"}, /* watchdog reset (activates reset) , */\
+ { 0xe0, "AMPS"}, /* Amplifier is enabled by manager , */\
+ { 0xf0, "AREFS"}, /* References are enabled by manager , */\
+ { 0x109, "BATS"}, /* Battery voltage from ADC readout , */\
+ { 0x208, "TEMPS"}, /* Temperature readout from the temperature sensor ( C), */\
+ { 0x30f, "REV"}, /* Device revision information , */\
+ { 0x420, "RCV"}, /* Enable receiver mode , */\
+ { 0x431, "CHS12"}, /* Channel Selection TDM input for Coolflux , */\
+ { 0x450, "INPLVL"}, /* Input level selection attenuator ( , */\
+ { 0x461, "CHSA"}, /* Input selection for amplifier , */\
+ { 0x4c3, "AUDFS"}, /* Audio sample rate setting , */\
+ { 0x501, "BSSCR"}, /* Batteery protection attack time , */\
+ { 0x523, "BSST"}, /* Battery protection threshold level , */\
+ { 0x561, "BSSRL"}, /* Battery protection maximum reduction , */\
+ { 0x582, "BSSRR"}, /* Battery protection release time , */\
+ { 0x5b1, "BSSHY"}, /* Battery Protection Hysteresis , */\
+ { 0x5e0, "BSSR"}, /* Battery voltage value for read out (only) , */\
+ { 0x5f0, "BSSBY"}, /* Bypass clipper battery protection , */\
+ { 0x600, "DPSA"}, /* Enable dynamic powerstage activation (DPSA) , */\
+ { 0x613, "ATTEN"}, /* Gain attenuation setting , */\
+ { 0x650, "CFSM"}, /* Soft mute in CoolFlux , */\
+ { 0x670, "BSSS"}, /* Battery sense steepness , */\
+ { 0x687, "VOL"}, /* Coolflux volume control , */\
+ { 0x702, "DCVO2"}, /* Second Boost Voltage , */\
+ { 0x733, "DCMCC"}, /* Max boost coil current - step of 175 mA , */\
+ { 0x772, "DCVO1"}, /* First Boost Voltage , */\
+ { 0x7a0, "DCIE"}, /* Adaptive boost mode , */\
+ { 0x7b0, "DCSR"}, /* Soft Rampup/down mode for DCDC controller , */\
+ { 0x7c0, "DCPAVG"}, /* ctrl_peak2avg for analog part of DCDC , */\
+ { 0x7d0, "DCPWM"}, /* DCDC PWM only mode , */\
+ { 0x800, "TROS"}, /* Selection ambient temperature for speaker calibration , */\
+ { 0x818, "EXTTS"}, /* External temperature for speaker calibration (C) , */\
+ { 0x900, "PWDN"}, /* powerdown selection , */\
+ { 0x910, "I2CR"}, /* All I2C registers reset to default , */\
+ { 0x920, "CFE"}, /* Enable CoolFlux , */\
+ { 0x930, "AMPE"}, /* Enable Amplifier , */\
+ { 0x940, "DCA"}, /* Enable DCDC Boost converter , */\
+ { 0x950, "SBSL"}, /* Coolflux configured , */\
+ { 0x960, "AMPC"}, /* Selection if Coolflux enables amplifier , */\
+ { 0x970, "DCDIS"}, /* DCDC boost converter not connected , */\
+ { 0x980, "PSDR"}, /* IDDQ amplifier test selection , */\
+ { 0x9c1, "INTPAD"}, /* INT pad (interrupt bump output) configuration , */\
+ { 0x9e0, "IPLL"}, /* PLL input reference clock selection , */\
+ { 0xa04, "DCTRIP"}, /* Adaptive boost trip levels (effective only when boost_intel is set to 1), */\
+ { 0xa54, "DCHOLD"}, /* Hold time for DCDC booster (effective only when boost_intel is set to 1), */\
+ { 0xb07, "MTPK"}, /* KEY2 to access key2 protected registers (default for engineering), */\
+ { 0xc25, "CVFDLY"}, /* Fractional delay adjustment between current and voltage sense, */\
+ { 0xec0, "OPENMTP"}, /* Enable programming of the MTP memory , */\
+ { 0x1011, "TDMPRF"}, /* TDM usecase selection control , */\
+ { 0x1030, "TDMEN"}, /* TDM interface enable , */\
+ { 0x1040, "TDMCKINV"}, /* TDM clock inversion, receive on , */\
+ { 0x1053, "TDMFSLN"}, /* TDM FS length , */\
+ { 0x1090, "TDMFSPOL"}, /* TDM FS polarity (start frame) , */\
+ { 0x10a4, "TDMSAMSZ"}, /* TDM sample size for all TDM sinks and sources , */\
+ { 0x1103, "TDMSLOTS"}, /* TDM number of slots , */\
+ { 0x1144, "TDMSLLN"}, /* TDM slot length , */\
+ { 0x1194, "TDMBRMG"}, /* TDM bits remaining after the last slot , */\
+ { 0x11e0, "TDMDDEL"}, /* TDM data delay , */\
+ { 0x11f0, "TDMDADJ"}, /* TDM data adjustment , */\
+ { 0x1201, "TDMTXFRM"}, /* TDM TXDATA format , */\
+ { 0x1221, "TDMUUS0"}, /* TDM TXDATA format unused slot SD0 , */\
+ { 0x1241, "TDMUUS1"}, /* TDM TXDATA format unused slot SD1 , */\
+ { 0x1270, "TDMSI0EN"}, /* TDM sink0 enable , */\
+ { 0x1280, "TDMSI1EN"}, /* TDM sink1 enable , */\
+ { 0x1290, "TDMSI2EN"}, /* TDM sink2 enable , */\
+ { 0x12a0, "TDMSO0EN"}, /* TDM source0 enable , */\
+ { 0x12b0, "TDMSO1EN"}, /* TDM source1 enable , */\
+ { 0x12c0, "TDMSO2EN"}, /* TDM source2 enable , */\
+ { 0x12d0, "TDMSI0IO"}, /* TDM sink0 IO selection , */\
+ { 0x12e0, "TDMSI1IO"}, /* TDM sink1 IO selection , */\
+ { 0x12f0, "TDMSI2IO"}, /* TDM sink2 IO selection , */\
+ { 0x1300, "TDMSO0IO"}, /* TDM source0 IO selection , */\
+ { 0x1310, "TDMSO1IO"}, /* TDM source1 IO selection , */\
+ { 0x1320, "TDMSO2IO"}, /* TDM source2 IO selection , */\
+ { 0x1333, "TDMSI0SL"}, /* TDM sink0 slot position [GAIN IN] , */\
+ { 0x1373, "TDMSI1SL"}, /* TDM sink1 slot position [CH1 IN] , */\
+ { 0x13b3, "TDMSI2SL"}, /* TDM sink2 slot position [CH2 IN] , */\
+ { 0x1403, "TDMSO0SL"}, /* TDM source0 slot position [GAIN OUT] , */\
+ { 0x1443, "TDMSO1SL"}, /* TDM source1 slot position [Voltage Sense] , */\
+ { 0x1483, "TDMSO2SL"}, /* TDM source2 slot position [Current Sense] , */\
+ { 0x14c3, "NBCK"}, /* TDM NBCK bit clock ratio , */\
+ { 0x2000, "INTOVDDS"}, /* flag_por_int_out , */\
+ { 0x2010, "INTOPLLS"}, /* flag_pll_lock_int_out , */\
+ { 0x2020, "INTOOTDS"}, /* flag_otpok_int_out , */\
+ { 0x2030, "INTOOVDS"}, /* flag_ovpok_int_out , */\
+ { 0x2040, "INTOUVDS"}, /* flag_uvpok_int_out , */\
+ { 0x2050, "INTOOCDS"}, /* flag_ocp_alarm_int_out , */\
+ { 0x2060, "INTOCLKS"}, /* flag_clocks_stable_int_out , */\
+ { 0x2070, "INTOCLIPS"}, /* flag_clip_int_out , */\
+ { 0x2080, "INTOMTPB"}, /* mtp_busy_int_out , */\
+ { 0x2090, "INTONOCLK"}, /* flag_lost_clk_int_out , */\
+ { 0x20a0, "INTOSPKS"}, /* flag_cf_speakererror_int_out , */\
+ { 0x20b0, "INTOACS"}, /* flag_cold_started_int_out , */\
+ { 0x20c0, "INTOSWS"}, /* flag_engage_int_out , */\
+ { 0x20d0, "INTOWDS"}, /* flag_watchdog_reset_int_out , */\
+ { 0x20e0, "INTOAMPS"}, /* flag_enbl_amp_int_out , */\
+ { 0x20f0, "INTOAREFS"}, /* flag_enbl_ref_int_out , */\
+ { 0x2200, "INTOERR"}, /* flag_cfma_err_int_out , */\
+ { 0x2210, "INTOACK"}, /* flag_cfma_ack_int_out , */\
+ { 0x2300, "INTIVDDS"}, /* flag_por_int_in , */\
+ { 0x2310, "INTIPLLS"}, /* flag_pll_lock_int_in , */\
+ { 0x2320, "INTIOTDS"}, /* flag_otpok_int_in , */\
+ { 0x2330, "INTIOVDS"}, /* flag_ovpok_int_in , */\
+ { 0x2340, "INTIUVDS"}, /* flag_uvpok_int_in , */\
+ { 0x2350, "INTIOCDS"}, /* flag_ocp_alarm_int_in , */\
+ { 0x2360, "INTICLKS"}, /* flag_clocks_stable_int_in , */\
+ { 0x2370, "INTICLIPS"}, /* flag_clip_int_in , */\
+ { 0x2380, "INTIMTPB"}, /* mtp_busy_int_in , */\
+ { 0x2390, "INTINOCLK"}, /* flag_lost_clk_int_in , */\
+ { 0x23a0, "INTISPKS"}, /* flag_cf_speakererror_int_in , */\
+ { 0x23b0, "INTIACS"}, /* flag_cold_started_int_in , */\
+ { 0x23c0, "INTISWS"}, /* flag_engage_int_in , */\
+ { 0x23d0, "INTIWDS"}, /* flag_watchdog_reset_int_in , */\
+ { 0x23e0, "INTIAMPS"}, /* flag_enbl_amp_int_in , */\
+ { 0x23f0, "INTIAREFS"}, /* flag_enbl_ref_int_in , */\
+ { 0x2500, "INTIERR"}, /* flag_cfma_err_int_in , */\
+ { 0x2510, "INTIACK"}, /* flag_cfma_ack_int_in , */\
+ { 0x2600, "INTENVDDS"}, /* flag_por_int_enable , */\
+ { 0x2610, "INTENPLLS"}, /* flag_pll_lock_int_enable , */\
+ { 0x2620, "INTENOTDS"}, /* flag_otpok_int_enable , */\
+ { 0x2630, "INTENOVDS"}, /* flag_ovpok_int_enable , */\
+ { 0x2640, "INTENUVDS"}, /* flag_uvpok_int_enable , */\
+ { 0x2650, "INTENOCDS"}, /* flag_ocp_alarm_int_enable , */\
+ { 0x2660, "INTENCLKS"}, /* flag_clocks_stable_int_enable , */\
+ { 0x2670, "INTENCLIPS"}, /* flag_clip_int_enable , */\
+ { 0x2680, "INTENMTPB"}, /* mtp_busy_int_enable , */\
+ { 0x2690, "INTENNOCLK"}, /* flag_lost_clk_int_enable , */\
+ { 0x26a0, "INTENSPKS"}, /* flag_cf_speakererror_int_enable , */\
+ { 0x26b0, "INTENACS"}, /* flag_cold_started_int_enable , */\
+ { 0x26c0, "INTENSWS"}, /* flag_engage_int_enable , */\
+ { 0x26d0, "INTENWDS"}, /* flag_watchdog_reset_int_enable , */\
+ { 0x26e0, "INTENAMPS"}, /* flag_enbl_amp_int_enable , */\
+ { 0x26f0, "INTENAREFS"}, /* flag_enbl_ref_int_enable , */\
+ { 0x2800, "INTENERR"}, /* flag_cfma_err_int_enable , */\
+ { 0x2810, "INTENACK"}, /* flag_cfma_ack_int_enable , */\
+ { 0x2900, "INTPOLVDDS"}, /* flag_por_int_pol , */\
+ { 0x2910, "INTPOLPLLS"}, /* flag_pll_lock_int_pol , */\
+ { 0x2920, "INTPOLOTDS"}, /* flag_otpok_int_pol , */\
+ { 0x2930, "INTPOLOVDS"}, /* flag_ovpok_int_pol , */\
+ { 0x2940, "INTPOLUVDS"}, /* flag_uvpok_int_pol , */\
+ { 0x2950, "INTPOLOCDS"}, /* flag_ocp_alarm_int_pol , */\
+ { 0x2960, "INTPOLCLKS"}, /* flag_clocks_stable_int_pol , */\
+ { 0x2970, "INTPOLCLIPS"}, /* flag_clip_int_pol , */\
+ { 0x2980, "INTPOLMTPB"}, /* mtp_busy_int_pol , */\
+ { 0x2990, "INTPOLNOCLK"}, /* flag_lost_clk_int_pol , */\
+ { 0x29a0, "INTPOLSPKS"}, /* flag_cf_speakererror_int_pol , */\
+ { 0x29b0, "INTPOLACS"}, /* flag_cold_started_int_pol , */\
+ { 0x29c0, "INTPOLSWS"}, /* flag_engage_int_pol , */\
+ { 0x29d0, "INTPOLWDS"}, /* flag_watchdog_reset_int_pol , */\
+ { 0x29e0, "INTPOLAMPS"}, /* flag_enbl_amp_int_pol , */\
+ { 0x29f0, "INTPOLAREFS"}, /* flag_enbl_ref_int_pol , */\
+ { 0x2b00, "INTPOLERR"}, /* flag_cfma_err_int_pol , */\
+ { 0x2b10, "INTPOLACK"}, /* flag_cfma_ack_int_pol , */\
+ { 0x4900, "CLIP"}, /* Bypass clip control , */\
+ { 0x62b0, "CIMTP"}, /* Start copying data from I2C mtp registers to mtp , */\
+ { 0x7000, "RST"}, /* Reset CoolFlux DSP , */\
+ { 0x7011, "DMEM"}, /* Target memory for access , */\
+ { 0x7030, "AIF"}, /* Auto increment flag for memory-address , */\
+ { 0x7040, "CFINT"}, /* CF Interrupt - auto clear , */\
+ { 0x7087, "REQ"}, /* CF request for accessing the 8 channels , */\
+ { 0x710f, "MADD"}, /* Memory address , */\
+ { 0x720f, "MEMA"}, /* Activate memory access , */\
+ { 0x7307, "ERR"}, /* CF error flags , */\
+ { 0x7387, "ACK"}, /* CF acknowledgement of the requests channels , */\
+ { 0x8000, "MTPOTC"}, /* Calibration schedule selection , */\
+ { 0x8010, "MTPEX"}, /* Calibration of RON status bit , */\
+ { 0x8045, "SWPROFIL" },\
+ { 0x80a5, "SWVSTEP" },\
+ { 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+
+#define TFA9896_BITNAMETABLE static tfaBfName_t Tfa9896BitNames[] = {\
+ { 0x0, "flag_por"}, /* Power-on-reset flag (auto clear by reading) , */\
+ { 0x10, "flag_pll_lock"}, /* PLL lock to programmed frequency , */\
+ { 0x20, "flag_otpok"}, /* Over Temperature Protection alarm , */\
+ { 0x30, "flag_ovpok"}, /* Over Voltage Protection alarm , */\
+ { 0x40, "flag_uvpok"}, /* Under Voltage Protection alarm , */\
+ { 0x50, "flag_ocp_alarm"}, /* Over Current Protection alarm , */\
+ { 0x60, "flag_clocks_stable"}, /* Clocks stable flag , */\
+ { 0x70, "flag_clip"}, /* Amplifier clipping , */\
+ { 0x80, "mtp_busy"}, /* MTP busy copying data to/from I2C registers , */\
+ { 0x90, "flag_lost_clk"}, /* lost clock detection (reference input clock) , */\
+ { 0xa0, "flag_cf_speakererror"}, /* Speaker error , */\
+ { 0xb0, "flag_cold_started"}, /* Cold Start required , */\
+ { 0xc0, "flag_engage"}, /* Amplifier engage (Amp Switching) , */\
+ { 0xd0, "flag_watchdog_reset"}, /* watchdog reset (activates reset) , */\
+ { 0xe0, "flag_enbl_amp"}, /* Amplifier is enabled by manager , */\
+ { 0xf0, "flag_enbl_ref"}, /* References are enabled by manager , */\
+ { 0x109, "bat_adc"}, /* Battery voltage from ADC readout , */\
+ { 0x208, "temp_adc"}, /* Temperature readout from the temperature sensor ( C), */\
+ { 0x30f, "device_rev"}, /* Device revision information , */\
+ { 0x420, "ctrl_rcv"}, /* Enable receiver mode , */\
+ { 0x431, "chan_sel"}, /* Channel Selection TDM input for Coolflux , */\
+ { 0x450, "input_level"}, /* Input level selection attenuator ( , */\
+ { 0x461, "vamp_sel"}, /* Input selection for amplifier , */\
+ { 0x4c3, "audio_fs"}, /* Audio sample rate setting , */\
+ { 0x501, "vbat_prot_attacktime"}, /* Batteery protection attack time , */\
+ { 0x523, "vbat_prot_thlevel"}, /* Battery protection threshold level , */\
+ { 0x561, "vbat_prot_max_reduct"}, /* Battery protection maximum reduction , */\
+ { 0x582, "vbat_prot_release_t"}, /* Battery protection release time , */\
+ { 0x5b1, "vbat_prot_hysterese"}, /* Battery Protection Hysteresis , */\
+ { 0x5d0, "reset_min_vbat"}, /* Battery supply safeguard clipper reset ( if CF_DSP is bypassed), */\
+ { 0x5e0, "sel_vbat"}, /* Battery voltage value for read out (only) , */\
+ { 0x5f0, "bypass_clipper"}, /* Bypass clipper battery protection , */\
+ { 0x600, "dpsa"}, /* Enable dynamic powerstage activation (DPSA) , */\
+ { 0x613, "ctrl_att"}, /* Gain attenuation setting , */\
+ { 0x650, "cf_mute"}, /* Soft mute in CoolFlux , */\
+ { 0x670, "batsense_steepness"}, /* Battery sense steepness , */\
+ { 0x687, "vol"}, /* Coolflux volume control , */\
+ { 0x702, "scnd_boost_voltage"}, /* Second Boost Voltage , */\
+ { 0x733, "boost_cur"}, /* Max boost coil current - step of 175 mA , */\
+ { 0x772, "frst_boost_voltage"}, /* First Boost Voltage , */\
+ { 0x7a0, "boost_intel"}, /* Adaptive boost mode , */\
+ { 0x7b0, "boost_speed"}, /* Soft Rampup/down mode for DCDC controller , */\
+ { 0x7c0, "boost_peak2avg"}, /* ctrl_peak2avg for analog part of DCDC , */\
+ { 0x7d0, "dcdc_pwmonly"}, /* DCDC PWM only mode , */\
+ { 0x7e0, "ignore_flag_voutcomp86"}, /* Ignore flag_voutcomp86 (flag from analog) , */\
+ { 0x800, "ext_temp_sel"}, /* Selection ambient temperature for speaker calibration , */\
+ { 0x818, "ext_temp"}, /* External temperature for speaker calibration (C) , */\
+ { 0x900, "powerdown"}, /* powerdown selection , */\
+ { 0x910, "reset"}, /* All I2C registers reset to default , */\
+ { 0x920, "enbl_coolflux"}, /* Enable CoolFlux , */\
+ { 0x930, "enbl_amplifier"}, /* Enable Amplifier , */\
+ { 0x940, "enbl_boost"}, /* Enable DCDC Boost converter , */\
+ { 0x950, "coolflux_configured"}, /* Coolflux configured , */\
+ { 0x960, "sel_enbl_amplifier"}, /* Selection if Coolflux enables amplifier , */\
+ { 0x970, "dcdcoff_mode"}, /* DCDC boost converter not connected , */\
+ { 0x980, "iddqtest"}, /* IDDQ amplifier test selection , */\
+ { 0x9c1, "int_pad_io"}, /* INT pad (interrupt bump output) configuration , */\
+ { 0x9e0, "sel_fs_bck"}, /* PLL input reference clock selection , */\
+ { 0x9f0, "sel_scl_cf_clock"}, /* Coolflux sub-system clock selection , */\
+ { 0xa04, "boost_trip_lvl"}, /* Adaptive boost trip levels (effective only when boost_intel is set to 1), */\
+ { 0xa54, "boost_hold_time"}, /* Hold time for DCDC booster (effective only when boost_intel is set to 1), */\
+ { 0xaa1, "bst_slpcmplvl"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
+ { 0xb07, "mtpkey2"}, /* KEY2 to access key2 protected registers (default for engineering), */\
+ { 0xc00, "enbl_volt_sense"}, /* Voltage sense enabling control bit , */\
+ { 0xc10, "vsense_pwm_sel"}, /* Voltage sense source selection , */\
+ { 0xc25, "vi_frac_delay"}, /* Fractional delay adjustment between current and voltage sense, */\
+ { 0xc80, "sel_voltsense_out"}, /* TDM output data selection for AEC , */\
+ { 0xc90, "vsense_bypass_avg"}, /* Voltage sense average block bypass , */\
+ { 0xd05, "cf_frac_delay"}, /* Fractional delay adjustment between current and voltage sense by firmware, */\
+ { 0xe00, "bypass_dcdc_curr_prot"}, /* Control to switch off dcdc current reduction with bat protection, */\
+ { 0xe10, "bypass_ocp"}, /* Bypass OCP (digital IP block) , */\
+ { 0xe20, "ocptest"}, /* ocptest (analog IP block) enable , */\
+ { 0xe80, "disable_clock_sh_prot"}, /* Disable clock_sh protection , */\
+ { 0xe92, "reserve_reg_15_09"}, /* Spare control bits for future usage , */\
+ { 0xec0, "unprotect_mtp"}, /* Enable programming of the MTP memory , */\
+ { 0xed2, "reserve_reg_15_13"}, /* Spare control bits for future usage , */\
+ { 0xf00, "dcdc_pfm20khz_limit"}, /* DCDC in PFM mode forcing each 50us a pwm pulse , */\
+ { 0xf11, "dcdc_ctrl_maxzercnt"}, /* DCDC number of zero current flags required to go to pfm mode, */\
+ { 0xf36, "dcdc_vbat_delta_detect"}, /* DCDC threshold required on a delta Vbat (in PFM mode) switching to PWM mode, */\
+ { 0xfa0, "dcdc_ignore_vbat"}, /* Ignore an increase on Vbat , */\
+ { 0x1011, "tdm_usecase"}, /* TDM usecase selection control , */\
+ { 0x1030, "tdm_enable"}, /* TDM interface enable , */\
+ { 0x1040, "tdm_clk_inversion"}, /* TDM clock inversion, receive on , */\
+ { 0x1053, "tdm_fs_ws_length"}, /* TDM FS length , */\
+ { 0x1090, "tdm_fs_ws_polarity"}, /* TDM FS polarity (start frame) , */\
+ { 0x10a4, "tdm_sample_size"}, /* TDM sample size for all TDM sinks and sources , */\
+ { 0x1103, "tdm_nb_of_slots"}, /* TDM number of slots , */\
+ { 0x1144, "tdm_slot_length"}, /* TDM slot length , */\
+ { 0x1194, "tdm_bits_remaining"}, /* TDM bits remaining after the last slot , */\
+ { 0x11e0, "tdm_data_delay"}, /* TDM data delay , */\
+ { 0x11f0, "tdm_data_adjustment"}, /* TDM data adjustment , */\
+ { 0x1201, "tdm_txdata_format"}, /* TDM TXDATA format , */\
+ { 0x1221, "tdm_txdata_format_unused_slot_sd0"}, /* TDM TXDATA format unused slot SD0 , */\
+ { 0x1241, "tdm_txdata_format_unused_slot_sd1"}, /* TDM TXDATA format unused slot SD1 , */\
+ { 0x1270, "tdm_sink0_enable"}, /* TDM sink0 enable , */\
+ { 0x1280, "tdm_sink1_enable"}, /* TDM sink1 enable , */\
+ { 0x1290, "tdm_sink2_enable"}, /* TDM sink2 enable , */\
+ { 0x12a0, "tdm_source0_enable"}, /* TDM source0 enable , */\
+ { 0x12b0, "tdm_source1_enable"}, /* TDM source1 enable , */\
+ { 0x12c0, "tdm_source2_enable"}, /* TDM source2 enable , */\
+ { 0x12d0, "tdm_sink0_io"}, /* TDM sink0 IO selection , */\
+ { 0x12e0, "tdm_sink1_io"}, /* TDM sink1 IO selection , */\
+ { 0x12f0, "tdm_sink2_io"}, /* TDM sink2 IO selection , */\
+ { 0x1300, "tdm_source0_io"}, /* TDM source0 IO selection , */\
+ { 0x1310, "tdm_source1_io"}, /* TDM source1 IO selection , */\
+ { 0x1320, "tdm_source2_io"}, /* TDM source2 IO selection , */\
+ { 0x1333, "tdm_sink0_slot"}, /* TDM sink0 slot position [GAIN IN] , */\
+ { 0x1373, "tdm_sink1_slot"}, /* TDM sink1 slot position [CH1 IN] , */\
+ { 0x13b3, "tdm_sink2_slot"}, /* TDM sink2 slot position [CH2 IN] , */\
+ { 0x1403, "tdm_source0_slot"}, /* TDM source0 slot position [GAIN OUT] , */\
+ { 0x1443, "tdm_source1_slot"}, /* TDM source1 slot position [Voltage Sense] , */\
+ { 0x1483, "tdm_source2_slot"}, /* TDM source2 slot position [Current Sense] , */\
+ { 0x14c3, "tdm_nbck"}, /* TDM NBCK bit clock ratio , */\
+ { 0x1500, "flag_tdm_lut_error"}, /* TDM LUT error flag , */\
+ { 0x1512, "flag_tdm_status"}, /* TDM interface status bits , */\
+ { 0x1540, "flag_tdm_error"}, /* TDM interface error indicator , */\
+ { 0x1551, "status_bst_mode"}, /* DCDC mode status bits , */\
+ { 0x2000, "flag_por_int_out"}, /* flag_por_int_out , */\
+ { 0x2010, "flag_pll_lock_int_out"}, /* flag_pll_lock_int_out , */\
+ { 0x2020, "flag_otpok_int_out"}, /* flag_otpok_int_out , */\
+ { 0x2030, "flag_ovpok_int_out"}, /* flag_ovpok_int_out , */\
+ { 0x2040, "flag_uvpok_int_out"}, /* flag_uvpok_int_out , */\
+ { 0x2050, "flag_ocp_alarm_int_out"}, /* flag_ocp_alarm_int_out , */\
+ { 0x2060, "flag_clocks_stable_int_out"}, /* flag_clocks_stable_int_out , */\
+ { 0x2070, "flag_clip_int_out"}, /* flag_clip_int_out , */\
+ { 0x2080, "mtp_busy_int_out"}, /* mtp_busy_int_out , */\
+ { 0x2090, "flag_lost_clk_int_out"}, /* flag_lost_clk_int_out , */\
+ { 0x20a0, "flag_cf_speakererror_int_out"}, /* flag_cf_speakererror_int_out , */\
+ { 0x20b0, "flag_cold_started_int_out"}, /* flag_cold_started_int_out , */\
+ { 0x20c0, "flag_engage_int_out"}, /* flag_engage_int_out , */\
+ { 0x20d0, "flag_watchdog_reset_int_out"}, /* flag_watchdog_reset_int_out , */\
+ { 0x20e0, "flag_enbl_amp_int_out"}, /* flag_enbl_amp_int_out , */\
+ { 0x20f0, "flag_enbl_ref_int_out"}, /* flag_enbl_ref_int_out , */\
+ { 0x2100, "flag_voutcomp_int_out"}, /* flag_voutcomp_int_out , */\
+ { 0x2110, "flag_voutcomp93_int_out"}, /* flag_voutcomp93_int_out , */\
+ { 0x2120, "flag_voutcomp86_int_out"}, /* flag_voutcomp86_int_out , */\
+ { 0x2130, "flag_hiz_int_out"}, /* flag_hiz_int_out , */\
+ { 0x2140, "flag_ocpokbst_int_out"}, /* flag_ocpokbst_int_out , */\
+ { 0x2150, "flag_peakcur_int_out"}, /* flag_peakcur_int_out , */\
+ { 0x2160, "flag_ocpokap_int_out"}, /* flag_ocpokap_int_out , */\
+ { 0x2170, "flag_ocpokan_int_out"}, /* flag_ocpokan_int_out , */\
+ { 0x2180, "flag_ocpokbp_int_out"}, /* flag_ocpokbp_int_out , */\
+ { 0x2190, "flag_ocpokbn_int_out"}, /* flag_ocpokbn_int_out , */\
+ { 0x21a0, "flag_adc10_ready_int_out"}, /* flag_adc10_ready_int_out , */\
+ { 0x21b0, "flag_clipa_high_int_out"}, /* flag_clipa_high_int_out , */\
+ { 0x21c0, "flag_clipa_low_int_out"}, /* flag_clipa_low_int_out , */\
+ { 0x21d0, "flag_clipb_high_int_out"}, /* flag_clipb_high_int_out , */\
+ { 0x21e0, "flag_clipb_low_int_out"}, /* flag_clipb_low_int_out , */\
+ { 0x21f0, "flag_tdm_error_int_out"}, /* flag_tdm_error_int_out , */\
+ { 0x2200, "flag_cfma_err_int_out"}, /* flag_cfma_err_int_out , */\
+ { 0x2210, "flag_cfma_ack_int_out"}, /* flag_cfma_ack_int_out , */\
+ { 0x2300, "flag_por_int_in"}, /* flag_por_int_in , */\
+ { 0x2310, "flag_pll_lock_int_in"}, /* flag_pll_lock_int_in , */\
+ { 0x2320, "flag_otpok_int_in"}, /* flag_otpok_int_in , */\
+ { 0x2330, "flag_ovpok_int_in"}, /* flag_ovpok_int_in , */\
+ { 0x2340, "flag_uvpok_int_in"}, /* flag_uvpok_int_in , */\
+ { 0x2350, "flag_ocp_alarm_int_in"}, /* flag_ocp_alarm_int_in , */\
+ { 0x2360, "flag_clocks_stable_int_in"}, /* flag_clocks_stable_int_in , */\
+ { 0x2370, "flag_clip_int_in"}, /* flag_clip_int_in , */\
+ { 0x2380, "mtp_busy_int_in"}, /* mtp_busy_int_in , */\
+ { 0x2390, "flag_lost_clk_int_in"}, /* flag_lost_clk_int_in , */\
+ { 0x23a0, "flag_cf_speakererror_int_in"}, /* flag_cf_speakererror_int_in , */\
+ { 0x23b0, "flag_cold_started_int_in"}, /* flag_cold_started_int_in , */\
+ { 0x23c0, "flag_engage_int_in"}, /* flag_engage_int_in , */\
+ { 0x23d0, "flag_watchdog_reset_int_in"}, /* flag_watchdog_reset_int_in , */\
+ { 0x23e0, "flag_enbl_amp_int_in"}, /* flag_enbl_amp_int_in , */\
+ { 0x23f0, "flag_enbl_ref_int_in"}, /* flag_enbl_ref_int_in , */\
+ { 0x2400, "flag_voutcomp_int_in"}, /* flag_voutcomp_int_in , */\
+ { 0x2410, "flag_voutcomp93_int_in"}, /* flag_voutcomp93_int_in , */\
+ { 0x2420, "flag_voutcomp86_int_in"}, /* flag_voutcomp86_int_in , */\
+ { 0x2430, "flag_hiz_int_in"}, /* flag_hiz_int_in , */\
+ { 0x2440, "flag_ocpokbst_int_in"}, /* flag_ocpokbst_int_in , */\
+ { 0x2450, "flag_peakcur_int_in"}, /* flag_peakcur_int_in , */\
+ { 0x2460, "flag_ocpokap_int_in"}, /* flag_ocpokap_int_in , */\
+ { 0x2470, "flag_ocpokan_int_in"}, /* flag_ocpokan_int_in , */\
+ { 0x2480, "flag_ocpokbp_int_in"}, /* flag_ocpokbp_int_in , */\
+ { 0x2490, "flag_ocpokbn_int_in"}, /* flag_ocpokbn_int_in , */\
+ { 0x24a0, "flag_adc10_ready_int_in"}, /* flag_adc10_ready_int_in , */\
+ { 0x24b0, "flag_clipa_high_int_in"}, /* flag_clipa_high_int_in , */\
+ { 0x24c0, "flag_clipa_low_int_in"}, /* flag_clipa_low_int_in , */\
+ { 0x24d0, "flag_clipb_high_int_in"}, /* flag_clipb_high_int_in , */\
+ { 0x24e0, "flag_clipb_low_int_in"}, /* flag_clipb_low_int_in , */\
+ { 0x24f0, "flag_tdm_error_int_in"}, /* flag_tdm_error_int_in , */\
+ { 0x2500, "flag_cfma_err_int_in"}, /* flag_cfma_err_int_in , */\
+ { 0x2510, "flag_cfma_ack_int_in"}, /* flag_cfma_ack_int_in , */\
+ { 0x2600, "flag_por_int_enable"}, /* flag_por_int_enable , */\
+ { 0x2610, "flag_pll_lock_int_enable"}, /* flag_pll_lock_int_enable , */\
+ { 0x2620, "flag_otpok_int_enable"}, /* flag_otpok_int_enable , */\
+ { 0x2630, "flag_ovpok_int_enable"}, /* flag_ovpok_int_enable , */\
+ { 0x2640, "flag_uvpok_int_enable"}, /* flag_uvpok_int_enable , */\
+ { 0x2650, "flag_ocp_alarm_int_enable"}, /* flag_ocp_alarm_int_enable , */\
+ { 0x2660, "flag_clocks_stable_int_enable"}, /* flag_clocks_stable_int_enable , */\
+ { 0x2670, "flag_clip_int_enable"}, /* flag_clip_int_enable , */\
+ { 0x2680, "mtp_busy_int_enable"}, /* mtp_busy_int_enable , */\
+ { 0x2690, "flag_lost_clk_int_enable"}, /* flag_lost_clk_int_enable , */\
+ { 0x26a0, "flag_cf_speakererror_int_enable"}, /* flag_cf_speakererror_int_enable , */\
+ { 0x26b0, "flag_cold_started_int_enable"}, /* flag_cold_started_int_enable , */\
+ { 0x26c0, "flag_engage_int_enable"}, /* flag_engage_int_enable , */\
+ { 0x26d0, "flag_watchdog_reset_int_enable"}, /* flag_watchdog_reset_int_enable , */\
+ { 0x26e0, "flag_enbl_amp_int_enable"}, /* flag_enbl_amp_int_enable , */\
+ { 0x26f0, "flag_enbl_ref_int_enable"}, /* flag_enbl_ref_int_enable , */\
+ { 0x2700, "flag_voutcomp_int_enable"}, /* flag_voutcomp_int_enable , */\
+ { 0x2710, "flag_voutcomp93_int_enable"}, /* flag_voutcomp93_int_enable , */\
+ { 0x2720, "flag_voutcomp86_int_enable"}, /* flag_voutcomp86_int_enable , */\
+ { 0x2730, "flag_hiz_int_enable"}, /* flag_hiz_int_enable , */\
+ { 0x2740, "flag_ocpokbst_int_enable"}, /* flag_ocpokbst_int_enable , */\
+ { 0x2750, "flag_peakcur_int_enable"}, /* flag_peakcur_int_enable , */\
+ { 0x2760, "flag_ocpokap_int_enable"}, /* flag_ocpokap_int_enable , */\
+ { 0x2770, "flag_ocpokan_int_enable"}, /* flag_ocpokan_int_enable , */\
+ { 0x2780, "flag_ocpokbp_int_enable"}, /* flag_ocpokbp_int_enable , */\
+ { 0x2790, "flag_ocpokbn_int_enable"}, /* flag_ocpokbn_int_enable , */\
+ { 0x27a0, "flag_adc10_ready_int_enable"}, /* flag_adc10_ready_int_enable , */\
+ { 0x27b0, "flag_clipa_high_int_enable"}, /* flag_clipa_high_int_enable , */\
+ { 0x27c0, "flag_clipa_low_int_enable"}, /* flag_clipa_low_int_enable , */\
+ { 0x27d0, "flag_clipb_high_int_enable"}, /* flag_clipb_high_int_enable , */\
+ { 0x27e0, "flag_clipb_low_int_enable"}, /* flag_clipb_low_int_enable , */\
+ { 0x27f0, "flag_tdm_error_int_enable"}, /* flag_tdm_error_int_enable , */\
+ { 0x2800, "flag_cfma_err_int_enable"}, /* flag_cfma_err_int_enable , */\
+ { 0x2810, "flag_cfma_ack_int_enable"}, /* flag_cfma_ack_int_enable , */\
+ { 0x2900, "flag_por_int_pol"}, /* flag_por_int_pol , */\
+ { 0x2910, "flag_pll_lock_int_pol"}, /* flag_pll_lock_int_pol , */\
+ { 0x2920, "flag_otpok_int_pol"}, /* flag_otpok_int_pol , */\
+ { 0x2930, "flag_ovpok_int_pol"}, /* flag_ovpok_int_pol , */\
+ { 0x2940, "flag_uvpok_int_pol"}, /* flag_uvpok_int_pol , */\
+ { 0x2950, "flag_ocp_alarm_int_pol"}, /* flag_ocp_alarm_int_pol , */\
+ { 0x2960, "flag_clocks_stable_int_pol"}, /* flag_clocks_stable_int_pol , */\
+ { 0x2970, "flag_clip_int_pol"}, /* flag_clip_int_pol , */\
+ { 0x2980, "mtp_busy_int_pol"}, /* mtp_busy_int_pol , */\
+ { 0x2990, "flag_lost_clk_int_pol"}, /* flag_lost_clk_int_pol , */\
+ { 0x29a0, "flag_cf_speakererror_int_pol"}, /* flag_cf_speakererror_int_pol , */\
+ { 0x29b0, "flag_cold_started_int_pol"}, /* flag_cold_started_int_pol , */\
+ { 0x29c0, "flag_engage_int_pol"}, /* flag_engage_int_pol , */\
+ { 0x29d0, "flag_watchdog_reset_int_pol"}, /* flag_watchdog_reset_int_pol , */\
+ { 0x29e0, "flag_enbl_amp_int_pol"}, /* flag_enbl_amp_int_pol , */\
+ { 0x29f0, "flag_enbl_ref_int_pol"}, /* flag_enbl_ref_int_pol , */\
+ { 0x2a00, "flag_voutcomp_int_pol"}, /* flag_voutcomp_int_pol , */\
+ { 0x2a10, "flag_voutcomp93_int_pol"}, /* flag_voutcomp93_int_pol , */\
+ { 0x2a20, "flag_voutcomp86_int_pol"}, /* flag_voutcomp86_int_pol , */\
+ { 0x2a30, "flag_hiz_int_pol"}, /* flag_hiz_int_pol , */\
+ { 0x2a40, "flag_ocpokbst_int_pol"}, /* flag_ocpokbst_int_pol , */\
+ { 0x2a50, "flag_peakcur_int_pol"}, /* flag_peakcur_int_pol , */\
+ { 0x2a60, "flag_ocpokap_int_pol"}, /* flag_ocpokap_int_pol , */\
+ { 0x2a70, "flag_ocpokan_int_pol"}, /* flag_ocpokan_int_pol , */\
+ { 0x2a80, "flag_ocpokbp_int_pol"}, /* flag_ocpokbp_int_pol , */\
+ { 0x2a90, "flag_ocpokbn_int_pol"}, /* flag_ocpokbn_int_pol , */\
+ { 0x2aa0, "flag_adc10_ready_int_pol"}, /* flag_adc10_ready_int_pol , */\
+ { 0x2ab0, "flag_clipa_high_int_pol"}, /* flag_clipa_high_int_pol , */\
+ { 0x2ac0, "flag_clipa_low_int_pol"}, /* flag_clipa_low_int_pol , */\
+ { 0x2ad0, "flag_clipb_high_int_pol"}, /* flag_clipb_high_int_pol , */\
+ { 0x2ae0, "flag_clipb_low_int_pol"}, /* flag_clipb_low_int_pol , */\
+ { 0x2af0, "flag_tdm_error_int_pol"}, /* flag_tdm_error_int_pol , */\
+ { 0x2b00, "flag_cfma_err_int_pol"}, /* flag_cfma_err_int_pol , */\
+ { 0x2b10, "flag_cfma_ack_int_pol"}, /* flag_cfma_ack_int_pol , */\
+ { 0x3000, "flag_voutcomp"}, /* Status flag_voutcomp, indication Vset is larger than Vbat, */\
+ { 0x3010, "flag_voutcomp93"}, /* Status flag_voutcomp93, indication Vset is larger than 1.07 x Vbat, */\
+ { 0x3020, "flag_voutcomp86"}, /* Status flag voutcomp86, indication Vset is larger than 1.14 x Vbat, */\
+ { 0x3030, "flag_hiz"}, /* Status flag_hiz, indication Vbst is larger than Vbat, */\
+ { 0x3040, "flag_ocpokbst"}, /* Status flag_ocpokbst, indication no over current in boost converter PMOS switch, */\
+ { 0x3050, "flag_peakcur"}, /* Status flag_peakcur, indication current is max in dcdc converter, */\
+ { 0x3060, "flag_ocpokap"}, /* Status flag_ocpokap, indication no over current in amplifier A PMOS output stage, */\
+ { 0x3070, "flag_ocpokan"}, /* Status flag_ocpokan, indication no over current in amplifier A NMOS output stage, */\
+ { 0x3080, "flag_ocpokbp"}, /* Status flag_ocpokbp, indication no over current in amplifier B PMOS output stage, */\
+ { 0x3090, "flag_ocpokbn"}, /* Status flag_ocpokbn, indication no over current in amplifier B NMOS output stage, */\
+ { 0x30a0, "flag_adc10_ready"}, /* Status flag_adc10_ready, indication adc10 is ready, */\
+ { 0x30b0, "flag_clipa_high"}, /* Status flag_clipa_high, indication pmos amplifier A is clipping, */\
+ { 0x30c0, "flag_clipa_low"}, /* Status flag_clipa_low, indication nmos amplifier A is clipping, */\
+ { 0x30d0, "flag_clipb_high"}, /* Status flag_clipb_high, indication pmos amplifier B is clipping, */\
+ { 0x30e0, "flag_clipb_low"}, /* Status flag_clipb_low, indication nmos amplifier B is clipping, */\
+ { 0x310f, "mtp_man_data_out"}, /* MTP manual read out data , */\
+ { 0x3200, "key01_locked"}, /* Indicates KEY1 is locked , */\
+ { 0x3210, "key02_locked"}, /* Indicates KEY2 is locked , */\
+ { 0x3225, "mtp_ecc_tcout"}, /* MTP error correction test data out , */\
+ { 0x3280, "mtpctrl_valid_test_rd"}, /* MTP test readout for read , */\
+ { 0x3290, "mtpctrl_valid_test_wr"}, /* MTP test readout for write , */\
+ { 0x32a0, "flag_in_alarm_state"}, /* Flag alarm state , */\
+ { 0x32b0, "mtp_ecc_err2"}, /* Two or more bit errors detected in MTP, can not reconstruct value, */\
+ { 0x32c0, "mtp_ecc_err1"}, /* One bit error detected in MTP, reconstructed value, */\
+ { 0x32d0, "mtp_mtp_hvf"}, /* High voltage ready flag for MTP , */\
+ { 0x32f0, "mtp_zero_check_fail"}, /* Zero check failed for MTP , */\
+ { 0x3309, "data_adc10_tempbat"}, /* ADC10 data output for testing battery voltage and temperature, */\
+ { 0x400f, "hid_code"}, /* 5A6Bh, 23147d to access hidden registers (default for engineering), */\
+ { 0x4100, "bypass_hp"}, /* Bypass High Pass Filter , */\
+ { 0x4110, "hard_mute"}, /* Hard Mute , */\
+ { 0x4120, "soft_mute"}, /* Soft Mute , */\
+ { 0x4134, "pwm_delay"}, /* PWM delay setting , */\
+ { 0x4180, "pwm_shape"}, /* PWM Shape , */\
+ { 0x4190, "pwm_bitlength"}, /* PWM Bitlength in noise shaper , */\
+ { 0x4203, "drive"}, /* Drive bits to select number of amplifier power stages, */\
+ { 0x4240, "reclock_pwm"}, /* Control for enabling reclocking of PWM signal , */\
+ { 0x4250, "reclock_voltsense"}, /* Control for enabling reclocking of voltage sense signal, */\
+ { 0x4281, "dpsalevel"}, /* DPSA threshold level , */\
+ { 0x42a1, "dpsa_release"}, /* DPSA release time , */\
+ { 0x42c0, "coincidence"}, /* Prevent simultaneously switching of output stage , */\
+ { 0x42d0, "kickback"}, /* Prevent double pulses of output stage , */\
+ { 0x4306, "drivebst"}, /* Drive bits to select the power transistor sections boost converter, */\
+ { 0x4370, "boost_alg"}, /* Control for boost adaptive loop gain , */\
+ { 0x4381, "boost_loopgain"}, /* DCDC boost loopgain setting , */\
+ { 0x43a0, "ocptestbst"}, /* Boost OCP. For old ocp (ctrl_reversebst is 0); For new ocp (ctrl_reversebst is 1), */\
+ { 0x43d0, "test_abistfft_enbl"}, /* FFT Coolflux , */\
+ { 0x43e0, "bst_dcmbst"}, /* DCM mode control for DCDC during I2C direct control mode, */\
+ { 0x43f0, "test_bcontrol"}, /* test_bcontrol , */\
+ { 0x4400, "reversebst"}, /* OverCurrent Protection selection of power stage boost converter, */\
+ { 0x4410, "sensetest"}, /* Test option for the sense NMOS in booster for current mode control., */\
+ { 0x4420, "enbl_engagebst"}, /* Enable power stage of dcdc controller , */\
+ { 0x4470, "enbl_slopecur"}, /* Enable bit of max-current dac , */\
+ { 0x4480, "enbl_voutcomp"}, /* Enable vout comparators , */\
+ { 0x4490, "enbl_voutcomp93"}, /* Enable vout-93 comparators , */\
+ { 0x44a0, "enbl_voutcomp86"}, /* Enable vout-86 comparators , */\
+ { 0x44b0, "enbl_hizcom"}, /* Enable hiz comparator , */\
+ { 0x44c0, "enbl_peakcur"}, /* Enable peak current , */\
+ { 0x44d0, "bypass_ovpglitch"}, /* Bypass OVP Glitch Filter , */\
+ { 0x44e0, "enbl_windac"}, /* Enable window dac , */\
+ { 0x44f0, "enbl_powerbst"}, /* Enable line of the powerstage , */\
+ { 0x4507, "ocp_thr"}, /* OCP threshold level , */\
+ { 0x4580, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
+ { 0x4590, "bypass_ovp"}, /* Bypass OVP , */\
+ { 0x45a0, "bypass_uvp"}, /* Bypass UVP , */\
+ { 0x45b0, "bypass_otp"}, /* Bypass OTP , */\
+ { 0x45d0, "bypass_ocpcounter"}, /* Bypass OCP counter , */\
+ { 0x45e0, "bypass_lost_clk"}, /* Bypass lost clock detector , */\
+ { 0x45f0, "vpalarm"}, /* vpalarm (UVP/OUP handling) , */\
+ { 0x4600, "bypass_gc"}, /* Bypasses the CS gain correction , */\
+ { 0x4610, "cs_gain_control"}, /* Current sense gain control , */\
+ { 0x4627, "cs_gain"}, /* Current sense gain , */\
+ { 0x46a0, "bypass_lp"}, /* Bypass the low power filter inside temperature sensor, */\
+ { 0x46b0, "bypass_pwmcounter"}, /* Bypass PWM Counter , */\
+ { 0x46c0, "cs_negfixed"}, /* Current sense does not switch to neg , */\
+ { 0x46d2, "cs_neghyst"}, /* Current sense switches to neg depending on hyseteris level, */\
+ { 0x4700, "switch_fb"}, /* Current sense control switch_fb , */\
+ { 0x4713, "se_hyst"}, /* Current sense control se_hyst , */\
+ { 0x4754, "se_level"}, /* Current sense control se_level , */\
+ { 0x47a5, "ktemp"}, /* Current sense control temperature compensation trimming, */\
+ { 0x4800, "cs_negin"}, /* Current sense control negin , */\
+ { 0x4810, "cs_sein"}, /* Current sense control cs_sein , */\
+ { 0x4820, "cs_coincidence"}, /* Coincidence current sense , */\
+ { 0x4830, "iddqtestbst"}, /* IDDQ testing in powerstage of DCDC boost converter, */\
+ { 0x4840, "coincidencebst"}, /* Switch protection on to prevent simultaneously switching power stages bst and amp, */\
+ { 0x4876, "delay_se_neg"}, /* delay of se and neg , */\
+ { 0x48e1, "cs_ttrack"}, /* Sample and hold track time , */\
+ { 0x4900, "bypass_clip"}, /* Bypass clip control , */\
+ { 0x4920, "cf_cgate_off"}, /* Disable clock gating in the coolflux , */\
+ { 0x4940, "clipfast"}, /* Clock selection for HW clipper for battery safeguard, */\
+ { 0x4950, "cs_8ohm"}, /* 8 ohm mode for current sense (gain mode) , */\
+ { 0x4974, "delay_clock_sh"}, /* delay_sh, tunes S7H delay , */\
+ { 0x49c0, "inv_clksh"}, /* Invert the sample/hold clock for current sense ADC, */\
+ { 0x49d0, "inv_neg"}, /* Invert neg signal , */\
+ { 0x49e0, "inv_se"}, /* Invert se signal , */\
+ { 0x49f0, "setse"}, /* Switches between Single Ended and differential mode; 1 is single ended, */\
+ { 0x4a12, "adc10_sel"}, /* Select the input to convert the 10b ADC , */\
+ { 0x4a60, "adc10_reset"}, /* Reset for ADC10 - I2C direct control mode , */\
+ { 0x4a81, "adc10_test"}, /* Test mode selection signal for ADC10 - I2C direct control mode, */\
+ { 0x4aa0, "bypass_lp_vbat"}, /* LP filter in batt sensor , */\
+ { 0x4ae0, "dc_offset"}, /* Current sense decimator offset control , */\
+ { 0x4af0, "tsense_hibias"}, /* Bit to set the biasing in temp sensor to high , */\
+ { 0x4b00, "adc13_iset"}, /* MICADC setting of current consumption (debug use only), */\
+ { 0x4b14, "adc13_gain"}, /* MICADC gain setting (two's complement format) , */\
+ { 0x4b61, "adc13_slowdel"}, /* MICADC delay setting for internal clock (debug use only), */\
+ { 0x4b83, "adc13_offset"}, /* MICADC offset setting , */\
+ { 0x4bc0, "adc13_bsoinv"}, /* MICADC bit stream output invert mode for test , */\
+ { 0x4bd0, "adc13_resonator_enable"}, /* MICADC give extra SNR with less stability (debug use only), */\
+ { 0x4be0, "testmicadc"}, /* Mux at input of MICADC for test purpose , */\
+ { 0x4c0f, "abist_offset"}, /* Offset control for ABIST testing , */\
+ { 0x4d05, "windac"}, /* For testing direct control windac , */\
+ { 0x4dc3, "pwm_dcc_cnt"}, /* control pwm duty cycle when enbl_pwm_dcc is 1 , */\
+ { 0x4e04, "slopecur"}, /* For testing direct control slopecur , */\
+ { 0x4e50, "ctrl_dem"}, /* Dynamic element matching control, rest of codes are optional, */\
+ { 0x4ed0, "enbl_pwm_dcc"}, /* Enable direct control of pwm duty cycle , */\
+ { 0x4f00, "bst_bypass_bstcur"}, /* Bypass control for boost current settings , */\
+ { 0x4f10, "bst_bypass_bstfoldback"}, /* Bypass control for boost foldback , */\
+ { 0x4f20, "bst_ctrl_azbst"}, /* Control of auto-zeroing of zero current comparator, */\
+ { 0x5007, "gain"}, /* Gain setting of the gain multiplier , */\
+ { 0x5081, "sourceb"}, /* PWM OUTB selection control , */\
+ { 0x50a1, "sourcea"}, /* PWM OUTA selection control , */\
+ { 0x50c1, "sourcebst"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
+ { 0x50e0, "tdm_enable_loopback"}, /* TDM loopback test , */\
+ { 0x5104, "pulselengthbst"}, /* Pulse length setting test input for boost converter, */\
+ { 0x5150, "bypasslatchbst"}, /* Bypass latch in boost converter , */\
+ { 0x5160, "invertbst"}, /* Invert pwmbst test signal , */\
+ { 0x5174, "pulselength"}, /* Pulse length setting test input for amplifier , */\
+ { 0x51c0, "bypasslatch"}, /* Bypass latch in PWM source selection module , */\
+ { 0x51d0, "invertb"}, /* invert pwmb test signal , */\
+ { 0x51e0, "inverta"}, /* invert pwma test signal , */\
+ { 0x51f0, "bypass_ctrlloop"}, /* bypass_ctrlloop bypasses the control loop of the amplifier, */\
+ { 0x5210, "test_rdsona"}, /* tbd for rdson testing , */\
+ { 0x5220, "test_rdsonb"}, /* tbd for rdson testing , */\
+ { 0x5230, "test_rdsonbst"}, /* tbd for rdson testing , */\
+ { 0x5240, "test_cvia"}, /* tbd for rdson testing , */\
+ { 0x5250, "test_cvib"}, /* tbd for rdson testing , */\
+ { 0x5260, "test_cvibst"}, /* tbd for rdson testing , */\
+ { 0x5306, "digimuxa_sel"}, /* DigimuxA input selection control (see Digimux list for details), */\
+ { 0x5376, "digimuxb_sel"}, /* DigimuxB input selection control (see Digimux list for details), */\
+ { 0x5400, "hs_mode"}, /* I2C high speed mode selection control , */\
+ { 0x5412, "test_parametric_io"}, /* Control for parametric tests of IO cells , */\
+ { 0x5440, "enbl_ringo"}, /* Enable ring oscillator control, for test purpose to check with ringo, */\
+ { 0x5456, "digimuxc_sel"}, /* DigimuxC input selection control (see Digimux list for details), */\
+ { 0x54c0, "dio_ehs"}, /* Slew control for DIO in output mode , */\
+ { 0x54d0, "gainio_ehs"}, /* Slew control for GAINIO in output mode , */\
+ { 0x550d, "enbl_amp"}, /* enbl_amp for testing to enable all analoge blocks in amplifier, */\
+ { 0x5600, "use_direct_ctrls"}, /* Use direct controls to overrule several functions for testing - I2C direct control mode, */\
+ { 0x5610, "rst_datapath"}, /* Reset datapath during direct control mode , */\
+ { 0x5620, "rst_cgu"}, /* Reset CGU during durect control mode , */\
+ { 0x5637, "enbl_ref"}, /* For testing to enable all analoge blocks in references, */\
+ { 0x56b0, "enbl_engage"}, /* Enable output stage amplifier , */\
+ { 0x56c0, "use_direct_clk_ctrl"}, /* use_direct_clk_ctrl, to overrule several functions direct for testing, */\
+ { 0x56d0, "use_direct_pll_ctrl"}, /* use_direct_pll_ctrl, to overrule several functions direct for testing, */\
+ { 0x5707, "anamux"}, /* Anamux control , */\
+ { 0x57e0, "otptest"}, /* otptest, test mode otp amplifier , */\
+ { 0x57f0, "reverse"}, /* 1b = Normal mode, slope is controlled , */\
+ { 0x5813, "pll_selr"}, /* PLL pll_selr , */\
+ { 0x5854, "pll_selp"}, /* PLL pll_selp , */\
+ { 0x58a5, "pll_seli"}, /* PLL pll_seli , */\
+ { 0x5950, "pll_mdec_msb"}, /* Most significant bits of pll_mdec[16] , */\
+ { 0x5960, "pll_ndec_msb"}, /* Most significant bits of pll_ndec[9] , */\
+ { 0x5970, "pll_frm"}, /* PLL pll_frm , */\
+ { 0x5980, "pll_directi"}, /* PLL pll_directi , */\
+ { 0x5990, "pll_directo"}, /* PLL pll_directo , */\
+ { 0x59a0, "enbl_pll"}, /* PLL enbl_pll , */\
+ { 0x59f0, "pll_bypass"}, /* PLL bypass , */\
+ { 0x5a0f, "tsig_freq"}, /* Internal sinus test generator frequency control LSB bits, */\
+ { 0x5b02, "tsig_freq_msb"}, /* Select internal sine wave generator, frequency control MSB bits, */\
+ { 0x5b30, "inject_tsig"}, /* Control bit to switch to internal sinus test generator, */\
+ { 0x5b44, "adc10_prog_sample"}, /* ADC10 program sample setting - I2C direct control mode, */\
+ { 0x5c0f, "pll_mdec"}, /* PLL MDEC - I2C direct PLL control mode only , */\
+ { 0x5d06, "pll_pdec"}, /* PLL PDEC - I2C direct PLL control mode only , */\
+ { 0x5d78, "pll_ndec"}, /* PLL NDEC - I2C direct PLL control mode only , */\
+ { 0x6007, "mtpkey1"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
+ { 0x6185, "mtp_ecc_tcin"}, /* MTP ECC TCIN data , */\
+ { 0x6203, "mtp_man_address_in"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
+ { 0x6260, "mtp_ecc_eeb"}, /* Enable code bit generation (active low!) , */\
+ { 0x6270, "mtp_ecc_ecb"}, /* Enable correction signal (active low!) , */\
+ { 0x6280, "man_copy_mtp_to_iic"}, /* Start copying single word from mtp to I2C mtp register, */\
+ { 0x6290, "man_copy_iic_to_mtp"}, /* Start copying single word from I2C mtp register to mtp, */\
+ { 0x62a0, "auto_copy_mtp_to_iic"}, /* Start copying all the data from mtp to I2C mtp registers, */\
+ { 0x62b0, "auto_copy_iic_to_mtp"}, /* Start copying data from I2C mtp registers to mtp , */\
+ { 0x62d2, "mtp_speed_mode"}, /* MTP speed mode , */\
+ { 0x6340, "mtp_direct_enable"}, /* mtp_direct_enable , */\
+ { 0x6350, "mtp_direct_wr"}, /* mtp_direct_wr , */\
+ { 0x6360, "mtp_direct_rd"}, /* mtp_direct_rd , */\
+ { 0x6370, "mtp_direct_rst"}, /* mtp_direct_rst , */\
+ { 0x6380, "mtp_direct_ers"}, /* mtp_direct_ers , */\
+ { 0x6390, "mtp_direct_prg"}, /* mtp_direct_prg , */\
+ { 0x63a0, "mtp_direct_epp"}, /* mtp_direct_epp , */\
+ { 0x63b4, "mtp_direct_test"}, /* mtp_direct_test , */\
+ { 0x640f, "mtp_man_data_in"}, /* Write data for MTP manual write , */\
+ { 0x7000, "cf_rst_dsp"}, /* Reset CoolFlux DSP , */\
+ { 0x7011, "cf_dmem"}, /* Target memory for access , */\
+ { 0x7030, "cf_aif"}, /* Auto increment flag for memory-address , */\
+ { 0x7040, "cf_int"}, /* CF Interrupt - auto clear , */\
+ { 0x7087, "cf_req"}, /* CF request for accessing the 8 channels , */\
+ { 0x710f, "cf_madd"}, /* Memory address , */\
+ { 0x720f, "cf_mema"}, /* Activate memory access , */\
+ { 0x7307, "cf_err"}, /* CF error flags , */\
+ { 0x7387, "cf_ack"}, /* CF acknowledgement of the requests channels , */\
+ { 0x8000, "calibration_onetime"}, /* Calibration schedule selection , */\
+ { 0x8010, "calibr_ron_done"}, /* Calibration of RON status bit , */\
+ { 0x8105, "calibr_vout_offset"}, /* calibr_vout_offset (DCDCoffset) 2's compliment (key1 protected), */\
+ { 0x8163, "calibr_delta_gain"}, /* delta gain for vamp (alpha) 2's compliment (key1 protected), */\
+ { 0x81a5, "calibr_offs_amp"}, /* offset for vamp (Ampoffset) 2's compliment (key1 protected), */\
+ { 0x8207, "calibr_gain_cs"}, /* gain current sense (Imeasalpha) 2's compliment (key1 protected), */\
+ { 0x8284, "calibr_temp_offset"}, /* temperature offset 2's compliment (key1 protected), */\
+ { 0x82d2, "calibr_temp_gain"}, /* temperature gain 2's compliment (key1 protected) , */\
+ { 0x830f, "calibr_ron"}, /* calibration value of the RON resistance of the coil, */\
+ { 0x8505, "type_bits_hw"}, /* bit0 = disable function dcdcoff_mode ($09[7]) , */\
+ { 0x8601, "type_bits_1_0_sw"}, /* MTP control SW , */\
+ { 0x8681, "type_bits_9_8_sw"}, /* MTP control SW , */\
+ { 0x870f, "type_bits2_sw"}, /* MTP-control SW2 , */\
+ { 0x8806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
+ { 0x8870, "htol_iic_addr_en"}, /* HTOL I2C_Address_Enable , */\
+ { 0x8881, "ctrl_ovp_response"}, /* OVP response control , */\
+ { 0x88a0, "disable_ovp_alarm_state"}, /* OVP alarm state control , */\
+ { 0x88b0, "enbl_stretch_ovp"}, /* OVP alram strech control , */\
+ { 0x88c0, "cf_debug_mode"}, /* Coolflux debug mode , */\
+ { 0x8a0f, "production_data1"}, /* production_data1 , */\
+ { 0x8b0f, "production_data2"}, /* production_data2 , */\
+ { 0x8c0f, "production_data3"}, /* production_data3 , */\
+ { 0x8d0f, "production_data4"}, /* production_data4 , */\
+ { 0x8e0f, "production_data5"}, /* production_data5 , */\
+ { 0x8f0f, "production_data6"}, /* production_data6 , */\
+ { 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+
+enum TFA9896_irq {
+ TFA9896_irq_vdds = 0,
+ TFA9896_irq_plls = 1,
+ TFA9896_irq_ds = 2,
+ TFA9896_irq_vds = 3,
+ TFA9896_irq_uvds = 4,
+ TFA9896_irq_cds = 5,
+ TFA9896_irq_clks = 6,
+ TFA9896_irq_clips = 7,
+ TFA9896_irq_mtpb = 8,
+ TFA9896_irq_clk = 9,
+ TFA9896_irq_spks = 10,
+ TFA9896_irq_acs = 11,
+ TFA9896_irq_sws = 12,
+ TFA9896_irq_wds = 13,
+ TFA9896_irq_amps = 14,
+ TFA9896_irq_arefs = 15,
+ TFA9896_irq_err = 32,
+ TFA9896_irq_ack = 33,
+ TFA9896_irq_max = 34,
+ TFA9896_irq_all = -1 /* all irqs */};
+
+#define TFA9896_IRQ_NAMETABLE static tfaIrqName_t TFA9896IrqNames[] = {\
+ { 0, "VDDS"},\
+ { 1, "PLLS"},\
+ { 2, "DS"},\
+ { 3, "VDS"},\
+ { 4, "UVDS"},\
+ { 5, "CDS"},\
+ { 6, "CLKS"},\
+ { 7, "CLIPS"},\
+ { 8, "MTPB"},\
+ { 9, "CLK"},\
+ { 10, "SPKS"},\
+ { 11, "ACS"},\
+ { 12, "SWS"},\
+ { 13, "WDS"},\
+ { 14, "AMPS"},\
+ { 15, "AREFS"},\
+ { 16, "16"},\
+ { 17, "17"},\
+ { 18, "18"},\
+ { 19, "19"},\
+ { 20, "20"},\
+ { 21, "21"},\
+ { 22, "22"},\
+ { 23, "23"},\
+ { 24, "24"},\
+ { 25, "25"},\
+ { 26, "26"},\
+ { 27, "27"},\
+ { 28, "28"},\
+ { 29, "29"},\
+ { 30, "30"},\
+ { 31, "31"},\
+ { 32, "ERR"},\
+ { 33, "ACK"},\
+ { 34, "34"},\
+};
+#endif /* _TFA9896_TFAFIELDNAMES_H */
diff --git a/src/tfa98xx.c b/sound/soc/codecs/tfa98xx.c
similarity index 91%
rename from src/tfa98xx.c
rename to sound/soc/codecs/tfa98xx.c
index c218cf8..15e9a0c 100644
--- a/src/tfa98xx.c
+++ b/sound/soc/codecs/tfa98xx.c
@@ -1,3243 +1,3278 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#define pr_fmt(fmt) "%s(): " fmt, __func__
-
-#include <linux/module.h>
-#include <linux/i2c.h>
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/pcm_params.h>
-#include <sound/soc.h>
-#include <linux/of_gpio.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/firmware.h>
-#include <linux/debugfs.h>
-#include <linux/version.h>
-#include <linux/input.h>
-#include "config.h"
-#include "tfa98xx.h"
-#include "tfa.h"
-
- /* required for enum tfa9912_irq */
-#include "tfa98xx_tfafieldnames.h"
-
-#define TFA98XX_VERSION TFA98XX_API_REV_STR
-
-#define I2C_RETRIES 50
-#define I2C_RETRY_DELAY 5 /* ms */
-
-/* Change volume selection behavior:
- * Uncomment following line to generate a profile change when updating
- * a volume control (also changes to the profile of the modified volume
- * control)
- */
- /*#define TFA98XX_ALSA_CTRL_PROF_CHG_ON_VOL 1
- */
-
- /* Supported rates and data formats */
-#define TFA98XX_RATES SNDRV_PCM_RATE_8000_48000
-#define TFA98XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
-
-#define TF98XX_MAX_DSP_START_TRY_COUNT 10
-
-/* data accessible by all instances */
-static struct kmem_cache *tfa98xx_cache = NULL; /* Memory pool used for DSP messages */
-/* Mutex protected data */
-static DEFINE_MUTEX(tfa98xx_mutex);
-static LIST_HEAD(tfa98xx_device_list);
-static int tfa98xx_device_count = 0;
-static int tfa98xx_sync_count = 0;
-static LIST_HEAD(profile_list); /* list of user selectable profiles */
-static int tfa98xx_mixer_profiles = 0; /* number of user selectable profiles */
-static int tfa98xx_mixer_profile = 0; /* current mixer profile */
-static struct snd_kcontrol_new *tfa98xx_controls;
-static nxpTfaContainer_t *tfa98xx_container = NULL;
-
-static int tfa98xx_kmsg_regs = 0;
-static int tfa98xx_ftrace_regs = 0;
-
-static char *fw_name = "tfa98xx.cnt";
-module_param(fw_name, charp, S_IRUGO | S_IWUSR);
-MODULE_PARM_DESC(fw_name, "TFA98xx DSP firmware (container file) name.");
-
-static int trace_level = 0;
-module_param(trace_level, int, S_IRUGO);
-MODULE_PARM_DESC(trace_level, "TFA98xx debug trace level (0=off, bits:1=verbose,2=regdmesg,3=regftrace,4=timing).");
-
-static char *dflt_prof_name = "";
-module_param(dflt_prof_name, charp, S_IRUGO);
-
-static int no_start = 0;
-module_param(no_start, int, S_IRUGO);
-MODULE_PARM_DESC(no_start, "do not start the work queue; for debugging via user\n");
-
-static int no_reset = 0;
-module_param(no_reset, int, S_IRUGO);
-MODULE_PARM_DESC(no_reset, "do not use the reset line; for debugging via user\n");
-
-static int pcm_sample_format = 0;
-module_param(pcm_sample_format, int, S_IRUGO);
-MODULE_PARM_DESC(pcm_sample_format, "PCM sample format: 0=S16_LE, 1=S24_LE, 2=S32_LE\n");
-
-static int pcm_no_constraint = 0;
-module_param(pcm_no_constraint, int, S_IRUGO);
-MODULE_PARM_DESC(pcm_no_constraint, "do not use constraints for PCM parameters\n");
-
-static void tfa98xx_tapdet_check_update(struct tfa98xx *tfa98xx);
-static int tfa98xx_get_fssel(unsigned int rate);
-static void tfa98xx_interrupt_enable(struct tfa98xx *tfa98xx, bool enable);
-
-static int get_profile_from_list(char *buf, int id);
-static int get_profile_id_for_sr(int id, unsigned int rate);
-
-struct tfa98xx_rate {
- unsigned int rate;
- unsigned int fssel;
-};
-
-static const struct tfa98xx_rate rate_to_fssel[] = {
- { 8000, 0 },
- { 11025, 1 },
- { 12000, 2 },
- { 16000, 3 },
- { 22050, 4 },
- { 24000, 5 },
- { 32000, 6 },
- { 44100, 7 },
- { 48000, 8 },
-};
-
-
-static inline char *tfa_cont_profile_name(struct tfa98xx *tfa98xx, int prof_idx)
-{
- if (tfa98xx->tfa->cnt == NULL)
- return NULL;
- return tfaContProfileName(tfa98xx->tfa->cnt, tfa98xx->tfa->dev_idx, prof_idx);
-}
-
-static enum tfa_error tfa98xx_write_re25(struct tfa_device *tfa, int value)
-{
- enum tfa_error err;
-
- /* clear MTPEX */
- err = tfa_dev_mtp_set(tfa, TFA_MTP_EX, 0);
- if (err == tfa_error_ok) {
- /* set RE25 in shadow regiser */
- err = tfa_dev_mtp_set(tfa, TFA_MTP_RE25_PRIM, value);
- }
- if (err == tfa_error_ok) {
- /* set MTPEX to copy RE25 into MTP */
- err = tfa_dev_mtp_set(tfa, TFA_MTP_EX, 2);
- }
-
- return err;
-}
-
-/* Wrapper for tfa start */
-static enum tfa_error tfa98xx_tfa_start(struct tfa98xx *tfa98xx, int next_profile, int vstep)
-{
- enum tfa_error err;
- ktime_t start_time, stop_time;
- u64 delta_time;
-
- if (trace_level & 8) {
- start_time = ktime_get_boottime();
- }
-
- err = tfa_dev_start(tfa98xx->tfa, next_profile, vstep);
-
- if (trace_level & 8) {
- stop_time = ktime_get_boottime();
- delta_time = ktime_to_ns(ktime_sub(stop_time, start_time));
- do_div(delta_time, 1000);
- dev_dbg(&tfa98xx->i2c->dev, "tfa_dev_start(%d,%d) time = %lld us\n",
- next_profile, vstep, delta_time);
- }
-
- if ((err == tfa_error_ok) && (tfa98xx->set_mtp_cal)) {
- enum tfa_error err_cal;
- err_cal = tfa98xx_write_re25(tfa98xx->tfa, tfa98xx->cal_data);
- if (err_cal != tfa_error_ok) {
- pr_err("Error, setting calibration value in mtp, err=%d\n", err_cal);
- }
- else {
- tfa98xx->set_mtp_cal = false;
- pr_info("Calibration value (%d) set in mtp\n",
- tfa98xx->cal_data);
- }
- }
-
- /* Check and update tap-detection state (in case of profile change) */
- tfa98xx_tapdet_check_update(tfa98xx);
-
- /* Remove sticky bit by reading it once */
- tfa_get_noclk(tfa98xx->tfa);
-
- /* A cold start erases the configuration, including interrupts setting.
- * Restore it if required
- */
- tfa98xx_interrupt_enable(tfa98xx, true);
-
- return err;
-}
-
-static int tfa98xx_input_open(struct input_dev *dev)
-{
- struct tfa98xx *tfa98xx = input_get_drvdata(dev);
- dev_dbg(tfa98xx->codec->dev, "opening device file\n");
-
- /* note: open function is called only once by the framework.
- * No need to count number of open file instances.
- */
- if (tfa98xx->dsp_fw_state != TFA98XX_DSP_FW_OK) {
- dev_dbg(&tfa98xx->i2c->dev,
- "DSP not loaded, cannot start tap-detection\n");
- return -EIO;
- }
-
- /* enable tap-detection service */
- tfa98xx->tapdet_open = true;
- tfa98xx_tapdet_check_update(tfa98xx);
-
- return 0;
-}
-
-static void tfa98xx_input_close(struct input_dev *dev)
-{
- struct tfa98xx *tfa98xx = input_get_drvdata(dev);
-
- dev_dbg(tfa98xx->codec->dev, "closing device file\n");
-
- /* Note: close function is called if the device is unregistered */
-
- /* disable tap-detection service */
- tfa98xx->tapdet_open = false;
- tfa98xx_tapdet_check_update(tfa98xx);
-}
-
-static int tfa98xx_register_inputdev(struct tfa98xx *tfa98xx)
-{
- int err;
- struct input_dev *input;
- input = input_allocate_device();
-
- if (!input) {
- dev_err(tfa98xx->codec->dev, "Unable to allocate input device\n");
- return -ENOMEM;
- }
-
- input->evbit[0] = BIT_MASK(EV_KEY);
- input->keybit[BIT_WORD(BTN_0)] |= BIT_MASK(BTN_0);
- input->keybit[BIT_WORD(BTN_1)] |= BIT_MASK(BTN_1);
- input->keybit[BIT_WORD(BTN_2)] |= BIT_MASK(BTN_2);
- input->keybit[BIT_WORD(BTN_3)] |= BIT_MASK(BTN_3);
- input->keybit[BIT_WORD(BTN_4)] |= BIT_MASK(BTN_4);
- input->keybit[BIT_WORD(BTN_5)] |= BIT_MASK(BTN_5);
- input->keybit[BIT_WORD(BTN_6)] |= BIT_MASK(BTN_6);
- input->keybit[BIT_WORD(BTN_7)] |= BIT_MASK(BTN_7);
- input->keybit[BIT_WORD(BTN_8)] |= BIT_MASK(BTN_8);
- input->keybit[BIT_WORD(BTN_9)] |= BIT_MASK(BTN_9);
-
- input->open = tfa98xx_input_open;
- input->close = tfa98xx_input_close;
-
- input->name = "tfa98xx-tapdetect";
-
- input->id.bustype = BUS_I2C;
- input_set_drvdata(input, tfa98xx);
-
- err = input_register_device(input);
- if (err) {
- dev_err(tfa98xx->codec->dev, "Unable to register input device\n");
- goto err_free_dev;
- }
-
- dev_dbg(tfa98xx->codec->dev, "Input device for tap-detection registered: %s\n",
- input->name);
- tfa98xx->input = input;
- return 0;
-
-err_free_dev:
- input_free_device(input);
- return err;
-}
-
-/*
- * Check if an input device for tap-detection can and shall be registered.
- * Register it if appropriate.
- * If already registered, check if still relevant and remove it if necessary.
- * unregister: true to request inputdev unregistration.
- */
-static void __tfa98xx_inputdev_check_register(struct tfa98xx *tfa98xx, bool unregister)
-{
- bool tap_profile = false;
- unsigned int i;
- for (i = 0; i < tfa_cnt_get_dev_nprof(tfa98xx->tfa); i++) {
- if (strstr(tfa_cont_profile_name(tfa98xx, i), ".tap")) {
- tap_profile = true;
- tfa98xx->tapdet_profiles |= 1 << i;
- dev_info(tfa98xx->codec->dev,
- "found a tap-detection profile (%d - %s)\n",
- i, tfa_cont_profile_name(tfa98xx, i));
- }
- }
-
- /* Check for device support:
- * - at device level
- * - at container (profile) level
- */
- if (!(tfa98xx->flags & TFA98XX_FLAG_TAPDET_AVAILABLE) ||
- !tap_profile ||
- unregister) {
- /* No input device supported or required */
- if (tfa98xx->input) {
- input_unregister_device(tfa98xx->input);
- tfa98xx->input = NULL;
- }
- return;
- }
-
- /* input device required */
- if (tfa98xx->input)
- dev_info(tfa98xx->codec->dev, "Input device already registered, skipping\n");
- else
- tfa98xx_register_inputdev(tfa98xx);
-}
-
-static void tfa98xx_inputdev_check_register(struct tfa98xx *tfa98xx)
-{
- __tfa98xx_inputdev_check_register(tfa98xx, false);
-}
-
-static void tfa98xx_inputdev_unregister(struct tfa98xx *tfa98xx)
-{
- __tfa98xx_inputdev_check_register(tfa98xx, true);
-}
-
-#ifdef CONFIG_DEBUG_FS
-/* OTC reporting
- * Returns the MTP0 OTC bit value
- */
-static int tfa98xx_dbgfs_otc_get(void *data, u64 *val)
-{
- struct i2c_client *i2c = (struct i2c_client *)data;
- struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
- int value;
-
- mutex_lock(&tfa98xx->dsp_lock);
- value = tfa_dev_mtp_get(tfa98xx->tfa, TFA_MTP_OTC);
- mutex_unlock(&tfa98xx->dsp_lock);
-
- if (value < 0) {
- pr_err("[0x%x] Unable to check DSP access: %d\n", tfa98xx->i2c->addr, value);
- return -EIO;
- }
-
- *val = value;
- pr_debug("[0x%x] OTC : %d\n", tfa98xx->i2c->addr, value);
-
- return 0;
-}
-
-static int tfa98xx_dbgfs_otc_set(void *data, u64 val)
-{
- struct i2c_client *i2c = (struct i2c_client *)data;
- struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
- enum tfa_error err;
-
- if (val != 0 && val != 1) {
- pr_err("[0x%x] Unexpected value %llu\n", tfa98xx->i2c->addr, val);
- return -EINVAL;
- }
-
- mutex_lock(&tfa98xx->dsp_lock);
- err = tfa_dev_mtp_set(tfa98xx->tfa, TFA_MTP_OTC, val);
- mutex_unlock(&tfa98xx->dsp_lock);
-
- if (err != tfa_error_ok) {
- pr_err("[0x%x] Unable to check DSP access: %d\n", tfa98xx->i2c->addr, err);
- return -EIO;
- }
-
- pr_debug("[0x%x] OTC < %llu\n", tfa98xx->i2c->addr, val);
-
- return 0;
-}
-
-static int tfa98xx_dbgfs_mtpex_get(void *data, u64 *val)
-{
- struct i2c_client *i2c = (struct i2c_client *)data;
- struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
- int value;
-
- mutex_lock(&tfa98xx->dsp_lock);
- value = tfa_dev_mtp_get(tfa98xx->tfa, TFA_MTP_EX);
- mutex_unlock(&tfa98xx->dsp_lock);
-
- if (value < 0) {
- pr_err("[0x%x] Unable to check DSP access: %d\n", tfa98xx->i2c->addr, value);
- return -EIO;
- }
-
-
- *val = value;
- pr_debug("[0x%x] MTPEX : %d\n", tfa98xx->i2c->addr, value);
-
- return 0;
-}
-
-static int tfa98xx_dbgfs_mtpex_set(void *data, u64 val)
-{
- struct i2c_client *i2c = (struct i2c_client *)data;
- struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
- enum tfa_error err;
-
- if (val != 0) {
- pr_err("[0x%x] Can only clear MTPEX (0 value expected)\n", tfa98xx->i2c->addr);
- return -EINVAL;
- }
-
- mutex_lock(&tfa98xx->dsp_lock);
- err = tfa_dev_mtp_set(tfa98xx->tfa, TFA_MTP_EX, val);
- mutex_unlock(&tfa98xx->dsp_lock);
-
- if (err != tfa_error_ok) {
- pr_err("[0x%x] Unable to check DSP access: %d\n", tfa98xx->i2c->addr, err);
- return -EIO;
- }
-
- pr_debug("[0x%x] MTPEX < 0\n", tfa98xx->i2c->addr);
-
- return 0;
-}
-
-static int tfa98xx_dbgfs_temp_get(void *data, u64 *val)
-{
- struct i2c_client *i2c = (struct i2c_client *)data;
- struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
-
- mutex_lock(&tfa98xx->dsp_lock);
- *val = tfa98xx_get_exttemp(tfa98xx->tfa);
- mutex_unlock(&tfa98xx->dsp_lock);
-
- pr_debug("[0x%x] TEMP : %llu\n", tfa98xx->i2c->addr, *val);
-
- return 0;
-}
-
-static int tfa98xx_dbgfs_temp_set(void *data, u64 val)
-{
- struct i2c_client *i2c = (struct i2c_client *)data;
- struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
-
- mutex_lock(&tfa98xx->dsp_lock);
- tfa98xx_set_exttemp(tfa98xx->tfa, (short)val);
- mutex_unlock(&tfa98xx->dsp_lock);
-
- pr_debug("[0x%x] TEMP < %llu\n", tfa98xx->i2c->addr, val);
-
- return 0;
-}
-
-static ssize_t tfa98xx_dbgfs_start_set(struct file *file,
- const char __user *user_buf,
- size_t count, loff_t *ppos)
-{
- struct i2c_client *i2c = file->private_data;
- struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
- enum tfa_error ret;
- char buf[32];
- const char ref[] = "please calibrate now";
- int buf_size, cal_profile = 0;
-
- /* check string length, and account for eol */
- if (count > sizeof(ref) + 1 || count < (sizeof(ref) - 1))
- return -EINVAL;
-
- buf_size = min(count, (size_t)(sizeof(buf) - 1));
- if (copy_from_user(buf, user_buf, buf_size))
- return -EFAULT;
- buf[buf_size] = 0;
-
- /* Compare string, excluding the trailing \0 and the potentials eol */
- if (strncmp(buf, ref, sizeof(ref) - 1))
- return -EINVAL;
-
- mutex_lock(&tfa98xx->dsp_lock);
- ret = tfa_calibrate(tfa98xx->tfa);
- if (ret == tfa_error_ok) {
- cal_profile = tfaContGetCalProfile(tfa98xx->tfa);
- if (cal_profile < 0) {
- pr_warn("[0x%x] Calibration profile not found\n",
- tfa98xx->i2c->addr);
- }
-
- ret = tfa98xx_tfa_start(tfa98xx, cal_profile, tfa98xx->vstep);
- }
- if (ret == tfa_error_ok)
- tfa_dev_set_state(tfa98xx->tfa, TFA_STATE_UNMUTE, 0);
- mutex_unlock(&tfa98xx->dsp_lock);
-
- if (ret) {
- pr_info("[0x%x] Calibration start failed (%d)\n", tfa98xx->i2c->addr, ret);
- return -EIO;
- }
- else {
- pr_info("[0x%x] Calibration started\n", tfa98xx->i2c->addr);
- }
-
- return count;
-}
-
-static ssize_t tfa98xx_dbgfs_r_read(struct file *file,
- char __user *user_buf, size_t count,
- loff_t *ppos)
-{
- struct i2c_client *i2c = file->private_data;
- struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
- char *str;
- uint16_t status;
- int ret;
-
- mutex_lock(&tfa98xx->dsp_lock);
-
- /* Need to ensure DSP is access-able, use mtp read access for this
- * purpose
- */
- ret = tfa98xx_get_mtp(tfa98xx->tfa, &status);
- if (ret) {
- ret = -EIO;
- pr_err("[0x%x] MTP read failed\n", tfa98xx->i2c->addr);
- goto r_c_err;
- }
-
- ret = tfaRunSpeakerCalibration(tfa98xx->tfa);
- if (ret) {
- ret = -EIO;
- pr_err("[0x%x] calibration failed\n", tfa98xx->i2c->addr);
- goto r_c_err;
- }
-
- str = kmalloc(PAGE_SIZE, GFP_KERNEL);
- if (!str) {
- ret = -ENOMEM;
- pr_err("[0x%x] memory allocation failed\n", tfa98xx->i2c->addr);
- goto r_c_err;
- }
-
- if (tfa98xx->tfa->spkr_count > 1) {
- ret = snprintf(str, PAGE_SIZE,
- "Prim:%d mOhms, Sec:%d mOhms\n",
- tfa98xx->tfa->mohm[0],
- tfa98xx->tfa->mohm[1]);
- }
- else {
- ret = snprintf(str, PAGE_SIZE,
- "Prim:%d mOhms\n",
- tfa98xx->tfa->mohm[0]);
- }
-
- pr_debug("[0x%x] calib_done: %s", tfa98xx->i2c->addr, str);
-
- if (ret < 0)
- goto r_err;
-
- ret = simple_read_from_buffer(user_buf, count, ppos, str, ret);
-
-r_err:
- kfree(str);
-r_c_err:
- mutex_unlock(&tfa98xx->dsp_lock);
- return ret;
-}
-
-static ssize_t tfa98xx_dbgfs_version_read(struct file *file,
- char __user *user_buf, size_t count,
- loff_t *ppos)
-{
- char str[] = TFA98XX_VERSION "\n";
- int ret;
-
- ret = simple_read_from_buffer(user_buf, count, ppos, str, sizeof(str));
-
- return ret;
-}
-
-static ssize_t tfa98xx_dbgfs_dsp_state_get(struct file *file,
- char __user *user_buf, size_t count,
- loff_t *ppos)
-{
- struct i2c_client *i2c = file->private_data;
- struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
- int ret = 0;
- char *str;
-
- switch (tfa98xx->dsp_init) {
- case TFA98XX_DSP_INIT_STOPPED:
- str = "Stopped\n";
- break;
- case TFA98XX_DSP_INIT_RECOVER:
- str = "Recover requested\n";
- break;
- case TFA98XX_DSP_INIT_FAIL:
- str = "Failed init\n";
- break;
- case TFA98XX_DSP_INIT_PENDING:
- str = "Pending init\n";
- break;
- case TFA98XX_DSP_INIT_DONE:
- str = "Init complete\n";
- break;
- default:
- str = "Invalid\n";
- }
-
- pr_debug("[0x%x] dsp_state : %s\n", tfa98xx->i2c->addr, str);
-
- ret = simple_read_from_buffer(user_buf, count, ppos, str, strlen(str));
- return ret;
-}
-
-static ssize_t tfa98xx_dbgfs_dsp_state_set(struct file *file,
- const char __user *user_buf,
- size_t count, loff_t *ppos)
-{
- struct i2c_client *i2c = file->private_data;
- struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
- enum tfa_error ret;
- char buf[32];
- const char start_cmd[] = "start";
- const char stop_cmd[] = "stop";
- const char mon_start_cmd[] = "monitor start";
- const char mon_stop_cmd[] = "monitor stop";
- int buf_size;
-
- buf_size = min(count, (size_t)(sizeof(buf) - 1));
- if (copy_from_user(buf, user_buf, buf_size))
- return -EFAULT;
- buf[buf_size] = 0;
-
- /* Compare strings, excluding the trailing \0 */
- if (!strncmp(buf, start_cmd, sizeof(start_cmd) - 1)) {
- pr_info("[0x%x] Manual triggering of dsp start...\n", tfa98xx->i2c->addr);
- mutex_lock(&tfa98xx->dsp_lock);
- ret = tfa98xx_tfa_start(tfa98xx, tfa98xx->profile, tfa98xx->vstep);
- mutex_unlock(&tfa98xx->dsp_lock);
- pr_debug("[0x%x] tfa_dev_start complete: %d\n", tfa98xx->i2c->addr, ret);
- }
- else if (!strncmp(buf, stop_cmd, sizeof(stop_cmd) - 1)) {
- pr_info("[0x%x] Manual triggering of dsp stop...\n", tfa98xx->i2c->addr);
- mutex_lock(&tfa98xx->dsp_lock);
- ret = tfa_dev_stop(tfa98xx->tfa);
- mutex_unlock(&tfa98xx->dsp_lock);
- pr_debug("[0x%x] tfa_dev_stop complete: %d\n", tfa98xx->i2c->addr, ret);
- }
- else if (!strncmp(buf, mon_start_cmd, sizeof(mon_start_cmd) - 1)) {
- pr_info("[0x%x] Manual start of monitor thread...\n", tfa98xx->i2c->addr);
- queue_delayed_work(tfa98xx->tfa98xx_wq,
- &tfa98xx->monitor_work, HZ);
- }
- else if (!strncmp(buf, mon_stop_cmd, sizeof(mon_stop_cmd) - 1)) {
- pr_info("[0x%x] Manual stop of monitor thread...\n", tfa98xx->i2c->addr);
- cancel_delayed_work_sync(&tfa98xx->monitor_work);
- }
- else {
- return -EINVAL;
- }
-
- return count;
-}
-
-static ssize_t tfa98xx_dbgfs_fw_state_get(struct file *file,
- char __user *user_buf, size_t count,
- loff_t *ppos)
-{
- struct i2c_client *i2c = file->private_data;
- struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
- char *str;
-
- switch (tfa98xx->dsp_fw_state) {
- case TFA98XX_DSP_FW_NONE:
- str = "None\n";
- break;
- case TFA98XX_DSP_FW_PENDING:
- str = "Pending\n";
- break;
- case TFA98XX_DSP_FW_FAIL:
- str = "Fail\n";
- break;
- case TFA98XX_DSP_FW_OK:
- str = "Ok\n";
- break;
- default:
- str = "Invalid\n";
- }
-
- pr_debug("[0x%x] fw_state : %s", tfa98xx->i2c->addr, str);
-
- return simple_read_from_buffer(user_buf, count, ppos, str, strlen(str));
-}
-
-static ssize_t tfa98xx_dbgfs_rpc_read(struct file *file,
- char __user *user_buf, size_t count,
- loff_t *ppos)
-{
- struct i2c_client *i2c = file->private_data;
- struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
- int ret = 0;
- uint8_t *buffer;
- enum Tfa98xx_Error error;
-
- if (tfa98xx->tfa == NULL) {
- pr_debug("[0x%x] dsp is not available\n", tfa98xx->i2c->addr);
- return -ENODEV;
- }
-
- if (count == 0)
- return 0;
-
- buffer = kmalloc(count, GFP_KERNEL);
- if (buffer == NULL) {
- pr_debug("[0x%x] can not allocate memory\n", tfa98xx->i2c->addr);
- return -ENOMEM;
- }
-
- mutex_lock(&tfa98xx->dsp_lock);
- error = dsp_msg_read(tfa98xx->tfa, count, buffer);
- mutex_unlock(&tfa98xx->dsp_lock);
- if (error != Tfa98xx_Error_Ok) {
- pr_debug("[0x%x] dsp_msg_read error: %d\n", tfa98xx->i2c->addr, error);
- kfree(buffer);
- return -EFAULT;
- }
-
- ret = copy_to_user(user_buf, buffer, count);
- kfree(buffer);
- if (ret)
- return -EFAULT;
-
- *ppos += count;
- return count;
-}
-
-static ssize_t tfa98xx_dbgfs_rpc_send(struct file *file,
- const char __user *user_buf,
- size_t count, loff_t *ppos)
-{
- struct i2c_client *i2c = file->private_data;
- struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
- nxpTfaFileDsc_t *msg_file;
- enum Tfa98xx_Error error;
- int err = 0;
-
- if (tfa98xx->tfa == NULL) {
- pr_debug("[0x%x] dsp is not available\n", tfa98xx->i2c->addr);
- return -ENODEV;
- }
-
- if (count == 0)
- return 0;
-
- /* msg_file.name is not used */
- msg_file = kmalloc(count + sizeof(nxpTfaFileDsc_t), GFP_KERNEL);
- if (msg_file == NULL) {
- pr_debug("[0x%x] can not allocate memory\n", tfa98xx->i2c->addr);
- return -ENOMEM;
- }
- msg_file->size = count;
-
- if (copy_from_user(msg_file->data, user_buf, count))
- return -EFAULT;
-
- mutex_lock(&tfa98xx->dsp_lock);
- if ((msg_file->data[0] == 'M') && (msg_file->data[1] == 'G')) {
- error = tfaContWriteFile(tfa98xx->tfa, msg_file, 0, 0); /* int vstep_idx, int vstep_msg_idx both 0 */
- if (error != Tfa98xx_Error_Ok) {
- pr_debug("[0x%x] tfaContWriteFile error: %d\n", tfa98xx->i2c->addr, error);
- err = -EIO;
- }
- }
- else {
- error = dsp_msg(tfa98xx->tfa, msg_file->size, msg_file->data);
- if (error != Tfa98xx_Error_Ok) {
- pr_debug("[0x%x] dsp_msg error: %d\n", tfa98xx->i2c->addr, error);
- err = -EIO;
- }
- }
- mutex_unlock(&tfa98xx->dsp_lock);
-
- kfree(msg_file);
-
- if (err)
- return err;
- return count;
-}
-/* -- RPC */
-
-static int tfa98xx_dbgfs_pga_gain_get(void *data, u64 *val)
-{
- struct i2c_client *i2c = (struct i2c_client *)data;
- struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
- unsigned int value;
-
- value = tfa_get_pga_gain(tfa98xx->tfa);
- if (value < 0)
- return -EINVAL;
-
- *val = value;
- return 0;
-}
-
-static int tfa98xx_dbgfs_pga_gain_set(void *data, u64 val)
-{
- struct i2c_client *i2c = (struct i2c_client *)data;
- struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
- uint16_t value;
- int err;
-
- value = val & 0xffff;
- if (value > 7)
- return -EINVAL;
-
- err = tfa_set_pga_gain(tfa98xx->tfa, value);
- if (err < 0)
- return -EINVAL;
-
- return 0;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(tfa98xx_dbgfs_calib_otc_fops, tfa98xx_dbgfs_otc_get,
- tfa98xx_dbgfs_otc_set, "%llu\n");
-DEFINE_SIMPLE_ATTRIBUTE(tfa98xx_dbgfs_calib_mtpex_fops, tfa98xx_dbgfs_mtpex_get,
- tfa98xx_dbgfs_mtpex_set, "%llu\n");
-DEFINE_SIMPLE_ATTRIBUTE(tfa98xx_dbgfs_calib_temp_fops, tfa98xx_dbgfs_temp_get,
- tfa98xx_dbgfs_temp_set, "%llu\n");
-
-DEFINE_SIMPLE_ATTRIBUTE(tfa98xx_dbgfs_pga_gain_fops, tfa98xx_dbgfs_pga_gain_get,
- tfa98xx_dbgfs_pga_gain_set, "%llu\n");
-
-static const struct file_operations tfa98xx_dbgfs_calib_start_fops = {
- .owner = THIS_MODULE,
- .open = simple_open,
- .write = tfa98xx_dbgfs_start_set,
- .llseek = default_llseek,
-};
-
-static const struct file_operations tfa98xx_dbgfs_r_fops = {
- .owner = THIS_MODULE,
- .open = simple_open,
- .read = tfa98xx_dbgfs_r_read,
- .llseek = default_llseek,
-};
-
-static const struct file_operations tfa98xx_dbgfs_version_fops = {
- .owner = THIS_MODULE,
- .open = simple_open,
- .read = tfa98xx_dbgfs_version_read,
- .llseek = default_llseek,
-};
-
-static const struct file_operations tfa98xx_dbgfs_dsp_state_fops = {
- .owner = THIS_MODULE,
- .open = simple_open,
- .read = tfa98xx_dbgfs_dsp_state_get,
- .write = tfa98xx_dbgfs_dsp_state_set,
- .llseek = default_llseek,
-};
-
-static const struct file_operations tfa98xx_dbgfs_fw_state_fops = {
- .owner = THIS_MODULE,
- .open = simple_open,
- .read = tfa98xx_dbgfs_fw_state_get,
- .llseek = default_llseek,
-};
-
-static const struct file_operations tfa98xx_dbgfs_rpc_fops = {
- .owner = THIS_MODULE,
- .open = simple_open,
- .read = tfa98xx_dbgfs_rpc_read,
- .write = tfa98xx_dbgfs_rpc_send,
- .llseek = default_llseek,
-};
-
-static void tfa98xx_debug_init(struct tfa98xx *tfa98xx, struct i2c_client *i2c)
-{
- char name[50];
-
- scnprintf(name, MAX_CONTROL_NAME, "%s-%x", i2c->name, i2c->addr);
- tfa98xx->dbg_dir = debugfs_create_dir(name, NULL);
- debugfs_create_file("OTC", S_IRUGO | S_IWUGO, tfa98xx->dbg_dir,
- i2c, &tfa98xx_dbgfs_calib_otc_fops);
- debugfs_create_file("MTPEX", S_IRUGO | S_IWUGO, tfa98xx->dbg_dir,
- i2c, &tfa98xx_dbgfs_calib_mtpex_fops);
- debugfs_create_file("TEMP", S_IRUGO | S_IWUGO, tfa98xx->dbg_dir,
- i2c, &tfa98xx_dbgfs_calib_temp_fops);
- debugfs_create_file("calibrate", S_IRUGO | S_IWUGO, tfa98xx->dbg_dir,
- i2c, &tfa98xx_dbgfs_calib_start_fops);
- debugfs_create_file("R", S_IRUGO, tfa98xx->dbg_dir,
- i2c, &tfa98xx_dbgfs_r_fops);
- debugfs_create_file("version", S_IRUGO, tfa98xx->dbg_dir,
- i2c, &tfa98xx_dbgfs_version_fops);
- debugfs_create_file("dsp-state", S_IRUGO | S_IWUGO, tfa98xx->dbg_dir,
- i2c, &tfa98xx_dbgfs_dsp_state_fops);
- debugfs_create_file("fw-state", S_IRUGO | S_IWUGO, tfa98xx->dbg_dir,
- i2c, &tfa98xx_dbgfs_fw_state_fops);
- debugfs_create_file("rpc", S_IRUGO | S_IWUGO, tfa98xx->dbg_dir,
- i2c, &tfa98xx_dbgfs_rpc_fops);
-
- if (tfa98xx->flags & TFA98XX_FLAG_SAAM_AVAILABLE) {
- dev_dbg(tfa98xx->dev, "Adding pga_gain debug interface\n");
- debugfs_create_file("pga_gain", S_IRUGO, tfa98xx->dbg_dir,
- tfa98xx->i2c,
- &tfa98xx_dbgfs_pga_gain_fops);
- }
-}
-
-static void tfa98xx_debug_remove(struct tfa98xx *tfa98xx)
-{
- if (tfa98xx->dbg_dir)
- debugfs_remove_recursive(tfa98xx->dbg_dir);
-}
-#endif
-
-
-/* copies the profile basename (i.e. part until .) into buf */
-static void get_profile_basename(char* buf, char* profile)
-{
- int cp_len = 0, idx = 0;
- char *pch;
-
- pch = strchr(profile, '.');
- idx = pch - profile;
- cp_len = (pch != NULL) ? idx : (int)strlen(profile);
- memcpy(buf, profile, cp_len);
- buf[cp_len] = 0;
-}
-
-/* return the profile name accociated with id from the profile list */
-static int get_profile_from_list(char *buf, int id)
-{
- struct tfa98xx_baseprofile *bprof;
-
- list_for_each_entry(bprof, &profile_list, list) {
- if (bprof->item_id == id) {
- strcpy(buf, bprof->basename);
- return 0;
- }
- }
-
- return -1;
-}
-
-/* search for the profile in the profile list */
-static int is_profile_in_list(char *profile, int len)
-{
- struct tfa98xx_baseprofile *bprof;
-
- list_for_each_entry(bprof, &profile_list, list) {
-
- if ((len == bprof->len) && (0 == strncmp(bprof->basename, profile, len)))
- return 1;
- }
-
- return 0;
-}
-
-/*
- * for the profile with id, look if the requested samplerate is
- * supported, if found return the (container)profile for this
- * samplerate, on error or if not found return -1
- */
-static int get_profile_id_for_sr(int id, unsigned int rate)
-{
- int idx = 0;
- struct tfa98xx_baseprofile *bprof;
-
- list_for_each_entry(bprof, &profile_list, list) {
- if (id == bprof->item_id) {
- idx = tfa98xx_get_fssel(rate);
- if (idx < 0) {
- /* samplerate not supported */
- return -1;
- }
-
- return bprof->sr_rate_sup[idx];
- }
- }
-
- /* profile not found */
- return -1;
-}
-
-/* check if this profile is a calibration profile */
-static int is_calibration_profile(char *profile)
-{
- if (strstr(profile, ".cal") != NULL)
- return 1;
- return 0;
-}
-
-/*
- * adds the (container)profile index of the samplerate found in
- * the (container)profile to a fixed samplerate table in the (mixer)profile
- */
-static int add_sr_to_profile(struct tfa98xx *tfa98xx, char *basename, int len, int profile)
-{
- struct tfa98xx_baseprofile *bprof;
- int idx = 0;
- unsigned int sr = 0;
-
- list_for_each_entry(bprof, &profile_list, list) {
- if ((len == bprof->len) && (0 == strncmp(bprof->basename, basename, len))) {
- /* add supported samplerate for this profile */
- sr = tfa98xx_get_profile_sr(tfa98xx->tfa, profile);
- if (!sr) {
- pr_err("unable to identify supported sample rate for %s\n", bprof->basename);
- return -1;
- }
-
- /* get the index for this samplerate */
- idx = tfa98xx_get_fssel(sr);
- if (idx < 0 || idx >= TFA98XX_NUM_RATES) {
- pr_err("invalid index for samplerate %d\n", idx);
- return -1;
- }
-
- /* enter the (container)profile for this samplerate at the corresponding index */
- bprof->sr_rate_sup[idx] = profile;
-
- pr_debug("added profile:samplerate = [%d:%d] for mixer profile: %s\n", profile, sr, bprof->basename);
- }
- }
-
- return 0;
-}
-
-#if LINUX_VERSION_CODE < KERNEL_VERSION(3,16,0)
-static struct snd_soc_codec *snd_soc_kcontrol_codec(struct snd_kcontrol *kcontrol)
-{
- return snd_kcontrol_chip(kcontrol);
-}
-#endif
-
-static int tfa98xx_get_vstep(struct snd_kcontrol *kcontrol,
- struct snd_ctl_elem_value *ucontrol)
-{
- struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
- struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec);
- int mixer_profile = kcontrol->private_value;
- int ret = 0;
- int profile;
-
- profile = get_profile_id_for_sr(mixer_profile, tfa98xx->rate);
- if (profile < 0) {
- pr_err("tfa98xx: tfa98xx_get_vstep: invalid profile %d (mixer_profile=%d, rate=%d)\n", profile, mixer_profile, tfa98xx->rate);
- return -EINVAL;
- }
-
- mutex_lock(&tfa98xx_mutex);
- list_for_each_entry(tfa98xx, &tfa98xx_device_list, list) {
- int vstep = tfa98xx->prof_vsteps[profile];
-
- ucontrol->value.integer.value[tfa98xx->tfa->dev_idx] =
- tfacont_get_max_vstep(tfa98xx->tfa, profile)
- - vstep - 1;
- }
- mutex_unlock(&tfa98xx_mutex);
-
- return ret;
-}
-
-static int tfa98xx_set_vstep(struct snd_kcontrol *kcontrol,
- struct snd_ctl_elem_value *ucontrol)
-{
- struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
- struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec);
- int mixer_profile = kcontrol->private_value;
- int profile;
- int err = 0;
- int change = 0;
-
- if (no_start != 0)
- return 0;
-
- profile = get_profile_id_for_sr(mixer_profile, tfa98xx->rate);
- if (profile < 0) {
- pr_err("tfa98xx: tfa98xx_set_vstep: invalid profile %d (mixer_profile=%d, rate=%d)\n", profile, mixer_profile, tfa98xx->rate);
- return -EINVAL;
- }
-
- mutex_lock(&tfa98xx_mutex);
- list_for_each_entry(tfa98xx, &tfa98xx_device_list, list) {
- int vstep, vsteps;
- int ready = 0;
- int new_vstep;
- int value = ucontrol->value.integer.value[tfa98xx->tfa->dev_idx];
-
- vstep = tfa98xx->prof_vsteps[profile];
- vsteps = tfacont_get_max_vstep(tfa98xx->tfa, profile);
-
- if (vstep == vsteps - value - 1)
- continue;
-
- new_vstep = vsteps - value - 1;
-
- if (new_vstep < 0)
- new_vstep = 0;
-
- tfa98xx->prof_vsteps[profile] = new_vstep;
-
-#ifndef TFA98XX_ALSA_CTRL_PROF_CHG_ON_VOL
- if (profile == tfa98xx->profile) {
-#endif
- /* this is the active profile, program the new vstep */
- tfa98xx->vstep = new_vstep;
- mutex_lock(&tfa98xx->dsp_lock);
- tfa98xx_dsp_system_stable(tfa98xx->tfa, &ready);
-
- if (ready) {
- err = tfa98xx_tfa_start(tfa98xx, tfa98xx->profile, tfa98xx->vstep);
- if (err) {
- pr_err("Write vstep error: %d\n", err);
- }
- else {
- pr_debug("Succesfully changed vstep index!\n");
- change = 1;
- }
- }
-
- mutex_unlock(&tfa98xx->dsp_lock);
-#ifndef TFA98XX_ALSA_CTRL_PROF_CHG_ON_VOL
- }
-#endif
- pr_debug("%d: vstep:%d, (control value: %d) - profile %d\n",
- tfa98xx->tfa->dev_idx, new_vstep, value, profile);
- }
-
- if (change) {
- list_for_each_entry(tfa98xx, &tfa98xx_device_list, list) {
- mutex_lock(&tfa98xx->dsp_lock);
- tfa_dev_set_state(tfa98xx->tfa, TFA_STATE_UNMUTE, 0);
- mutex_unlock(&tfa98xx->dsp_lock);
- }
- }
-
- mutex_unlock(&tfa98xx_mutex);
-
- return change;
-}
-
-static int tfa98xx_info_vstep(struct snd_kcontrol *kcontrol,
- struct snd_ctl_elem_info *uinfo)
-{
- struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
- struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec);
-
- int mixer_profile = tfa98xx_mixer_profile;
- int profile = get_profile_id_for_sr(mixer_profile, tfa98xx->rate);
- if (profile < 0) {
- pr_err("tfa98xx: tfa98xx_info_vstep: invalid profile %d (mixer_profile=%d, rate=%d)\n", profile, mixer_profile, tfa98xx->rate);
- return -EINVAL;
- }
-
- uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
- mutex_lock(&tfa98xx_mutex);
- uinfo->count = tfa98xx_device_count;
- mutex_unlock(&tfa98xx_mutex);
- uinfo->value.integer.min = 0;
- uinfo->value.integer.max = max(0, tfacont_get_max_vstep(tfa98xx->tfa, profile) - 1);
- pr_debug("vsteps count: %d [prof=%d]\n", tfacont_get_max_vstep(tfa98xx->tfa, profile),
- profile);
- return 0;
-}
-
-static int tfa98xx_get_profile(struct snd_kcontrol *kcontrol,
- struct snd_ctl_elem_value *ucontrol)
-{
- mutex_lock(&tfa98xx_mutex);
- ucontrol->value.integer.value[0] = tfa98xx_mixer_profile;
- mutex_unlock(&tfa98xx_mutex);
-
- return 0;
-}
-
-static int tfa98xx_set_profile(struct snd_kcontrol *kcontrol,
- struct snd_ctl_elem_value *ucontrol)
-{
- struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
- struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec);
- int change = 0;
- int new_profile;
- int prof_idx;
- int profile_count = tfa98xx_mixer_profiles;
- int profile = tfa98xx_mixer_profile;
-
- if (no_start != 0)
- return 0;
-
- new_profile = ucontrol->value.integer.value[0];
- if (new_profile == profile)
- return 0;
-
- if ((new_profile < 0) || (new_profile >= profile_count)) {
- pr_err("not existing profile (%d)\n", new_profile);
- return -EINVAL;
- }
-
- /* get the container profile for the requested sample rate */
- prof_idx = get_profile_id_for_sr(new_profile, tfa98xx->rate);
- if (prof_idx < 0) {
- pr_err("tfa98xx: sample rate [%d] not supported for this mixer profile [%d].\n", tfa98xx->rate, new_profile);
- return 0;
- }
- pr_debug("selected container profile [%d]\n", prof_idx);
-
- /* update mixer profile */
- tfa98xx_mixer_profile = new_profile;
-
- mutex_lock(&tfa98xx_mutex);
- list_for_each_entry(tfa98xx, &tfa98xx_device_list, list) {
- int err;
- int ready = 0;
-
- /* update 'real' profile (container profile) */
- tfa98xx->profile = prof_idx;
- tfa98xx->vstep = tfa98xx->prof_vsteps[prof_idx];
-
- /* Don't call tfa_dev_start() if there is no clock. */
- mutex_lock(&tfa98xx->dsp_lock);
- tfa98xx_dsp_system_stable(tfa98xx->tfa, &ready);
- if (ready) {
- /* Also re-enables the interrupts */
- err = tfa98xx_tfa_start(tfa98xx, prof_idx, tfa98xx->vstep);
- if (err) {
- pr_info("Write profile error: %d\n", err);
- }
- else {
- pr_debug("Changed to profile %d (vstep = %d)\n",
- prof_idx, tfa98xx->vstep);
- change = 1;
- }
- }
- mutex_unlock(&tfa98xx->dsp_lock);
-
- /* Flag DSP as invalidated as the profile change may invalidate the
- * current DSP configuration. That way, further stream start can
- * trigger a tfa_dev_start.
- */
- tfa98xx->dsp_init = TFA98XX_DSP_INIT_INVALIDATED;
- }
-
- if (change) {
- list_for_each_entry(tfa98xx, &tfa98xx_device_list, list) {
- mutex_lock(&tfa98xx->dsp_lock);
- tfa_dev_set_state(tfa98xx->tfa, TFA_STATE_UNMUTE, 0);
- mutex_unlock(&tfa98xx->dsp_lock);
- }
- }
-
- mutex_unlock(&tfa98xx_mutex);
-
- return change;
-}
-
-static int tfa98xx_info_profile(struct snd_kcontrol *kcontrol,
- struct snd_ctl_elem_info *uinfo)
-{
- char profile_name[MAX_CONTROL_NAME] = { 0 };
- int count = tfa98xx_mixer_profiles, err = -1;
-
- uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
- uinfo->count = 1;
- uinfo->value.enumerated.items = count;
-
- if (uinfo->value.enumerated.item >= count)
- uinfo->value.enumerated.item = count - 1;
-
- err = get_profile_from_list(profile_name, uinfo->value.enumerated.item);
- if (err != 0)
- return -EINVAL;
-
- strcpy(uinfo->value.enumerated.name, profile_name);
-
- return 0;
-}
-
-static int tfa98xx_info_stop_ctl(struct snd_kcontrol *kcontrol,
- struct snd_ctl_elem_info *uinfo)
-{
- uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
- mutex_lock(&tfa98xx_mutex);
- uinfo->count = tfa98xx_device_count;
- mutex_unlock(&tfa98xx_mutex);
- uinfo->value.integer.min = 0;
- uinfo->value.integer.max = 1;
-
- return 0;
-}
-
-static int tfa98xx_get_stop_ctl(struct snd_kcontrol *kcontrol,
- struct snd_ctl_elem_value *ucontrol)
-{
- struct tfa98xx *tfa98xx;
-
- mutex_lock(&tfa98xx_mutex);
- list_for_each_entry(tfa98xx, &tfa98xx_device_list, list) {
- ucontrol->value.integer.value[tfa98xx->tfa->dev_idx] = 0;
- }
- mutex_unlock(&tfa98xx_mutex);
-
- return 0;
-}
-
-static int tfa98xx_set_stop_ctl(struct snd_kcontrol *kcontrol,
- struct snd_ctl_elem_value *ucontrol)
-{
- struct tfa98xx *tfa98xx;
-
- mutex_lock(&tfa98xx_mutex);
- list_for_each_entry(tfa98xx, &tfa98xx_device_list, list) {
- int ready = 0;
- int i = tfa98xx->tfa->dev_idx;
-
- pr_debug("%d: %ld\n", i, ucontrol->value.integer.value[i]);
-
- tfa98xx_dsp_system_stable(tfa98xx->tfa, &ready);
-
- if ((ucontrol->value.integer.value[i] != 0) && ready) {
- cancel_delayed_work_sync(&tfa98xx->monitor_work);
-
- cancel_delayed_work_sync(&tfa98xx->init_work);
- if (tfa98xx->dsp_fw_state != TFA98XX_DSP_FW_OK)
- continue;
-
- mutex_lock(&tfa98xx->dsp_lock);
- tfa_dev_stop(tfa98xx->tfa);
- tfa98xx->dsp_init = TFA98XX_DSP_INIT_STOPPED;
- mutex_unlock(&tfa98xx->dsp_lock);
- }
-
- ucontrol->value.integer.value[i] = 0;
- }
- mutex_unlock(&tfa98xx_mutex);
-
- return 1;
-}
-
-static int tfa98xx_info_cal_ctl(struct snd_kcontrol *kcontrol,
- struct snd_ctl_elem_info *uinfo)
-{
- uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
- mutex_lock(&tfa98xx_mutex);
- uinfo->count = tfa98xx_device_count;
- mutex_unlock(&tfa98xx_mutex);
- uinfo->value.integer.min = 0;
- uinfo->value.integer.max = 0xffff; /* 16 bit value */
-
- return 0;
-}
-
-static int tfa98xx_set_cal_ctl(struct snd_kcontrol *kcontrol,
- struct snd_ctl_elem_value *ucontrol)
-{
- struct tfa98xx *tfa98xx;
-
- mutex_lock(&tfa98xx_mutex);
- list_for_each_entry(tfa98xx, &tfa98xx_device_list, list) {
- enum tfa_error err;
- int i = tfa98xx->tfa->dev_idx;
-
- tfa98xx->cal_data = (uint16_t)ucontrol->value.integer.value[i];
-
- mutex_lock(&tfa98xx->dsp_lock);
- err = tfa98xx_write_re25(tfa98xx->tfa, tfa98xx->cal_data);
- tfa98xx->set_mtp_cal = (err != tfa_error_ok);
- if (tfa98xx->set_mtp_cal == false) {
- pr_info("Calibration value (%d) set in mtp\n",
- tfa98xx->cal_data);
- }
- mutex_unlock(&tfa98xx->dsp_lock);
- }
- mutex_unlock(&tfa98xx_mutex);
-
- return 1;
-}
-
-static int tfa98xx_get_cal_ctl(struct snd_kcontrol *kcontrol,
- struct snd_ctl_elem_value *ucontrol)
-{
- struct tfa98xx *tfa98xx;
-
- mutex_lock(&tfa98xx_mutex);
- list_for_each_entry(tfa98xx, &tfa98xx_device_list, list) {
- mutex_lock(&tfa98xx->dsp_lock);
- ucontrol->value.integer.value[tfa98xx->tfa->dev_idx] = tfa_dev_mtp_get(tfa98xx->tfa, TFA_MTP_RE25_PRIM);
- mutex_unlock(&tfa98xx->dsp_lock);
- }
- mutex_unlock(&tfa98xx_mutex);
-
- return 0;
-}
-
-static int tfa98xx_create_controls(struct tfa98xx *tfa98xx)
-{
- int prof, nprof, mix_index = 0;
- int nr_controls = 0, id = 0;
- char *name;
- struct tfa98xx_baseprofile *bprofile;
-
- /* Create the following controls:
- * - enum control to select the active profile
- * - one volume control for each profile hosting a vstep
- * - Stop control on TFA1 devices
- */
-
- nr_controls = 2; /* Profile and stop control */
-
- if (tfa98xx->flags & TFA98XX_FLAG_CALIBRATION_CTL)
- nr_controls += 1; /* calibration */
-
- /* allocate the tfa98xx_controls base on the nr of profiles */
- nprof = tfa_cnt_get_dev_nprof(tfa98xx->tfa);
- for (prof = 0; prof < nprof; prof++) {
- if (tfacont_get_max_vstep(tfa98xx->tfa, prof))
- nr_controls++; /* Playback Volume control */
- }
-
- tfa98xx_controls = devm_kzalloc(tfa98xx->codec->dev,
- nr_controls * sizeof(tfa98xx_controls[0]), GFP_KERNEL);
- if (!tfa98xx_controls)
- return -ENOMEM;
-
- /* Create a mixer item for selecting the active profile */
- name = devm_kzalloc(tfa98xx->codec->dev, MAX_CONTROL_NAME, GFP_KERNEL);
- if (!name)
- return -ENOMEM;
- scnprintf(name, MAX_CONTROL_NAME, "%s Profile", tfa98xx->fw.name);
- tfa98xx_controls[mix_index].name = name;
- tfa98xx_controls[mix_index].iface = SNDRV_CTL_ELEM_IFACE_MIXER;
- tfa98xx_controls[mix_index].info = tfa98xx_info_profile;
- tfa98xx_controls[mix_index].get = tfa98xx_get_profile;
- tfa98xx_controls[mix_index].put = tfa98xx_set_profile;
- // tfa98xx_controls[mix_index].private_value = profs; /* save number of profiles */
- mix_index++;
-
- /* create mixer items for each profile that has volume */
- for (prof = 0; prof < nprof; prof++) {
- /* create an new empty profile */
- bprofile = devm_kzalloc(tfa98xx->codec->dev, sizeof(*bprofile), GFP_KERNEL);
- if (!bprofile)
- return -ENOMEM;
-
- bprofile->len = 0;
- bprofile->item_id = -1;
- INIT_LIST_HEAD(&bprofile->list);
-
- /* copy profile name into basename until the . */
- get_profile_basename(bprofile->basename, tfa_cont_profile_name(tfa98xx, prof));
- bprofile->len = strlen(bprofile->basename);
-
- /*
- * search the profile list for a profile with basename, if it is not found then
- * add it to the list and add a new mixer control (if it has vsteps)
- * also, if it is a calibration profile, do not add it to the list
- */
- if ((is_profile_in_list(bprofile->basename, bprofile->len) == 0) &&
- is_calibration_profile(tfa_cont_profile_name(tfa98xx, prof)) == 0) {
- /* the profile is not present, add it to the list */
- list_add(&bprofile->list, &profile_list);
- bprofile->item_id = id++;
-
- pr_debug("profile added [%d]: %s\n", bprofile->item_id, bprofile->basename);
-
- if (tfacont_get_max_vstep(tfa98xx->tfa, prof)) {
- name = devm_kzalloc(tfa98xx->codec->dev, MAX_CONTROL_NAME, GFP_KERNEL);
- if (!name)
- return -ENOMEM;
-
- scnprintf(name, MAX_CONTROL_NAME, "%s %s Playback Volume",
- tfa98xx->fw.name, bprofile->basename);
-
- tfa98xx_controls[mix_index].name = name;
- tfa98xx_controls[mix_index].iface = SNDRV_CTL_ELEM_IFACE_MIXER;
- tfa98xx_controls[mix_index].info = tfa98xx_info_vstep;
- tfa98xx_controls[mix_index].get = tfa98xx_get_vstep;
- tfa98xx_controls[mix_index].put = tfa98xx_set_vstep;
- tfa98xx_controls[mix_index].private_value = bprofile->item_id; /* save profile index */
- mix_index++;
- }
- }
-
- /* look for the basename profile in the list of mixer profiles and add the
- container profile index to the supported samplerates of this mixer profile */
- add_sr_to_profile(tfa98xx, bprofile->basename, bprofile->len, prof);
- }
-
- /* set the number of user selectable profiles in the mixer */
- tfa98xx_mixer_profiles = id;
-
- /* Create a mixer item for stop control on TFA1 */
- name = devm_kzalloc(tfa98xx->codec->dev, MAX_CONTROL_NAME, GFP_KERNEL);
- if (!name)
- return -ENOMEM;
-
- scnprintf(name, MAX_CONTROL_NAME, "%s Stop", tfa98xx->fw.name);
- tfa98xx_controls[mix_index].name = name;
- tfa98xx_controls[mix_index].iface = SNDRV_CTL_ELEM_IFACE_MIXER;
- tfa98xx_controls[mix_index].info = tfa98xx_info_stop_ctl;
- tfa98xx_controls[mix_index].get = tfa98xx_get_stop_ctl;
- tfa98xx_controls[mix_index].put = tfa98xx_set_stop_ctl;
- mix_index++;
-
- if (tfa98xx->flags & TFA98XX_FLAG_CALIBRATION_CTL) {
- name = devm_kzalloc(tfa98xx->codec->dev, MAX_CONTROL_NAME, GFP_KERNEL);
- if (!name)
- return -ENOMEM;
-
- scnprintf(name, MAX_CONTROL_NAME, "%s Calibration", tfa98xx->fw.name);
- tfa98xx_controls[mix_index].name = name;
- tfa98xx_controls[mix_index].iface = SNDRV_CTL_ELEM_IFACE_MIXER;
- tfa98xx_controls[mix_index].info = tfa98xx_info_cal_ctl;
- tfa98xx_controls[mix_index].get = tfa98xx_get_cal_ctl;
- tfa98xx_controls[mix_index].put = tfa98xx_set_cal_ctl;
- mix_index++;
- }
-
- return snd_soc_add_codec_controls(tfa98xx->codec,
- tfa98xx_controls, mix_index);
-}
-
-static void *tfa98xx_devm_kstrdup(struct device *dev, char *buf)
-{
- char *str = devm_kzalloc(dev, strlen(buf) + 1, GFP_KERNEL);
- if (!str)
- return str;
- memcpy(str, buf, strlen(buf));
- return str;
-}
-
-static int tfa98xx_append_i2c_address(struct device *dev,
- struct i2c_client *i2c,
- struct snd_soc_dapm_widget *widgets,
- int num_widgets,
- struct snd_soc_dai_driver *dai_drv,
- int num_dai)
-{
- char buf[50];
- int i;
- int i2cbus = i2c->adapter->nr;
- int addr = i2c->addr;
- if (dai_drv && num_dai > 0)
- for (i = 0; i < num_dai; i++) {
- snprintf(buf, 50, "%s-%x-%x", dai_drv[i].name, i2cbus,
- addr);
- dai_drv[i].name = tfa98xx_devm_kstrdup(dev, buf);
-
- snprintf(buf, 50, "%s-%x-%x",
- dai_drv[i].playback.stream_name,
- i2cbus, addr);
- dai_drv[i].playback.stream_name = tfa98xx_devm_kstrdup(dev, buf);
-
- snprintf(buf, 50, "%s-%x-%x",
- dai_drv[i].capture.stream_name,
- i2cbus, addr);
- dai_drv[i].capture.stream_name = tfa98xx_devm_kstrdup(dev, buf);
- }
-
- /* the idea behind this is convert:
- * SND_SOC_DAPM_AIF_IN("AIF IN", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
- * into:
- * SND_SOC_DAPM_AIF_IN("AIF IN", "AIF Playback-2-36", 0, SND_SOC_NOPM, 0, 0),
- */
- if (widgets && num_widgets > 0)
- for (i = 0; i < num_widgets; i++) {
- if (!widgets[i].sname)
- continue;
- if ((widgets[i].id == snd_soc_dapm_aif_in)
- || (widgets[i].id == snd_soc_dapm_aif_out)) {
- snprintf(buf, 50, "%s-%x-%x", widgets[i].sname,
- i2cbus, addr);
- widgets[i].sname = tfa98xx_devm_kstrdup(dev, buf);
- }
- }
-
- return 0;
-}
-
-static struct snd_soc_dapm_widget tfa98xx_dapm_widgets_common[] = {
- /* Stream widgets */
- SND_SOC_DAPM_AIF_IN("AIF IN", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
- SND_SOC_DAPM_AIF_OUT("AIF OUT", "AIF Capture", 0, SND_SOC_NOPM, 0, 0),
-
- SND_SOC_DAPM_OUTPUT("OUTL"),
- SND_SOC_DAPM_INPUT("AEC Loopback"),
-};
-
-static struct snd_soc_dapm_widget tfa98xx_dapm_widgets_stereo[] = {
- SND_SOC_DAPM_OUTPUT("OUTR"),
-};
-
-static struct snd_soc_dapm_widget tfa98xx_dapm_widgets_saam[] = {
- SND_SOC_DAPM_INPUT("SAAM MIC"),
-};
-
-static struct snd_soc_dapm_widget tfa9888_dapm_inputs[] = {
- SND_SOC_DAPM_INPUT("DMIC1"),
- SND_SOC_DAPM_INPUT("DMIC2"),
- SND_SOC_DAPM_INPUT("DMIC3"),
- SND_SOC_DAPM_INPUT("DMIC4"),
-};
-
-static const struct snd_soc_dapm_route tfa98xx_dapm_routes_common[] = {
- { "OUTL", NULL, "AIF IN" },
- { "AIF OUT", NULL, "AEC Loopback" },
-};
-
-static const struct snd_soc_dapm_route tfa98xx_dapm_routes_saam[] = {
- { "AIF OUT", NULL, "SAAM MIC" },
-};
-
-static const struct snd_soc_dapm_route tfa98xx_dapm_routes_stereo[] = {
- { "OUTR", NULL, "AIF IN" },
-};
-
-static const struct snd_soc_dapm_route tfa9888_input_dapm_routes[] = {
- { "AIF OUT", NULL, "DMIC1" },
- { "AIF OUT", NULL, "DMIC2" },
- { "AIF OUT", NULL, "DMIC3" },
- { "AIF OUT", NULL, "DMIC4" },
-};
-
-#if LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0)
-static struct snd_soc_dapm_context *snd_soc_codec_get_dapm(struct snd_soc_codec *codec)
-{
- return &codec->dapm;
-}
-#endif
-
-static void tfa98xx_add_widgets(struct tfa98xx *tfa98xx)
-{
- struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(tfa98xx->codec);
- struct snd_soc_dapm_widget *widgets;
- unsigned int num_dapm_widgets = ARRAY_SIZE(tfa98xx_dapm_widgets_common);
-
- widgets = devm_kzalloc(&tfa98xx->i2c->dev,
- sizeof(struct snd_soc_dapm_widget) *
- ARRAY_SIZE(tfa98xx_dapm_widgets_common),
- GFP_KERNEL);
- if (!widgets)
- return;
- memcpy(widgets, tfa98xx_dapm_widgets_common,
- sizeof(struct snd_soc_dapm_widget) *
- ARRAY_SIZE(tfa98xx_dapm_widgets_common));
-
- tfa98xx_append_i2c_address(&tfa98xx->i2c->dev,
- tfa98xx->i2c,
- widgets,
- num_dapm_widgets,
- NULL,
- 0);
-
- snd_soc_dapm_new_controls(dapm, widgets,
- ARRAY_SIZE(tfa98xx_dapm_widgets_common));
- snd_soc_dapm_add_routes(dapm, tfa98xx_dapm_routes_common,
- ARRAY_SIZE(tfa98xx_dapm_routes_common));
-
- if (tfa98xx->flags & TFA98XX_FLAG_STEREO_DEVICE) {
- snd_soc_dapm_new_controls(dapm, tfa98xx_dapm_widgets_stereo,
- ARRAY_SIZE(tfa98xx_dapm_widgets_stereo));
- snd_soc_dapm_add_routes(dapm, tfa98xx_dapm_routes_stereo,
- ARRAY_SIZE(tfa98xx_dapm_routes_stereo));
- }
-
- if (tfa98xx->flags & TFA98XX_FLAG_MULTI_MIC_INPUTS) {
- snd_soc_dapm_new_controls(dapm, tfa9888_dapm_inputs,
- ARRAY_SIZE(tfa9888_dapm_inputs));
- snd_soc_dapm_add_routes(dapm, tfa9888_input_dapm_routes,
- ARRAY_SIZE(tfa9888_input_dapm_routes));
- }
-
- if (tfa98xx->flags & TFA98XX_FLAG_SAAM_AVAILABLE) {
- snd_soc_dapm_new_controls(dapm, tfa98xx_dapm_widgets_saam,
- ARRAY_SIZE(tfa98xx_dapm_widgets_saam));
- snd_soc_dapm_add_routes(dapm, tfa98xx_dapm_routes_saam,
- ARRAY_SIZE(tfa98xx_dapm_routes_saam));
- }
-}
-
-/* I2C wrapper functions */
-enum Tfa98xx_Error tfa98xx_write_register16(struct tfa_device *tfa,
- unsigned char subaddress,
- unsigned short value)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- struct tfa98xx *tfa98xx;
- int ret;
- int retries = I2C_RETRIES;
-
- if (tfa == NULL) {
- pr_err("No device available\n");
- return Tfa98xx_Error_Fail;
- }
-
- tfa98xx = (struct tfa98xx *)tfa->data;
- if (!tfa98xx || !tfa98xx->regmap) {
- pr_err("No tfa98xx regmap available\n");
- return Tfa98xx_Error_Bad_Parameter;
- }
-retry:
- ret = regmap_write(tfa98xx->regmap, subaddress, value);
- if (ret < 0) {
- pr_warn("i2c error, retries left: %d\n", retries);
- if (retries) {
- retries--;
- msleep(I2C_RETRY_DELAY);
- goto retry;
- }
- return Tfa98xx_Error_Fail;
- }
- if (tfa98xx_kmsg_regs)
- dev_dbg(&tfa98xx->i2c->dev, " WR reg=0x%02x, val=0x%04x %s\n",
- subaddress, value,
- ret < 0 ? "Error!!" : "");
-
- if (tfa98xx_ftrace_regs)
- tfa98xx_trace_printk("\tWR reg=0x%02x, val=0x%04x %s\n",
- subaddress, value,
- ret < 0 ? "Error!!" : "");
- return error;
-}
-
-enum Tfa98xx_Error tfa98xx_read_register16(struct tfa_device *tfa,
- unsigned char subaddress,
- unsigned short *val)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- struct tfa98xx *tfa98xx;
- unsigned int value;
- int retries = I2C_RETRIES;
- int ret;
-
- if (tfa == NULL) {
- pr_err("No device available\n");
- return Tfa98xx_Error_Fail;
- }
-
- tfa98xx = (struct tfa98xx *)tfa->data;
- if (!tfa98xx || !tfa98xx->regmap) {
- pr_err("No tfa98xx regmap available\n");
- return Tfa98xx_Error_Bad_Parameter;
- }
-retry:
- ret = regmap_read(tfa98xx->regmap, subaddress, &value);
- if (ret < 0) {
- pr_warn("i2c error at subaddress 0x%x, retries left: %d\n", subaddress, retries);
- if (retries) {
- retries--;
- msleep(I2C_RETRY_DELAY);
- goto retry;
- }
- return Tfa98xx_Error_Fail;
- }
- *val = value & 0xffff;
-
- if (tfa98xx_kmsg_regs)
- dev_dbg(&tfa98xx->i2c->dev, "RD reg=0x%02x, val=0x%04x %s\n",
- subaddress, *val,
- ret < 0 ? "Error!!" : "");
- if (tfa98xx_ftrace_regs)
- tfa98xx_trace_printk("\tRD reg=0x%02x, val=0x%04x %s\n",
- subaddress, *val,
- ret < 0 ? "Error!!" : "");
-
- return error;
-}
-
-
-/*
- * init external dsp
- */
-enum Tfa98xx_Error
- tfa98xx_init_dsp(struct tfa_device *tfa)
-{
- return Tfa98xx_Error_Not_Supported;
-}
-
-int tfa98xx_get_dsp_status(struct tfa_device *tfa)
-{
- return 0;
-}
-
-/*
- * write external dsp message
- */
-enum Tfa98xx_Error
- tfa98xx_write_dsp(struct tfa_device *tfa, int num_bytes, const char *command_buffer)
-{
- return Tfa98xx_Error_Not_Supported;
-}
-
-/*
- * read external dsp message
- */
-enum Tfa98xx_Error
- tfa98xx_read_dsp(struct tfa_device *tfa, int num_bytes, unsigned char *result_buffer)
-{
- return Tfa98xx_Error_Not_Supported;
-}
-/*
- * write/read external dsp message
- */
-enum Tfa98xx_Error
- tfa98xx_writeread_dsp(struct tfa_device *tfa, int command_length, void *command_buffer,
- int result_length, void *result_buffer)
-{
- return Tfa98xx_Error_Not_Supported;
-}
-
-enum Tfa98xx_Error tfa98xx_read_data(struct tfa_device *tfa,
- unsigned char reg,
- int len, unsigned char value[])
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- struct tfa98xx *tfa98xx;
- struct i2c_client *tfa98xx_client;
- int err;
- int tries = 0;
- unsigned char *reg_buf = NULL;
- struct i2c_msg msgs[] = {
- {
- .flags = 0,
- .len = 1,
- .buf = NULL,
- }, {
- .flags = I2C_M_RD,
- .len = len,
- .buf = value,
- },
- };
- reg_buf = (unsigned char *)kmalloc(sizeof(reg), GFP_DMA); //GRP_KERNEL also works,
- if (!reg_buf) {
- return -ENOMEM;;
- }
-
- *reg_buf = reg;
- msgs[0].buf = reg_buf;
-
- if (tfa == NULL) {
- pr_err("No device available\n");
- return Tfa98xx_Error_Fail;
- }
-
- tfa98xx = (struct tfa98xx *)tfa->data;
- if (tfa98xx->i2c) {
- tfa98xx_client = tfa98xx->i2c;
- msgs[0].addr = tfa98xx_client->addr;
- msgs[1].addr = tfa98xx_client->addr;
-
- do {
- err = i2c_transfer(tfa98xx_client->adapter, msgs,
- ARRAY_SIZE(msgs));
- if (err != ARRAY_SIZE(msgs))
- msleep_interruptible(I2C_RETRY_DELAY);
- } while ((err != ARRAY_SIZE(msgs)) && (++tries < I2C_RETRIES));
-
- if (err != ARRAY_SIZE(msgs)) {
- dev_err(&tfa98xx_client->dev, "read transfer error %d\n",
- err);
- error = Tfa98xx_Error_Fail;
- }
-
- if (tfa98xx_kmsg_regs)
- dev_dbg(&tfa98xx_client->dev, "RD-DAT reg=0x%02x, len=%d\n",
- reg, len);
- if (tfa98xx_ftrace_regs)
- tfa98xx_trace_printk("\t\tRD-DAT reg=0x%02x, len=%d\n",
- reg, len);
- }
- else {
- pr_err("No device available\n");
- error = Tfa98xx_Error_Fail;
- }
- kfree(reg_buf);
- return error;
-}
-
-enum Tfa98xx_Error tfa98xx_write_raw(struct tfa_device *tfa,
- int len,
- const unsigned char data[])
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- struct tfa98xx *tfa98xx;
- int ret;
- int retries = I2C_RETRIES;
-
-
- if (tfa == NULL) {
- pr_err("No device available\n");
- return Tfa98xx_Error_Fail;
- }
-
- tfa98xx = (struct tfa98xx *)tfa->data;
-
-retry:
- ret = i2c_master_send(tfa98xx->i2c, data, len);
- if (ret < 0) {
- pr_warn("i2c error, retries left: %d\n", retries);
- if (retries) {
- retries--;
- msleep(I2C_RETRY_DELAY);
- goto retry;
- }
- }
-
- if (ret == len) {
- if (tfa98xx_kmsg_regs)
- dev_dbg(&tfa98xx->i2c->dev, " WR-RAW len=%d\n", len);
- if (tfa98xx_ftrace_regs)
- tfa98xx_trace_printk("\t\tWR-RAW len=%d\n", len);
- return Tfa98xx_Error_Ok;
- }
- pr_err(" WR-RAW (len=%d) Error I2C send size mismatch %d\n", len, ret);
- error = Tfa98xx_Error_Fail;
-
- return error;
-}
-
-/* Interrupts management */
-
-static void tfa98xx_interrupt_enable_tfa2(struct tfa98xx *tfa98xx, bool enable)
-{
- /* Only for 0x72 we need to enable NOCLK interrupts */
- if (tfa98xx->flags & TFA98XX_FLAG_REMOVE_PLOP_NOISE)
- tfa_irq_ena(tfa98xx->tfa, tfa9912_irq_stnoclk, enable);
-
- if (tfa98xx->flags & TFA98XX_FLAG_LP_MODES) {
- tfa_irq_ena(tfa98xx->tfa, 36, enable); /* FIXME: IELP0 does not excist for 9912 */
- tfa_irq_ena(tfa98xx->tfa, tfa9912_irq_stclpr, enable);
- }
-}
-
-/* Check if tap-detection can and shall be enabled.
- * Configure SPK interrupt accordingly or setup polling mode
- * Tap-detection shall be active if:
- * - the service is enabled (tapdet_open), AND
- * - the current profile is a tap-detection profile
- * On TFA1 familiy of devices, activating tap-detection means enabling the SPK
- * interrupt if available.
- * We also update the tapdet_enabled and tapdet_poll variables.
- */
-static void tfa98xx_tapdet_check_update(struct tfa98xx *tfa98xx)
-{
- unsigned int enable = false;
-
- /* Support tap-detection on TFA1 family of devices */
- if ((tfa98xx->flags & TFA98XX_FLAG_TAPDET_AVAILABLE) == 0)
- return;
-
- if (tfa98xx->tapdet_open &&
- (tfa98xx->tapdet_profiles & (1 << tfa98xx->profile)))
- enable = true;
-
- if (!gpio_is_valid(tfa98xx->irq_gpio)) {
- /* interrupt not available, setup polling mode */
- tfa98xx->tapdet_poll = true;
- if (enable)
- queue_delayed_work(tfa98xx->tfa98xx_wq,
- &tfa98xx->tapdet_work, HZ / 10);
- else
- cancel_delayed_work_sync(&tfa98xx->tapdet_work);
- dev_dbg(tfa98xx->codec->dev,
- "Polling for tap-detection: %s (%d; 0x%x, %d)\n",
- enable ? "enabled" : "disabled",
- tfa98xx->tapdet_open, tfa98xx->tapdet_profiles,
- tfa98xx->profile);
-
- }
- else {
- dev_dbg(tfa98xx->codec->dev,
- "Interrupt for tap-detection: %s (%d; 0x%x, %d)\n",
- enable ? "enabled" : "disabled",
- tfa98xx->tapdet_open, tfa98xx->tapdet_profiles,
- tfa98xx->profile);
- /* enabled interrupt */
- tfa_irq_ena(tfa98xx->tfa, tfa9912_irq_sttapdet, enable);
- }
-
- /* check disabled => enabled transition to clear pending events */
- if (!tfa98xx->tapdet_enabled && enable) {
- /* clear pending event if any */
- tfa_irq_clear(tfa98xx->tfa, tfa9912_irq_sttapdet);
- }
-
- if (!tfa98xx->tapdet_poll)
- tfa_irq_ena(tfa98xx->tfa, tfa9912_irq_sttapdet, 1); /* enable again */
-}
-
-/* global enable / disable interrupts */
-static void tfa98xx_interrupt_enable(struct tfa98xx *tfa98xx, bool enable)
-{
- if (tfa98xx->flags & TFA98XX_FLAG_SKIP_INTERRUPTS)
- return;
-
- if (tfa98xx->tfa->tfa_family == 2)
- tfa98xx_interrupt_enable_tfa2(tfa98xx, enable);
-}
-
-/* Firmware management */
-static void tfa98xx_container_loaded(const struct firmware *cont, void *context)
-{
- nxpTfaContainer_t *container;
- struct tfa98xx *tfa98xx = context;
- enum tfa_error tfa_err;
- int container_size;
- int ret;
-
- tfa98xx->dsp_fw_state = TFA98XX_DSP_FW_FAIL;
-
- if (!cont) {
- pr_err("Failed to read %s\n", fw_name);
- return;
- }
-
- pr_debug("loaded %s - size: %zu\n", fw_name, cont->size);
-
- mutex_lock(&tfa98xx_mutex);
- if (tfa98xx_container == NULL) {
- container = kzalloc(cont->size, GFP_KERNEL);
- if (container == NULL) {
- mutex_unlock(&tfa98xx_mutex);
- release_firmware(cont);
- pr_err("Error allocating memory\n");
- return;
- }
-
- container_size = cont->size;
- memcpy(container, cont->data, container_size);
- release_firmware(cont);
-
- pr_debug("%.2s%.2s\n", container->version, container->subversion);
- pr_debug("%.8s\n", container->customer);
- pr_debug("%.8s\n", container->application);
- pr_debug("%.8s\n", container->type);
- pr_debug("%d ndev\n", container->ndev);
- pr_debug("%d nprof\n", container->nprof);
-
- tfa_err = tfa_load_cnt(container, container_size);
- if (tfa_err != tfa_error_ok) {
- mutex_unlock(&tfa98xx_mutex);
- kfree(container);
- dev_err(tfa98xx->dev, "Cannot load container file, aborting\n");
- return;
- }
-
- tfa98xx_container = container;
- }
- else {
- pr_debug("container file already loaded...\n");
- container = tfa98xx_container;
- release_firmware(cont);
- }
- mutex_unlock(&tfa98xx_mutex);
-
- tfa98xx->tfa->cnt = container;
-
- /*
- i2c transaction limited to 64k
- (Documentation/i2c/writing-clients)
- */
- tfa98xx->tfa->buffer_size = 65536;
-
- /* DSP messages via i2c */
- tfa98xx->tfa->has_msg = 0;
-
- if (tfa_dev_probe(tfa98xx->i2c->addr, tfa98xx->tfa) != 0) {
- dev_err(tfa98xx->dev, "Failed to probe TFA98xx @ 0x%.2x\n", tfa98xx->i2c->addr);
- return;
- }
-
- tfa98xx->tfa->dev_idx = tfa_cont_get_idx(tfa98xx->tfa);
- if (tfa98xx->tfa->dev_idx < 0) {
- dev_err(tfa98xx->dev, "Failed to find TFA98xx @ 0x%.2x in container file\n", tfa98xx->i2c->addr);
- return;
- }
-
- /* Enable debug traces */
- tfa98xx->tfa->verbose = trace_level & 1;
-
- /* prefix is the application name from the cnt */
- tfa_cnt_get_app_name(tfa98xx->tfa, tfa98xx->fw.name);
-
- /* set default profile/vstep */
- tfa98xx->profile = 0;
- tfa98xx->vstep = 0;
-
- /* Override default profile if requested */
- if (strcmp(dflt_prof_name, "")) {
- unsigned int i;
- int nprof = tfa_cnt_get_dev_nprof(tfa98xx->tfa);
- for (i = 0; i < nprof; i++) {
- if (strcmp(tfa_cont_profile_name(tfa98xx, i),
- dflt_prof_name) == 0) {
- tfa98xx->profile = i;
- dev_info(tfa98xx->dev,
- "changing default profile to %s (%d)\n",
- dflt_prof_name, tfa98xx->profile);
- break;
- }
- }
- if (i >= nprof)
- dev_info(tfa98xx->dev,
- "Default profile override failed (%s profile not found)\n",
- dflt_prof_name);
- }
-
- tfa98xx->dsp_fw_state = TFA98XX_DSP_FW_OK;
- pr_debug("Firmware init complete\n");
-
- if (no_start != 0)
- return;
-
- /* Only controls for master device */
- if (tfa98xx->tfa->dev_idx == 0)
- tfa98xx_create_controls(tfa98xx);
-
- tfa98xx_inputdev_check_register(tfa98xx);
-
- if (tfa_is_cold(tfa98xx->tfa) == 0) {
- pr_debug("Warning: device 0x%.2x is still warm\n", tfa98xx->i2c->addr);
- tfa_reset(tfa98xx->tfa);
- }
-
- /* Preload settings using internal clock on TFA2 */
- if (tfa98xx->tfa->tfa_family == 2) {
- mutex_lock(&tfa98xx->dsp_lock);
- ret = tfa98xx_tfa_start(tfa98xx, tfa98xx->profile, tfa98xx->vstep);
- if (ret == Tfa98xx_Error_Not_Supported)
- tfa98xx->dsp_fw_state = TFA98XX_DSP_FW_FAIL;
- mutex_unlock(&tfa98xx->dsp_lock);
- }
-
- tfa98xx_interrupt_enable(tfa98xx, true);
-}
-
-static int tfa98xx_load_container(struct tfa98xx *tfa98xx)
-{
- tfa98xx->dsp_fw_state = TFA98XX_DSP_FW_PENDING;
-
- return request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
- fw_name, tfa98xx->dev, GFP_KERNEL,
- tfa98xx, tfa98xx_container_loaded);
-}
-
-
-static void tfa98xx_tapdet(struct tfa98xx *tfa98xx)
-{
- unsigned int tap_pattern;
- int btn;
-
- /* check tap pattern (BTN_0 is "error" wrong tap indication */
- tap_pattern = tfa_get_tap_pattern(tfa98xx->tfa);
- switch (tap_pattern) {
- case 0xffffffff:
- pr_info("More than 4 taps detected! (flagTapPattern = -1)\n");
- btn = BTN_0;
- break;
- case 0xfffffffe:
- case 0xfe:
- pr_info("Illegal tap detected!\n");
- btn = BTN_0;
- break;
- case 0:
- pr_info("Unrecognized pattern! (flagTapPattern = 0)\n");
- btn = BTN_0;
- break;
- default:
- pr_info("Detected pattern: %d\n", tap_pattern);
- btn = BTN_0 + tap_pattern;
- break;
- }
-
- input_report_key(tfa98xx->input, btn, 1);
- input_report_key(tfa98xx->input, btn, 0);
- input_sync(tfa98xx->input);
-
- /* acknowledge event done by clearing interrupt */
-
-}
-
-static void tfa98xx_tapdet_work(struct work_struct *work)
-{
- struct tfa98xx *tfa98xx;
-
- //TODO check is this is still needed for tap polling
- tfa98xx = container_of(work, struct tfa98xx, tapdet_work.work);
-
- if (tfa_irq_get(tfa98xx->tfa, tfa9912_irq_sttapdet))
- tfa98xx_tapdet(tfa98xx);
-
- queue_delayed_work(tfa98xx->tfa98xx_wq, &tfa98xx->tapdet_work, HZ / 10);
-}
-
-static void tfa98xx_monitor(struct work_struct *work)
-{
- struct tfa98xx *tfa98xx;
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
-
- tfa98xx = container_of(work, struct tfa98xx, monitor_work.work);
-
- /* Check for tap-detection - bypass monitor if it is active */
- if (!tfa98xx->input) {
- mutex_lock(&tfa98xx->dsp_lock);
- error = tfa_status(tfa98xx->tfa);
- mutex_unlock(&tfa98xx->dsp_lock);
- if (error == Tfa98xx_Error_DSP_not_running) {
- if (tfa98xx->dsp_init == TFA98XX_DSP_INIT_DONE) {
- tfa98xx->dsp_init = TFA98XX_DSP_INIT_RECOVER;
- queue_delayed_work(tfa98xx->tfa98xx_wq, &tfa98xx->init_work, 0);
- }
- }
- }
-
- /* reschedule */
- queue_delayed_work(tfa98xx->tfa98xx_wq, &tfa98xx->monitor_work, 5 * HZ);
-}
-
-static void tfa98xx_dsp_init(struct tfa98xx *tfa98xx)
-{
- int ret;
- bool failed = false;
- bool reschedule = false;
- bool sync = false;
-
- if (tfa98xx->dsp_fw_state != TFA98XX_DSP_FW_OK) {
- pr_debug("Skipping tfa_dev_start (no FW: %d)\n", tfa98xx->dsp_fw_state);
- return;
- }
-
- if (tfa98xx->dsp_init == TFA98XX_DSP_INIT_DONE) {
- pr_debug("Stream already started, skipping DSP power-on\n");
- return;
- }
-
- mutex_lock(&tfa98xx->dsp_lock);
-
- tfa98xx->dsp_init = TFA98XX_DSP_INIT_PENDING;
-
- if (tfa98xx->init_count < TF98XX_MAX_DSP_START_TRY_COUNT) {
- /* directly try to start DSP */
- ret = tfa98xx_tfa_start(tfa98xx, tfa98xx->profile, tfa98xx->vstep);
- if (ret == Tfa98xx_Error_Not_Supported) {
- tfa98xx->dsp_fw_state = TFA98XX_DSP_FW_FAIL;
- dev_err(&tfa98xx->i2c->dev, "Failed starting device\n");
- failed = true;
- }
- else if (ret != Tfa98xx_Error_Ok) {
- /* It may fail as we may not have a valid clock at that
- * time, so re-schedule and re-try later.
- */
- dev_err(&tfa98xx->i2c->dev,
- "tfa_dev_start failed! (err %d) - %d\n",
- ret, tfa98xx->init_count);
- reschedule = true;
- }
- else {
- sync = true;
-
- /* Subsystem ready, tfa init complete */
- tfa98xx->dsp_init = TFA98XX_DSP_INIT_DONE;
- dev_dbg(&tfa98xx->i2c->dev,
- "tfa_dev_start success (%d)\n",
- tfa98xx->init_count);
- /* cancel other pending init works */
- cancel_delayed_work(&tfa98xx->init_work);
- tfa98xx->init_count = 0;
- }
- }
- else {
- /* exceeded max number ot start tentatives, cancel start */
- dev_err(&tfa98xx->i2c->dev,
- "Failed starting device (%d)\n",
- tfa98xx->init_count);
- failed = true;
- }
- if (reschedule) {
- /* reschedule this init work for later */
- queue_delayed_work(tfa98xx->tfa98xx_wq,
- &tfa98xx->init_work,
- msecs_to_jiffies(5));
- tfa98xx->init_count++;
- }
- if (failed) {
- tfa98xx->dsp_init = TFA98XX_DSP_INIT_FAIL;
- /* cancel other pending init works */
- cancel_delayed_work(&tfa98xx->init_work);
- tfa98xx->init_count = 0;
- }
- mutex_unlock(&tfa98xx->dsp_lock);
-
- if (sync) {
- /* check if all devices have started */
- bool do_sync;
- mutex_lock(&tfa98xx_mutex);
-
- if (tfa98xx_sync_count < tfa98xx_device_count)
- tfa98xx_sync_count++;
-
- do_sync = (tfa98xx_sync_count >= tfa98xx_device_count);
- mutex_unlock(&tfa98xx_mutex);
-
- /* when all devices have started then unmute */
- if (do_sync) {
- tfa98xx_sync_count = 0;
- list_for_each_entry(tfa98xx, &tfa98xx_device_list, list) {
- mutex_lock(&tfa98xx->dsp_lock);
- tfa_dev_set_state(tfa98xx->tfa, TFA_STATE_UNMUTE, 0);
-
- /*
- * start monitor thread to check IC status bit
- * periodically, and re-init IC to recover if
- * needed.
- */
- if (tfa98xx->tfa->tfa_family == 1)
- queue_delayed_work(tfa98xx->tfa98xx_wq,
- &tfa98xx->monitor_work,
- 1 * HZ);
- mutex_unlock(&tfa98xx->dsp_lock);
- }
-
- }
- }
-
-
- return;
-}
-
-
-static void tfa98xx_dsp_init_work(struct work_struct *work)
-{
- struct tfa98xx *tfa98xx = container_of(work, struct tfa98xx, init_work.work);
-
- tfa98xx_dsp_init(tfa98xx);
-}
-
-static void tfa98xx_interrupt(struct work_struct *work)
-{
- struct tfa98xx *tfa98xx = container_of(work, struct tfa98xx, interrupt_work.work);
-
- pr_info("\n");
-
- if (tfa98xx->flags & TFA98XX_FLAG_TAPDET_AVAILABLE) {
- /* check for tap interrupt */
- if (tfa_irq_get(tfa98xx->tfa, tfa9912_irq_sttapdet)) {
- tfa98xx_tapdet(tfa98xx);
-
- /* clear interrupt */
- tfa_irq_clear(tfa98xx->tfa, tfa9912_irq_sttapdet);
- }
- } /* TFA98XX_FLAG_TAPDET_AVAILABLE */
-
- if (tfa98xx->flags & TFA98XX_FLAG_REMOVE_PLOP_NOISE) {
- int start_triggered;
-
- mutex_lock(&tfa98xx->dsp_lock);
- start_triggered = tfa_plop_noise_interrupt(tfa98xx->tfa, tfa98xx->profile, tfa98xx->vstep);
- /* Only enable when the return value is 1, otherwise the interrupt is triggered twice */
- if (start_triggered)
- tfa98xx_interrupt_enable(tfa98xx, true);
- mutex_unlock(&tfa98xx->dsp_lock);
- } /* TFA98XX_FLAG_REMOVE_PLOP_NOISE */
-
- if (tfa98xx->flags & TFA98XX_FLAG_LP_MODES) {
- tfa_lp_mode_interrupt(tfa98xx->tfa);
- } /* TFA98XX_FLAG_LP_MODES */
-
- /* unmask interrupts masked in IRQ handler */
- tfa_irq_unmask(tfa98xx->tfa);
-}
-
-static int tfa98xx_startup(struct snd_pcm_substream *substream,
- struct snd_soc_dai *dai)
-{
- struct snd_soc_codec *codec = dai->codec;
- struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec);
- unsigned int sr;
- int len, prof, nprof, idx = 0;
- char *basename;
- u64 formats;
- int err;
-
- /*
- * Support CODEC to CODEC links,
- * these are called with a NULL runtime pointer.
- */
- if (!substream->runtime)
- return 0;
-
- if (pcm_no_constraint != 0)
- return 0;
-
- switch (pcm_sample_format) {
- case 1:
- formats = SNDRV_PCM_FMTBIT_S24_LE;
- break;
- case 2:
- formats = SNDRV_PCM_FMTBIT_S32_LE;
- break;
- default:
- formats = SNDRV_PCM_FMTBIT_S16_LE;
- break;
- }
-
- err = snd_pcm_hw_constraint_mask64(substream->runtime,
- SNDRV_PCM_HW_PARAM_FORMAT, formats);
- if (err < 0)
- return err;
-
- if (no_start != 0)
- return 0;
-
- if (tfa98xx->dsp_fw_state != TFA98XX_DSP_FW_OK) {
- dev_info(codec->dev, "Container file not loaded\n");
- return -EINVAL;
- }
-
- basename = kzalloc(MAX_CONTROL_NAME, GFP_KERNEL);
- if (!basename)
- return -ENOMEM;
-
- /* copy profile name into basename until the . */
- get_profile_basename(basename, tfa_cont_profile_name(tfa98xx, tfa98xx->profile));
- len = strlen(basename);
-
- /* loop over all profiles and get the supported samples rate(s) from
- * the profiles with the same basename
- */
- nprof = tfa_cnt_get_dev_nprof(tfa98xx->tfa);
- tfa98xx->rate_constraint.list = &tfa98xx->rate_constraint_list[0];
- tfa98xx->rate_constraint.count = 0;
- for (prof = 0; prof < nprof; prof++) {
- if (0 == strncmp(basename, tfa_cont_profile_name(tfa98xx, prof), len)) {
- /* Check which sample rate is supported with current profile,
- * and enforce this.
- */
- sr = tfa98xx_get_profile_sr(tfa98xx->tfa, prof);
- if (!sr)
- dev_info(codec->dev, "Unable to identify supported sample rate\n");
-
- if (tfa98xx->rate_constraint.count >= TFA98XX_NUM_RATES) {
- dev_err(codec->dev, "too many sample rates\n");
- }
- else {
- tfa98xx->rate_constraint_list[idx++] = sr;
- tfa98xx->rate_constraint.count += 1;
- }
- }
- }
-
- kfree(basename);
-
- return snd_pcm_hw_constraint_list(substream->runtime, 0,
- SNDRV_PCM_HW_PARAM_RATE,
- &tfa98xx->rate_constraint);
-}
-
-static int tfa98xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
- int clk_id, unsigned int freq, int dir)
-{
- struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec_dai->codec);
-
- tfa98xx->sysclk = freq;
- return 0;
-}
-
-static int tfa98xx_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
- unsigned int rx_mask, int slots, int slot_width)
-{
- pr_debug("\n");
- return 0;
-}
-
-static int tfa98xx_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
-{
- struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(dai->codec);
- struct snd_soc_codec *codec = dai->codec;
-
- pr_debug("fmt=0x%x\n", fmt);
-
- /* Supported mode: regular I2S, slave, or PDM */
- switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
- case SND_SOC_DAIFMT_I2S:
- if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) {
- dev_err(codec->dev, "Invalid Codec master mode\n");
- return -EINVAL;
- }
- break;
- case SND_SOC_DAIFMT_PDM:
- break;
- default:
- dev_err(codec->dev, "Unsupported DAI format %d\n",
- fmt & SND_SOC_DAIFMT_FORMAT_MASK);
- return -EINVAL;
- }
-
- tfa98xx->audio_mode = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
-
- return 0;
-}
-
-static int tfa98xx_get_fssel(unsigned int rate)
-{
- int i;
- for (i = 0; i < ARRAY_SIZE(rate_to_fssel); i++) {
- if (rate_to_fssel[i].rate == rate) {
- return rate_to_fssel[i].fssel;
- }
- }
- return -EINVAL;
-}
-
-static int tfa98xx_hw_params(struct snd_pcm_substream *substream,
- struct snd_pcm_hw_params *params,
- struct snd_soc_dai *dai)
-{
- struct snd_soc_codec *codec = dai->codec;
- struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec);
- unsigned int rate;
- int prof_idx;
-
- /* Supported */
- rate = params_rate(params);
- pr_debug("Requested rate: %d, sample size: %d, physical size: %d\n",
- rate, snd_pcm_format_width(params_format(params)),
- snd_pcm_format_physical_width(params_format(params)));
-
- if (no_start != 0)
- return 0;
-
- /* check if samplerate is supported for this mixer profile */
- prof_idx = get_profile_id_for_sr(tfa98xx_mixer_profile, rate);
- if (prof_idx < 0) {
- pr_err("tfa98xx: invalid sample rate %d.\n", rate);
- return -EINVAL;
- }
- pr_debug("mixer profile:container profile = [%d:%d]\n", tfa98xx_mixer_profile, prof_idx);
-
-
- /* update 'real' profile (container profile) */
- tfa98xx->profile = prof_idx;
-
- /* update to new rate */
- tfa98xx->rate = rate;
-
- return 0;
-}
-
-static int tfa98xx_mute(struct snd_soc_dai *dai, int mute, int stream)
-{
- struct snd_soc_codec *codec = dai->codec;
- struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec);
-
- dev_dbg(&tfa98xx->i2c->dev, "%s: state: %d\n", __func__, mute);
-
- if (no_start) {
- pr_debug("no_start parameter set no tfa_dev_start or tfa_dev_stop, returning\n");
- return 0;
- }
-
- if (mute) {
- /* stop DSP only when both playback and capture streams
- * are deactivated
- */
- if (stream == SNDRV_PCM_STREAM_PLAYBACK)
- tfa98xx->pstream = 0;
- else
- tfa98xx->cstream = 0;
- if (tfa98xx->pstream != 0 || tfa98xx->cstream != 0)
- return 0;
-
- mutex_lock(&tfa98xx_mutex);
- tfa98xx_sync_count = 0;
- mutex_unlock(&tfa98xx_mutex);
-
- cancel_delayed_work_sync(&tfa98xx->monitor_work);
-
- cancel_delayed_work_sync(&tfa98xx->init_work);
- if (tfa98xx->dsp_fw_state != TFA98XX_DSP_FW_OK)
- return 0;
- mutex_lock(&tfa98xx->dsp_lock);
- tfa_dev_stop(tfa98xx->tfa);
- tfa98xx->dsp_init = TFA98XX_DSP_INIT_STOPPED;
- mutex_unlock(&tfa98xx->dsp_lock);
- }
- else {
- if (stream == SNDRV_PCM_STREAM_PLAYBACK)
- tfa98xx->pstream = 1;
- else
- tfa98xx->cstream = 1;
-
- /* Start DSP */
-#if 1
- if (tfa98xx->dsp_init != TFA98XX_DSP_INIT_PENDING)
- queue_delayed_work(tfa98xx->tfa98xx_wq,
- &tfa98xx->init_work, 0);
-#else
- tfa98xx_dsp_init(tfa98xx);
-#endif//
- }
-
- return 0;
-}
-
-static const struct snd_soc_dai_ops tfa98xx_dai_ops = {
- .startup = tfa98xx_startup,
- .set_fmt = tfa98xx_set_fmt,
- .set_sysclk = tfa98xx_set_dai_sysclk,
- .set_tdm_slot = tfa98xx_set_tdm_slot,
- .hw_params = tfa98xx_hw_params,
- .mute_stream = tfa98xx_mute,
-};
-
-static struct snd_soc_dai_driver tfa98xx_dai[] = {
- {
- .name = "tfa98xx-aif",
- .id = 1,
- .playback = {
- .stream_name = "AIF Playback",
- .channels_min = 1,
- .channels_max = 4,
- .rates = TFA98XX_RATES,
- .formats = TFA98XX_FORMATS,
- },
- .capture = {
- .stream_name = "AIF Capture",
- .channels_min = 1,
- .channels_max = 4,
- .rates = TFA98XX_RATES,
- .formats = TFA98XX_FORMATS,
- },
- .ops = &tfa98xx_dai_ops,
- .symmetric_rates = 1,
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
- .symmetric_channels = 1,
- .symmetric_samplebits = 1,
-#endif
- },
-};
-
-static int tfa98xx_probe(struct snd_soc_codec *codec)
-{
- struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec);
- int ret;
-
- pr_debug("\n");
-
- /* setup work queue, will be used to initial DSP on first boot up */
- tfa98xx->tfa98xx_wq = create_singlethread_workqueue("tfa98xx");
- if (!tfa98xx->tfa98xx_wq)
- return -ENOMEM;
-
- INIT_DELAYED_WORK(&tfa98xx->init_work, tfa98xx_dsp_init_work);
- INIT_DELAYED_WORK(&tfa98xx->monitor_work, tfa98xx_monitor);
- INIT_DELAYED_WORK(&tfa98xx->interrupt_work, tfa98xx_interrupt);
- INIT_DELAYED_WORK(&tfa98xx->tapdet_work, tfa98xx_tapdet_work);
-
- tfa98xx->codec = codec;
-
- ret = tfa98xx_load_container(tfa98xx);
- pr_debug("Container loading requested: %d\n", ret);
-
-#if LINUX_VERSION_CODE < KERNEL_VERSION(3,16,0)
- codec->control_data = tfa98xx->regmap;
- ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
- if (ret != 0) {
- dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
- return ret;
- }
-#endif
- tfa98xx_add_widgets(tfa98xx);
-
- dev_info(codec->dev, "tfa98xx codec registered (%s)",
- tfa98xx->fw.name);
-
- return ret;
-}
-
-static int tfa98xx_remove(struct snd_soc_codec *codec)
-{
- struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec);
- pr_debug("\n");
-
- tfa98xx_interrupt_enable(tfa98xx, false);
-
- tfa98xx_inputdev_unregister(tfa98xx);
-
- cancel_delayed_work_sync(&tfa98xx->interrupt_work);
- cancel_delayed_work_sync(&tfa98xx->monitor_work);
- cancel_delayed_work_sync(&tfa98xx->init_work);
- cancel_delayed_work_sync(&tfa98xx->tapdet_work);
-
- if (tfa98xx->tfa98xx_wq)
- destroy_workqueue(tfa98xx->tfa98xx_wq);
-
- return 0;
-}
-
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0)
-static struct regmap *tfa98xx_get_regmap(struct device *dev)
-{
- struct tfa98xx *tfa98xx = dev_get_drvdata(dev);
-
- return tfa98xx->regmap;
-}
-#endif
-static struct snd_soc_codec_driver soc_codec_dev_tfa98xx = {
- .probe = tfa98xx_probe,
- .remove = tfa98xx_remove,
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0)
- .get_regmap = tfa98xx_get_regmap,
-#endif
-};
-
-
-static bool tfa98xx_writeable_register(struct device *dev, unsigned int reg)
-{
- /* enable read access for all registers */
- return 1;
-}
-
-static bool tfa98xx_readable_register(struct device *dev, unsigned int reg)
-{
- /* enable read access for all registers */
- return 1;
-}
-
-static bool tfa98xx_volatile_register(struct device *dev, unsigned int reg)
-{
- /* enable read access for all registers */
- return 1;
-}
-
-static const struct regmap_config tfa98xx_regmap = {
- .reg_bits = 8,
- .val_bits = 16,
-
- .max_register = TFA98XX_MAX_REGISTER,
- .writeable_reg = tfa98xx_writeable_register,
- .readable_reg = tfa98xx_readable_register,
- .volatile_reg = tfa98xx_volatile_register,
- .cache_type = REGCACHE_NONE,
-};
-
-static void tfa98xx_irq_tfa2(struct tfa98xx *tfa98xx)
-{
- pr_info("\n");
-
- /*
- * mask interrupts
- * will be unmasked after handling interrupts in workqueue
- */
- tfa_irq_mask(tfa98xx->tfa);
- queue_delayed_work(tfa98xx->tfa98xx_wq, &tfa98xx->interrupt_work, 0);
-}
-
-
-static irqreturn_t tfa98xx_irq(int irq, void *data)
-{
- struct tfa98xx *tfa98xx = data;
-
- if (tfa98xx->tfa->tfa_family == 2)
- tfa98xx_irq_tfa2(tfa98xx);
-
- return IRQ_HANDLED;
-}
-
-static int tfa98xx_ext_reset(struct tfa98xx *tfa98xx)
-{
- if (tfa98xx && gpio_is_valid(tfa98xx->reset_gpio)) {
- int reset = tfa98xx->reset_polarity;
- gpio_set_value_cansleep(tfa98xx->reset_gpio, reset);
- mdelay(1);
- gpio_set_value_cansleep(tfa98xx->reset_gpio, !reset);
- mdelay(1);
- }
- return 0;
-}
-
-static int tfa98xx_parse_dt(struct device *dev, struct tfa98xx *tfa98xx,
- struct device_node *np) {
- u32 value;
- int ret;
- tfa98xx->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
- if (tfa98xx->reset_gpio < 0)
- dev_dbg(dev, "No reset GPIO provided, will not HW reset device\n");
-
- tfa98xx->irq_gpio = of_get_named_gpio(np, "irq-gpio", 0);
- if (tfa98xx->irq_gpio < 0)
- dev_dbg(dev, "No IRQ GPIO provided.\n");
- ret = of_property_read_u32(np,"reset-polarity",&value);
- if(ret< 0)
- {
- tfa98xx->reset_polarity = HIGH;
- }else {
- tfa98xx->reset_polarity = (value == 0) ? LOW : HIGH;
- }
- dev_dbg(dev, "reset-polarity:%d\n",tfa98xx->reset_polarity);
- return 0;
-}
-
-static ssize_t tfa98xx_reg_write(struct file *filp, struct kobject *kobj,
- struct bin_attribute *bin_attr,
- char *buf, loff_t off, size_t count)
-{
- struct device *dev = container_of(kobj, struct device, kobj);
- struct tfa98xx *tfa98xx = dev_get_drvdata(dev);
-
- if (count != 1) {
- pr_debug("invalid register address");
- return -EINVAL;
- }
-
- tfa98xx->reg = buf[0];
-
- return 1;
-}
-
-static ssize_t tfa98xx_rw_write(struct file *filp, struct kobject *kobj,
- struct bin_attribute *bin_attr,
- char *buf, loff_t off, size_t count)
-{
- struct device *dev = container_of(kobj, struct device, kobj);
- struct tfa98xx *tfa98xx = dev_get_drvdata(dev);
- u8 *data;
- int ret;
- int retries = I2C_RETRIES;
-
- data = kmalloc(count + 1, GFP_KERNEL);
- if (data == NULL) {
- pr_debug("can not allocate memory\n");
- return -ENOMEM;
- }
-
- data[0] = tfa98xx->reg;
- memcpy(&data[1], buf, count);
-
-retry:
- ret = i2c_master_send(tfa98xx->i2c, data, count + 1);
- if (ret < 0) {
- pr_warn("i2c error, retries left: %d\n", retries);
- if (retries) {
- retries--;
- msleep(I2C_RETRY_DELAY);
- goto retry;
- }
- }
-
- kfree(data);
-
- /* the number of data bytes written without the register address */
- return ((ret > 1) ? count : -EIO);
-}
-
-static ssize_t tfa98xx_rw_read(struct file *filp, struct kobject *kobj,
- struct bin_attribute *bin_attr,
- char *buf, loff_t off, size_t count)
-{
- struct device *dev = container_of(kobj, struct device, kobj);
- struct tfa98xx *tfa98xx = dev_get_drvdata(dev);
- struct i2c_msg msgs[] = {
- {
- .addr = tfa98xx->i2c->addr,
- .flags = 0,
- .len = 1,
- .buf = &tfa98xx->reg,
- },
- {
- .addr = tfa98xx->i2c->addr,
- .flags = I2C_M_RD,
- .len = count,
- .buf = buf,
- },
- };
- int ret;
- int retries = I2C_RETRIES;
-retry:
- ret = i2c_transfer(tfa98xx->i2c->adapter, msgs, ARRAY_SIZE(msgs));
- if (ret < 0) {
- pr_warn("i2c error, retries left: %d\n", retries);
- if (retries) {
- retries--;
- msleep(I2C_RETRY_DELAY);
- goto retry;
- }
- return ret;
- }
- /* ret contains the number of i2c transaction */
- /* return the number of bytes read */
- return ((ret > 1) ? count : -EIO);
-}
-
-static struct bin_attribute dev_attr_rw = {
- .attr = {
- .name = "rw",
- .mode = S_IRUSR | S_IWUSR,
- },
- .size = 0,
- .read = tfa98xx_rw_read,
- .write = tfa98xx_rw_write,
-};
-
-static struct bin_attribute dev_attr_reg = {
- .attr = {
- .name = "reg",
- .mode = S_IWUSR,
- },
- .size = 0,
- .read = NULL,
- .write = tfa98xx_reg_write,
-};
-
-static int tfa98xx_i2c_probe(struct i2c_client *i2c,
- const struct i2c_device_id *id)
-{
- struct snd_soc_dai_driver *dai;
- struct tfa98xx *tfa98xx;
- struct device_node *np = i2c->dev.of_node;
- int irq_flags;
- unsigned int reg;
- int ret;
-
- pr_info("addr=0x%x\n", i2c->addr);
-
- if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_I2C)) {
- dev_err(&i2c->dev, "check_functionality failed\n");
- return -EIO;
- }
-
- tfa98xx = devm_kzalloc(&i2c->dev, sizeof(struct tfa98xx), GFP_KERNEL);
- if (tfa98xx == NULL)
- return -ENOMEM;
-
- tfa98xx->dev = &i2c->dev;
- tfa98xx->i2c = i2c;
- tfa98xx->dsp_init = TFA98XX_DSP_INIT_STOPPED;
- tfa98xx->rate = 48000; /* init to the default sample rate (48kHz) */
- tfa98xx->tfa = NULL;
-
- tfa98xx->regmap = devm_regmap_init_i2c(i2c, &tfa98xx_regmap);
- if (IS_ERR(tfa98xx->regmap)) {
- ret = PTR_ERR(tfa98xx->regmap);
- dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
- ret);
- return ret;
- }
-
- i2c_set_clientdata(i2c, tfa98xx);
- mutex_init(&tfa98xx->dsp_lock);
- init_waitqueue_head(&tfa98xx->wq);
-
- if (np) {
- ret = tfa98xx_parse_dt(&i2c->dev, tfa98xx, np);
- if (ret) {
- dev_err(&i2c->dev, "Failed to parse DT node\n");
- return ret;
- }
- if (no_start)
- tfa98xx->irq_gpio = -1;
- if (no_reset)
- tfa98xx->reset_gpio = -1;
- }
- else {
- tfa98xx->reset_gpio = -1;
- tfa98xx->irq_gpio = -1;
- }
-
- if (gpio_is_valid(tfa98xx->reset_gpio)) {
- ret = devm_gpio_request_one(&i2c->dev, tfa98xx->reset_gpio,
- GPIOF_OUT_INIT_LOW, "TFA98XX_RST");
- if (ret)
- return ret;
- }
-
- if (gpio_is_valid(tfa98xx->irq_gpio)) {
- ret = devm_gpio_request_one(&i2c->dev, tfa98xx->irq_gpio,
- GPIOF_DIR_IN, "TFA98XX_INT");
- if (ret)
- return ret;
- }
-
- /* Power up! */
- tfa98xx_ext_reset(tfa98xx);
-
- if ((no_start == 0) && (no_reset == 0)) {
- ret = regmap_read(tfa98xx->regmap, 0x03, ®);
- if (ret < 0) {
- dev_err(&i2c->dev, "Failed to read Revision register: %d\n",
- ret);
- return -EIO;
- }
- switch (reg & 0xff) {
- case 0x72: /* tfa9872 */
- pr_info("TFA9872 detected\n");
- tfa98xx->flags |= TFA98XX_FLAG_MULTI_MIC_INPUTS;
- tfa98xx->flags |= TFA98XX_FLAG_CALIBRATION_CTL;
- tfa98xx->flags |= TFA98XX_FLAG_REMOVE_PLOP_NOISE;
- /* tfa98xx->flags |= TFA98XX_FLAG_LP_MODES; */
- tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE;
- break;
- case 0x74: /* tfa9874 */
- pr_info("TFA9874 detected\n");
- tfa98xx->flags |= TFA98XX_FLAG_MULTI_MIC_INPUTS;
- tfa98xx->flags |= TFA98XX_FLAG_CALIBRATION_CTL;
- tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE;
- break;
- case 0x78: /* tfa9878 */
- pr_info("TFA9878 detected\n");
- tfa98xx->flags |= TFA98XX_FLAG_MULTI_MIC_INPUTS;
- tfa98xx->flags |= TFA98XX_FLAG_CALIBRATION_CTL;
- tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE;
- break;
- case 0x88: /* tfa9888 */
- pr_info("TFA9888 detected\n");
- tfa98xx->flags |= TFA98XX_FLAG_STEREO_DEVICE;
- tfa98xx->flags |= TFA98XX_FLAG_MULTI_MIC_INPUTS;
- tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE;
- break;
- case 0x13: /* tfa9912 */
- pr_info("TFA9912 detected\n");
- tfa98xx->flags |= TFA98XX_FLAG_MULTI_MIC_INPUTS;
- tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE;
- /* tfa98xx->flags |= TFA98XX_FLAG_TAPDET_AVAILABLE; */
- break;
- case 0x94: /* tfa9894 */
- pr_info("TFA9894 detected\n");
- tfa98xx->flags |= TFA98XX_FLAG_MULTI_MIC_INPUTS;
- tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE;
- break;
- case 0x80: /* tfa9890 */
- case 0x81: /* tfa9890 */
- pr_info("TFA9890 detected\n");
- tfa98xx->flags |= TFA98XX_FLAG_SKIP_INTERRUPTS;
- break;
- case 0x92: /* tfa9891 */
- pr_info("TFA9891 detected\n");
- tfa98xx->flags |= TFA98XX_FLAG_SAAM_AVAILABLE;
- tfa98xx->flags |= TFA98XX_FLAG_SKIP_INTERRUPTS;
- break;
- case 0x12: /* tfa9895 */
- pr_info("TFA9895 detected\n");
- tfa98xx->flags |= TFA98XX_FLAG_SKIP_INTERRUPTS;
- break;
- case 0x97:
- pr_info("TFA9897 detected\n");
- tfa98xx->flags |= TFA98XX_FLAG_SKIP_INTERRUPTS;
- tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE;
- break;
- case 0x96:
- pr_info("TFA9896 detected\n");
- tfa98xx->flags |= TFA98XX_FLAG_SKIP_INTERRUPTS;
- tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE;
- break;
- default:
- pr_info("Unsupported device revision (0x%x)\n", reg & 0xff);
- return -EINVAL;
- }
- }
-
- tfa98xx->tfa = devm_kzalloc(&i2c->dev, sizeof(struct tfa_device), GFP_KERNEL);
- if (tfa98xx->tfa == NULL)
- return -ENOMEM;
-
- tfa98xx->tfa->data = (void *)tfa98xx;
- tfa98xx->tfa->cachep = tfa98xx_cache;
-
- /* Modify the stream names, by appending the i2c device address.
- * This is used with multicodec, in order to discriminate the devices.
- * Stream names appear in the dai definition and in the stream .
- * We create copies of original structures because each device will
- * have its own instance of this structure, with its own address.
- */
- dai = devm_kzalloc(&i2c->dev, sizeof(tfa98xx_dai), GFP_KERNEL);
- if (!dai)
- return -ENOMEM;
- memcpy(dai, tfa98xx_dai, sizeof(tfa98xx_dai));
-
- tfa98xx_append_i2c_address(&i2c->dev,
- i2c,
- NULL,
- 0,
- dai,
- ARRAY_SIZE(tfa98xx_dai));
-
- ret = snd_soc_register_codec(&i2c->dev,
- &soc_codec_dev_tfa98xx, dai,
- ARRAY_SIZE(tfa98xx_dai));
-
- if (ret < 0) {
- dev_err(&i2c->dev, "Failed to register TFA98xx: %d\n", ret);
- return ret;
- }
-
- if (gpio_is_valid(tfa98xx->irq_gpio) &&
- !(tfa98xx->flags & TFA98XX_FLAG_SKIP_INTERRUPTS)) {
- /* register irq handler */
- irq_flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
- ret = devm_request_threaded_irq(&i2c->dev,
- gpio_to_irq(tfa98xx->irq_gpio),
- NULL, tfa98xx_irq, irq_flags,
- "tfa98xx", tfa98xx);
- if (ret != 0) {
- dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
- gpio_to_irq(tfa98xx->irq_gpio), ret);
- return ret;
- }
- }
- else {
- dev_info(&i2c->dev, "Skipping IRQ registration\n");
- /* disable feature support if gpio was invalid */
- tfa98xx->flags |= TFA98XX_FLAG_SKIP_INTERRUPTS;
- }
-
-#ifdef CONFIG_DEBUG_FS
- if (no_start == 0)
- tfa98xx_debug_init(tfa98xx, i2c);
-#endif
- /* Register the sysfs files for climax backdoor access */
- ret = device_create_bin_file(&i2c->dev, &dev_attr_rw);
- if (ret)
- dev_info(&i2c->dev, "error creating sysfs files\n");
- ret = device_create_bin_file(&i2c->dev, &dev_attr_reg);
- if (ret)
- dev_info(&i2c->dev, "error creating sysfs files\n");
-
- pr_info("%s Probe completed successfully!\n", __func__);
-
- INIT_LIST_HEAD(&tfa98xx->list);
-
- mutex_lock(&tfa98xx_mutex);
- tfa98xx_device_count++;
- list_add(&tfa98xx->list, &tfa98xx_device_list);
- mutex_unlock(&tfa98xx_mutex);
-
- return 0;
-}
-
-static int tfa98xx_i2c_remove(struct i2c_client *i2c)
-{
- struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
-
- pr_debug("addr=0x%x\n", i2c->addr);
-
- tfa98xx_interrupt_enable(tfa98xx, false);
-
- cancel_delayed_work_sync(&tfa98xx->interrupt_work);
- cancel_delayed_work_sync(&tfa98xx->monitor_work);
- cancel_delayed_work_sync(&tfa98xx->init_work);
- cancel_delayed_work_sync(&tfa98xx->tapdet_work);
-
- device_remove_bin_file(&i2c->dev, &dev_attr_reg);
- device_remove_bin_file(&i2c->dev, &dev_attr_rw);
-#ifdef CONFIG_DEBUG_FS
- tfa98xx_debug_remove(tfa98xx);
-#endif
-
- snd_soc_unregister_codec(&i2c->dev);
-
- if (gpio_is_valid(tfa98xx->irq_gpio))
- devm_gpio_free(&i2c->dev, tfa98xx->irq_gpio);
- if (gpio_is_valid(tfa98xx->reset_gpio))
- devm_gpio_free(&i2c->dev, tfa98xx->reset_gpio);
-
- mutex_lock(&tfa98xx_mutex);
- list_del(&tfa98xx->list);
- tfa98xx_device_count--;
- if (tfa98xx_device_count == 0) {
- kfree(tfa98xx_container);
- tfa98xx_container = NULL;
- }
- mutex_unlock(&tfa98xx_mutex);
-
- return 0;
-}
-
-static const struct i2c_device_id tfa98xx_i2c_id[] = {
- { "tfa98xx", 0 },
- { }
-};
-MODULE_DEVICE_TABLE(i2c, tfa98xx_i2c_id);
-
-#ifdef CONFIG_OF
-static struct of_device_id tfa98xx_dt_match[] = {
- {.compatible = "nxp,tfa98xx" },
- {.compatible = "nxp,tfa9872" },
- {.compatible = "nxp,tfa9874" },
- {.compatible = "nxp,tfa9878" },
- {.compatible = "nxp,tfa9888" },
- {.compatible = "nxp,tfa9890" },
- {.compatible = "nxp,tfa9891" },
- {.compatible = "nxp,tfa9894" },
- {.compatible = "nxp,tfa9895" },
- {.compatible = "nxp,tfa9896" },
- {.compatible = "nxp,tfa9897" },
- {.compatible = "nxp,tfa9912" },
- { },
-};
-#endif
-
-static struct i2c_driver tfa98xx_i2c_driver = {
- .driver = {
- .name = "tfa98xx",
- .owner = THIS_MODULE,
- .of_match_table = of_match_ptr(tfa98xx_dt_match),
- },
- .probe = tfa98xx_i2c_probe,
- .remove = tfa98xx_i2c_remove,
- .id_table = tfa98xx_i2c_id,
-};
-
-static int __init tfa98xx_i2c_init(void)
-{
- int ret = 0;
-
- pr_info("TFA98XX driver version %s\n", TFA98XX_VERSION);
-
- /* Enable debug traces */
- tfa98xx_kmsg_regs = trace_level & 2;
- tfa98xx_ftrace_regs = trace_level & 4;
-
- /* Initialize kmem_cache */
- tfa98xx_cache = kmem_cache_create("tfa98xx_cache", /* Cache name /proc/slabinfo */
- PAGE_SIZE, /* Structure size, we should fit in single page */
- 0, /* Structure alignment */
- (SLAB_HWCACHE_ALIGN | SLAB_RECLAIM_ACCOUNT |
- SLAB_MEM_SPREAD), /* Cache property */
- NULL); /* Object constructor */
- if (!tfa98xx_cache) {
- pr_err("tfa98xx can't create memory pool\n");
- ret = -ENOMEM;
- }
-
- ret = i2c_add_driver(&tfa98xx_i2c_driver);
-
- return ret;
-}
-module_init(tfa98xx_i2c_init);
-
-static void __exit tfa98xx_i2c_exit(void)
-{
- i2c_del_driver(&tfa98xx_i2c_driver);
- kmem_cache_destroy(tfa98xx_cache);
-}
-module_exit(tfa98xx_i2c_exit);
-
-MODULE_DESCRIPTION("ASoC TFA98XX driver");
-MODULE_LICENSE("GPL");
-
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#define pr_fmt(fmt) "%s(): " fmt, __func__
+
+#include <linux/module.h>
+#include <linux/i2c.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/of_gpio.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/firmware.h>
+#include <linux/debugfs.h>
+#include <linux/version.h>
+#include <linux/input.h>
+#include "config.h"
+#include "tfa98xx.h"
+#include "tfa.h"
+
+ /* required for enum tfa9912_irq */
+#include "tfa98xx_tfafieldnames.h"
+
+#define TFA98XX_VERSION TFA98XX_API_REV_STR
+
+#define I2C_RETRIES 50
+#define I2C_RETRY_DELAY 5 /* ms */
+#define ERR -1
+
+/* Change volume selection behavior:
+ * Uncomment following line to generate a profile change when updating
+ * a volume control (also changes to the profile of the modified volume
+ * control)
+ */
+ /*#define TFA98XX_ALSA_CTRL_PROF_CHG_ON_VOL 1
+ */
+
+ /* Supported rates and data formats */
+#define TFA98XX_RATES SNDRV_PCM_RATE_8000_48000
+#define TFA98XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
+ SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
+
+#define TF98XX_MAX_DSP_START_TRY_COUNT 10
+
+/* data accessible by all instances */
+/* Memory pool used for DSP messages */
+static struct kmem_cache *tfa98xx_cache;
+/* Mutex protected data */
+static DEFINE_MUTEX(tfa98xx_mutex);
+static LIST_HEAD(tfa98xx_device_list);
+static int tfa98xx_device_count;
+static int tfa98xx_sync_count;
+static LIST_HEAD(profile_list); /* list of user selectable profiles */
+static int tfa98xx_mixer_profiles; /* number of user selectable profiles */
+static int tfa98xx_mixer_profile; /* current mixer profile */
+static struct snd_kcontrol_new *tfa98xx_controls;
+static nxpTfaContainer_t *tfa98xx_container;
+
+static int tfa98xx_kmsg_regs;
+static int tfa98xx_ftrace_regs;
+
+static char *fw_name = "tfa98xx.cnt";
+module_param(fw_name, charp, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(fw_name, "TFA98xx DSP firmware (container file) name.");
+
+static int trace_level;
+module_param(trace_level, int, S_IRUGO);
+MODULE_PARM_DESC(trace_level, "TFA98xx debug trace level (0=off, bits:1=verbose,2=regdmesg,3=regftrace,4=timing).");
+
+static char *dflt_prof_name = "";
+module_param(dflt_prof_name, charp, S_IRUGO);
+
+static int no_start;
+module_param(no_start, int, S_IRUGO);
+MODULE_PARM_DESC(no_start, "do not start the work queue; for debugging via user\n");
+
+static int no_reset;
+module_param(no_reset, int, S_IRUGO);
+MODULE_PARM_DESC(no_reset, "do not use the reset line; for debugging via user\n");
+
+static int pcm_sample_format;
+module_param(pcm_sample_format, int, S_IRUGO);
+MODULE_PARM_DESC(pcm_sample_format, "PCM sample format: 0=S16_LE, 1=S24_LE, 2=S32_LE\n");
+
+static int pcm_no_constraint;
+module_param(pcm_no_constraint, int, S_IRUGO);
+MODULE_PARM_DESC(pcm_no_constraint, "do not use constraints for PCM parameters\n");
+
+static void tfa98xx_tapdet_check_update(struct tfa98xx *tfa98xx);
+static int tfa98xx_get_fssel(unsigned int rate);
+static void tfa98xx_interrupt_enable(struct tfa98xx *tfa98xx, bool enable);
+
+static int get_profile_from_list(char *buf, int id);
+static int get_profile_id_for_sr(int id, unsigned int rate);
+
+struct tfa98xx_rate {
+ unsigned int rate;
+ unsigned int fssel;
+};
+
+static const struct tfa98xx_rate rate_to_fssel[] = {
+ { 8000, 0 },
+ { 11025, 1 },
+ { 12000, 2 },
+ { 16000, 3 },
+ { 22050, 4 },
+ { 24000, 5 },
+ { 32000, 6 },
+ { 44100, 7 },
+ { 48000, 8 },
+};
+
+
+static inline char *tfa_cont_profile_name(struct tfa98xx *tfa98xx,
+ int prof_idx)
+{
+ if (tfa98xx->tfa->cnt == NULL)
+ return NULL;
+ return tfaContProfileName(tfa98xx->tfa->cnt,
+ tfa98xx->tfa->dev_idx, prof_idx);
+}
+
+static enum tfa_error tfa98xx_write_re25(struct tfa_device *tfa, int value)
+{
+ enum tfa_error err;
+
+ /* clear MTPEX */
+ err = tfa_dev_mtp_set(tfa, TFA_MTP_EX, 0);
+ if (err == tfa_error_ok) {
+ /* set RE25 in shadow regiser */
+ err = tfa_dev_mtp_set(tfa, TFA_MTP_RE25_PRIM, value);
+ }
+ if (err == tfa_error_ok) {
+ /* set MTPEX to copy RE25 into MTP */
+ err = tfa_dev_mtp_set(tfa, TFA_MTP_EX, 2);
+ }
+
+ return err;
+}
+
+/* Wrapper for tfa start */
+static enum tfa_error tfa98xx_tfa_start(struct tfa98xx *tfa98xx,
+ int next_profile, int vstep)
+{
+ enum tfa_error err;
+ ktime_t start_time, stop_time;
+ u64 delta_time;
+
+ if (trace_level & 8)
+ start_time = ktime_get_boottime();
+
+ err = tfa_dev_start(tfa98xx->tfa, next_profile, vstep);
+
+ if (trace_level & 8) {
+ stop_time = ktime_get_boottime();
+ delta_time = ktime_to_ns(ktime_sub(stop_time, start_time));
+ do_div(delta_time, 1000);
+ dev_dbg(&tfa98xx->i2c->dev, "tfa_dev_start(%d,%d) time = %lld us\n",
+ next_profile, vstep, delta_time);
+ }
+
+ if ((err == tfa_error_ok) && (tfa98xx->set_mtp_cal)) {
+ enum tfa_error err_cal;
+
+ err_cal = tfa98xx_write_re25(tfa98xx->tfa, tfa98xx->cal_data);
+ if (err_cal != tfa_error_ok) {
+ pr_err("Error, setting calibration value in mtp, err=%d\n",
+ err_cal);
+ } else {
+ tfa98xx->set_mtp_cal = false;
+ pr_info("Calibration value (%d) set in mtp\n",
+ tfa98xx->cal_data);
+ }
+ }
+
+ /* Check and update tap-detection state (in case of profile change) */
+ tfa98xx_tapdet_check_update(tfa98xx);
+
+ /* Remove sticky bit by reading it once */
+ tfa_get_noclk(tfa98xx->tfa);
+
+ /* A cold start erases the configuration, including interrupts setting.
+ * Restore it if required
+ */
+ tfa98xx_interrupt_enable(tfa98xx, true);
+
+ return err;
+}
+
+static int tfa98xx_input_open(struct input_dev *dev)
+{
+ struct tfa98xx *tfa98xx = input_get_drvdata(dev);
+
+ dev_dbg(tfa98xx->codec->dev, "opening device file\n");
+
+ /* note: open function is called only once by the framework.
+ * No need to count number of open file instances.
+ */
+ if (tfa98xx->dsp_fw_state != TFA98XX_DSP_FW_OK) {
+ dev_dbg(&tfa98xx->i2c->dev,
+ "DSP not loaded, cannot start tap-detection\n");
+ return -EIO;
+ }
+
+ /* enable tap-detection service */
+ tfa98xx->tapdet_open = true;
+ tfa98xx_tapdet_check_update(tfa98xx);
+
+ return 0;
+}
+
+static void tfa98xx_input_close(struct input_dev *dev)
+{
+ struct tfa98xx *tfa98xx = input_get_drvdata(dev);
+
+ dev_dbg(tfa98xx->codec->dev, "closing device file\n");
+
+ /* Note: close function is called if the device is unregistered */
+
+ /* disable tap-detection service */
+ tfa98xx->tapdet_open = false;
+ tfa98xx_tapdet_check_update(tfa98xx);
+}
+
+static int tfa98xx_register_inputdev(struct tfa98xx *tfa98xx)
+{
+ int err;
+ struct input_dev *input;
+ input = input_allocate_device();
+
+ if (!input) {
+ dev_err(tfa98xx->codec->dev, "Unable to allocate input device\n");
+ return -ENOMEM;
+ }
+
+ input->evbit[0] = BIT_MASK(EV_KEY);
+ input->keybit[BIT_WORD(BTN_0)] |= BIT_MASK(BTN_0);
+ input->keybit[BIT_WORD(BTN_1)] |= BIT_MASK(BTN_1);
+ input->keybit[BIT_WORD(BTN_2)] |= BIT_MASK(BTN_2);
+ input->keybit[BIT_WORD(BTN_3)] |= BIT_MASK(BTN_3);
+ input->keybit[BIT_WORD(BTN_4)] |= BIT_MASK(BTN_4);
+ input->keybit[BIT_WORD(BTN_5)] |= BIT_MASK(BTN_5);
+ input->keybit[BIT_WORD(BTN_6)] |= BIT_MASK(BTN_6);
+ input->keybit[BIT_WORD(BTN_7)] |= BIT_MASK(BTN_7);
+ input->keybit[BIT_WORD(BTN_8)] |= BIT_MASK(BTN_8);
+ input->keybit[BIT_WORD(BTN_9)] |= BIT_MASK(BTN_9);
+
+ input->open = tfa98xx_input_open;
+ input->close = tfa98xx_input_close;
+
+ input->name = "tfa98xx-tapdetect";
+
+ input->id.bustype = BUS_I2C;
+ input_set_drvdata(input, tfa98xx);
+
+ err = input_register_device(input);
+ if (err) {
+ dev_err(tfa98xx->codec->dev, "Unable to register input device\n");
+ goto err_free_dev;
+ }
+
+ dev_dbg(tfa98xx->codec->dev, "Input device for tap-detection registered: %s\n",
+ input->name);
+ tfa98xx->input = input;
+ return 0;
+
+err_free_dev:
+ input_free_device(input);
+ return err;
+}
+
+/*
+ * Check if an input device for tap-detection can and shall be registered.
+ * Register it if appropriate.
+ * If already registered, check if still relevant and remove it if necessary.
+ * unregister: true to request inputdev unregistration.
+ */
+static void __tfa98xx_inputdev_check_register(struct tfa98xx *tfa98xx, bool unregister)
+{
+ bool tap_profile = false;
+ unsigned int i;
+ for (i = 0; i < tfa_cnt_get_dev_nprof(tfa98xx->tfa); i++) {
+ if (strstr(tfa_cont_profile_name(tfa98xx, i), ".tap")) {
+ tap_profile = true;
+ tfa98xx->tapdet_profiles |= 1 << i;
+ dev_info(tfa98xx->codec->dev,
+ "found a tap-detection profile (%d - %s)\n",
+ i, tfa_cont_profile_name(tfa98xx, i));
+ }
+ }
+
+ /* Check for device support:
+ * - at device level
+ * - at container (profile) level
+ */
+ if (!(tfa98xx->flags & TFA98XX_FLAG_TAPDET_AVAILABLE) ||
+ !tap_profile ||
+ unregister) {
+ /* No input device supported or required */
+ if (tfa98xx->input) {
+ input_unregister_device(tfa98xx->input);
+ tfa98xx->input = NULL;
+ }
+ return;
+ }
+
+ /* input device required */
+ if (tfa98xx->input)
+ dev_info(tfa98xx->codec->dev, "Input device already registered, skipping\n");
+ else
+ tfa98xx_register_inputdev(tfa98xx);
+}
+
+static void tfa98xx_inputdev_check_register(struct tfa98xx *tfa98xx)
+{
+ __tfa98xx_inputdev_check_register(tfa98xx, false);
+}
+
+static void tfa98xx_inputdev_unregister(struct tfa98xx *tfa98xx)
+{
+ __tfa98xx_inputdev_check_register(tfa98xx, true);
+}
+
+#ifdef CONFIG_DEBUG_FS
+/* OTC reporting
+ * Returns the MTP0 OTC bit value
+ */
+static int tfa98xx_dbgfs_otc_get(void *data, u64 *val)
+{
+ struct i2c_client *i2c = (struct i2c_client *)data;
+ struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
+ int value;
+
+ mutex_lock(&tfa98xx->dsp_lock);
+ value = tfa_dev_mtp_get(tfa98xx->tfa, TFA_MTP_OTC);
+ mutex_unlock(&tfa98xx->dsp_lock);
+
+ if (value < 0) {
+ pr_err("[0x%x] Unable to check DSP access: %d\n", tfa98xx->i2c->addr, value);
+ return -EIO;
+ }
+
+ *val = value;
+ pr_debug("[0x%x] OTC : %d\n", tfa98xx->i2c->addr, value);
+
+ return 0;
+}
+
+static int tfa98xx_dbgfs_otc_set(void *data, u64 val)
+{
+ struct i2c_client *i2c = (struct i2c_client *)data;
+ struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
+ enum tfa_error err;
+
+ if (val != 0 && val != 1) {
+ pr_err("[0x%x] Unexpected value %llu\n", tfa98xx->i2c->addr, val);
+ return -EINVAL;
+ }
+
+ mutex_lock(&tfa98xx->dsp_lock);
+ err = tfa_dev_mtp_set(tfa98xx->tfa, TFA_MTP_OTC, val);
+ mutex_unlock(&tfa98xx->dsp_lock);
+
+ if (err != tfa_error_ok) {
+ pr_err("[0x%x] Unable to check DSP access: %d\n", tfa98xx->i2c->addr, err);
+ return -EIO;
+ }
+
+ pr_debug("[0x%x] OTC < %llu\n", tfa98xx->i2c->addr, val);
+
+ return 0;
+}
+
+static int tfa98xx_dbgfs_mtpex_get(void *data, u64 *val)
+{
+ struct i2c_client *i2c = (struct i2c_client *)data;
+ struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
+ int value;
+
+ mutex_lock(&tfa98xx->dsp_lock);
+ value = tfa_dev_mtp_get(tfa98xx->tfa, TFA_MTP_EX);
+ mutex_unlock(&tfa98xx->dsp_lock);
+
+ if (value < 0) {
+ pr_err("[0x%x] Unable to check DSP access: %d\n", tfa98xx->i2c->addr, value);
+ return -EIO;
+ }
+
+
+ *val = value;
+ pr_debug("[0x%x] MTPEX : %d\n", tfa98xx->i2c->addr, value);
+
+ return 0;
+}
+
+static int tfa98xx_dbgfs_mtpex_set(void *data, u64 val)
+{
+ struct i2c_client *i2c = (struct i2c_client *)data;
+ struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
+ enum tfa_error err;
+
+ if (val != 0) {
+ pr_err("[0x%x] Can only clear MTPEX (0 value expected)\n", tfa98xx->i2c->addr);
+ return -EINVAL;
+ }
+
+ mutex_lock(&tfa98xx->dsp_lock);
+ err = tfa_dev_mtp_set(tfa98xx->tfa, TFA_MTP_EX, val);
+ mutex_unlock(&tfa98xx->dsp_lock);
+
+ if (err != tfa_error_ok) {
+ pr_err("[0x%x] Unable to check DSP access: %d\n", tfa98xx->i2c->addr, err);
+ return -EIO;
+ }
+
+ pr_debug("[0x%x] MTPEX < 0\n", tfa98xx->i2c->addr);
+
+ return 0;
+}
+
+static int tfa98xx_dbgfs_temp_get(void *data, u64 *val)
+{
+ struct i2c_client *i2c = (struct i2c_client *)data;
+ struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
+
+ mutex_lock(&tfa98xx->dsp_lock);
+ *val = tfa98xx_get_exttemp(tfa98xx->tfa);
+ mutex_unlock(&tfa98xx->dsp_lock);
+
+ pr_debug("[0x%x] TEMP : %llu\n", tfa98xx->i2c->addr, *val);
+
+ return 0;
+}
+
+static int tfa98xx_dbgfs_temp_set(void *data, u64 val)
+{
+ struct i2c_client *i2c = (struct i2c_client *)data;
+ struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
+
+ mutex_lock(&tfa98xx->dsp_lock);
+ tfa98xx_set_exttemp(tfa98xx->tfa, (short)val);
+ mutex_unlock(&tfa98xx->dsp_lock);
+
+ pr_debug("[0x%x] TEMP < %llu\n", tfa98xx->i2c->addr, val);
+
+ return 0;
+}
+
+static ssize_t tfa98xx_dbgfs_start_set(struct file *file,
+ const char __user *user_buf,
+ size_t count, loff_t *ppos)
+{
+ struct i2c_client *i2c = file->private_data;
+ struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
+ enum tfa_error ret;
+ char buf[32];
+ const char ref[] = "please calibrate now";
+ int buf_size, cal_profile = 0;
+
+ /* check string length, and account for eol */
+ if (count > sizeof(ref) + 1 || count < (sizeof(ref) - 1))
+ return -EINVAL;
+
+ buf_size = min(count, (size_t)(sizeof(buf) - 1));
+ if (copy_from_user(buf, user_buf, buf_size))
+ return -EFAULT;
+ buf[buf_size] = 0;
+
+ /* Compare string, excluding the trailing \0 and the potentials eol */
+ if (strncmp(buf, ref, sizeof(ref) - 1))
+ return -EINVAL;
+
+ mutex_lock(&tfa98xx->dsp_lock);
+ ret = (enum tfa_error)tfa_calibrate(tfa98xx->tfa);
+ if (ret == tfa_error_ok) {
+ cal_profile = tfaContGetCalProfile(tfa98xx->tfa);
+ if (cal_profile < 0) {
+ pr_warn("[0x%x] Calibration profile not found\n",
+ tfa98xx->i2c->addr);
+ }
+
+ ret = tfa98xx_tfa_start(tfa98xx, cal_profile, tfa98xx->vstep);
+ }
+ if (ret == tfa_error_ok)
+ tfa_dev_set_state(tfa98xx->tfa, TFA_STATE_UNMUTE, 0);
+ mutex_unlock(&tfa98xx->dsp_lock);
+
+ if (ret) {
+ pr_info("[0x%x] Calibration start failed (%d)\n", tfa98xx->i2c->addr, ret);
+ return -EIO;
+ } else {
+ pr_info("[0x%x] Calibration started\n", tfa98xx->i2c->addr);
+ }
+
+ return count;
+}
+
+static ssize_t tfa98xx_dbgfs_r_read(struct file *file,
+ char __user *user_buf, size_t count,
+ loff_t *ppos)
+{
+ struct i2c_client *i2c = file->private_data;
+ struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
+ char *str;
+ uint16_t status;
+ int ret;
+
+ mutex_lock(&tfa98xx->dsp_lock);
+
+ /* Need to ensure DSP is access-able, use mtp read access for this
+ * purpose
+ */
+ ret = tfa98xx_get_mtp(tfa98xx->tfa, &status);
+ if (ret) {
+ ret = -EIO;
+ pr_err("[0x%x] MTP read failed\n", tfa98xx->i2c->addr);
+ goto r_c_err;
+ }
+
+ ret = tfaRunSpeakerCalibration(tfa98xx->tfa);
+ if (ret) {
+ ret = -EIO;
+ pr_err("[0x%x] calibration failed\n", tfa98xx->i2c->addr);
+ goto r_c_err;
+ }
+
+ str = kmalloc(PAGE_SIZE, GFP_KERNEL);
+ if (!str) {
+ ret = -ENOMEM;
+ pr_err("[0x%x] memory allocation failed\n", tfa98xx->i2c->addr);
+ goto r_c_err;
+ }
+
+ if (tfa98xx->tfa->spkr_count > 1) {
+ ret = snprintf(str, PAGE_SIZE,
+ "Prim:%d mOhms, Sec:%d mOhms\n",
+ tfa98xx->tfa->mohm[0],
+ tfa98xx->tfa->mohm[1]);
+ } else {
+ ret = snprintf(str, PAGE_SIZE,
+ "Prim:%d mOhms\n",
+ tfa98xx->tfa->mohm[0]);
+ }
+
+ pr_debug("[0x%x] calib_done: %s", tfa98xx->i2c->addr, str);
+
+ if (ret < 0)
+ goto r_err;
+
+ ret = simple_read_from_buffer(user_buf, count, ppos, str, ret);
+
+r_err:
+ kfree(str);
+r_c_err:
+ mutex_unlock(&tfa98xx->dsp_lock);
+ return ret;
+}
+
+static ssize_t tfa98xx_dbgfs_version_read(struct file *file,
+ char __user *user_buf, size_t count,
+ loff_t *ppos)
+{
+ char str[] = TFA98XX_VERSION "\n";
+ int ret;
+
+ ret = simple_read_from_buffer(user_buf, count, ppos, str, sizeof(str));
+
+ return ret;
+}
+
+static ssize_t tfa98xx_dbgfs_dsp_state_get(struct file *file,
+ char __user *user_buf, size_t count,
+ loff_t *ppos)
+{
+ struct i2c_client *i2c = file->private_data;
+ struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
+ int ret = 0;
+ char *str;
+
+ switch (tfa98xx->dsp_init) {
+ case TFA98XX_DSP_INIT_STOPPED:
+ str = "Stopped\n";
+ break;
+ case TFA98XX_DSP_INIT_RECOVER:
+ str = "Recover requested\n";
+ break;
+ case TFA98XX_DSP_INIT_FAIL:
+ str = "Failed init\n";
+ break;
+ case TFA98XX_DSP_INIT_PENDING:
+ str = "Pending init\n";
+ break;
+ case TFA98XX_DSP_INIT_DONE:
+ str = "Init complete\n";
+ break;
+ default:
+ str = "Invalid\n";
+ }
+
+ pr_debug("[0x%x] dsp_state : %s\n", tfa98xx->i2c->addr, str);
+
+ ret = simple_read_from_buffer(user_buf, count, ppos, str, strlen(str));
+ return ret;
+}
+
+static ssize_t tfa98xx_dbgfs_dsp_state_set(struct file *file,
+ const char __user *user_buf,
+ size_t count, loff_t *ppos)
+{
+ struct i2c_client *i2c = file->private_data;
+ struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
+ enum tfa_error ret;
+ char buf[32];
+ const char start_cmd[] = "start";
+ const char stop_cmd[] = "stop";
+ const char mon_start_cmd[] = "monitor start";
+ const char mon_stop_cmd[] = "monitor stop";
+ int buf_size;
+
+ buf_size = min(count, (size_t)(sizeof(buf) - 1));
+ if (copy_from_user(buf, user_buf, buf_size))
+ return -EFAULT;
+ buf[buf_size] = 0;
+
+ /* Compare strings, excluding the trailing \0 */
+ if (!strncmp(buf, start_cmd, sizeof(start_cmd) - 1)) {
+ pr_info("[0x%x] Manual triggering of dsp start...\n", tfa98xx->i2c->addr);
+ mutex_lock(&tfa98xx->dsp_lock);
+ ret = tfa98xx_tfa_start(tfa98xx, tfa98xx->profile, tfa98xx->vstep);
+ mutex_unlock(&tfa98xx->dsp_lock);
+ pr_debug("[0x%x] tfa_dev_start complete: %d\n", tfa98xx->i2c->addr, ret);
+ } else if (!strncmp(buf, stop_cmd, sizeof(stop_cmd) - 1)) {
+ pr_info("[0x%x] Manual triggering of dsp stop...\n", tfa98xx->i2c->addr);
+ mutex_lock(&tfa98xx->dsp_lock);
+ ret = tfa_dev_stop(tfa98xx->tfa);
+ mutex_unlock(&tfa98xx->dsp_lock);
+ pr_debug("[0x%x] tfa_dev_stop complete: %d\n", tfa98xx->i2c->addr, ret);
+ } else if (!strncmp(buf, mon_start_cmd, sizeof(mon_start_cmd) - 1)) {
+ pr_info("[0x%x] Manual start of monitor thread...\n", tfa98xx->i2c->addr);
+ queue_delayed_work(tfa98xx->tfa98xx_wq,
+ &tfa98xx->monitor_work, HZ);
+ } else if (!strncmp(buf, mon_stop_cmd, sizeof(mon_stop_cmd) - 1)) {
+ pr_info("[0x%x] Manual stop of monitor thread...\n", tfa98xx->i2c->addr);
+ cancel_delayed_work_sync(&tfa98xx->monitor_work);
+ } else {
+ return -EINVAL;
+ }
+
+ return count;
+}
+
+static ssize_t tfa98xx_dbgfs_fw_state_get(struct file *file,
+ char __user *user_buf, size_t count,
+ loff_t *ppos)
+{
+ struct i2c_client *i2c = file->private_data;
+ struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
+ char *str;
+
+ switch (tfa98xx->dsp_fw_state) {
+ case TFA98XX_DSP_FW_NONE:
+ str = "None\n";
+ break;
+ case TFA98XX_DSP_FW_PENDING:
+ str = "Pending\n";
+ break;
+ case TFA98XX_DSP_FW_FAIL:
+ str = "Fail\n";
+ break;
+ case TFA98XX_DSP_FW_OK:
+ str = "Ok\n";
+ break;
+ default:
+ str = "Invalid\n";
+ }
+
+ pr_debug("[0x%x] fw_state : %s", tfa98xx->i2c->addr, str);
+
+ return simple_read_from_buffer(user_buf, count, ppos, str, strlen(str));
+}
+
+static ssize_t tfa98xx_dbgfs_rpc_read(struct file *file,
+ char __user *user_buf, size_t count,
+ loff_t *ppos)
+{
+ struct i2c_client *i2c = file->private_data;
+ struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
+ int ret = 0;
+ uint8_t *buffer;
+ enum Tfa98xx_Error error;
+
+ if (tfa98xx->tfa == NULL) {
+ pr_debug("[0x%x] dsp is not available\n", tfa98xx->i2c->addr);
+ return -ENODEV;
+ }
+
+ if (count == 0)
+ return 0;
+
+ buffer = kmalloc(count, GFP_KERNEL);
+ if (buffer == NULL) {
+ pr_debug("[0x%x] can not allocate memory\n", tfa98xx->i2c->addr);
+ return -ENOMEM;
+ }
+
+ mutex_lock(&tfa98xx->dsp_lock);
+ error = dsp_msg_read(tfa98xx->tfa, count, buffer);
+ mutex_unlock(&tfa98xx->dsp_lock);
+ if (error != Tfa98xx_Error_Ok) {
+ pr_debug("[0x%x] dsp_msg_read error: %d\n", tfa98xx->i2c->addr, error);
+ kfree(buffer);
+ return -EFAULT;
+ }
+
+ ret = copy_to_user(user_buf, buffer, count);
+ kfree(buffer);
+ if (ret)
+ return -EFAULT;
+
+ *ppos += count;
+ return count;
+}
+
+static ssize_t tfa98xx_dbgfs_rpc_send(struct file *file,
+ const char __user *user_buf,
+ size_t count, loff_t *ppos)
+{
+ struct i2c_client *i2c = file->private_data;
+ struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
+ nxpTfaFileDsc_t *msg_file;
+ enum Tfa98xx_Error error;
+ int err = 0;
+
+ if (tfa98xx->tfa == NULL) {
+ pr_debug("[0x%x] dsp is not available\n", tfa98xx->i2c->addr);
+ return -ENODEV;
+ }
+
+ if (count == 0)
+ return 0;
+
+ /* msg_file.name is not used */
+ msg_file = kmalloc(count + sizeof(nxpTfaFileDsc_t), GFP_KERNEL);
+ if (msg_file == NULL) {
+ pr_debug("[0x%x] can not allocate memory\n", tfa98xx->i2c->addr);
+ return -ENOMEM;
+ }
+ msg_file->size = count;
+
+ if (copy_from_user(msg_file->data, user_buf, count))
+ return -EFAULT;
+
+ mutex_lock(&tfa98xx->dsp_lock);
+ if ((msg_file->data[0] == 'M') && (msg_file->data[1] == 'G')) {
+ /* int vstep_idx, int vstep_msg_idx both 0 */
+ error = tfaContWriteFile(tfa98xx->tfa, msg_file, 0, 0);
+ if (error != Tfa98xx_Error_Ok) {
+ pr_debug("[0x%x] tfaContWriteFile error: %d\n",
+ tfa98xx->i2c->addr, error);
+ err = -EIO;
+ }
+ } else {
+ error = dsp_msg(tfa98xx->tfa, msg_file->size, msg_file->data);
+ if (error != Tfa98xx_Error_Ok) {
+ pr_debug("[0x%x] dsp_msg error: %d\n", tfa98xx->i2c->addr, error);
+ err = -EIO;
+ }
+ }
+ mutex_unlock(&tfa98xx->dsp_lock);
+
+ kfree(msg_file);
+
+ if (err)
+ return err;
+ return count;
+}
+/* -- RPC */
+
+static int tfa98xx_dbgfs_pga_gain_get(void *data, u64 *val)
+{
+ struct i2c_client *i2c = (struct i2c_client *)data;
+ struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
+ unsigned int value;
+
+ value = tfa_get_pga_gain(tfa98xx->tfa);
+ if (value < 0)
+ return -EINVAL;
+
+ *val = value;
+ return 0;
+}
+
+static int tfa98xx_dbgfs_pga_gain_set(void *data, u64 val)
+{
+ struct i2c_client *i2c = (struct i2c_client *)data;
+ struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
+ uint16_t value;
+ int err;
+
+ value = val & 0xffff;
+ if (value > 7)
+ return -EINVAL;
+
+ err = tfa_set_pga_gain(tfa98xx->tfa, value);
+ if (err < 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(tfa98xx_dbgfs_calib_otc_fops, tfa98xx_dbgfs_otc_get,
+ tfa98xx_dbgfs_otc_set, "%llu\n");
+DEFINE_SIMPLE_ATTRIBUTE(tfa98xx_dbgfs_calib_mtpex_fops, tfa98xx_dbgfs_mtpex_get,
+ tfa98xx_dbgfs_mtpex_set, "%llu\n");
+DEFINE_SIMPLE_ATTRIBUTE(tfa98xx_dbgfs_calib_temp_fops, tfa98xx_dbgfs_temp_get,
+ tfa98xx_dbgfs_temp_set, "%llu\n");
+
+DEFINE_SIMPLE_ATTRIBUTE(tfa98xx_dbgfs_pga_gain_fops, tfa98xx_dbgfs_pga_gain_get,
+ tfa98xx_dbgfs_pga_gain_set, "%llu\n");
+
+static const struct file_operations tfa98xx_dbgfs_calib_start_fops = {
+ .owner = THIS_MODULE,
+ .open = simple_open,
+ .write = tfa98xx_dbgfs_start_set,
+ .llseek = default_llseek,
+};
+
+static const struct file_operations tfa98xx_dbgfs_r_fops = {
+ .owner = THIS_MODULE,
+ .open = simple_open,
+ .read = tfa98xx_dbgfs_r_read,
+ .llseek = default_llseek,
+};
+
+static const struct file_operations tfa98xx_dbgfs_version_fops = {
+ .owner = THIS_MODULE,
+ .open = simple_open,
+ .read = tfa98xx_dbgfs_version_read,
+ .llseek = default_llseek,
+};
+
+static const struct file_operations tfa98xx_dbgfs_dsp_state_fops = {
+ .owner = THIS_MODULE,
+ .open = simple_open,
+ .read = tfa98xx_dbgfs_dsp_state_get,
+ .write = tfa98xx_dbgfs_dsp_state_set,
+ .llseek = default_llseek,
+};
+
+static const struct file_operations tfa98xx_dbgfs_fw_state_fops = {
+ .owner = THIS_MODULE,
+ .open = simple_open,
+ .read = tfa98xx_dbgfs_fw_state_get,
+ .llseek = default_llseek,
+};
+
+static const struct file_operations tfa98xx_dbgfs_rpc_fops = {
+ .owner = THIS_MODULE,
+ .open = simple_open,
+ .read = tfa98xx_dbgfs_rpc_read,
+ .write = tfa98xx_dbgfs_rpc_send,
+ .llseek = default_llseek,
+};
+
+static void tfa98xx_debug_init(struct tfa98xx *tfa98xx,
+ struct i2c_client *i2c)
+{
+ char name[50];
+
+ scnprintf(name, MAX_CONTROL_NAME, "%s-%x", i2c->name, i2c->addr);
+ tfa98xx->dbg_dir = debugfs_create_dir(name, NULL);
+ debugfs_create_file("OTC", S_IRUGO | S_IWUGO, tfa98xx->dbg_dir,
+ i2c, &tfa98xx_dbgfs_calib_otc_fops);
+ debugfs_create_file("MTPEX", S_IRUGO | S_IWUGO, tfa98xx->dbg_dir,
+ i2c, &tfa98xx_dbgfs_calib_mtpex_fops);
+ debugfs_create_file("TEMP", S_IRUGO | S_IWUGO, tfa98xx->dbg_dir,
+ i2c, &tfa98xx_dbgfs_calib_temp_fops);
+ debugfs_create_file("calibrate", S_IRUGO | S_IWUGO, tfa98xx->dbg_dir,
+ i2c, &tfa98xx_dbgfs_calib_start_fops);
+ debugfs_create_file("R", S_IRUGO, tfa98xx->dbg_dir,
+ i2c, &tfa98xx_dbgfs_r_fops);
+ debugfs_create_file("version", S_IRUGO, tfa98xx->dbg_dir,
+ i2c, &tfa98xx_dbgfs_version_fops);
+ debugfs_create_file("dsp-state", S_IRUGO | S_IWUGO, tfa98xx->dbg_dir,
+ i2c, &tfa98xx_dbgfs_dsp_state_fops);
+ debugfs_create_file("fw-state", S_IRUGO | S_IWUGO, tfa98xx->dbg_dir,
+ i2c, &tfa98xx_dbgfs_fw_state_fops);
+ debugfs_create_file("rpc", S_IRUGO | S_IWUGO, tfa98xx->dbg_dir,
+ i2c, &tfa98xx_dbgfs_rpc_fops);
+
+ if (tfa98xx->flags & TFA98XX_FLAG_SAAM_AVAILABLE) {
+ dev_dbg(tfa98xx->dev, "Adding pga_gain debug interface\n");
+ debugfs_create_file("pga_gain", S_IRUGO, tfa98xx->dbg_dir,
+ tfa98xx->i2c,
+ &tfa98xx_dbgfs_pga_gain_fops);
+ }
+}
+
+static void tfa98xx_debug_remove(struct tfa98xx *tfa98xx)
+{
+ if (tfa98xx->dbg_dir)
+ debugfs_remove_recursive(tfa98xx->dbg_dir);
+}
+#endif
+
+
+/* copies the profile basename (i.e. part until .) into buf */
+static void get_profile_basename(char *buf, char *profile)
+{
+ int cp_len = 0, idx = 0;
+ char *pch;
+
+ pch = strchr(profile, '.');
+ idx = pch - profile;
+ cp_len = (pch != NULL) ? idx : (int)strlen(profile);
+ memcpy(buf, profile, cp_len);
+ buf[cp_len] = 0;
+}
+
+/* return the profile name accociated with id from the profile list */
+static int get_profile_from_list(char *buf, int id)
+{
+ struct tfa98xx_baseprofile *bprof;
+
+ list_for_each_entry(bprof, &profile_list, list) {
+ if (bprof->item_id == id) {
+ strcpy(buf, bprof->basename);
+ return 0;
+ }
+ }
+
+ return ERR;
+}
+
+/* search for the profile in the profile list */
+static int is_profile_in_list(char *profile, int len)
+{
+ struct tfa98xx_baseprofile *bprof;
+
+ list_for_each_entry(bprof, &profile_list, list) {
+
+ if ((len == bprof->len) && (0 == strncmp(bprof->basename,
+ profile, len)))
+ return 1;
+ }
+
+ return 0;
+}
+
+/*
+ * for the profile with id, look if the requested samplerate is
+ * supported, if found return the (container)profile for this
+ * samplerate, on error or if not found return -1
+ */
+static int get_profile_id_for_sr(int id, unsigned int rate)
+{
+ int idx = 0;
+ struct tfa98xx_baseprofile *bprof;
+
+ list_for_each_entry(bprof, &profile_list, list) {
+ if (id == bprof->item_id) {
+ idx = tfa98xx_get_fssel(rate);
+ if (idx < 0) {
+ /* samplerate not supported */
+ return ERR;
+ }
+
+ return bprof->sr_rate_sup[idx];
+ }
+ }
+
+ /* profile not found */
+ return ERR;
+}
+
+/* check if this profile is a calibration profile */
+static int is_calibration_profile(char *profile)
+{
+ if (strstr(profile, ".cal") != NULL)
+ return 1;
+ return 0;
+}
+
+/*
+ * adds the (container)profile index of the samplerate found in
+ * the (container)profile to a fixed samplerate table in the (mixer)profile
+ */
+static int add_sr_to_profile(struct tfa98xx *tfa98xx, char *basename,
+ int len, int profile)
+{
+ struct tfa98xx_baseprofile *bprof;
+ int idx = 0;
+ unsigned int sr = 0;
+
+ list_for_each_entry(bprof, &profile_list, list) {
+ if ((len == bprof->len) && (0 == strncmp(bprof->basename,
+ basename, len))) {
+ /* add supported samplerate for this profile */
+ sr = tfa98xx_get_profile_sr(tfa98xx->tfa, profile);
+ if (!sr) {
+ pr_err("unable to identify supported sample rate for %s\n",
+ bprof->basename);
+ return ERR;
+ }
+
+ /* get the index for this samplerate */
+ idx = tfa98xx_get_fssel(sr);
+ if (idx < 0 || idx >= TFA98XX_NUM_RATES) {
+ pr_err("invalid index for samplerate %d\n", idx);
+ return ERR;
+ }
+
+ /* enter the (container)profile for this samplerate
+ * at the corresponding index
+ */
+ bprof->sr_rate_sup[idx] = profile;
+
+ pr_debug("added profile:samplerate = [%d:%d]\
+ for mixer profile: %s\n", profile, sr, bprof->basename);
+ }
+ }
+
+ return 0;
+}
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0)
+static struct snd_soc_codec *snd_soc_kcontrol_codec(
+ struct snd_kcontrol *kcontrol)
+{
+ return snd_kcontrol_chip(kcontrol);
+}
+#endif
+
+static int tfa98xx_get_vstep(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+ struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec);
+ int mixer_profile = kcontrol->private_value;
+ int ret = 0;
+ int profile;
+
+ profile = get_profile_id_for_sr(mixer_profile, tfa98xx->rate);
+ if (profile < 0) {
+ pr_err("tfa98xx: tfa98xx_get_vstep: invalid profile %d\
+ (mixer_profile=%d, rate=%d)\n", profile, mixer_profile, tfa98xx->rate);
+ return -EINVAL;
+ }
+
+ mutex_lock(&tfa98xx_mutex);
+ list_for_each_entry(tfa98xx, &tfa98xx_device_list, list) {
+ int vstep = tfa98xx->prof_vsteps[profile];
+
+ ucontrol->value.integer.value[tfa98xx->tfa->dev_idx] =
+ tfacont_get_max_vstep(tfa98xx->tfa, profile)
+ - vstep - 1;
+ }
+ mutex_unlock(&tfa98xx_mutex);
+
+ return ret;
+}
+
+static int tfa98xx_set_vstep(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+ struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec);
+ int mixer_profile = kcontrol->private_value;
+ int profile;
+ int err = 0;
+ int change = 0;
+
+ if (no_start != 0)
+ return 0;
+
+ profile = get_profile_id_for_sr(mixer_profile, tfa98xx->rate);
+ if (profile < 0) {
+ pr_err("tfa98xx: tfa98xx_set_vstep: invalid profile %d\
+ (mixer_profile=%d, rate=%d)\n", profile, mixer_profile, tfa98xx->rate);
+ return -EINVAL;
+ }
+
+ mutex_lock(&tfa98xx_mutex);
+ list_for_each_entry(tfa98xx, &tfa98xx_device_list, list) {
+ int vstep, vsteps;
+ int ready = 0;
+ int new_vstep;
+ int value = ucontrol->value.integer.value[tfa98xx->tfa->dev_idx];
+
+ vstep = tfa98xx->prof_vsteps[profile];
+ vsteps = tfacont_get_max_vstep(tfa98xx->tfa, profile);
+
+ if (vstep == vsteps - value - 1)
+ continue;
+
+ new_vstep = vsteps - value - 1;
+
+ if (new_vstep < 0)
+ new_vstep = 0;
+
+ tfa98xx->prof_vsteps[profile] = new_vstep;
+
+#ifndef TFA98XX_ALSA_CTRL_PROF_CHG_ON_VOL
+ if (profile == tfa98xx->profile) {
+#endif
+ /* this is the active profile, program the new vstep */
+ tfa98xx->vstep = new_vstep;
+ mutex_lock(&tfa98xx->dsp_lock);
+ tfa98xx_dsp_system_stable(tfa98xx->tfa, &ready);
+
+ if (ready) {
+ err = tfa98xx_tfa_start(tfa98xx, tfa98xx->profile,
+ tfa98xx->vstep);
+ if (err) {
+ pr_err("Write vstep error: %d\n", err);
+ } else {
+ pr_debug("Succesfully changed vstep index!\n");
+ change = 1;
+ }
+ }
+
+ mutex_unlock(&tfa98xx->dsp_lock);
+#ifndef TFA98XX_ALSA_CTRL_PROF_CHG_ON_VOL
+ }
+#endif
+ pr_debug("%d: vstep:%d, (control value: %d) - profile %d\n",
+ tfa98xx->tfa->dev_idx, new_vstep, value, profile);
+ }
+
+ if (change) {
+ list_for_each_entry(tfa98xx, &tfa98xx_device_list, list) {
+ mutex_lock(&tfa98xx->dsp_lock);
+ tfa_dev_set_state(tfa98xx->tfa, TFA_STATE_UNMUTE, 0);
+ mutex_unlock(&tfa98xx->dsp_lock);
+ }
+ }
+
+ mutex_unlock(&tfa98xx_mutex);
+
+ return change;
+}
+
+static int tfa98xx_info_vstep(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+ struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec);
+
+ int mixer_profile = tfa98xx_mixer_profile;
+ int profile = get_profile_id_for_sr(mixer_profile, tfa98xx->rate);
+ if (profile < 0) {
+ pr_err("tfa98xx: tfa98xx_info_vstep: invalid profile %d\
+ (mixer_profile=%d, rate=%d)\n", profile, mixer_profile, tfa98xx->rate);
+ return -EINVAL;
+ }
+
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+ mutex_lock(&tfa98xx_mutex);
+ uinfo->count = tfa98xx_device_count;
+ mutex_unlock(&tfa98xx_mutex);
+ uinfo->value.integer.min = 0;
+ uinfo->value.integer.max = max(0,
+ tfacont_get_max_vstep(tfa98xx->tfa, profile) - 1);
+ pr_debug("vsteps count: %d [prof=%d]\n",
+ tfacont_get_max_vstep(tfa98xx->tfa, profile),
+ profile);
+ return 0;
+}
+
+static int tfa98xx_get_profile(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ mutex_lock(&tfa98xx_mutex);
+ ucontrol->value.integer.value[0] = tfa98xx_mixer_profile;
+ mutex_unlock(&tfa98xx_mutex);
+
+ return 0;
+}
+
+static int tfa98xx_set_profile(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+ struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec);
+ int change = 0;
+ int new_profile;
+ int prof_idx;
+ int profile_count = tfa98xx_mixer_profiles;
+ int profile = tfa98xx_mixer_profile;
+
+ if (no_start != 0)
+ return 0;
+
+ new_profile = ucontrol->value.integer.value[0];
+ if (new_profile == profile)
+ return 0;
+
+ if ((new_profile < 0) || (new_profile >= profile_count)) {
+ pr_err("not existing profile (%d)\n", new_profile);
+ return -EINVAL;
+ }
+
+ /* get the container profile for the requested sample rate */
+ prof_idx = get_profile_id_for_sr(new_profile, tfa98xx->rate);
+ if (prof_idx < 0) {
+ pr_err("tfa98xx: sample rate [%d] not supported for this \
+ mixer profile [%d].\n", tfa98xx->rate, new_profile);
+ return 0;
+ }
+ pr_debug("selected container profile [%d]\n", prof_idx);
+
+ /* update mixer profile */
+ tfa98xx_mixer_profile = new_profile;
+
+ mutex_lock(&tfa98xx_mutex);
+ list_for_each_entry(tfa98xx, &tfa98xx_device_list, list) {
+ int err;
+ int ready = 0;
+
+ /* update 'real' profile (container profile) */
+ tfa98xx->profile = prof_idx;
+ tfa98xx->vstep = tfa98xx->prof_vsteps[prof_idx];
+
+ /* Don't call tfa_dev_start() if there is no clock. */
+ mutex_lock(&tfa98xx->dsp_lock);
+ tfa98xx_dsp_system_stable(tfa98xx->tfa, &ready);
+ if (ready) {
+ /* Also re-enables the interrupts */
+ err = tfa98xx_tfa_start(tfa98xx, prof_idx, tfa98xx->vstep);
+ if (err) {
+ pr_info("Write profile error: %d\n", err);
+ } else {
+ pr_debug("Changed to profile %d (vstep = %d)\n",
+ prof_idx, tfa98xx->vstep);
+ change = 1;
+ }
+ }
+ mutex_unlock(&tfa98xx->dsp_lock);
+
+ /* Flag DSP as invalidated as the profile change may invalidate the
+ * current DSP configuration. That way, further stream start can
+ * trigger a tfa_dev_start.
+ */
+ tfa98xx->dsp_init = TFA98XX_DSP_INIT_INVALIDATED;
+ }
+
+ if (change) {
+ list_for_each_entry(tfa98xx, &tfa98xx_device_list, list) {
+ mutex_lock(&tfa98xx->dsp_lock);
+ tfa_dev_set_state(tfa98xx->tfa, TFA_STATE_UNMUTE, 0);
+ mutex_unlock(&tfa98xx->dsp_lock);
+ }
+ }
+
+ mutex_unlock(&tfa98xx_mutex);
+
+ return change;
+}
+
+static int tfa98xx_info_profile(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ char profile_name[MAX_CONTROL_NAME] = { 0 };
+ int count = tfa98xx_mixer_profiles, err = -1;
+
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
+ uinfo->count = 1;
+ uinfo->value.enumerated.items = count;
+
+ if (uinfo->value.enumerated.item >= count)
+ uinfo->value.enumerated.item = count - 1;
+
+ err = get_profile_from_list(profile_name, uinfo->value.enumerated.item);
+ if (err != 0)
+ return -EINVAL;
+
+ strcpy(uinfo->value.enumerated.name, profile_name);
+
+ return 0;
+}
+
+static int tfa98xx_info_stop_ctl(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+ mutex_lock(&tfa98xx_mutex);
+ uinfo->count = tfa98xx_device_count;
+ mutex_unlock(&tfa98xx_mutex);
+ uinfo->value.integer.min = 0;
+ uinfo->value.integer.max = 1;
+
+ return 0;
+}
+
+static int tfa98xx_get_stop_ctl(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct tfa98xx *tfa98xx;
+
+ mutex_lock(&tfa98xx_mutex);
+ list_for_each_entry(tfa98xx, &tfa98xx_device_list, list) {
+ ucontrol->value.integer.value[tfa98xx->tfa->dev_idx] = 0;
+ }
+ mutex_unlock(&tfa98xx_mutex);
+
+ return 0;
+}
+
+static int tfa98xx_set_stop_ctl(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct tfa98xx *tfa98xx;
+
+ mutex_lock(&tfa98xx_mutex);
+ list_for_each_entry(tfa98xx, &tfa98xx_device_list, list) {
+ int ready = 0;
+ int i = tfa98xx->tfa->dev_idx;
+
+ pr_debug("%d: %ld\n", i, ucontrol->value.integer.value[i]);
+
+ tfa98xx_dsp_system_stable(tfa98xx->tfa, &ready);
+
+ if ((ucontrol->value.integer.value[i] != 0) && ready) {
+ cancel_delayed_work_sync(&tfa98xx->monitor_work);
+
+ cancel_delayed_work_sync(&tfa98xx->init_work);
+ if (tfa98xx->dsp_fw_state != TFA98XX_DSP_FW_OK)
+ continue;
+
+ mutex_lock(&tfa98xx->dsp_lock);
+ tfa_dev_stop(tfa98xx->tfa);
+ tfa98xx->dsp_init = TFA98XX_DSP_INIT_STOPPED;
+ mutex_unlock(&tfa98xx->dsp_lock);
+ }
+
+ ucontrol->value.integer.value[i] = 0;
+ }
+ mutex_unlock(&tfa98xx_mutex);
+
+ return 1;
+}
+
+static int tfa98xx_info_cal_ctl(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+ mutex_lock(&tfa98xx_mutex);
+ uinfo->count = tfa98xx_device_count;
+ mutex_unlock(&tfa98xx_mutex);
+ uinfo->value.integer.min = 0;
+ uinfo->value.integer.max = 0xffff; /* 16 bit value */
+
+ return 0;
+}
+
+static int tfa98xx_set_cal_ctl(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct tfa98xx *tfa98xx;
+
+ mutex_lock(&tfa98xx_mutex);
+ list_for_each_entry(tfa98xx, &tfa98xx_device_list, list) {
+ enum tfa_error err;
+ int i = tfa98xx->tfa->dev_idx;
+
+ tfa98xx->cal_data = (uint16_t)ucontrol->value.integer.value[i];
+
+ mutex_lock(&tfa98xx->dsp_lock);
+ err = tfa98xx_write_re25(tfa98xx->tfa, tfa98xx->cal_data);
+ tfa98xx->set_mtp_cal = (err != tfa_error_ok);
+ if (tfa98xx->set_mtp_cal == false) {
+ pr_info("Calibration value (%d) set in mtp\n",
+ tfa98xx->cal_data);
+ }
+ mutex_unlock(&tfa98xx->dsp_lock);
+ }
+ mutex_unlock(&tfa98xx_mutex);
+
+ return 1;
+}
+
+static int tfa98xx_get_cal_ctl(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct tfa98xx *tfa98xx;
+
+ mutex_lock(&tfa98xx_mutex);
+ list_for_each_entry(tfa98xx, &tfa98xx_device_list, list) {
+ mutex_lock(&tfa98xx->dsp_lock);
+ ucontrol->value.integer.value[tfa98xx->tfa->dev_idx] =
+ tfa_dev_mtp_get(tfa98xx->tfa, TFA_MTP_RE25_PRIM);
+ mutex_unlock(&tfa98xx->dsp_lock);
+ }
+ mutex_unlock(&tfa98xx_mutex);
+
+ return 0;
+}
+
+static int tfa98xx_create_controls(struct tfa98xx *tfa98xx)
+{
+ int prof, nprof, mix_index = 0;
+ int nr_controls = 0, id = 0;
+ char *name;
+ struct tfa98xx_baseprofile *bprofile;
+
+ /* Create the following controls:
+ * - enum control to select the active profile
+ * - one volume control for each profile hosting a vstep
+ * - Stop control on TFA1 devices
+ */
+
+ nr_controls = 2; /* Profile and stop control */
+
+ if (tfa98xx->flags & TFA98XX_FLAG_CALIBRATION_CTL)
+ nr_controls += 1; /* calibration */
+
+ /* allocate the tfa98xx_controls base on the nr of profiles */
+ nprof = tfa_cnt_get_dev_nprof(tfa98xx->tfa);
+ for (prof = 0; prof < nprof; prof++) {
+ if (tfacont_get_max_vstep(tfa98xx->tfa, prof))
+ nr_controls++; /* Playback Volume control */
+ }
+
+ tfa98xx_controls = devm_kzalloc(tfa98xx->codec->dev,
+ nr_controls * sizeof(tfa98xx_controls[0]), GFP_KERNEL);
+ if (!tfa98xx_controls)
+ return -ENOMEM;
+
+ /* Create a mixer item for selecting the active profile */
+ name = devm_kzalloc(tfa98xx->codec->dev, MAX_CONTROL_NAME, GFP_KERNEL);
+ if (!name)
+ return -ENOMEM;
+ scnprintf(name, MAX_CONTROL_NAME, "%s Profile", tfa98xx->fw.name);
+ tfa98xx_controls[mix_index].name = name;
+ tfa98xx_controls[mix_index].iface = SNDRV_CTL_ELEM_IFACE_MIXER;
+ tfa98xx_controls[mix_index].info = tfa98xx_info_profile;
+ tfa98xx_controls[mix_index].get = tfa98xx_get_profile;
+ tfa98xx_controls[mix_index].put = tfa98xx_set_profile;
+ /* save number of profiles */
+ // tfa98xx_controls[mix_index].private_value = profs;
+ mix_index++;
+
+ /* create mixer items for each profile that has volume */
+ for (prof = 0; prof < nprof; prof++) {
+ /* create an new empty profile */
+ bprofile = devm_kzalloc(tfa98xx->codec->dev,
+ sizeof(*bprofile), GFP_KERNEL);
+ if (!bprofile)
+ return -ENOMEM;
+
+ bprofile->len = 0;
+ bprofile->item_id = -1;
+ INIT_LIST_HEAD(&bprofile->list);
+
+ /* copy profile name into basename until the . */
+ get_profile_basename(bprofile->basename,
+ tfa_cont_profile_name(tfa98xx, prof));
+ bprofile->len = strlen(bprofile->basename);
+
+ /*
+ * search the profile list for a profile with basename, if it is not
+ * found then add it to the list and add a new mixer control
+ * (if it has vsteps)also, if it is a calibration profile,
+ * do not add it to the list
+ */
+ if ((is_profile_in_list(bprofile->basename, bprofile->len) == 0) &&
+ is_calibration_profile(
+ tfa_cont_profile_name(tfa98xx, prof)) == 0) {
+ /* the profile is not present, add it to the list */
+ list_add(&bprofile->list, &profile_list);
+ bprofile->item_id = id++;
+
+ pr_debug("profile added [%d]: %s\n",
+ bprofile->item_id, bprofile->basename);
+
+ if (tfacont_get_max_vstep(tfa98xx->tfa, prof)) {
+ name = devm_kzalloc(tfa98xx->codec->dev, MAX_CONTROL_NAME,
+ GFP_KERNEL);
+ if (!name)
+ return -ENOMEM;
+
+ scnprintf(name, MAX_CONTROL_NAME, "%s %s Playback Volume",
+ tfa98xx->fw.name, bprofile->basename);
+
+ tfa98xx_controls[mix_index].name = name;
+ tfa98xx_controls[mix_index].iface = SNDRV_CTL_ELEM_IFACE_MIXER;
+ tfa98xx_controls[mix_index].info = tfa98xx_info_vstep;
+ tfa98xx_controls[mix_index].get = tfa98xx_get_vstep;
+ tfa98xx_controls[mix_index].put = tfa98xx_set_vstep;
+ /* save profile index */
+ tfa98xx_controls[mix_index].private_value = bprofile->item_id;
+ mix_index++;
+ }
+ }
+
+ /* look for the basename profile in the list of mixer profiles and
+ * add the container profile index to the supported samplerates
+ * of this mixer profile */
+ add_sr_to_profile(tfa98xx, bprofile->basename, bprofile->len, prof);
+ }
+
+ /* set the number of user selectable profiles in the mixer */
+ tfa98xx_mixer_profiles = id;
+
+ /* Create a mixer item for stop control on TFA1 */
+ name = devm_kzalloc(tfa98xx->codec->dev, MAX_CONTROL_NAME, GFP_KERNEL);
+ if (!name)
+ return -ENOMEM;
+
+ scnprintf(name, MAX_CONTROL_NAME, "%s Stop", tfa98xx->fw.name);
+ tfa98xx_controls[mix_index].name = name;
+ tfa98xx_controls[mix_index].iface = SNDRV_CTL_ELEM_IFACE_MIXER;
+ tfa98xx_controls[mix_index].info = tfa98xx_info_stop_ctl;
+ tfa98xx_controls[mix_index].get = tfa98xx_get_stop_ctl;
+ tfa98xx_controls[mix_index].put = tfa98xx_set_stop_ctl;
+ mix_index++;
+
+ if (tfa98xx->flags & TFA98XX_FLAG_CALIBRATION_CTL) {
+ name = devm_kzalloc(tfa98xx->codec->dev, MAX_CONTROL_NAME, GFP_KERNEL);
+ if (!name)
+ return -ENOMEM;
+
+ scnprintf(name, MAX_CONTROL_NAME, "%s Calibration", tfa98xx->fw.name);
+ tfa98xx_controls[mix_index].name = name;
+ tfa98xx_controls[mix_index].iface = SNDRV_CTL_ELEM_IFACE_MIXER;
+ tfa98xx_controls[mix_index].info = tfa98xx_info_cal_ctl;
+ tfa98xx_controls[mix_index].get = tfa98xx_get_cal_ctl;
+ tfa98xx_controls[mix_index].put = tfa98xx_set_cal_ctl;
+ mix_index++;
+ }
+
+ return snd_soc_add_codec_controls(tfa98xx->codec,
+ tfa98xx_controls, mix_index);
+}
+
+static void *tfa98xx_devm_kstrdup(struct device *dev, char *buf)
+{
+ char *str = devm_kzalloc(dev, strlen(buf) + 1, GFP_KERNEL);
+ if (!str)
+ return str;
+ memcpy(str, buf, strlen(buf));
+ return str;
+}
+
+static int tfa98xx_append_i2c_address(struct device *dev,
+ struct i2c_client *i2c,
+ struct snd_soc_dapm_widget *widgets,
+ int num_widgets,
+ struct snd_soc_dai_driver *dai_drv,
+ int num_dai)
+{
+ char buf[50];
+ int i;
+ int i2cbus = i2c->adapter->nr;
+ int addr = i2c->addr;
+ if (dai_drv && num_dai > 0)
+ for (i = 0; i < num_dai; i++) {
+ snprintf(buf, 50, "%s-%x-%x", dai_drv[i].name, i2cbus,
+ addr);
+ dai_drv[i].name = tfa98xx_devm_kstrdup(dev, buf);
+
+ snprintf(buf, 50, "%s-%x-%x",
+ dai_drv[i].playback.stream_name,
+ i2cbus, addr);
+ dai_drv[i].playback.stream_name = tfa98xx_devm_kstrdup(dev, buf);
+
+ snprintf(buf, 50, "%s-%x-%x",
+ dai_drv[i].capture.stream_name,
+ i2cbus, addr);
+ dai_drv[i].capture.stream_name = tfa98xx_devm_kstrdup(dev, buf);
+ }
+
+ /* the idea behind this is convert:
+ * SND_SOC_DAPM_AIF_IN("AIF IN", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
+ * into:
+ * SND_SOC_DAPM_AIF_IN("AIF IN", "AIF Playback-2-36",
+ * 0, SND_SOC_NOPM, 0, 0),
+ */
+ if (widgets && num_widgets > 0)
+ for (i = 0; i < num_widgets; i++) {
+ if (!widgets[i].sname)
+ continue;
+ if ((widgets[i].id == snd_soc_dapm_aif_in)
+ || (widgets[i].id == snd_soc_dapm_aif_out)) {
+ snprintf(buf, 50, "%s-%x-%x", widgets[i].sname,
+ i2cbus, addr);
+ widgets[i].sname = tfa98xx_devm_kstrdup(dev, buf);
+ }
+ }
+
+ return 0;
+}
+
+static struct snd_soc_dapm_widget tfa98xx_dapm_widgets_common[] = {
+ /* Stream widgets */
+ SND_SOC_DAPM_AIF_IN("AIF IN", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF OUT", "AIF Capture", 0, SND_SOC_NOPM, 0, 0),
+
+ SND_SOC_DAPM_OUTPUT("OUTL"),
+ SND_SOC_DAPM_INPUT("AEC Loopback"),
+};
+
+static struct snd_soc_dapm_widget tfa98xx_dapm_widgets_stereo[] = {
+ SND_SOC_DAPM_OUTPUT("OUTR"),
+};
+
+static struct snd_soc_dapm_widget tfa98xx_dapm_widgets_saam[] = {
+ SND_SOC_DAPM_INPUT("SAAM MIC"),
+};
+
+static struct snd_soc_dapm_widget tfa9888_dapm_inputs[] = {
+ SND_SOC_DAPM_INPUT("DMIC1"),
+ SND_SOC_DAPM_INPUT("DMIC2"),
+ SND_SOC_DAPM_INPUT("DMIC3"),
+ SND_SOC_DAPM_INPUT("DMIC4"),
+};
+
+static const struct snd_soc_dapm_route tfa98xx_dapm_routes_common[] = {
+ { "OUTL", NULL, "AIF IN" },
+ { "AIF OUT", NULL, "AEC Loopback" },
+};
+
+static const struct snd_soc_dapm_route tfa98xx_dapm_routes_saam[] = {
+ { "AIF OUT", NULL, "SAAM MIC" },
+};
+
+static const struct snd_soc_dapm_route tfa98xx_dapm_routes_stereo[] = {
+ { "OUTR", NULL, "AIF IN" },
+};
+
+static const struct snd_soc_dapm_route tfa9888_input_dapm_routes[] = {
+ { "AIF OUT", NULL, "DMIC1" },
+ { "AIF OUT", NULL, "DMIC2" },
+ { "AIF OUT", NULL, "DMIC3" },
+ { "AIF OUT", NULL, "DMIC4" },
+};
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0)
+static struct snd_soc_dapm_context *snd_soc_codec_get_dapm(
+ struct snd_soc_codec *codec)
+{
+ return &codec->dapm;
+}
+#endif
+
+static void tfa98xx_add_widgets(struct tfa98xx *tfa98xx)
+{
+ struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(tfa98xx->codec);
+ struct snd_soc_dapm_widget *widgets;
+ unsigned int num_dapm_widgets = ARRAY_SIZE(tfa98xx_dapm_widgets_common);
+
+ widgets = devm_kzalloc(&tfa98xx->i2c->dev,
+ sizeof(struct snd_soc_dapm_widget) *
+ ARRAY_SIZE(tfa98xx_dapm_widgets_common),
+ GFP_KERNEL);
+ if (!widgets)
+ return;
+ memcpy(widgets, tfa98xx_dapm_widgets_common,
+ sizeof(struct snd_soc_dapm_widget) *
+ ARRAY_SIZE(tfa98xx_dapm_widgets_common));
+
+ tfa98xx_append_i2c_address(&tfa98xx->i2c->dev,
+ tfa98xx->i2c,
+ widgets,
+ num_dapm_widgets,
+ NULL,
+ 0);
+
+ snd_soc_dapm_new_controls(dapm, widgets,
+ ARRAY_SIZE(tfa98xx_dapm_widgets_common));
+ snd_soc_dapm_add_routes(dapm, tfa98xx_dapm_routes_common,
+ ARRAY_SIZE(tfa98xx_dapm_routes_common));
+
+ if (tfa98xx->flags & TFA98XX_FLAG_STEREO_DEVICE) {
+ snd_soc_dapm_new_controls(dapm, tfa98xx_dapm_widgets_stereo,
+ ARRAY_SIZE(tfa98xx_dapm_widgets_stereo));
+ snd_soc_dapm_add_routes(dapm, tfa98xx_dapm_routes_stereo,
+ ARRAY_SIZE(tfa98xx_dapm_routes_stereo));
+ }
+
+ if (tfa98xx->flags & TFA98XX_FLAG_MULTI_MIC_INPUTS) {
+ snd_soc_dapm_new_controls(dapm, tfa9888_dapm_inputs,
+ ARRAY_SIZE(tfa9888_dapm_inputs));
+ snd_soc_dapm_add_routes(dapm, tfa9888_input_dapm_routes,
+ ARRAY_SIZE(tfa9888_input_dapm_routes));
+ }
+
+ if (tfa98xx->flags & TFA98XX_FLAG_SAAM_AVAILABLE) {
+ snd_soc_dapm_new_controls(dapm, tfa98xx_dapm_widgets_saam,
+ ARRAY_SIZE(tfa98xx_dapm_widgets_saam));
+ snd_soc_dapm_add_routes(dapm, tfa98xx_dapm_routes_saam,
+ ARRAY_SIZE(tfa98xx_dapm_routes_saam));
+ }
+}
+
+/* I2C wrapper functions */
+enum Tfa98xx_Error tfa98xx_write_register16(struct tfa_device *tfa,
+ unsigned char subaddress,
+ unsigned short value)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ struct tfa98xx *tfa98xx;
+ int ret;
+ int retries = I2C_RETRIES;
+
+ if (tfa == NULL) {
+ pr_err("No device available\n");
+ return Tfa98xx_Error_Fail;
+ }
+
+ tfa98xx = (struct tfa98xx *)tfa->data;
+ if (!tfa98xx || !tfa98xx->regmap) {
+ pr_err("No tfa98xx regmap available\n");
+ return Tfa98xx_Error_Bad_Parameter;
+ }
+retry:
+ ret = regmap_write(tfa98xx->regmap, subaddress, value);
+ if (ret < 0) {
+ pr_warn("i2c error, retries left: %d\n", retries);
+ if (retries) {
+ retries--;
+ msleep(I2C_RETRY_DELAY);
+ goto retry;
+ }
+ return Tfa98xx_Error_Fail;
+ }
+ if (tfa98xx_kmsg_regs)
+ dev_dbg(&tfa98xx->i2c->dev, " WR reg=0x%02x, val=0x%04x %s\n",
+ subaddress, value,
+ ret < 0 ? "Error!!" : "");
+
+ if (tfa98xx_ftrace_regs)
+ tfa98xx_trace_printk("\tWR reg=0x%02x, val=0x%04x %s\n",
+ subaddress, value,
+ ret < 0 ? "Error!!" : "");
+ return error;
+}
+
+enum Tfa98xx_Error tfa98xx_read_register16(struct tfa_device *tfa,
+ unsigned char subaddress,
+ unsigned short *val)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ struct tfa98xx *tfa98xx;
+ unsigned int value;
+ int retries = I2C_RETRIES;
+ int ret;
+
+ if (tfa == NULL) {
+ pr_err("No device available\n");
+ return Tfa98xx_Error_Fail;
+ }
+
+ tfa98xx = (struct tfa98xx *)tfa->data;
+ if (!tfa98xx || !tfa98xx->regmap) {
+ pr_err("No tfa98xx regmap available\n");
+ return Tfa98xx_Error_Bad_Parameter;
+ }
+retry:
+ ret = regmap_read(tfa98xx->regmap, subaddress, &value);
+ if (ret < 0) {
+ pr_warn("i2c error at subaddress 0x%x, retries left: %d\n",
+ subaddress, retries);
+ if (retries) {
+ retries--;
+ msleep(I2C_RETRY_DELAY);
+ goto retry;
+ }
+ return Tfa98xx_Error_Fail;
+ }
+ *val = value & 0xffff;
+
+ if (tfa98xx_kmsg_regs)
+ dev_dbg(&tfa98xx->i2c->dev, "RD reg=0x%02x, val=0x%04x %s\n",
+ subaddress, *val,
+ ret < 0 ? "Error!!" : "");
+ if (tfa98xx_ftrace_regs)
+ tfa98xx_trace_printk("\tRD reg=0x%02x, val=0x%04x %s\n",
+ subaddress, *val,
+ ret < 0 ? "Error!!" : "");
+
+ return error;
+}
+
+
+/*
+ * init external dsp
+ */
+enum Tfa98xx_Error
+ tfa98xx_init_dsp(struct tfa_device *tfa)
+{
+ return Tfa98xx_Error_Not_Supported;
+}
+
+int tfa98xx_get_dsp_status(struct tfa_device *tfa)
+{
+ return 0;
+}
+
+/*
+ * write external dsp message
+ */
+enum Tfa98xx_Error
+ tfa98xx_write_dsp(struct tfa_device *tfa, int num_bytes,
+ const char *command_buffer)
+{
+ return Tfa98xx_Error_Not_Supported;
+}
+
+/*
+ * read external dsp message
+ */
+enum Tfa98xx_Error
+ tfa98xx_read_dsp(struct tfa_device *tfa, int num_bytes,
+ unsigned char *result_buffer)
+{
+ return Tfa98xx_Error_Not_Supported;
+}
+/*
+ * write/read external dsp message
+ */
+enum Tfa98xx_Error
+ tfa98xx_writeread_dsp(struct tfa_device *tfa, int command_length,
+ void *command_buffer, int result_length, void *result_buffer)
+{
+ return Tfa98xx_Error_Not_Supported;
+}
+
+enum Tfa98xx_Error tfa98xx_read_data(struct tfa_device *tfa,
+ unsigned char reg,
+ int len, unsigned char value[])
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ struct tfa98xx *tfa98xx;
+ struct i2c_client *tfa98xx_client;
+ int err;
+ int tries = 0;
+ unsigned char *reg_buf = NULL;
+ struct i2c_msg msgs[] = {
+ {
+ .flags = 0,
+ .len = 1,
+ .buf = NULL,
+ }, {
+ .flags = I2C_M_RD,
+ .len = len,
+ .buf = value,
+ },
+ };
+ //GRP_KERNEL also works,
+ reg_buf = (unsigned char *)kmalloc(sizeof(reg), GFP_DMA);
+ if (!reg_buf) {
+ return -ENOMEM;;
+ }
+
+ *reg_buf = reg;
+ msgs[0].buf = reg_buf;
+
+ if (tfa == NULL) {
+ pr_err("No device available\n");
+ return Tfa98xx_Error_Fail;
+ }
+
+ tfa98xx = (struct tfa98xx *)tfa->data;
+ if (tfa98xx->i2c) {
+ tfa98xx_client = tfa98xx->i2c;
+ msgs[0].addr = tfa98xx_client->addr;
+ msgs[1].addr = tfa98xx_client->addr;
+
+ do {
+ err = i2c_transfer(tfa98xx_client->adapter, msgs,
+ ARRAY_SIZE(msgs));
+ if (err != ARRAY_SIZE(msgs))
+ msleep_interruptible(I2C_RETRY_DELAY);
+ } while ((err != ARRAY_SIZE(msgs)) && (++tries < I2C_RETRIES));
+
+ if (err != ARRAY_SIZE(msgs)) {
+ dev_err(&tfa98xx_client->dev, "read transfer error %d\n",
+ err);
+ error = Tfa98xx_Error_Fail;
+ }
+
+ if (tfa98xx_kmsg_regs)
+ dev_dbg(&tfa98xx_client->dev, "RD-DAT reg=0x%02x, len=%d\n",
+ reg, len);
+ if (tfa98xx_ftrace_regs)
+ tfa98xx_trace_printk("\t\tRD-DAT reg=0x%02x, len=%d\n",
+ reg, len);
+ } else {
+ pr_err("No device available\n");
+ error = Tfa98xx_Error_Fail;
+ }
+ kfree(reg_buf);
+ return error;
+}
+
+enum Tfa98xx_Error tfa98xx_write_raw(struct tfa_device *tfa,
+ int len,
+ const unsigned char data[])
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ struct tfa98xx *tfa98xx;
+ int ret;
+ int retries = I2C_RETRIES;
+
+
+ if (tfa == NULL) {
+ pr_err("No device available\n");
+ return Tfa98xx_Error_Fail;
+ }
+
+ tfa98xx = (struct tfa98xx *)tfa->data;
+
+retry:
+ ret = i2c_master_send(tfa98xx->i2c, data, len);
+ if (ret < 0) {
+ pr_warn("i2c error, retries left: %d\n", retries);
+ if (retries) {
+ retries--;
+ msleep(I2C_RETRY_DELAY);
+ goto retry;
+ }
+ }
+
+ if (ret == len) {
+ if (tfa98xx_kmsg_regs)
+ dev_dbg(&tfa98xx->i2c->dev, " WR-RAW len=%d\n", len);
+ if (tfa98xx_ftrace_regs)
+ tfa98xx_trace_printk("\t\tWR-RAW len=%d\n", len);
+ return Tfa98xx_Error_Ok;
+ }
+ pr_err(" WR-RAW (len=%d) Error I2C send size mismatch %d\n", len, ret);
+ error = Tfa98xx_Error_Fail;
+
+ return error;
+}
+
+/* Interrupts management */
+
+static void tfa98xx_interrupt_enable_tfa2(struct tfa98xx *tfa98xx, bool enable)
+{
+ /* Only for 0x72 we need to enable NOCLK interrupts */
+ if (tfa98xx->flags & TFA98XX_FLAG_REMOVE_PLOP_NOISE)
+ tfa_irq_ena(tfa98xx->tfa, tfa9912_irq_stnoclk, enable);
+
+ if (tfa98xx->flags & TFA98XX_FLAG_LP_MODES) {
+ /* FIXME: IELP0 does not excist for 9912 */
+ tfa_irq_ena(tfa98xx->tfa, 36, enable);
+ tfa_irq_ena(tfa98xx->tfa, tfa9912_irq_stclpr, enable);
+ }
+}
+
+/* Check if tap-detection can and shall be enabled.
+ * Configure SPK interrupt accordingly or setup polling mode
+ * Tap-detection shall be active if:
+ * - the service is enabled (tapdet_open), AND
+ * - the current profile is a tap-detection profile
+ * On TFA1 familiy of devices, activating tap-detection means enabling the SPK
+ * interrupt if available.
+ * We also update the tapdet_enabled and tapdet_poll variables.
+ */
+static void tfa98xx_tapdet_check_update(struct tfa98xx *tfa98xx)
+{
+ unsigned int enable = false;
+
+ /* Support tap-detection on TFA1 family of devices */
+ if ((tfa98xx->flags & TFA98XX_FLAG_TAPDET_AVAILABLE) == 0)
+ return;
+
+ if (tfa98xx->tapdet_open &&
+ (tfa98xx->tapdet_profiles & (1 << tfa98xx->profile)))
+ enable = true;
+
+ if (!gpio_is_valid(tfa98xx->irq_gpio)) {
+ /* interrupt not available, setup polling mode */
+ tfa98xx->tapdet_poll = true;
+ if (enable)
+ queue_delayed_work(tfa98xx->tfa98xx_wq,
+ &tfa98xx->tapdet_work, HZ / 10);
+ else
+ cancel_delayed_work_sync(&tfa98xx->tapdet_work);
+ dev_dbg(tfa98xx->codec->dev,
+ "Polling for tap-detection: %s (%d; 0x%x, %d)\n",
+ enable ? "enabled" : "disabled",
+ tfa98xx->tapdet_open, tfa98xx->tapdet_profiles,
+ tfa98xx->profile);
+
+ } else {
+ dev_dbg(tfa98xx->codec->dev,
+ "Interrupt for tap-detection: %s (%d; 0x%x, %d)\n",
+ enable ? "enabled" : "disabled",
+ tfa98xx->tapdet_open, tfa98xx->tapdet_profiles,
+ tfa98xx->profile);
+ /* enabled interrupt */
+ tfa_irq_ena(tfa98xx->tfa, tfa9912_irq_sttapdet, enable);
+ }
+
+ /* check disabled => enabled transition to clear pending events */
+ if (!tfa98xx->tapdet_enabled && enable) {
+ /* clear pending event if any */
+ tfa_irq_clear(tfa98xx->tfa, tfa9912_irq_sttapdet);
+ }
+
+ if (!tfa98xx->tapdet_poll)
+ tfa_irq_ena(tfa98xx->tfa, tfa9912_irq_sttapdet, 1); /* enable again */
+}
+
+/* global enable / disable interrupts */
+static void tfa98xx_interrupt_enable(struct tfa98xx *tfa98xx, bool enable)
+{
+ if (tfa98xx->flags & TFA98XX_FLAG_SKIP_INTERRUPTS)
+ return;
+
+ if (tfa98xx->tfa->tfa_family == 2)
+ tfa98xx_interrupt_enable_tfa2(tfa98xx, enable);
+}
+
+/* Firmware management */
+static void tfa98xx_container_loaded(const struct firmware *cont,
+ void *context)
+{
+ nxpTfaContainer_t *container;
+ struct tfa98xx *tfa98xx = context;
+ enum tfa_error tfa_err;
+ int container_size;
+ int ret;
+
+ tfa98xx->dsp_fw_state = TFA98XX_DSP_FW_FAIL;
+
+ if (!cont) {
+ pr_err("Failed to read %s\n", fw_name);
+ return;
+ }
+
+ pr_debug("loaded %s - size: %zu\n", fw_name, cont->size);
+
+ mutex_lock(&tfa98xx_mutex);
+ if (tfa98xx_container == NULL) {
+ container = kzalloc(cont->size, GFP_KERNEL);
+ if (container == NULL) {
+ mutex_unlock(&tfa98xx_mutex);
+ release_firmware(cont);
+ pr_err("Error allocating memory\n");
+ return;
+ }
+
+ container_size = cont->size;
+ memcpy(container, cont->data, container_size);
+ release_firmware(cont);
+
+ pr_debug("%.2s%.2s\n", container->version, container->subversion);
+ pr_debug("%.8s\n", container->customer);
+ pr_debug("%.8s\n", container->application);
+ pr_debug("%.8s\n", container->type);
+ pr_debug("%d ndev\n", container->ndev);
+ pr_debug("%d nprof\n", container->nprof);
+
+ tfa_err = tfa_load_cnt(container, container_size);
+ if (tfa_err != tfa_error_ok) {
+ mutex_unlock(&tfa98xx_mutex);
+ kfree(container);
+ dev_err(tfa98xx->dev, "Cannot load container file, aborting\n");
+ return;
+ }
+
+ tfa98xx_container = container;
+ } else {
+ pr_debug("container file already loaded...\n");
+ container = tfa98xx_container;
+ release_firmware(cont);
+ }
+ mutex_unlock(&tfa98xx_mutex);
+
+ tfa98xx->tfa->cnt = container;
+
+ /*
+ i2c transaction limited to 64k
+ (Documentation/i2c/writing-clients)
+ */
+ tfa98xx->tfa->buffer_size = 65536;
+
+ /* DSP messages via i2c */
+ tfa98xx->tfa->has_msg = 0;
+
+ if (tfa_dev_probe(tfa98xx->i2c->addr, tfa98xx->tfa) != 0) {
+ dev_err(tfa98xx->dev, "Failed to probe TFA98xx @ 0x%.2x\n",
+ tfa98xx->i2c->addr);
+ return;
+ }
+
+ tfa98xx->tfa->dev_idx = tfa_cont_get_idx(tfa98xx->tfa);
+ if (tfa98xx->tfa->dev_idx < 0) {
+ dev_err(tfa98xx->dev, "Failed to find TFA98xx @ 0x%.2x in \
+ container file\n", tfa98xx->i2c->addr);
+ return;
+ }
+
+ /* Enable debug traces */
+ tfa98xx->tfa->verbose = trace_level & 1;
+
+ /* prefix is the application name from the cnt */
+ tfa_cnt_get_app_name(tfa98xx->tfa, tfa98xx->fw.name);
+
+ /* set default profile/vstep */
+ tfa98xx->profile = 0;
+ tfa98xx->vstep = 0;
+
+ /* Override default profile if requested */
+ if (strcmp(dflt_prof_name, "")) {
+ unsigned int i;
+ int nprof = tfa_cnt_get_dev_nprof(tfa98xx->tfa);
+ for (i = 0; i < nprof; i++) {
+ if (strcmp(tfa_cont_profile_name(tfa98xx, i),
+ dflt_prof_name) == 0) {
+ tfa98xx->profile = i;
+ dev_info(tfa98xx->dev,
+ "changing default profile to %s (%d)\n",
+ dflt_prof_name, tfa98xx->profile);
+ break;
+ }
+ }
+ if (i >= nprof)
+ dev_info(tfa98xx->dev,
+ "Default profile override failed (%s profile not found)\n",
+ dflt_prof_name);
+ }
+
+ tfa98xx->dsp_fw_state = TFA98XX_DSP_FW_OK;
+ pr_debug("Firmware init complete\n");
+
+ if (no_start != 0)
+ return;
+
+ /* Only controls for master device */
+ if (tfa98xx->tfa->dev_idx == 0)
+ tfa98xx_create_controls(tfa98xx);
+
+ tfa98xx_inputdev_check_register(tfa98xx);
+
+ if (tfa_is_cold(tfa98xx->tfa) == 0) {
+ pr_debug("Warning: device 0x%.2x is still warm\n", tfa98xx->i2c->addr);
+ tfa_reset(tfa98xx->tfa);
+ }
+
+ /* Preload settings using internal clock on TFA2 */
+ if (tfa98xx->tfa->tfa_family == 2) {
+ mutex_lock(&tfa98xx->dsp_lock);
+ ret = tfa98xx_tfa_start(tfa98xx, tfa98xx->profile, tfa98xx->vstep);
+ if (ret == Tfa98xx_Error_Not_Supported)
+ tfa98xx->dsp_fw_state = TFA98XX_DSP_FW_FAIL;
+ mutex_unlock(&tfa98xx->dsp_lock);
+ }
+
+ tfa98xx_interrupt_enable(tfa98xx, true);
+}
+
+static int tfa98xx_load_container(struct tfa98xx *tfa98xx)
+{
+ tfa98xx->dsp_fw_state = TFA98XX_DSP_FW_PENDING;
+
+ return request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
+ fw_name, tfa98xx->dev, GFP_KERNEL,
+ tfa98xx, tfa98xx_container_loaded);
+}
+
+
+static void tfa98xx_tapdet(struct tfa98xx *tfa98xx)
+{
+ unsigned int tap_pattern;
+ int btn;
+
+ /* check tap pattern (BTN_0 is "error" wrong tap indication */
+ tap_pattern = tfa_get_tap_pattern(tfa98xx->tfa);
+ switch (tap_pattern) {
+ case 0xffffffff:
+ pr_info("More than 4 taps detected! (flagTapPattern = -1)\n");
+ btn = BTN_0;
+ break;
+ case 0xfffffffe:
+ case 0xfe:
+ pr_info("Illegal tap detected!\n");
+ btn = BTN_0;
+ break;
+ case 0:
+ pr_info("Unrecognized pattern! (flagTapPattern = 0)\n");
+ btn = BTN_0;
+ break;
+ default:
+ pr_info("Detected pattern: %d\n", tap_pattern);
+ btn = BTN_0 + tap_pattern;
+ break;
+ }
+
+ input_report_key(tfa98xx->input, btn, 1);
+ input_report_key(tfa98xx->input, btn, 0);
+ input_sync(tfa98xx->input);
+
+ /* acknowledge event done by clearing interrupt */
+
+}
+
+static void tfa98xx_tapdet_work(struct work_struct *work)
+{
+ struct tfa98xx *tfa98xx;
+
+ //TODO check is this is still needed for tap polling
+ tfa98xx = container_of(work, struct tfa98xx, tapdet_work.work);
+
+ if (tfa_irq_get(tfa98xx->tfa, tfa9912_irq_sttapdet))
+ tfa98xx_tapdet(tfa98xx);
+
+ queue_delayed_work(tfa98xx->tfa98xx_wq, &tfa98xx->tapdet_work, HZ / 10);
+}
+
+static void tfa98xx_monitor(struct work_struct *work)
+{
+ struct tfa98xx *tfa98xx;
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+
+ tfa98xx = container_of(work, struct tfa98xx, monitor_work.work);
+
+ /* Check for tap-detection - bypass monitor if it is active */
+ if (!tfa98xx->input) {
+ mutex_lock(&tfa98xx->dsp_lock);
+ error = tfa_status(tfa98xx->tfa);
+ mutex_unlock(&tfa98xx->dsp_lock);
+ if (error == Tfa98xx_Error_DSP_not_running) {
+ if (tfa98xx->dsp_init == TFA98XX_DSP_INIT_DONE) {
+ tfa98xx->dsp_init = TFA98XX_DSP_INIT_RECOVER;
+ queue_delayed_work(tfa98xx->tfa98xx_wq,
+ &tfa98xx->init_work, 0);
+ }
+ }
+ }
+
+ /* reschedule */
+ queue_delayed_work(tfa98xx->tfa98xx_wq, &tfa98xx->monitor_work, 5 * HZ);
+}
+
+static void tfa98xx_dsp_init(struct tfa98xx *tfa98xx)
+{
+ int ret;
+ bool failed = false;
+ bool reschedule = false;
+ bool sync = false;
+
+ if (tfa98xx->dsp_fw_state != TFA98XX_DSP_FW_OK) {
+ pr_debug("Skipping tfa_dev_start (no FW: %d)\n", tfa98xx->dsp_fw_state);
+ return;
+ }
+
+ if (tfa98xx->dsp_init == TFA98XX_DSP_INIT_DONE) {
+ pr_debug("Stream already started, skipping DSP power-on\n");
+ return;
+ }
+ mutex_lock(&tfa98xx->dsp_lock);
+
+ tfa98xx->dsp_init = TFA98XX_DSP_INIT_PENDING;
+
+ if (tfa98xx->init_count < TF98XX_MAX_DSP_START_TRY_COUNT) {
+ /* directly try to start DSP */
+ ret = tfa98xx_tfa_start(tfa98xx, tfa98xx->profile, tfa98xx->vstep);
+ if (ret == Tfa98xx_Error_Not_Supported) {
+ tfa98xx->dsp_fw_state = TFA98XX_DSP_FW_FAIL;
+ dev_err(&tfa98xx->i2c->dev, "Failed starting device\n");
+ failed = true;
+ } else if (ret != Tfa98xx_Error_Ok) {
+ /* It may fail as we may not have a valid clock at that
+ * time, so re-schedule and re-try later.
+ */
+ dev_err(&tfa98xx->i2c->dev,
+ "tfa_dev_start failed! (err %d) - %d\n",
+ ret, tfa98xx->init_count);
+ reschedule = true;
+ } else {
+ sync = true;
+
+ /* Subsystem ready, tfa init complete */
+ tfa98xx->dsp_init = TFA98XX_DSP_INIT_DONE;
+ dev_dbg(&tfa98xx->i2c->dev,
+ "tfa_dev_start success (%d)\n",
+ tfa98xx->init_count);
+ /* cancel other pending init works */
+ cancel_delayed_work(&tfa98xx->init_work);
+ tfa98xx->init_count = 0;
+ }
+ } else {
+ /* exceeded max number ot start tentatives, cancel start */
+ dev_err(&tfa98xx->i2c->dev,
+ "Failed starting device (%d)\n",
+ tfa98xx->init_count);
+ failed = true;
+ }
+
+ if (reschedule) {
+ /* reschedule this init work for later */
+ queue_delayed_work(tfa98xx->tfa98xx_wq,
+ &tfa98xx->init_work,
+ msecs_to_jiffies(5));
+ tfa98xx->init_count++;
+ }
+ if (failed) {
+ tfa98xx->dsp_init = TFA98XX_DSP_INIT_FAIL;
+ /* cancel other pending init works */
+ cancel_delayed_work(&tfa98xx->init_work);
+ tfa98xx->init_count = 0;
+ }
+ mutex_unlock(&tfa98xx->dsp_lock);
+
+ if (sync) {
+ /* check if all devices have started */
+ bool do_sync;
+ mutex_lock(&tfa98xx_mutex);
+
+ if (tfa98xx_sync_count < tfa98xx_device_count)
+ tfa98xx_sync_count++;
+
+ do_sync = (tfa98xx_sync_count >= tfa98xx_device_count);
+ mutex_unlock(&tfa98xx_mutex);
+
+ /* when all devices have started then unmute */
+ if (do_sync) {
+ tfa98xx_sync_count = 0;
+ list_for_each_entry(tfa98xx, &tfa98xx_device_list, list) {
+ mutex_lock(&tfa98xx->dsp_lock);
+ tfa_dev_set_state(tfa98xx->tfa, TFA_STATE_UNMUTE, 0);
+
+ /*
+ * start monitor thread to check IC status bit
+ * periodically, and re-init IC to recover if
+ * needed.
+ */
+ if (tfa98xx->tfa->tfa_family == 1)
+ queue_delayed_work(tfa98xx->tfa98xx_wq,
+ &tfa98xx->monitor_work,
+ 1 * HZ);
+ mutex_unlock(&tfa98xx->dsp_lock);
+ }
+
+ }
+ }
+}
+
+
+static void tfa98xx_dsp_init_work(struct work_struct *work)
+{
+ struct tfa98xx *tfa98xx = container_of(work, struct tfa98xx,
+ init_work.work);
+
+ tfa98xx_dsp_init(tfa98xx);
+}
+
+static void tfa98xx_interrupt(struct work_struct *work)
+{
+ struct tfa98xx *tfa98xx = container_of(work, struct tfa98xx,
+ interrupt_work.work);
+
+ pr_info("\n");
+
+ if (tfa98xx->flags & TFA98XX_FLAG_TAPDET_AVAILABLE) {
+ /* check for tap interrupt */
+ if (tfa_irq_get(tfa98xx->tfa, tfa9912_irq_sttapdet)) {
+ tfa98xx_tapdet(tfa98xx);
+
+ /* clear interrupt */
+ tfa_irq_clear(tfa98xx->tfa, tfa9912_irq_sttapdet);
+ }
+ } /* TFA98XX_FLAG_TAPDET_AVAILABLE */
+
+ if (tfa98xx->flags & TFA98XX_FLAG_REMOVE_PLOP_NOISE) {
+ int start_triggered;
+
+ mutex_lock(&tfa98xx->dsp_lock);
+ start_triggered = tfa_plop_noise_interrupt(tfa98xx->tfa,
+ tfa98xx->profile, tfa98xx->vstep);
+ /* Only enable when the return value is 1,
+ * otherwise the interrupt is triggered twice
+ */
+ if (start_triggered)
+ tfa98xx_interrupt_enable(tfa98xx, true);
+ mutex_unlock(&tfa98xx->dsp_lock);
+ } /* TFA98XX_FLAG_REMOVE_PLOP_NOISE */
+
+ if (tfa98xx->flags & TFA98XX_FLAG_LP_MODES)
+ tfa_lp_mode_interrupt(tfa98xx->tfa);
+ /* TFA98XX_FLAG_LP_MODES */
+
+ /* unmask interrupts masked in IRQ handler */
+ tfa_irq_unmask(tfa98xx->tfa);
+}
+
+static int tfa98xx_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec);
+ unsigned int sr;
+ int len, prof, nprof, idx = 0;
+ char *basename;
+ u64 formats;
+ int err;
+
+ /*
+ * Support CODEC to CODEC links,
+ * these are called with a NULL runtime pointer.
+ */
+ if (!substream->runtime)
+ return 0;
+
+ if (pcm_no_constraint != 0)
+ return 0;
+
+ switch (pcm_sample_format) {
+ case 1:
+ formats = SNDRV_PCM_FMTBIT_S24_LE;
+ break;
+ case 2:
+ formats = SNDRV_PCM_FMTBIT_S32_LE;
+ break;
+ default:
+ formats = SNDRV_PCM_FMTBIT_S16_LE;
+ break;
+ }
+
+ err = snd_pcm_hw_constraint_mask64(substream->runtime,
+ SNDRV_PCM_HW_PARAM_FORMAT, formats);
+ if (err < 0)
+ return err;
+
+ if (no_start != 0)
+ return 0;
+
+ if (tfa98xx->dsp_fw_state != TFA98XX_DSP_FW_OK) {
+ dev_info(codec->dev, "Container file not loaded\n");
+ return -EINVAL;
+ }
+
+ basename = kzalloc(MAX_CONTROL_NAME, GFP_KERNEL);
+ if (!basename)
+ return -ENOMEM;
+
+ /* copy profile name into basename until the . */
+ get_profile_basename(basename,
+ tfa_cont_profile_name(tfa98xx, tfa98xx->profile));
+ len = strlen(basename);
+
+ /* loop over all profiles and get the supported samples rate(s) from
+ * the profiles with the same basename
+ */
+ nprof = tfa_cnt_get_dev_nprof(tfa98xx->tfa);
+ tfa98xx->rate_constraint.list = &tfa98xx->rate_constraint_list[0];
+ tfa98xx->rate_constraint.count = 0;
+ for (prof = 0; prof < nprof; prof++) {
+ if (0 == strncmp(basename, tfa_cont_profile_name(tfa98xx, prof),
+ len)) {
+ /* Check which sample rate is supported with current profile,
+ * and enforce this.
+ */
+ sr = tfa98xx_get_profile_sr(tfa98xx->tfa, prof);
+ if (!sr)
+ dev_info(codec->dev, "Unable to identify \
+ supported sample rate\n");
+
+ if (tfa98xx->rate_constraint.count >= TFA98XX_NUM_RATES) {
+ dev_err(codec->dev, "too many sample rates\n");
+ } else {
+ tfa98xx->rate_constraint_list[idx++] = sr;
+ tfa98xx->rate_constraint.count += 1;
+ }
+ }
+ }
+
+ kfree(basename);
+
+ return snd_pcm_hw_constraint_list(substream->runtime, 0,
+ SNDRV_PCM_HW_PARAM_RATE,
+ &tfa98xx->rate_constraint);
+}
+
+static int tfa98xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec_dai->codec);
+
+ tfa98xx->sysclk = freq;
+ return 0;
+}
+
+static int tfa98xx_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
+ unsigned int rx_mask, int slots, int slot_width)
+{
+ pr_debug("\n");
+ return 0;
+}
+
+static int tfa98xx_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+ struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(dai->codec);
+ struct snd_soc_codec *codec = dai->codec;
+
+ pr_debug("fmt=0x%x\n", fmt);
+
+ /* Supported mode: regular I2S, slave, or PDM */
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_I2S:
+ if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) {
+ dev_err(codec->dev, "Invalid Codec master mode\n");
+ return -EINVAL;
+ }
+ break;
+ case SND_SOC_DAIFMT_PDM:
+ break;
+ default:
+ dev_err(codec->dev, "Unsupported DAI format %d\n",
+ fmt & SND_SOC_DAIFMT_FORMAT_MASK);
+ return -EINVAL;
+ }
+
+ tfa98xx->audio_mode = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
+
+ return 0;
+}
+
+static int tfa98xx_get_fssel(unsigned int rate)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(rate_to_fssel); i++) {
+ if (rate_to_fssel[i].rate == rate)
+ return rate_to_fssel[i].fssel;
+ }
+ return -EINVAL;
+}
+
+static int tfa98xx_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec);
+ unsigned int rate;
+ int prof_idx;
+
+ /* Supported */
+ rate = params_rate(params);
+ pr_debug("Requested rate: %d, sample size: %d, physical size: %d\n",
+ rate, snd_pcm_format_width(params_format(params)),
+ snd_pcm_format_physical_width(params_format(params)));
+
+ if (no_start != 0)
+ return 0;
+
+ /* check if samplerate is supported for this mixer profile */
+ prof_idx = get_profile_id_for_sr(tfa98xx_mixer_profile, rate);
+ if (prof_idx < 0) {
+ pr_err("tfa98xx: invalid sample rate %d.\n", rate);
+ return -EINVAL;
+ }
+ pr_debug("mixer profile:container profile = [%d:%d]\n",
+ tfa98xx_mixer_profile, prof_idx);
+
+
+ /* update 'real' profile (container profile) */
+ tfa98xx->profile = prof_idx;
+
+ /* update to new rate */
+ tfa98xx->rate = rate;
+
+ return 0;
+}
+
+static int tfa98xx_mute(struct snd_soc_dai *dai, int mute, int stream)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec);
+
+ dev_dbg(&tfa98xx->i2c->dev, "%s: state: %d\n", __func__, mute);
+
+ if (no_start) {
+ pr_debug("no_start parameter set no tfa_dev_start or tfa_dev_stop, returning\n");
+ return 0;
+ }
+
+ if (mute) {
+ /* stop DSP only when both playback and capture streams
+ * are deactivated
+ */
+ if (stream == SNDRV_PCM_STREAM_PLAYBACK)
+ tfa98xx->pstream = 0;
+ else
+ tfa98xx->cstream = 0;
+ if (tfa98xx->pstream != 0 || tfa98xx->cstream != 0)
+ return 0;
+
+ mutex_lock(&tfa98xx_mutex);
+ tfa98xx_sync_count = 0;
+ mutex_unlock(&tfa98xx_mutex);
+
+ cancel_delayed_work_sync(&tfa98xx->monitor_work);
+
+ cancel_delayed_work_sync(&tfa98xx->init_work);
+ if (tfa98xx->dsp_fw_state != TFA98XX_DSP_FW_OK)
+ return 0;
+ mutex_lock(&tfa98xx->dsp_lock);
+ tfa_dev_stop(tfa98xx->tfa);
+ tfa98xx->dsp_init = TFA98XX_DSP_INIT_STOPPED;
+ mutex_unlock(&tfa98xx->dsp_lock);
+ } else {
+ if (stream == SNDRV_PCM_STREAM_PLAYBACK)
+ tfa98xx->pstream = 1;
+ else
+ tfa98xx->cstream = 1;
+
+ /* Start DSP */
+#if 1
+ if (tfa98xx->dsp_init != TFA98XX_DSP_INIT_PENDING)
+ queue_delayed_work(tfa98xx->tfa98xx_wq,
+ &tfa98xx->init_work, 0);
+#else
+ tfa98xx_dsp_init(tfa98xx);
+#endif//
+ }
+
+ return 0;
+}
+
+static const struct snd_soc_dai_ops tfa98xx_dai_ops = {
+ .startup = tfa98xx_startup,
+ .set_fmt = tfa98xx_set_fmt,
+ .set_sysclk = tfa98xx_set_dai_sysclk,
+ .set_tdm_slot = tfa98xx_set_tdm_slot,
+ .hw_params = tfa98xx_hw_params,
+ .mute_stream = tfa98xx_mute,
+};
+
+static struct snd_soc_dai_driver tfa98xx_dai[] = {
+ {
+ .name = "tfa98xx-aif",
+ .id = 1,
+ .playback = {
+ .stream_name = "AIF Playback",
+ .channels_min = 1,
+ .channels_max = 4,
+ .rates = TFA98XX_RATES,
+ .formats = TFA98XX_FORMATS,
+ },
+ .capture = {
+ .stream_name = "AIF Capture",
+ .channels_min = 1,
+ .channels_max = 4,
+ .rates = TFA98XX_RATES,
+ .formats = TFA98XX_FORMATS,
+ },
+ .ops = &tfa98xx_dai_ops,
+ .symmetric_rates = 1,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)
+ .symmetric_channels = 1,
+ .symmetric_samplebits = 1,
+#endif
+ },
+};
+
+static int tfa98xx_probe(struct snd_soc_codec *codec)
+{
+ struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec);
+ int ret;
+
+ pr_debug("\n");
+
+ /* setup work queue, will be used to initial DSP on first boot up */
+ tfa98xx->tfa98xx_wq = create_singlethread_workqueue("tfa98xx");
+ if (!tfa98xx->tfa98xx_wq)
+ return -ENOMEM;
+
+ INIT_DELAYED_WORK(&tfa98xx->init_work, tfa98xx_dsp_init_work);
+ INIT_DELAYED_WORK(&tfa98xx->monitor_work, tfa98xx_monitor);
+ INIT_DELAYED_WORK(&tfa98xx->interrupt_work, tfa98xx_interrupt);
+ INIT_DELAYED_WORK(&tfa98xx->tapdet_work, tfa98xx_tapdet_work);
+
+ tfa98xx->codec = codec;
+
+ ret = tfa98xx_load_container(tfa98xx);
+ pr_debug("Container loading requested: %d\n", ret);
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0)
+ codec->control_data = tfa98xx->regmap;
+ ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
+ if (ret != 0) {
+ dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+ return ret;
+ }
+#endif
+ tfa98xx_add_widgets(tfa98xx);
+
+ dev_info(codec->dev, "tfa98xx codec registered (%s)",
+ tfa98xx->fw.name);
+
+ return ret;
+}
+
+static int tfa98xx_remove(struct snd_soc_codec *codec)
+{
+ struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec);
+ pr_debug("\n");
+
+ tfa98xx_interrupt_enable(tfa98xx, false);
+
+ tfa98xx_inputdev_unregister(tfa98xx);
+
+ cancel_delayed_work_sync(&tfa98xx->interrupt_work);
+ cancel_delayed_work_sync(&tfa98xx->monitor_work);
+ cancel_delayed_work_sync(&tfa98xx->init_work);
+ cancel_delayed_work_sync(&tfa98xx->tapdet_work);
+
+ if (tfa98xx->tfa98xx_wq)
+ destroy_workqueue(tfa98xx->tfa98xx_wq);
+
+ return 0;
+}
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)
+static struct regmap *tfa98xx_get_regmap(struct device *dev)
+{
+ struct tfa98xx *tfa98xx = dev_get_drvdata(dev);
+
+ return tfa98xx->regmap;
+}
+#endif
+static struct snd_soc_codec_driver soc_codec_dev_tfa98xx = {
+ .probe = tfa98xx_probe,
+ .remove = tfa98xx_remove,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)
+ .get_regmap = tfa98xx_get_regmap,
+#endif
+};
+
+
+static bool tfa98xx_writeable_register(struct device *dev, unsigned int reg)
+{
+ /* enable read access for all registers */
+ return 1;
+}
+
+static bool tfa98xx_readable_register(struct device *dev, unsigned int reg)
+{
+ /* enable read access for all registers */
+ return 1;
+}
+
+static bool tfa98xx_volatile_register(struct device *dev, unsigned int reg)
+{
+ /* enable read access for all registers */
+ return 1;
+}
+
+static const struct regmap_config tfa98xx_regmap = {
+ .reg_bits = 8,
+ .val_bits = 16,
+
+ .max_register = TFA98XX_MAX_REGISTER,
+ .writeable_reg = tfa98xx_writeable_register,
+ .readable_reg = tfa98xx_readable_register,
+ .volatile_reg = tfa98xx_volatile_register,
+ .cache_type = REGCACHE_NONE,
+};
+
+static void tfa98xx_irq_tfa2(struct tfa98xx *tfa98xx)
+{
+ pr_info("\n");
+
+ /*
+ * mask interrupts
+ * will be unmasked after handling interrupts in workqueue
+ */
+ tfa_irq_mask(tfa98xx->tfa);
+ queue_delayed_work(tfa98xx->tfa98xx_wq, &tfa98xx->interrupt_work, 0);
+}
+
+
+static irqreturn_t tfa98xx_irq(int irq, void *data)
+{
+ struct tfa98xx *tfa98xx = data;
+
+ if (tfa98xx->tfa->tfa_family == 2)
+ tfa98xx_irq_tfa2(tfa98xx);
+
+ return IRQ_HANDLED;
+}
+
+static int tfa98xx_ext_reset(struct tfa98xx *tfa98xx)
+{
+ if (tfa98xx && gpio_is_valid(tfa98xx->reset_gpio)) {
+ int reset = tfa98xx->reset_polarity;
+
+ gpio_set_value_cansleep(tfa98xx->reset_gpio, reset);
+ mdelay(1);
+ gpio_set_value_cansleep(tfa98xx->reset_gpio, !reset);
+ mdelay(1);
+ }
+ return 0;
+}
+
+static int tfa98xx_parse_dt(struct device *dev, struct tfa98xx *tfa98xx,
+ struct device_node *np) {
+ u32 value;
+ int ret;
+
+ tfa98xx->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
+ if (tfa98xx->reset_gpio < 0)
+ dev_dbg(dev, "No reset GPIO provided, will not HW reset device\n");
+
+ tfa98xx->irq_gpio = of_get_named_gpio(np, "irq-gpio", 0);
+ if (tfa98xx->irq_gpio < 0)
+ dev_dbg(dev, "No IRQ GPIO provided.\n");
+ ret = of_property_read_u32(np, "reset-polarity", &value);
+ if (ret < 0)
+ tfa98xx->reset_polarity = HIGH;
+ else
+ tfa98xx->reset_polarity = (value == 0) ? LOW : HIGH;
+
+ dev_dbg(dev, "reset-polarity:%d\n", tfa98xx->reset_polarity);
+ return 0;
+}
+
+static ssize_t tfa98xx_reg_write(struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ struct device *dev = container_of(kobj, struct device, kobj);
+ struct tfa98xx *tfa98xx = dev_get_drvdata(dev);
+
+ if (count != 1) {
+ pr_debug("invalid register address");
+ return -EINVAL;
+ }
+
+ tfa98xx->reg = buf[0];
+
+ return 1;
+}
+
+static ssize_t tfa98xx_rw_write(struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ struct device *dev = container_of(kobj, struct device, kobj);
+ struct tfa98xx *tfa98xx = dev_get_drvdata(dev);
+ u8 *data;
+ int ret;
+ int retries = I2C_RETRIES;
+
+ data = kmalloc(count + 1, GFP_KERNEL);
+ if (!data) {
+ pr_debug("can not allocate memory\n");
+ return -ENOMEM;
+ }
+
+ data[0] = tfa98xx->reg;
+ memcpy(&data[1], buf, count);
+
+retry:
+ ret = i2c_master_send(tfa98xx->i2c, data, count + 1);
+ if (ret < 0) {
+ pr_warn("i2c error, retries left: %d\n", retries);
+ if (retries) {
+ retries--;
+ msleep(I2C_RETRY_DELAY);
+ goto retry;
+ }
+ }
+
+ kfree(data);
+
+ /* the number of data bytes written without the register address */
+ return ((ret > 1) ? count : -EIO);
+}
+
+static ssize_t tfa98xx_rw_read(struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ struct device *dev = container_of(kobj, struct device, kobj);
+ struct tfa98xx *tfa98xx = dev_get_drvdata(dev);
+ struct i2c_msg msgs[] = {
+ {
+ .addr = tfa98xx->i2c->addr,
+ .flags = 0,
+ .len = 1,
+ .buf = &tfa98xx->reg,
+ },
+ {
+ .addr = tfa98xx->i2c->addr,
+ .flags = I2C_M_RD,
+ .len = count,
+ .buf = buf,
+ },
+ };
+ int ret;
+ int retries = I2C_RETRIES;
+retry:
+ ret = i2c_transfer(tfa98xx->i2c->adapter, msgs, ARRAY_SIZE(msgs));
+ if (ret < 0) {
+ pr_warn("i2c error, retries left: %d\n", retries);
+ if (retries) {
+ retries--;
+ msleep(I2C_RETRY_DELAY);
+ goto retry;
+ }
+ return ret;
+ }
+ /* ret contains the number of i2c transaction */
+ /* return the number of bytes read */
+ return ((ret > 1) ? count : -EIO);
+}
+
+static struct bin_attribute dev_attr_rw = {
+ .attr = {
+ .name = "rw",
+ .mode = S_IRUSR | S_IWUSR,
+ },
+ .size = 0,
+ .read = tfa98xx_rw_read,
+ .write = tfa98xx_rw_write,
+};
+
+static struct bin_attribute dev_attr_reg = {
+ .attr = {
+ .name = "reg",
+ .mode = S_IWUSR,
+ },
+ .size = 0,
+ .read = NULL,
+ .write = tfa98xx_reg_write,
+};
+
+static int tfa98xx_i2c_probe(struct i2c_client *i2c,
+ const struct i2c_device_id *id)
+{
+ struct snd_soc_dai_driver *dai;
+ struct tfa98xx *tfa98xx;
+ struct device_node *np = i2c->dev.of_node;
+ int irq_flags;
+ unsigned int reg;
+ int ret;
+
+ pr_info("addr=0x%x\n", i2c->addr);
+
+ if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_I2C)) {
+ dev_err(&i2c->dev, "check_functionality failed\n");
+ return -EIO;
+ }
+
+ tfa98xx = devm_kzalloc(&i2c->dev, sizeof(struct tfa98xx), GFP_KERNEL);
+ if (tfa98xx == NULL)
+ return -ENOMEM;
+
+ tfa98xx->dev = &i2c->dev;
+ tfa98xx->i2c = i2c;
+ tfa98xx->dsp_init = TFA98XX_DSP_INIT_STOPPED;
+ tfa98xx->rate = 48000; /* init to the default sample rate (48kHz) */
+ tfa98xx->tfa = NULL;
+
+ tfa98xx->regmap = devm_regmap_init_i2c(i2c, &tfa98xx_regmap);
+ if (IS_ERR(tfa98xx->regmap)) {
+ ret = PTR_ERR(tfa98xx->regmap);
+ dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
+ ret);
+ return ret;
+ }
+
+ i2c_set_clientdata(i2c, tfa98xx);
+ mutex_init(&tfa98xx->dsp_lock);
+ init_waitqueue_head(&tfa98xx->wq);
+
+ if (np) {
+ ret = tfa98xx_parse_dt(&i2c->dev, tfa98xx, np);
+ if (ret) {
+ dev_err(&i2c->dev, "Failed to parse DT node\n");
+ return ret;
+ }
+ if (no_start)
+ tfa98xx->irq_gpio = -1;
+ if (no_reset)
+ tfa98xx->reset_gpio = -1;
+ } else {
+ tfa98xx->reset_gpio = -1;
+ tfa98xx->irq_gpio = -1;
+ }
+
+ if (gpio_is_valid(tfa98xx->reset_gpio)) {
+ ret = devm_gpio_request_one(&i2c->dev, tfa98xx->reset_gpio,
+ GPIOF_OUT_INIT_LOW, "TFA98XX_RST");
+ if (ret)
+ return ret;
+ }
+
+ if (gpio_is_valid(tfa98xx->irq_gpio)) {
+ ret = devm_gpio_request_one(&i2c->dev, tfa98xx->irq_gpio,
+ GPIOF_DIR_IN, "TFA98XX_INT");
+ if (ret)
+ return ret;
+ }
+
+ /* Power up! */
+ tfa98xx_ext_reset(tfa98xx);
+
+ if ((no_start == 0) && (no_reset == 0)) {
+ ret = regmap_read(tfa98xx->regmap, 0x03, ®);
+ if (ret < 0) {
+ dev_err(&i2c->dev, "Failed to read Revision register: %d\n",
+ ret);
+ return -EIO;
+ }
+ switch (reg & 0xff) {
+ case 0x72: /* tfa9872 */
+ pr_info("TFA9872 detected\n");
+ tfa98xx->flags |= TFA98XX_FLAG_MULTI_MIC_INPUTS;
+ tfa98xx->flags |= TFA98XX_FLAG_CALIBRATION_CTL;
+ tfa98xx->flags |= TFA98XX_FLAG_REMOVE_PLOP_NOISE;
+ /* tfa98xx->flags |= TFA98XX_FLAG_LP_MODES; */
+ tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE;
+ break;
+ case 0x74: /* tfa9874 */
+ pr_info("TFA9874 detected\n");
+ tfa98xx->flags |= TFA98XX_FLAG_MULTI_MIC_INPUTS;
+ tfa98xx->flags |= TFA98XX_FLAG_CALIBRATION_CTL;
+ tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE;
+ break;
+ case 0x78: /* tfa9878 */
+ pr_info("TFA9878 detected\n");
+ tfa98xx->flags |= TFA98XX_FLAG_MULTI_MIC_INPUTS;
+ tfa98xx->flags |= TFA98XX_FLAG_CALIBRATION_CTL;
+ tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE;
+ break;
+ case 0x88: /* tfa9888 */
+ pr_info("TFA9888 detected\n");
+ tfa98xx->flags |= TFA98XX_FLAG_STEREO_DEVICE;
+ tfa98xx->flags |= TFA98XX_FLAG_MULTI_MIC_INPUTS;
+ tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE;
+ break;
+ case 0x13: /* tfa9912 */
+ pr_info("TFA9912 detected\n");
+ tfa98xx->flags |= TFA98XX_FLAG_MULTI_MIC_INPUTS;
+ tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE;
+ /* tfa98xx->flags |= TFA98XX_FLAG_TAPDET_AVAILABLE; */
+ break;
+ case 0x94: /* tfa9894 */
+ pr_info("TFA9894 detected\n");
+ tfa98xx->flags |= TFA98XX_FLAG_MULTI_MIC_INPUTS;
+ tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE;
+ break;
+ case 0x80: /* tfa9890 */
+ case 0x81: /* tfa9890 */
+ pr_info("TFA9890 detected\n");
+ tfa98xx->flags |= TFA98XX_FLAG_SKIP_INTERRUPTS;
+ break;
+ case 0x92: /* tfa9891 */
+ pr_info("TFA9891 detected\n");
+ tfa98xx->flags |= TFA98XX_FLAG_SAAM_AVAILABLE;
+ tfa98xx->flags |= TFA98XX_FLAG_SKIP_INTERRUPTS;
+ break;
+ case 0x12: /* tfa9895 */
+ pr_info("TFA9895 detected\n");
+ tfa98xx->flags |= TFA98XX_FLAG_SKIP_INTERRUPTS;
+ break;
+ case 0x97:
+ pr_info("TFA9897 detected\n");
+ tfa98xx->flags |= TFA98XX_FLAG_SKIP_INTERRUPTS;
+ tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE;
+ break;
+ case 0x96:
+ pr_info("TFA9896 detected\n");
+ tfa98xx->flags |= TFA98XX_FLAG_SKIP_INTERRUPTS;
+ tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE;
+ break;
+ default:
+ pr_info("Unsupported device revision (0x%x)\n", reg & 0xff);
+ return -EINVAL;
+ }
+ }
+
+ tfa98xx->tfa = devm_kzalloc(&i2c->dev, sizeof(struct tfa_device),
+ GFP_KERNEL);
+ if (tfa98xx->tfa == NULL)
+ return -ENOMEM;
+
+ tfa98xx->tfa->data = (void *)tfa98xx;
+ tfa98xx->tfa->cachep = tfa98xx_cache;
+
+ /* Modify the stream names, by appending the i2c device address.
+ * This is used with multicodec, in order to discriminate the devices.
+ * Stream names appear in the dai definition and in the stream.
+ * We create copies of original structures because each device will
+ * have its own instance of this structure, with its own address.
+ */
+ dai = devm_kzalloc(&i2c->dev, sizeof(tfa98xx_dai), GFP_KERNEL);
+ if (!dai)
+ return -ENOMEM;
+ memcpy(dai, tfa98xx_dai, sizeof(tfa98xx_dai));
+
+ tfa98xx_append_i2c_address(&i2c->dev,
+ i2c,
+ NULL,
+ 0,
+ dai,
+ ARRAY_SIZE(tfa98xx_dai));
+
+ ret = snd_soc_register_codec(&i2c->dev,
+ &soc_codec_dev_tfa98xx, dai,
+ ARRAY_SIZE(tfa98xx_dai));
+
+ if (ret < 0) {
+ dev_err(&i2c->dev, "Failed to register TFA98xx: %d\n", ret);
+ return ret;
+ }
+
+ if (gpio_is_valid(tfa98xx->irq_gpio) &&
+ !(tfa98xx->flags & TFA98XX_FLAG_SKIP_INTERRUPTS)) {
+ /* register irq handler */
+ irq_flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
+ ret = devm_request_threaded_irq(&i2c->dev,
+ gpio_to_irq(tfa98xx->irq_gpio),
+ NULL, tfa98xx_irq, irq_flags,
+ "tfa98xx", tfa98xx);
+ if (ret != 0) {
+ dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
+ gpio_to_irq(tfa98xx->irq_gpio), ret);
+ return ret;
+ }
+ } else {
+ dev_info(&i2c->dev, "Skipping IRQ registration\n");
+ /* disable feature support if gpio was invalid */
+ tfa98xx->flags |= TFA98XX_FLAG_SKIP_INTERRUPTS;
+ }
+
+#ifdef CONFIG_DEBUG_FS
+ if (no_start == 0)
+ tfa98xx_debug_init(tfa98xx, i2c);
+#endif
+ /* Register the sysfs files for climax backdoor access */
+ ret = device_create_bin_file(&i2c->dev, &dev_attr_rw);
+ if (ret)
+ dev_info(&i2c->dev, "error creating sysfs files\n");
+ ret = device_create_bin_file(&i2c->dev, &dev_attr_reg);
+ if (ret)
+ dev_info(&i2c->dev, "error creating sysfs files\n");
+
+ pr_info("%s Probe completed successfully!\n", __func__);
+
+ INIT_LIST_HEAD(&tfa98xx->list);
+
+ mutex_lock(&tfa98xx_mutex);
+ tfa98xx_device_count++;
+ list_add(&tfa98xx->list, &tfa98xx_device_list);
+ mutex_unlock(&tfa98xx_mutex);
+
+ return 0;
+}
+
+static int tfa98xx_i2c_remove(struct i2c_client *i2c)
+{
+ struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c);
+
+ pr_debug("addr=0x%x\n", i2c->addr);
+
+ tfa98xx_interrupt_enable(tfa98xx, false);
+
+ cancel_delayed_work_sync(&tfa98xx->interrupt_work);
+ cancel_delayed_work_sync(&tfa98xx->monitor_work);
+ cancel_delayed_work_sync(&tfa98xx->init_work);
+ cancel_delayed_work_sync(&tfa98xx->tapdet_work);
+
+ device_remove_bin_file(&i2c->dev, &dev_attr_reg);
+ device_remove_bin_file(&i2c->dev, &dev_attr_rw);
+#ifdef CONFIG_DEBUG_FS
+ tfa98xx_debug_remove(tfa98xx);
+#endif
+
+ snd_soc_unregister_codec(&i2c->dev);
+
+ if (gpio_is_valid(tfa98xx->irq_gpio))
+ devm_gpio_free(&i2c->dev, tfa98xx->irq_gpio);
+ if (gpio_is_valid(tfa98xx->reset_gpio))
+ devm_gpio_free(&i2c->dev, tfa98xx->reset_gpio);
+
+ mutex_lock(&tfa98xx_mutex);
+ list_del(&tfa98xx->list);
+ tfa98xx_device_count--;
+ if (tfa98xx_device_count == 0) {
+ kfree(tfa98xx_container);
+ tfa98xx_container = NULL;
+ }
+ mutex_unlock(&tfa98xx_mutex);
+
+ return 0;
+}
+
+static const struct i2c_device_id tfa98xx_i2c_id[] = {
+ { "tfa98xx", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, tfa98xx_i2c_id);
+
+#ifdef CONFIG_OF
+static const struct of_device_id tfa98xx_dt_match[] = {
+ {.compatible = "nxp,tfa98xx" },
+ {.compatible = "nxp,tfa9872" },
+ {.compatible = "nxp,tfa9874" },
+ {.compatible = "nxp,tfa9878" },
+ {.compatible = "nxp,tfa9888" },
+ {.compatible = "nxp,tfa9890" },
+ {.compatible = "nxp,tfa9891" },
+ {.compatible = "nxp,tfa9894" },
+ {.compatible = "nxp,tfa9895" },
+ {.compatible = "nxp,tfa9896" },
+ {.compatible = "nxp,tfa9897" },
+ {.compatible = "nxp,tfa9912" },
+ { },
+};
+#endif
+
+static struct i2c_driver tfa98xx_i2c_driver = {
+ .driver = {
+ .name = "tfa98xx",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(tfa98xx_dt_match),
+ },
+ .probe = tfa98xx_i2c_probe,
+ .remove = tfa98xx_i2c_remove,
+ .id_table = tfa98xx_i2c_id,
+};
+
+static int __init tfa98xx_i2c_init(void)
+{
+ int ret = 0;
+
+ pr_info("TFA98XX driver version %s\n", TFA98XX_VERSION);
+
+ /* Enable debug traces */
+ tfa98xx_kmsg_regs = trace_level & 2;
+ tfa98xx_ftrace_regs = trace_level & 4;
+
+ /* Initialize kmem_cache */
+ /* Cache name /proc/slabinfo */
+ tfa98xx_cache = kmem_cache_create("tfa98xx_cache",
+ PAGE_SIZE, /* Structure size, we should fit in single page */
+ 0, /* Structure alignment */
+ (SLAB_HWCACHE_ALIGN | SLAB_RECLAIM_ACCOUNT |
+ SLAB_MEM_SPREAD), /* Cache property */
+ NULL); /* Object constructor */
+ if (!tfa98xx_cache) {
+ pr_err("tfa98xx can't create memory pool\n");
+ ret = -ENOMEM;
+ }
+
+ ret = i2c_add_driver(&tfa98xx_i2c_driver);
+
+ return ret;
+}
+module_init(tfa98xx_i2c_init);
+
+static void __exit tfa98xx_i2c_exit(void)
+{
+ i2c_del_driver(&tfa98xx_i2c_driver);
+ kmem_cache_destroy(tfa98xx_cache);
+}
+module_exit(tfa98xx_i2c_exit);
+
+MODULE_DESCRIPTION("ASoC TFA98XX driver");
+MODULE_LICENSE("GPL");
+
diff --git a/inc/tfa98xx.h b/sound/soc/codecs/tfa98xx.h
similarity index 97%
rename from inc/tfa98xx.h
rename to sound/soc/codecs/tfa98xx.h
index f6e9ff8..3ba367a 100644
--- a/inc/tfa98xx.h
+++ b/sound/soc/codecs/tfa98xx.h
@@ -1,127 +1,127 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __TFA98XX_INC__
-#define __TFA98XX_INC__
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/list.h>
-
-#include "tfa_device.h"
-#include "tfa_container.h"
-#include "config.h"
-
-/* max. length of a alsa mixer control name */
-#define MAX_CONTROL_NAME 48
-
-#define TFA98XX_MAX_REGISTER 0xff
-
-#define TFA98XX_FLAG_SKIP_INTERRUPTS (1 << 0)
-#define TFA98XX_FLAG_SAAM_AVAILABLE (1 << 1)
-#define TFA98XX_FLAG_STEREO_DEVICE (1 << 2)
-#define TFA98XX_FLAG_MULTI_MIC_INPUTS (1 << 3)
-#define TFA98XX_FLAG_TAPDET_AVAILABLE (1 << 4)
-#define TFA98XX_FLAG_CALIBRATION_CTL (1 << 5)
-#define TFA98XX_FLAG_REMOVE_PLOP_NOISE (1 << 6)
-#define TFA98XX_FLAG_LP_MODES (1 << 7)
-#define TFA98XX_FLAG_TDM_DEVICE (1 << 8)
-
-#define TFA98XX_NUM_RATES 9
-
-/* DSP init status */
-enum tfa98xx_dsp_init_state {
- TFA98XX_DSP_INIT_STOPPED, /* DSP not running */
- TFA98XX_DSP_INIT_RECOVER, /* DSP error detected at runtime */
- TFA98XX_DSP_INIT_FAIL, /* DSP init failed */
- TFA98XX_DSP_INIT_PENDING, /* DSP start requested */
- TFA98XX_DSP_INIT_DONE, /* DSP running */
- TFA98XX_DSP_INIT_INVALIDATED, /* DSP was running, requires re-init */
-};
-
-enum tfa98xx_dsp_fw_state {
- TFA98XX_DSP_FW_NONE = 0,
- TFA98XX_DSP_FW_PENDING,
- TFA98XX_DSP_FW_FAIL,
- TFA98XX_DSP_FW_OK,
-};
-
-struct tfa98xx_firmware {
- void *base;
- struct tfa98xx_device *dev;
- char name[9]; //TODO get length from tfa parameter defs
-};
-
-struct tfa98xx_baseprofile {
- char basename[MAX_CONTROL_NAME]; /* profile basename */
- int len; /* profile length */
- int item_id; /* profile id */
- int sr_rate_sup[TFA98XX_NUM_RATES]; /* sample rates supported by this profile */
- struct list_head list; /* list of all profiles */
-};
-enum tfa_reset_polarity{
- LOW=0,
- HIGH=1
-};
-struct tfa98xx {
- struct regmap *regmap;
- struct i2c_client *i2c;
- struct regulator *vdd;
- struct snd_soc_codec *codec;
- struct workqueue_struct *tfa98xx_wq;
- struct delayed_work init_work;
- struct delayed_work monitor_work;
- struct delayed_work interrupt_work;
- struct delayed_work tapdet_work;
- struct mutex dsp_lock;
- int dsp_init;
- int dsp_fw_state;
- int sysclk;
- int rst_gpio;
- u16 rev;
- int audio_mode;
- struct tfa98xx_firmware fw;
- char *fw_name;
- int rate;
- wait_queue_head_t wq;
- struct device *dev;
- unsigned int init_count;
- int pstream;
- int cstream;
- struct input_dev *input;
- bool tapdet_enabled; /* service enabled */
- bool tapdet_open; /* device file opened */
- unsigned int tapdet_profiles; /* tapdet profile bitfield */
- bool tapdet_poll; /* tapdet running on polling mode */
-
- unsigned int rate_constraint_list[TFA98XX_NUM_RATES];
- struct snd_pcm_hw_constraint_list rate_constraint;
-
- int reset_gpio;
- int power_gpio;
- int irq_gpio;
- enum tfa_reset_polarity reset_polarity;
- struct list_head list;
- struct tfa_device *tfa;
- int vstep;
- int profile;
- int prof_vsteps[TFACONT_MAXPROFS]; /* store vstep per profile (single device) */
-
-#ifdef CONFIG_DEBUG_FS
- struct dentry *dbg_dir;
-#endif
- u8 reg;
- unsigned int flags;
- bool set_mtp_cal;
- uint16_t cal_data;
-};
-
-
-#endif /* __TFA98XX_INC__ */
-
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __TFA98XX_INC__
+#define __TFA98XX_INC__
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/list.h>
+
+#include "tfa_device.h"
+#include "tfa_container.h"
+#include "config.h"
+
+/* max. length of a alsa mixer control name */
+#define MAX_CONTROL_NAME 48
+
+#define TFA98XX_MAX_REGISTER 0xff
+
+#define TFA98XX_FLAG_SKIP_INTERRUPTS (1 << 0)
+#define TFA98XX_FLAG_SAAM_AVAILABLE (1 << 1)
+#define TFA98XX_FLAG_STEREO_DEVICE (1 << 2)
+#define TFA98XX_FLAG_MULTI_MIC_INPUTS (1 << 3)
+#define TFA98XX_FLAG_TAPDET_AVAILABLE (1 << 4)
+#define TFA98XX_FLAG_CALIBRATION_CTL (1 << 5)
+#define TFA98XX_FLAG_REMOVE_PLOP_NOISE (1 << 6)
+#define TFA98XX_FLAG_LP_MODES (1 << 7)
+#define TFA98XX_FLAG_TDM_DEVICE (1 << 8)
+
+#define TFA98XX_NUM_RATES 9
+
+/* DSP init status */
+enum tfa98xx_dsp_init_state {
+ TFA98XX_DSP_INIT_STOPPED, /* DSP not running */
+ TFA98XX_DSP_INIT_RECOVER, /* DSP error detected at runtime */
+ TFA98XX_DSP_INIT_FAIL, /* DSP init failed */
+ TFA98XX_DSP_INIT_PENDING, /* DSP start requested */
+ TFA98XX_DSP_INIT_DONE, /* DSP running */
+ TFA98XX_DSP_INIT_INVALIDATED, /* DSP was running, requires re-init */
+};
+
+enum tfa98xx_dsp_fw_state {
+ TFA98XX_DSP_FW_NONE = 0,
+ TFA98XX_DSP_FW_PENDING,
+ TFA98XX_DSP_FW_FAIL,
+ TFA98XX_DSP_FW_OK,
+};
+
+struct tfa98xx_firmware {
+ void *base;
+ struct tfa98xx_device *dev;
+ char name[9]; //TODO get length from tfa parameter defs
+};
+
+struct tfa98xx_baseprofile {
+ char basename[MAX_CONTROL_NAME]; /* profile basename */
+ int len; /* profile length */
+ int item_id; /* profile id */
+ int sr_rate_sup[TFA98XX_NUM_RATES]; /* sample rates supported by this profile */
+ struct list_head list; /* list of all profiles */
+};
+enum tfa_reset_polarity{
+ LOW = 0,
+ HIGH = 1
+};
+struct tfa98xx {
+ struct regmap *regmap;
+ struct i2c_client *i2c;
+ struct regulator *vdd;
+ struct snd_soc_codec *codec;
+ struct workqueue_struct *tfa98xx_wq;
+ struct delayed_work init_work;
+ struct delayed_work monitor_work;
+ struct delayed_work interrupt_work;
+ struct delayed_work tapdet_work;
+ struct mutex dsp_lock;
+ int dsp_init;
+ int dsp_fw_state;
+ int sysclk;
+ int rst_gpio;
+ u16 rev;
+ int audio_mode;
+ struct tfa98xx_firmware fw;
+ char *fw_name;
+ int rate;
+ wait_queue_head_t wq;
+ struct device *dev;
+ unsigned int init_count;
+ int pstream;
+ int cstream;
+ struct input_dev *input;
+ bool tapdet_enabled; /* service enabled */
+ bool tapdet_open; /* device file opened */
+ unsigned int tapdet_profiles; /* tapdet profile bitfield */
+ bool tapdet_poll; /* tapdet running on polling mode */
+
+ unsigned int rate_constraint_list[TFA98XX_NUM_RATES];
+ struct snd_pcm_hw_constraint_list rate_constraint;
+
+ int reset_gpio;
+ int power_gpio;
+ int irq_gpio;
+ enum tfa_reset_polarity reset_polarity;
+ struct list_head list;
+ struct tfa_device *tfa;
+ int vstep;
+ int profile;
+ int prof_vsteps[TFACONT_MAXPROFS]; /* store vstep per profile (single device) */
+
+#ifdef CONFIG_DEBUG_FS
+ struct dentry *dbg_dir;
+#endif
+ u8 reg;
+ unsigned int flags;
+ bool set_mtp_cal;
+ uint16_t cal_data;
+};
+
+
+#endif /* __TFA98XX_INC__ */
+
diff --git a/inc/tfa98xx_genregs_N1C.h b/sound/soc/codecs/tfa98xx_genregs_N1C.h
similarity index 99%
rename from inc/tfa98xx_genregs_N1C.h
rename to sound/soc/codecs/tfa98xx_genregs_N1C.h
index aa67c38..eb1e1ad 100644
--- a/inc/tfa98xx_genregs_N1C.h
+++ b/sound/soc/codecs/tfa98xx_genregs_N1C.h
@@ -1,3857 +1,3857 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef TFA2_GENREGS_H
-#define TFA2_GENREGS_H
-
-
-#define TFA98XX_SYS_CONTROL0 0x00
-#define TFA98XX_SYS_CONTROL1 0x01
-#define TFA98XX_SYS_CONTROL2 0x02
-#define TFA98XX_DEVICE_REVISION 0x03
-#define TFA98XX_CLOCK_CONTROL 0x04
-#define TFA98XX_CLOCK_GATING_CONTROL 0x05
-#define TFA98XX_SIDE_TONE_CONFIG 0x0d
-#define TFA98XX_CTRL_DIGTOANA_REG 0x0e
-#define TFA98XX_STATUS_FLAGS0 0x10
-#define TFA98XX_STATUS_FLAGS1 0x11
-#define TFA98XX_STATUS_FLAGS2 0x12
-#define TFA98XX_STATUS_FLAGS3 0x13
-#define TFA98XX_STATUS_FLAGS4 0x14
-#define TFA98XX_BATTERY_VOLTAGE 0x15
-#define TFA98XX_TEMPERATURE 0x16
-#define TFA98XX_TDM_CONFIG0 0x20
-#define TFA98XX_TDM_CONFIG1 0x21
-#define TFA98XX_TDM_CONFIG2 0x22
-#define TFA98XX_TDM_CONFIG3 0x23
-#define TFA98XX_TDM_CONFIG4 0x24
-#define TFA98XX_TDM_CONFIG5 0x25
-#define TFA98XX_TDM_CONFIG6 0x26
-#define TFA98XX_TDM_CONFIG7 0x27
-#define TFA98XX_TDM_CONFIG8 0x28
-#define TFA98XX_TDM_CONFIG9 0x29
-#define TFA98XX_PDM_CONFIG0 0x31
-#define TFA98XX_PDM_CONFIG1 0x32
-#define TFA98XX_HAPTIC_DRIVER_CONFIG 0x33
-#define TFA98XX_GPIO_DATAIN_REG 0x34
-#define TFA98XX_GPIO_CONFIG 0x35
-#define TFA98XX_INTERRUPT_OUT_REG1 0x40
-#define TFA98XX_INTERRUPT_OUT_REG2 0x41
-#define TFA98XX_INTERRUPT_OUT_REG3 0x42
-#define TFA98XX_INTERRUPT_IN_REG1 0x44
-#define TFA98XX_INTERRUPT_IN_REG2 0x45
-#define TFA98XX_INTERRUPT_IN_REG3 0x46
-#define TFA98XX_INTERRUPT_ENABLE_REG1 0x48
-#define TFA98XX_INTERRUPT_ENABLE_REG2 0x49
-#define TFA98XX_INTERRUPT_ENABLE_REG3 0x4a
-#define TFA98XX_STATUS_POLARITY_REG1 0x4c
-#define TFA98XX_STATUS_POLARITY_REG2 0x4d
-#define TFA98XX_STATUS_POLARITY_REG3 0x4e
-#define TFA98XX_BAT_PROT_CONFIG 0x50
-#define TFA98XX_AUDIO_CONTROL 0x51
-#define TFA98XX_AMPLIFIER_CONFIG 0x52
-#define TFA98XX_AUDIO_CONTROL2 0x5a
-#define TFA98XX_DCDC_CONTROL0 0x70
-#define TFA98XX_CF_CONTROLS 0x90
-#define TFA98XX_CF_MAD 0x91
-#define TFA98XX_CF_MEM 0x92
-#define TFA98XX_CF_STATUS 0x93
-#define TFA98XX_MTPKEY2_REG 0xa1
-#define TFA98XX_MTP_STATUS 0xa2
-#define TFA98XX_KEY_PROTECTED_MTP_CONTROL 0xa3
-#define TFA98XX_MTP_DATA_OUT_MSB 0xa5
-#define TFA98XX_MTP_DATA_OUT_LSB 0xa6
-#define TFA98XX_TEMP_SENSOR_CONFIG 0xb1
-#define TFA98XX_KEY2_PROTECTED_MTP0 0xf0
-#define TFA98XX_KEY1_PROTECTED_MTP4 0xf4
-#define TFA98XX_KEY1_PROTECTED_MTP5 0xf5
-
-/*
- * (0x00)-sys_control0
- */
-
-/*
- * powerdown
- */
-#define TFA98XX_SYS_CONTROL0_PWDN (0x1<<0)
-#define TFA98XX_SYS_CONTROL0_PWDN_POS 0
-#define TFA98XX_SYS_CONTROL0_PWDN_LEN 1
-#define TFA98XX_SYS_CONTROL0_PWDN_MAX 1
-#define TFA98XX_SYS_CONTROL0_PWDN_MSK 0x1
-
-/*
- * reset
- */
-#define TFA98XX_SYS_CONTROL0_I2CR (0x1<<1)
-#define TFA98XX_SYS_CONTROL0_I2CR_POS 1
-#define TFA98XX_SYS_CONTROL0_I2CR_LEN 1
-#define TFA98XX_SYS_CONTROL0_I2CR_MAX 1
-#define TFA98XX_SYS_CONTROL0_I2CR_MSK 0x2
-
-/*
- * enbl_coolflux
- */
-#define TFA98XX_SYS_CONTROL0_CFE (0x1<<2)
-#define TFA98XX_SYS_CONTROL0_CFE_POS 2
-#define TFA98XX_SYS_CONTROL0_CFE_LEN 1
-#define TFA98XX_SYS_CONTROL0_CFE_MAX 1
-#define TFA98XX_SYS_CONTROL0_CFE_MSK 0x4
-
-/*
- * enbl_amplifier
- */
-#define TFA98XX_SYS_CONTROL0_AMPE (0x1<<3)
-#define TFA98XX_SYS_CONTROL0_AMPE_POS 3
-#define TFA98XX_SYS_CONTROL0_AMPE_LEN 1
-#define TFA98XX_SYS_CONTROL0_AMPE_MAX 1
-#define TFA98XX_SYS_CONTROL0_AMPE_MSK 0x8
-
-/*
- * enbl_boost
- */
-#define TFA98XX_SYS_CONTROL0_DCA (0x1<<4)
-#define TFA98XX_SYS_CONTROL0_DCA_POS 4
-#define TFA98XX_SYS_CONTROL0_DCA_LEN 1
-#define TFA98XX_SYS_CONTROL0_DCA_MAX 1
-#define TFA98XX_SYS_CONTROL0_DCA_MSK 0x10
-
-/*
- * coolflux_configured
- */
-#define TFA98XX_SYS_CONTROL0_SBSL (0x1<<5)
-#define TFA98XX_SYS_CONTROL0_SBSL_POS 5
-#define TFA98XX_SYS_CONTROL0_SBSL_LEN 1
-#define TFA98XX_SYS_CONTROL0_SBSL_MAX 1
-#define TFA98XX_SYS_CONTROL0_SBSL_MSK 0x20
-
-/*
- * sel_enbl_amplifier
- */
-#define TFA98XX_SYS_CONTROL0_AMPC (0x1<<6)
-#define TFA98XX_SYS_CONTROL0_AMPC_POS 6
-#define TFA98XX_SYS_CONTROL0_AMPC_LEN 1
-#define TFA98XX_SYS_CONTROL0_AMPC_MAX 1
-#define TFA98XX_SYS_CONTROL0_AMPC_MSK 0x40
-
-/*
- * int_pad_io
- */
-#define TFA98XX_SYS_CONTROL0_INTP (0x3<<7)
-#define TFA98XX_SYS_CONTROL0_INTP_POS 7
-#define TFA98XX_SYS_CONTROL0_INTP_LEN 2
-#define TFA98XX_SYS_CONTROL0_INTP_MAX 3
-#define TFA98XX_SYS_CONTROL0_INTP_MSK 0x180
-
-/*
- * fs_pulse_sel
- */
-#define TFA98XX_SYS_CONTROL0_FSSSEL (0x3<<9)
-#define TFA98XX_SYS_CONTROL0_FSSSEL_POS 9
-#define TFA98XX_SYS_CONTROL0_FSSSEL_LEN 2
-#define TFA98XX_SYS_CONTROL0_FSSSEL_MAX 3
-#define TFA98XX_SYS_CONTROL0_FSSSEL_MSK 0x600
-
-/*
- * bypass_ocp
- */
-#define TFA98XX_SYS_CONTROL0_BYPOCP (0x1<<11)
-#define TFA98XX_SYS_CONTROL0_BYPOCP_POS 11
-#define TFA98XX_SYS_CONTROL0_BYPOCP_LEN 1
-#define TFA98XX_SYS_CONTROL0_BYPOCP_MAX 1
-#define TFA98XX_SYS_CONTROL0_BYPOCP_MSK 0x800
-
-/*
- * test_ocp
- */
-#define TFA98XX_SYS_CONTROL0_TSTOCP (0x1<<12)
-#define TFA98XX_SYS_CONTROL0_TSTOCP_POS 12
-#define TFA98XX_SYS_CONTROL0_TSTOCP_LEN 1
-#define TFA98XX_SYS_CONTROL0_TSTOCP_MAX 1
-#define TFA98XX_SYS_CONTROL0_TSTOCP_MSK 0x1000
-
-
-/*
- * (0x01)-sys_control1
- */
-
-/*
- * vamp_sel
- */
-#define TFA98XX_SYS_CONTROL1_AMPINSEL (0x3<<0)
-#define TFA98XX_SYS_CONTROL1_AMPINSEL_POS 0
-#define TFA98XX_SYS_CONTROL1_AMPINSEL_LEN 2
-#define TFA98XX_SYS_CONTROL1_AMPINSEL_MAX 3
-#define TFA98XX_SYS_CONTROL1_AMPINSEL_MSK 0x3
-
-/*
- * src_set_configured
- */
-#define TFA98XX_SYS_CONTROL1_MANSCONF (0x1<<2)
-#define TFA98XX_SYS_CONTROL1_MANSCONF_POS 2
-#define TFA98XX_SYS_CONTROL1_MANSCONF_LEN 1
-#define TFA98XX_SYS_CONTROL1_MANSCONF_MAX 1
-#define TFA98XX_SYS_CONTROL1_MANSCONF_MSK 0x4
-
-/*
- * execute_cold_start
- */
-#define TFA98XX_SYS_CONTROL1_MANCOLD (0x1<<3)
-#define TFA98XX_SYS_CONTROL1_MANCOLD_POS 3
-#define TFA98XX_SYS_CONTROL1_MANCOLD_LEN 1
-#define TFA98XX_SYS_CONTROL1_MANCOLD_MAX 1
-#define TFA98XX_SYS_CONTROL1_MANCOLD_MSK 0x8
-
-/*
- * enbl_osc1m_auto_off
- */
-#define TFA98XX_SYS_CONTROL1_MANAOOSC (0x1<<4)
-#define TFA98XX_SYS_CONTROL1_MANAOOSC_POS 4
-#define TFA98XX_SYS_CONTROL1_MANAOOSC_LEN 1
-#define TFA98XX_SYS_CONTROL1_MANAOOSC_MAX 1
-#define TFA98XX_SYS_CONTROL1_MANAOOSC_MSK 0x10
-
-/*
- * man_enbl_brown_out
- */
-#define TFA98XX_SYS_CONTROL1_MANROBOD (0x1<<5)
-#define TFA98XX_SYS_CONTROL1_MANROBOD_POS 5
-#define TFA98XX_SYS_CONTROL1_MANROBOD_LEN 1
-#define TFA98XX_SYS_CONTROL1_MANROBOD_MAX 1
-#define TFA98XX_SYS_CONTROL1_MANROBOD_MSK 0x20
-
-/*
- * enbl_bod
- */
-#define TFA98XX_SYS_CONTROL1_BODE (0x1<<6)
-#define TFA98XX_SYS_CONTROL1_BODE_POS 6
-#define TFA98XX_SYS_CONTROL1_BODE_LEN 1
-#define TFA98XX_SYS_CONTROL1_BODE_MAX 1
-#define TFA98XX_SYS_CONTROL1_BODE_MSK 0x40
-
-/*
- * enbl_bod_hyst
- */
-#define TFA98XX_SYS_CONTROL1_BODHYS (0x1<<7)
-#define TFA98XX_SYS_CONTROL1_BODHYS_POS 7
-#define TFA98XX_SYS_CONTROL1_BODHYS_LEN 1
-#define TFA98XX_SYS_CONTROL1_BODHYS_MAX 1
-#define TFA98XX_SYS_CONTROL1_BODHYS_MSK 0x80
-
-/*
- * bod_delay
- */
-#define TFA98XX_SYS_CONTROL1_BODFILT (0x3<<8)
-#define TFA98XX_SYS_CONTROL1_BODFILT_POS 8
-#define TFA98XX_SYS_CONTROL1_BODFILT_LEN 2
-#define TFA98XX_SYS_CONTROL1_BODFILT_MAX 3
-#define TFA98XX_SYS_CONTROL1_BODFILT_MSK 0x300
-
-/*
- * bod_lvlsel
- */
-#define TFA98XX_SYS_CONTROL1_BODTHLVL (0x3<<10)
-#define TFA98XX_SYS_CONTROL1_BODTHLVL_POS 10
-#define TFA98XX_SYS_CONTROL1_BODTHLVL_LEN 2
-#define TFA98XX_SYS_CONTROL1_BODTHLVL_MAX 3
-#define TFA98XX_SYS_CONTROL1_BODTHLVL_MSK 0xc00
-
-/*
- * disable_mute_time_out
- */
-#define TFA98XX_SYS_CONTROL1_MUTETO (0x1<<13)
-#define TFA98XX_SYS_CONTROL1_MUTETO_POS 13
-#define TFA98XX_SYS_CONTROL1_MUTETO_LEN 1
-#define TFA98XX_SYS_CONTROL1_MUTETO_MAX 1
-#define TFA98XX_SYS_CONTROL1_MUTETO_MSK 0x2000
-
-/*
- * pwm_sel_rcv_ns
- */
-#define TFA98XX_SYS_CONTROL1_RCVNS (0x1<<14)
-#define TFA98XX_SYS_CONTROL1_RCVNS_POS 14
-#define TFA98XX_SYS_CONTROL1_RCVNS_LEN 1
-#define TFA98XX_SYS_CONTROL1_RCVNS_MAX 1
-#define TFA98XX_SYS_CONTROL1_RCVNS_MSK 0x4000
-
-/*
- * man_enbl_watchdog
- */
-#define TFA98XX_SYS_CONTROL1_MANWDE (0x1<<15)
-#define TFA98XX_SYS_CONTROL1_MANWDE_POS 15
-#define TFA98XX_SYS_CONTROL1_MANWDE_LEN 1
-#define TFA98XX_SYS_CONTROL1_MANWDE_MAX 1
-#define TFA98XX_SYS_CONTROL1_MANWDE_MSK 0x8000
-
-
-/*
- * (0x02)-sys_control2
- */
-
-/*
- * audio_fs
- */
-#define TFA98XX_SYS_CONTROL2_AUDFS (0xf<<0)
-#define TFA98XX_SYS_CONTROL2_AUDFS_POS 0
-#define TFA98XX_SYS_CONTROL2_AUDFS_LEN 4
-#define TFA98XX_SYS_CONTROL2_AUDFS_MAX 15
-#define TFA98XX_SYS_CONTROL2_AUDFS_MSK 0xf
-
-/*
- * input_level
- */
-#define TFA98XX_SYS_CONTROL2_INPLEV (0x1<<4)
-#define TFA98XX_SYS_CONTROL2_INPLEV_POS 4
-#define TFA98XX_SYS_CONTROL2_INPLEV_LEN 1
-#define TFA98XX_SYS_CONTROL2_INPLEV_MAX 1
-#define TFA98XX_SYS_CONTROL2_INPLEV_MSK 0x10
-
-/*
- * cs_frac_delay
- */
-#define TFA98XX_SYS_CONTROL2_FRACTDEL (0x3f<<5)
-#define TFA98XX_SYS_CONTROL2_FRACTDEL_POS 5
-#define TFA98XX_SYS_CONTROL2_FRACTDEL_LEN 6
-#define TFA98XX_SYS_CONTROL2_FRACTDEL_MAX 63
-#define TFA98XX_SYS_CONTROL2_FRACTDEL_MSK 0x7e0
-
-/*
- * bypass_hvbat_filter
- */
-#define TFA98XX_SYS_CONTROL2_BYPHVBF (0x1<<11)
-#define TFA98XX_SYS_CONTROL2_BYPHVBF_POS 11
-#define TFA98XX_SYS_CONTROL2_BYPHVBF_LEN 1
-#define TFA98XX_SYS_CONTROL2_BYPHVBF_MAX 1
-#define TFA98XX_SYS_CONTROL2_BYPHVBF_MSK 0x800
-
-/*
- * ctrl_rcvldop_bypass
- */
-#define TFA98XX_SYS_CONTROL2_LDOBYP (0x1<<12)
-#define TFA98XX_SYS_CONTROL2_LDOBYP_POS 12
-#define TFA98XX_SYS_CONTROL2_LDOBYP_LEN 1
-#define TFA98XX_SYS_CONTROL2_LDOBYP_MAX 1
-#define TFA98XX_SYS_CONTROL2_LDOBYP_MSK 0x1000
-
-
-/*
- * (0x03)-device_revision
- */
-
-/*
- * device_rev
- */
-#define TFA98XX_DEVICE_REVISION_REV (0xffff<<0)
-#define TFA98XX_DEVICE_REVISION_REV_POS 0
-#define TFA98XX_DEVICE_REVISION_REV_LEN 16
-#define TFA98XX_DEVICE_REVISION_REV_MAX 65535
-#define TFA98XX_DEVICE_REVISION_REV_MSK 0xffff
-
-
-/*
- * (0x04)-clock_control
- */
-
-/*
- * pll_clkin_sel
- */
-#define TFA98XX_CLOCK_CONTROL_REFCKEXT (0x3<<0)
-#define TFA98XX_CLOCK_CONTROL_REFCKEXT_POS 0
-#define TFA98XX_CLOCK_CONTROL_REFCKEXT_LEN 2
-#define TFA98XX_CLOCK_CONTROL_REFCKEXT_MAX 3
-#define TFA98XX_CLOCK_CONTROL_REFCKEXT_MSK 0x3
-
-/*
- * pll_clkin_sel_osc
- */
-#define TFA98XX_CLOCK_CONTROL_REFCKSEL (0x1<<2)
-#define TFA98XX_CLOCK_CONTROL_REFCKSEL_POS 2
-#define TFA98XX_CLOCK_CONTROL_REFCKSEL_LEN 1
-#define TFA98XX_CLOCK_CONTROL_REFCKSEL_MAX 1
-#define TFA98XX_CLOCK_CONTROL_REFCKSEL_MSK 0x4
-
-
-/*
- * (0x05)-clock_gating_control
- */
-
-/*
- * enbl_spkr_ss_left
- */
-#define TFA98XX_CLOCK_GATING_CONTROL_SSLEFTE (0x1<<0)
-#define TFA98XX_CLOCK_GATING_CONTROL_SSLEFTE_POS 0
-#define TFA98XX_CLOCK_GATING_CONTROL_SSLEFTE_LEN 1
-#define TFA98XX_CLOCK_GATING_CONTROL_SSLEFTE_MAX 1
-#define TFA98XX_CLOCK_GATING_CONTROL_SSLEFTE_MSK 0x1
-
-/*
- * enbl_spkr_ss_right
- */
-#define TFA98XX_CLOCK_GATING_CONTROL_SSRIGHTE (0x1<<1)
-#define TFA98XX_CLOCK_GATING_CONTROL_SSRIGHTE_POS 1
-#define TFA98XX_CLOCK_GATING_CONTROL_SSRIGHTE_LEN 1
-#define TFA98XX_CLOCK_GATING_CONTROL_SSRIGHTE_MAX 1
-#define TFA98XX_CLOCK_GATING_CONTROL_SSRIGHTE_MSK 0x2
-
-/*
- * enbl_volsense_left
- */
-#define TFA98XX_CLOCK_GATING_CONTROL_VSLEFTE (0x1<<2)
-#define TFA98XX_CLOCK_GATING_CONTROL_VSLEFTE_POS 2
-#define TFA98XX_CLOCK_GATING_CONTROL_VSLEFTE_LEN 1
-#define TFA98XX_CLOCK_GATING_CONTROL_VSLEFTE_MAX 1
-#define TFA98XX_CLOCK_GATING_CONTROL_VSLEFTE_MSK 0x4
-
-/*
- * enbl_volsense_right
- */
-#define TFA98XX_CLOCK_GATING_CONTROL_VSRIGHTE (0x1<<3)
-#define TFA98XX_CLOCK_GATING_CONTROL_VSRIGHTE_POS 3
-#define TFA98XX_CLOCK_GATING_CONTROL_VSRIGHTE_LEN 1
-#define TFA98XX_CLOCK_GATING_CONTROL_VSRIGHTE_MAX 1
-#define TFA98XX_CLOCK_GATING_CONTROL_VSRIGHTE_MSK 0x8
-
-/*
- * enbl_cursense_left
- */
-#define TFA98XX_CLOCK_GATING_CONTROL_CSLEFTE (0x1<<4)
-#define TFA98XX_CLOCK_GATING_CONTROL_CSLEFTE_POS 4
-#define TFA98XX_CLOCK_GATING_CONTROL_CSLEFTE_LEN 1
-#define TFA98XX_CLOCK_GATING_CONTROL_CSLEFTE_MAX 1
-#define TFA98XX_CLOCK_GATING_CONTROL_CSLEFTE_MSK 0x10
-
-/*
- * enbl_cursense_right
- */
-#define TFA98XX_CLOCK_GATING_CONTROL_CSRIGHTE (0x1<<5)
-#define TFA98XX_CLOCK_GATING_CONTROL_CSRIGHTE_POS 5
-#define TFA98XX_CLOCK_GATING_CONTROL_CSRIGHTE_LEN 1
-#define TFA98XX_CLOCK_GATING_CONTROL_CSRIGHTE_MAX 1
-#define TFA98XX_CLOCK_GATING_CONTROL_CSRIGHTE_MSK 0x20
-
-/*
- * enbl_pdm_ss
- */
-#define TFA98XX_CLOCK_GATING_CONTROL_SSPDME (0x1<<6)
-#define TFA98XX_CLOCK_GATING_CONTROL_SSPDME_POS 6
-#define TFA98XX_CLOCK_GATING_CONTROL_SSPDME_LEN 1
-#define TFA98XX_CLOCK_GATING_CONTROL_SSPDME_MAX 1
-#define TFA98XX_CLOCK_GATING_CONTROL_SSPDME_MSK 0x40
-
-
-/*
- * (0x0d)-side_tone_config
- */
-
-/*
- * side_tone_gain
- */
-#define TFA98XX_SIDE_TONE_CONFIG_STGAIN (0x1ff<<1)
-#define TFA98XX_SIDE_TONE_CONFIG_STGAIN_POS 1
-#define TFA98XX_SIDE_TONE_CONFIG_STGAIN_LEN 9
-#define TFA98XX_SIDE_TONE_CONFIG_STGAIN_MAX 511
-#define TFA98XX_SIDE_TONE_CONFIG_STGAIN_MSK 0x3fe
-
-/*
- * mute_side_tone
- */
-#define TFA98XX_SIDE_TONE_CONFIG_PDMSMUTE (0x1<<10)
-#define TFA98XX_SIDE_TONE_CONFIG_PDMSMUTE_POS 10
-#define TFA98XX_SIDE_TONE_CONFIG_PDMSMUTE_LEN 1
-#define TFA98XX_SIDE_TONE_CONFIG_PDMSMUTE_MAX 1
-#define TFA98XX_SIDE_TONE_CONFIG_PDMSMUTE_MSK 0x400
-
-
-/*
- * (0x0e)-ctrl_digtoana_reg
- */
-
-/*
- * ctrl_digtoana
- */
-#define TFA98XX_CTRL_DIGTOANA_REG_SWVSTEP (0x7f<<0)
-#define TFA98XX_CTRL_DIGTOANA_REG_SWVSTEP_POS 0
-#define TFA98XX_CTRL_DIGTOANA_REG_SWVSTEP_LEN 7
-#define TFA98XX_CTRL_DIGTOANA_REG_SWVSTEP_MAX 127
-#define TFA98XX_CTRL_DIGTOANA_REG_SWVSTEP_MSK 0x7f
-
-
-/*
- * (0x10)-status_flags0
- */
-
-/*
- * flag_por
- */
-#define TFA98XX_STATUS_FLAGS0_VDDS (0x1<<0)
-#define TFA98XX_STATUS_FLAGS0_VDDS_POS 0
-#define TFA98XX_STATUS_FLAGS0_VDDS_LEN 1
-#define TFA98XX_STATUS_FLAGS0_VDDS_MAX 1
-#define TFA98XX_STATUS_FLAGS0_VDDS_MSK 0x1
-
-/*
- * flag_pll_lock
- */
-#define TFA98XX_STATUS_FLAGS0_PLLS (0x1<<1)
-#define TFA98XX_STATUS_FLAGS0_PLLS_POS 1
-#define TFA98XX_STATUS_FLAGS0_PLLS_LEN 1
-#define TFA98XX_STATUS_FLAGS0_PLLS_MAX 1
-#define TFA98XX_STATUS_FLAGS0_PLLS_MSK 0x2
-
-/*
- * flag_otpok
- */
-#define TFA98XX_STATUS_FLAGS0_OTDS (0x1<<2)
-#define TFA98XX_STATUS_FLAGS0_OTDS_POS 2
-#define TFA98XX_STATUS_FLAGS0_OTDS_LEN 1
-#define TFA98XX_STATUS_FLAGS0_OTDS_MAX 1
-#define TFA98XX_STATUS_FLAGS0_OTDS_MSK 0x4
-
-/*
- * flag_ovpok
- */
-#define TFA98XX_STATUS_FLAGS0_OVDS (0x1<<3)
-#define TFA98XX_STATUS_FLAGS0_OVDS_POS 3
-#define TFA98XX_STATUS_FLAGS0_OVDS_LEN 1
-#define TFA98XX_STATUS_FLAGS0_OVDS_MAX 1
-#define TFA98XX_STATUS_FLAGS0_OVDS_MSK 0x8
-
-/*
- * flag_uvpok
- */
-#define TFA98XX_STATUS_FLAGS0_UVDS (0x1<<4)
-#define TFA98XX_STATUS_FLAGS0_UVDS_POS 4
-#define TFA98XX_STATUS_FLAGS0_UVDS_LEN 1
-#define TFA98XX_STATUS_FLAGS0_UVDS_MAX 1
-#define TFA98XX_STATUS_FLAGS0_UVDS_MSK 0x10
-
-/*
- * flag_clocks_stable
- */
-#define TFA98XX_STATUS_FLAGS0_CLKS (0x1<<6)
-#define TFA98XX_STATUS_FLAGS0_CLKS_POS 5
-#define TFA98XX_STATUS_FLAGS0_CLKS_LEN 1
-#define TFA98XX_STATUS_FLAGS0_CLKS_MAX 1
-#define TFA98XX_STATUS_FLAGS0_CLKS_MSK 0x20
-
-/*
- * flag_mtp_busy
- */
-#define TFA98XX_STATUS_FLAGS0_MTPB (0x1<<6)
-#define TFA98XX_STATUS_FLAGS0_MTPB_POS 6
-#define TFA98XX_STATUS_FLAGS0_MTPB_LEN 1
-#define TFA98XX_STATUS_FLAGS0_MTPB_MAX 1
-#define TFA98XX_STATUS_FLAGS0_MTPB_MSK 0x40
-
-/*
- * flag_lost_clk
- */
-#define TFA98XX_STATUS_FLAGS0_NOCLK (0x1<<7)
-#define TFA98XX_STATUS_FLAGS0_NOCLK_POS 7
-#define TFA98XX_STATUS_FLAGS0_NOCLK_LEN 1
-#define TFA98XX_STATUS_FLAGS0_NOCLK_MAX 1
-#define TFA98XX_STATUS_FLAGS0_NOCLK_MSK 0x80
-
-/*
- * flag_cf_speakererror
- */
-#define TFA98XX_STATUS_FLAGS0_SPKS (0x1<<8)
-#define TFA98XX_STATUS_FLAGS0_SPKS_POS 8
-#define TFA98XX_STATUS_FLAGS0_SPKS_LEN 1
-#define TFA98XX_STATUS_FLAGS0_SPKS_MAX 1
-#define TFA98XX_STATUS_FLAGS0_SPKS_MSK 0x100
-
-/*
- * flag_cold_started
- */
-#define TFA98XX_STATUS_FLAGS0_ACS (0x1<<9)
-#define TFA98XX_STATUS_FLAGS0_ACS_POS 9
-#define TFA98XX_STATUS_FLAGS0_ACS_LEN 1
-#define TFA98XX_STATUS_FLAGS0_ACS_MAX 1
-#define TFA98XX_STATUS_FLAGS0_ACS_MSK 0x200
-
-/*
- * flag_engage
- */
-#define TFA98XX_STATUS_FLAGS0_SWS (0x1<<10)
-#define TFA98XX_STATUS_FLAGS0_SWS_POS 10
-#define TFA98XX_STATUS_FLAGS0_SWS_LEN 1
-#define TFA98XX_STATUS_FLAGS0_SWS_MAX 1
-#define TFA98XX_STATUS_FLAGS0_SWS_MSK 0x400
-
-/*
- * flag_watchdog_reset
- */
-#define TFA98XX_STATUS_FLAGS0_WDS (0x1<<11)
-#define TFA98XX_STATUS_FLAGS0_WDS_POS 11
-#define TFA98XX_STATUS_FLAGS0_WDS_LEN 1
-#define TFA98XX_STATUS_FLAGS0_WDS_MAX 1
-#define TFA98XX_STATUS_FLAGS0_WDS_MSK 0x800
-
-/*
- * flag_enbl_amp
- */
-#define TFA98XX_STATUS_FLAGS0_AMPS (0x1<<12)
-#define TFA98XX_STATUS_FLAGS0_AMPS_POS 12
-#define TFA98XX_STATUS_FLAGS0_AMPS_LEN 1
-#define TFA98XX_STATUS_FLAGS0_AMPS_MAX 1
-#define TFA98XX_STATUS_FLAGS0_AMPS_MSK 0x1000
-
-/*
- * flag_enbl_ref
- */
-#define TFA98XX_STATUS_FLAGS0_AREFS (0x1<<13)
-#define TFA98XX_STATUS_FLAGS0_AREFS_POS 13
-#define TFA98XX_STATUS_FLAGS0_AREFS_LEN 1
-#define TFA98XX_STATUS_FLAGS0_AREFS_MAX 1
-#define TFA98XX_STATUS_FLAGS0_AREFS_MSK 0x2000
-
-/*
- * flag_adc10_ready
- */
-#define TFA98XX_STATUS_FLAGS0_ADCCR (0x1<<14)
-#define TFA98XX_STATUS_FLAGS0_ADCCR_POS 14
-#define TFA98XX_STATUS_FLAGS0_ADCCR_LEN 1
-#define TFA98XX_STATUS_FLAGS0_ADCCR_MAX 1
-#define TFA98XX_STATUS_FLAGS0_ADCCR_MSK 0x4000
-
-/*
- * flag_bod_vddd_nok
- */
-#define TFA98XX_STATUS_FLAGS0_BODNOK (0x1<<15)
-#define TFA98XX_STATUS_FLAGS0_BODNOK_POS 15
-#define TFA98XX_STATUS_FLAGS0_BODNOK_LEN 1
-#define TFA98XX_STATUS_FLAGS0_BODNOK_MAX 1
-#define TFA98XX_STATUS_FLAGS0_BODNOK_MSK 0x8000
-
-
-/*
- * (0x11)-status_flags1
- */
-
-/*
- * flag_bst_bstcur
- */
-#define TFA98XX_STATUS_FLAGS1_DCIL (0x1<<0)
-#define TFA98XX_STATUS_FLAGS1_DCIL_POS 0
-#define TFA98XX_STATUS_FLAGS1_DCIL_LEN 1
-#define TFA98XX_STATUS_FLAGS1_DCIL_MAX 1
-#define TFA98XX_STATUS_FLAGS1_DCIL_MSK 0x1
-
-/*
- * flag_bst_hiz
- */
-#define TFA98XX_STATUS_FLAGS1_DCDCA (0x1<<1)
-#define TFA98XX_STATUS_FLAGS1_DCDCA_POS 1
-#define TFA98XX_STATUS_FLAGS1_DCDCA_LEN 1
-#define TFA98XX_STATUS_FLAGS1_DCDCA_MAX 1
-#define TFA98XX_STATUS_FLAGS1_DCDCA_MSK 0x2
-
-/*
- * flag_bst_ocpok
- */
-#define TFA98XX_STATUS_FLAGS1_DCOCPOK (0x1<<2)
-#define TFA98XX_STATUS_FLAGS1_DCOCPOK_POS 2
-#define TFA98XX_STATUS_FLAGS1_DCOCPOK_LEN 1
-#define TFA98XX_STATUS_FLAGS1_DCOCPOK_MAX 1
-#define TFA98XX_STATUS_FLAGS1_DCOCPOK_MSK 0x4
-
-/*
- * flag_bst_voutcomp
- */
-#define TFA98XX_STATUS_FLAGS1_DCHVBAT (0x1<<4)
-#define TFA98XX_STATUS_FLAGS1_DCHVBAT_POS 4
-#define TFA98XX_STATUS_FLAGS1_DCHVBAT_LEN 1
-#define TFA98XX_STATUS_FLAGS1_DCHVBAT_MAX 1
-#define TFA98XX_STATUS_FLAGS1_DCHVBAT_MSK 0x10
-
-/*
- * flag_bst_voutcomp86
- */
-#define TFA98XX_STATUS_FLAGS1_DCH114 (0x1<<5)
-#define TFA98XX_STATUS_FLAGS1_DCH114_POS 5
-#define TFA98XX_STATUS_FLAGS1_DCH114_LEN 1
-#define TFA98XX_STATUS_FLAGS1_DCH114_MAX 1
-#define TFA98XX_STATUS_FLAGS1_DCH114_MSK 0x20
-
-/*
- * flag_bst_voutcomp93
- */
-#define TFA98XX_STATUS_FLAGS1_DCH107 (0x1<<6)
-#define TFA98XX_STATUS_FLAGS1_DCH107_POS 6
-#define TFA98XX_STATUS_FLAGS1_DCH107_LEN 1
-#define TFA98XX_STATUS_FLAGS1_DCH107_MAX 1
-#define TFA98XX_STATUS_FLAGS1_DCH107_MSK 0x40
-
-/*
- * flag_soft_mute_busy
- */
-#define TFA98XX_STATUS_FLAGS1_STMUTEB (0x1<<7)
-#define TFA98XX_STATUS_FLAGS1_STMUTEB_POS 7
-#define TFA98XX_STATUS_FLAGS1_STMUTEB_LEN 1
-#define TFA98XX_STATUS_FLAGS1_STMUTEB_MAX 1
-#define TFA98XX_STATUS_FLAGS1_STMUTEB_MSK 0x80
-
-/*
- * flag_soft_mute_state
- */
-#define TFA98XX_STATUS_FLAGS1_STMUTE (0x1<<8)
-#define TFA98XX_STATUS_FLAGS1_STMUTE_POS 8
-#define TFA98XX_STATUS_FLAGS1_STMUTE_LEN 1
-#define TFA98XX_STATUS_FLAGS1_STMUTE_MAX 1
-#define TFA98XX_STATUS_FLAGS1_STMUTE_MSK 0x100
-
-/*
- * flag_tdm_lut_error
- */
-#define TFA98XX_STATUS_FLAGS1_TDMLUTER (0x1<<9)
-#define TFA98XX_STATUS_FLAGS1_TDMLUTER_POS 9
-#define TFA98XX_STATUS_FLAGS1_TDMLUTER_LEN 1
-#define TFA98XX_STATUS_FLAGS1_TDMLUTER_MAX 1
-#define TFA98XX_STATUS_FLAGS1_TDMLUTER_MSK 0x200
-
-/*
- * flag_tdm_status
- */
-#define TFA98XX_STATUS_FLAGS1_TDMSTAT (0x7<<10)
-#define TFA98XX_STATUS_FLAGS1_TDMSTAT_POS 10
-#define TFA98XX_STATUS_FLAGS1_TDMSTAT_LEN 3
-#define TFA98XX_STATUS_FLAGS1_TDMSTAT_MAX 7
-#define TFA98XX_STATUS_FLAGS1_TDMSTAT_MSK 0x1c00
-
-/*
- * flag_tdm_error
- */
-#define TFA98XX_STATUS_FLAGS1_TDMERR (0x1<<13)
-#define TFA98XX_STATUS_FLAGS1_TDMERR_POS 13
-#define TFA98XX_STATUS_FLAGS1_TDMERR_LEN 1
-#define TFA98XX_STATUS_FLAGS1_TDMERR_MAX 1
-#define TFA98XX_STATUS_FLAGS1_TDMERR_MSK 0x2000
-
-/*
- * flag_haptic_busy
- */
-#define TFA98XX_STATUS_FLAGS1_HAPTIC (0x1<<14)
-#define TFA98XX_STATUS_FLAGS1_HAPTIC_POS 14
-#define TFA98XX_STATUS_FLAGS1_HAPTIC_LEN 1
-#define TFA98XX_STATUS_FLAGS1_HAPTIC_MAX 1
-#define TFA98XX_STATUS_FLAGS1_HAPTIC_MSK 0x4000
-
-
-/*
- * (0x12)-status_flags2
- */
-
-/*
- * flag_ocpokap_left
- */
-#define TFA98XX_STATUS_FLAGS2_OCPOAPL (0x1<<0)
-#define TFA98XX_STATUS_FLAGS2_OCPOAPL_POS 0
-#define TFA98XX_STATUS_FLAGS2_OCPOAPL_LEN 1
-#define TFA98XX_STATUS_FLAGS2_OCPOAPL_MAX 1
-#define TFA98XX_STATUS_FLAGS2_OCPOAPL_MSK 0x1
-
-/*
- * flag_ocpokan_left
- */
-#define TFA98XX_STATUS_FLAGS2_OCPOANL (0x1<<1)
-#define TFA98XX_STATUS_FLAGS2_OCPOANL_POS 1
-#define TFA98XX_STATUS_FLAGS2_OCPOANL_LEN 1
-#define TFA98XX_STATUS_FLAGS2_OCPOANL_MAX 1
-#define TFA98XX_STATUS_FLAGS2_OCPOANL_MSK 0x2
-
-/*
- * flag_ocpokbp_left
- */
-#define TFA98XX_STATUS_FLAGS2_OCPOBPL (0x1<<2)
-#define TFA98XX_STATUS_FLAGS2_OCPOBPL_POS 2
-#define TFA98XX_STATUS_FLAGS2_OCPOBPL_LEN 1
-#define TFA98XX_STATUS_FLAGS2_OCPOBPL_MAX 1
-#define TFA98XX_STATUS_FLAGS2_OCPOBPL_MSK 0x4
-
-/*
- * flag_ocpokbn_left
- */
-#define TFA98XX_STATUS_FLAGS2_OCPOBNL (0x1<<3)
-#define TFA98XX_STATUS_FLAGS2_OCPOBNL_POS 3
-#define TFA98XX_STATUS_FLAGS2_OCPOBNL_LEN 1
-#define TFA98XX_STATUS_FLAGS2_OCPOBNL_MAX 1
-#define TFA98XX_STATUS_FLAGS2_OCPOBNL_MSK 0x8
-
-/*
- * flag_clipa_high_left
- */
-#define TFA98XX_STATUS_FLAGS2_CLIPAHL (0x1<<4)
-#define TFA98XX_STATUS_FLAGS2_CLIPAHL_POS 4
-#define TFA98XX_STATUS_FLAGS2_CLIPAHL_LEN 1
-#define TFA98XX_STATUS_FLAGS2_CLIPAHL_MAX 1
-#define TFA98XX_STATUS_FLAGS2_CLIPAHL_MSK 0x10
-
-/*
- * flag_clipa_low_left
- */
-#define TFA98XX_STATUS_FLAGS2_CLIPALL (0x1<<5)
-#define TFA98XX_STATUS_FLAGS2_CLIPALL_POS 5
-#define TFA98XX_STATUS_FLAGS2_CLIPALL_LEN 1
-#define TFA98XX_STATUS_FLAGS2_CLIPALL_MAX 1
-#define TFA98XX_STATUS_FLAGS2_CLIPALL_MSK 0x20
-
-/*
- * flag_clipb_high_left
- */
-#define TFA98XX_STATUS_FLAGS2_CLIPBHL (0x1<<6)
-#define TFA98XX_STATUS_FLAGS2_CLIPBHL_POS 6
-#define TFA98XX_STATUS_FLAGS2_CLIPBHL_LEN 1
-#define TFA98XX_STATUS_FLAGS2_CLIPBHL_MAX 1
-#define TFA98XX_STATUS_FLAGS2_CLIPBHL_MSK 0x40
-
-/*
- * flag_clipb_low_left
- */
-#define TFA98XX_STATUS_FLAGS2_CLIPBLL (0x1<<7)
-#define TFA98XX_STATUS_FLAGS2_CLIPBLL_POS 7
-#define TFA98XX_STATUS_FLAGS2_CLIPBLL_LEN 1
-#define TFA98XX_STATUS_FLAGS2_CLIPBLL_MAX 1
-#define TFA98XX_STATUS_FLAGS2_CLIPBLL_MSK 0x80
-
-/*
- * flag_ocpokap_rcv
- */
-#define TFA98XX_STATUS_FLAGS2_OCPOAPRC (0x1<<8)
-#define TFA98XX_STATUS_FLAGS2_OCPOAPRC_POS 8
-#define TFA98XX_STATUS_FLAGS2_OCPOAPRC_LEN 1
-#define TFA98XX_STATUS_FLAGS2_OCPOAPRC_MAX 1
-#define TFA98XX_STATUS_FLAGS2_OCPOAPRC_MSK 0x100
-
-/*
- * flag_ocpokan_rcv
- */
-#define TFA98XX_STATUS_FLAGS2_OCPOANRC (0x1<<9)
-#define TFA98XX_STATUS_FLAGS2_OCPOANRC_POS 9
-#define TFA98XX_STATUS_FLAGS2_OCPOANRC_LEN 1
-#define TFA98XX_STATUS_FLAGS2_OCPOANRC_MAX 1
-#define TFA98XX_STATUS_FLAGS2_OCPOANRC_MSK 0x200
-
-/*
- * flag_ocpokbp_rcv
- */
-#define TFA98XX_STATUS_FLAGS2_OCPOBPRC (0x1<<10)
-#define TFA98XX_STATUS_FLAGS2_OCPOBPRC_POS 10
-#define TFA98XX_STATUS_FLAGS2_OCPOBPRC_LEN 1
-#define TFA98XX_STATUS_FLAGS2_OCPOBPRC_MAX 1
-#define TFA98XX_STATUS_FLAGS2_OCPOBPRC_MSK 0x400
-
-/*
- * flag_ocpokbn_rcv
- */
-#define TFA98XX_STATUS_FLAGS2_OCPOBNRC (0x1<<11)
-#define TFA98XX_STATUS_FLAGS2_OCPOBNRC_POS 11
-#define TFA98XX_STATUS_FLAGS2_OCPOBNRC_LEN 1
-#define TFA98XX_STATUS_FLAGS2_OCPOBNRC_MAX 1
-#define TFA98XX_STATUS_FLAGS2_OCPOBNRC_MSK 0x800
-
-/*
- * flag_rcvldop_ready
- */
-#define TFA98XX_STATUS_FLAGS2_RCVLDOR (0x1<<12)
-#define TFA98XX_STATUS_FLAGS2_RCVLDOR_POS 12
-#define TFA98XX_STATUS_FLAGS2_RCVLDOR_LEN 1
-#define TFA98XX_STATUS_FLAGS2_RCVLDOR_MAX 1
-#define TFA98XX_STATUS_FLAGS2_RCVLDOR_MSK 0x1000
-
-/*
- * flag_rcvldop_bypassready
- */
-#define TFA98XX_STATUS_FLAGS2_RCVLDOBR (0x1<<13)
-#define TFA98XX_STATUS_FLAGS2_RCVLDOBR_POS 13
-#define TFA98XX_STATUS_FLAGS2_RCVLDOBR_LEN 1
-#define TFA98XX_STATUS_FLAGS2_RCVLDOBR_MAX 1
-#define TFA98XX_STATUS_FLAGS2_RCVLDOBR_MSK 0x2000
-
-/*
- * flag_ocp_alarm_left
- */
-#define TFA98XX_STATUS_FLAGS2_OCDSL (0x1<<14)
-#define TFA98XX_STATUS_FLAGS2_OCDSL_POS 14
-#define TFA98XX_STATUS_FLAGS2_OCDSL_LEN 1
-#define TFA98XX_STATUS_FLAGS2_OCDSL_MAX 1
-#define TFA98XX_STATUS_FLAGS2_OCDSL_MSK 0x4000
-
-/*
- * flag_clip_left
- */
-#define TFA98XX_STATUS_FLAGS2_CLIPSL (0x1<<15)
-#define TFA98XX_STATUS_FLAGS2_CLIPSL_POS 15
-#define TFA98XX_STATUS_FLAGS2_CLIPSL_LEN 1
-#define TFA98XX_STATUS_FLAGS2_CLIPSL_MAX 1
-#define TFA98XX_STATUS_FLAGS2_CLIPSL_MSK 0x8000
-
-
-/*
- * (0x13)-status_flags3
- */
-
-/*
- * flag_ocpokap_right
- */
-#define TFA98XX_STATUS_FLAGS3_OCPOAPR (0x1<<0)
-#define TFA98XX_STATUS_FLAGS3_OCPOAPR_POS 0
-#define TFA98XX_STATUS_FLAGS3_OCPOAPR_LEN 1
-#define TFA98XX_STATUS_FLAGS3_OCPOAPR_MAX 1
-#define TFA98XX_STATUS_FLAGS3_OCPOAPR_MSK 0x1
-
-/*
- * flag_ocpokan_right
- */
-#define TFA98XX_STATUS_FLAGS3_OCPOANR (0x1<<1)
-#define TFA98XX_STATUS_FLAGS3_OCPOANR_POS 1
-#define TFA98XX_STATUS_FLAGS3_OCPOANR_LEN 1
-#define TFA98XX_STATUS_FLAGS3_OCPOANR_MAX 1
-#define TFA98XX_STATUS_FLAGS3_OCPOANR_MSK 0x2
-
-/*
- * flag_ocpokbp_right
- */
-#define TFA98XX_STATUS_FLAGS3_OCPOBPR (0x1<<2)
-#define TFA98XX_STATUS_FLAGS3_OCPOBPR_POS 2
-#define TFA98XX_STATUS_FLAGS3_OCPOBPR_LEN 1
-#define TFA98XX_STATUS_FLAGS3_OCPOBPR_MAX 1
-#define TFA98XX_STATUS_FLAGS3_OCPOBPR_MSK 0x4
-
-/*
- * flag_ocpokbn_right
- */
-#define TFA98XX_STATUS_FLAGS3_OCPOBNR (0x1<<3)
-#define TFA98XX_STATUS_FLAGS3_OCPOBNR_POS 3
-#define TFA98XX_STATUS_FLAGS3_OCPOBNR_LEN 1
-#define TFA98XX_STATUS_FLAGS3_OCPOBNR_MAX 1
-#define TFA98XX_STATUS_FLAGS3_OCPOBNR_MSK 0x8
-
-/*
- * flag_clipa_high_right
- */
-#define TFA98XX_STATUS_FLAGS3_CLIPAHR (0x1<<4)
-#define TFA98XX_STATUS_FLAGS3_CLIPAHR_POS 4
-#define TFA98XX_STATUS_FLAGS3_CLIPAHR_LEN 1
-#define TFA98XX_STATUS_FLAGS3_CLIPAHR_MAX 1
-#define TFA98XX_STATUS_FLAGS3_CLIPAHR_MSK 0x10
-
-/*
- * flag_clipa_low_right
- */
-#define TFA98XX_STATUS_FLAGS3_CLIPALR (0x1<<5)
-#define TFA98XX_STATUS_FLAGS3_CLIPALR_POS 5
-#define TFA98XX_STATUS_FLAGS3_CLIPALR_LEN 1
-#define TFA98XX_STATUS_FLAGS3_CLIPALR_MAX 1
-#define TFA98XX_STATUS_FLAGS3_CLIPALR_MSK 0x20
-
-/*
- * flag_clipb_high_right
- */
-#define TFA98XX_STATUS_FLAGS3_CLIPBHR (0x1<<6)
-#define TFA98XX_STATUS_FLAGS3_CLIPBHR_POS 6
-#define TFA98XX_STATUS_FLAGS3_CLIPBHR_LEN 1
-#define TFA98XX_STATUS_FLAGS3_CLIPBHR_MAX 1
-#define TFA98XX_STATUS_FLAGS3_CLIPBHR_MSK 0x40
-
-/*
- * flag_clipb_low_right
- */
-#define TFA98XX_STATUS_FLAGS3_CLIPBLR (0x1<<7)
-#define TFA98XX_STATUS_FLAGS3_CLIPBLR_POS 7
-#define TFA98XX_STATUS_FLAGS3_CLIPBLR_LEN 1
-#define TFA98XX_STATUS_FLAGS3_CLIPBLR_MAX 1
-#define TFA98XX_STATUS_FLAGS3_CLIPBLR_MSK 0x80
-
-/*
- * flag_ocp_alarm_right
- */
-#define TFA98XX_STATUS_FLAGS3_OCDSR (0x1<<8)
-#define TFA98XX_STATUS_FLAGS3_OCDSR_POS 8
-#define TFA98XX_STATUS_FLAGS3_OCDSR_LEN 1
-#define TFA98XX_STATUS_FLAGS3_OCDSR_MAX 1
-#define TFA98XX_STATUS_FLAGS3_OCDSR_MSK 0x100
-
-/*
- * flag_clip_right
- */
-#define TFA98XX_STATUS_FLAGS3_CLIPSR (0x1<<9)
-#define TFA98XX_STATUS_FLAGS3_CLIPSR_POS 9
-#define TFA98XX_STATUS_FLAGS3_CLIPSR_LEN 1
-#define TFA98XX_STATUS_FLAGS3_CLIPSR_MAX 1
-#define TFA98XX_STATUS_FLAGS3_CLIPSR_MSK 0x200
-
-/*
- * flag_mic_ocpok
- */
-#define TFA98XX_STATUS_FLAGS3_OCPOKMC (0x1<<10)
-#define TFA98XX_STATUS_FLAGS3_OCPOKMC_POS 10
-#define TFA98XX_STATUS_FLAGS3_OCPOKMC_LEN 1
-#define TFA98XX_STATUS_FLAGS3_OCPOKMC_MAX 1
-#define TFA98XX_STATUS_FLAGS3_OCPOKMC_MSK 0x400
-
-/*
- * flag_man_alarm_state
- */
-#define TFA98XX_STATUS_FLAGS3_MANALARM (0x1<<11)
-#define TFA98XX_STATUS_FLAGS3_MANALARM_POS 11
-#define TFA98XX_STATUS_FLAGS3_MANALARM_LEN 1
-#define TFA98XX_STATUS_FLAGS3_MANALARM_MAX 1
-#define TFA98XX_STATUS_FLAGS3_MANALARM_MSK 0x800
-
-/*
- * flag_man_wait_src_settings
- */
-#define TFA98XX_STATUS_FLAGS3_MANWAIT1 (0x1<<12)
-#define TFA98XX_STATUS_FLAGS3_MANWAIT1_POS 12
-#define TFA98XX_STATUS_FLAGS3_MANWAIT1_LEN 1
-#define TFA98XX_STATUS_FLAGS3_MANWAIT1_MAX 1
-#define TFA98XX_STATUS_FLAGS3_MANWAIT1_MSK 0x1000
-
-/*
- * flag_man_wait_cf_config
- */
-#define TFA98XX_STATUS_FLAGS3_MANWAIT2 (0x1<<13)
-#define TFA98XX_STATUS_FLAGS3_MANWAIT2_POS 13
-#define TFA98XX_STATUS_FLAGS3_MANWAIT2_LEN 1
-#define TFA98XX_STATUS_FLAGS3_MANWAIT2_MAX 1
-#define TFA98XX_STATUS_FLAGS3_MANWAIT2_MSK 0x2000
-
-/*
- * flag_man_start_mute_audio
- */
-#define TFA98XX_STATUS_FLAGS3_MANMUTE (0x1<<14)
-#define TFA98XX_STATUS_FLAGS3_MANMUTE_POS 14
-#define TFA98XX_STATUS_FLAGS3_MANMUTE_LEN 1
-#define TFA98XX_STATUS_FLAGS3_MANMUTE_MAX 1
-#define TFA98XX_STATUS_FLAGS3_MANMUTE_MSK 0x4000
-
-/*
- * flag_man_operating_state
- */
-#define TFA98XX_STATUS_FLAGS3_MANOPER (0x1<<15)
-#define TFA98XX_STATUS_FLAGS3_MANOPER_POS 15
-#define TFA98XX_STATUS_FLAGS3_MANOPER_LEN 1
-#define TFA98XX_STATUS_FLAGS3_MANOPER_MAX 1
-#define TFA98XX_STATUS_FLAGS3_MANOPER_MSK 0x8000
-
-
-/*
- * (0x14)-status_flags4
- */
-
-/*
- * flag_cf_speakererror_left
- */
-#define TFA98XX_STATUS_FLAGS4_SPKSL (0x1<<0)
-#define TFA98XX_STATUS_FLAGS4_SPKSL_POS 0
-#define TFA98XX_STATUS_FLAGS4_SPKSL_LEN 1
-#define TFA98XX_STATUS_FLAGS4_SPKSL_MAX 1
-#define TFA98XX_STATUS_FLAGS4_SPKSL_MSK 0x1
-
-/*
- * flag_cf_speakererror_right
- */
-#define TFA98XX_STATUS_FLAGS4_SPKSR (0x1<<1)
-#define TFA98XX_STATUS_FLAGS4_SPKSR_POS 1
-#define TFA98XX_STATUS_FLAGS4_SPKSR_LEN 1
-#define TFA98XX_STATUS_FLAGS4_SPKSR_MAX 1
-#define TFA98XX_STATUS_FLAGS4_SPKSR_MSK 0x2
-
-/*
- * flag_clk_out_of_range
- */
-#define TFA98XX_STATUS_FLAGS4_CLKOOR (0x1<<2)
-#define TFA98XX_STATUS_FLAGS4_CLKOOR_POS 2
-#define TFA98XX_STATUS_FLAGS4_CLKOOR_LEN 1
-#define TFA98XX_STATUS_FLAGS4_CLKOOR_MAX 1
-#define TFA98XX_STATUS_FLAGS4_CLKOOR_MSK 0x4
-
-/*
- * man_state
- */
-#define TFA98XX_STATUS_FLAGS4_MANSTATE (0xf<<3)
-#define TFA98XX_STATUS_FLAGS4_MANSTATE_POS 3
-#define TFA98XX_STATUS_FLAGS4_MANSTATE_LEN 4
-#define TFA98XX_STATUS_FLAGS4_MANSTATE_MAX 15
-#define TFA98XX_STATUS_FLAGS4_MANSTATE_MSK 0x78
-
-
-/*
- * (0x15)-battery_voltage
- */
-
-/*
- * bat_adc
- */
-#define TFA98XX_BATTERY_VOLTAGE_BATS (0x3ff<<0)
-#define TFA98XX_BATTERY_VOLTAGE_BATS_POS 0
-#define TFA98XX_BATTERY_VOLTAGE_BATS_LEN 10
-#define TFA98XX_BATTERY_VOLTAGE_BATS_MAX 1023
-#define TFA98XX_BATTERY_VOLTAGE_BATS_MSK 0x3ff
-
-
-/*
- * (0x16)-temperature
- */
-
-/*
- * temp_adc
- */
-#define TFA98XX_TEMPERATURE_TEMPS (0x1ff<<0)
-#define TFA98XX_TEMPERATURE_TEMPS_POS 0
-#define TFA98XX_TEMPERATURE_TEMPS_LEN 9
-#define TFA98XX_TEMPERATURE_TEMPS_MAX 511
-#define TFA98XX_TEMPERATURE_TEMPS_MSK 0x1ff
-
-
-/*
- * (0x20)-tdm_config0
- */
-
-/*
- * tdm_usecase
- */
-#define TFA98XX_TDM_CONFIG0_TDMUC (0xf<<0)
-#define TFA98XX_TDM_CONFIG0_TDMUC_POS 0
-#define TFA98XX_TDM_CONFIG0_TDMUC_LEN 4
-#define TFA98XX_TDM_CONFIG0_TDMUC_MAX 15
-#define TFA98XX_TDM_CONFIG0_TDMUC_MSK 0xf
-
-/*
- * tdm_enable
- */
-#define TFA98XX_TDM_CONFIG0_TDME (0x1<<4)
-#define TFA98XX_TDM_CONFIG0_TDME_POS 4
-#define TFA98XX_TDM_CONFIG0_TDME_LEN 1
-#define TFA98XX_TDM_CONFIG0_TDME_MAX 1
-#define TFA98XX_TDM_CONFIG0_TDME_MSK 0x10
-
-/*
- * tdm_mode
- */
-#define TFA98XX_TDM_CONFIG0_TDMMODE (0x1<<5)
-#define TFA98XX_TDM_CONFIG0_TDMMODE_POS 5
-#define TFA98XX_TDM_CONFIG0_TDMMODE_LEN 1
-#define TFA98XX_TDM_CONFIG0_TDMMODE_MAX 1
-#define TFA98XX_TDM_CONFIG0_TDMMODE_MSK 0x20
-
-/*
- * tdm_clk_inversion
- */
-#define TFA98XX_TDM_CONFIG0_TDMCLINV (0x1<<6)
-#define TFA98XX_TDM_CONFIG0_TDMCLINV_POS 6
-#define TFA98XX_TDM_CONFIG0_TDMCLINV_LEN 1
-#define TFA98XX_TDM_CONFIG0_TDMCLINV_MAX 1
-#define TFA98XX_TDM_CONFIG0_TDMCLINV_MSK 0x40
-
-/*
- * tdm_fs_ws_length
- */
-#define TFA98XX_TDM_CONFIG0_TDMFSLN (0xf<<7)
-#define TFA98XX_TDM_CONFIG0_TDMFSLN_POS 7
-#define TFA98XX_TDM_CONFIG0_TDMFSLN_LEN 4
-#define TFA98XX_TDM_CONFIG0_TDMFSLN_MAX 15
-#define TFA98XX_TDM_CONFIG0_TDMFSLN_MSK 0x780
-
-/*
- * tdm_fs_ws_polarity
- */
-#define TFA98XX_TDM_CONFIG0_TDMFSPOL (0x1<<11)
-#define TFA98XX_TDM_CONFIG0_TDMFSPOL_POS 11
-#define TFA98XX_TDM_CONFIG0_TDMFSPOL_LEN 1
-#define TFA98XX_TDM_CONFIG0_TDMFSPOL_MAX 1
-#define TFA98XX_TDM_CONFIG0_TDMFSPOL_MSK 0x800
-
-/*
- * tdm_nbck
- */
-#define TFA98XX_TDM_CONFIG0_TDMNBCK (0xf<<12)
-#define TFA98XX_TDM_CONFIG0_TDMNBCK_POS 12
-#define TFA98XX_TDM_CONFIG0_TDMNBCK_LEN 4
-#define TFA98XX_TDM_CONFIG0_TDMNBCK_MAX 15
-#define TFA98XX_TDM_CONFIG0_TDMNBCK_MSK 0xf000
-
-
-/*
- * (0x21)-tdm_config1
- */
-
-/*
- * tdm_nb_of_slots
- */
-#define TFA98XX_TDM_CONFIG1_TDMSLOTS (0xf<<0)
-#define TFA98XX_TDM_CONFIG1_TDMSLOTS_POS 0
-#define TFA98XX_TDM_CONFIG1_TDMSLOTS_LEN 4
-#define TFA98XX_TDM_CONFIG1_TDMSLOTS_MAX 15
-#define TFA98XX_TDM_CONFIG1_TDMSLOTS_MSK 0xf
-
-/*
- * tdm_slot_length
- */
-#define TFA98XX_TDM_CONFIG1_TDMSLLN (0x1f<<4)
-#define TFA98XX_TDM_CONFIG1_TDMSLLN_POS 4
-#define TFA98XX_TDM_CONFIG1_TDMSLLN_LEN 5
-#define TFA98XX_TDM_CONFIG1_TDMSLLN_MAX 31
-#define TFA98XX_TDM_CONFIG1_TDMSLLN_MSK 0x1f0
-
-/*
- * tdm_bits_remaining
- */
-#define TFA98XX_TDM_CONFIG1_TDMBRMG (0x1f<<9)
-#define TFA98XX_TDM_CONFIG1_TDMBRMG_POS 9
-#define TFA98XX_TDM_CONFIG1_TDMBRMG_LEN 5
-#define TFA98XX_TDM_CONFIG1_TDMBRMG_MAX 31
-#define TFA98XX_TDM_CONFIG1_TDMBRMG_MSK 0x3e00
-
-/*
- * tdm_data_delay
- */
-#define TFA98XX_TDM_CONFIG1_TDMDEL (0x1<<14)
-#define TFA98XX_TDM_CONFIG1_TDMDEL_POS 14
-#define TFA98XX_TDM_CONFIG1_TDMDEL_LEN 1
-#define TFA98XX_TDM_CONFIG1_TDMDEL_MAX 1
-#define TFA98XX_TDM_CONFIG1_TDMDEL_MSK 0x4000
-
-/*
- * tdm_data_adjustment
- */
-#define TFA98XX_TDM_CONFIG1_TDMADJ (0x1<<15)
-#define TFA98XX_TDM_CONFIG1_TDMADJ_POS 15
-#define TFA98XX_TDM_CONFIG1_TDMADJ_LEN 1
-#define TFA98XX_TDM_CONFIG1_TDMADJ_MAX 1
-#define TFA98XX_TDM_CONFIG1_TDMADJ_MSK 0x8000
-
-
-/*
- * (0x22)-tdm_config2
- */
-
-/*
- * tdm_audio_sample_compression
- */
-#define TFA98XX_TDM_CONFIG2_TDMOOMP (0x3<<0)
-#define TFA98XX_TDM_CONFIG2_TDMOOMP_POS 0
-#define TFA98XX_TDM_CONFIG2_TDMOOMP_LEN 2
-#define TFA98XX_TDM_CONFIG2_TDMOOMP_MAX 3
-#define TFA98XX_TDM_CONFIG2_TDMOOMP_MSK 0x3
-
-/*
- * tdm_sample_size
- */
-#define TFA98XX_TDM_CONFIG2_TDMSSIZE (0x1f<<2)
-#define TFA98XX_TDM_CONFIG2_TDMSSIZE_POS 2
-#define TFA98XX_TDM_CONFIG2_TDMSSIZE_LEN 5
-#define TFA98XX_TDM_CONFIG2_TDMSSIZE_MAX 31
-#define TFA98XX_TDM_CONFIG2_TDMSSIZE_MSK 0x7c
-
-/*
- * tdm_txdata_format
- */
-#define TFA98XX_TDM_CONFIG2_TDMTXDFO (0x3<<7)
-#define TFA98XX_TDM_CONFIG2_TDMTXDFO_POS 7
-#define TFA98XX_TDM_CONFIG2_TDMTXDFO_LEN 2
-#define TFA98XX_TDM_CONFIG2_TDMTXDFO_MAX 3
-#define TFA98XX_TDM_CONFIG2_TDMTXDFO_MSK 0x180
-
-/*
- * tdm_txdata_format_unused_slot_sd0
- */
-#define TFA98XX_TDM_CONFIG2_TDMTXUS0 (0x3<<9)
-#define TFA98XX_TDM_CONFIG2_TDMTXUS0_POS 9
-#define TFA98XX_TDM_CONFIG2_TDMTXUS0_LEN 2
-#define TFA98XX_TDM_CONFIG2_TDMTXUS0_MAX 3
-#define TFA98XX_TDM_CONFIG2_TDMTXUS0_MSK 0x600
-
-/*
- * tdm_txdata_format_unused_slot_sd1
- */
-#define TFA98XX_TDM_CONFIG2_TDMTXUS1 (0x3<<11)
-#define TFA98XX_TDM_CONFIG2_TDMTXUS1_POS 11
-#define TFA98XX_TDM_CONFIG2_TDMTXUS1_LEN 2
-#define TFA98XX_TDM_CONFIG2_TDMTXUS1_MAX 3
-#define TFA98XX_TDM_CONFIG2_TDMTXUS1_MSK 0x1800
-
-/*
- * tdm_txdata_format_unused_slot_sd2
- */
-#define TFA98XX_TDM_CONFIG2_TDMTXUS2 (0x3<<13)
-#define TFA98XX_TDM_CONFIG2_TDMTXUS2_POS 13
-#define TFA98XX_TDM_CONFIG2_TDMTXUS2_LEN 2
-#define TFA98XX_TDM_CONFIG2_TDMTXUS2_MAX 3
-#define TFA98XX_TDM_CONFIG2_TDMTXUS2_MSK 0x6000
-
-
-/*
- * (0x23)-tdm_config3
- */
-
-/*
- * tdm_sink1_enable
- */
-#define TFA98XX_TDM_CONFIG3_TDMLE (0x1<<1)
-#define TFA98XX_TDM_CONFIG3_TDMLE_POS 1
-#define TFA98XX_TDM_CONFIG3_TDMLE_LEN 1
-#define TFA98XX_TDM_CONFIG3_TDMLE_MAX 1
-#define TFA98XX_TDM_CONFIG3_TDMLE_MSK 0x2
-
-/*
- * tdm_sink2_enable
- */
-#define TFA98XX_TDM_CONFIG3_TDMRE (0x1<<2)
-#define TFA98XX_TDM_CONFIG3_TDMRE_POS 2
-#define TFA98XX_TDM_CONFIG3_TDMRE_LEN 1
-#define TFA98XX_TDM_CONFIG3_TDMRE_MAX 1
-#define TFA98XX_TDM_CONFIG3_TDMRE_MSK 0x4
-
-/*
- * tdm_source1_enable
- */
-#define TFA98XX_TDM_CONFIG3_TDMVSRE (0x1<<4)
-#define TFA98XX_TDM_CONFIG3_TDMVSRE_POS 4
-#define TFA98XX_TDM_CONFIG3_TDMVSRE_LEN 1
-#define TFA98XX_TDM_CONFIG3_TDMVSRE_MAX 1
-#define TFA98XX_TDM_CONFIG3_TDMVSRE_MSK 0x10
-
-/*
- * tdm_source2_enable
- */
-#define TFA98XX_TDM_CONFIG3_TDMCSRE (0x1<<5)
-#define TFA98XX_TDM_CONFIG3_TDMCSRE_POS 5
-#define TFA98XX_TDM_CONFIG3_TDMCSRE_LEN 1
-#define TFA98XX_TDM_CONFIG3_TDMCSRE_MAX 1
-#define TFA98XX_TDM_CONFIG3_TDMCSRE_MSK 0x20
-
-/*
- * tdm_source3_enable
- */
-#define TFA98XX_TDM_CONFIG3_TDMVSLE (0x1<<6)
-#define TFA98XX_TDM_CONFIG3_TDMVSLE_POS 6
-#define TFA98XX_TDM_CONFIG3_TDMVSLE_LEN 1
-#define TFA98XX_TDM_CONFIG3_TDMVSLE_MAX 1
-#define TFA98XX_TDM_CONFIG3_TDMVSLE_MSK 0x40
-
-/*
- * tdm_source4_enable
- */
-#define TFA98XX_TDM_CONFIG3_TDMCSLE (0x1<<7)
-#define TFA98XX_TDM_CONFIG3_TDMCSLE_POS 7
-#define TFA98XX_TDM_CONFIG3_TDMCSLE_LEN 1
-#define TFA98XX_TDM_CONFIG3_TDMCSLE_MAX 1
-#define TFA98XX_TDM_CONFIG3_TDMCSLE_MSK 0x80
-
-/*
- * tdm_source5_enable
- */
-#define TFA98XX_TDM_CONFIG3_TDMCFRE (0x1<<8)
-#define TFA98XX_TDM_CONFIG3_TDMCFRE_POS 8
-#define TFA98XX_TDM_CONFIG3_TDMCFRE_LEN 1
-#define TFA98XX_TDM_CONFIG3_TDMCFRE_MAX 1
-#define TFA98XX_TDM_CONFIG3_TDMCFRE_MSK 0x100
-
-/*
- * tdm_source6_enable
- */
-#define TFA98XX_TDM_CONFIG3_TDMCFLE (0x1<<9)
-#define TFA98XX_TDM_CONFIG3_TDMCFLE_POS 9
-#define TFA98XX_TDM_CONFIG3_TDMCFLE_LEN 1
-#define TFA98XX_TDM_CONFIG3_TDMCFLE_MAX 1
-#define TFA98XX_TDM_CONFIG3_TDMCFLE_MSK 0x200
-
-/*
- * tdm_source7_enable
- */
-#define TFA98XX_TDM_CONFIG3_TDMCF3E (0x1<<10)
-#define TFA98XX_TDM_CONFIG3_TDMCF3E_POS 10
-#define TFA98XX_TDM_CONFIG3_TDMCF3E_LEN 1
-#define TFA98XX_TDM_CONFIG3_TDMCF3E_MAX 1
-#define TFA98XX_TDM_CONFIG3_TDMCF3E_MSK 0x400
-
-/*
- * tdm_source8_enable
- */
-#define TFA98XX_TDM_CONFIG3_TDMCF4E (0x1<<11)
-#define TFA98XX_TDM_CONFIG3_TDMCF4E_POS 11
-#define TFA98XX_TDM_CONFIG3_TDMCF4E_LEN 1
-#define TFA98XX_TDM_CONFIG3_TDMCF4E_MAX 1
-#define TFA98XX_TDM_CONFIG3_TDMCF4E_MSK 0x800
-
-/*
- * tdm_source9_enable
- */
-#define TFA98XX_TDM_CONFIG3_TDMPD1E (0x1<<12)
-#define TFA98XX_TDM_CONFIG3_TDMPD1E_POS 12
-#define TFA98XX_TDM_CONFIG3_TDMPD1E_LEN 1
-#define TFA98XX_TDM_CONFIG3_TDMPD1E_MAX 1
-#define TFA98XX_TDM_CONFIG3_TDMPD1E_MSK 0x1000
-
-/*
- * tdm_source10_enable
- */
-#define TFA98XX_TDM_CONFIG3_TDMPD2E (0x1<<13)
-#define TFA98XX_TDM_CONFIG3_TDMPD2E_POS 13
-#define TFA98XX_TDM_CONFIG3_TDMPD2E_LEN 1
-#define TFA98XX_TDM_CONFIG3_TDMPD2E_MAX 1
-#define TFA98XX_TDM_CONFIG3_TDMPD2E_MSK 0x2000
-
-
-/*
- * (0x24)-tdm_config4
- */
-
-/*
- * tdm_sink1_io
- */
-#define TFA98XX_TDM_CONFIG4_TDMLIO (0x3<<2)
-#define TFA98XX_TDM_CONFIG4_TDMLIO_POS 2
-#define TFA98XX_TDM_CONFIG4_TDMLIO_LEN 2
-#define TFA98XX_TDM_CONFIG4_TDMLIO_MAX 3
-#define TFA98XX_TDM_CONFIG4_TDMLIO_MSK 0xc
-
-/*
- * tdm_sink2_io
- */
-#define TFA98XX_TDM_CONFIG4_TDMRIO (0x3<<4)
-#define TFA98XX_TDM_CONFIG4_TDMRIO_POS 4
-#define TFA98XX_TDM_CONFIG4_TDMRIO_LEN 2
-#define TFA98XX_TDM_CONFIG4_TDMRIO_MAX 3
-#define TFA98XX_TDM_CONFIG4_TDMRIO_MSK 0x30
-
-/*
- * tdm_source1_io
- */
-#define TFA98XX_TDM_CONFIG4_TDMVSRIO (0x3<<8)
-#define TFA98XX_TDM_CONFIG4_TDMVSRIO_POS 8
-#define TFA98XX_TDM_CONFIG4_TDMVSRIO_LEN 2
-#define TFA98XX_TDM_CONFIG4_TDMVSRIO_MAX 3
-#define TFA98XX_TDM_CONFIG4_TDMVSRIO_MSK 0x300
-
-/*
- * tdm_source2_io
- */
-#define TFA98XX_TDM_CONFIG4_TDMCSRIO (0x3<<10)
-#define TFA98XX_TDM_CONFIG4_TDMCSRIO_POS 10
-#define TFA98XX_TDM_CONFIG4_TDMCSRIO_LEN 2
-#define TFA98XX_TDM_CONFIG4_TDMCSRIO_MAX 3
-#define TFA98XX_TDM_CONFIG4_TDMCSRIO_MSK 0xc00
-
-/*
- * tdm_source3_io
- */
-#define TFA98XX_TDM_CONFIG4_TDMVSLIO (0x3<<12)
-#define TFA98XX_TDM_CONFIG4_TDMVSLIO_POS 12
-#define TFA98XX_TDM_CONFIG4_TDMVSLIO_LEN 2
-#define TFA98XX_TDM_CONFIG4_TDMVSLIO_MAX 3
-#define TFA98XX_TDM_CONFIG4_TDMVSLIO_MSK 0x3000
-
-/*
- * tdm_source4_io
- */
-#define TFA98XX_TDM_CONFIG4_TDMCSLIO (0x3<<14)
-#define TFA98XX_TDM_CONFIG4_TDMCSLIO_POS 14
-#define TFA98XX_TDM_CONFIG4_TDMCSLIO_LEN 2
-#define TFA98XX_TDM_CONFIG4_TDMCSLIO_MAX 3
-#define TFA98XX_TDM_CONFIG4_TDMCSLIO_MSK 0xc000
-
-
-/*
- * (0x25)-tdm_config5
- */
-
-/*
- * tdm_source5_io
- */
-#define TFA98XX_TDM_CONFIG5_TDMCFRIO (0x3<<0)
-#define TFA98XX_TDM_CONFIG5_TDMCFRIO_POS 0
-#define TFA98XX_TDM_CONFIG5_TDMCFRIO_LEN 2
-#define TFA98XX_TDM_CONFIG5_TDMCFRIO_MAX 3
-#define TFA98XX_TDM_CONFIG5_TDMCFRIO_MSK 0x3
-
-/*
- * tdm_source6_io
- */
-#define TFA98XX_TDM_CONFIG5_TDMCFLIO (0x3<<2)
-#define TFA98XX_TDM_CONFIG5_TDMCFLIO_POS 2
-#define TFA98XX_TDM_CONFIG5_TDMCFLIO_LEN 2
-#define TFA98XX_TDM_CONFIG5_TDMCFLIO_MAX 3
-#define TFA98XX_TDM_CONFIG5_TDMCFLIO_MSK 0xc
-
-/*
- * tdm_source7_io
- */
-#define TFA98XX_TDM_CONFIG5_TDMCF3IO (0x3<<4)
-#define TFA98XX_TDM_CONFIG5_TDMCF3IO_POS 4
-#define TFA98XX_TDM_CONFIG5_TDMCF3IO_LEN 2
-#define TFA98XX_TDM_CONFIG5_TDMCF3IO_MAX 3
-#define TFA98XX_TDM_CONFIG5_TDMCF3IO_MSK 0x30
-
-/*
- * tdm_source8_io
- */
-#define TFA98XX_TDM_CONFIG5_TDMCF4IO (0x3<<6)
-#define TFA98XX_TDM_CONFIG5_TDMCF4IO_POS 6
-#define TFA98XX_TDM_CONFIG5_TDMCF4IO_LEN 2
-#define TFA98XX_TDM_CONFIG5_TDMCF4IO_MAX 3
-#define TFA98XX_TDM_CONFIG5_TDMCF4IO_MSK 0xc0
-
-/*
- * tdm_source9_io
- */
-#define TFA98XX_TDM_CONFIG5_TDMPD1IO (0x3<<8)
-#define TFA98XX_TDM_CONFIG5_TDMPD1IO_POS 8
-#define TFA98XX_TDM_CONFIG5_TDMPD1IO_LEN 2
-#define TFA98XX_TDM_CONFIG5_TDMPD1IO_MAX 3
-#define TFA98XX_TDM_CONFIG5_TDMPD1IO_MSK 0x300
-
-/*
- * tdm_source10_io
- */
-#define TFA98XX_TDM_CONFIG5_TDMPD2IO (0x3<<10)
-#define TFA98XX_TDM_CONFIG5_TDMPD2IO_POS 10
-#define TFA98XX_TDM_CONFIG5_TDMPD2IO_LEN 2
-#define TFA98XX_TDM_CONFIG5_TDMPD2IO_MAX 3
-#define TFA98XX_TDM_CONFIG5_TDMPD2IO_MSK 0xc00
-
-
-/*
- * (0x26)-tdm_config6
- */
-
-/*
- * tdm_sink1_slot
- */
-#define TFA98XX_TDM_CONFIG6_TDMLS (0xf<<4)
-#define TFA98XX_TDM_CONFIG6_TDMLS_POS 4
-#define TFA98XX_TDM_CONFIG6_TDMLS_LEN 4
-#define TFA98XX_TDM_CONFIG6_TDMLS_MAX 15
-#define TFA98XX_TDM_CONFIG6_TDMLS_MSK 0xf0
-
-/*
- * tdm_sink2_slot
- */
-#define TFA98XX_TDM_CONFIG6_TDMRS (0xf<<8)
-#define TFA98XX_TDM_CONFIG6_TDMRS_POS 8
-#define TFA98XX_TDM_CONFIG6_TDMRS_LEN 4
-#define TFA98XX_TDM_CONFIG6_TDMRS_MAX 15
-#define TFA98XX_TDM_CONFIG6_TDMRS_MSK 0xf00
-
-
-/*
- * (0x27)-tdm_config7
- */
-
-/*
- * tdm_source1_slot
- */
-#define TFA98XX_TDM_CONFIG7_TDMVSRS (0xf<<0)
-#define TFA98XX_TDM_CONFIG7_TDMVSRS_POS 0
-#define TFA98XX_TDM_CONFIG7_TDMVSRS_LEN 4
-#define TFA98XX_TDM_CONFIG7_TDMVSRS_MAX 15
-#define TFA98XX_TDM_CONFIG7_TDMVSRS_MSK 0xf
-
-/*
- * tdm_source2_slot
- */
-#define TFA98XX_TDM_CONFIG7_TDMCSRS (0xf<<4)
-#define TFA98XX_TDM_CONFIG7_TDMCSRS_POS 4
-#define TFA98XX_TDM_CONFIG7_TDMCSRS_LEN 4
-#define TFA98XX_TDM_CONFIG7_TDMCSRS_MAX 15
-#define TFA98XX_TDM_CONFIG7_TDMCSRS_MSK 0xf0
-
-/*
- * tdm_source3_slot
- */
-#define TFA98XX_TDM_CONFIG7_TDMVSLS (0xf<<8)
-#define TFA98XX_TDM_CONFIG7_TDMVSLS_POS 8
-#define TFA98XX_TDM_CONFIG7_TDMVSLS_LEN 4
-#define TFA98XX_TDM_CONFIG7_TDMVSLS_MAX 15
-#define TFA98XX_TDM_CONFIG7_TDMVSLS_MSK 0xf00
-
-/*
- * tdm_source4_slot
- */
-#define TFA98XX_TDM_CONFIG7_TDMCSLS (0xf<<12)
-#define TFA98XX_TDM_CONFIG7_TDMCSLS_POS 12
-#define TFA98XX_TDM_CONFIG7_TDMCSLS_LEN 4
-#define TFA98XX_TDM_CONFIG7_TDMCSLS_MAX 15
-#define TFA98XX_TDM_CONFIG7_TDMCSLS_MSK 0xf000
-
-
-/*
- * (0x28)-tdm_config8
- */
-
-/*
- * tdm_source5_slot
- */
-#define TFA98XX_TDM_CONFIG8_TDMCFRS (0xf<<0)
-#define TFA98XX_TDM_CONFIG8_TDMCFRS_POS 0
-#define TFA98XX_TDM_CONFIG8_TDMCFRS_LEN 4
-#define TFA98XX_TDM_CONFIG8_TDMCFRS_MAX 15
-#define TFA98XX_TDM_CONFIG8_TDMCFRS_MSK 0xf
-
-/*
- * tdm_source6_slot
- */
-#define TFA98XX_TDM_CONFIG8_TDMCFLS (0xf<<4)
-#define TFA98XX_TDM_CONFIG8_TDMCFLS_POS 4
-#define TFA98XX_TDM_CONFIG8_TDMCFLS_LEN 4
-#define TFA98XX_TDM_CONFIG8_TDMCFLS_MAX 15
-#define TFA98XX_TDM_CONFIG8_TDMCFLS_MSK 0xf0
-
-/*
- * tdm_source7_slot
- */
-#define TFA98XX_TDM_CONFIG8_TDMCF3S (0xf<<8)
-#define TFA98XX_TDM_CONFIG8_TDMCF3S_POS 8
-#define TFA98XX_TDM_CONFIG8_TDMCF3S_LEN 4
-#define TFA98XX_TDM_CONFIG8_TDMCF3S_MAX 15
-#define TFA98XX_TDM_CONFIG8_TDMCF3S_MSK 0xf00
-
-/*
- * tdm_source8_slot
- */
-#define TFA98XX_TDM_CONFIG8_TDMCF4S (0xf<<12)
-#define TFA98XX_TDM_CONFIG8_TDMCF4S_POS 12
-#define TFA98XX_TDM_CONFIG8_TDMCF4S_LEN 4
-#define TFA98XX_TDM_CONFIG8_TDMCF4S_MAX 15
-#define TFA98XX_TDM_CONFIG8_TDMCF4S_MSK 0xf000
-
-
-/*
- * (0x29)-tdm_config9
- */
-
-/*
- * tdm_source9_slot
- */
-#define TFA98XX_TDM_CONFIG9_TDMPD1S (0xf<<0)
-#define TFA98XX_TDM_CONFIG9_TDMPD1S_POS 0
-#define TFA98XX_TDM_CONFIG9_TDMPD1S_LEN 4
-#define TFA98XX_TDM_CONFIG9_TDMPD1S_MAX 15
-#define TFA98XX_TDM_CONFIG9_TDMPD1S_MSK 0xf
-
-/*
- * tdm_source10_slot
- */
-#define TFA98XX_TDM_CONFIG9_TDMPD2S (0xf<<4)
-#define TFA98XX_TDM_CONFIG9_TDMPD2S_POS 4
-#define TFA98XX_TDM_CONFIG9_TDMPD2S_LEN 4
-#define TFA98XX_TDM_CONFIG9_TDMPD2S_MAX 15
-#define TFA98XX_TDM_CONFIG9_TDMPD2S_MSK 0xf0
-
-
-/*
- * (0x31)-pdm_config0
- */
-
-/*
- * pdm_mode
- */
-#define TFA98XX_PDM_CONFIG0_PDMSM (0x1<<0)
-#define TFA98XX_PDM_CONFIG0_PDMSM_POS 0
-#define TFA98XX_PDM_CONFIG0_PDMSM_LEN 1
-#define TFA98XX_PDM_CONFIG0_PDMSM_MAX 1
-#define TFA98XX_PDM_CONFIG0_PDMSM_MSK 0x1
-
-/*
- * pdm_side_tone_sel
- */
-#define TFA98XX_PDM_CONFIG0_PDMSTSEL (0x3<<1)
-#define TFA98XX_PDM_CONFIG0_PDMSTSEL_POS 1
-#define TFA98XX_PDM_CONFIG0_PDMSTSEL_LEN 2
-#define TFA98XX_PDM_CONFIG0_PDMSTSEL_MAX 3
-#define TFA98XX_PDM_CONFIG0_PDMSTSEL_MSK 0x6
-
-/*
- * pdm_left_sel
- */
-#define TFA98XX_PDM_CONFIG0_PDMLSEL (0x1<<3)
-#define TFA98XX_PDM_CONFIG0_PDMLSEL_POS 3
-#define TFA98XX_PDM_CONFIG0_PDMLSEL_LEN 1
-#define TFA98XX_PDM_CONFIG0_PDMLSEL_MAX 1
-#define TFA98XX_PDM_CONFIG0_PDMLSEL_MSK 0x8
-
-/*
- * pdm_right_sel
- */
-#define TFA98XX_PDM_CONFIG0_PDMRSEL (0x1<<4)
-#define TFA98XX_PDM_CONFIG0_PDMRSEL_POS 4
-#define TFA98XX_PDM_CONFIG0_PDMRSEL_LEN 1
-#define TFA98XX_PDM_CONFIG0_PDMRSEL_MAX 1
-#define TFA98XX_PDM_CONFIG0_PDMRSEL_MSK 0x10
-
-/*
- * enbl_micvdd
- */
-#define TFA98XX_PDM_CONFIG0_MICVDDE (0x1<<5)
-#define TFA98XX_PDM_CONFIG0_MICVDDE_POS 5
-#define TFA98XX_PDM_CONFIG0_MICVDDE_LEN 1
-#define TFA98XX_PDM_CONFIG0_MICVDDE_MAX 1
-#define TFA98XX_PDM_CONFIG0_MICVDDE_MSK 0x20
-
-
-/*
- * (0x32)-pdm_config1
- */
-
-/*
- * pdm_nbck
- */
-#define TFA98XX_PDM_CONFIG1_PDMCLRAT (0x3<<0)
-#define TFA98XX_PDM_CONFIG1_PDMCLRAT_POS 0
-#define TFA98XX_PDM_CONFIG1_PDMCLRAT_LEN 2
-#define TFA98XX_PDM_CONFIG1_PDMCLRAT_MAX 3
-#define TFA98XX_PDM_CONFIG1_PDMCLRAT_MSK 0x3
-
-/*
- * pdm_gain
- */
-#define TFA98XX_PDM_CONFIG1_PDMGAIN (0xf<<2)
-#define TFA98XX_PDM_CONFIG1_PDMGAIN_POS 2
-#define TFA98XX_PDM_CONFIG1_PDMGAIN_LEN 4
-#define TFA98XX_PDM_CONFIG1_PDMGAIN_MAX 15
-#define TFA98XX_PDM_CONFIG1_PDMGAIN_MSK 0x3c
-
-/*
- * sel_pdm_out_data
- */
-#define TFA98XX_PDM_CONFIG1_PDMOSEL (0xf<<6)
-#define TFA98XX_PDM_CONFIG1_PDMOSEL_POS 6
-#define TFA98XX_PDM_CONFIG1_PDMOSEL_LEN 4
-#define TFA98XX_PDM_CONFIG1_PDMOSEL_MAX 15
-#define TFA98XX_PDM_CONFIG1_PDMOSEL_MSK 0x3c0
-
-/*
- * sel_cf_haptic_data
- */
-#define TFA98XX_PDM_CONFIG1_SELCFHAPD (0x1<<10)
-#define TFA98XX_PDM_CONFIG1_SELCFHAPD_POS 10
-#define TFA98XX_PDM_CONFIG1_SELCFHAPD_LEN 1
-#define TFA98XX_PDM_CONFIG1_SELCFHAPD_MAX 1
-#define TFA98XX_PDM_CONFIG1_SELCFHAPD_MSK 0x400
-
-
-/*
- * (0x33)-haptic_driver_config
- */
-
-/*
- * haptic_duration
- */
-#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPTIME (0xff<<0)
-#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPTIME_POS 0
-#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPTIME_LEN 8
-#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPTIME_MAX 255
-#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPTIME_MSK 0xff
-
-/*
- * haptic_data
- */
-#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPLEVEL (0xff<<8)
-#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPLEVEL_POS 8
-#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPLEVEL_LEN 8
-#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPLEVEL_MAX 255
-#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPLEVEL_MSK 0xff00
-
-
-/*
- * (0x34)-gpio_datain_reg
- */
-
-/*
- * gpio_datain
- */
-#define TFA98XX_GPIO_DATAIN_REG_GPIODIN (0xf<<0)
-#define TFA98XX_GPIO_DATAIN_REG_GPIODIN_POS 0
-#define TFA98XX_GPIO_DATAIN_REG_GPIODIN_LEN 4
-#define TFA98XX_GPIO_DATAIN_REG_GPIODIN_MAX 15
-#define TFA98XX_GPIO_DATAIN_REG_GPIODIN_MSK 0xf
-
-
-/*
- * (0x35)-gpio_config
- */
-
-/*
- * gpio_ctrl
- */
-#define TFA98XX_GPIO_CONFIG_GPIOCTRL (0x1<<0)
-#define TFA98XX_GPIO_CONFIG_GPIOCTRL_POS 0
-#define TFA98XX_GPIO_CONFIG_GPIOCTRL_LEN 1
-#define TFA98XX_GPIO_CONFIG_GPIOCTRL_MAX 1
-#define TFA98XX_GPIO_CONFIG_GPIOCTRL_MSK 0x1
-
-/*
- * gpio_dir
- */
-#define TFA98XX_GPIO_CONFIG_GPIOCONF (0xf<<1)
-#define TFA98XX_GPIO_CONFIG_GPIOCONF_POS 1
-#define TFA98XX_GPIO_CONFIG_GPIOCONF_LEN 4
-#define TFA98XX_GPIO_CONFIG_GPIOCONF_MAX 15
-#define TFA98XX_GPIO_CONFIG_GPIOCONF_MSK 0x1e
-
-/*
- * gpio_dataout
- */
-#define TFA98XX_GPIO_CONFIG_GPIODOUT (0xf<<5)
-#define TFA98XX_GPIO_CONFIG_GPIODOUT_POS 5
-#define TFA98XX_GPIO_CONFIG_GPIODOUT_LEN 4
-#define TFA98XX_GPIO_CONFIG_GPIODOUT_MAX 15
-#define TFA98XX_GPIO_CONFIG_GPIODOUT_MSK 0x1e0
-
-
-/*
- * (0x40)-interrupt_out_reg1
- */
-
-/*
- * int_out_flag_por
- */
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTVDDS (0x1<<0)
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTVDDS_POS 0
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTVDDS_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTVDDS_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTVDDS_MSK 0x1
-
-/*
- * int_out_flag_pll_lock
- */
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTPLLS (0x1<<1)
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTPLLS_POS 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTPLLS_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTPLLS_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTPLLS_MSK 0x2
-
-/*
- * int_out_flag_otpok
- */
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTOTDS (0x1<<2)
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTOTDS_POS 2
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTOTDS_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTOTDS_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTOTDS_MSK 0x4
-
-/*
- * int_out_flag_ovpok
- */
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTOVDS (0x1<<3)
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTOVDS_POS 3
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTOVDS_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTOVDS_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTOVDS_MSK 0x8
-
-/*
- * int_out_flag_uvpok
- */
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTUVDS (0x1<<4)
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTUVDS_POS 4
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTUVDS_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTUVDS_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTUVDS_MSK 0x10
-
-/*
- * int_out_flag_clocks_stable
- */
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTCLKS (0x1<<5)
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTCLKS_POS 5
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTCLKS_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTCLKS_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTCLKS_MSK 0x20
-
-/*
- * int_out_flag_mtp_busy
- */
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTMTPB (0x1<<6)
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTMTPB_POS 6
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTMTPB_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTMTPB_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTMTPB_MSK 0x40
-
-/*
- * int_out_flag_lost_clk
- */
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTNOCLK (0x1<<7)
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTNOCLK_POS 7
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTNOCLK_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTNOCLK_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTNOCLK_MSK 0x80
-
-/*
- * int_out_flag_cf_speakererror
- */
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTSPKS (0x1<<8)
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTSPKS_POS 8
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTSPKS_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTSPKS_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTSPKS_MSK 0x100
-
-/*
- * int_out_flag_cold_started
- */
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTACS (0x1<<9)
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTACS_POS 9
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTACS_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTACS_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTACS_MSK 0x200
-
-/*
- * int_out_flag_engage
- */
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTSWS (0x1<<10)
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTSWS_POS 10
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTSWS_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTSWS_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTSWS_MSK 0x400
-
-/*
- * int_out_flag_watchdog_reset
- */
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTWDS (0x1<<11)
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTWDS_POS 11
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTWDS_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTWDS_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTWDS_MSK 0x800
-
-/*
- * int_out_flag_enbl_amp
- */
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTAMPS (0x1<<12)
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTAMPS_POS 12
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTAMPS_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTAMPS_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTAMPS_MSK 0x1000
-
-/*
- * int_out_flag_enbl_ref
- */
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTAREFS (0x1<<13)
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTAREFS_POS 13
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTAREFS_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTAREFS_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTAREFS_MSK 0x2000
-
-/*
- * int_out_flag_adc10_ready
- */
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTADCCR (0x1<<14)
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTADCCR_POS 14
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTADCCR_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTADCCR_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTADCCR_MSK 0x4000
-
-/*
- * int_out_flag_bod_vddd_nok
- */
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTBODNOK (0x1<<15)
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTBODNOK_POS 15
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTBODNOK_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTBODNOK_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG1_ISTBODNOK_MSK 0x8000
-
-
-/*
- * (0x41)-interrupt_out_reg2
- */
-
-/*
- * int_out_flag_bst_bstcur
- */
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTCU (0x1<<0)
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTCU_POS 0
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTCU_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTCU_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTCU_MSK 0x1
-
-/*
- * int_out_flag_bst_hiz
- */
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTHI (0x1<<1)
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTHI_POS 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTHI_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTHI_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTHI_MSK 0x2
-
-/*
- * int_out_flag_bst_ocpok
- */
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTOC (0x1<<2)
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTOC_POS 2
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTOC_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTOC_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTOC_MSK 0x4
-
-/*
- * int_out_flag_bst_peakcur
- */
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTPKCUR (0x1<<3)
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTPKCUR_POS 3
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTPKCUR_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTPKCUR_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTPKCUR_MSK 0x8
-
-/*
- * int_out_flag_bst_voutcomp
- */
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTVC (0x1<<4)
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTVC_POS 4
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTVC_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTVC_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTVC_MSK 0x10
-
-/*
- * int_out_flag_bst_voutcomp86
- */
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST86 (0x1<<5)
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST86_POS 5
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST86_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST86_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST86_MSK 0x20
-
-/*
- * int_out_flag_bst_voutcomp93
- */
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST93 (0x1<<6)
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST93_POS 6
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST93_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST93_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST93_MSK 0x40
-
-/*
- * int_out_flag_rcvldop_ready
- */
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTRCVLD (0x1<<7)
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTRCVLD_POS 7
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTRCVLD_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTRCVLD_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTRCVLD_MSK 0x80
-
-/*
- * int_out_flag_ocp_alarm_left
- */
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPL (0x1<<8)
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPL_POS 8
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPL_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPL_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPL_MSK 0x100
-
-/*
- * int_out_flag_ocp_alarm_right
- */
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPR (0x1<<9)
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPR_POS 9
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPR_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPR_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPR_MSK 0x200
-
-/*
- * int_out_flag_man_wait_src_settings
- */
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSRC (0x1<<10)
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSRC_POS 10
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSRC_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSRC_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSRC_MSK 0x400
-
-/*
- * int_out_flag_man_wait_cf_config
- */
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWCFC (0x1<<11)
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWCFC_POS 11
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWCFC_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWCFC_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWCFC_MSK 0x800
-
-/*
- * int_out_flag_man_start_mute_audio
- */
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSMU (0x1<<12)
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSMU_POS 12
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSMU_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSMU_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSMU_MSK 0x1000
-
-/*
- * int_out_flag_cfma_err
- */
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMER (0x1<<13)
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMER_POS 13
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMER_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMER_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMER_MSK 0x2000
-
-/*
- * int_out_flag_cfma_ack
- */
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMAC (0x1<<14)
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMAC_POS 14
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMAC_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMAC_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMAC_MSK 0x4000
-
-/*
- * int_out_flag_clk_out_of_range
- */
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTCLKOOR (0x1<<15)
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTCLKOOR_POS 15
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTCLKOOR_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTCLKOOR_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG2_ISTCLKOOR_MSK 0x8000
-
-
-/*
- * (0x42)-interrupt_out_reg3
- */
-
-/*
- * int_out_flag_tdm_error
- */
-#define TFA98XX_INTERRUPT_OUT_REG3_ISTTDMER (0x1<<0)
-#define TFA98XX_INTERRUPT_OUT_REG3_ISTTDMER_POS 0
-#define TFA98XX_INTERRUPT_OUT_REG3_ISTTDMER_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG3_ISTTDMER_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG3_ISTTDMER_MSK 0x1
-
-/*
- * int_out_flag_clip_left
- */
-#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPL (0x1<<1)
-#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPL_POS 1
-#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPL_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPL_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPL_MSK 0x2
-
-/*
- * int_out_flag_clip_right
- */
-#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPR (0x1<<2)
-#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPR_POS 2
-#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPR_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPR_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPR_MSK 0x4
-
-/*
- * int_out_flag_mic_ocpok
- */
-#define TFA98XX_INTERRUPT_OUT_REG3_ISTOCPM (0x1<<3)
-#define TFA98XX_INTERRUPT_OUT_REG3_ISTOCPM_POS 3
-#define TFA98XX_INTERRUPT_OUT_REG3_ISTOCPM_LEN 1
-#define TFA98XX_INTERRUPT_OUT_REG3_ISTOCPM_MAX 1
-#define TFA98XX_INTERRUPT_OUT_REG3_ISTOCPM_MSK 0x8
-
-
-/*
- * (0x44)-interrupt_in_reg1
- */
-
-/*
- * int_in_flag_por
- */
-#define TFA98XX_INTERRUPT_IN_REG1_ICLVDDS (0x1<<0)
-#define TFA98XX_INTERRUPT_IN_REG1_ICLVDDS_POS 0
-#define TFA98XX_INTERRUPT_IN_REG1_ICLVDDS_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLVDDS_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLVDDS_MSK 0x1
-
-/*
- * int_in_flag_pll_lock
- */
-#define TFA98XX_INTERRUPT_IN_REG1_ICLPLLS (0x1<<1)
-#define TFA98XX_INTERRUPT_IN_REG1_ICLPLLS_POS 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLPLLS_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLPLLS_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLPLLS_MSK 0x2
-
-/*
- * int_in_flag_otpok
- */
-#define TFA98XX_INTERRUPT_IN_REG1_ICLOTDS (0x1<<2)
-#define TFA98XX_INTERRUPT_IN_REG1_ICLOTDS_POS 2
-#define TFA98XX_INTERRUPT_IN_REG1_ICLOTDS_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLOTDS_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLOTDS_MSK 0x4
-
-/*
- * int_in_flag_ovpok
- */
-#define TFA98XX_INTERRUPT_IN_REG1_ICLOVDS (0x1<<3)
-#define TFA98XX_INTERRUPT_IN_REG1_ICLOVDS_POS 3
-#define TFA98XX_INTERRUPT_IN_REG1_ICLOVDS_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLOVDS_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLOVDS_MSK 0x8
-
-/*
- * int_in_flag_uvpok
- */
-#define TFA98XX_INTERRUPT_IN_REG1_ICLUVDS (0x1<<4)
-#define TFA98XX_INTERRUPT_IN_REG1_ICLUVDS_POS 4
-#define TFA98XX_INTERRUPT_IN_REG1_ICLUVDS_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLUVDS_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLUVDS_MSK 0x10
-
-/*
- * int_in_flag_clocks_stable
- */
-#define TFA98XX_INTERRUPT_IN_REG1_ICLCLKS (0x1<<5)
-#define TFA98XX_INTERRUPT_IN_REG1_ICLCLKS_POS 5
-#define TFA98XX_INTERRUPT_IN_REG1_ICLCLKS_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLCLKS_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLCLKS_MSK 0x20
-
-/*
- * int_in_flag_mtp_busy
- */
-#define TFA98XX_INTERRUPT_IN_REG1_ICLMTPB (0x1<<6)
-#define TFA98XX_INTERRUPT_IN_REG1_ICLMTPB_POS 6
-#define TFA98XX_INTERRUPT_IN_REG1_ICLMTPB_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLMTPB_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLMTPB_MSK 0x40
-
-/*
- * int_in_flag_lost_clk
- */
-#define TFA98XX_INTERRUPT_IN_REG1_ICLNOCLK (0x1<<7)
-#define TFA98XX_INTERRUPT_IN_REG1_ICLNOCLK_POS 7
-#define TFA98XX_INTERRUPT_IN_REG1_ICLNOCLK_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLNOCLK_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLNOCLK_MSK 0x80
-
-/*
- * int_in_flag_cf_speakererror
- */
-#define TFA98XX_INTERRUPT_IN_REG1_ICLSPKS (0x1<<8)
-#define TFA98XX_INTERRUPT_IN_REG1_ICLSPKS_POS 8
-#define TFA98XX_INTERRUPT_IN_REG1_ICLSPKS_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLSPKS_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLSPKS_MSK 0x100
-
-/*
- * int_in_flag_cold_started
- */
-#define TFA98XX_INTERRUPT_IN_REG1_ICLACS (0x1<<9)
-#define TFA98XX_INTERRUPT_IN_REG1_ICLACS_POS 9
-#define TFA98XX_INTERRUPT_IN_REG1_ICLACS_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLACS_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLACS_MSK 0x200
-
-/*
- * int_in_flag_engage
- */
-#define TFA98XX_INTERRUPT_IN_REG1_ICLSWS (0x1<<10)
-#define TFA98XX_INTERRUPT_IN_REG1_ICLSWS_POS 10
-#define TFA98XX_INTERRUPT_IN_REG1_ICLSWS_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLSWS_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLSWS_MSK 0x400
-
-/*
- * int_in_flag_watchdog_reset
- */
-#define TFA98XX_INTERRUPT_IN_REG1_ICLWDS (0x1<<11)
-#define TFA98XX_INTERRUPT_IN_REG1_ICLWDS_POS 11
-#define TFA98XX_INTERRUPT_IN_REG1_ICLWDS_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLWDS_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLWDS_MSK 0x800
-
-/*
- * int_in_flag_enbl_amp
- */
-#define TFA98XX_INTERRUPT_IN_REG1_ICLAMPS (0x1<<12)
-#define TFA98XX_INTERRUPT_IN_REG1_ICLAMPS_POS 12
-#define TFA98XX_INTERRUPT_IN_REG1_ICLAMPS_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLAMPS_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLAMPS_MSK 0x1000
-
-/*
- * int_in_flag_enbl_ref
- */
-#define TFA98XX_INTERRUPT_IN_REG1_ICLAREFS (0x1<<13)
-#define TFA98XX_INTERRUPT_IN_REG1_ICLAREFS_POS 13
-#define TFA98XX_INTERRUPT_IN_REG1_ICLAREFS_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLAREFS_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLAREFS_MSK 0x2000
-
-/*
- * int_in_flag_adc10_ready
- */
-#define TFA98XX_INTERRUPT_IN_REG1_ICLADCCR (0x1<<14)
-#define TFA98XX_INTERRUPT_IN_REG1_ICLADCCR_POS 14
-#define TFA98XX_INTERRUPT_IN_REG1_ICLADCCR_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLADCCR_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLADCCR_MSK 0x4000
-
-/*
- * int_in_flag_bod_vddd_nok
- */
-#define TFA98XX_INTERRUPT_IN_REG1_ICLBODNOK (0x1<<15)
-#define TFA98XX_INTERRUPT_IN_REG1_ICLBODNOK_POS 15
-#define TFA98XX_INTERRUPT_IN_REG1_ICLBODNOK_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLBODNOK_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG1_ICLBODNOK_MSK 0x8000
-
-
-/*
- * (0x45)-interrupt_in_reg2
- */
-
-/*
- * int_in_flag_bst_bstcur
- */
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTCU (0x1<<0)
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTCU_POS 0
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTCU_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTCU_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTCU_MSK 0x1
-
-/*
- * int_in_flag_bst_hiz
- */
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTHI (0x1<<1)
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTHI_POS 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTHI_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTHI_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTHI_MSK 0x2
-
-/*
- * int_in_flag_bst_ocpok
- */
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTOC (0x1<<2)
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTOC_POS 2
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTOC_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTOC_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTOC_MSK 0x4
-
-/*
- * int_in_flag_bst_peakcur
- */
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTPC (0x1<<3)
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTPC_POS 3
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTPC_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTPC_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTPC_MSK 0x8
-
-/*
- * int_in_flag_bst_voutcomp
- */
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTVC (0x1<<4)
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTVC_POS 4
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTVC_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTVC_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTVC_MSK 0x10
-
-/*
- * int_in_flag_bst_voutcomp86
- */
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBST86 (0x1<<5)
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBST86_POS 5
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBST86_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBST86_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBST86_MSK 0x20
-
-/*
- * int_in_flag_bst_voutcomp93
- */
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBST93 (0x1<<6)
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBST93_POS 6
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBST93_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBST93_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLBST93_MSK 0x40
-
-/*
- * int_in_flag_rcvldop_ready
- */
-#define TFA98XX_INTERRUPT_IN_REG2_ICLRCVLD (0x1<<7)
-#define TFA98XX_INTERRUPT_IN_REG2_ICLRCVLD_POS 7
-#define TFA98XX_INTERRUPT_IN_REG2_ICLRCVLD_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLRCVLD_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLRCVLD_MSK 0x80
-
-/*
- * int_in_flag_ocp_alarm_left
- */
-#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPL (0x1<<8)
-#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPL_POS 8
-#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPL_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPL_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPL_MSK 0x100
-
-/*
- * int_in_flag_ocp_alarm_right
- */
-#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPR (0x1<<9)
-#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPR_POS 9
-#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPR_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPR_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPR_MSK 0x200
-
-/*
- * int_in_flag_man_wait_src_settings
- */
-#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSRC (0x1<<10)
-#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSRC_POS 10
-#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSRC_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSRC_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSRC_MSK 0x400
-
-/*
- * int_in_flag_man_wait_cf_config
- */
-#define TFA98XX_INTERRUPT_IN_REG2_ICLMWCFC (0x1<<11)
-#define TFA98XX_INTERRUPT_IN_REG2_ICLMWCFC_POS 11
-#define TFA98XX_INTERRUPT_IN_REG2_ICLMWCFC_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLMWCFC_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLMWCFC_MSK 0x800
-
-/*
- * int_in_flag_man_start_mute_audio
- */
-#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSMU (0x1<<12)
-#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSMU_POS 12
-#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSMU_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSMU_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSMU_MSK 0x1000
-
-/*
- * int_in_flag_cfma_err
- */
-#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMER (0x1<<13)
-#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMER_POS 13
-#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMER_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMER_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMER_MSK 0x2000
-
-/*
- * int_in_flag_cfma_ack
- */
-#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMAC (0x1<<14)
-#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMAC_POS 14
-#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMAC_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMAC_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMAC_MSK 0x4000
-
-/*
- * int_in_flag_clk_out_of_range
- */
-#define TFA98XX_INTERRUPT_IN_REG2_ICLCLKOOR (0x1<<15)
-#define TFA98XX_INTERRUPT_IN_REG2_ICLCLKOOR_POS 15
-#define TFA98XX_INTERRUPT_IN_REG2_ICLCLKOOR_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLCLKOOR_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG2_ICLCLKOOR_MSK 0x8000
-
-
-/*
- * (0x46)-interrupt_in_reg3
- */
-
-/*
- * int_in_flag_tdm_error
- */
-#define TFA98XX_INTERRUPT_IN_REG3_ICLTDMER (0x1<<0)
-#define TFA98XX_INTERRUPT_IN_REG3_ICLTDMER_POS 0
-#define TFA98XX_INTERRUPT_IN_REG3_ICLTDMER_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG3_ICLTDMER_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG3_ICLTDMER_MSK 0x1
-
-/*
- * int_in_flag_clip_left
- */
-#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPL (0x1<<1)
-#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPL_POS 1
-#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPL_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPL_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPL_MSK 0x2
-
-/*
- * int_in_flag_clip_right
- */
-#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPR (0x1<<2)
-#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPR_POS 2
-#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPR_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPR_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPR_MSK 0x4
-
-/*
- * int_in_flag_mic_ocpok
- */
-#define TFA98XX_INTERRUPT_IN_REG3_ICLOCPM (0x1<<3)
-#define TFA98XX_INTERRUPT_IN_REG3_ICLOCPM_POS 3
-#define TFA98XX_INTERRUPT_IN_REG3_ICLOCPM_LEN 1
-#define TFA98XX_INTERRUPT_IN_REG3_ICLOCPM_MAX 1
-#define TFA98XX_INTERRUPT_IN_REG3_ICLOCPM_MSK 0x8
-
-
-/*
- * (0x48)-interrupt_enable_reg1
- */
-
-/*
- * int_enable_flag_por
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEVDDS (0x1<<0)
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEVDDS_POS 0
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEVDDS_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEVDDS_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEVDDS_MSK 0x1
-
-/*
- * int_enable_flag_pll_lock
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEPLLS (0x1<<1)
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEPLLS_POS 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEPLLS_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEPLLS_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEPLLS_MSK 0x2
-
-/*
- * int_enable_flag_otpok
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOTDS (0x1<<2)
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOTDS_POS 2
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOTDS_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOTDS_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOTDS_MSK 0x4
-
-/*
- * int_enable_flag_ovpok
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOVDS (0x1<<3)
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOVDS_POS 3
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOVDS_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOVDS_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOVDS_MSK 0x8
-
-/*
- * int_enable_flag_uvpok
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEUVDS (0x1<<4)
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEUVDS_POS 4
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEUVDS_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEUVDS_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEUVDS_MSK 0x10
-
-/*
- * int_enable_flag_clocks_stable
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IECLKS (0x1<<5)
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IECLKS_POS 5
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IECLKS_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IECLKS_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IECLKS_MSK 0x20
-
-/*
- * int_enable_flag_mtp_busy
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEMTPB (0x1<<6)
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEMTPB_POS 6
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEMTPB_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEMTPB_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEMTPB_MSK 0x40
-
-/*
- * int_enable_flag_lost_clk
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IENOCLK (0x1<<7)
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IENOCLK_POS 7
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IENOCLK_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IENOCLK_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IENOCLK_MSK 0x80
-
-/*
- * int_enable_flag_cf_speakererror
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IESPKS (0x1<<8)
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IESPKS_POS 8
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IESPKS_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IESPKS_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IESPKS_MSK 0x100
-
-/*
- * int_enable_flag_cold_started
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEACS (0x1<<9)
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEACS_POS 9
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEACS_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEACS_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEACS_MSK 0x200
-
-/*
- * int_enable_flag_engage
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IESWS (0x1<<10)
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IESWS_POS 10
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IESWS_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IESWS_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IESWS_MSK 0x400
-
-/*
- * int_enable_flag_watchdog_reset
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEWDS (0x1<<11)
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEWDS_POS 11
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEWDS_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEWDS_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEWDS_MSK 0x800
-
-/*
- * int_enable_flag_enbl_amp
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAMPS (0x1<<12)
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAMPS_POS 12
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAMPS_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAMPS_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAMPS_MSK 0x1000
-
-/*
- * int_enable_flag_enbl_ref
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAREFS (0x1<<13)
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAREFS_POS 13
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAREFS_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAREFS_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAREFS_MSK 0x2000
-
-/*
- * int_enable_flag_adc10_ready
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEADCCR (0x1<<14)
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEADCCR_POS 14
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEADCCR_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEADCCR_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEADCCR_MSK 0x4000
-
-/*
- * int_enable_flag_bod_vddd_nok
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEBODNOK (0x1<<15)
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEBODNOK_POS 15
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEBODNOK_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEBODNOK_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG1_IEBODNOK_MSK 0x8000
-
-
-/*
- * (0x49)-interrupt_enable_reg2
- */
-
-/*
- * int_enable_flag_bst_bstcur
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTCU (0x1<<0)
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTCU_POS 0
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTCU_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTCU_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTCU_MSK 0x1
-
-/*
- * int_enable_flag_bst_hiz
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTHI (0x1<<1)
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTHI_POS 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTHI_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTHI_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTHI_MSK 0x2
-
-/*
- * int_enable_flag_bst_ocpok
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTOC (0x1<<2)
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTOC_POS 2
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTOC_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTOC_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTOC_MSK 0x4
-
-/*
- * int_enable_flag_bst_peakcur
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTPC (0x1<<3)
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTPC_POS 3
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTPC_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTPC_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTPC_MSK 0x8
-
-/*
- * int_enable_flag_bst_voutcomp
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTVC (0x1<<4)
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTVC_POS 4
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTVC_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTVC_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTVC_MSK 0x10
-
-/*
- * int_enable_flag_bst_voutcomp86
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST86 (0x1<<5)
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST86_POS 5
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST86_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST86_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST86_MSK 0x20
-
-/*
- * int_enable_flag_bst_voutcomp93
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST93 (0x1<<6)
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST93_POS 6
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST93_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST93_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST93_MSK 0x40
-
-/*
- * int_enable_flag_rcvldop_ready
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IERCVLD (0x1<<7)
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IERCVLD_POS 7
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IERCVLD_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IERCVLD_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IERCVLD_MSK 0x80
-
-/*
- * int_enable_flag_ocp_alarm_left
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPL (0x1<<8)
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPL_POS 8
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPL_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPL_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPL_MSK 0x100
-
-/*
- * int_enable_flag_ocp_alarm_right
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPR (0x1<<9)
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPR_POS 9
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPR_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPR_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPR_MSK 0x200
-
-/*
- * int_enable_flag_man_wait_src_settings
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSRC (0x1<<10)
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSRC_POS 10
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSRC_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSRC_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSRC_MSK 0x400
-
-/*
- * int_enable_flag_man_wait_cf_config
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWCFC (0x1<<11)
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWCFC_POS 11
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWCFC_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWCFC_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWCFC_MSK 0x800
-
-/*
- * int_enable_flag_man_start_mute_audio
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSMU (0x1<<12)
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSMU_POS 12
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSMU_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSMU_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSMU_MSK 0x1000
-
-/*
- * int_enable_flag_cfma_err
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMER (0x1<<13)
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMER_POS 13
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMER_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMER_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMER_MSK 0x2000
-
-/*
- * int_enable_flag_cfma_ack
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMAC (0x1<<14)
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMAC_POS 14
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMAC_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMAC_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMAC_MSK 0x4000
-
-/*
- * int_enable_flag_clk_out_of_range
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IECLKOOR (0x1<<15)
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IECLKOOR_POS 15
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IECLKOOR_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IECLKOOR_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG2_IECLKOOR_MSK 0x8000
-
-
-/*
- * (0x4a)-interrupt_enable_reg3
- */
-
-/*
- * int_enable_flag_tdm_error
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG3_IETDMER (0x1<<0)
-#define TFA98XX_INTERRUPT_ENABLE_REG3_IETDMER_POS 0
-#define TFA98XX_INTERRUPT_ENABLE_REG3_IETDMER_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG3_IETDMER_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG3_IETDMER_MSK 0x1
-
-/*
- * int_enable_flag_clip_left
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPL (0x1<<1)
-#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPL_POS 1
-#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPL_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPL_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPL_MSK 0x2
-
-/*
- * int_enable_flag_clip_right
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPR (0x1<<2)
-#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPR_POS 2
-#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPR_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPR_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPR_MSK 0x4
-
-/*
- * int_enable_flag_mic_ocpok
- */
-#define TFA98XX_INTERRUPT_ENABLE_REG3_IEOCPM1 (0x1<<3)
-#define TFA98XX_INTERRUPT_ENABLE_REG3_IEOCPM1_POS 3
-#define TFA98XX_INTERRUPT_ENABLE_REG3_IEOCPM1_LEN 1
-#define TFA98XX_INTERRUPT_ENABLE_REG3_IEOCPM1_MAX 1
-#define TFA98XX_INTERRUPT_ENABLE_REG3_IEOCPM1_MSK 0x8
-
-
-/*
- * (0x4c)-status_polarity_reg1
- */
-
-/*
- * int_polarity_flag_por
- */
-#define TFA98XX_STATUS_POLARITY_REG1_IPOVDDS (0x1<<0)
-#define TFA98XX_STATUS_POLARITY_REG1_IPOVDDS_POS 0
-#define TFA98XX_STATUS_POLARITY_REG1_IPOVDDS_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOVDDS_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOVDDS_MSK 0x1
-
-/*
- * int_polarity_flag_pll_lock
- */
-#define TFA98XX_STATUS_POLARITY_REG1_IPOPLLS (0x1<<1)
-#define TFA98XX_STATUS_POLARITY_REG1_IPOPLLS_POS 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOPLLS_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOPLLS_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOPLLS_MSK 0x2
-
-/*
- * int_polarity_flag_otpok
- */
-#define TFA98XX_STATUS_POLARITY_REG1_IPOOTDS (0x1<<2)
-#define TFA98XX_STATUS_POLARITY_REG1_IPOOTDS_POS 2
-#define TFA98XX_STATUS_POLARITY_REG1_IPOOTDS_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOOTDS_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOOTDS_MSK 0x4
-
-/*
- * int_polarity_flag_ovpok
- */
-#define TFA98XX_STATUS_POLARITY_REG1_IPOOVDS (0x1<<3)
-#define TFA98XX_STATUS_POLARITY_REG1_IPOOVDS_POS 3
-#define TFA98XX_STATUS_POLARITY_REG1_IPOOVDS_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOOVDS_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOOVDS_MSK 0x8
-
-/*
- * int_polarity_flag_uvpok
- */
-#define TFA98XX_STATUS_POLARITY_REG1_IPOUVDS (0x1<<4)
-#define TFA98XX_STATUS_POLARITY_REG1_IPOUVDS_POS 4
-#define TFA98XX_STATUS_POLARITY_REG1_IPOUVDS_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOUVDS_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOUVDS_MSK 0x10
-
-/*
- * int_polarity_flag_clocks_stable
- */
-#define TFA98XX_STATUS_POLARITY_REG1_IPOCLKS (0x1<<5)
-#define TFA98XX_STATUS_POLARITY_REG1_IPOCLKS_POS 5
-#define TFA98XX_STATUS_POLARITY_REG1_IPOCLKS_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOCLKS_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOCLKS_MSK 0x20
-
-/*
- * int_polarity_flag_mtp_busy
- */
-#define TFA98XX_STATUS_POLARITY_REG1_IPOMTPB (0x1<<6)
-#define TFA98XX_STATUS_POLARITY_REG1_IPOMTPB_POS 6
-#define TFA98XX_STATUS_POLARITY_REG1_IPOMTPB_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOMTPB_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOMTPB_MSK 0x40
-
-/*
- * int_polarity_flag_lost_clk
- */
-#define TFA98XX_STATUS_POLARITY_REG1_IPONOCLK (0x1<<7)
-#define TFA98XX_STATUS_POLARITY_REG1_IPONOCLK_POS 7
-#define TFA98XX_STATUS_POLARITY_REG1_IPONOCLK_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPONOCLK_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPONOCLK_MSK 0x80
-
-/*
- * int_polarity_flag_cf_speakererror
- */
-#define TFA98XX_STATUS_POLARITY_REG1_IPOSPKS (0x1<<8)
-#define TFA98XX_STATUS_POLARITY_REG1_IPOSPKS_POS 8
-#define TFA98XX_STATUS_POLARITY_REG1_IPOSPKS_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOSPKS_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOSPKS_MSK 0x100
-
-/*
- * int_polarity_flag_cold_started
- */
-#define TFA98XX_STATUS_POLARITY_REG1_IPOACS (0x1<<9)
-#define TFA98XX_STATUS_POLARITY_REG1_IPOACS_POS 9
-#define TFA98XX_STATUS_POLARITY_REG1_IPOACS_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOACS_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOACS_MSK 0x200
-
-/*
- * int_polarity_flag_engage
- */
-#define TFA98XX_STATUS_POLARITY_REG1_IPOSWS (0x1<<10)
-#define TFA98XX_STATUS_POLARITY_REG1_IPOSWS_POS 10
-#define TFA98XX_STATUS_POLARITY_REG1_IPOSWS_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOSWS_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOSWS_MSK 0x400
-
-/*
- * int_polarity_flag_watchdog_reset
- */
-#define TFA98XX_STATUS_POLARITY_REG1_IPOWDS (0x1<<11)
-#define TFA98XX_STATUS_POLARITY_REG1_IPOWDS_POS 11
-#define TFA98XX_STATUS_POLARITY_REG1_IPOWDS_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOWDS_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOWDS_MSK 0x800
-
-/*
- * int_polarity_flag_enbl_amp
- */
-#define TFA98XX_STATUS_POLARITY_REG1_IPOAMPS (0x1<<12)
-#define TFA98XX_STATUS_POLARITY_REG1_IPOAMPS_POS 12
-#define TFA98XX_STATUS_POLARITY_REG1_IPOAMPS_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOAMPS_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOAMPS_MSK 0x1000
-
-/*
- * int_polarity_flag_enbl_ref
- */
-#define TFA98XX_STATUS_POLARITY_REG1_IPOAREFS (0x1<<13)
-#define TFA98XX_STATUS_POLARITY_REG1_IPOAREFS_POS 13
-#define TFA98XX_STATUS_POLARITY_REG1_IPOAREFS_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOAREFS_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOAREFS_MSK 0x2000
-
-/*
- * int_polarity_flag_adc10_ready
- */
-#define TFA98XX_STATUS_POLARITY_REG1_IPOADCCR (0x1<<14)
-#define TFA98XX_STATUS_POLARITY_REG1_IPOADCCR_POS 14
-#define TFA98XX_STATUS_POLARITY_REG1_IPOADCCR_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOADCCR_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOADCCR_MSK 0x4000
-
-/*
- * int_polarity_flag_bod_vddd_nok
- */
-#define TFA98XX_STATUS_POLARITY_REG1_IPOBODNOK (0x1<<15)
-#define TFA98XX_STATUS_POLARITY_REG1_IPOBODNOK_POS 15
-#define TFA98XX_STATUS_POLARITY_REG1_IPOBODNOK_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOBODNOK_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG1_IPOBODNOK_MSK 0x8000
-
-
-/*
- * (0x4d)-status_polarity_reg2
- */
-
-/*
- * int_polarity_flag_bst_bstcur
- */
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTCU (0x1<<0)
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTCU_POS 0
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTCU_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTCU_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTCU_MSK 0x1
-
-/*
- * int_polarity_flag_bst_hiz
- */
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTHI (0x1<<1)
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTHI_POS 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTHI_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTHI_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTHI_MSK 0x2
-
-/*
- * int_polarity_flag_bst_ocpok
- */
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTOC (0x1<<2)
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTOC_POS 2
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTOC_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTOC_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTOC_MSK 0x4
-
-/*
- * int_polarity_flag_bst_peakcur
- */
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTPC (0x1<<3)
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTPC_POS 3
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTPC_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTPC_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTPC_MSK 0x8
-
-/*
- * int_polarity_flag_bst_voutcomp
- */
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTVC (0x1<<4)
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTVC_POS 4
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTVC_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTVC_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTVC_MSK 0x10
-
-/*
- * int_polarity_flag_bst_voutcomp86
- */
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBST86 (0x1<<5)
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBST86_POS 5
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBST86_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBST86_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBST86_MSK 0x20
-
-/*
- * int_polarity_flag_bst_voutcomp93
- */
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBST93 (0x1<<6)
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBST93_POS 6
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBST93_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBST93_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOBST93_MSK 0x40
-
-/*
- * int_polarity_flag_rcvldop_ready
- */
-#define TFA98XX_STATUS_POLARITY_REG2_IPORCVLD (0x1<<7)
-#define TFA98XX_STATUS_POLARITY_REG2_IPORCVLD_POS 7
-#define TFA98XX_STATUS_POLARITY_REG2_IPORCVLD_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPORCVLD_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPORCVLD_MSK 0x80
-
-/*
- * int_polarity_flag_ocp_alarm_left
- */
-#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPL (0x1<<8)
-#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPL_POS 8
-#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPL_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPL_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPL_MSK 0x100
-
-/*
- * int_polarity_flag_ocp_alarm_right
- */
-#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPR (0x1<<9)
-#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPR_POS 9
-#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPR_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPR_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPR_MSK 0x200
-
-/*
- * int_polarity_flag_man_wait_src_settings
- */
-#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSRC (0x1<<10)
-#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSRC_POS 10
-#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSRC_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSRC_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSRC_MSK 0x400
-
-/*
- * int_polarity_flag_man_wait_cf_config
- */
-#define TFA98XX_STATUS_POLARITY_REG2_IPOMWCFC (0x1<<11)
-#define TFA98XX_STATUS_POLARITY_REG2_IPOMWCFC_POS 11
-#define TFA98XX_STATUS_POLARITY_REG2_IPOMWCFC_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOMWCFC_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOMWCFC_MSK 0x800
-
-/*
- * int_polarity_flag_man_start_mute_audio
- */
-#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSMU (0x1<<12)
-#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSMU_POS 12
-#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSMU_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSMU_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSMU_MSK 0x1000
-
-/*
- * int_polarity_flag_cfma_err
- */
-#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMER (0x1<<13)
-#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMER_POS 13
-#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMER_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMER_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMER_MSK 0x2000
-
-/*
- * int_polarity_flag_cfma_ack
- */
-#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMAC (0x1<<14)
-#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMAC_POS 14
-#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMAC_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMAC_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMAC_MSK 0x4000
-
-/*
- * int_polarity_flag_clk_out_of_range
- */
-#define TFA98XX_STATUS_POLARITY_REG2_IPCLKOOR (0x1<<15)
-#define TFA98XX_STATUS_POLARITY_REG2_IPCLKOOR_POS 15
-#define TFA98XX_STATUS_POLARITY_REG2_IPCLKOOR_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPCLKOOR_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG2_IPCLKOOR_MSK 0x8000
-
-
-/*
- * (0x4e)-status_polarity_reg3
- */
-
-/*
- * int_polarity_flag_tdm_error
- */
-#define TFA98XX_STATUS_POLARITY_REG3_IPOTDMER (0x1<<0)
-#define TFA98XX_STATUS_POLARITY_REG3_IPOTDMER_POS 0
-#define TFA98XX_STATUS_POLARITY_REG3_IPOTDMER_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG3_IPOTDMER_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG3_IPOTDMER_MSK 0x1
-
-/*
- * int_polarity_flag_clip_left
- */
-#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPL (0x1<<1)
-#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPL_POS 1
-#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPL_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPL_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPL_MSK 0x2
-
-/*
- * int_polarity_flag_clip_right
- */
-#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPR (0x1<<2)
-#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPR_POS 2
-#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPR_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPR_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPR_MSK 0x4
-
-/*
- * int_polarity_flag_mic_ocpok
- */
-#define TFA98XX_STATUS_POLARITY_REG3_IPOOCPM (0x1<<3)
-#define TFA98XX_STATUS_POLARITY_REG3_IPOOCPM_POS 3
-#define TFA98XX_STATUS_POLARITY_REG3_IPOOCPM_LEN 1
-#define TFA98XX_STATUS_POLARITY_REG3_IPOOCPM_MAX 1
-#define TFA98XX_STATUS_POLARITY_REG3_IPOOCPM_MSK 0x8
-
-
-/*
- * (0x50)-bat_prot_config
- */
-
-/*
- * vbat_prot_attack_time
- */
-#define TFA98XX_BAT_PROT_CONFIG_BSSCR (0x3<<0)
-#define TFA98XX_BAT_PROT_CONFIG_BSSCR_POS 0
-#define TFA98XX_BAT_PROT_CONFIG_BSSCR_LEN 2
-#define TFA98XX_BAT_PROT_CONFIG_BSSCR_MAX 3
-#define TFA98XX_BAT_PROT_CONFIG_BSSCR_MSK 0x3
-
-/*
- * vbat_prot_thlevel
- */
-#define TFA98XX_BAT_PROT_CONFIG_BSST (0xf<<2)
-#define TFA98XX_BAT_PROT_CONFIG_BSST_POS 2
-#define TFA98XX_BAT_PROT_CONFIG_BSST_LEN 4
-#define TFA98XX_BAT_PROT_CONFIG_BSST_MAX 15
-#define TFA98XX_BAT_PROT_CONFIG_BSST_MSK 0x3c
-
-/*
- * vbat_prot_max_reduct
- */
-#define TFA98XX_BAT_PROT_CONFIG_BSSRL (0x3<<6)
-#define TFA98XX_BAT_PROT_CONFIG_BSSRL_POS 6
-#define TFA98XX_BAT_PROT_CONFIG_BSSRL_LEN 2
-#define TFA98XX_BAT_PROT_CONFIG_BSSRL_MAX 3
-#define TFA98XX_BAT_PROT_CONFIG_BSSRL_MSK 0xc0
-
-/*
- * vbat_prot_release_time
- */
-#define TFA98XX_BAT_PROT_CONFIG_BSSRR (0x7<<8)
-#define TFA98XX_BAT_PROT_CONFIG_BSSRR_POS 8
-#define TFA98XX_BAT_PROT_CONFIG_BSSRR_LEN 3
-#define TFA98XX_BAT_PROT_CONFIG_BSSRR_MAX 7
-#define TFA98XX_BAT_PROT_CONFIG_BSSRR_MSK 0x700
-
-/*
- * vbat_prot_hysterese
- */
-#define TFA98XX_BAT_PROT_CONFIG_BSSHY (0x3<<11)
-#define TFA98XX_BAT_PROT_CONFIG_BSSHY_POS 11
-#define TFA98XX_BAT_PROT_CONFIG_BSSHY_LEN 2
-#define TFA98XX_BAT_PROT_CONFIG_BSSHY_MAX 3
-#define TFA98XX_BAT_PROT_CONFIG_BSSHY_MSK 0x1800
-
-/*
- * sel_vbat
- */
-#define TFA98XX_BAT_PROT_CONFIG_BSSR (0x1<<14)
-#define TFA98XX_BAT_PROT_CONFIG_BSSR_POS 14
-#define TFA98XX_BAT_PROT_CONFIG_BSSR_LEN 1
-#define TFA98XX_BAT_PROT_CONFIG_BSSR_MAX 1
-#define TFA98XX_BAT_PROT_CONFIG_BSSR_MSK 0x4000
-
-/*
- * bypass_clipper
- */
-#define TFA98XX_BAT_PROT_CONFIG_BSSBY (0x1<<15)
-#define TFA98XX_BAT_PROT_CONFIG_BSSBY_POS 15
-#define TFA98XX_BAT_PROT_CONFIG_BSSBY_LEN 1
-#define TFA98XX_BAT_PROT_CONFIG_BSSBY_MAX 1
-#define TFA98XX_BAT_PROT_CONFIG_BSSBY_MSK 0x8000
-
-
-/*
- * (0x51)-audio_control
- */
-
-/*
- * batsense_steepness
- */
-#define TFA98XX_AUDIO_CONTROL_BSSS (0x1<<0)
-#define TFA98XX_AUDIO_CONTROL_BSSS_POS 0
-#define TFA98XX_AUDIO_CONTROL_BSSS_LEN 1
-#define TFA98XX_AUDIO_CONTROL_BSSS_MAX 1
-#define TFA98XX_AUDIO_CONTROL_BSSS_MSK 0x1
-
-/*
- * soft_mute
- */
-#define TFA98XX_AUDIO_CONTROL_INTSMUTE (0x1<<1)
-#define TFA98XX_AUDIO_CONTROL_INTSMUTE_POS 1
-#define TFA98XX_AUDIO_CONTROL_INTSMUTE_LEN 1
-#define TFA98XX_AUDIO_CONTROL_INTSMUTE_MAX 1
-#define TFA98XX_AUDIO_CONTROL_INTSMUTE_MSK 0x2
-
-/*
- * cf_mute_left
- */
-#define TFA98XX_AUDIO_CONTROL_CFSML (0x1<<2)
-#define TFA98XX_AUDIO_CONTROL_CFSML_POS 2
-#define TFA98XX_AUDIO_CONTROL_CFSML_LEN 1
-#define TFA98XX_AUDIO_CONTROL_CFSML_MAX 1
-#define TFA98XX_AUDIO_CONTROL_CFSML_MSK 0x4
-
-/*
- * cf_mute_right
- */
-#define TFA98XX_AUDIO_CONTROL_CFSMR (0x1<<3)
-#define TFA98XX_AUDIO_CONTROL_CFSMR_POS 3
-#define TFA98XX_AUDIO_CONTROL_CFSMR_LEN 1
-#define TFA98XX_AUDIO_CONTROL_CFSMR_MAX 1
-#define TFA98XX_AUDIO_CONTROL_CFSMR_MSK 0x8
-
-/*
- * bypass_hp_left
- */
-#define TFA98XX_AUDIO_CONTROL_HPFBYPL (0x1<<4)
-#define TFA98XX_AUDIO_CONTROL_HPFBYPL_POS 4
-#define TFA98XX_AUDIO_CONTROL_HPFBYPL_LEN 1
-#define TFA98XX_AUDIO_CONTROL_HPFBYPL_MAX 1
-#define TFA98XX_AUDIO_CONTROL_HPFBYPL_MSK 0x10
-
-/*
- * bypass_hp_right
- */
-#define TFA98XX_AUDIO_CONTROL_HPFBYPR (0x1<<5)
-#define TFA98XX_AUDIO_CONTROL_HPFBYPR_POS 5
-#define TFA98XX_AUDIO_CONTROL_HPFBYPR_LEN 1
-#define TFA98XX_AUDIO_CONTROL_HPFBYPR_MAX 1
-#define TFA98XX_AUDIO_CONTROL_HPFBYPR_MSK 0x20
-
-/*
- * enbl_dpsa_left
- */
-#define TFA98XX_AUDIO_CONTROL_DPSAL (0x1<<6)
-#define TFA98XX_AUDIO_CONTROL_DPSAL_POS 6
-#define TFA98XX_AUDIO_CONTROL_DPSAL_LEN 1
-#define TFA98XX_AUDIO_CONTROL_DPSAL_MAX 1
-#define TFA98XX_AUDIO_CONTROL_DPSAL_MSK 0x40
-
-/*
- * enbl_dpsa_right
- */
-#define TFA98XX_AUDIO_CONTROL_DPSAR (0x1<<7)
-#define TFA98XX_AUDIO_CONTROL_DPSAR_POS 7
-#define TFA98XX_AUDIO_CONTROL_DPSAR_LEN 1
-#define TFA98XX_AUDIO_CONTROL_DPSAR_MAX 1
-#define TFA98XX_AUDIO_CONTROL_DPSAR_MSK 0x80
-
-/*
- * cf_volume
- */
-#define TFA98XX_AUDIO_CONTROL_VOL (0xff<<8)
-#define TFA98XX_AUDIO_CONTROL_VOL_POS 8
-#define TFA98XX_AUDIO_CONTROL_VOL_LEN 8
-#define TFA98XX_AUDIO_CONTROL_VOL_MAX 255
-#define TFA98XX_AUDIO_CONTROL_VOL_MSK 0xff00
-
-
-/*
- * (0x52)-amplifier_config
- */
-
-/*
- * ctrl_rcv
- */
-#define TFA98XX_AMPLIFIER_CONFIG_HNDSFRCV (0x1<<0)
-#define TFA98XX_AMPLIFIER_CONFIG_HNDSFRCV_POS 0
-#define TFA98XX_AMPLIFIER_CONFIG_HNDSFRCV_LEN 1
-#define TFA98XX_AMPLIFIER_CONFIG_HNDSFRCV_MAX 1
-#define TFA98XX_AMPLIFIER_CONFIG_HNDSFRCV_MSK 0x1
-
-/*
- * ctrl_cc
- */
-#define TFA98XX_AMPLIFIER_CONFIG_CLIPCTRL (0x7<<2)
-#define TFA98XX_AMPLIFIER_CONFIG_CLIPCTRL_POS 2
-#define TFA98XX_AMPLIFIER_CONFIG_CLIPCTRL_LEN 3
-#define TFA98XX_AMPLIFIER_CONFIG_CLIPCTRL_MAX 7
-#define TFA98XX_AMPLIFIER_CONFIG_CLIPCTRL_MSK 0x1c
-
-/*
- * gain
- */
-#define TFA98XX_AMPLIFIER_CONFIG_AMPGAIN (0xff<<5)
-#define TFA98XX_AMPLIFIER_CONFIG_AMPGAIN_POS 5
-#define TFA98XX_AMPLIFIER_CONFIG_AMPGAIN_LEN 8
-#define TFA98XX_AMPLIFIER_CONFIG_AMPGAIN_MAX 255
-#define TFA98XX_AMPLIFIER_CONFIG_AMPGAIN_MSK 0x1fe0
-
-/*
- * ctrl_slopectrl
- */
-#define TFA98XX_AMPLIFIER_CONFIG_SLOPEE (0x1<<13)
-#define TFA98XX_AMPLIFIER_CONFIG_SLOPEE_POS 13
-#define TFA98XX_AMPLIFIER_CONFIG_SLOPEE_LEN 1
-#define TFA98XX_AMPLIFIER_CONFIG_SLOPEE_MAX 1
-#define TFA98XX_AMPLIFIER_CONFIG_SLOPEE_MSK 0x2000
-
-/*
- * ctrl_slope
- */
-#define TFA98XX_AMPLIFIER_CONFIG_SLOPESET (0x3<<14)
-#define TFA98XX_AMPLIFIER_CONFIG_SLOPESET_POS 14
-#define TFA98XX_AMPLIFIER_CONFIG_SLOPESET_LEN 2
-#define TFA98XX_AMPLIFIER_CONFIG_SLOPESET_MAX 3
-#define TFA98XX_AMPLIFIER_CONFIG_SLOPESET_MSK 0xc000
-
-
-/*
- * (0x5a)-audio_control2
- */
-
-/*
- * cf_volume_sec
- */
-#define TFA98XX_AUDIO_CONTROL2_VOLSEC (0xff<<0)
-#define TFA98XX_AUDIO_CONTROL2_VOLSEC_POS 0
-#define TFA98XX_AUDIO_CONTROL2_VOLSEC_LEN 8
-#define TFA98XX_AUDIO_CONTROL2_VOLSEC_MAX 255
-#define TFA98XX_AUDIO_CONTROL2_VOLSEC_MSK 0xff
-
-/*
- * sw_profile
- */
-#define TFA98XX_AUDIO_CONTROL2_SWPROFIL (0xff<<8)
-#define TFA98XX_AUDIO_CONTROL2_SWPROFIL_POS 8
-#define TFA98XX_AUDIO_CONTROL2_SWPROFIL_LEN 8
-#define TFA98XX_AUDIO_CONTROL2_SWPROFIL_MAX 255
-#define TFA98XX_AUDIO_CONTROL2_SWPROFIL_MSK 0xff00
-
-
-/*
- * (0x70)-dcdc_control0
- */
-
-/*
- * boost_volt
- */
-#define TFA98XX_DCDC_CONTROL0_DCVO (0x7<<0)
-#define TFA98XX_DCDC_CONTROL0_DCVO_POS 0
-#define TFA98XX_DCDC_CONTROL0_DCVO_LEN 3
-#define TFA98XX_DCDC_CONTROL0_DCVO_MAX 7
-#define TFA98XX_DCDC_CONTROL0_DCVO_MSK 0x7
-
-/*
- * boost_cur
- */
-#define TFA98XX_DCDC_CONTROL0_DCMCC (0xf<<3)
-#define TFA98XX_DCDC_CONTROL0_DCMCC_POS 3
-#define TFA98XX_DCDC_CONTROL0_DCMCC_LEN 4
-#define TFA98XX_DCDC_CONTROL0_DCMCC_MAX 15
-#define TFA98XX_DCDC_CONTROL0_DCMCC_MSK 0x78
-
-/*
- * bst_coil_value
- */
-#define TFA98XX_DCDC_CONTROL0_DCCV (0x3<<7)
-#define TFA98XX_DCDC_CONTROL0_DCCV_POS 7
-#define TFA98XX_DCDC_CONTROL0_DCCV_LEN 2
-#define TFA98XX_DCDC_CONTROL0_DCCV_MAX 3
-#define TFA98XX_DCDC_CONTROL0_DCCV_MSK 0x180
-
-/*
- * boost_intel
- */
-#define TFA98XX_DCDC_CONTROL0_DCIE (0x1<<9)
-#define TFA98XX_DCDC_CONTROL0_DCIE_POS 9
-#define TFA98XX_DCDC_CONTROL0_DCIE_LEN 1
-#define TFA98XX_DCDC_CONTROL0_DCIE_MAX 1
-#define TFA98XX_DCDC_CONTROL0_DCIE_MSK 0x200
-
-/*
- * boost_speed
- */
-#define TFA98XX_DCDC_CONTROL0_DCSR (0x1<<10)
-#define TFA98XX_DCDC_CONTROL0_DCSR_POS 10
-#define TFA98XX_DCDC_CONTROL0_DCSR_LEN 1
-#define TFA98XX_DCDC_CONTROL0_DCSR_MAX 1
-#define TFA98XX_DCDC_CONTROL0_DCSR_MSK 0x400
-
-/*
- * dcdc_synchronisation
- */
-#define TFA98XX_DCDC_CONTROL0_DCSYNCP (0x7<<11)
-#define TFA98XX_DCDC_CONTROL0_DCSYNCP_POS 11
-#define TFA98XX_DCDC_CONTROL0_DCSYNCP_LEN 3
-#define TFA98XX_DCDC_CONTROL0_DCSYNCP_MAX 7
-#define TFA98XX_DCDC_CONTROL0_DCSYNCP_MSK 0x3800
-
-/*
- * dcdcoff_mode
- */
-#define TFA98XX_DCDC_CONTROL0_DCDIS (0x1<<14)
-#define TFA98XX_DCDC_CONTROL0_DCDIS_POS 14
-#define TFA98XX_DCDC_CONTROL0_DCDIS_LEN 1
-#define TFA98XX_DCDC_CONTROL0_DCDIS_MAX 1
-#define TFA98XX_DCDC_CONTROL0_DCDIS_MSK 0x4000
-
-
-/*
- * (0x90)-cf_controls
- */
-
-/*
- * cf_rst_dsp
- */
-#define TFA98XX_CF_CONTROLS_RST (0x1<<0)
-#define TFA98XX_CF_CONTROLS_RST_POS 0
-#define TFA98XX_CF_CONTROLS_RST_LEN 1
-#define TFA98XX_CF_CONTROLS_RST_MAX 1
-#define TFA98XX_CF_CONTROLS_RST_MSK 0x1
-
-/*
- * cf_dmem
- */
-#define TFA98XX_CF_CONTROLS_DMEM (0x3<<1)
-#define TFA98XX_CF_CONTROLS_DMEM_POS 1
-#define TFA98XX_CF_CONTROLS_DMEM_LEN 2
-#define TFA98XX_CF_CONTROLS_DMEM_MAX 3
-#define TFA98XX_CF_CONTROLS_DMEM_MSK 0x6
-
-/*
- * cf_aif
- */
-#define TFA98XX_CF_CONTROLS_AIF (0x1<<3)
-#define TFA98XX_CF_CONTROLS_AIF_POS 3
-#define TFA98XX_CF_CONTROLS_AIF_LEN 1
-#define TFA98XX_CF_CONTROLS_AIF_MAX 1
-#define TFA98XX_CF_CONTROLS_AIF_MSK 0x8
-
-/*
- * cf_int
- */
-#define TFA98XX_CF_CONTROLS_CFINT (0x1<<4)
-#define TFA98XX_CF_CONTROLS_CFINT_POS 4
-#define TFA98XX_CF_CONTROLS_CFINT_LEN 1
-#define TFA98XX_CF_CONTROLS_CFINT_MAX 1
-#define TFA98XX_CF_CONTROLS_CFINT_MSK 0x10
-
-/*
- * cf_cgate_off
- */
-#define TFA98XX_CF_CONTROLS_CFCGATE (0x1<<5)
-#define TFA98XX_CF_CONTROLS_CFCGATE_POS 5
-#define TFA98XX_CF_CONTROLS_CFCGATE_LEN 1
-#define TFA98XX_CF_CONTROLS_CFCGATE_MAX 1
-#define TFA98XX_CF_CONTROLS_CFCGATE_MSK 0x20
-
-/*
- * cf_req_cmd
- */
-#define TFA98XX_CF_CONTROLS_REQCMD (0x1<<8)
-#define TFA98XX_CF_CONTROLS_REQCMD_POS 8
-#define TFA98XX_CF_CONTROLS_REQCMD_LEN 1
-#define TFA98XX_CF_CONTROLS_REQCMD_MAX 1
-#define TFA98XX_CF_CONTROLS_REQCMD_MSK 0x100
-
-/*
- * cf_req_reset
- */
-#define TFA98XX_CF_CONTROLS_REQRST (0x1<<9)
-#define TFA98XX_CF_CONTROLS_REQRST_POS 9
-#define TFA98XX_CF_CONTROLS_REQRST_LEN 1
-#define TFA98XX_CF_CONTROLS_REQRST_MAX 1
-#define TFA98XX_CF_CONTROLS_REQRST_MSK 0x200
-
-/*
- * cf_req_mips
- */
-#define TFA98XX_CF_CONTROLS_REQMIPS (0x1<<10)
-#define TFA98XX_CF_CONTROLS_REQMIPS_POS 10
-#define TFA98XX_CF_CONTROLS_REQMIPS_LEN 1
-#define TFA98XX_CF_CONTROLS_REQMIPS_MAX 1
-#define TFA98XX_CF_CONTROLS_REQMIPS_MSK 0x400
-
-/*
- * cf_req_mute_ready
- */
-#define TFA98XX_CF_CONTROLS_REQMUTED (0x1<<11)
-#define TFA98XX_CF_CONTROLS_REQMUTED_POS 11
-#define TFA98XX_CF_CONTROLS_REQMUTED_LEN 1
-#define TFA98XX_CF_CONTROLS_REQMUTED_MAX 1
-#define TFA98XX_CF_CONTROLS_REQMUTED_MSK 0x800
-
-/*
- * cf_req_volume_ready
- */
-#define TFA98XX_CF_CONTROLS_REQVOL (0x1<<12)
-#define TFA98XX_CF_CONTROLS_REQVOL_POS 12
-#define TFA98XX_CF_CONTROLS_REQVOL_LEN 1
-#define TFA98XX_CF_CONTROLS_REQVOL_MAX 1
-#define TFA98XX_CF_CONTROLS_REQVOL_MSK 0x1000
-
-/*
- * cf_req_damage
- */
-#define TFA98XX_CF_CONTROLS_REQDMG (0x1<<13)
-#define TFA98XX_CF_CONTROLS_REQDMG_POS 13
-#define TFA98XX_CF_CONTROLS_REQDMG_LEN 1
-#define TFA98XX_CF_CONTROLS_REQDMG_MAX 1
-#define TFA98XX_CF_CONTROLS_REQDMG_MSK 0x2000
-
-/*
- * cf_req_calibrate_ready
- */
-#define TFA98XX_CF_CONTROLS_REQCAL (0x1<<14)
-#define TFA98XX_CF_CONTROLS_REQCAL_POS 14
-#define TFA98XX_CF_CONTROLS_REQCAL_LEN 1
-#define TFA98XX_CF_CONTROLS_REQCAL_MAX 1
-#define TFA98XX_CF_CONTROLS_REQCAL_MSK 0x4000
-
-/*
- * cf_req_reserved
- */
-#define TFA98XX_CF_CONTROLS_REQRSV (0x1<<15)
-#define TFA98XX_CF_CONTROLS_REQRSV_POS 15
-#define TFA98XX_CF_CONTROLS_REQRSV_LEN 1
-#define TFA98XX_CF_CONTROLS_REQRSV_MAX 1
-#define TFA98XX_CF_CONTROLS_REQRSV_MSK 0x8000
-
-
-/*
- * (0x91)-cf_mad
- */
-
-/*
- * cf_madd
- */
-#define TFA98XX_CF_MAD_MADD (0xffff<<0)
-#define TFA98XX_CF_MAD_MADD_POS 0
-#define TFA98XX_CF_MAD_MADD_LEN 16
-#define TFA98XX_CF_MAD_MADD_MAX 65535
-#define TFA98XX_CF_MAD_MADD_MSK 0xffff
-
-
-/*
- * (0x92)-cf_mem
- */
-
-/*
- * cf_mema
- */
-#define TFA98XX_CF_MEM_MEMA (0xffff<<0)
-#define TFA98XX_CF_MEM_MEMA_POS 0
-#define TFA98XX_CF_MEM_MEMA_LEN 16
-#define TFA98XX_CF_MEM_MEMA_MAX 65535
-#define TFA98XX_CF_MEM_MEMA_MSK 0xffff
-
-
-/*
- * (0x93)-cf_status
- */
-
-/*
- * cf_err
- */
-#define TFA98XX_CF_STATUS_ERR (0xff<<0)
-#define TFA98XX_CF_STATUS_ERR_POS 0
-#define TFA98XX_CF_STATUS_ERR_LEN 8
-#define TFA98XX_CF_STATUS_ERR_MAX 255
-#define TFA98XX_CF_STATUS_ERR_MSK 0xff
-
-/*
- * cf_ack_cmd
- */
-#define TFA98XX_CF_STATUS_ACKCMD (0x1<<8)
-#define TFA98XX_CF_STATUS_ACKCMD_POS 8
-#define TFA98XX_CF_STATUS_ACKCMD_LEN 1
-#define TFA98XX_CF_STATUS_ACKCMD_MAX 1
-#define TFA98XX_CF_STATUS_ACKCMD_MSK 0x100
-
-/*
- * cf_ack_reset
- */
-#define TFA98XX_CF_STATUS_ACKRST (0x1<<9)
-#define TFA98XX_CF_STATUS_ACKRST_POS 9
-#define TFA98XX_CF_STATUS_ACKRST_LEN 1
-#define TFA98XX_CF_STATUS_ACKRST_MAX 1
-#define TFA98XX_CF_STATUS_ACKRST_MSK 0x200
-
-/*
- * cf_ack_mips
- */
-#define TFA98XX_CF_STATUS_ACKMIPS (0x1<<10)
-#define TFA98XX_CF_STATUS_ACKMIPS_POS 10
-#define TFA98XX_CF_STATUS_ACKMIPS_LEN 1
-#define TFA98XX_CF_STATUS_ACKMIPS_MAX 1
-#define TFA98XX_CF_STATUS_ACKMIPS_MSK 0x400
-
-/*
- * cf_ack_mute_ready
- */
-#define TFA98XX_CF_STATUS_ACKMUTED (0x1<<11)
-#define TFA98XX_CF_STATUS_ACKMUTED_POS 11
-#define TFA98XX_CF_STATUS_ACKMUTED_LEN 1
-#define TFA98XX_CF_STATUS_ACKMUTED_MAX 1
-#define TFA98XX_CF_STATUS_ACKMUTED_MSK 0x800
-
-/*
- * cf_ack_volume_ready
- */
-#define TFA98XX_CF_STATUS_ACKVOL (0x1<<12)
-#define TFA98XX_CF_STATUS_ACKVOL_POS 12
-#define TFA98XX_CF_STATUS_ACKVOL_LEN 1
-#define TFA98XX_CF_STATUS_ACKVOL_MAX 1
-#define TFA98XX_CF_STATUS_ACKVOL_MSK 0x1000
-
-/*
- * cf_ack_damage
- */
-#define TFA98XX_CF_STATUS_ACKDMG (0x1<<13)
-#define TFA98XX_CF_STATUS_ACKDMG_POS 13
-#define TFA98XX_CF_STATUS_ACKDMG_LEN 1
-#define TFA98XX_CF_STATUS_ACKDMG_MAX 1
-#define TFA98XX_CF_STATUS_ACKDMG_MSK 0x2000
-
-/*
- * cf_ack_calibrate_ready
- */
-#define TFA98XX_CF_STATUS_ACKCAL (0x1<<14)
-#define TFA98XX_CF_STATUS_ACKCAL_POS 14
-#define TFA98XX_CF_STATUS_ACKCAL_LEN 1
-#define TFA98XX_CF_STATUS_ACKCAL_MAX 1
-#define TFA98XX_CF_STATUS_ACKCAL_MSK 0x4000
-
-/*
- * cf_ack_reserved
- */
-#define TFA98XX_CF_STATUS_ACKRSV (0x1<<15)
-#define TFA98XX_CF_STATUS_ACKRSV_POS 15
-#define TFA98XX_CF_STATUS_ACKRSV_LEN 1
-#define TFA98XX_CF_STATUS_ACKRSV_MAX 1
-#define TFA98XX_CF_STATUS_ACKRSV_MSK 0x8000
-
-
-/*
- * (0xa1)-mtpkey2_reg
- */
-
-/*
- * mtpkey2
- */
-#define TFA98XX_MTPKEY2_REG_MTPK (0xff<<0)
-#define TFA98XX_MTPKEY2_REG_MTPK_POS 0
-#define TFA98XX_MTPKEY2_REG_MTPK_LEN 8
-#define TFA98XX_MTPKEY2_REG_MTPK_MAX 255
-#define TFA98XX_MTPKEY2_REG_MTPK_MSK 0xff
-
-
-/*
- * (0xa2)-mtp_status
- */
-
-/*
- * key01_locked
- */
-#define TFA98XX_MTP_STATUS_KEY1LOCKED (0x1<<0)
-#define TFA98XX_MTP_STATUS_KEY1LOCKED_POS 0
-#define TFA98XX_MTP_STATUS_KEY1LOCKED_LEN 1
-#define TFA98XX_MTP_STATUS_KEY1LOCKED_MAX 1
-#define TFA98XX_MTP_STATUS_KEY1LOCKED_MSK 0x1
-
-/*
- * key02_locked
- */
-#define TFA98XX_MTP_STATUS_KEY2LOCKED (0x1<<1)
-#define TFA98XX_MTP_STATUS_KEY2LOCKED_POS 1
-#define TFA98XX_MTP_STATUS_KEY2LOCKED_LEN 1
-#define TFA98XX_MTP_STATUS_KEY2LOCKED_MAX 1
-#define TFA98XX_MTP_STATUS_KEY2LOCKED_MSK 0x2
-
-
-/*
- * (0xa3)-KEY_protected_mtp_control
- */
-
-/*
- * auto_copy_iic_to_mtp
- */
-#define TFA98XX_KEY_PROTECTED_MTP_CONTROL_CIMTP (0x1<<6)
-#define TFA98XX_KEY_PROTECTED_MTP_CONTROL_CIMTP_POS 6
-#define TFA98XX_KEY_PROTECTED_MTP_CONTROL_CIMTP_LEN 1
-#define TFA98XX_KEY_PROTECTED_MTP_CONTROL_CIMTP_MAX 1
-#define TFA98XX_KEY_PROTECTED_MTP_CONTROL_CIMTP_MSK 0x40
-
-
-/*
- * (0xa5)-mtp_data_out_msb
- */
-
-/*
- * mtp_man_data_out_msb
- */
-#define TFA98XX_MTP_DATA_OUT_MSB_MTPRDMSB (0xffff<<0)
-#define TFA98XX_MTP_DATA_OUT_MSB_MTPRDMSB_POS 0
-#define TFA98XX_MTP_DATA_OUT_MSB_MTPRDMSB_LEN 16
-#define TFA98XX_MTP_DATA_OUT_MSB_MTPRDMSB_MAX 65535
-#define TFA98XX_MTP_DATA_OUT_MSB_MTPRDMSB_MSK 0xffff
-
-
-/*
- * (0xa6)-mtp_data_out_lsb
- */
-
-/*
- * mtp_man_data_out_lsb
- */
-#define TFA98XX_MTP_DATA_OUT_LSB_MTPRDLSB (0xffff<<0)
-#define TFA98XX_MTP_DATA_OUT_LSB_MTPRDLSB_POS 0
-#define TFA98XX_MTP_DATA_OUT_LSB_MTPRDLSB_LEN 16
-#define TFA98XX_MTP_DATA_OUT_LSB_MTPRDLSB_MAX 65535
-#define TFA98XX_MTP_DATA_OUT_LSB_MTPRDLSB_MSK 0xffff
-
-
-/*
- * (0xb1)-temp_sensor_config
- */
-
-/*
- * ext_temp
- */
-#define TFA98XX_TEMP_SENSOR_CONFIG_EXTTS (0x1ff<<0)
-#define TFA98XX_TEMP_SENSOR_CONFIG_EXTTS_POS 0
-#define TFA98XX_TEMP_SENSOR_CONFIG_EXTTS_LEN 9
-#define TFA98XX_TEMP_SENSOR_CONFIG_EXTTS_MAX 511
-#define TFA98XX_TEMP_SENSOR_CONFIG_EXTTS_MSK 0x1ff
-
-/*
- * ext_temp_sel
- */
-#define TFA98XX_TEMP_SENSOR_CONFIG_TROS (0x1<<9)
-#define TFA98XX_TEMP_SENSOR_CONFIG_TROS_POS 9
-#define TFA98XX_TEMP_SENSOR_CONFIG_TROS_LEN 1
-#define TFA98XX_TEMP_SENSOR_CONFIG_TROS_MAX 1
-#define TFA98XX_TEMP_SENSOR_CONFIG_TROS_MSK 0x200
-
-
-/*
- * (0xf0)-KEY2_protected_MTP0
- */
-
-/*
- * calibration_onetime
- */
-#define TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC (0x1<<0)
-#define TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC_POS 0
-#define TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC_LEN 1
-#define TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC_MAX 1
-#define TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC_MSK 0x1
-
-/*
- * calibr_ron_done
- */
-#define TFA98XX_KEY2_PROTECTED_MTP0_MTPEX (0x1<<1)
-#define TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_POS 1
-#define TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_LEN 1
-#define TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_MAX 1
-#define TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_MSK 0x2
-
-/*
- * calibr_dcdc_api_calibrate
- */
-#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCAPI (0x1<<2)
-#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCAPI_POS 2
-#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCAPI_LEN 1
-#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCAPI_MAX 1
-#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCAPI_MSK 0x4
-
-/*
- * calibr_dcdc_delta_sign
- */
-#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCSB (0x1<<3)
-#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCSB_POS 3
-#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCSB_LEN 1
-#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCSB_MAX 1
-#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCSB_MSK 0x8
-
-/*
- * calibr_dcdc_delta
- */
-#define TFA98XX_KEY2_PROTECTED_MTP0_USERDEF (0x7<<4)
-#define TFA98XX_KEY2_PROTECTED_MTP0_USERDEF_POS 4
-#define TFA98XX_KEY2_PROTECTED_MTP0_USERDEF_LEN 3
-#define TFA98XX_KEY2_PROTECTED_MTP0_USERDEF_MAX 7
-#define TFA98XX_KEY2_PROTECTED_MTP0_USERDEF_MSK 0x70
-
-
-/*
- * (0xf4)-KEY1_protected_MTP4
- */
-
-
-/*
- * (0xf5)-KEY1_protected_MTP5
- */
-
-#endif /* TFA98XX_GENREGS_H */
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef TFA2_GENREGS_H
+#define TFA2_GENREGS_H
+
+
+#define TFA98XX_SYS_CONTROL0 0x00
+#define TFA98XX_SYS_CONTROL1 0x01
+#define TFA98XX_SYS_CONTROL2 0x02
+#define TFA98XX_DEVICE_REVISION 0x03
+#define TFA98XX_CLOCK_CONTROL 0x04
+#define TFA98XX_CLOCK_GATING_CONTROL 0x05
+#define TFA98XX_SIDE_TONE_CONFIG 0x0d
+#define TFA98XX_CTRL_DIGTOANA_REG 0x0e
+#define TFA98XX_STATUS_FLAGS0 0x10
+#define TFA98XX_STATUS_FLAGS1 0x11
+#define TFA98XX_STATUS_FLAGS2 0x12
+#define TFA98XX_STATUS_FLAGS3 0x13
+#define TFA98XX_STATUS_FLAGS4 0x14
+#define TFA98XX_BATTERY_VOLTAGE 0x15
+#define TFA98XX_TEMPERATURE 0x16
+#define TFA98XX_TDM_CONFIG0 0x20
+#define TFA98XX_TDM_CONFIG1 0x21
+#define TFA98XX_TDM_CONFIG2 0x22
+#define TFA98XX_TDM_CONFIG3 0x23
+#define TFA98XX_TDM_CONFIG4 0x24
+#define TFA98XX_TDM_CONFIG5 0x25
+#define TFA98XX_TDM_CONFIG6 0x26
+#define TFA98XX_TDM_CONFIG7 0x27
+#define TFA98XX_TDM_CONFIG8 0x28
+#define TFA98XX_TDM_CONFIG9 0x29
+#define TFA98XX_PDM_CONFIG0 0x31
+#define TFA98XX_PDM_CONFIG1 0x32
+#define TFA98XX_HAPTIC_DRIVER_CONFIG 0x33
+#define TFA98XX_GPIO_DATAIN_REG 0x34
+#define TFA98XX_GPIO_CONFIG 0x35
+#define TFA98XX_INTERRUPT_OUT_REG1 0x40
+#define TFA98XX_INTERRUPT_OUT_REG2 0x41
+#define TFA98XX_INTERRUPT_OUT_REG3 0x42
+#define TFA98XX_INTERRUPT_IN_REG1 0x44
+#define TFA98XX_INTERRUPT_IN_REG2 0x45
+#define TFA98XX_INTERRUPT_IN_REG3 0x46
+#define TFA98XX_INTERRUPT_ENABLE_REG1 0x48
+#define TFA98XX_INTERRUPT_ENABLE_REG2 0x49
+#define TFA98XX_INTERRUPT_ENABLE_REG3 0x4a
+#define TFA98XX_STATUS_POLARITY_REG1 0x4c
+#define TFA98XX_STATUS_POLARITY_REG2 0x4d
+#define TFA98XX_STATUS_POLARITY_REG3 0x4e
+#define TFA98XX_BAT_PROT_CONFIG 0x50
+#define TFA98XX_AUDIO_CONTROL 0x51
+#define TFA98XX_AMPLIFIER_CONFIG 0x52
+#define TFA98XX_AUDIO_CONTROL2 0x5a
+#define TFA98XX_DCDC_CONTROL0 0x70
+#define TFA98XX_CF_CONTROLS 0x90
+#define TFA98XX_CF_MAD 0x91
+#define TFA98XX_CF_MEM 0x92
+#define TFA98XX_CF_STATUS 0x93
+#define TFA98XX_MTPKEY2_REG 0xa1
+#define TFA98XX_MTP_STATUS 0xa2
+#define TFA98XX_KEY_PROTECTED_MTP_CONTROL 0xa3
+#define TFA98XX_MTP_DATA_OUT_MSB 0xa5
+#define TFA98XX_MTP_DATA_OUT_LSB 0xa6
+#define TFA98XX_TEMP_SENSOR_CONFIG 0xb1
+#define TFA98XX_KEY2_PROTECTED_MTP0 0xf0
+#define TFA98XX_KEY1_PROTECTED_MTP4 0xf4
+#define TFA98XX_KEY1_PROTECTED_MTP5 0xf5
+
+/*
+ * (0x00)-sys_control0
+ */
+
+/*
+ * powerdown
+ */
+#define TFA98XX_SYS_CONTROL0_PWDN (0x1<<0)
+#define TFA98XX_SYS_CONTROL0_PWDN_POS 0
+#define TFA98XX_SYS_CONTROL0_PWDN_LEN 1
+#define TFA98XX_SYS_CONTROL0_PWDN_MAX 1
+#define TFA98XX_SYS_CONTROL0_PWDN_MSK 0x1
+
+/*
+ * reset
+ */
+#define TFA98XX_SYS_CONTROL0_I2CR (0x1<<1)
+#define TFA98XX_SYS_CONTROL0_I2CR_POS 1
+#define TFA98XX_SYS_CONTROL0_I2CR_LEN 1
+#define TFA98XX_SYS_CONTROL0_I2CR_MAX 1
+#define TFA98XX_SYS_CONTROL0_I2CR_MSK 0x2
+
+/*
+ * enbl_coolflux
+ */
+#define TFA98XX_SYS_CONTROL0_CFE (0x1<<2)
+#define TFA98XX_SYS_CONTROL0_CFE_POS 2
+#define TFA98XX_SYS_CONTROL0_CFE_LEN 1
+#define TFA98XX_SYS_CONTROL0_CFE_MAX 1
+#define TFA98XX_SYS_CONTROL0_CFE_MSK 0x4
+
+/*
+ * enbl_amplifier
+ */
+#define TFA98XX_SYS_CONTROL0_AMPE (0x1<<3)
+#define TFA98XX_SYS_CONTROL0_AMPE_POS 3
+#define TFA98XX_SYS_CONTROL0_AMPE_LEN 1
+#define TFA98XX_SYS_CONTROL0_AMPE_MAX 1
+#define TFA98XX_SYS_CONTROL0_AMPE_MSK 0x8
+
+/*
+ * enbl_boost
+ */
+#define TFA98XX_SYS_CONTROL0_DCA (0x1<<4)
+#define TFA98XX_SYS_CONTROL0_DCA_POS 4
+#define TFA98XX_SYS_CONTROL0_DCA_LEN 1
+#define TFA98XX_SYS_CONTROL0_DCA_MAX 1
+#define TFA98XX_SYS_CONTROL0_DCA_MSK 0x10
+
+/*
+ * coolflux_configured
+ */
+#define TFA98XX_SYS_CONTROL0_SBSL (0x1<<5)
+#define TFA98XX_SYS_CONTROL0_SBSL_POS 5
+#define TFA98XX_SYS_CONTROL0_SBSL_LEN 1
+#define TFA98XX_SYS_CONTROL0_SBSL_MAX 1
+#define TFA98XX_SYS_CONTROL0_SBSL_MSK 0x20
+
+/*
+ * sel_enbl_amplifier
+ */
+#define TFA98XX_SYS_CONTROL0_AMPC (0x1<<6)
+#define TFA98XX_SYS_CONTROL0_AMPC_POS 6
+#define TFA98XX_SYS_CONTROL0_AMPC_LEN 1
+#define TFA98XX_SYS_CONTROL0_AMPC_MAX 1
+#define TFA98XX_SYS_CONTROL0_AMPC_MSK 0x40
+
+/*
+ * int_pad_io
+ */
+#define TFA98XX_SYS_CONTROL0_INTP (0x3<<7)
+#define TFA98XX_SYS_CONTROL0_INTP_POS 7
+#define TFA98XX_SYS_CONTROL0_INTP_LEN 2
+#define TFA98XX_SYS_CONTROL0_INTP_MAX 3
+#define TFA98XX_SYS_CONTROL0_INTP_MSK 0x180
+
+/*
+ * fs_pulse_sel
+ */
+#define TFA98XX_SYS_CONTROL0_FSSSEL (0x3<<9)
+#define TFA98XX_SYS_CONTROL0_FSSSEL_POS 9
+#define TFA98XX_SYS_CONTROL0_FSSSEL_LEN 2
+#define TFA98XX_SYS_CONTROL0_FSSSEL_MAX 3
+#define TFA98XX_SYS_CONTROL0_FSSSEL_MSK 0x600
+
+/*
+ * bypass_ocp
+ */
+#define TFA98XX_SYS_CONTROL0_BYPOCP (0x1<<11)
+#define TFA98XX_SYS_CONTROL0_BYPOCP_POS 11
+#define TFA98XX_SYS_CONTROL0_BYPOCP_LEN 1
+#define TFA98XX_SYS_CONTROL0_BYPOCP_MAX 1
+#define TFA98XX_SYS_CONTROL0_BYPOCP_MSK 0x800
+
+/*
+ * test_ocp
+ */
+#define TFA98XX_SYS_CONTROL0_TSTOCP (0x1<<12)
+#define TFA98XX_SYS_CONTROL0_TSTOCP_POS 12
+#define TFA98XX_SYS_CONTROL0_TSTOCP_LEN 1
+#define TFA98XX_SYS_CONTROL0_TSTOCP_MAX 1
+#define TFA98XX_SYS_CONTROL0_TSTOCP_MSK 0x1000
+
+
+/*
+ * (0x01)-sys_control1
+ */
+
+/*
+ * vamp_sel
+ */
+#define TFA98XX_SYS_CONTROL1_AMPINSEL (0x3<<0)
+#define TFA98XX_SYS_CONTROL1_AMPINSEL_POS 0
+#define TFA98XX_SYS_CONTROL1_AMPINSEL_LEN 2
+#define TFA98XX_SYS_CONTROL1_AMPINSEL_MAX 3
+#define TFA98XX_SYS_CONTROL1_AMPINSEL_MSK 0x3
+
+/*
+ * src_set_configured
+ */
+#define TFA98XX_SYS_CONTROL1_MANSCONF (0x1<<2)
+#define TFA98XX_SYS_CONTROL1_MANSCONF_POS 2
+#define TFA98XX_SYS_CONTROL1_MANSCONF_LEN 1
+#define TFA98XX_SYS_CONTROL1_MANSCONF_MAX 1
+#define TFA98XX_SYS_CONTROL1_MANSCONF_MSK 0x4
+
+/*
+ * execute_cold_start
+ */
+#define TFA98XX_SYS_CONTROL1_MANCOLD (0x1<<3)
+#define TFA98XX_SYS_CONTROL1_MANCOLD_POS 3
+#define TFA98XX_SYS_CONTROL1_MANCOLD_LEN 1
+#define TFA98XX_SYS_CONTROL1_MANCOLD_MAX 1
+#define TFA98XX_SYS_CONTROL1_MANCOLD_MSK 0x8
+
+/*
+ * enbl_osc1m_auto_off
+ */
+#define TFA98XX_SYS_CONTROL1_MANAOOSC (0x1<<4)
+#define TFA98XX_SYS_CONTROL1_MANAOOSC_POS 4
+#define TFA98XX_SYS_CONTROL1_MANAOOSC_LEN 1
+#define TFA98XX_SYS_CONTROL1_MANAOOSC_MAX 1
+#define TFA98XX_SYS_CONTROL1_MANAOOSC_MSK 0x10
+
+/*
+ * man_enbl_brown_out
+ */
+#define TFA98XX_SYS_CONTROL1_MANROBOD (0x1<<5)
+#define TFA98XX_SYS_CONTROL1_MANROBOD_POS 5
+#define TFA98XX_SYS_CONTROL1_MANROBOD_LEN 1
+#define TFA98XX_SYS_CONTROL1_MANROBOD_MAX 1
+#define TFA98XX_SYS_CONTROL1_MANROBOD_MSK 0x20
+
+/*
+ * enbl_bod
+ */
+#define TFA98XX_SYS_CONTROL1_BODE (0x1<<6)
+#define TFA98XX_SYS_CONTROL1_BODE_POS 6
+#define TFA98XX_SYS_CONTROL1_BODE_LEN 1
+#define TFA98XX_SYS_CONTROL1_BODE_MAX 1
+#define TFA98XX_SYS_CONTROL1_BODE_MSK 0x40
+
+/*
+ * enbl_bod_hyst
+ */
+#define TFA98XX_SYS_CONTROL1_BODHYS (0x1<<7)
+#define TFA98XX_SYS_CONTROL1_BODHYS_POS 7
+#define TFA98XX_SYS_CONTROL1_BODHYS_LEN 1
+#define TFA98XX_SYS_CONTROL1_BODHYS_MAX 1
+#define TFA98XX_SYS_CONTROL1_BODHYS_MSK 0x80
+
+/*
+ * bod_delay
+ */
+#define TFA98XX_SYS_CONTROL1_BODFILT (0x3<<8)
+#define TFA98XX_SYS_CONTROL1_BODFILT_POS 8
+#define TFA98XX_SYS_CONTROL1_BODFILT_LEN 2
+#define TFA98XX_SYS_CONTROL1_BODFILT_MAX 3
+#define TFA98XX_SYS_CONTROL1_BODFILT_MSK 0x300
+
+/*
+ * bod_lvlsel
+ */
+#define TFA98XX_SYS_CONTROL1_BODTHLVL (0x3<<10)
+#define TFA98XX_SYS_CONTROL1_BODTHLVL_POS 10
+#define TFA98XX_SYS_CONTROL1_BODTHLVL_LEN 2
+#define TFA98XX_SYS_CONTROL1_BODTHLVL_MAX 3
+#define TFA98XX_SYS_CONTROL1_BODTHLVL_MSK 0xc00
+
+/*
+ * disable_mute_time_out
+ */
+#define TFA98XX_SYS_CONTROL1_MUTETO (0x1<<13)
+#define TFA98XX_SYS_CONTROL1_MUTETO_POS 13
+#define TFA98XX_SYS_CONTROL1_MUTETO_LEN 1
+#define TFA98XX_SYS_CONTROL1_MUTETO_MAX 1
+#define TFA98XX_SYS_CONTROL1_MUTETO_MSK 0x2000
+
+/*
+ * pwm_sel_rcv_ns
+ */
+#define TFA98XX_SYS_CONTROL1_RCVNS (0x1<<14)
+#define TFA98XX_SYS_CONTROL1_RCVNS_POS 14
+#define TFA98XX_SYS_CONTROL1_RCVNS_LEN 1
+#define TFA98XX_SYS_CONTROL1_RCVNS_MAX 1
+#define TFA98XX_SYS_CONTROL1_RCVNS_MSK 0x4000
+
+/*
+ * man_enbl_watchdog
+ */
+#define TFA98XX_SYS_CONTROL1_MANWDE (0x1<<15)
+#define TFA98XX_SYS_CONTROL1_MANWDE_POS 15
+#define TFA98XX_SYS_CONTROL1_MANWDE_LEN 1
+#define TFA98XX_SYS_CONTROL1_MANWDE_MAX 1
+#define TFA98XX_SYS_CONTROL1_MANWDE_MSK 0x8000
+
+
+/*
+ * (0x02)-sys_control2
+ */
+
+/*
+ * audio_fs
+ */
+#define TFA98XX_SYS_CONTROL2_AUDFS (0xf<<0)
+#define TFA98XX_SYS_CONTROL2_AUDFS_POS 0
+#define TFA98XX_SYS_CONTROL2_AUDFS_LEN 4
+#define TFA98XX_SYS_CONTROL2_AUDFS_MAX 15
+#define TFA98XX_SYS_CONTROL2_AUDFS_MSK 0xf
+
+/*
+ * input_level
+ */
+#define TFA98XX_SYS_CONTROL2_INPLEV (0x1<<4)
+#define TFA98XX_SYS_CONTROL2_INPLEV_POS 4
+#define TFA98XX_SYS_CONTROL2_INPLEV_LEN 1
+#define TFA98XX_SYS_CONTROL2_INPLEV_MAX 1
+#define TFA98XX_SYS_CONTROL2_INPLEV_MSK 0x10
+
+/*
+ * cs_frac_delay
+ */
+#define TFA98XX_SYS_CONTROL2_FRACTDEL (0x3f<<5)
+#define TFA98XX_SYS_CONTROL2_FRACTDEL_POS 5
+#define TFA98XX_SYS_CONTROL2_FRACTDEL_LEN 6
+#define TFA98XX_SYS_CONTROL2_FRACTDEL_MAX 63
+#define TFA98XX_SYS_CONTROL2_FRACTDEL_MSK 0x7e0
+
+/*
+ * bypass_hvbat_filter
+ */
+#define TFA98XX_SYS_CONTROL2_BYPHVBF (0x1<<11)
+#define TFA98XX_SYS_CONTROL2_BYPHVBF_POS 11
+#define TFA98XX_SYS_CONTROL2_BYPHVBF_LEN 1
+#define TFA98XX_SYS_CONTROL2_BYPHVBF_MAX 1
+#define TFA98XX_SYS_CONTROL2_BYPHVBF_MSK 0x800
+
+/*
+ * ctrl_rcvldop_bypass
+ */
+#define TFA98XX_SYS_CONTROL2_LDOBYP (0x1<<12)
+#define TFA98XX_SYS_CONTROL2_LDOBYP_POS 12
+#define TFA98XX_SYS_CONTROL2_LDOBYP_LEN 1
+#define TFA98XX_SYS_CONTROL2_LDOBYP_MAX 1
+#define TFA98XX_SYS_CONTROL2_LDOBYP_MSK 0x1000
+
+
+/*
+ * (0x03)-device_revision
+ */
+
+/*
+ * device_rev
+ */
+#define TFA98XX_DEVICE_REVISION_REV (0xffff<<0)
+#define TFA98XX_DEVICE_REVISION_REV_POS 0
+#define TFA98XX_DEVICE_REVISION_REV_LEN 16
+#define TFA98XX_DEVICE_REVISION_REV_MAX 65535
+#define TFA98XX_DEVICE_REVISION_REV_MSK 0xffff
+
+
+/*
+ * (0x04)-clock_control
+ */
+
+/*
+ * pll_clkin_sel
+ */
+#define TFA98XX_CLOCK_CONTROL_REFCKEXT (0x3<<0)
+#define TFA98XX_CLOCK_CONTROL_REFCKEXT_POS 0
+#define TFA98XX_CLOCK_CONTROL_REFCKEXT_LEN 2
+#define TFA98XX_CLOCK_CONTROL_REFCKEXT_MAX 3
+#define TFA98XX_CLOCK_CONTROL_REFCKEXT_MSK 0x3
+
+/*
+ * pll_clkin_sel_osc
+ */
+#define TFA98XX_CLOCK_CONTROL_REFCKSEL (0x1<<2)
+#define TFA98XX_CLOCK_CONTROL_REFCKSEL_POS 2
+#define TFA98XX_CLOCK_CONTROL_REFCKSEL_LEN 1
+#define TFA98XX_CLOCK_CONTROL_REFCKSEL_MAX 1
+#define TFA98XX_CLOCK_CONTROL_REFCKSEL_MSK 0x4
+
+
+/*
+ * (0x05)-clock_gating_control
+ */
+
+/*
+ * enbl_spkr_ss_left
+ */
+#define TFA98XX_CLOCK_GATING_CONTROL_SSLEFTE (0x1<<0)
+#define TFA98XX_CLOCK_GATING_CONTROL_SSLEFTE_POS 0
+#define TFA98XX_CLOCK_GATING_CONTROL_SSLEFTE_LEN 1
+#define TFA98XX_CLOCK_GATING_CONTROL_SSLEFTE_MAX 1
+#define TFA98XX_CLOCK_GATING_CONTROL_SSLEFTE_MSK 0x1
+
+/*
+ * enbl_spkr_ss_right
+ */
+#define TFA98XX_CLOCK_GATING_CONTROL_SSRIGHTE (0x1<<1)
+#define TFA98XX_CLOCK_GATING_CONTROL_SSRIGHTE_POS 1
+#define TFA98XX_CLOCK_GATING_CONTROL_SSRIGHTE_LEN 1
+#define TFA98XX_CLOCK_GATING_CONTROL_SSRIGHTE_MAX 1
+#define TFA98XX_CLOCK_GATING_CONTROL_SSRIGHTE_MSK 0x2
+
+/*
+ * enbl_volsense_left
+ */
+#define TFA98XX_CLOCK_GATING_CONTROL_VSLEFTE (0x1<<2)
+#define TFA98XX_CLOCK_GATING_CONTROL_VSLEFTE_POS 2
+#define TFA98XX_CLOCK_GATING_CONTROL_VSLEFTE_LEN 1
+#define TFA98XX_CLOCK_GATING_CONTROL_VSLEFTE_MAX 1
+#define TFA98XX_CLOCK_GATING_CONTROL_VSLEFTE_MSK 0x4
+
+/*
+ * enbl_volsense_right
+ */
+#define TFA98XX_CLOCK_GATING_CONTROL_VSRIGHTE (0x1<<3)
+#define TFA98XX_CLOCK_GATING_CONTROL_VSRIGHTE_POS 3
+#define TFA98XX_CLOCK_GATING_CONTROL_VSRIGHTE_LEN 1
+#define TFA98XX_CLOCK_GATING_CONTROL_VSRIGHTE_MAX 1
+#define TFA98XX_CLOCK_GATING_CONTROL_VSRIGHTE_MSK 0x8
+
+/*
+ * enbl_cursense_left
+ */
+#define TFA98XX_CLOCK_GATING_CONTROL_CSLEFTE (0x1<<4)
+#define TFA98XX_CLOCK_GATING_CONTROL_CSLEFTE_POS 4
+#define TFA98XX_CLOCK_GATING_CONTROL_CSLEFTE_LEN 1
+#define TFA98XX_CLOCK_GATING_CONTROL_CSLEFTE_MAX 1
+#define TFA98XX_CLOCK_GATING_CONTROL_CSLEFTE_MSK 0x10
+
+/*
+ * enbl_cursense_right
+ */
+#define TFA98XX_CLOCK_GATING_CONTROL_CSRIGHTE (0x1<<5)
+#define TFA98XX_CLOCK_GATING_CONTROL_CSRIGHTE_POS 5
+#define TFA98XX_CLOCK_GATING_CONTROL_CSRIGHTE_LEN 1
+#define TFA98XX_CLOCK_GATING_CONTROL_CSRIGHTE_MAX 1
+#define TFA98XX_CLOCK_GATING_CONTROL_CSRIGHTE_MSK 0x20
+
+/*
+ * enbl_pdm_ss
+ */
+#define TFA98XX_CLOCK_GATING_CONTROL_SSPDME (0x1<<6)
+#define TFA98XX_CLOCK_GATING_CONTROL_SSPDME_POS 6
+#define TFA98XX_CLOCK_GATING_CONTROL_SSPDME_LEN 1
+#define TFA98XX_CLOCK_GATING_CONTROL_SSPDME_MAX 1
+#define TFA98XX_CLOCK_GATING_CONTROL_SSPDME_MSK 0x40
+
+
+/*
+ * (0x0d)-side_tone_config
+ */
+
+/*
+ * side_tone_gain
+ */
+#define TFA98XX_SIDE_TONE_CONFIG_STGAIN (0x1ff<<1)
+#define TFA98XX_SIDE_TONE_CONFIG_STGAIN_POS 1
+#define TFA98XX_SIDE_TONE_CONFIG_STGAIN_LEN 9
+#define TFA98XX_SIDE_TONE_CONFIG_STGAIN_MAX 511
+#define TFA98XX_SIDE_TONE_CONFIG_STGAIN_MSK 0x3fe
+
+/*
+ * mute_side_tone
+ */
+#define TFA98XX_SIDE_TONE_CONFIG_PDMSMUTE (0x1<<10)
+#define TFA98XX_SIDE_TONE_CONFIG_PDMSMUTE_POS 10
+#define TFA98XX_SIDE_TONE_CONFIG_PDMSMUTE_LEN 1
+#define TFA98XX_SIDE_TONE_CONFIG_PDMSMUTE_MAX 1
+#define TFA98XX_SIDE_TONE_CONFIG_PDMSMUTE_MSK 0x400
+
+
+/*
+ * (0x0e)-ctrl_digtoana_reg
+ */
+
+/*
+ * ctrl_digtoana
+ */
+#define TFA98XX_CTRL_DIGTOANA_REG_SWVSTEP (0x7f<<0)
+#define TFA98XX_CTRL_DIGTOANA_REG_SWVSTEP_POS 0
+#define TFA98XX_CTRL_DIGTOANA_REG_SWVSTEP_LEN 7
+#define TFA98XX_CTRL_DIGTOANA_REG_SWVSTEP_MAX 127
+#define TFA98XX_CTRL_DIGTOANA_REG_SWVSTEP_MSK 0x7f
+
+
+/*
+ * (0x10)-status_flags0
+ */
+
+/*
+ * flag_por
+ */
+#define TFA98XX_STATUS_FLAGS0_VDDS (0x1<<0)
+#define TFA98XX_STATUS_FLAGS0_VDDS_POS 0
+#define TFA98XX_STATUS_FLAGS0_VDDS_LEN 1
+#define TFA98XX_STATUS_FLAGS0_VDDS_MAX 1
+#define TFA98XX_STATUS_FLAGS0_VDDS_MSK 0x1
+
+/*
+ * flag_pll_lock
+ */
+#define TFA98XX_STATUS_FLAGS0_PLLS (0x1<<1)
+#define TFA98XX_STATUS_FLAGS0_PLLS_POS 1
+#define TFA98XX_STATUS_FLAGS0_PLLS_LEN 1
+#define TFA98XX_STATUS_FLAGS0_PLLS_MAX 1
+#define TFA98XX_STATUS_FLAGS0_PLLS_MSK 0x2
+
+/*
+ * flag_otpok
+ */
+#define TFA98XX_STATUS_FLAGS0_OTDS (0x1<<2)
+#define TFA98XX_STATUS_FLAGS0_OTDS_POS 2
+#define TFA98XX_STATUS_FLAGS0_OTDS_LEN 1
+#define TFA98XX_STATUS_FLAGS0_OTDS_MAX 1
+#define TFA98XX_STATUS_FLAGS0_OTDS_MSK 0x4
+
+/*
+ * flag_ovpok
+ */
+#define TFA98XX_STATUS_FLAGS0_OVDS (0x1<<3)
+#define TFA98XX_STATUS_FLAGS0_OVDS_POS 3
+#define TFA98XX_STATUS_FLAGS0_OVDS_LEN 1
+#define TFA98XX_STATUS_FLAGS0_OVDS_MAX 1
+#define TFA98XX_STATUS_FLAGS0_OVDS_MSK 0x8
+
+/*
+ * flag_uvpok
+ */
+#define TFA98XX_STATUS_FLAGS0_UVDS (0x1<<4)
+#define TFA98XX_STATUS_FLAGS0_UVDS_POS 4
+#define TFA98XX_STATUS_FLAGS0_UVDS_LEN 1
+#define TFA98XX_STATUS_FLAGS0_UVDS_MAX 1
+#define TFA98XX_STATUS_FLAGS0_UVDS_MSK 0x10
+
+/*
+ * flag_clocks_stable
+ */
+#define TFA98XX_STATUS_FLAGS0_CLKS (0x1<<6)
+#define TFA98XX_STATUS_FLAGS0_CLKS_POS 5
+#define TFA98XX_STATUS_FLAGS0_CLKS_LEN 1
+#define TFA98XX_STATUS_FLAGS0_CLKS_MAX 1
+#define TFA98XX_STATUS_FLAGS0_CLKS_MSK 0x20
+
+/*
+ * flag_mtp_busy
+ */
+#define TFA98XX_STATUS_FLAGS0_MTPB (0x1<<6)
+#define TFA98XX_STATUS_FLAGS0_MTPB_POS 6
+#define TFA98XX_STATUS_FLAGS0_MTPB_LEN 1
+#define TFA98XX_STATUS_FLAGS0_MTPB_MAX 1
+#define TFA98XX_STATUS_FLAGS0_MTPB_MSK 0x40
+
+/*
+ * flag_lost_clk
+ */
+#define TFA98XX_STATUS_FLAGS0_NOCLK (0x1<<7)
+#define TFA98XX_STATUS_FLAGS0_NOCLK_POS 7
+#define TFA98XX_STATUS_FLAGS0_NOCLK_LEN 1
+#define TFA98XX_STATUS_FLAGS0_NOCLK_MAX 1
+#define TFA98XX_STATUS_FLAGS0_NOCLK_MSK 0x80
+
+/*
+ * flag_cf_speakererror
+ */
+#define TFA98XX_STATUS_FLAGS0_SPKS (0x1<<8)
+#define TFA98XX_STATUS_FLAGS0_SPKS_POS 8
+#define TFA98XX_STATUS_FLAGS0_SPKS_LEN 1
+#define TFA98XX_STATUS_FLAGS0_SPKS_MAX 1
+#define TFA98XX_STATUS_FLAGS0_SPKS_MSK 0x100
+
+/*
+ * flag_cold_started
+ */
+#define TFA98XX_STATUS_FLAGS0_ACS (0x1<<9)
+#define TFA98XX_STATUS_FLAGS0_ACS_POS 9
+#define TFA98XX_STATUS_FLAGS0_ACS_LEN 1
+#define TFA98XX_STATUS_FLAGS0_ACS_MAX 1
+#define TFA98XX_STATUS_FLAGS0_ACS_MSK 0x200
+
+/*
+ * flag_engage
+ */
+#define TFA98XX_STATUS_FLAGS0_SWS (0x1<<10)
+#define TFA98XX_STATUS_FLAGS0_SWS_POS 10
+#define TFA98XX_STATUS_FLAGS0_SWS_LEN 1
+#define TFA98XX_STATUS_FLAGS0_SWS_MAX 1
+#define TFA98XX_STATUS_FLAGS0_SWS_MSK 0x400
+
+/*
+ * flag_watchdog_reset
+ */
+#define TFA98XX_STATUS_FLAGS0_WDS (0x1<<11)
+#define TFA98XX_STATUS_FLAGS0_WDS_POS 11
+#define TFA98XX_STATUS_FLAGS0_WDS_LEN 1
+#define TFA98XX_STATUS_FLAGS0_WDS_MAX 1
+#define TFA98XX_STATUS_FLAGS0_WDS_MSK 0x800
+
+/*
+ * flag_enbl_amp
+ */
+#define TFA98XX_STATUS_FLAGS0_AMPS (0x1<<12)
+#define TFA98XX_STATUS_FLAGS0_AMPS_POS 12
+#define TFA98XX_STATUS_FLAGS0_AMPS_LEN 1
+#define TFA98XX_STATUS_FLAGS0_AMPS_MAX 1
+#define TFA98XX_STATUS_FLAGS0_AMPS_MSK 0x1000
+
+/*
+ * flag_enbl_ref
+ */
+#define TFA98XX_STATUS_FLAGS0_AREFS (0x1<<13)
+#define TFA98XX_STATUS_FLAGS0_AREFS_POS 13
+#define TFA98XX_STATUS_FLAGS0_AREFS_LEN 1
+#define TFA98XX_STATUS_FLAGS0_AREFS_MAX 1
+#define TFA98XX_STATUS_FLAGS0_AREFS_MSK 0x2000
+
+/*
+ * flag_adc10_ready
+ */
+#define TFA98XX_STATUS_FLAGS0_ADCCR (0x1<<14)
+#define TFA98XX_STATUS_FLAGS0_ADCCR_POS 14
+#define TFA98XX_STATUS_FLAGS0_ADCCR_LEN 1
+#define TFA98XX_STATUS_FLAGS0_ADCCR_MAX 1
+#define TFA98XX_STATUS_FLAGS0_ADCCR_MSK 0x4000
+
+/*
+ * flag_bod_vddd_nok
+ */
+#define TFA98XX_STATUS_FLAGS0_BODNOK (0x1<<15)
+#define TFA98XX_STATUS_FLAGS0_BODNOK_POS 15
+#define TFA98XX_STATUS_FLAGS0_BODNOK_LEN 1
+#define TFA98XX_STATUS_FLAGS0_BODNOK_MAX 1
+#define TFA98XX_STATUS_FLAGS0_BODNOK_MSK 0x8000
+
+
+/*
+ * (0x11)-status_flags1
+ */
+
+/*
+ * flag_bst_bstcur
+ */
+#define TFA98XX_STATUS_FLAGS1_DCIL (0x1<<0)
+#define TFA98XX_STATUS_FLAGS1_DCIL_POS 0
+#define TFA98XX_STATUS_FLAGS1_DCIL_LEN 1
+#define TFA98XX_STATUS_FLAGS1_DCIL_MAX 1
+#define TFA98XX_STATUS_FLAGS1_DCIL_MSK 0x1
+
+/*
+ * flag_bst_hiz
+ */
+#define TFA98XX_STATUS_FLAGS1_DCDCA (0x1<<1)
+#define TFA98XX_STATUS_FLAGS1_DCDCA_POS 1
+#define TFA98XX_STATUS_FLAGS1_DCDCA_LEN 1
+#define TFA98XX_STATUS_FLAGS1_DCDCA_MAX 1
+#define TFA98XX_STATUS_FLAGS1_DCDCA_MSK 0x2
+
+/*
+ * flag_bst_ocpok
+ */
+#define TFA98XX_STATUS_FLAGS1_DCOCPOK (0x1<<2)
+#define TFA98XX_STATUS_FLAGS1_DCOCPOK_POS 2
+#define TFA98XX_STATUS_FLAGS1_DCOCPOK_LEN 1
+#define TFA98XX_STATUS_FLAGS1_DCOCPOK_MAX 1
+#define TFA98XX_STATUS_FLAGS1_DCOCPOK_MSK 0x4
+
+/*
+ * flag_bst_voutcomp
+ */
+#define TFA98XX_STATUS_FLAGS1_DCHVBAT (0x1<<4)
+#define TFA98XX_STATUS_FLAGS1_DCHVBAT_POS 4
+#define TFA98XX_STATUS_FLAGS1_DCHVBAT_LEN 1
+#define TFA98XX_STATUS_FLAGS1_DCHVBAT_MAX 1
+#define TFA98XX_STATUS_FLAGS1_DCHVBAT_MSK 0x10
+
+/*
+ * flag_bst_voutcomp86
+ */
+#define TFA98XX_STATUS_FLAGS1_DCH114 (0x1<<5)
+#define TFA98XX_STATUS_FLAGS1_DCH114_POS 5
+#define TFA98XX_STATUS_FLAGS1_DCH114_LEN 1
+#define TFA98XX_STATUS_FLAGS1_DCH114_MAX 1
+#define TFA98XX_STATUS_FLAGS1_DCH114_MSK 0x20
+
+/*
+ * flag_bst_voutcomp93
+ */
+#define TFA98XX_STATUS_FLAGS1_DCH107 (0x1<<6)
+#define TFA98XX_STATUS_FLAGS1_DCH107_POS 6
+#define TFA98XX_STATUS_FLAGS1_DCH107_LEN 1
+#define TFA98XX_STATUS_FLAGS1_DCH107_MAX 1
+#define TFA98XX_STATUS_FLAGS1_DCH107_MSK 0x40
+
+/*
+ * flag_soft_mute_busy
+ */
+#define TFA98XX_STATUS_FLAGS1_STMUTEB (0x1<<7)
+#define TFA98XX_STATUS_FLAGS1_STMUTEB_POS 7
+#define TFA98XX_STATUS_FLAGS1_STMUTEB_LEN 1
+#define TFA98XX_STATUS_FLAGS1_STMUTEB_MAX 1
+#define TFA98XX_STATUS_FLAGS1_STMUTEB_MSK 0x80
+
+/*
+ * flag_soft_mute_state
+ */
+#define TFA98XX_STATUS_FLAGS1_STMUTE (0x1<<8)
+#define TFA98XX_STATUS_FLAGS1_STMUTE_POS 8
+#define TFA98XX_STATUS_FLAGS1_STMUTE_LEN 1
+#define TFA98XX_STATUS_FLAGS1_STMUTE_MAX 1
+#define TFA98XX_STATUS_FLAGS1_STMUTE_MSK 0x100
+
+/*
+ * flag_tdm_lut_error
+ */
+#define TFA98XX_STATUS_FLAGS1_TDMLUTER (0x1<<9)
+#define TFA98XX_STATUS_FLAGS1_TDMLUTER_POS 9
+#define TFA98XX_STATUS_FLAGS1_TDMLUTER_LEN 1
+#define TFA98XX_STATUS_FLAGS1_TDMLUTER_MAX 1
+#define TFA98XX_STATUS_FLAGS1_TDMLUTER_MSK 0x200
+
+/*
+ * flag_tdm_status
+ */
+#define TFA98XX_STATUS_FLAGS1_TDMSTAT (0x7<<10)
+#define TFA98XX_STATUS_FLAGS1_TDMSTAT_POS 10
+#define TFA98XX_STATUS_FLAGS1_TDMSTAT_LEN 3
+#define TFA98XX_STATUS_FLAGS1_TDMSTAT_MAX 7
+#define TFA98XX_STATUS_FLAGS1_TDMSTAT_MSK 0x1c00
+
+/*
+ * flag_tdm_error
+ */
+#define TFA98XX_STATUS_FLAGS1_TDMERR (0x1<<13)
+#define TFA98XX_STATUS_FLAGS1_TDMERR_POS 13
+#define TFA98XX_STATUS_FLAGS1_TDMERR_LEN 1
+#define TFA98XX_STATUS_FLAGS1_TDMERR_MAX 1
+#define TFA98XX_STATUS_FLAGS1_TDMERR_MSK 0x2000
+
+/*
+ * flag_haptic_busy
+ */
+#define TFA98XX_STATUS_FLAGS1_HAPTIC (0x1<<14)
+#define TFA98XX_STATUS_FLAGS1_HAPTIC_POS 14
+#define TFA98XX_STATUS_FLAGS1_HAPTIC_LEN 1
+#define TFA98XX_STATUS_FLAGS1_HAPTIC_MAX 1
+#define TFA98XX_STATUS_FLAGS1_HAPTIC_MSK 0x4000
+
+
+/*
+ * (0x12)-status_flags2
+ */
+
+/*
+ * flag_ocpokap_left
+ */
+#define TFA98XX_STATUS_FLAGS2_OCPOAPL (0x1<<0)
+#define TFA98XX_STATUS_FLAGS2_OCPOAPL_POS 0
+#define TFA98XX_STATUS_FLAGS2_OCPOAPL_LEN 1
+#define TFA98XX_STATUS_FLAGS2_OCPOAPL_MAX 1
+#define TFA98XX_STATUS_FLAGS2_OCPOAPL_MSK 0x1
+
+/*
+ * flag_ocpokan_left
+ */
+#define TFA98XX_STATUS_FLAGS2_OCPOANL (0x1<<1)
+#define TFA98XX_STATUS_FLAGS2_OCPOANL_POS 1
+#define TFA98XX_STATUS_FLAGS2_OCPOANL_LEN 1
+#define TFA98XX_STATUS_FLAGS2_OCPOANL_MAX 1
+#define TFA98XX_STATUS_FLAGS2_OCPOANL_MSK 0x2
+
+/*
+ * flag_ocpokbp_left
+ */
+#define TFA98XX_STATUS_FLAGS2_OCPOBPL (0x1<<2)
+#define TFA98XX_STATUS_FLAGS2_OCPOBPL_POS 2
+#define TFA98XX_STATUS_FLAGS2_OCPOBPL_LEN 1
+#define TFA98XX_STATUS_FLAGS2_OCPOBPL_MAX 1
+#define TFA98XX_STATUS_FLAGS2_OCPOBPL_MSK 0x4
+
+/*
+ * flag_ocpokbn_left
+ */
+#define TFA98XX_STATUS_FLAGS2_OCPOBNL (0x1<<3)
+#define TFA98XX_STATUS_FLAGS2_OCPOBNL_POS 3
+#define TFA98XX_STATUS_FLAGS2_OCPOBNL_LEN 1
+#define TFA98XX_STATUS_FLAGS2_OCPOBNL_MAX 1
+#define TFA98XX_STATUS_FLAGS2_OCPOBNL_MSK 0x8
+
+/*
+ * flag_clipa_high_left
+ */
+#define TFA98XX_STATUS_FLAGS2_CLIPAHL (0x1<<4)
+#define TFA98XX_STATUS_FLAGS2_CLIPAHL_POS 4
+#define TFA98XX_STATUS_FLAGS2_CLIPAHL_LEN 1
+#define TFA98XX_STATUS_FLAGS2_CLIPAHL_MAX 1
+#define TFA98XX_STATUS_FLAGS2_CLIPAHL_MSK 0x10
+
+/*
+ * flag_clipa_low_left
+ */
+#define TFA98XX_STATUS_FLAGS2_CLIPALL (0x1<<5)
+#define TFA98XX_STATUS_FLAGS2_CLIPALL_POS 5
+#define TFA98XX_STATUS_FLAGS2_CLIPALL_LEN 1
+#define TFA98XX_STATUS_FLAGS2_CLIPALL_MAX 1
+#define TFA98XX_STATUS_FLAGS2_CLIPALL_MSK 0x20
+
+/*
+ * flag_clipb_high_left
+ */
+#define TFA98XX_STATUS_FLAGS2_CLIPBHL (0x1<<6)
+#define TFA98XX_STATUS_FLAGS2_CLIPBHL_POS 6
+#define TFA98XX_STATUS_FLAGS2_CLIPBHL_LEN 1
+#define TFA98XX_STATUS_FLAGS2_CLIPBHL_MAX 1
+#define TFA98XX_STATUS_FLAGS2_CLIPBHL_MSK 0x40
+
+/*
+ * flag_clipb_low_left
+ */
+#define TFA98XX_STATUS_FLAGS2_CLIPBLL (0x1<<7)
+#define TFA98XX_STATUS_FLAGS2_CLIPBLL_POS 7
+#define TFA98XX_STATUS_FLAGS2_CLIPBLL_LEN 1
+#define TFA98XX_STATUS_FLAGS2_CLIPBLL_MAX 1
+#define TFA98XX_STATUS_FLAGS2_CLIPBLL_MSK 0x80
+
+/*
+ * flag_ocpokap_rcv
+ */
+#define TFA98XX_STATUS_FLAGS2_OCPOAPRC (0x1<<8)
+#define TFA98XX_STATUS_FLAGS2_OCPOAPRC_POS 8
+#define TFA98XX_STATUS_FLAGS2_OCPOAPRC_LEN 1
+#define TFA98XX_STATUS_FLAGS2_OCPOAPRC_MAX 1
+#define TFA98XX_STATUS_FLAGS2_OCPOAPRC_MSK 0x100
+
+/*
+ * flag_ocpokan_rcv
+ */
+#define TFA98XX_STATUS_FLAGS2_OCPOANRC (0x1<<9)
+#define TFA98XX_STATUS_FLAGS2_OCPOANRC_POS 9
+#define TFA98XX_STATUS_FLAGS2_OCPOANRC_LEN 1
+#define TFA98XX_STATUS_FLAGS2_OCPOANRC_MAX 1
+#define TFA98XX_STATUS_FLAGS2_OCPOANRC_MSK 0x200
+
+/*
+ * flag_ocpokbp_rcv
+ */
+#define TFA98XX_STATUS_FLAGS2_OCPOBPRC (0x1<<10)
+#define TFA98XX_STATUS_FLAGS2_OCPOBPRC_POS 10
+#define TFA98XX_STATUS_FLAGS2_OCPOBPRC_LEN 1
+#define TFA98XX_STATUS_FLAGS2_OCPOBPRC_MAX 1
+#define TFA98XX_STATUS_FLAGS2_OCPOBPRC_MSK 0x400
+
+/*
+ * flag_ocpokbn_rcv
+ */
+#define TFA98XX_STATUS_FLAGS2_OCPOBNRC (0x1<<11)
+#define TFA98XX_STATUS_FLAGS2_OCPOBNRC_POS 11
+#define TFA98XX_STATUS_FLAGS2_OCPOBNRC_LEN 1
+#define TFA98XX_STATUS_FLAGS2_OCPOBNRC_MAX 1
+#define TFA98XX_STATUS_FLAGS2_OCPOBNRC_MSK 0x800
+
+/*
+ * flag_rcvldop_ready
+ */
+#define TFA98XX_STATUS_FLAGS2_RCVLDOR (0x1<<12)
+#define TFA98XX_STATUS_FLAGS2_RCVLDOR_POS 12
+#define TFA98XX_STATUS_FLAGS2_RCVLDOR_LEN 1
+#define TFA98XX_STATUS_FLAGS2_RCVLDOR_MAX 1
+#define TFA98XX_STATUS_FLAGS2_RCVLDOR_MSK 0x1000
+
+/*
+ * flag_rcvldop_bypassready
+ */
+#define TFA98XX_STATUS_FLAGS2_RCVLDOBR (0x1<<13)
+#define TFA98XX_STATUS_FLAGS2_RCVLDOBR_POS 13
+#define TFA98XX_STATUS_FLAGS2_RCVLDOBR_LEN 1
+#define TFA98XX_STATUS_FLAGS2_RCVLDOBR_MAX 1
+#define TFA98XX_STATUS_FLAGS2_RCVLDOBR_MSK 0x2000
+
+/*
+ * flag_ocp_alarm_left
+ */
+#define TFA98XX_STATUS_FLAGS2_OCDSL (0x1<<14)
+#define TFA98XX_STATUS_FLAGS2_OCDSL_POS 14
+#define TFA98XX_STATUS_FLAGS2_OCDSL_LEN 1
+#define TFA98XX_STATUS_FLAGS2_OCDSL_MAX 1
+#define TFA98XX_STATUS_FLAGS2_OCDSL_MSK 0x4000
+
+/*
+ * flag_clip_left
+ */
+#define TFA98XX_STATUS_FLAGS2_CLIPSL (0x1<<15)
+#define TFA98XX_STATUS_FLAGS2_CLIPSL_POS 15
+#define TFA98XX_STATUS_FLAGS2_CLIPSL_LEN 1
+#define TFA98XX_STATUS_FLAGS2_CLIPSL_MAX 1
+#define TFA98XX_STATUS_FLAGS2_CLIPSL_MSK 0x8000
+
+
+/*
+ * (0x13)-status_flags3
+ */
+
+/*
+ * flag_ocpokap_right
+ */
+#define TFA98XX_STATUS_FLAGS3_OCPOAPR (0x1<<0)
+#define TFA98XX_STATUS_FLAGS3_OCPOAPR_POS 0
+#define TFA98XX_STATUS_FLAGS3_OCPOAPR_LEN 1
+#define TFA98XX_STATUS_FLAGS3_OCPOAPR_MAX 1
+#define TFA98XX_STATUS_FLAGS3_OCPOAPR_MSK 0x1
+
+/*
+ * flag_ocpokan_right
+ */
+#define TFA98XX_STATUS_FLAGS3_OCPOANR (0x1<<1)
+#define TFA98XX_STATUS_FLAGS3_OCPOANR_POS 1
+#define TFA98XX_STATUS_FLAGS3_OCPOANR_LEN 1
+#define TFA98XX_STATUS_FLAGS3_OCPOANR_MAX 1
+#define TFA98XX_STATUS_FLAGS3_OCPOANR_MSK 0x2
+
+/*
+ * flag_ocpokbp_right
+ */
+#define TFA98XX_STATUS_FLAGS3_OCPOBPR (0x1<<2)
+#define TFA98XX_STATUS_FLAGS3_OCPOBPR_POS 2
+#define TFA98XX_STATUS_FLAGS3_OCPOBPR_LEN 1
+#define TFA98XX_STATUS_FLAGS3_OCPOBPR_MAX 1
+#define TFA98XX_STATUS_FLAGS3_OCPOBPR_MSK 0x4
+
+/*
+ * flag_ocpokbn_right
+ */
+#define TFA98XX_STATUS_FLAGS3_OCPOBNR (0x1<<3)
+#define TFA98XX_STATUS_FLAGS3_OCPOBNR_POS 3
+#define TFA98XX_STATUS_FLAGS3_OCPOBNR_LEN 1
+#define TFA98XX_STATUS_FLAGS3_OCPOBNR_MAX 1
+#define TFA98XX_STATUS_FLAGS3_OCPOBNR_MSK 0x8
+
+/*
+ * flag_clipa_high_right
+ */
+#define TFA98XX_STATUS_FLAGS3_CLIPAHR (0x1<<4)
+#define TFA98XX_STATUS_FLAGS3_CLIPAHR_POS 4
+#define TFA98XX_STATUS_FLAGS3_CLIPAHR_LEN 1
+#define TFA98XX_STATUS_FLAGS3_CLIPAHR_MAX 1
+#define TFA98XX_STATUS_FLAGS3_CLIPAHR_MSK 0x10
+
+/*
+ * flag_clipa_low_right
+ */
+#define TFA98XX_STATUS_FLAGS3_CLIPALR (0x1<<5)
+#define TFA98XX_STATUS_FLAGS3_CLIPALR_POS 5
+#define TFA98XX_STATUS_FLAGS3_CLIPALR_LEN 1
+#define TFA98XX_STATUS_FLAGS3_CLIPALR_MAX 1
+#define TFA98XX_STATUS_FLAGS3_CLIPALR_MSK 0x20
+
+/*
+ * flag_clipb_high_right
+ */
+#define TFA98XX_STATUS_FLAGS3_CLIPBHR (0x1<<6)
+#define TFA98XX_STATUS_FLAGS3_CLIPBHR_POS 6
+#define TFA98XX_STATUS_FLAGS3_CLIPBHR_LEN 1
+#define TFA98XX_STATUS_FLAGS3_CLIPBHR_MAX 1
+#define TFA98XX_STATUS_FLAGS3_CLIPBHR_MSK 0x40
+
+/*
+ * flag_clipb_low_right
+ */
+#define TFA98XX_STATUS_FLAGS3_CLIPBLR (0x1<<7)
+#define TFA98XX_STATUS_FLAGS3_CLIPBLR_POS 7
+#define TFA98XX_STATUS_FLAGS3_CLIPBLR_LEN 1
+#define TFA98XX_STATUS_FLAGS3_CLIPBLR_MAX 1
+#define TFA98XX_STATUS_FLAGS3_CLIPBLR_MSK 0x80
+
+/*
+ * flag_ocp_alarm_right
+ */
+#define TFA98XX_STATUS_FLAGS3_OCDSR (0x1<<8)
+#define TFA98XX_STATUS_FLAGS3_OCDSR_POS 8
+#define TFA98XX_STATUS_FLAGS3_OCDSR_LEN 1
+#define TFA98XX_STATUS_FLAGS3_OCDSR_MAX 1
+#define TFA98XX_STATUS_FLAGS3_OCDSR_MSK 0x100
+
+/*
+ * flag_clip_right
+ */
+#define TFA98XX_STATUS_FLAGS3_CLIPSR (0x1<<9)
+#define TFA98XX_STATUS_FLAGS3_CLIPSR_POS 9
+#define TFA98XX_STATUS_FLAGS3_CLIPSR_LEN 1
+#define TFA98XX_STATUS_FLAGS3_CLIPSR_MAX 1
+#define TFA98XX_STATUS_FLAGS3_CLIPSR_MSK 0x200
+
+/*
+ * flag_mic_ocpok
+ */
+#define TFA98XX_STATUS_FLAGS3_OCPOKMC (0x1<<10)
+#define TFA98XX_STATUS_FLAGS3_OCPOKMC_POS 10
+#define TFA98XX_STATUS_FLAGS3_OCPOKMC_LEN 1
+#define TFA98XX_STATUS_FLAGS3_OCPOKMC_MAX 1
+#define TFA98XX_STATUS_FLAGS3_OCPOKMC_MSK 0x400
+
+/*
+ * flag_man_alarm_state
+ */
+#define TFA98XX_STATUS_FLAGS3_MANALARM (0x1<<11)
+#define TFA98XX_STATUS_FLAGS3_MANALARM_POS 11
+#define TFA98XX_STATUS_FLAGS3_MANALARM_LEN 1
+#define TFA98XX_STATUS_FLAGS3_MANALARM_MAX 1
+#define TFA98XX_STATUS_FLAGS3_MANALARM_MSK 0x800
+
+/*
+ * flag_man_wait_src_settings
+ */
+#define TFA98XX_STATUS_FLAGS3_MANWAIT1 (0x1<<12)
+#define TFA98XX_STATUS_FLAGS3_MANWAIT1_POS 12
+#define TFA98XX_STATUS_FLAGS3_MANWAIT1_LEN 1
+#define TFA98XX_STATUS_FLAGS3_MANWAIT1_MAX 1
+#define TFA98XX_STATUS_FLAGS3_MANWAIT1_MSK 0x1000
+
+/*
+ * flag_man_wait_cf_config
+ */
+#define TFA98XX_STATUS_FLAGS3_MANWAIT2 (0x1<<13)
+#define TFA98XX_STATUS_FLAGS3_MANWAIT2_POS 13
+#define TFA98XX_STATUS_FLAGS3_MANWAIT2_LEN 1
+#define TFA98XX_STATUS_FLAGS3_MANWAIT2_MAX 1
+#define TFA98XX_STATUS_FLAGS3_MANWAIT2_MSK 0x2000
+
+/*
+ * flag_man_start_mute_audio
+ */
+#define TFA98XX_STATUS_FLAGS3_MANMUTE (0x1<<14)
+#define TFA98XX_STATUS_FLAGS3_MANMUTE_POS 14
+#define TFA98XX_STATUS_FLAGS3_MANMUTE_LEN 1
+#define TFA98XX_STATUS_FLAGS3_MANMUTE_MAX 1
+#define TFA98XX_STATUS_FLAGS3_MANMUTE_MSK 0x4000
+
+/*
+ * flag_man_operating_state
+ */
+#define TFA98XX_STATUS_FLAGS3_MANOPER (0x1<<15)
+#define TFA98XX_STATUS_FLAGS3_MANOPER_POS 15
+#define TFA98XX_STATUS_FLAGS3_MANOPER_LEN 1
+#define TFA98XX_STATUS_FLAGS3_MANOPER_MAX 1
+#define TFA98XX_STATUS_FLAGS3_MANOPER_MSK 0x8000
+
+
+/*
+ * (0x14)-status_flags4
+ */
+
+/*
+ * flag_cf_speakererror_left
+ */
+#define TFA98XX_STATUS_FLAGS4_SPKSL (0x1<<0)
+#define TFA98XX_STATUS_FLAGS4_SPKSL_POS 0
+#define TFA98XX_STATUS_FLAGS4_SPKSL_LEN 1
+#define TFA98XX_STATUS_FLAGS4_SPKSL_MAX 1
+#define TFA98XX_STATUS_FLAGS4_SPKSL_MSK 0x1
+
+/*
+ * flag_cf_speakererror_right
+ */
+#define TFA98XX_STATUS_FLAGS4_SPKSR (0x1<<1)
+#define TFA98XX_STATUS_FLAGS4_SPKSR_POS 1
+#define TFA98XX_STATUS_FLAGS4_SPKSR_LEN 1
+#define TFA98XX_STATUS_FLAGS4_SPKSR_MAX 1
+#define TFA98XX_STATUS_FLAGS4_SPKSR_MSK 0x2
+
+/*
+ * flag_clk_out_of_range
+ */
+#define TFA98XX_STATUS_FLAGS4_CLKOOR (0x1<<2)
+#define TFA98XX_STATUS_FLAGS4_CLKOOR_POS 2
+#define TFA98XX_STATUS_FLAGS4_CLKOOR_LEN 1
+#define TFA98XX_STATUS_FLAGS4_CLKOOR_MAX 1
+#define TFA98XX_STATUS_FLAGS4_CLKOOR_MSK 0x4
+
+/*
+ * man_state
+ */
+#define TFA98XX_STATUS_FLAGS4_MANSTATE (0xf<<3)
+#define TFA98XX_STATUS_FLAGS4_MANSTATE_POS 3
+#define TFA98XX_STATUS_FLAGS4_MANSTATE_LEN 4
+#define TFA98XX_STATUS_FLAGS4_MANSTATE_MAX 15
+#define TFA98XX_STATUS_FLAGS4_MANSTATE_MSK 0x78
+
+
+/*
+ * (0x15)-battery_voltage
+ */
+
+/*
+ * bat_adc
+ */
+#define TFA98XX_BATTERY_VOLTAGE_BATS (0x3ff<<0)
+#define TFA98XX_BATTERY_VOLTAGE_BATS_POS 0
+#define TFA98XX_BATTERY_VOLTAGE_BATS_LEN 10
+#define TFA98XX_BATTERY_VOLTAGE_BATS_MAX 1023
+#define TFA98XX_BATTERY_VOLTAGE_BATS_MSK 0x3ff
+
+
+/*
+ * (0x16)-temperature
+ */
+
+/*
+ * temp_adc
+ */
+#define TFA98XX_TEMPERATURE_TEMPS (0x1ff<<0)
+#define TFA98XX_TEMPERATURE_TEMPS_POS 0
+#define TFA98XX_TEMPERATURE_TEMPS_LEN 9
+#define TFA98XX_TEMPERATURE_TEMPS_MAX 511
+#define TFA98XX_TEMPERATURE_TEMPS_MSK 0x1ff
+
+
+/*
+ * (0x20)-tdm_config0
+ */
+
+/*
+ * tdm_usecase
+ */
+#define TFA98XX_TDM_CONFIG0_TDMUC (0xf<<0)
+#define TFA98XX_TDM_CONFIG0_TDMUC_POS 0
+#define TFA98XX_TDM_CONFIG0_TDMUC_LEN 4
+#define TFA98XX_TDM_CONFIG0_TDMUC_MAX 15
+#define TFA98XX_TDM_CONFIG0_TDMUC_MSK 0xf
+
+/*
+ * tdm_enable
+ */
+#define TFA98XX_TDM_CONFIG0_TDME (0x1<<4)
+#define TFA98XX_TDM_CONFIG0_TDME_POS 4
+#define TFA98XX_TDM_CONFIG0_TDME_LEN 1
+#define TFA98XX_TDM_CONFIG0_TDME_MAX 1
+#define TFA98XX_TDM_CONFIG0_TDME_MSK 0x10
+
+/*
+ * tdm_mode
+ */
+#define TFA98XX_TDM_CONFIG0_TDMMODE (0x1<<5)
+#define TFA98XX_TDM_CONFIG0_TDMMODE_POS 5
+#define TFA98XX_TDM_CONFIG0_TDMMODE_LEN 1
+#define TFA98XX_TDM_CONFIG0_TDMMODE_MAX 1
+#define TFA98XX_TDM_CONFIG0_TDMMODE_MSK 0x20
+
+/*
+ * tdm_clk_inversion
+ */
+#define TFA98XX_TDM_CONFIG0_TDMCLINV (0x1<<6)
+#define TFA98XX_TDM_CONFIG0_TDMCLINV_POS 6
+#define TFA98XX_TDM_CONFIG0_TDMCLINV_LEN 1
+#define TFA98XX_TDM_CONFIG0_TDMCLINV_MAX 1
+#define TFA98XX_TDM_CONFIG0_TDMCLINV_MSK 0x40
+
+/*
+ * tdm_fs_ws_length
+ */
+#define TFA98XX_TDM_CONFIG0_TDMFSLN (0xf<<7)
+#define TFA98XX_TDM_CONFIG0_TDMFSLN_POS 7
+#define TFA98XX_TDM_CONFIG0_TDMFSLN_LEN 4
+#define TFA98XX_TDM_CONFIG0_TDMFSLN_MAX 15
+#define TFA98XX_TDM_CONFIG0_TDMFSLN_MSK 0x780
+
+/*
+ * tdm_fs_ws_polarity
+ */
+#define TFA98XX_TDM_CONFIG0_TDMFSPOL (0x1<<11)
+#define TFA98XX_TDM_CONFIG0_TDMFSPOL_POS 11
+#define TFA98XX_TDM_CONFIG0_TDMFSPOL_LEN 1
+#define TFA98XX_TDM_CONFIG0_TDMFSPOL_MAX 1
+#define TFA98XX_TDM_CONFIG0_TDMFSPOL_MSK 0x800
+
+/*
+ * tdm_nbck
+ */
+#define TFA98XX_TDM_CONFIG0_TDMNBCK (0xf<<12)
+#define TFA98XX_TDM_CONFIG0_TDMNBCK_POS 12
+#define TFA98XX_TDM_CONFIG0_TDMNBCK_LEN 4
+#define TFA98XX_TDM_CONFIG0_TDMNBCK_MAX 15
+#define TFA98XX_TDM_CONFIG0_TDMNBCK_MSK 0xf000
+
+
+/*
+ * (0x21)-tdm_config1
+ */
+
+/*
+ * tdm_nb_of_slots
+ */
+#define TFA98XX_TDM_CONFIG1_TDMSLOTS (0xf<<0)
+#define TFA98XX_TDM_CONFIG1_TDMSLOTS_POS 0
+#define TFA98XX_TDM_CONFIG1_TDMSLOTS_LEN 4
+#define TFA98XX_TDM_CONFIG1_TDMSLOTS_MAX 15
+#define TFA98XX_TDM_CONFIG1_TDMSLOTS_MSK 0xf
+
+/*
+ * tdm_slot_length
+ */
+#define TFA98XX_TDM_CONFIG1_TDMSLLN (0x1f<<4)
+#define TFA98XX_TDM_CONFIG1_TDMSLLN_POS 4
+#define TFA98XX_TDM_CONFIG1_TDMSLLN_LEN 5
+#define TFA98XX_TDM_CONFIG1_TDMSLLN_MAX 31
+#define TFA98XX_TDM_CONFIG1_TDMSLLN_MSK 0x1f0
+
+/*
+ * tdm_bits_remaining
+ */
+#define TFA98XX_TDM_CONFIG1_TDMBRMG (0x1f<<9)
+#define TFA98XX_TDM_CONFIG1_TDMBRMG_POS 9
+#define TFA98XX_TDM_CONFIG1_TDMBRMG_LEN 5
+#define TFA98XX_TDM_CONFIG1_TDMBRMG_MAX 31
+#define TFA98XX_TDM_CONFIG1_TDMBRMG_MSK 0x3e00
+
+/*
+ * tdm_data_delay
+ */
+#define TFA98XX_TDM_CONFIG1_TDMDEL (0x1<<14)
+#define TFA98XX_TDM_CONFIG1_TDMDEL_POS 14
+#define TFA98XX_TDM_CONFIG1_TDMDEL_LEN 1
+#define TFA98XX_TDM_CONFIG1_TDMDEL_MAX 1
+#define TFA98XX_TDM_CONFIG1_TDMDEL_MSK 0x4000
+
+/*
+ * tdm_data_adjustment
+ */
+#define TFA98XX_TDM_CONFIG1_TDMADJ (0x1<<15)
+#define TFA98XX_TDM_CONFIG1_TDMADJ_POS 15
+#define TFA98XX_TDM_CONFIG1_TDMADJ_LEN 1
+#define TFA98XX_TDM_CONFIG1_TDMADJ_MAX 1
+#define TFA98XX_TDM_CONFIG1_TDMADJ_MSK 0x8000
+
+
+/*
+ * (0x22)-tdm_config2
+ */
+
+/*
+ * tdm_audio_sample_compression
+ */
+#define TFA98XX_TDM_CONFIG2_TDMOOMP (0x3<<0)
+#define TFA98XX_TDM_CONFIG2_TDMOOMP_POS 0
+#define TFA98XX_TDM_CONFIG2_TDMOOMP_LEN 2
+#define TFA98XX_TDM_CONFIG2_TDMOOMP_MAX 3
+#define TFA98XX_TDM_CONFIG2_TDMOOMP_MSK 0x3
+
+/*
+ * tdm_sample_size
+ */
+#define TFA98XX_TDM_CONFIG2_TDMSSIZE (0x1f<<2)
+#define TFA98XX_TDM_CONFIG2_TDMSSIZE_POS 2
+#define TFA98XX_TDM_CONFIG2_TDMSSIZE_LEN 5
+#define TFA98XX_TDM_CONFIG2_TDMSSIZE_MAX 31
+#define TFA98XX_TDM_CONFIG2_TDMSSIZE_MSK 0x7c
+
+/*
+ * tdm_txdata_format
+ */
+#define TFA98XX_TDM_CONFIG2_TDMTXDFO (0x3<<7)
+#define TFA98XX_TDM_CONFIG2_TDMTXDFO_POS 7
+#define TFA98XX_TDM_CONFIG2_TDMTXDFO_LEN 2
+#define TFA98XX_TDM_CONFIG2_TDMTXDFO_MAX 3
+#define TFA98XX_TDM_CONFIG2_TDMTXDFO_MSK 0x180
+
+/*
+ * tdm_txdata_format_unused_slot_sd0
+ */
+#define TFA98XX_TDM_CONFIG2_TDMTXUS0 (0x3<<9)
+#define TFA98XX_TDM_CONFIG2_TDMTXUS0_POS 9
+#define TFA98XX_TDM_CONFIG2_TDMTXUS0_LEN 2
+#define TFA98XX_TDM_CONFIG2_TDMTXUS0_MAX 3
+#define TFA98XX_TDM_CONFIG2_TDMTXUS0_MSK 0x600
+
+/*
+ * tdm_txdata_format_unused_slot_sd1
+ */
+#define TFA98XX_TDM_CONFIG2_TDMTXUS1 (0x3<<11)
+#define TFA98XX_TDM_CONFIG2_TDMTXUS1_POS 11
+#define TFA98XX_TDM_CONFIG2_TDMTXUS1_LEN 2
+#define TFA98XX_TDM_CONFIG2_TDMTXUS1_MAX 3
+#define TFA98XX_TDM_CONFIG2_TDMTXUS1_MSK 0x1800
+
+/*
+ * tdm_txdata_format_unused_slot_sd2
+ */
+#define TFA98XX_TDM_CONFIG2_TDMTXUS2 (0x3<<13)
+#define TFA98XX_TDM_CONFIG2_TDMTXUS2_POS 13
+#define TFA98XX_TDM_CONFIG2_TDMTXUS2_LEN 2
+#define TFA98XX_TDM_CONFIG2_TDMTXUS2_MAX 3
+#define TFA98XX_TDM_CONFIG2_TDMTXUS2_MSK 0x6000
+
+
+/*
+ * (0x23)-tdm_config3
+ */
+
+/*
+ * tdm_sink1_enable
+ */
+#define TFA98XX_TDM_CONFIG3_TDMLE (0x1<<1)
+#define TFA98XX_TDM_CONFIG3_TDMLE_POS 1
+#define TFA98XX_TDM_CONFIG3_TDMLE_LEN 1
+#define TFA98XX_TDM_CONFIG3_TDMLE_MAX 1
+#define TFA98XX_TDM_CONFIG3_TDMLE_MSK 0x2
+
+/*
+ * tdm_sink2_enable
+ */
+#define TFA98XX_TDM_CONFIG3_TDMRE (0x1<<2)
+#define TFA98XX_TDM_CONFIG3_TDMRE_POS 2
+#define TFA98XX_TDM_CONFIG3_TDMRE_LEN 1
+#define TFA98XX_TDM_CONFIG3_TDMRE_MAX 1
+#define TFA98XX_TDM_CONFIG3_TDMRE_MSK 0x4
+
+/*
+ * tdm_source1_enable
+ */
+#define TFA98XX_TDM_CONFIG3_TDMVSRE (0x1<<4)
+#define TFA98XX_TDM_CONFIG3_TDMVSRE_POS 4
+#define TFA98XX_TDM_CONFIG3_TDMVSRE_LEN 1
+#define TFA98XX_TDM_CONFIG3_TDMVSRE_MAX 1
+#define TFA98XX_TDM_CONFIG3_TDMVSRE_MSK 0x10
+
+/*
+ * tdm_source2_enable
+ */
+#define TFA98XX_TDM_CONFIG3_TDMCSRE (0x1<<5)
+#define TFA98XX_TDM_CONFIG3_TDMCSRE_POS 5
+#define TFA98XX_TDM_CONFIG3_TDMCSRE_LEN 1
+#define TFA98XX_TDM_CONFIG3_TDMCSRE_MAX 1
+#define TFA98XX_TDM_CONFIG3_TDMCSRE_MSK 0x20
+
+/*
+ * tdm_source3_enable
+ */
+#define TFA98XX_TDM_CONFIG3_TDMVSLE (0x1<<6)
+#define TFA98XX_TDM_CONFIG3_TDMVSLE_POS 6
+#define TFA98XX_TDM_CONFIG3_TDMVSLE_LEN 1
+#define TFA98XX_TDM_CONFIG3_TDMVSLE_MAX 1
+#define TFA98XX_TDM_CONFIG3_TDMVSLE_MSK 0x40
+
+/*
+ * tdm_source4_enable
+ */
+#define TFA98XX_TDM_CONFIG3_TDMCSLE (0x1<<7)
+#define TFA98XX_TDM_CONFIG3_TDMCSLE_POS 7
+#define TFA98XX_TDM_CONFIG3_TDMCSLE_LEN 1
+#define TFA98XX_TDM_CONFIG3_TDMCSLE_MAX 1
+#define TFA98XX_TDM_CONFIG3_TDMCSLE_MSK 0x80
+
+/*
+ * tdm_source5_enable
+ */
+#define TFA98XX_TDM_CONFIG3_TDMCFRE (0x1<<8)
+#define TFA98XX_TDM_CONFIG3_TDMCFRE_POS 8
+#define TFA98XX_TDM_CONFIG3_TDMCFRE_LEN 1
+#define TFA98XX_TDM_CONFIG3_TDMCFRE_MAX 1
+#define TFA98XX_TDM_CONFIG3_TDMCFRE_MSK 0x100
+
+/*
+ * tdm_source6_enable
+ */
+#define TFA98XX_TDM_CONFIG3_TDMCFLE (0x1<<9)
+#define TFA98XX_TDM_CONFIG3_TDMCFLE_POS 9
+#define TFA98XX_TDM_CONFIG3_TDMCFLE_LEN 1
+#define TFA98XX_TDM_CONFIG3_TDMCFLE_MAX 1
+#define TFA98XX_TDM_CONFIG3_TDMCFLE_MSK 0x200
+
+/*
+ * tdm_source7_enable
+ */
+#define TFA98XX_TDM_CONFIG3_TDMCF3E (0x1<<10)
+#define TFA98XX_TDM_CONFIG3_TDMCF3E_POS 10
+#define TFA98XX_TDM_CONFIG3_TDMCF3E_LEN 1
+#define TFA98XX_TDM_CONFIG3_TDMCF3E_MAX 1
+#define TFA98XX_TDM_CONFIG3_TDMCF3E_MSK 0x400
+
+/*
+ * tdm_source8_enable
+ */
+#define TFA98XX_TDM_CONFIG3_TDMCF4E (0x1<<11)
+#define TFA98XX_TDM_CONFIG3_TDMCF4E_POS 11
+#define TFA98XX_TDM_CONFIG3_TDMCF4E_LEN 1
+#define TFA98XX_TDM_CONFIG3_TDMCF4E_MAX 1
+#define TFA98XX_TDM_CONFIG3_TDMCF4E_MSK 0x800
+
+/*
+ * tdm_source9_enable
+ */
+#define TFA98XX_TDM_CONFIG3_TDMPD1E (0x1<<12)
+#define TFA98XX_TDM_CONFIG3_TDMPD1E_POS 12
+#define TFA98XX_TDM_CONFIG3_TDMPD1E_LEN 1
+#define TFA98XX_TDM_CONFIG3_TDMPD1E_MAX 1
+#define TFA98XX_TDM_CONFIG3_TDMPD1E_MSK 0x1000
+
+/*
+ * tdm_source10_enable
+ */
+#define TFA98XX_TDM_CONFIG3_TDMPD2E (0x1<<13)
+#define TFA98XX_TDM_CONFIG3_TDMPD2E_POS 13
+#define TFA98XX_TDM_CONFIG3_TDMPD2E_LEN 1
+#define TFA98XX_TDM_CONFIG3_TDMPD2E_MAX 1
+#define TFA98XX_TDM_CONFIG3_TDMPD2E_MSK 0x2000
+
+
+/*
+ * (0x24)-tdm_config4
+ */
+
+/*
+ * tdm_sink1_io
+ */
+#define TFA98XX_TDM_CONFIG4_TDMLIO (0x3<<2)
+#define TFA98XX_TDM_CONFIG4_TDMLIO_POS 2
+#define TFA98XX_TDM_CONFIG4_TDMLIO_LEN 2
+#define TFA98XX_TDM_CONFIG4_TDMLIO_MAX 3
+#define TFA98XX_TDM_CONFIG4_TDMLIO_MSK 0xc
+
+/*
+ * tdm_sink2_io
+ */
+#define TFA98XX_TDM_CONFIG4_TDMRIO (0x3<<4)
+#define TFA98XX_TDM_CONFIG4_TDMRIO_POS 4
+#define TFA98XX_TDM_CONFIG4_TDMRIO_LEN 2
+#define TFA98XX_TDM_CONFIG4_TDMRIO_MAX 3
+#define TFA98XX_TDM_CONFIG4_TDMRIO_MSK 0x30
+
+/*
+ * tdm_source1_io
+ */
+#define TFA98XX_TDM_CONFIG4_TDMVSRIO (0x3<<8)
+#define TFA98XX_TDM_CONFIG4_TDMVSRIO_POS 8
+#define TFA98XX_TDM_CONFIG4_TDMVSRIO_LEN 2
+#define TFA98XX_TDM_CONFIG4_TDMVSRIO_MAX 3
+#define TFA98XX_TDM_CONFIG4_TDMVSRIO_MSK 0x300
+
+/*
+ * tdm_source2_io
+ */
+#define TFA98XX_TDM_CONFIG4_TDMCSRIO (0x3<<10)
+#define TFA98XX_TDM_CONFIG4_TDMCSRIO_POS 10
+#define TFA98XX_TDM_CONFIG4_TDMCSRIO_LEN 2
+#define TFA98XX_TDM_CONFIG4_TDMCSRIO_MAX 3
+#define TFA98XX_TDM_CONFIG4_TDMCSRIO_MSK 0xc00
+
+/*
+ * tdm_source3_io
+ */
+#define TFA98XX_TDM_CONFIG4_TDMVSLIO (0x3<<12)
+#define TFA98XX_TDM_CONFIG4_TDMVSLIO_POS 12
+#define TFA98XX_TDM_CONFIG4_TDMVSLIO_LEN 2
+#define TFA98XX_TDM_CONFIG4_TDMVSLIO_MAX 3
+#define TFA98XX_TDM_CONFIG4_TDMVSLIO_MSK 0x3000
+
+/*
+ * tdm_source4_io
+ */
+#define TFA98XX_TDM_CONFIG4_TDMCSLIO (0x3<<14)
+#define TFA98XX_TDM_CONFIG4_TDMCSLIO_POS 14
+#define TFA98XX_TDM_CONFIG4_TDMCSLIO_LEN 2
+#define TFA98XX_TDM_CONFIG4_TDMCSLIO_MAX 3
+#define TFA98XX_TDM_CONFIG4_TDMCSLIO_MSK 0xc000
+
+
+/*
+ * (0x25)-tdm_config5
+ */
+
+/*
+ * tdm_source5_io
+ */
+#define TFA98XX_TDM_CONFIG5_TDMCFRIO (0x3<<0)
+#define TFA98XX_TDM_CONFIG5_TDMCFRIO_POS 0
+#define TFA98XX_TDM_CONFIG5_TDMCFRIO_LEN 2
+#define TFA98XX_TDM_CONFIG5_TDMCFRIO_MAX 3
+#define TFA98XX_TDM_CONFIG5_TDMCFRIO_MSK 0x3
+
+/*
+ * tdm_source6_io
+ */
+#define TFA98XX_TDM_CONFIG5_TDMCFLIO (0x3<<2)
+#define TFA98XX_TDM_CONFIG5_TDMCFLIO_POS 2
+#define TFA98XX_TDM_CONFIG5_TDMCFLIO_LEN 2
+#define TFA98XX_TDM_CONFIG5_TDMCFLIO_MAX 3
+#define TFA98XX_TDM_CONFIG5_TDMCFLIO_MSK 0xc
+
+/*
+ * tdm_source7_io
+ */
+#define TFA98XX_TDM_CONFIG5_TDMCF3IO (0x3<<4)
+#define TFA98XX_TDM_CONFIG5_TDMCF3IO_POS 4
+#define TFA98XX_TDM_CONFIG5_TDMCF3IO_LEN 2
+#define TFA98XX_TDM_CONFIG5_TDMCF3IO_MAX 3
+#define TFA98XX_TDM_CONFIG5_TDMCF3IO_MSK 0x30
+
+/*
+ * tdm_source8_io
+ */
+#define TFA98XX_TDM_CONFIG5_TDMCF4IO (0x3<<6)
+#define TFA98XX_TDM_CONFIG5_TDMCF4IO_POS 6
+#define TFA98XX_TDM_CONFIG5_TDMCF4IO_LEN 2
+#define TFA98XX_TDM_CONFIG5_TDMCF4IO_MAX 3
+#define TFA98XX_TDM_CONFIG5_TDMCF4IO_MSK 0xc0
+
+/*
+ * tdm_source9_io
+ */
+#define TFA98XX_TDM_CONFIG5_TDMPD1IO (0x3<<8)
+#define TFA98XX_TDM_CONFIG5_TDMPD1IO_POS 8
+#define TFA98XX_TDM_CONFIG5_TDMPD1IO_LEN 2
+#define TFA98XX_TDM_CONFIG5_TDMPD1IO_MAX 3
+#define TFA98XX_TDM_CONFIG5_TDMPD1IO_MSK 0x300
+
+/*
+ * tdm_source10_io
+ */
+#define TFA98XX_TDM_CONFIG5_TDMPD2IO (0x3<<10)
+#define TFA98XX_TDM_CONFIG5_TDMPD2IO_POS 10
+#define TFA98XX_TDM_CONFIG5_TDMPD2IO_LEN 2
+#define TFA98XX_TDM_CONFIG5_TDMPD2IO_MAX 3
+#define TFA98XX_TDM_CONFIG5_TDMPD2IO_MSK 0xc00
+
+
+/*
+ * (0x26)-tdm_config6
+ */
+
+/*
+ * tdm_sink1_slot
+ */
+#define TFA98XX_TDM_CONFIG6_TDMLS (0xf<<4)
+#define TFA98XX_TDM_CONFIG6_TDMLS_POS 4
+#define TFA98XX_TDM_CONFIG6_TDMLS_LEN 4
+#define TFA98XX_TDM_CONFIG6_TDMLS_MAX 15
+#define TFA98XX_TDM_CONFIG6_TDMLS_MSK 0xf0
+
+/*
+ * tdm_sink2_slot
+ */
+#define TFA98XX_TDM_CONFIG6_TDMRS (0xf<<8)
+#define TFA98XX_TDM_CONFIG6_TDMRS_POS 8
+#define TFA98XX_TDM_CONFIG6_TDMRS_LEN 4
+#define TFA98XX_TDM_CONFIG6_TDMRS_MAX 15
+#define TFA98XX_TDM_CONFIG6_TDMRS_MSK 0xf00
+
+
+/*
+ * (0x27)-tdm_config7
+ */
+
+/*
+ * tdm_source1_slot
+ */
+#define TFA98XX_TDM_CONFIG7_TDMVSRS (0xf<<0)
+#define TFA98XX_TDM_CONFIG7_TDMVSRS_POS 0
+#define TFA98XX_TDM_CONFIG7_TDMVSRS_LEN 4
+#define TFA98XX_TDM_CONFIG7_TDMVSRS_MAX 15
+#define TFA98XX_TDM_CONFIG7_TDMVSRS_MSK 0xf
+
+/*
+ * tdm_source2_slot
+ */
+#define TFA98XX_TDM_CONFIG7_TDMCSRS (0xf<<4)
+#define TFA98XX_TDM_CONFIG7_TDMCSRS_POS 4
+#define TFA98XX_TDM_CONFIG7_TDMCSRS_LEN 4
+#define TFA98XX_TDM_CONFIG7_TDMCSRS_MAX 15
+#define TFA98XX_TDM_CONFIG7_TDMCSRS_MSK 0xf0
+
+/*
+ * tdm_source3_slot
+ */
+#define TFA98XX_TDM_CONFIG7_TDMVSLS (0xf<<8)
+#define TFA98XX_TDM_CONFIG7_TDMVSLS_POS 8
+#define TFA98XX_TDM_CONFIG7_TDMVSLS_LEN 4
+#define TFA98XX_TDM_CONFIG7_TDMVSLS_MAX 15
+#define TFA98XX_TDM_CONFIG7_TDMVSLS_MSK 0xf00
+
+/*
+ * tdm_source4_slot
+ */
+#define TFA98XX_TDM_CONFIG7_TDMCSLS (0xf<<12)
+#define TFA98XX_TDM_CONFIG7_TDMCSLS_POS 12
+#define TFA98XX_TDM_CONFIG7_TDMCSLS_LEN 4
+#define TFA98XX_TDM_CONFIG7_TDMCSLS_MAX 15
+#define TFA98XX_TDM_CONFIG7_TDMCSLS_MSK 0xf000
+
+
+/*
+ * (0x28)-tdm_config8
+ */
+
+/*
+ * tdm_source5_slot
+ */
+#define TFA98XX_TDM_CONFIG8_TDMCFRS (0xf<<0)
+#define TFA98XX_TDM_CONFIG8_TDMCFRS_POS 0
+#define TFA98XX_TDM_CONFIG8_TDMCFRS_LEN 4
+#define TFA98XX_TDM_CONFIG8_TDMCFRS_MAX 15
+#define TFA98XX_TDM_CONFIG8_TDMCFRS_MSK 0xf
+
+/*
+ * tdm_source6_slot
+ */
+#define TFA98XX_TDM_CONFIG8_TDMCFLS (0xf<<4)
+#define TFA98XX_TDM_CONFIG8_TDMCFLS_POS 4
+#define TFA98XX_TDM_CONFIG8_TDMCFLS_LEN 4
+#define TFA98XX_TDM_CONFIG8_TDMCFLS_MAX 15
+#define TFA98XX_TDM_CONFIG8_TDMCFLS_MSK 0xf0
+
+/*
+ * tdm_source7_slot
+ */
+#define TFA98XX_TDM_CONFIG8_TDMCF3S (0xf<<8)
+#define TFA98XX_TDM_CONFIG8_TDMCF3S_POS 8
+#define TFA98XX_TDM_CONFIG8_TDMCF3S_LEN 4
+#define TFA98XX_TDM_CONFIG8_TDMCF3S_MAX 15
+#define TFA98XX_TDM_CONFIG8_TDMCF3S_MSK 0xf00
+
+/*
+ * tdm_source8_slot
+ */
+#define TFA98XX_TDM_CONFIG8_TDMCF4S (0xf<<12)
+#define TFA98XX_TDM_CONFIG8_TDMCF4S_POS 12
+#define TFA98XX_TDM_CONFIG8_TDMCF4S_LEN 4
+#define TFA98XX_TDM_CONFIG8_TDMCF4S_MAX 15
+#define TFA98XX_TDM_CONFIG8_TDMCF4S_MSK 0xf000
+
+
+/*
+ * (0x29)-tdm_config9
+ */
+
+/*
+ * tdm_source9_slot
+ */
+#define TFA98XX_TDM_CONFIG9_TDMPD1S (0xf<<0)
+#define TFA98XX_TDM_CONFIG9_TDMPD1S_POS 0
+#define TFA98XX_TDM_CONFIG9_TDMPD1S_LEN 4
+#define TFA98XX_TDM_CONFIG9_TDMPD1S_MAX 15
+#define TFA98XX_TDM_CONFIG9_TDMPD1S_MSK 0xf
+
+/*
+ * tdm_source10_slot
+ */
+#define TFA98XX_TDM_CONFIG9_TDMPD2S (0xf<<4)
+#define TFA98XX_TDM_CONFIG9_TDMPD2S_POS 4
+#define TFA98XX_TDM_CONFIG9_TDMPD2S_LEN 4
+#define TFA98XX_TDM_CONFIG9_TDMPD2S_MAX 15
+#define TFA98XX_TDM_CONFIG9_TDMPD2S_MSK 0xf0
+
+
+/*
+ * (0x31)-pdm_config0
+ */
+
+/*
+ * pdm_mode
+ */
+#define TFA98XX_PDM_CONFIG0_PDMSM (0x1<<0)
+#define TFA98XX_PDM_CONFIG0_PDMSM_POS 0
+#define TFA98XX_PDM_CONFIG0_PDMSM_LEN 1
+#define TFA98XX_PDM_CONFIG0_PDMSM_MAX 1
+#define TFA98XX_PDM_CONFIG0_PDMSM_MSK 0x1
+
+/*
+ * pdm_side_tone_sel
+ */
+#define TFA98XX_PDM_CONFIG0_PDMSTSEL (0x3<<1)
+#define TFA98XX_PDM_CONFIG0_PDMSTSEL_POS 1
+#define TFA98XX_PDM_CONFIG0_PDMSTSEL_LEN 2
+#define TFA98XX_PDM_CONFIG0_PDMSTSEL_MAX 3
+#define TFA98XX_PDM_CONFIG0_PDMSTSEL_MSK 0x6
+
+/*
+ * pdm_left_sel
+ */
+#define TFA98XX_PDM_CONFIG0_PDMLSEL (0x1<<3)
+#define TFA98XX_PDM_CONFIG0_PDMLSEL_POS 3
+#define TFA98XX_PDM_CONFIG0_PDMLSEL_LEN 1
+#define TFA98XX_PDM_CONFIG0_PDMLSEL_MAX 1
+#define TFA98XX_PDM_CONFIG0_PDMLSEL_MSK 0x8
+
+/*
+ * pdm_right_sel
+ */
+#define TFA98XX_PDM_CONFIG0_PDMRSEL (0x1<<4)
+#define TFA98XX_PDM_CONFIG0_PDMRSEL_POS 4
+#define TFA98XX_PDM_CONFIG0_PDMRSEL_LEN 1
+#define TFA98XX_PDM_CONFIG0_PDMRSEL_MAX 1
+#define TFA98XX_PDM_CONFIG0_PDMRSEL_MSK 0x10
+
+/*
+ * enbl_micvdd
+ */
+#define TFA98XX_PDM_CONFIG0_MICVDDE (0x1<<5)
+#define TFA98XX_PDM_CONFIG0_MICVDDE_POS 5
+#define TFA98XX_PDM_CONFIG0_MICVDDE_LEN 1
+#define TFA98XX_PDM_CONFIG0_MICVDDE_MAX 1
+#define TFA98XX_PDM_CONFIG0_MICVDDE_MSK 0x20
+
+
+/*
+ * (0x32)-pdm_config1
+ */
+
+/*
+ * pdm_nbck
+ */
+#define TFA98XX_PDM_CONFIG1_PDMCLRAT (0x3<<0)
+#define TFA98XX_PDM_CONFIG1_PDMCLRAT_POS 0
+#define TFA98XX_PDM_CONFIG1_PDMCLRAT_LEN 2
+#define TFA98XX_PDM_CONFIG1_PDMCLRAT_MAX 3
+#define TFA98XX_PDM_CONFIG1_PDMCLRAT_MSK 0x3
+
+/*
+ * pdm_gain
+ */
+#define TFA98XX_PDM_CONFIG1_PDMGAIN (0xf<<2)
+#define TFA98XX_PDM_CONFIG1_PDMGAIN_POS 2
+#define TFA98XX_PDM_CONFIG1_PDMGAIN_LEN 4
+#define TFA98XX_PDM_CONFIG1_PDMGAIN_MAX 15
+#define TFA98XX_PDM_CONFIG1_PDMGAIN_MSK 0x3c
+
+/*
+ * sel_pdm_out_data
+ */
+#define TFA98XX_PDM_CONFIG1_PDMOSEL (0xf<<6)
+#define TFA98XX_PDM_CONFIG1_PDMOSEL_POS 6
+#define TFA98XX_PDM_CONFIG1_PDMOSEL_LEN 4
+#define TFA98XX_PDM_CONFIG1_PDMOSEL_MAX 15
+#define TFA98XX_PDM_CONFIG1_PDMOSEL_MSK 0x3c0
+
+/*
+ * sel_cf_haptic_data
+ */
+#define TFA98XX_PDM_CONFIG1_SELCFHAPD (0x1<<10)
+#define TFA98XX_PDM_CONFIG1_SELCFHAPD_POS 10
+#define TFA98XX_PDM_CONFIG1_SELCFHAPD_LEN 1
+#define TFA98XX_PDM_CONFIG1_SELCFHAPD_MAX 1
+#define TFA98XX_PDM_CONFIG1_SELCFHAPD_MSK 0x400
+
+
+/*
+ * (0x33)-haptic_driver_config
+ */
+
+/*
+ * haptic_duration
+ */
+#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPTIME (0xff<<0)
+#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPTIME_POS 0
+#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPTIME_LEN 8
+#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPTIME_MAX 255
+#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPTIME_MSK 0xff
+
+/*
+ * haptic_data
+ */
+#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPLEVEL (0xff<<8)
+#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPLEVEL_POS 8
+#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPLEVEL_LEN 8
+#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPLEVEL_MAX 255
+#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPLEVEL_MSK 0xff00
+
+
+/*
+ * (0x34)-gpio_datain_reg
+ */
+
+/*
+ * gpio_datain
+ */
+#define TFA98XX_GPIO_DATAIN_REG_GPIODIN (0xf<<0)
+#define TFA98XX_GPIO_DATAIN_REG_GPIODIN_POS 0
+#define TFA98XX_GPIO_DATAIN_REG_GPIODIN_LEN 4
+#define TFA98XX_GPIO_DATAIN_REG_GPIODIN_MAX 15
+#define TFA98XX_GPIO_DATAIN_REG_GPIODIN_MSK 0xf
+
+
+/*
+ * (0x35)-gpio_config
+ */
+
+/*
+ * gpio_ctrl
+ */
+#define TFA98XX_GPIO_CONFIG_GPIOCTRL (0x1<<0)
+#define TFA98XX_GPIO_CONFIG_GPIOCTRL_POS 0
+#define TFA98XX_GPIO_CONFIG_GPIOCTRL_LEN 1
+#define TFA98XX_GPIO_CONFIG_GPIOCTRL_MAX 1
+#define TFA98XX_GPIO_CONFIG_GPIOCTRL_MSK 0x1
+
+/*
+ * gpio_dir
+ */
+#define TFA98XX_GPIO_CONFIG_GPIOCONF (0xf<<1)
+#define TFA98XX_GPIO_CONFIG_GPIOCONF_POS 1
+#define TFA98XX_GPIO_CONFIG_GPIOCONF_LEN 4
+#define TFA98XX_GPIO_CONFIG_GPIOCONF_MAX 15
+#define TFA98XX_GPIO_CONFIG_GPIOCONF_MSK 0x1e
+
+/*
+ * gpio_dataout
+ */
+#define TFA98XX_GPIO_CONFIG_GPIODOUT (0xf<<5)
+#define TFA98XX_GPIO_CONFIG_GPIODOUT_POS 5
+#define TFA98XX_GPIO_CONFIG_GPIODOUT_LEN 4
+#define TFA98XX_GPIO_CONFIG_GPIODOUT_MAX 15
+#define TFA98XX_GPIO_CONFIG_GPIODOUT_MSK 0x1e0
+
+
+/*
+ * (0x40)-interrupt_out_reg1
+ */
+
+/*
+ * int_out_flag_por
+ */
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTVDDS (0x1<<0)
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTVDDS_POS 0
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTVDDS_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTVDDS_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTVDDS_MSK 0x1
+
+/*
+ * int_out_flag_pll_lock
+ */
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTPLLS (0x1<<1)
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTPLLS_POS 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTPLLS_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTPLLS_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTPLLS_MSK 0x2
+
+/*
+ * int_out_flag_otpok
+ */
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTOTDS (0x1<<2)
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTOTDS_POS 2
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTOTDS_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTOTDS_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTOTDS_MSK 0x4
+
+/*
+ * int_out_flag_ovpok
+ */
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTOVDS (0x1<<3)
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTOVDS_POS 3
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTOVDS_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTOVDS_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTOVDS_MSK 0x8
+
+/*
+ * int_out_flag_uvpok
+ */
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTUVDS (0x1<<4)
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTUVDS_POS 4
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTUVDS_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTUVDS_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTUVDS_MSK 0x10
+
+/*
+ * int_out_flag_clocks_stable
+ */
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTCLKS (0x1<<5)
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTCLKS_POS 5
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTCLKS_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTCLKS_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTCLKS_MSK 0x20
+
+/*
+ * int_out_flag_mtp_busy
+ */
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTMTPB (0x1<<6)
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTMTPB_POS 6
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTMTPB_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTMTPB_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTMTPB_MSK 0x40
+
+/*
+ * int_out_flag_lost_clk
+ */
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTNOCLK (0x1<<7)
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTNOCLK_POS 7
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTNOCLK_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTNOCLK_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTNOCLK_MSK 0x80
+
+/*
+ * int_out_flag_cf_speakererror
+ */
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTSPKS (0x1<<8)
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTSPKS_POS 8
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTSPKS_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTSPKS_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTSPKS_MSK 0x100
+
+/*
+ * int_out_flag_cold_started
+ */
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTACS (0x1<<9)
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTACS_POS 9
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTACS_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTACS_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTACS_MSK 0x200
+
+/*
+ * int_out_flag_engage
+ */
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTSWS (0x1<<10)
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTSWS_POS 10
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTSWS_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTSWS_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTSWS_MSK 0x400
+
+/*
+ * int_out_flag_watchdog_reset
+ */
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTWDS (0x1<<11)
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTWDS_POS 11
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTWDS_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTWDS_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTWDS_MSK 0x800
+
+/*
+ * int_out_flag_enbl_amp
+ */
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTAMPS (0x1<<12)
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTAMPS_POS 12
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTAMPS_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTAMPS_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTAMPS_MSK 0x1000
+
+/*
+ * int_out_flag_enbl_ref
+ */
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTAREFS (0x1<<13)
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTAREFS_POS 13
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTAREFS_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTAREFS_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTAREFS_MSK 0x2000
+
+/*
+ * int_out_flag_adc10_ready
+ */
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTADCCR (0x1<<14)
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTADCCR_POS 14
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTADCCR_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTADCCR_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTADCCR_MSK 0x4000
+
+/*
+ * int_out_flag_bod_vddd_nok
+ */
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTBODNOK (0x1<<15)
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTBODNOK_POS 15
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTBODNOK_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTBODNOK_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG1_ISTBODNOK_MSK 0x8000
+
+
+/*
+ * (0x41)-interrupt_out_reg2
+ */
+
+/*
+ * int_out_flag_bst_bstcur
+ */
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTCU (0x1<<0)
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTCU_POS 0
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTCU_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTCU_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTCU_MSK 0x1
+
+/*
+ * int_out_flag_bst_hiz
+ */
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTHI (0x1<<1)
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTHI_POS 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTHI_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTHI_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTHI_MSK 0x2
+
+/*
+ * int_out_flag_bst_ocpok
+ */
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTOC (0x1<<2)
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTOC_POS 2
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTOC_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTOC_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTOC_MSK 0x4
+
+/*
+ * int_out_flag_bst_peakcur
+ */
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTPKCUR (0x1<<3)
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTPKCUR_POS 3
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTPKCUR_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTPKCUR_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTPKCUR_MSK 0x8
+
+/*
+ * int_out_flag_bst_voutcomp
+ */
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTVC (0x1<<4)
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTVC_POS 4
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTVC_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTVC_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTVC_MSK 0x10
+
+/*
+ * int_out_flag_bst_voutcomp86
+ */
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST86 (0x1<<5)
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST86_POS 5
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST86_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST86_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST86_MSK 0x20
+
+/*
+ * int_out_flag_bst_voutcomp93
+ */
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST93 (0x1<<6)
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST93_POS 6
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST93_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST93_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST93_MSK 0x40
+
+/*
+ * int_out_flag_rcvldop_ready
+ */
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTRCVLD (0x1<<7)
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTRCVLD_POS 7
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTRCVLD_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTRCVLD_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTRCVLD_MSK 0x80
+
+/*
+ * int_out_flag_ocp_alarm_left
+ */
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPL (0x1<<8)
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPL_POS 8
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPL_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPL_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPL_MSK 0x100
+
+/*
+ * int_out_flag_ocp_alarm_right
+ */
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPR (0x1<<9)
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPR_POS 9
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPR_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPR_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPR_MSK 0x200
+
+/*
+ * int_out_flag_man_wait_src_settings
+ */
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSRC (0x1<<10)
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSRC_POS 10
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSRC_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSRC_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSRC_MSK 0x400
+
+/*
+ * int_out_flag_man_wait_cf_config
+ */
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWCFC (0x1<<11)
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWCFC_POS 11
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWCFC_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWCFC_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWCFC_MSK 0x800
+
+/*
+ * int_out_flag_man_start_mute_audio
+ */
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSMU (0x1<<12)
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSMU_POS 12
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSMU_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSMU_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSMU_MSK 0x1000
+
+/*
+ * int_out_flag_cfma_err
+ */
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMER (0x1<<13)
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMER_POS 13
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMER_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMER_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMER_MSK 0x2000
+
+/*
+ * int_out_flag_cfma_ack
+ */
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMAC (0x1<<14)
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMAC_POS 14
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMAC_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMAC_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMAC_MSK 0x4000
+
+/*
+ * int_out_flag_clk_out_of_range
+ */
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTCLKOOR (0x1<<15)
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTCLKOOR_POS 15
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTCLKOOR_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTCLKOOR_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG2_ISTCLKOOR_MSK 0x8000
+
+
+/*
+ * (0x42)-interrupt_out_reg3
+ */
+
+/*
+ * int_out_flag_tdm_error
+ */
+#define TFA98XX_INTERRUPT_OUT_REG3_ISTTDMER (0x1<<0)
+#define TFA98XX_INTERRUPT_OUT_REG3_ISTTDMER_POS 0
+#define TFA98XX_INTERRUPT_OUT_REG3_ISTTDMER_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG3_ISTTDMER_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG3_ISTTDMER_MSK 0x1
+
+/*
+ * int_out_flag_clip_left
+ */
+#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPL (0x1<<1)
+#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPL_POS 1
+#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPL_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPL_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPL_MSK 0x2
+
+/*
+ * int_out_flag_clip_right
+ */
+#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPR (0x1<<2)
+#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPR_POS 2
+#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPR_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPR_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPR_MSK 0x4
+
+/*
+ * int_out_flag_mic_ocpok
+ */
+#define TFA98XX_INTERRUPT_OUT_REG3_ISTOCPM (0x1<<3)
+#define TFA98XX_INTERRUPT_OUT_REG3_ISTOCPM_POS 3
+#define TFA98XX_INTERRUPT_OUT_REG3_ISTOCPM_LEN 1
+#define TFA98XX_INTERRUPT_OUT_REG3_ISTOCPM_MAX 1
+#define TFA98XX_INTERRUPT_OUT_REG3_ISTOCPM_MSK 0x8
+
+
+/*
+ * (0x44)-interrupt_in_reg1
+ */
+
+/*
+ * int_in_flag_por
+ */
+#define TFA98XX_INTERRUPT_IN_REG1_ICLVDDS (0x1<<0)
+#define TFA98XX_INTERRUPT_IN_REG1_ICLVDDS_POS 0
+#define TFA98XX_INTERRUPT_IN_REG1_ICLVDDS_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLVDDS_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLVDDS_MSK 0x1
+
+/*
+ * int_in_flag_pll_lock
+ */
+#define TFA98XX_INTERRUPT_IN_REG1_ICLPLLS (0x1<<1)
+#define TFA98XX_INTERRUPT_IN_REG1_ICLPLLS_POS 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLPLLS_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLPLLS_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLPLLS_MSK 0x2
+
+/*
+ * int_in_flag_otpok
+ */
+#define TFA98XX_INTERRUPT_IN_REG1_ICLOTDS (0x1<<2)
+#define TFA98XX_INTERRUPT_IN_REG1_ICLOTDS_POS 2
+#define TFA98XX_INTERRUPT_IN_REG1_ICLOTDS_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLOTDS_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLOTDS_MSK 0x4
+
+/*
+ * int_in_flag_ovpok
+ */
+#define TFA98XX_INTERRUPT_IN_REG1_ICLOVDS (0x1<<3)
+#define TFA98XX_INTERRUPT_IN_REG1_ICLOVDS_POS 3
+#define TFA98XX_INTERRUPT_IN_REG1_ICLOVDS_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLOVDS_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLOVDS_MSK 0x8
+
+/*
+ * int_in_flag_uvpok
+ */
+#define TFA98XX_INTERRUPT_IN_REG1_ICLUVDS (0x1<<4)
+#define TFA98XX_INTERRUPT_IN_REG1_ICLUVDS_POS 4
+#define TFA98XX_INTERRUPT_IN_REG1_ICLUVDS_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLUVDS_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLUVDS_MSK 0x10
+
+/*
+ * int_in_flag_clocks_stable
+ */
+#define TFA98XX_INTERRUPT_IN_REG1_ICLCLKS (0x1<<5)
+#define TFA98XX_INTERRUPT_IN_REG1_ICLCLKS_POS 5
+#define TFA98XX_INTERRUPT_IN_REG1_ICLCLKS_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLCLKS_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLCLKS_MSK 0x20
+
+/*
+ * int_in_flag_mtp_busy
+ */
+#define TFA98XX_INTERRUPT_IN_REG1_ICLMTPB (0x1<<6)
+#define TFA98XX_INTERRUPT_IN_REG1_ICLMTPB_POS 6
+#define TFA98XX_INTERRUPT_IN_REG1_ICLMTPB_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLMTPB_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLMTPB_MSK 0x40
+
+/*
+ * int_in_flag_lost_clk
+ */
+#define TFA98XX_INTERRUPT_IN_REG1_ICLNOCLK (0x1<<7)
+#define TFA98XX_INTERRUPT_IN_REG1_ICLNOCLK_POS 7
+#define TFA98XX_INTERRUPT_IN_REG1_ICLNOCLK_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLNOCLK_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLNOCLK_MSK 0x80
+
+/*
+ * int_in_flag_cf_speakererror
+ */
+#define TFA98XX_INTERRUPT_IN_REG1_ICLSPKS (0x1<<8)
+#define TFA98XX_INTERRUPT_IN_REG1_ICLSPKS_POS 8
+#define TFA98XX_INTERRUPT_IN_REG1_ICLSPKS_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLSPKS_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLSPKS_MSK 0x100
+
+/*
+ * int_in_flag_cold_started
+ */
+#define TFA98XX_INTERRUPT_IN_REG1_ICLACS (0x1<<9)
+#define TFA98XX_INTERRUPT_IN_REG1_ICLACS_POS 9
+#define TFA98XX_INTERRUPT_IN_REG1_ICLACS_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLACS_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLACS_MSK 0x200
+
+/*
+ * int_in_flag_engage
+ */
+#define TFA98XX_INTERRUPT_IN_REG1_ICLSWS (0x1<<10)
+#define TFA98XX_INTERRUPT_IN_REG1_ICLSWS_POS 10
+#define TFA98XX_INTERRUPT_IN_REG1_ICLSWS_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLSWS_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLSWS_MSK 0x400
+
+/*
+ * int_in_flag_watchdog_reset
+ */
+#define TFA98XX_INTERRUPT_IN_REG1_ICLWDS (0x1<<11)
+#define TFA98XX_INTERRUPT_IN_REG1_ICLWDS_POS 11
+#define TFA98XX_INTERRUPT_IN_REG1_ICLWDS_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLWDS_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLWDS_MSK 0x800
+
+/*
+ * int_in_flag_enbl_amp
+ */
+#define TFA98XX_INTERRUPT_IN_REG1_ICLAMPS (0x1<<12)
+#define TFA98XX_INTERRUPT_IN_REG1_ICLAMPS_POS 12
+#define TFA98XX_INTERRUPT_IN_REG1_ICLAMPS_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLAMPS_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLAMPS_MSK 0x1000
+
+/*
+ * int_in_flag_enbl_ref
+ */
+#define TFA98XX_INTERRUPT_IN_REG1_ICLAREFS (0x1<<13)
+#define TFA98XX_INTERRUPT_IN_REG1_ICLAREFS_POS 13
+#define TFA98XX_INTERRUPT_IN_REG1_ICLAREFS_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLAREFS_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLAREFS_MSK 0x2000
+
+/*
+ * int_in_flag_adc10_ready
+ */
+#define TFA98XX_INTERRUPT_IN_REG1_ICLADCCR (0x1<<14)
+#define TFA98XX_INTERRUPT_IN_REG1_ICLADCCR_POS 14
+#define TFA98XX_INTERRUPT_IN_REG1_ICLADCCR_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLADCCR_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLADCCR_MSK 0x4000
+
+/*
+ * int_in_flag_bod_vddd_nok
+ */
+#define TFA98XX_INTERRUPT_IN_REG1_ICLBODNOK (0x1<<15)
+#define TFA98XX_INTERRUPT_IN_REG1_ICLBODNOK_POS 15
+#define TFA98XX_INTERRUPT_IN_REG1_ICLBODNOK_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLBODNOK_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG1_ICLBODNOK_MSK 0x8000
+
+
+/*
+ * (0x45)-interrupt_in_reg2
+ */
+
+/*
+ * int_in_flag_bst_bstcur
+ */
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTCU (0x1<<0)
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTCU_POS 0
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTCU_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTCU_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTCU_MSK 0x1
+
+/*
+ * int_in_flag_bst_hiz
+ */
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTHI (0x1<<1)
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTHI_POS 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTHI_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTHI_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTHI_MSK 0x2
+
+/*
+ * int_in_flag_bst_ocpok
+ */
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTOC (0x1<<2)
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTOC_POS 2
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTOC_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTOC_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTOC_MSK 0x4
+
+/*
+ * int_in_flag_bst_peakcur
+ */
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTPC (0x1<<3)
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTPC_POS 3
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTPC_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTPC_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTPC_MSK 0x8
+
+/*
+ * int_in_flag_bst_voutcomp
+ */
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTVC (0x1<<4)
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTVC_POS 4
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTVC_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTVC_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTVC_MSK 0x10
+
+/*
+ * int_in_flag_bst_voutcomp86
+ */
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBST86 (0x1<<5)
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBST86_POS 5
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBST86_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBST86_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBST86_MSK 0x20
+
+/*
+ * int_in_flag_bst_voutcomp93
+ */
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBST93 (0x1<<6)
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBST93_POS 6
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBST93_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBST93_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLBST93_MSK 0x40
+
+/*
+ * int_in_flag_rcvldop_ready
+ */
+#define TFA98XX_INTERRUPT_IN_REG2_ICLRCVLD (0x1<<7)
+#define TFA98XX_INTERRUPT_IN_REG2_ICLRCVLD_POS 7
+#define TFA98XX_INTERRUPT_IN_REG2_ICLRCVLD_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLRCVLD_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLRCVLD_MSK 0x80
+
+/*
+ * int_in_flag_ocp_alarm_left
+ */
+#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPL (0x1<<8)
+#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPL_POS 8
+#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPL_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPL_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPL_MSK 0x100
+
+/*
+ * int_in_flag_ocp_alarm_right
+ */
+#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPR (0x1<<9)
+#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPR_POS 9
+#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPR_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPR_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPR_MSK 0x200
+
+/*
+ * int_in_flag_man_wait_src_settings
+ */
+#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSRC (0x1<<10)
+#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSRC_POS 10
+#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSRC_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSRC_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSRC_MSK 0x400
+
+/*
+ * int_in_flag_man_wait_cf_config
+ */
+#define TFA98XX_INTERRUPT_IN_REG2_ICLMWCFC (0x1<<11)
+#define TFA98XX_INTERRUPT_IN_REG2_ICLMWCFC_POS 11
+#define TFA98XX_INTERRUPT_IN_REG2_ICLMWCFC_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLMWCFC_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLMWCFC_MSK 0x800
+
+/*
+ * int_in_flag_man_start_mute_audio
+ */
+#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSMU (0x1<<12)
+#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSMU_POS 12
+#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSMU_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSMU_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSMU_MSK 0x1000
+
+/*
+ * int_in_flag_cfma_err
+ */
+#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMER (0x1<<13)
+#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMER_POS 13
+#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMER_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMER_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMER_MSK 0x2000
+
+/*
+ * int_in_flag_cfma_ack
+ */
+#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMAC (0x1<<14)
+#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMAC_POS 14
+#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMAC_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMAC_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMAC_MSK 0x4000
+
+/*
+ * int_in_flag_clk_out_of_range
+ */
+#define TFA98XX_INTERRUPT_IN_REG2_ICLCLKOOR (0x1<<15)
+#define TFA98XX_INTERRUPT_IN_REG2_ICLCLKOOR_POS 15
+#define TFA98XX_INTERRUPT_IN_REG2_ICLCLKOOR_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLCLKOOR_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG2_ICLCLKOOR_MSK 0x8000
+
+
+/*
+ * (0x46)-interrupt_in_reg3
+ */
+
+/*
+ * int_in_flag_tdm_error
+ */
+#define TFA98XX_INTERRUPT_IN_REG3_ICLTDMER (0x1<<0)
+#define TFA98XX_INTERRUPT_IN_REG3_ICLTDMER_POS 0
+#define TFA98XX_INTERRUPT_IN_REG3_ICLTDMER_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG3_ICLTDMER_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG3_ICLTDMER_MSK 0x1
+
+/*
+ * int_in_flag_clip_left
+ */
+#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPL (0x1<<1)
+#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPL_POS 1
+#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPL_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPL_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPL_MSK 0x2
+
+/*
+ * int_in_flag_clip_right
+ */
+#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPR (0x1<<2)
+#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPR_POS 2
+#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPR_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPR_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPR_MSK 0x4
+
+/*
+ * int_in_flag_mic_ocpok
+ */
+#define TFA98XX_INTERRUPT_IN_REG3_ICLOCPM (0x1<<3)
+#define TFA98XX_INTERRUPT_IN_REG3_ICLOCPM_POS 3
+#define TFA98XX_INTERRUPT_IN_REG3_ICLOCPM_LEN 1
+#define TFA98XX_INTERRUPT_IN_REG3_ICLOCPM_MAX 1
+#define TFA98XX_INTERRUPT_IN_REG3_ICLOCPM_MSK 0x8
+
+
+/*
+ * (0x48)-interrupt_enable_reg1
+ */
+
+/*
+ * int_enable_flag_por
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEVDDS (0x1<<0)
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEVDDS_POS 0
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEVDDS_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEVDDS_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEVDDS_MSK 0x1
+
+/*
+ * int_enable_flag_pll_lock
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEPLLS (0x1<<1)
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEPLLS_POS 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEPLLS_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEPLLS_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEPLLS_MSK 0x2
+
+/*
+ * int_enable_flag_otpok
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOTDS (0x1<<2)
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOTDS_POS 2
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOTDS_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOTDS_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOTDS_MSK 0x4
+
+/*
+ * int_enable_flag_ovpok
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOVDS (0x1<<3)
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOVDS_POS 3
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOVDS_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOVDS_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOVDS_MSK 0x8
+
+/*
+ * int_enable_flag_uvpok
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEUVDS (0x1<<4)
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEUVDS_POS 4
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEUVDS_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEUVDS_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEUVDS_MSK 0x10
+
+/*
+ * int_enable_flag_clocks_stable
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IECLKS (0x1<<5)
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IECLKS_POS 5
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IECLKS_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IECLKS_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IECLKS_MSK 0x20
+
+/*
+ * int_enable_flag_mtp_busy
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEMTPB (0x1<<6)
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEMTPB_POS 6
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEMTPB_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEMTPB_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEMTPB_MSK 0x40
+
+/*
+ * int_enable_flag_lost_clk
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IENOCLK (0x1<<7)
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IENOCLK_POS 7
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IENOCLK_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IENOCLK_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IENOCLK_MSK 0x80
+
+/*
+ * int_enable_flag_cf_speakererror
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IESPKS (0x1<<8)
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IESPKS_POS 8
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IESPKS_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IESPKS_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IESPKS_MSK 0x100
+
+/*
+ * int_enable_flag_cold_started
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEACS (0x1<<9)
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEACS_POS 9
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEACS_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEACS_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEACS_MSK 0x200
+
+/*
+ * int_enable_flag_engage
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IESWS (0x1<<10)
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IESWS_POS 10
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IESWS_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IESWS_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IESWS_MSK 0x400
+
+/*
+ * int_enable_flag_watchdog_reset
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEWDS (0x1<<11)
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEWDS_POS 11
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEWDS_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEWDS_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEWDS_MSK 0x800
+
+/*
+ * int_enable_flag_enbl_amp
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAMPS (0x1<<12)
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAMPS_POS 12
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAMPS_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAMPS_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAMPS_MSK 0x1000
+
+/*
+ * int_enable_flag_enbl_ref
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAREFS (0x1<<13)
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAREFS_POS 13
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAREFS_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAREFS_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAREFS_MSK 0x2000
+
+/*
+ * int_enable_flag_adc10_ready
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEADCCR (0x1<<14)
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEADCCR_POS 14
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEADCCR_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEADCCR_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEADCCR_MSK 0x4000
+
+/*
+ * int_enable_flag_bod_vddd_nok
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEBODNOK (0x1<<15)
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEBODNOK_POS 15
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEBODNOK_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEBODNOK_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG1_IEBODNOK_MSK 0x8000
+
+
+/*
+ * (0x49)-interrupt_enable_reg2
+ */
+
+/*
+ * int_enable_flag_bst_bstcur
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTCU (0x1<<0)
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTCU_POS 0
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTCU_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTCU_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTCU_MSK 0x1
+
+/*
+ * int_enable_flag_bst_hiz
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTHI (0x1<<1)
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTHI_POS 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTHI_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTHI_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTHI_MSK 0x2
+
+/*
+ * int_enable_flag_bst_ocpok
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTOC (0x1<<2)
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTOC_POS 2
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTOC_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTOC_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTOC_MSK 0x4
+
+/*
+ * int_enable_flag_bst_peakcur
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTPC (0x1<<3)
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTPC_POS 3
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTPC_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTPC_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTPC_MSK 0x8
+
+/*
+ * int_enable_flag_bst_voutcomp
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTVC (0x1<<4)
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTVC_POS 4
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTVC_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTVC_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTVC_MSK 0x10
+
+/*
+ * int_enable_flag_bst_voutcomp86
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST86 (0x1<<5)
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST86_POS 5
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST86_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST86_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST86_MSK 0x20
+
+/*
+ * int_enable_flag_bst_voutcomp93
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST93 (0x1<<6)
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST93_POS 6
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST93_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST93_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST93_MSK 0x40
+
+/*
+ * int_enable_flag_rcvldop_ready
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IERCVLD (0x1<<7)
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IERCVLD_POS 7
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IERCVLD_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IERCVLD_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IERCVLD_MSK 0x80
+
+/*
+ * int_enable_flag_ocp_alarm_left
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPL (0x1<<8)
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPL_POS 8
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPL_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPL_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPL_MSK 0x100
+
+/*
+ * int_enable_flag_ocp_alarm_right
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPR (0x1<<9)
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPR_POS 9
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPR_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPR_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPR_MSK 0x200
+
+/*
+ * int_enable_flag_man_wait_src_settings
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSRC (0x1<<10)
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSRC_POS 10
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSRC_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSRC_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSRC_MSK 0x400
+
+/*
+ * int_enable_flag_man_wait_cf_config
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWCFC (0x1<<11)
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWCFC_POS 11
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWCFC_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWCFC_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWCFC_MSK 0x800
+
+/*
+ * int_enable_flag_man_start_mute_audio
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSMU (0x1<<12)
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSMU_POS 12
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSMU_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSMU_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSMU_MSK 0x1000
+
+/*
+ * int_enable_flag_cfma_err
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMER (0x1<<13)
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMER_POS 13
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMER_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMER_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMER_MSK 0x2000
+
+/*
+ * int_enable_flag_cfma_ack
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMAC (0x1<<14)
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMAC_POS 14
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMAC_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMAC_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMAC_MSK 0x4000
+
+/*
+ * int_enable_flag_clk_out_of_range
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IECLKOOR (0x1<<15)
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IECLKOOR_POS 15
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IECLKOOR_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IECLKOOR_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG2_IECLKOOR_MSK 0x8000
+
+
+/*
+ * (0x4a)-interrupt_enable_reg3
+ */
+
+/*
+ * int_enable_flag_tdm_error
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG3_IETDMER (0x1<<0)
+#define TFA98XX_INTERRUPT_ENABLE_REG3_IETDMER_POS 0
+#define TFA98XX_INTERRUPT_ENABLE_REG3_IETDMER_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG3_IETDMER_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG3_IETDMER_MSK 0x1
+
+/*
+ * int_enable_flag_clip_left
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPL (0x1<<1)
+#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPL_POS 1
+#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPL_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPL_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPL_MSK 0x2
+
+/*
+ * int_enable_flag_clip_right
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPR (0x1<<2)
+#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPR_POS 2
+#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPR_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPR_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPR_MSK 0x4
+
+/*
+ * int_enable_flag_mic_ocpok
+ */
+#define TFA98XX_INTERRUPT_ENABLE_REG3_IEOCPM1 (0x1<<3)
+#define TFA98XX_INTERRUPT_ENABLE_REG3_IEOCPM1_POS 3
+#define TFA98XX_INTERRUPT_ENABLE_REG3_IEOCPM1_LEN 1
+#define TFA98XX_INTERRUPT_ENABLE_REG3_IEOCPM1_MAX 1
+#define TFA98XX_INTERRUPT_ENABLE_REG3_IEOCPM1_MSK 0x8
+
+
+/*
+ * (0x4c)-status_polarity_reg1
+ */
+
+/*
+ * int_polarity_flag_por
+ */
+#define TFA98XX_STATUS_POLARITY_REG1_IPOVDDS (0x1<<0)
+#define TFA98XX_STATUS_POLARITY_REG1_IPOVDDS_POS 0
+#define TFA98XX_STATUS_POLARITY_REG1_IPOVDDS_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOVDDS_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOVDDS_MSK 0x1
+
+/*
+ * int_polarity_flag_pll_lock
+ */
+#define TFA98XX_STATUS_POLARITY_REG1_IPOPLLS (0x1<<1)
+#define TFA98XX_STATUS_POLARITY_REG1_IPOPLLS_POS 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOPLLS_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOPLLS_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOPLLS_MSK 0x2
+
+/*
+ * int_polarity_flag_otpok
+ */
+#define TFA98XX_STATUS_POLARITY_REG1_IPOOTDS (0x1<<2)
+#define TFA98XX_STATUS_POLARITY_REG1_IPOOTDS_POS 2
+#define TFA98XX_STATUS_POLARITY_REG1_IPOOTDS_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOOTDS_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOOTDS_MSK 0x4
+
+/*
+ * int_polarity_flag_ovpok
+ */
+#define TFA98XX_STATUS_POLARITY_REG1_IPOOVDS (0x1<<3)
+#define TFA98XX_STATUS_POLARITY_REG1_IPOOVDS_POS 3
+#define TFA98XX_STATUS_POLARITY_REG1_IPOOVDS_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOOVDS_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOOVDS_MSK 0x8
+
+/*
+ * int_polarity_flag_uvpok
+ */
+#define TFA98XX_STATUS_POLARITY_REG1_IPOUVDS (0x1<<4)
+#define TFA98XX_STATUS_POLARITY_REG1_IPOUVDS_POS 4
+#define TFA98XX_STATUS_POLARITY_REG1_IPOUVDS_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOUVDS_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOUVDS_MSK 0x10
+
+/*
+ * int_polarity_flag_clocks_stable
+ */
+#define TFA98XX_STATUS_POLARITY_REG1_IPOCLKS (0x1<<5)
+#define TFA98XX_STATUS_POLARITY_REG1_IPOCLKS_POS 5
+#define TFA98XX_STATUS_POLARITY_REG1_IPOCLKS_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOCLKS_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOCLKS_MSK 0x20
+
+/*
+ * int_polarity_flag_mtp_busy
+ */
+#define TFA98XX_STATUS_POLARITY_REG1_IPOMTPB (0x1<<6)
+#define TFA98XX_STATUS_POLARITY_REG1_IPOMTPB_POS 6
+#define TFA98XX_STATUS_POLARITY_REG1_IPOMTPB_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOMTPB_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOMTPB_MSK 0x40
+
+/*
+ * int_polarity_flag_lost_clk
+ */
+#define TFA98XX_STATUS_POLARITY_REG1_IPONOCLK (0x1<<7)
+#define TFA98XX_STATUS_POLARITY_REG1_IPONOCLK_POS 7
+#define TFA98XX_STATUS_POLARITY_REG1_IPONOCLK_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPONOCLK_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPONOCLK_MSK 0x80
+
+/*
+ * int_polarity_flag_cf_speakererror
+ */
+#define TFA98XX_STATUS_POLARITY_REG1_IPOSPKS (0x1<<8)
+#define TFA98XX_STATUS_POLARITY_REG1_IPOSPKS_POS 8
+#define TFA98XX_STATUS_POLARITY_REG1_IPOSPKS_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOSPKS_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOSPKS_MSK 0x100
+
+/*
+ * int_polarity_flag_cold_started
+ */
+#define TFA98XX_STATUS_POLARITY_REG1_IPOACS (0x1<<9)
+#define TFA98XX_STATUS_POLARITY_REG1_IPOACS_POS 9
+#define TFA98XX_STATUS_POLARITY_REG1_IPOACS_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOACS_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOACS_MSK 0x200
+
+/*
+ * int_polarity_flag_engage
+ */
+#define TFA98XX_STATUS_POLARITY_REG1_IPOSWS (0x1<<10)
+#define TFA98XX_STATUS_POLARITY_REG1_IPOSWS_POS 10
+#define TFA98XX_STATUS_POLARITY_REG1_IPOSWS_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOSWS_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOSWS_MSK 0x400
+
+/*
+ * int_polarity_flag_watchdog_reset
+ */
+#define TFA98XX_STATUS_POLARITY_REG1_IPOWDS (0x1<<11)
+#define TFA98XX_STATUS_POLARITY_REG1_IPOWDS_POS 11
+#define TFA98XX_STATUS_POLARITY_REG1_IPOWDS_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOWDS_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOWDS_MSK 0x800
+
+/*
+ * int_polarity_flag_enbl_amp
+ */
+#define TFA98XX_STATUS_POLARITY_REG1_IPOAMPS (0x1<<12)
+#define TFA98XX_STATUS_POLARITY_REG1_IPOAMPS_POS 12
+#define TFA98XX_STATUS_POLARITY_REG1_IPOAMPS_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOAMPS_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOAMPS_MSK 0x1000
+
+/*
+ * int_polarity_flag_enbl_ref
+ */
+#define TFA98XX_STATUS_POLARITY_REG1_IPOAREFS (0x1<<13)
+#define TFA98XX_STATUS_POLARITY_REG1_IPOAREFS_POS 13
+#define TFA98XX_STATUS_POLARITY_REG1_IPOAREFS_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOAREFS_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOAREFS_MSK 0x2000
+
+/*
+ * int_polarity_flag_adc10_ready
+ */
+#define TFA98XX_STATUS_POLARITY_REG1_IPOADCCR (0x1<<14)
+#define TFA98XX_STATUS_POLARITY_REG1_IPOADCCR_POS 14
+#define TFA98XX_STATUS_POLARITY_REG1_IPOADCCR_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOADCCR_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOADCCR_MSK 0x4000
+
+/*
+ * int_polarity_flag_bod_vddd_nok
+ */
+#define TFA98XX_STATUS_POLARITY_REG1_IPOBODNOK (0x1<<15)
+#define TFA98XX_STATUS_POLARITY_REG1_IPOBODNOK_POS 15
+#define TFA98XX_STATUS_POLARITY_REG1_IPOBODNOK_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOBODNOK_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG1_IPOBODNOK_MSK 0x8000
+
+
+/*
+ * (0x4d)-status_polarity_reg2
+ */
+
+/*
+ * int_polarity_flag_bst_bstcur
+ */
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTCU (0x1<<0)
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTCU_POS 0
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTCU_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTCU_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTCU_MSK 0x1
+
+/*
+ * int_polarity_flag_bst_hiz
+ */
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTHI (0x1<<1)
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTHI_POS 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTHI_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTHI_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTHI_MSK 0x2
+
+/*
+ * int_polarity_flag_bst_ocpok
+ */
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTOC (0x1<<2)
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTOC_POS 2
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTOC_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTOC_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTOC_MSK 0x4
+
+/*
+ * int_polarity_flag_bst_peakcur
+ */
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTPC (0x1<<3)
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTPC_POS 3
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTPC_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTPC_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTPC_MSK 0x8
+
+/*
+ * int_polarity_flag_bst_voutcomp
+ */
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTVC (0x1<<4)
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTVC_POS 4
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTVC_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTVC_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTVC_MSK 0x10
+
+/*
+ * int_polarity_flag_bst_voutcomp86
+ */
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBST86 (0x1<<5)
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBST86_POS 5
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBST86_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBST86_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBST86_MSK 0x20
+
+/*
+ * int_polarity_flag_bst_voutcomp93
+ */
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBST93 (0x1<<6)
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBST93_POS 6
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBST93_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBST93_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOBST93_MSK 0x40
+
+/*
+ * int_polarity_flag_rcvldop_ready
+ */
+#define TFA98XX_STATUS_POLARITY_REG2_IPORCVLD (0x1<<7)
+#define TFA98XX_STATUS_POLARITY_REG2_IPORCVLD_POS 7
+#define TFA98XX_STATUS_POLARITY_REG2_IPORCVLD_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPORCVLD_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPORCVLD_MSK 0x80
+
+/*
+ * int_polarity_flag_ocp_alarm_left
+ */
+#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPL (0x1<<8)
+#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPL_POS 8
+#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPL_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPL_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPL_MSK 0x100
+
+/*
+ * int_polarity_flag_ocp_alarm_right
+ */
+#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPR (0x1<<9)
+#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPR_POS 9
+#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPR_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPR_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPR_MSK 0x200
+
+/*
+ * int_polarity_flag_man_wait_src_settings
+ */
+#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSRC (0x1<<10)
+#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSRC_POS 10
+#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSRC_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSRC_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSRC_MSK 0x400
+
+/*
+ * int_polarity_flag_man_wait_cf_config
+ */
+#define TFA98XX_STATUS_POLARITY_REG2_IPOMWCFC (0x1<<11)
+#define TFA98XX_STATUS_POLARITY_REG2_IPOMWCFC_POS 11
+#define TFA98XX_STATUS_POLARITY_REG2_IPOMWCFC_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOMWCFC_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOMWCFC_MSK 0x800
+
+/*
+ * int_polarity_flag_man_start_mute_audio
+ */
+#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSMU (0x1<<12)
+#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSMU_POS 12
+#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSMU_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSMU_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSMU_MSK 0x1000
+
+/*
+ * int_polarity_flag_cfma_err
+ */
+#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMER (0x1<<13)
+#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMER_POS 13
+#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMER_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMER_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMER_MSK 0x2000
+
+/*
+ * int_polarity_flag_cfma_ack
+ */
+#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMAC (0x1<<14)
+#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMAC_POS 14
+#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMAC_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMAC_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMAC_MSK 0x4000
+
+/*
+ * int_polarity_flag_clk_out_of_range
+ */
+#define TFA98XX_STATUS_POLARITY_REG2_IPCLKOOR (0x1<<15)
+#define TFA98XX_STATUS_POLARITY_REG2_IPCLKOOR_POS 15
+#define TFA98XX_STATUS_POLARITY_REG2_IPCLKOOR_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPCLKOOR_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG2_IPCLKOOR_MSK 0x8000
+
+
+/*
+ * (0x4e)-status_polarity_reg3
+ */
+
+/*
+ * int_polarity_flag_tdm_error
+ */
+#define TFA98XX_STATUS_POLARITY_REG3_IPOTDMER (0x1<<0)
+#define TFA98XX_STATUS_POLARITY_REG3_IPOTDMER_POS 0
+#define TFA98XX_STATUS_POLARITY_REG3_IPOTDMER_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG3_IPOTDMER_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG3_IPOTDMER_MSK 0x1
+
+/*
+ * int_polarity_flag_clip_left
+ */
+#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPL (0x1<<1)
+#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPL_POS 1
+#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPL_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPL_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPL_MSK 0x2
+
+/*
+ * int_polarity_flag_clip_right
+ */
+#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPR (0x1<<2)
+#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPR_POS 2
+#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPR_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPR_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPR_MSK 0x4
+
+/*
+ * int_polarity_flag_mic_ocpok
+ */
+#define TFA98XX_STATUS_POLARITY_REG3_IPOOCPM (0x1<<3)
+#define TFA98XX_STATUS_POLARITY_REG3_IPOOCPM_POS 3
+#define TFA98XX_STATUS_POLARITY_REG3_IPOOCPM_LEN 1
+#define TFA98XX_STATUS_POLARITY_REG3_IPOOCPM_MAX 1
+#define TFA98XX_STATUS_POLARITY_REG3_IPOOCPM_MSK 0x8
+
+
+/*
+ * (0x50)-bat_prot_config
+ */
+
+/*
+ * vbat_prot_attack_time
+ */
+#define TFA98XX_BAT_PROT_CONFIG_BSSCR (0x3<<0)
+#define TFA98XX_BAT_PROT_CONFIG_BSSCR_POS 0
+#define TFA98XX_BAT_PROT_CONFIG_BSSCR_LEN 2
+#define TFA98XX_BAT_PROT_CONFIG_BSSCR_MAX 3
+#define TFA98XX_BAT_PROT_CONFIG_BSSCR_MSK 0x3
+
+/*
+ * vbat_prot_thlevel
+ */
+#define TFA98XX_BAT_PROT_CONFIG_BSST (0xf<<2)
+#define TFA98XX_BAT_PROT_CONFIG_BSST_POS 2
+#define TFA98XX_BAT_PROT_CONFIG_BSST_LEN 4
+#define TFA98XX_BAT_PROT_CONFIG_BSST_MAX 15
+#define TFA98XX_BAT_PROT_CONFIG_BSST_MSK 0x3c
+
+/*
+ * vbat_prot_max_reduct
+ */
+#define TFA98XX_BAT_PROT_CONFIG_BSSRL (0x3<<6)
+#define TFA98XX_BAT_PROT_CONFIG_BSSRL_POS 6
+#define TFA98XX_BAT_PROT_CONFIG_BSSRL_LEN 2
+#define TFA98XX_BAT_PROT_CONFIG_BSSRL_MAX 3
+#define TFA98XX_BAT_PROT_CONFIG_BSSRL_MSK 0xc0
+
+/*
+ * vbat_prot_release_time
+ */
+#define TFA98XX_BAT_PROT_CONFIG_BSSRR (0x7<<8)
+#define TFA98XX_BAT_PROT_CONFIG_BSSRR_POS 8
+#define TFA98XX_BAT_PROT_CONFIG_BSSRR_LEN 3
+#define TFA98XX_BAT_PROT_CONFIG_BSSRR_MAX 7
+#define TFA98XX_BAT_PROT_CONFIG_BSSRR_MSK 0x700
+
+/*
+ * vbat_prot_hysterese
+ */
+#define TFA98XX_BAT_PROT_CONFIG_BSSHY (0x3<<11)
+#define TFA98XX_BAT_PROT_CONFIG_BSSHY_POS 11
+#define TFA98XX_BAT_PROT_CONFIG_BSSHY_LEN 2
+#define TFA98XX_BAT_PROT_CONFIG_BSSHY_MAX 3
+#define TFA98XX_BAT_PROT_CONFIG_BSSHY_MSK 0x1800
+
+/*
+ * sel_vbat
+ */
+#define TFA98XX_BAT_PROT_CONFIG_BSSR (0x1<<14)
+#define TFA98XX_BAT_PROT_CONFIG_BSSR_POS 14
+#define TFA98XX_BAT_PROT_CONFIG_BSSR_LEN 1
+#define TFA98XX_BAT_PROT_CONFIG_BSSR_MAX 1
+#define TFA98XX_BAT_PROT_CONFIG_BSSR_MSK 0x4000
+
+/*
+ * bypass_clipper
+ */
+#define TFA98XX_BAT_PROT_CONFIG_BSSBY (0x1<<15)
+#define TFA98XX_BAT_PROT_CONFIG_BSSBY_POS 15
+#define TFA98XX_BAT_PROT_CONFIG_BSSBY_LEN 1
+#define TFA98XX_BAT_PROT_CONFIG_BSSBY_MAX 1
+#define TFA98XX_BAT_PROT_CONFIG_BSSBY_MSK 0x8000
+
+
+/*
+ * (0x51)-audio_control
+ */
+
+/*
+ * batsense_steepness
+ */
+#define TFA98XX_AUDIO_CONTROL_BSSS (0x1<<0)
+#define TFA98XX_AUDIO_CONTROL_BSSS_POS 0
+#define TFA98XX_AUDIO_CONTROL_BSSS_LEN 1
+#define TFA98XX_AUDIO_CONTROL_BSSS_MAX 1
+#define TFA98XX_AUDIO_CONTROL_BSSS_MSK 0x1
+
+/*
+ * soft_mute
+ */
+#define TFA98XX_AUDIO_CONTROL_INTSMUTE (0x1<<1)
+#define TFA98XX_AUDIO_CONTROL_INTSMUTE_POS 1
+#define TFA98XX_AUDIO_CONTROL_INTSMUTE_LEN 1
+#define TFA98XX_AUDIO_CONTROL_INTSMUTE_MAX 1
+#define TFA98XX_AUDIO_CONTROL_INTSMUTE_MSK 0x2
+
+/*
+ * cf_mute_left
+ */
+#define TFA98XX_AUDIO_CONTROL_CFSML (0x1<<2)
+#define TFA98XX_AUDIO_CONTROL_CFSML_POS 2
+#define TFA98XX_AUDIO_CONTROL_CFSML_LEN 1
+#define TFA98XX_AUDIO_CONTROL_CFSML_MAX 1
+#define TFA98XX_AUDIO_CONTROL_CFSML_MSK 0x4
+
+/*
+ * cf_mute_right
+ */
+#define TFA98XX_AUDIO_CONTROL_CFSMR (0x1<<3)
+#define TFA98XX_AUDIO_CONTROL_CFSMR_POS 3
+#define TFA98XX_AUDIO_CONTROL_CFSMR_LEN 1
+#define TFA98XX_AUDIO_CONTROL_CFSMR_MAX 1
+#define TFA98XX_AUDIO_CONTROL_CFSMR_MSK 0x8
+
+/*
+ * bypass_hp_left
+ */
+#define TFA98XX_AUDIO_CONTROL_HPFBYPL (0x1<<4)
+#define TFA98XX_AUDIO_CONTROL_HPFBYPL_POS 4
+#define TFA98XX_AUDIO_CONTROL_HPFBYPL_LEN 1
+#define TFA98XX_AUDIO_CONTROL_HPFBYPL_MAX 1
+#define TFA98XX_AUDIO_CONTROL_HPFBYPL_MSK 0x10
+
+/*
+ * bypass_hp_right
+ */
+#define TFA98XX_AUDIO_CONTROL_HPFBYPR (0x1<<5)
+#define TFA98XX_AUDIO_CONTROL_HPFBYPR_POS 5
+#define TFA98XX_AUDIO_CONTROL_HPFBYPR_LEN 1
+#define TFA98XX_AUDIO_CONTROL_HPFBYPR_MAX 1
+#define TFA98XX_AUDIO_CONTROL_HPFBYPR_MSK 0x20
+
+/*
+ * enbl_dpsa_left
+ */
+#define TFA98XX_AUDIO_CONTROL_DPSAL (0x1<<6)
+#define TFA98XX_AUDIO_CONTROL_DPSAL_POS 6
+#define TFA98XX_AUDIO_CONTROL_DPSAL_LEN 1
+#define TFA98XX_AUDIO_CONTROL_DPSAL_MAX 1
+#define TFA98XX_AUDIO_CONTROL_DPSAL_MSK 0x40
+
+/*
+ * enbl_dpsa_right
+ */
+#define TFA98XX_AUDIO_CONTROL_DPSAR (0x1<<7)
+#define TFA98XX_AUDIO_CONTROL_DPSAR_POS 7
+#define TFA98XX_AUDIO_CONTROL_DPSAR_LEN 1
+#define TFA98XX_AUDIO_CONTROL_DPSAR_MAX 1
+#define TFA98XX_AUDIO_CONTROL_DPSAR_MSK 0x80
+
+/*
+ * cf_volume
+ */
+#define TFA98XX_AUDIO_CONTROL_VOL (0xff<<8)
+#define TFA98XX_AUDIO_CONTROL_VOL_POS 8
+#define TFA98XX_AUDIO_CONTROL_VOL_LEN 8
+#define TFA98XX_AUDIO_CONTROL_VOL_MAX 255
+#define TFA98XX_AUDIO_CONTROL_VOL_MSK 0xff00
+
+
+/*
+ * (0x52)-amplifier_config
+ */
+
+/*
+ * ctrl_rcv
+ */
+#define TFA98XX_AMPLIFIER_CONFIG_HNDSFRCV (0x1<<0)
+#define TFA98XX_AMPLIFIER_CONFIG_HNDSFRCV_POS 0
+#define TFA98XX_AMPLIFIER_CONFIG_HNDSFRCV_LEN 1
+#define TFA98XX_AMPLIFIER_CONFIG_HNDSFRCV_MAX 1
+#define TFA98XX_AMPLIFIER_CONFIG_HNDSFRCV_MSK 0x1
+
+/*
+ * ctrl_cc
+ */
+#define TFA98XX_AMPLIFIER_CONFIG_CLIPCTRL (0x7<<2)
+#define TFA98XX_AMPLIFIER_CONFIG_CLIPCTRL_POS 2
+#define TFA98XX_AMPLIFIER_CONFIG_CLIPCTRL_LEN 3
+#define TFA98XX_AMPLIFIER_CONFIG_CLIPCTRL_MAX 7
+#define TFA98XX_AMPLIFIER_CONFIG_CLIPCTRL_MSK 0x1c
+
+/*
+ * gain
+ */
+#define TFA98XX_AMPLIFIER_CONFIG_AMPGAIN (0xff<<5)
+#define TFA98XX_AMPLIFIER_CONFIG_AMPGAIN_POS 5
+#define TFA98XX_AMPLIFIER_CONFIG_AMPGAIN_LEN 8
+#define TFA98XX_AMPLIFIER_CONFIG_AMPGAIN_MAX 255
+#define TFA98XX_AMPLIFIER_CONFIG_AMPGAIN_MSK 0x1fe0
+
+/*
+ * ctrl_slopectrl
+ */
+#define TFA98XX_AMPLIFIER_CONFIG_SLOPEE (0x1<<13)
+#define TFA98XX_AMPLIFIER_CONFIG_SLOPEE_POS 13
+#define TFA98XX_AMPLIFIER_CONFIG_SLOPEE_LEN 1
+#define TFA98XX_AMPLIFIER_CONFIG_SLOPEE_MAX 1
+#define TFA98XX_AMPLIFIER_CONFIG_SLOPEE_MSK 0x2000
+
+/*
+ * ctrl_slope
+ */
+#define TFA98XX_AMPLIFIER_CONFIG_SLOPESET (0x3<<14)
+#define TFA98XX_AMPLIFIER_CONFIG_SLOPESET_POS 14
+#define TFA98XX_AMPLIFIER_CONFIG_SLOPESET_LEN 2
+#define TFA98XX_AMPLIFIER_CONFIG_SLOPESET_MAX 3
+#define TFA98XX_AMPLIFIER_CONFIG_SLOPESET_MSK 0xc000
+
+
+/*
+ * (0x5a)-audio_control2
+ */
+
+/*
+ * cf_volume_sec
+ */
+#define TFA98XX_AUDIO_CONTROL2_VOLSEC (0xff<<0)
+#define TFA98XX_AUDIO_CONTROL2_VOLSEC_POS 0
+#define TFA98XX_AUDIO_CONTROL2_VOLSEC_LEN 8
+#define TFA98XX_AUDIO_CONTROL2_VOLSEC_MAX 255
+#define TFA98XX_AUDIO_CONTROL2_VOLSEC_MSK 0xff
+
+/*
+ * sw_profile
+ */
+#define TFA98XX_AUDIO_CONTROL2_SWPROFIL (0xff<<8)
+#define TFA98XX_AUDIO_CONTROL2_SWPROFIL_POS 8
+#define TFA98XX_AUDIO_CONTROL2_SWPROFIL_LEN 8
+#define TFA98XX_AUDIO_CONTROL2_SWPROFIL_MAX 255
+#define TFA98XX_AUDIO_CONTROL2_SWPROFIL_MSK 0xff00
+
+
+/*
+ * (0x70)-dcdc_control0
+ */
+
+/*
+ * boost_volt
+ */
+#define TFA98XX_DCDC_CONTROL0_DCVO (0x7<<0)
+#define TFA98XX_DCDC_CONTROL0_DCVO_POS 0
+#define TFA98XX_DCDC_CONTROL0_DCVO_LEN 3
+#define TFA98XX_DCDC_CONTROL0_DCVO_MAX 7
+#define TFA98XX_DCDC_CONTROL0_DCVO_MSK 0x7
+
+/*
+ * boost_cur
+ */
+#define TFA98XX_DCDC_CONTROL0_DCMCC (0xf<<3)
+#define TFA98XX_DCDC_CONTROL0_DCMCC_POS 3
+#define TFA98XX_DCDC_CONTROL0_DCMCC_LEN 4
+#define TFA98XX_DCDC_CONTROL0_DCMCC_MAX 15
+#define TFA98XX_DCDC_CONTROL0_DCMCC_MSK 0x78
+
+/*
+ * bst_coil_value
+ */
+#define TFA98XX_DCDC_CONTROL0_DCCV (0x3<<7)
+#define TFA98XX_DCDC_CONTROL0_DCCV_POS 7
+#define TFA98XX_DCDC_CONTROL0_DCCV_LEN 2
+#define TFA98XX_DCDC_CONTROL0_DCCV_MAX 3
+#define TFA98XX_DCDC_CONTROL0_DCCV_MSK 0x180
+
+/*
+ * boost_intel
+ */
+#define TFA98XX_DCDC_CONTROL0_DCIE (0x1<<9)
+#define TFA98XX_DCDC_CONTROL0_DCIE_POS 9
+#define TFA98XX_DCDC_CONTROL0_DCIE_LEN 1
+#define TFA98XX_DCDC_CONTROL0_DCIE_MAX 1
+#define TFA98XX_DCDC_CONTROL0_DCIE_MSK 0x200
+
+/*
+ * boost_speed
+ */
+#define TFA98XX_DCDC_CONTROL0_DCSR (0x1<<10)
+#define TFA98XX_DCDC_CONTROL0_DCSR_POS 10
+#define TFA98XX_DCDC_CONTROL0_DCSR_LEN 1
+#define TFA98XX_DCDC_CONTROL0_DCSR_MAX 1
+#define TFA98XX_DCDC_CONTROL0_DCSR_MSK 0x400
+
+/*
+ * dcdc_synchronisation
+ */
+#define TFA98XX_DCDC_CONTROL0_DCSYNCP (0x7<<11)
+#define TFA98XX_DCDC_CONTROL0_DCSYNCP_POS 11
+#define TFA98XX_DCDC_CONTROL0_DCSYNCP_LEN 3
+#define TFA98XX_DCDC_CONTROL0_DCSYNCP_MAX 7
+#define TFA98XX_DCDC_CONTROL0_DCSYNCP_MSK 0x3800
+
+/*
+ * dcdcoff_mode
+ */
+#define TFA98XX_DCDC_CONTROL0_DCDIS (0x1<<14)
+#define TFA98XX_DCDC_CONTROL0_DCDIS_POS 14
+#define TFA98XX_DCDC_CONTROL0_DCDIS_LEN 1
+#define TFA98XX_DCDC_CONTROL0_DCDIS_MAX 1
+#define TFA98XX_DCDC_CONTROL0_DCDIS_MSK 0x4000
+
+
+/*
+ * (0x90)-cf_controls
+ */
+
+/*
+ * cf_rst_dsp
+ */
+#define TFA98XX_CF_CONTROLS_RST (0x1<<0)
+#define TFA98XX_CF_CONTROLS_RST_POS 0
+#define TFA98XX_CF_CONTROLS_RST_LEN 1
+#define TFA98XX_CF_CONTROLS_RST_MAX 1
+#define TFA98XX_CF_CONTROLS_RST_MSK 0x1
+
+/*
+ * cf_dmem
+ */
+#define TFA98XX_CF_CONTROLS_DMEM (0x3<<1)
+#define TFA98XX_CF_CONTROLS_DMEM_POS 1
+#define TFA98XX_CF_CONTROLS_DMEM_LEN 2
+#define TFA98XX_CF_CONTROLS_DMEM_MAX 3
+#define TFA98XX_CF_CONTROLS_DMEM_MSK 0x6
+
+/*
+ * cf_aif
+ */
+#define TFA98XX_CF_CONTROLS_AIF (0x1<<3)
+#define TFA98XX_CF_CONTROLS_AIF_POS 3
+#define TFA98XX_CF_CONTROLS_AIF_LEN 1
+#define TFA98XX_CF_CONTROLS_AIF_MAX 1
+#define TFA98XX_CF_CONTROLS_AIF_MSK 0x8
+
+/*
+ * cf_int
+ */
+#define TFA98XX_CF_CONTROLS_CFINT (0x1<<4)
+#define TFA98XX_CF_CONTROLS_CFINT_POS 4
+#define TFA98XX_CF_CONTROLS_CFINT_LEN 1
+#define TFA98XX_CF_CONTROLS_CFINT_MAX 1
+#define TFA98XX_CF_CONTROLS_CFINT_MSK 0x10
+
+/*
+ * cf_cgate_off
+ */
+#define TFA98XX_CF_CONTROLS_CFCGATE (0x1<<5)
+#define TFA98XX_CF_CONTROLS_CFCGATE_POS 5
+#define TFA98XX_CF_CONTROLS_CFCGATE_LEN 1
+#define TFA98XX_CF_CONTROLS_CFCGATE_MAX 1
+#define TFA98XX_CF_CONTROLS_CFCGATE_MSK 0x20
+
+/*
+ * cf_req_cmd
+ */
+#define TFA98XX_CF_CONTROLS_REQCMD (0x1<<8)
+#define TFA98XX_CF_CONTROLS_REQCMD_POS 8
+#define TFA98XX_CF_CONTROLS_REQCMD_LEN 1
+#define TFA98XX_CF_CONTROLS_REQCMD_MAX 1
+#define TFA98XX_CF_CONTROLS_REQCMD_MSK 0x100
+
+/*
+ * cf_req_reset
+ */
+#define TFA98XX_CF_CONTROLS_REQRST (0x1<<9)
+#define TFA98XX_CF_CONTROLS_REQRST_POS 9
+#define TFA98XX_CF_CONTROLS_REQRST_LEN 1
+#define TFA98XX_CF_CONTROLS_REQRST_MAX 1
+#define TFA98XX_CF_CONTROLS_REQRST_MSK 0x200
+
+/*
+ * cf_req_mips
+ */
+#define TFA98XX_CF_CONTROLS_REQMIPS (0x1<<10)
+#define TFA98XX_CF_CONTROLS_REQMIPS_POS 10
+#define TFA98XX_CF_CONTROLS_REQMIPS_LEN 1
+#define TFA98XX_CF_CONTROLS_REQMIPS_MAX 1
+#define TFA98XX_CF_CONTROLS_REQMIPS_MSK 0x400
+
+/*
+ * cf_req_mute_ready
+ */
+#define TFA98XX_CF_CONTROLS_REQMUTED (0x1<<11)
+#define TFA98XX_CF_CONTROLS_REQMUTED_POS 11
+#define TFA98XX_CF_CONTROLS_REQMUTED_LEN 1
+#define TFA98XX_CF_CONTROLS_REQMUTED_MAX 1
+#define TFA98XX_CF_CONTROLS_REQMUTED_MSK 0x800
+
+/*
+ * cf_req_volume_ready
+ */
+#define TFA98XX_CF_CONTROLS_REQVOL (0x1<<12)
+#define TFA98XX_CF_CONTROLS_REQVOL_POS 12
+#define TFA98XX_CF_CONTROLS_REQVOL_LEN 1
+#define TFA98XX_CF_CONTROLS_REQVOL_MAX 1
+#define TFA98XX_CF_CONTROLS_REQVOL_MSK 0x1000
+
+/*
+ * cf_req_damage
+ */
+#define TFA98XX_CF_CONTROLS_REQDMG (0x1<<13)
+#define TFA98XX_CF_CONTROLS_REQDMG_POS 13
+#define TFA98XX_CF_CONTROLS_REQDMG_LEN 1
+#define TFA98XX_CF_CONTROLS_REQDMG_MAX 1
+#define TFA98XX_CF_CONTROLS_REQDMG_MSK 0x2000
+
+/*
+ * cf_req_calibrate_ready
+ */
+#define TFA98XX_CF_CONTROLS_REQCAL (0x1<<14)
+#define TFA98XX_CF_CONTROLS_REQCAL_POS 14
+#define TFA98XX_CF_CONTROLS_REQCAL_LEN 1
+#define TFA98XX_CF_CONTROLS_REQCAL_MAX 1
+#define TFA98XX_CF_CONTROLS_REQCAL_MSK 0x4000
+
+/*
+ * cf_req_reserved
+ */
+#define TFA98XX_CF_CONTROLS_REQRSV (0x1<<15)
+#define TFA98XX_CF_CONTROLS_REQRSV_POS 15
+#define TFA98XX_CF_CONTROLS_REQRSV_LEN 1
+#define TFA98XX_CF_CONTROLS_REQRSV_MAX 1
+#define TFA98XX_CF_CONTROLS_REQRSV_MSK 0x8000
+
+
+/*
+ * (0x91)-cf_mad
+ */
+
+/*
+ * cf_madd
+ */
+#define TFA98XX_CF_MAD_MADD (0xffff<<0)
+#define TFA98XX_CF_MAD_MADD_POS 0
+#define TFA98XX_CF_MAD_MADD_LEN 16
+#define TFA98XX_CF_MAD_MADD_MAX 65535
+#define TFA98XX_CF_MAD_MADD_MSK 0xffff
+
+
+/*
+ * (0x92)-cf_mem
+ */
+
+/*
+ * cf_mema
+ */
+#define TFA98XX_CF_MEM_MEMA (0xffff<<0)
+#define TFA98XX_CF_MEM_MEMA_POS 0
+#define TFA98XX_CF_MEM_MEMA_LEN 16
+#define TFA98XX_CF_MEM_MEMA_MAX 65535
+#define TFA98XX_CF_MEM_MEMA_MSK 0xffff
+
+
+/*
+ * (0x93)-cf_status
+ */
+
+/*
+ * cf_err
+ */
+#define TFA98XX_CF_STATUS_ERR (0xff<<0)
+#define TFA98XX_CF_STATUS_ERR_POS 0
+#define TFA98XX_CF_STATUS_ERR_LEN 8
+#define TFA98XX_CF_STATUS_ERR_MAX 255
+#define TFA98XX_CF_STATUS_ERR_MSK 0xff
+
+/*
+ * cf_ack_cmd
+ */
+#define TFA98XX_CF_STATUS_ACKCMD (0x1<<8)
+#define TFA98XX_CF_STATUS_ACKCMD_POS 8
+#define TFA98XX_CF_STATUS_ACKCMD_LEN 1
+#define TFA98XX_CF_STATUS_ACKCMD_MAX 1
+#define TFA98XX_CF_STATUS_ACKCMD_MSK 0x100
+
+/*
+ * cf_ack_reset
+ */
+#define TFA98XX_CF_STATUS_ACKRST (0x1<<9)
+#define TFA98XX_CF_STATUS_ACKRST_POS 9
+#define TFA98XX_CF_STATUS_ACKRST_LEN 1
+#define TFA98XX_CF_STATUS_ACKRST_MAX 1
+#define TFA98XX_CF_STATUS_ACKRST_MSK 0x200
+
+/*
+ * cf_ack_mips
+ */
+#define TFA98XX_CF_STATUS_ACKMIPS (0x1<<10)
+#define TFA98XX_CF_STATUS_ACKMIPS_POS 10
+#define TFA98XX_CF_STATUS_ACKMIPS_LEN 1
+#define TFA98XX_CF_STATUS_ACKMIPS_MAX 1
+#define TFA98XX_CF_STATUS_ACKMIPS_MSK 0x400
+
+/*
+ * cf_ack_mute_ready
+ */
+#define TFA98XX_CF_STATUS_ACKMUTED (0x1<<11)
+#define TFA98XX_CF_STATUS_ACKMUTED_POS 11
+#define TFA98XX_CF_STATUS_ACKMUTED_LEN 1
+#define TFA98XX_CF_STATUS_ACKMUTED_MAX 1
+#define TFA98XX_CF_STATUS_ACKMUTED_MSK 0x800
+
+/*
+ * cf_ack_volume_ready
+ */
+#define TFA98XX_CF_STATUS_ACKVOL (0x1<<12)
+#define TFA98XX_CF_STATUS_ACKVOL_POS 12
+#define TFA98XX_CF_STATUS_ACKVOL_LEN 1
+#define TFA98XX_CF_STATUS_ACKVOL_MAX 1
+#define TFA98XX_CF_STATUS_ACKVOL_MSK 0x1000
+
+/*
+ * cf_ack_damage
+ */
+#define TFA98XX_CF_STATUS_ACKDMG (0x1<<13)
+#define TFA98XX_CF_STATUS_ACKDMG_POS 13
+#define TFA98XX_CF_STATUS_ACKDMG_LEN 1
+#define TFA98XX_CF_STATUS_ACKDMG_MAX 1
+#define TFA98XX_CF_STATUS_ACKDMG_MSK 0x2000
+
+/*
+ * cf_ack_calibrate_ready
+ */
+#define TFA98XX_CF_STATUS_ACKCAL (0x1<<14)
+#define TFA98XX_CF_STATUS_ACKCAL_POS 14
+#define TFA98XX_CF_STATUS_ACKCAL_LEN 1
+#define TFA98XX_CF_STATUS_ACKCAL_MAX 1
+#define TFA98XX_CF_STATUS_ACKCAL_MSK 0x4000
+
+/*
+ * cf_ack_reserved
+ */
+#define TFA98XX_CF_STATUS_ACKRSV (0x1<<15)
+#define TFA98XX_CF_STATUS_ACKRSV_POS 15
+#define TFA98XX_CF_STATUS_ACKRSV_LEN 1
+#define TFA98XX_CF_STATUS_ACKRSV_MAX 1
+#define TFA98XX_CF_STATUS_ACKRSV_MSK 0x8000
+
+
+/*
+ * (0xa1)-mtpkey2_reg
+ */
+
+/*
+ * mtpkey2
+ */
+#define TFA98XX_MTPKEY2_REG_MTPK (0xff<<0)
+#define TFA98XX_MTPKEY2_REG_MTPK_POS 0
+#define TFA98XX_MTPKEY2_REG_MTPK_LEN 8
+#define TFA98XX_MTPKEY2_REG_MTPK_MAX 255
+#define TFA98XX_MTPKEY2_REG_MTPK_MSK 0xff
+
+
+/*
+ * (0xa2)-mtp_status
+ */
+
+/*
+ * key01_locked
+ */
+#define TFA98XX_MTP_STATUS_KEY1LOCKED (0x1<<0)
+#define TFA98XX_MTP_STATUS_KEY1LOCKED_POS 0
+#define TFA98XX_MTP_STATUS_KEY1LOCKED_LEN 1
+#define TFA98XX_MTP_STATUS_KEY1LOCKED_MAX 1
+#define TFA98XX_MTP_STATUS_KEY1LOCKED_MSK 0x1
+
+/*
+ * key02_locked
+ */
+#define TFA98XX_MTP_STATUS_KEY2LOCKED (0x1<<1)
+#define TFA98XX_MTP_STATUS_KEY2LOCKED_POS 1
+#define TFA98XX_MTP_STATUS_KEY2LOCKED_LEN 1
+#define TFA98XX_MTP_STATUS_KEY2LOCKED_MAX 1
+#define TFA98XX_MTP_STATUS_KEY2LOCKED_MSK 0x2
+
+
+/*
+ * (0xa3)-KEY_protected_mtp_control
+ */
+
+/*
+ * auto_copy_iic_to_mtp
+ */
+#define TFA98XX_KEY_PROTECTED_MTP_CONTROL_CIMTP (0x1<<6)
+#define TFA98XX_KEY_PROTECTED_MTP_CONTROL_CIMTP_POS 6
+#define TFA98XX_KEY_PROTECTED_MTP_CONTROL_CIMTP_LEN 1
+#define TFA98XX_KEY_PROTECTED_MTP_CONTROL_CIMTP_MAX 1
+#define TFA98XX_KEY_PROTECTED_MTP_CONTROL_CIMTP_MSK 0x40
+
+
+/*
+ * (0xa5)-mtp_data_out_msb
+ */
+
+/*
+ * mtp_man_data_out_msb
+ */
+#define TFA98XX_MTP_DATA_OUT_MSB_MTPRDMSB (0xffff<<0)
+#define TFA98XX_MTP_DATA_OUT_MSB_MTPRDMSB_POS 0
+#define TFA98XX_MTP_DATA_OUT_MSB_MTPRDMSB_LEN 16
+#define TFA98XX_MTP_DATA_OUT_MSB_MTPRDMSB_MAX 65535
+#define TFA98XX_MTP_DATA_OUT_MSB_MTPRDMSB_MSK 0xffff
+
+
+/*
+ * (0xa6)-mtp_data_out_lsb
+ */
+
+/*
+ * mtp_man_data_out_lsb
+ */
+#define TFA98XX_MTP_DATA_OUT_LSB_MTPRDLSB (0xffff<<0)
+#define TFA98XX_MTP_DATA_OUT_LSB_MTPRDLSB_POS 0
+#define TFA98XX_MTP_DATA_OUT_LSB_MTPRDLSB_LEN 16
+#define TFA98XX_MTP_DATA_OUT_LSB_MTPRDLSB_MAX 65535
+#define TFA98XX_MTP_DATA_OUT_LSB_MTPRDLSB_MSK 0xffff
+
+
+/*
+ * (0xb1)-temp_sensor_config
+ */
+
+/*
+ * ext_temp
+ */
+#define TFA98XX_TEMP_SENSOR_CONFIG_EXTTS (0x1ff<<0)
+#define TFA98XX_TEMP_SENSOR_CONFIG_EXTTS_POS 0
+#define TFA98XX_TEMP_SENSOR_CONFIG_EXTTS_LEN 9
+#define TFA98XX_TEMP_SENSOR_CONFIG_EXTTS_MAX 511
+#define TFA98XX_TEMP_SENSOR_CONFIG_EXTTS_MSK 0x1ff
+
+/*
+ * ext_temp_sel
+ */
+#define TFA98XX_TEMP_SENSOR_CONFIG_TROS (0x1<<9)
+#define TFA98XX_TEMP_SENSOR_CONFIG_TROS_POS 9
+#define TFA98XX_TEMP_SENSOR_CONFIG_TROS_LEN 1
+#define TFA98XX_TEMP_SENSOR_CONFIG_TROS_MAX 1
+#define TFA98XX_TEMP_SENSOR_CONFIG_TROS_MSK 0x200
+
+
+/*
+ * (0xf0)-KEY2_protected_MTP0
+ */
+
+/*
+ * calibration_onetime
+ */
+#define TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC (0x1<<0)
+#define TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC_POS 0
+#define TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC_LEN 1
+#define TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC_MAX 1
+#define TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC_MSK 0x1
+
+/*
+ * calibr_ron_done
+ */
+#define TFA98XX_KEY2_PROTECTED_MTP0_MTPEX (0x1<<1)
+#define TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_POS 1
+#define TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_LEN 1
+#define TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_MAX 1
+#define TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_MSK 0x2
+
+/*
+ * calibr_dcdc_api_calibrate
+ */
+#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCAPI (0x1<<2)
+#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCAPI_POS 2
+#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCAPI_LEN 1
+#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCAPI_MAX 1
+#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCAPI_MSK 0x4
+
+/*
+ * calibr_dcdc_delta_sign
+ */
+#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCSB (0x1<<3)
+#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCSB_POS 3
+#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCSB_LEN 1
+#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCSB_MAX 1
+#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCSB_MSK 0x8
+
+/*
+ * calibr_dcdc_delta
+ */
+#define TFA98XX_KEY2_PROTECTED_MTP0_USERDEF (0x7<<4)
+#define TFA98XX_KEY2_PROTECTED_MTP0_USERDEF_POS 4
+#define TFA98XX_KEY2_PROTECTED_MTP0_USERDEF_LEN 3
+#define TFA98XX_KEY2_PROTECTED_MTP0_USERDEF_MAX 7
+#define TFA98XX_KEY2_PROTECTED_MTP0_USERDEF_MSK 0x70
+
+
+/*
+ * (0xf4)-KEY1_protected_MTP4
+ */
+
+
+/*
+ * (0xf5)-KEY1_protected_MTP5
+ */
+
+#endif /* TFA98XX_GENREGS_H */
diff --git a/inc/tfa98xx_parameters.h b/sound/soc/codecs/tfa98xx_parameters.h
similarity index 95%
rename from inc/tfa98xx_parameters.h
rename to sound/soc/codecs/tfa98xx_parameters.h
index f775403..d2d68f7 100644
--- a/inc/tfa98xx_parameters.h
+++ b/sound/soc/codecs/tfa98xx_parameters.h
@@ -1,724 +1,724 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef TFA98XXPARAMETERS_H_
-#define TFA98XXPARAMETERS_H_
-
-#ifdef __KERNEL__
-#include <linux/types.h>
-#else
-#include <stdint.h>
-#endif
-
-#include "tfa_service.h"
-
-#if (defined(WIN32) || defined(_X64))
-/* These warnings are disabled because it is only given by Windows and there is no easy fix */
-#pragma warning(disable:4200)
-#pragma warning(disable:4214)
-#endif
-
-/*
- * profiles & volumesteps
- *
- */
-#define TFA_MAX_PROFILES (64)
-#define TFA_MAX_VSTEPS (64)
-#define TFA_MAX_VSTEP_MSG_MARKER (100) /* This marker is used to indicate if all msgs need to be written to the device */
-#define TFA_MAX_MSGS (10)
-
-// the pack pragma is required to make that the size in memory
-// matches the actual variable lenghts
-// This is to assure that the binary files can be transported between
-// different platforms.
-#pragma pack (push, 1)
-
-/*
- * typedef for 24 bit value using 3 bytes
- */
-typedef struct uint24 {
- uint8_t b[3];
-} uint24_t;
-/*
- * the generic header
- * all char types are in ASCII
- */
-typedef struct nxpTfaHeader {
- uint16_t id;
- char version[2]; // "V_" : V=version, vv=subversion
- char subversion[2]; // "vv" : vv=subversion
- uint16_t size; // data size in bytes following CRC
- uint32_t CRC; // 32-bits CRC for following data
- char customer[8]; // “name of customer”
- char application[8]; // “application name”
- char type[8]; // “application type name”
-} nxpTfaHeader_t;
-
-typedef enum nxpTfaSamplerate {
- fs_8k, // 8kHz
- fs_11k025, // 11.025kHz
- fs_12k, // 12kHz
- fs_16k, // 16kHz
- fs_22k05, // 22.05kHz
- fs_24k, // 24kHz
- fs_32k, // 32kHz
- fs_44k1, // 44.1kHz
- fs_48k, // 48kHz
- fs_96k, // 96kHz
- fs_count // Should always be last item.
-} nxpTfaSamplerate_t;
-
-// Keep in sync with nxpTfaSamplerate_t !
-static const int nxpTfaSamplerateHz[fs_count] = { 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000, 96000 };
-
-
-/*
- * coolflux direct memory access
- */
-typedef struct nxpTfaDspMem {
- uint8_t type; /* 0--3: p, x, y, iomem */
- uint16_t address; /* target address */
- uint8_t size; /* data size in words */
- int words[]; /* payload in signed 32bit integer (two's complement) */
-} nxpTfaDspMem_t;
-
-/*
- * the biquad coefficients for the API together with index in filter
- * the biquad_index is the actual index in the equalizer +1
- */
-#define BIQUAD_COEFF_SIZE 6
-
-/*
-* Output fixed point coeffs structure
-*/
-typedef struct {
- int a2;
- int a1;
- int b2;
- int b1;
- int b0;
-}nxpTfaBiquad_t;
-
-typedef struct nxpTfaBiquadOld {
- uint8_t bytes[BIQUAD_COEFF_SIZE*sizeof(uint24_t)];
-}nxpTfaBiquadOld_t;
-
-typedef struct nxpTfaBiquadFloat {
- float headroom;
- float b0;
- float b1;
- float b2;
- float a1;
- float a2;
-} nxpTfaBiquadFloat_t;
-
-/*
-* EQ filter definitions
-* Note: This is not in line with smartstudio (JV: 12/12/2016)
-*/
-typedef enum nxpTfaFilterType {
- fCustom, //User defined biquad coefficients
- fFlat, //Vary only gain
- fLowpass, //2nd order Butterworth low pass
- fHighpass, //2nd order Butterworth high pass
- fLowshelf,
- fHighshelf,
- fNotch,
- fPeak,
- fBandpass,
- f1stLP,
- f1stHP,
- fElliptic
-} nxpTfaFilterType_t;
-
-/*
- * filter parameters for biquad (re-)calculation
- */
-typedef struct nxpTfaFilter {
- nxpTfaBiquadOld_t biquad;
- uint8_t enabled;
- uint8_t type; // (== enum FilterTypes, assure 8bits length)
- float frequency;
- float Q;
- float gain;
-} nxpTfaFilter_t ; //8 * float + int32 + byte == 37
-
-/*
- * biquad params for calculation
-*/
-
-#define TFA_BQ_EQ_INDEX 0
-#define TFA_BQ_ANTI_ALIAS_INDEX 10
-#define TFA_BQ_INTEGRATOR_INDEX 13
-
-/*
-* Loudspeaker Compensation filter definitions
-*/
-typedef struct nxpTfaLsCompensationFilter {
- nxpTfaBiquad_t biquad;
- uint8_t lsCompOn; // Loudspeaker compensation on/off; when 'off', the DSP code doesn't apply the bwExt => bwExtOn GUI flag should be gray to avoid confusion
- uint8_t bwExtOn; // Bandwidth extension on/off
- float fRes; // [Hz] speaker resonance frequency
- float Qt; // Speaker resonance Q-factor
- float fBwExt; // [Hz] Band width extension frequency
- float samplingFreq;// [Hz] Sampling frequency
-} nxpTfaLsCompensationFilter_t;
-
-/*
-* Anti Aliasing Elliptic filter definitions
-*/
-typedef struct nxpTfaAntiAliasFilter {
- nxpTfaBiquad_t biquad; /**< Output results fixed point coeffs */
- uint8_t enabled;
- float cutOffFreq; // cut off frequency
- float samplingFreq; // sampling frequency
- float rippleDb; // range: [0.1 3.0]
- float rolloff; // range: [-1.0 1.0]
-} nxpTfaAntiAliasFilter_t;
-
-/**
-* Integrator filter input definitions
-*/
-typedef struct nxpTfaIntegratorFilter {
- nxpTfaBiquad_t biquad; /**< Output results fixed point coeffs */
- uint8_t type; /**< Butterworth filter type: high or low pass */
- float cutOffFreq; /**< cut off frequency in Hertz; range: [100.0 4000.0] */
- float samplingFreq; /**< sampling frequency in Hertz */
- float leakage; /**< leakage factor; range [0.0 1.0] */
-} nxpTfaIntegratorFilter_t;
-
-
-typedef struct nxpTfaEqFilter {
- nxpTfaBiquad_t biquad;
- uint8_t enabled;
- uint8_t type; // (== enum FilterTypes, assure 8bits length)
- float cutOffFreq; // cut off frequency, // range: [100.0 4000.0]
- float samplingFreq; // sampling frequency
- float Q; // range: [0.5 5.0]
- float gainDb; // range: [-10.0 10.0]
-} nxpTfaEqFilter_t ; //8 * float + int32 + byte == 37
-
-typedef struct nxpTfaContAntiAlias {
- int8_t index; /**< index determines destination type; anti-alias, integrator,eq */
- uint8_t type;
- float cutOffFreq; // cut off frequency
- float samplingFreq;
- float rippleDb; // integrator leakage
- float rolloff;
- uint8_t bytes[5*3]; // payload 5*24buts coeffs
-}nxpTfaContAntiAlias_t;
-
-typedef struct nxpTfaContIntegrator {
- int8_t index; /**< index determines destination type; anti-alias, integrator,eq */
- uint8_t type;
- float cutOffFreq; // cut off frequency
- float samplingFreq;
- float leakage; // integrator leakage
- float reserved;
- uint8_t bytes[5*3]; // payload 5*24buts coeffs
-}nxpTfaContIntegrator_t;
-
-typedef struct nxpTfaContEq {
- int8_t index;
- uint8_t type; // (== enum FilterTypes, assure 8bits length)
- float cutOffFreq; // cut off frequency, // range: [100.0 4000.0]
- float samplingFreq; // sampling frequency
- float Q; // range: [0.5 5.0]
- float gainDb; // range: [-10.0 10.0]
- uint8_t bytes[5*3]; // payload 5*24buts coeffs
-} nxpTfaContEq_t ; //8 * float + int32 + byte == 37
-
-typedef union nxpTfaContBiquad {
- nxpTfaContEq_t eq;
- nxpTfaContAntiAlias_t aa;
- nxpTfaContIntegrator_t in;
-}nxpTfaContBiquad_t;
-
-#define TFA_BQ_EQ_INDEX 0
-#define TFA_BQ_ANTI_ALIAS_INDEX 10
-#define TFA_BQ_INTEGRATOR_INDEX 13
-#define TFA98XX_MAX_EQ 10
-
-typedef struct nxpTfaEqualizer {
- nxpTfaFilter_t filter[TFA98XX_MAX_EQ];
-} nxpTfaEqualizer_t;
-
-/*
- * files
- */
-#define HDR(c1,c2) (c2<<8|c1) // little endian
-typedef enum nxpTfaHeaderType {
- paramsHdr = HDR('P','M'), /* containter file */
- volstepHdr = HDR('V','P'),
- patchHdr = HDR('P','A'),
- speakerHdr = HDR('S','P'),
- presetHdr = HDR('P','R'),
- configHdr = HDR('C','O'),
- equalizerHdr = HDR('E','Q'),
- drcHdr = HDR('D','R'),
- msgHdr = HDR('M','G'), /* generic message */
- infoHdr = HDR('I','N')
-} nxpTfaHeaderType_t;
-
-/*
- * equalizer file
- */
-#define NXPTFA_EQ_VERSION '1'
-#define NXPTFA_EQ_SUBVERSION "00"
-typedef struct nxpTfaEqualizerFile {
- nxpTfaHeader_t hdr;
- uint8_t samplerate; // ==enum samplerates, assure 8 bits
- nxpTfaFilter_t filter[TFA98XX_MAX_EQ];// note: API index counts from 1..10
-} nxpTfaEqualizerFile_t;
-
-/*
- * patch file
- */
-#define NXPTFA_PA_VERSION '1'
-#define NXPTFA_PA_SUBVERSION "00"
-typedef struct nxpTfaPatchFile {
- nxpTfaHeader_t hdr;
- uint8_t data[];
-} nxpTfaPatch_t;
-
-/*
- * generic message file
- * - the payload of this file includes the opcode and is send straight to the DSP
- */
-#define NXPTFA_MG_VERSION '3'
-#define NXPTFA_MG_SUBVERSION "00"
-typedef struct nxpTfaMsgFile {
- nxpTfaHeader_t hdr;
- uint8_t data[];
-} nxpTfaMsgFile_t;
-
-/*
- * NOTE the tfa98xx API defines the enum Tfa98xx_config_type that defines
- * the subtypes as decribes below.
- * tfa98xx_dsp_config_parameter_type() can be used to get the
- * supported type for the active device..
- */
-/*
- * config file V1 sub 1
- */
-#define NXPTFA_CO_VERSION '1'
-#define NXPTFA_CO3_VERSION '3'
-#define NXPTFA_CO_SUBVERSION1 "01"
-typedef struct nxpTfaConfigS1File {
- nxpTfaHeader_t hdr;
- uint8_t data[55*3];
-} nxpTfaConfigS1_t;
-
-/*
- * config file V1 sub 2
- */
-#define NXPTFA_CO_SUBVERSION2 "02"
-typedef struct nxpTfaConfigS2File {
- nxpTfaHeader_t hdr;
- uint8_t data[67*3];
-} nxpTfaConfigS2_t;
-
-/*
- * config file V1 sub 3
- */
-#define NXPTFA_CO_SUBVERSION3 "03"
-typedef struct nxpTfaConfigS3File {
- nxpTfaHeader_t hdr;
- uint8_t data[67*3];
-} nxpTfaConfigS3_t;
-
-/*
- * config file V1.0
- */
-#define NXPTFA_CO_SUBVERSION "00"
-typedef struct nxpTfaConfigFile {
- nxpTfaHeader_t hdr;
- uint8_t data[];
-} nxpTfaConfig_t;
-
-/*
- * preset file
- */
-#define NXPTFA_PR_VERSION '1'
-#define NXPTFA_PR_SUBVERSION "00"
-typedef struct nxpTfaPresetFile {
- nxpTfaHeader_t hdr;
- uint8_t data[];
-} nxpTfaPreset_t;
-
-/*
- * drc file
- */
-#define NXPTFA_DR_VERSION '1'
-#define NXPTFA_DR_SUBVERSION "00"
-typedef struct nxpTfaDrcFile {
- nxpTfaHeader_t hdr;
- uint8_t data[];
-} nxpTfaDrc_t;
-
-/*
- * drc file
- * for tfa 2 there is also a xml-version
- */
-#define NXPTFA_DR3_VERSION '3'
-#define NXPTFA_DR3_SUBVERSION "00"
-typedef struct nxpTfaDrcFile2 {
- nxpTfaHeader_t hdr;
- uint8_t version[3];
- uint8_t data[];
-} nxpTfaDrc2_t;
-
-/*
- * volume step structures
- */
-// VP01
-#define NXPTFA_VP1_VERSION '1'
-#define NXPTFA_VP1_SUBVERSION "01"
-typedef struct nxpTfaVolumeStep1 {
- float attenuation; // IEEE single float
- uint8_t preset[TFA98XX_PRESET_LENGTH];
-} nxpTfaVolumeStep1_t;
-
-// VP02
-#define NXPTFA_VP2_VERSION '2'
-#define NXPTFA_VP2_SUBVERSION "01"
-typedef struct nxpTfaVolumeStep2 {
- float attenuation; // IEEE single float
- uint8_t preset[TFA98XX_PRESET_LENGTH];
- nxpTfaFilter_t filter[TFA98XX_MAX_EQ];// note: API index counts from 1..10
-} nxpTfaVolumeStep2_t;
-
-/*
- * volumestep file
- */
-#define NXPTFA_VP_VERSION '1'
-#define NXPTFA_VP_SUBVERSION "00"
-typedef struct nxpTfaVolumeStepFile {
- nxpTfaHeader_t hdr;
- uint8_t vsteps; // can also be calulated from size+type
- uint8_t samplerate; // ==enum samplerates, assure 8 bits
- uint8_t payload; //start of variable length contents:N times volsteps
-}nxpTfaVolumeStepFile_t;
-/*
- * volumestep2 file
- */
-typedef struct nxpTfaVolumeStep2File {
- nxpTfaHeader_t hdr;
- uint8_t vsteps; // can also be calulated from size+type
- uint8_t samplerate; // ==enum samplerates, assure 8 bits
- nxpTfaVolumeStep2_t vstep[]; //start of variable length contents:N times volsteps
-}nxpTfaVolumeStep2File_t;
-
-/*
- * volumestepMax2 file
- */
-typedef struct nxpTfaVolumeStepMax2File {
- nxpTfaHeader_t hdr;
- uint8_t version[3];
- uint8_t NrOfVsteps;
- uint8_t vstepsBin[];
-}nxpTfaVolumeStepMax2File_t;
-
-/*
- * volumestepMax2 file
- * This volumestep should ONLY be used for the use of bin2hdr!
- * This can only be used to find the messagetype of the vstep (without header)
- */
-typedef struct nxpTfaVolumeStepMax2_1File {
- uint8_t version[3];
- uint8_t NrOfVsteps;
- uint8_t vstepsBin[];
-}nxpTfaVolumeStepMax2_1File_t;
-
-struct nxpTfaVolumeStepRegisterInfo {
- uint8_t NrOfRegisters;
- uint16_t registerInfo[];
-};
-
-struct nxpTfaVolumeStepMessageInfo {
- uint8_t NrOfMessages;
- uint8_t MessageType;
- uint24_t MessageLength;
- uint8_t CmdId[3];
- uint8_t ParameterData[];
-};
-/**************************old v2 *************************************************/
-
-/*
- * subv 00 volumestep file
- */
-typedef struct nxpTfaOldHeader {
- uint16_t id;
- char version[2]; // "V_" : V=version, vv=subversion
- char subversion[2]; // "vv" : vv=subversion
- uint16_t size; // data size in bytes following CRC
- uint32_t CRC; // 32-bits CRC for following data
-} nxpTfaOldHeader_t;
-
-typedef struct nxpOldTfaFilter {
- double bq[5];
- int32_t type;
- double frequency;
- double Q;
- double gain;
- uint8_t enabled;
-} nxpTfaOldFilter_t ;
-
-typedef struct nxpTfaOldVolumeStep2 {
- float attenuation; // IEEE single float
- uint8_t preset[TFA98XX_PRESET_LENGTH];
- nxpTfaOldFilter_t eq[10];
-} nxpTfaOldVolumeStep2_t;
-
-typedef struct nxpTfaOldVolumeStepFile {
- nxpTfaOldHeader_t hdr;
- nxpTfaOldVolumeStep2_t step[];
-}nxpTfaOldVolumeStep2File_t;
-/**************************end old v2 *************************************************/
-
-/*
- * speaker file header
- */
-struct nxpTfaSpkHeader {
- struct nxpTfaHeader hdr;
- char name[8]; // speaker nick name (e.g. “dumbo”)
- char vendor[16];
- char type[8];
- // dimensions (mm)
- uint8_t height;
- uint8_t width;
- uint8_t depth;
- uint16_t ohm;
-};
-
-/*
- * speaker file
- */
-#define NXPTFA_SP_VERSION '1'
-#define NXPTFA_SP_SUBVERSION "00"
-typedef struct nxpTfaSpeakerFile {
- nxpTfaHeader_t hdr;
- char name[8]; // speaker nick name (e.g. “dumbo”)
- char vendor[16];
- char type[8];
- // dimensions (mm)
- uint8_t height;
- uint8_t width;
- uint8_t depth;
- uint8_t ohm_primary;
- uint8_t ohm_secondary;
- uint8_t data[]; //payload TFA98XX_SPEAKERPARAMETER_LENGTH
-} nxpTfaSpeakerFile_t;
-
-#define NXPTFA_VP3_VERSION '3'
-#define NXPTFA_VP3_SUBVERSION "00"
-
-struct nxpTfaFWVer {
- uint8_t Major;
- uint8_t minor;
- uint8_t minor_update:6;
- uint8_t Update:2;
-};
-
-struct nxpTfaFWMsg {
- struct nxpTfaFWVer fwVersion;
- struct nxpTfaMsg payload;
-};
-
-typedef struct nxpTfaLiveData {
- char name[25];
- char addrs[25];
- int tracker;
- int scalefactor;
-} nxpTfaLiveData_t;
-
-#define NXPTFA_SP3_VERSION '3'
-#define NXPTFA_SP3_SUBVERSION "00"
-struct nxpTfaSpeakerFileMax2 {
- nxpTfaHeader_t hdr;
- char name[8]; // speaker nick name (e.g. “dumbo”)
- char vendor[16];
- char type[8];
- // dimensions (mm)
- uint8_t height;
- uint8_t width;
- uint8_t depth;
- uint8_t ohm_primary;
- uint8_t ohm_secondary;
- struct nxpTfaFWMsg FWmsg; //payload including FW ver and Cmd ID
-};
-
-/*
- * parameter container file
- */
-/*
- * descriptors
- * Note 1: append new DescriptorType at the end
- * Note 2: add new descriptors to dsc_name[] in tfaContUtil.c
- */
-typedef enum nxpTfaDescriptorType {
- dscDevice, // device list
- dscProfile, // profile list
- dscRegister, // register patch
- dscString, // ascii, zero terminated string
- dscFile, // filename + file contents
- dscPatch, // patch file
- dscMarker, // marker to indicate end of a list
- dscMode,
- dscSetInputSelect,
- dscSetOutputSelect,
- dscSetProgramConfig,
- dscSetLagW,
- dscSetGains,
- dscSetvBatFactors,
- dscSetSensesCal,
- dscSetSensesDelay,
- dscBitfield,
- dscDefault, // used to reset bitfields to there default values
- dscLiveData,
- dscLiveDataString,
- dscGroup,
- dscCmd,
- dscSetMBDrc,
- dscFilter,
- dscNoInit,
- dscFeatures,
- dscCfMem, // coolflux memory x,y,io
- dscSetFwkUseCase,
- dscSetVddpConfig,
- dsc_last // trailer
-} nxpTfaDescriptorType_t;
-
-#define TFA_BITFIELDDSCMSK 0x7fffffff
-typedef struct nxpTfaDescPtr {
- uint32_t offset:24;
- uint32_t type:8; // (== enum nxpTfaDescriptorType, assure 8bits length)
-}nxpTfaDescPtr_t;
-
-/*
- * generic file descriptor
- */
-typedef struct nxpTfaFileDsc {
- nxpTfaDescPtr_t name;
- uint32_t size; // file data length in bytes
- uint8_t data[]; //payload
-} nxpTfaFileDsc_t;
-
-
-/*
- * device descriptor list
- */
-typedef struct nxpTfaDeviceList {
- uint8_t length; // nr of items in the list
- uint8_t bus; // bus
- uint8_t dev; // device
- uint8_t func; // subfunction or subdevice
- uint32_t devid; // device hw fw id
- nxpTfaDescPtr_t name; // device name
- nxpTfaDescPtr_t list[]; // items list
-} nxpTfaDeviceList_t;
-
-/*
- * profile descriptor list
- */
-typedef struct nxpTfaProfileList {
- uint32_t length:8; // nr of items in the list + name
- uint32_t group:8; // profile group number
- uint32_t ID:16; // profile ID
- nxpTfaDescPtr_t name; // profile name
- nxpTfaDescPtr_t list[]; // items list (lenght-1 items)
-} nxpTfaProfileList_t;
-#define TFA_PROFID 0x1234
-
-/*
- * livedata descriptor list
- */
-typedef struct nxpTfaLiveDataList {
- uint32_t length:8; // nr of items in the list
- uint32_t ID:24; // profile ID
- nxpTfaDescPtr_t name; // livedata name
- nxpTfaDescPtr_t list[]; // items list
-} nxpTfaLiveDataList_t;
-#define TFA_LIVEDATAID 0x5678
-
-/*
- * Bitfield descriptor
- */
-typedef struct nxpTfaBitfield {
- uint16_t value;
- uint16_t field; // ==datasheet defined, 16 bits
-} nxpTfaBitfield_t;
-
-/*
- * Bitfield enumuration bits descriptor
- */
-typedef struct nxpTfaBfEnum {
- unsigned int len:4; // this is the actual length-1
- unsigned int pos:4;
- unsigned int address:8;
-} nxpTfaBfEnum_t;
-
-/*
- * Register patch descriptor
- */
-typedef struct nxpTfaRegpatch {
- uint8_t address; // register address
- uint16_t value; // value to write
- uint16_t mask; // mask of bits to write
-} nxpTfaRegpatch_t;
-
-/*
- * Mode descriptor
- */
-typedef struct nxpTfaUseCase {
- int value; // mode value, maps to enum Tfa98xx_Mode
-} nxpTfaMode_t;
-
-/*
- * NoInit descriptor
- */
-typedef struct nxpTfaNoInit {
- uint8_t value; // noInit value
-} nxpTfaNoInit_t;
-
-/*
- * Features descriptor
- */
-typedef struct nxpTfaFeatures {
- uint16_t value[3]; // features value
-} nxpTfaFeatures_t;
-
-
-/*
- * the container file
- * - the size field is 32bits long (generic=16)
- * - all char types are in ASCII
- */
-#define NXPTFA_PM_VERSION '1'
-#define NXPTFA_PM3_VERSION '3'
-#define NXPTFA_PM_SUBVERSION '1'
-typedef struct nxpTfaContainer {
- char id[2]; // "XX" : XX=type
- char version[2]; // "V_" : V=version, vv=subversion
- char subversion[2]; // "vv" : vv=subversion
- uint32_t size; // data size in bytes following CRC
- uint32_t CRC; // 32-bits CRC for following data
- uint16_t rev; // "extra chars for rev nr"
- char customer[8]; // “name of customer”
- char application[8]; // “application name”
- char type[8]; // “application type name”
- uint16_t ndev; // "nr of device lists"
- uint16_t nprof; // "nr of profile lists"
- uint16_t nliveData; // "nr of livedata lists"
- nxpTfaDescPtr_t index[]; // start of item index table
-} nxpTfaContainer_t;
-
-#pragma pack (pop)
-
-#endif /* TFA98XXPARAMETERS_H_ */
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef TFA98XXPARAMETERS_H_
+#define TFA98XXPARAMETERS_H_
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
+#include <stdint.h>
+#endif
+
+#include "tfa_service.h"
+
+#if (defined(WIN32) || defined(_X64))
+/* These warnings are disabled because it is only given by Windows and there is no easy fix */
+#pragma warning(disable:4200)
+#pragma warning(disable:4214)
+#endif
+
+/*
+ * profiles & volumesteps
+ *
+ */
+#define TFA_MAX_PROFILES (64)
+#define TFA_MAX_VSTEPS (64)
+#define TFA_MAX_VSTEP_MSG_MARKER (100) /* This marker is used to indicate if all msgs need to be written to the device */
+#define TFA_MAX_MSGS (10)
+
+// the pack pragma is required to make that the size in memory
+// matches the actual variable lenghts
+// This is to assure that the binary files can be transported between
+// different platforms.
+#pragma pack (push, 1)
+
+/*
+ * typedef for 24 bit value using 3 bytes
+ */
+typedef struct uint24 {
+ uint8_t b[3];
+} uint24_t;
+/*
+ * the generic header
+ * all char types are in ASCII
+ */
+typedef struct nxpTfaHeader {
+ uint16_t id;
+ char version[2]; // "V_" : V=version, vv=subversion
+ char subversion[2]; // "vv" : vv=subversion
+ uint16_t size; // data size in bytes following CRC
+ uint32_t CRC; // 32-bits CRC for following data
+ char customer[8]; // “name of customer”
+ char application[8]; // “application name”
+ char type[8]; // “application type name”
+} nxpTfaHeader_t;
+
+typedef enum nxpTfaSamplerate {
+ fs_8k, // 8kHz
+ fs_11k025, // 11.025kHz
+ fs_12k, // 12kHz
+ fs_16k, // 16kHz
+ fs_22k05, // 22.05kHz
+ fs_24k, // 24kHz
+ fs_32k, // 32kHz
+ fs_44k1, // 44.1kHz
+ fs_48k, // 48kHz
+ fs_96k, // 96kHz
+ fs_count // Should always be last item.
+} nxpTfaSamplerate_t;
+
+// Keep in sync with nxpTfaSamplerate_t !
+static const int nxpTfaSamplerateHz[fs_count] = { 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000, 96000 };
+
+
+/*
+ * coolflux direct memory access
+ */
+typedef struct nxpTfaDspMem {
+ uint8_t type; /* 0--3: p, x, y, iomem */
+ uint16_t address; /* target address */
+ uint8_t size; /* data size in words */
+ int words[]; /* payload in signed 32bit integer (two's complement) */
+} nxpTfaDspMem_t;
+
+/*
+ * the biquad coefficients for the API together with index in filter
+ * the biquad_index is the actual index in the equalizer +1
+ */
+#define BIQUAD_COEFF_SIZE 6
+
+/*
+* Output fixed point coeffs structure
+*/
+typedef struct {
+ int a2;
+ int a1;
+ int b2;
+ int b1;
+ int b0;
+} nxpTfaBiquad_t;
+
+typedef struct nxpTfaBiquadOld {
+ uint8_t bytes[BIQUAD_COEFF_SIZE*sizeof(uint24_t)];
+} nxpTfaBiquadOld_t;
+
+typedef struct nxpTfaBiquadFloat {
+ float headroom;
+ float b0;
+ float b1;
+ float b2;
+ float a1;
+ float a2;
+} nxpTfaBiquadFloat_t;
+
+/*
+* EQ filter definitions
+* Note: This is not in line with smartstudio (JV: 12/12/2016)
+*/
+typedef enum nxpTfaFilterType {
+ fCustom, //User defined biquad coefficients
+ fFlat, //Vary only gain
+ fLowpass, //2nd order Butterworth low pass
+ fHighpass, //2nd order Butterworth high pass
+ fLowshelf,
+ fHighshelf,
+ fNotch,
+ fPeak,
+ fBandpass,
+ f1stLP,
+ f1stHP,
+ fElliptic
+} nxpTfaFilterType_t;
+
+/*
+ * filter parameters for biquad (re-)calculation
+ */
+typedef struct nxpTfaFilter {
+ nxpTfaBiquadOld_t biquad;
+ uint8_t enabled;
+ uint8_t type; // (== enum FilterTypes, assure 8bits length)
+ float frequency;
+ float Q;
+ float gain;
+} nxpTfaFilter_t ; //8 * float + int32 + byte == 37
+
+/*
+ * biquad params for calculation
+*/
+
+#define TFA_BQ_EQ_INDEX 0
+#define TFA_BQ_ANTI_ALIAS_INDEX 10
+#define TFA_BQ_INTEGRATOR_INDEX 13
+
+/*
+* Loudspeaker Compensation filter definitions
+*/
+typedef struct nxpTfaLsCompensationFilter {
+ nxpTfaBiquad_t biquad;
+ uint8_t lsCompOn; // Loudspeaker compensation on/off; when 'off', the DSP code doesn't apply the bwExt => bwExtOn GUI flag should be gray to avoid confusion
+ uint8_t bwExtOn; // Bandwidth extension on/off
+ float fRes; // [Hz] speaker resonance frequency
+ float Qt; // Speaker resonance Q-factor
+ float fBwExt; // [Hz] Band width extension frequency
+ float samplingFreq;// [Hz] Sampling frequency
+} nxpTfaLsCompensationFilter_t;
+
+/*
+* Anti Aliasing Elliptic filter definitions
+*/
+typedef struct nxpTfaAntiAliasFilter {
+ nxpTfaBiquad_t biquad; /**< Output results fixed point coeffs */
+ uint8_t enabled;
+ float cutOffFreq; // cut off frequency
+ float samplingFreq; // sampling frequency
+ float rippleDb; // range: [0.1 3.0]
+ float rolloff; // range: [-1.0 1.0]
+} nxpTfaAntiAliasFilter_t;
+
+/**
+* Integrator filter input definitions
+*/
+typedef struct nxpTfaIntegratorFilter {
+ nxpTfaBiquad_t biquad; /**< Output results fixed point coeffs */
+ uint8_t type; /**< Butterworth filter type: high or low pass */
+ float cutOffFreq; /**< cut off frequency in Hertz; range: [100.0 4000.0] */
+ float samplingFreq; /**< sampling frequency in Hertz */
+ float leakage; /**< leakage factor; range [0.0 1.0] */
+} nxpTfaIntegratorFilter_t;
+
+
+typedef struct nxpTfaEqFilter {
+ nxpTfaBiquad_t biquad;
+ uint8_t enabled;
+ uint8_t type; // (== enum FilterTypes, assure 8bits length)
+ float cutOffFreq; // cut off frequency, // range: [100.0 4000.0]
+ float samplingFreq; // sampling frequency
+ float Q; // range: [0.5 5.0]
+ float gainDb; // range: [-10.0 10.0]
+} nxpTfaEqFilter_t ; //8 * float + int32 + byte == 37
+
+typedef struct nxpTfaContAntiAlias {
+ int8_t index; /**< index determines destination type; anti-alias, integrator,eq */
+ uint8_t type;
+ float cutOffFreq; // cut off frequency
+ float samplingFreq;
+ float rippleDb; // integrator leakage
+ float rolloff;
+ uint8_t bytes[5*3]; // payload 5*24buts coeffs
+} nxpTfaContAntiAlias_t;
+
+typedef struct nxpTfaContIntegrator {
+ int8_t index; /**< index determines destination type; anti-alias, integrator,eq */
+ uint8_t type;
+ float cutOffFreq; // cut off frequency
+ float samplingFreq;
+ float leakage; // integrator leakage
+ float reserved;
+ uint8_t bytes[5*3]; // payload 5*24buts coeffs
+} nxpTfaContIntegrator_t;
+
+typedef struct nxpTfaContEq {
+ int8_t index;
+ uint8_t type; // (== enum FilterTypes, assure 8bits length)
+ float cutOffFreq; // cut off frequency, // range: [100.0 4000.0]
+ float samplingFreq; // sampling frequency
+ float Q; // range: [0.5 5.0]
+ float gainDb; // range: [-10.0 10.0]
+ uint8_t bytes[5*3]; // payload 5*24buts coeffs
+} nxpTfaContEq_t ; //8 * float + int32 + byte == 37
+
+typedef union nxpTfaContBiquad {
+ nxpTfaContEq_t eq;
+ nxpTfaContAntiAlias_t aa;
+ nxpTfaContIntegrator_t in;
+} nxpTfaContBiquad_t;
+
+#define TFA_BQ_EQ_INDEX 0
+#define TFA_BQ_ANTI_ALIAS_INDEX 10
+#define TFA_BQ_INTEGRATOR_INDEX 13
+#define TFA98XX_MAX_EQ 10
+
+typedef struct nxpTfaEqualizer {
+ nxpTfaFilter_t filter[TFA98XX_MAX_EQ];
+} nxpTfaEqualizer_t;
+
+/*
+ * files
+ */
+#define HDR(c1, c2) (c2<<8|c1) // little endian
+typedef enum nxpTfaHeaderType {
+ paramsHdr = HDR('P', 'M'), /* containter file */
+ volstepHdr = HDR('V', 'P'),
+ patchHdr = HDR('P', 'A'),
+ speakerHdr = HDR('S', 'P'),
+ presetHdr = HDR('P', 'R'),
+ configHdr = HDR('C', 'O'),
+ equalizerHdr = HDR('E', 'Q'),
+ drcHdr = HDR('D', 'R'),
+ msgHdr = HDR('M', 'G'), /* generic message */
+ infoHdr = HDR('I', 'N')
+} nxpTfaHeaderType_t;
+
+/*
+ * equalizer file
+ */
+#define NXPTFA_EQ_VERSION '1'
+#define NXPTFA_EQ_SUBVERSION "00"
+typedef struct nxpTfaEqualizerFile {
+ nxpTfaHeader_t hdr;
+ uint8_t samplerate; // ==enum samplerates, assure 8 bits
+ nxpTfaFilter_t filter[TFA98XX_MAX_EQ];// note: API index counts from 1..10
+} nxpTfaEqualizerFile_t;
+
+/*
+ * patch file
+ */
+#define NXPTFA_PA_VERSION '1'
+#define NXPTFA_PA_SUBVERSION "00"
+typedef struct nxpTfaPatchFile {
+ nxpTfaHeader_t hdr;
+ uint8_t data[];
+} nxpTfaPatch_t;
+
+/*
+ * generic message file
+ * - the payload of this file includes the opcode and is send straight to the DSP
+ */
+#define NXPTFA_MG_VERSION '3'
+#define NXPTFA_MG_SUBVERSION "00"
+typedef struct nxpTfaMsgFile {
+ nxpTfaHeader_t hdr;
+ uint8_t data[];
+} nxpTfaMsgFile_t;
+
+/*
+ * NOTE the tfa98xx API defines the enum Tfa98xx_config_type that defines
+ * the subtypes as decribes below.
+ * tfa98xx_dsp_config_parameter_type() can be used to get the
+ * supported type for the active device..
+ */
+/*
+ * config file V1 sub 1
+ */
+#define NXPTFA_CO_VERSION '1'
+#define NXPTFA_CO3_VERSION '3'
+#define NXPTFA_CO_SUBVERSION1 "01"
+typedef struct nxpTfaConfigS1File {
+ nxpTfaHeader_t hdr;
+ uint8_t data[55*3];
+} nxpTfaConfigS1_t;
+
+/*
+ * config file V1 sub 2
+ */
+#define NXPTFA_CO_SUBVERSION2 "02"
+typedef struct nxpTfaConfigS2File {
+ nxpTfaHeader_t hdr;
+ uint8_t data[67*3];
+} nxpTfaConfigS2_t;
+
+/*
+ * config file V1 sub 3
+ */
+#define NXPTFA_CO_SUBVERSION3 "03"
+typedef struct nxpTfaConfigS3File {
+ nxpTfaHeader_t hdr;
+ uint8_t data[67*3];
+} nxpTfaConfigS3_t;
+
+/*
+ * config file V1.0
+ */
+#define NXPTFA_CO_SUBVERSION "00"
+typedef struct nxpTfaConfigFile {
+ nxpTfaHeader_t hdr;
+ uint8_t data[];
+} nxpTfaConfig_t;
+
+/*
+ * preset file
+ */
+#define NXPTFA_PR_VERSION '1'
+#define NXPTFA_PR_SUBVERSION "00"
+typedef struct nxpTfaPresetFile {
+ nxpTfaHeader_t hdr;
+ uint8_t data[];
+} nxpTfaPreset_t;
+
+/*
+ * drc file
+ */
+#define NXPTFA_DR_VERSION '1'
+#define NXPTFA_DR_SUBVERSION "00"
+typedef struct nxpTfaDrcFile {
+ nxpTfaHeader_t hdr;
+ uint8_t data[];
+} nxpTfaDrc_t;
+
+/*
+ * drc file
+ * for tfa 2 there is also a xml-version
+ */
+#define NXPTFA_DR3_VERSION '3'
+#define NXPTFA_DR3_SUBVERSION "00"
+typedef struct nxpTfaDrcFile2 {
+ nxpTfaHeader_t hdr;
+ uint8_t version[3];
+ uint8_t data[];
+} nxpTfaDrc2_t;
+
+/*
+ * volume step structures
+ */
+// VP01
+#define NXPTFA_VP1_VERSION '1'
+#define NXPTFA_VP1_SUBVERSION "01"
+typedef struct nxpTfaVolumeStep1 {
+ float attenuation; // IEEE single float
+ uint8_t preset[TFA98XX_PRESET_LENGTH];
+} nxpTfaVolumeStep1_t;
+
+// VP02
+#define NXPTFA_VP2_VERSION '2'
+#define NXPTFA_VP2_SUBVERSION "01"
+typedef struct nxpTfaVolumeStep2 {
+ float attenuation; // IEEE single float
+ uint8_t preset[TFA98XX_PRESET_LENGTH];
+ nxpTfaFilter_t filter[TFA98XX_MAX_EQ];// note: API index counts from 1..10
+} nxpTfaVolumeStep2_t;
+
+/*
+ * volumestep file
+ */
+#define NXPTFA_VP_VERSION '1'
+#define NXPTFA_VP_SUBVERSION "00"
+typedef struct nxpTfaVolumeStepFile {
+ nxpTfaHeader_t hdr;
+ uint8_t vsteps; // can also be calulated from size+type
+ uint8_t samplerate; // ==enum samplerates, assure 8 bits
+ uint8_t payload; //start of variable length contents:N times volsteps
+} nxpTfaVolumeStepFile_t;
+/*
+ * volumestep2 file
+ */
+typedef struct nxpTfaVolumeStep2File {
+ nxpTfaHeader_t hdr;
+ uint8_t vsteps; // can also be calulated from size+type
+ uint8_t samplerate; // ==enum samplerates, assure 8 bits
+ nxpTfaVolumeStep2_t vstep[]; //start of variable length contents:N times volsteps
+} nxpTfaVolumeStep2File_t;
+
+/*
+ * volumestepMax2 file
+ */
+typedef struct nxpTfaVolumeStepMax2File {
+ nxpTfaHeader_t hdr;
+ uint8_t version[3];
+ uint8_t NrOfVsteps;
+ uint8_t vstepsBin[];
+} nxpTfaVolumeStepMax2File_t;
+
+/*
+ * volumestepMax2 file
+ * This volumestep should ONLY be used for the use of bin2hdr!
+ * This can only be used to find the messagetype of the vstep (without header)
+ */
+typedef struct nxpTfaVolumeStepMax2_1File {
+ uint8_t version[3];
+ uint8_t NrOfVsteps;
+ uint8_t vstepsBin[];
+} nxpTfaVolumeStepMax2_1File_t;
+
+struct nxpTfaVolumeStepRegisterInfo {
+ uint8_t NrOfRegisters;
+ uint16_t registerInfo[];
+};
+
+struct nxpTfaVolumeStepMessageInfo {
+ uint8_t NrOfMessages;
+ uint8_t MessageType;
+ uint24_t MessageLength;
+ uint8_t CmdId[3];
+ uint8_t ParameterData[];
+};
+/**************************old v2 *************************************************/
+
+/*
+ * subv 00 volumestep file
+ */
+typedef struct nxpTfaOldHeader {
+ uint16_t id;
+ char version[2]; // "V_" : V=version, vv=subversion
+ char subversion[2]; // "vv" : vv=subversion
+ uint16_t size; // data size in bytes following CRC
+ uint32_t CRC; // 32-bits CRC for following data
+} nxpTfaOldHeader_t;
+
+typedef struct nxpOldTfaFilter {
+ double bq[5];
+ int32_t type;
+ double frequency;
+ double Q;
+ double gain;
+ uint8_t enabled;
+} nxpTfaOldFilter_t ;
+
+typedef struct nxpTfaOldVolumeStep2 {
+ float attenuation; // IEEE single float
+ uint8_t preset[TFA98XX_PRESET_LENGTH];
+ nxpTfaOldFilter_t eq[10];
+} nxpTfaOldVolumeStep2_t;
+
+typedef struct nxpTfaOldVolumeStepFile {
+ nxpTfaOldHeader_t hdr;
+ nxpTfaOldVolumeStep2_t step[];
+} nxpTfaOldVolumeStep2File_t;
+/**************************end old v2 *************************************************/
+
+/*
+ * speaker file header
+ */
+struct nxpTfaSpkHeader {
+ struct nxpTfaHeader hdr;
+ char name[8]; // speaker nick name (e.g. “dumbo”)
+ char vendor[16];
+ char type[8];
+ // dimensions (mm)
+ uint8_t height;
+ uint8_t width;
+ uint8_t depth;
+ uint16_t ohm;
+};
+
+/*
+ * speaker file
+ */
+#define NXPTFA_SP_VERSION '1'
+#define NXPTFA_SP_SUBVERSION "00"
+typedef struct nxpTfaSpeakerFile {
+ nxpTfaHeader_t hdr;
+ char name[8]; // speaker nick name (e.g. “dumbo”)
+ char vendor[16];
+ char type[8];
+ // dimensions (mm)
+ uint8_t height;
+ uint8_t width;
+ uint8_t depth;
+ uint8_t ohm_primary;
+ uint8_t ohm_secondary;
+ uint8_t data[]; //payload TFA98XX_SPEAKERPARAMETER_LENGTH
+} nxpTfaSpeakerFile_t;
+
+#define NXPTFA_VP3_VERSION '3'
+#define NXPTFA_VP3_SUBVERSION "00"
+
+struct nxpTfaFWVer {
+ uint8_t Major;
+ uint8_t minor;
+ uint8_t minor_update:6;
+ uint8_t Update:2;
+};
+
+struct nxpTfaFWMsg {
+ struct nxpTfaFWVer fwVersion;
+ struct nxpTfaMsg payload;
+};
+
+typedef struct nxpTfaLiveData {
+ char name[25];
+ char addrs[25];
+ int tracker;
+ int scalefactor;
+} nxpTfaLiveData_t;
+
+#define NXPTFA_SP3_VERSION '3'
+#define NXPTFA_SP3_SUBVERSION "00"
+struct nxpTfaSpeakerFileMax2 {
+ nxpTfaHeader_t hdr;
+ char name[8]; // speaker nick name (e.g. “dumbo”)
+ char vendor[16];
+ char type[8];
+ // dimensions (mm)
+ uint8_t height;
+ uint8_t width;
+ uint8_t depth;
+ uint8_t ohm_primary;
+ uint8_t ohm_secondary;
+ struct nxpTfaFWMsg FWmsg; //payload including FW ver and Cmd ID
+};
+
+/*
+ * parameter container file
+ */
+/*
+ * descriptors
+ * Note 1: append new DescriptorType at the end
+ * Note 2: add new descriptors to dsc_name[] in tfaContUtil.c
+ */
+typedef enum nxpTfaDescriptorType {
+ dscDevice, // device list
+ dscProfile, // profile list
+ dscRegister, // register patch
+ dscString, // ascii, zero terminated string
+ dscFile, // filename + file contents
+ dscPatch, // patch file
+ dscMarker, // marker to indicate end of a list
+ dscMode,
+ dscSetInputSelect,
+ dscSetOutputSelect,
+ dscSetProgramConfig,
+ dscSetLagW,
+ dscSetGains,
+ dscSetvBatFactors,
+ dscSetSensesCal,
+ dscSetSensesDelay,
+ dscBitfield,
+ dscDefault, // used to reset bitfields to there default values
+ dscLiveData,
+ dscLiveDataString,
+ dscGroup,
+ dscCmd,
+ dscSetMBDrc,
+ dscFilter,
+ dscNoInit,
+ dscFeatures,
+ dscCfMem, // coolflux memory x,y,io
+ dscSetFwkUseCase,
+ dscSetVddpConfig,
+ dsc_last // trailer
+} nxpTfaDescriptorType_t;
+
+#define TFA_BITFIELDDSCMSK 0x7fffffff
+typedef struct nxpTfaDescPtr {
+ uint32_t offset:24;
+ uint32_t type:8; // (== enum nxpTfaDescriptorType, assure 8bits length)
+} nxpTfaDescPtr_t;
+
+/*
+ * generic file descriptor
+ */
+typedef struct nxpTfaFileDsc {
+ nxpTfaDescPtr_t name;
+ uint32_t size; // file data length in bytes
+ uint8_t data[]; //payload
+} nxpTfaFileDsc_t;
+
+
+/*
+ * device descriptor list
+ */
+typedef struct nxpTfaDeviceList {
+ uint8_t length; // nr of items in the list
+ uint8_t bus; // bus
+ uint8_t dev; // device
+ uint8_t func; // subfunction or subdevice
+ uint32_t devid; // device hw fw id
+ nxpTfaDescPtr_t name; // device name
+ nxpTfaDescPtr_t list[]; // items list
+} nxpTfaDeviceList_t;
+
+/*
+ * profile descriptor list
+ */
+typedef struct nxpTfaProfileList {
+ uint32_t length:8; // nr of items in the list + name
+ uint32_t group:8; // profile group number
+ uint32_t ID:16; // profile ID
+ nxpTfaDescPtr_t name; // profile name
+ nxpTfaDescPtr_t list[]; // items list (lenght-1 items)
+} nxpTfaProfileList_t;
+#define TFA_PROFID 0x1234
+
+/*
+ * livedata descriptor list
+ */
+typedef struct nxpTfaLiveDataList {
+ uint32_t length:8; // nr of items in the list
+ uint32_t ID:24; // profile ID
+ nxpTfaDescPtr_t name; // livedata name
+ nxpTfaDescPtr_t list[]; // items list
+} nxpTfaLiveDataList_t;
+#define TFA_LIVEDATAID 0x5678
+
+/*
+ * Bitfield descriptor
+ */
+typedef struct nxpTfaBitfield {
+ uint16_t value;
+ uint16_t field; // ==datasheet defined, 16 bits
+} nxpTfaBitfield_t;
+
+/*
+ * Bitfield enumuration bits descriptor
+ */
+typedef struct nxpTfaBfEnum {
+ unsigned int len:4; // this is the actual length-1
+ unsigned int pos:4;
+ unsigned int address:8;
+} nxpTfaBfEnum_t;
+
+/*
+ * Register patch descriptor
+ */
+typedef struct nxpTfaRegpatch {
+ uint8_t address; // register address
+ uint16_t value; // value to write
+ uint16_t mask; // mask of bits to write
+} nxpTfaRegpatch_t;
+
+/*
+ * Mode descriptor
+ */
+typedef struct nxpTfaUseCase {
+ int value; // mode value, maps to enum Tfa98xx_Mode
+} nxpTfaMode_t;
+
+/*
+ * NoInit descriptor
+ */
+typedef struct nxpTfaNoInit {
+ uint8_t value; // noInit value
+} nxpTfaNoInit_t;
+
+/*
+ * Features descriptor
+ */
+typedef struct nxpTfaFeatures {
+ uint16_t value[3]; // features value
+} nxpTfaFeatures_t;
+
+
+/*
+ * the container file
+ * - the size field is 32bits long (generic=16)
+ * - all char types are in ASCII
+ */
+#define NXPTFA_PM_VERSION '1'
+#define NXPTFA_PM3_VERSION '3'
+#define NXPTFA_PM_SUBVERSION '1'
+typedef struct nxpTfaContainer {
+ char id[2]; // "XX" : XX=type
+ char version[2]; // "V_" : V=version, vv=subversion
+ char subversion[2]; // "vv" : vv=subversion
+ uint32_t size; // data size in bytes following CRC
+ uint32_t CRC; // 32-bits CRC for following data
+ uint16_t rev; // "extra chars for rev nr"
+ char customer[8]; // “name of customer”
+ char application[8]; // “application name”
+ char type[8]; // “application type name”
+ uint16_t ndev; // "nr of device lists"
+ uint16_t nprof; // "nr of profile lists"
+ uint16_t nliveData; // "nr of livedata lists"
+ nxpTfaDescPtr_t index[]; // start of item index table
+} nxpTfaContainer_t;
+
+#pragma pack (pop)
+
+#endif /* TFA98XXPARAMETERS_H_ */
diff --git a/inc/tfa98xx_tfafieldnames.h b/sound/soc/codecs/tfa98xx_tfafieldnames.h
similarity index 99%
rename from inc/tfa98xx_tfafieldnames.h
rename to sound/soc/codecs/tfa98xx_tfafieldnames.h
index 5e08a48..09f9833 100644
--- a/inc/tfa98xx_tfafieldnames.h
+++ b/sound/soc/codecs/tfa98xx_tfafieldnames.h
@@ -1,142 +1,142 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-typedef struct TfaBfName {
- unsigned short bfEnum;
- char *bfName;
-} tfaBfName_t;
-
-typedef struct TfaIrqName {
- unsigned short irqEnum;
- char *irqName;
-} tfaIrqName_t;
-
-#include "tfa1_tfafieldnames.h"
-#include "tfa2_tfafieldnames_N1C.h"
-/* diffs for specific devices */
-#include "tfa9887_tfafieldnames.h"
-#include "tfa9890_tfafieldnames.h"
-#include "tfa9891_tfafieldnames.h"
-#include "tfa9872_tfafieldnames.h"
-#include "tfa9912_tfafieldnames.h"
-#include "tfa9896_tfafieldnames.h"
-#include "tfa9874_tfafieldnames.h"
-#include "tfa9878_tfafieldnames.h"
-#include "tfa9894_tfafieldnames.h"
-#include "tfa9894_tfafieldnames_N2.h"
-
-/* missing 'common' defs break the build but unused in TFA1 context */
-#define TFA1_BF_AMPINSEL -1
-#define TFA1_BF_MANSCONF -1
-#define TFA1_BF_MANCOLD -1
-#define TFA1_BF_INTSMUTE -1
-#define TFA1_BF_CFSMR -1
-#define TFA1_BF_CFSML -1
-#define TFA1_BF_DCMCCAPI -1
-#define TFA1_BF_DCMCCSB -1
-#define TFA1_BF_USERDEF -1
-#define TFA1_BF_MANSTATE -1
-#define TFA1_BF_MANOPER -1
-#define TFA1_BF_REFCKSEL -1
-#define TFA1_BF_VOLSEC -1
-#define TFA1_BF_FRACTDEL -1
-#define TFA1_BF_ACKDMG -1
-#define TFA1_BF_SSRIGHTE -1
-#define TFA1_BF_SSLEFTE -1
-#define TFA1_BF_R25CL -1
-#define TFA1_BF_R25CR -1
-#define TFA1_BF_SWPROFIL 0x8045 /*!< profile save */
-#define TFA1_BF_SWVSTEP 0x80a5 /*!< vstep save */
-
-/* missing 'common' defs break the build */
-#define TFA2_BF_CFSM -1
-
-
-/* MTP access uses registers
- * defs are derived from corresponding bitfield names as used in the BF macros
- */
-#define MTPKEY2 MTPK /* unlock key2 MTPK */
-#define MTP0 MTPOTC /* MTP data */
-#define MTP_CONTROL CIMTP /* copy i2c to mtp */
-
-/* interrupt enable register uses HW name in TFA2 */
-#define TFA2_BF_INTENVDDS TFA2_BF_IEVDDS
-
-
-/* TFA9891 specific bit field names */
-#define TFA1_BF_SAAMGAIN 0x2202
-#define TFA2_BF_SAAMGAIN -1
-
-/* TFA9872 specific bit field names */
-#define TFA2_BF_IELP0 TFA9872_BF_IELP0
-#define TFA2_BF_ISTLP0 TFA9872_BF_ISTLP0
-#define TFA2_BF_IPOLP0 TFA9872_BF_IPOLP0
-#define TFA2_BF_IELP1 TFA9872_BF_IELP1
-#define TFA2_BF_ISTLP1 TFA9872_BF_ISTLP1
-#define TFA2_BF_IPOLP1 TFA9872_BF_IPOLP1
-#define TFA2_BF_LP0 TFA9872_BF_LP0
-#define TFA2_BF_LP1 TFA9872_BF_LP1
-#define TFA2_BF_R25C TFA9872_BF_R25C
-#define TFA2_BF_SAMMODE TFA9872_BF_SAMMODE
-
-/* interrupt bit field names of TFA2 and TFA1 do not match */
-#define TFA1_BF_IEACS TFA1_BF_INTENACS
-#define TFA1_BF_IPOACS TFA1_BF_INTPOLACS
-#define TFA1_BF_ISTACS TFA1_BF_INTOACS
-#define TFA1_BF_ISTVDDS TFA1_BF_INTOVDDS
-#define TFA1_BF_ICLVDDS TFA1_BF_INTIVDDS
-#define TFA1_BF_IPOVDDS TFA1_BF_INTPOLVDDS
-#define TFA1_BF_IENOCLK TFA1_BF_INTENNOCLK
-#define TFA1_BF_ISTNOCLK TFA1_BF_INTONOCLK
-#define TFA1_BF_IPONOCLK TFA1_BF_INTPOLNOCLK
-
-/* interrupt bit fields not available on TFA1 */
-#define TFA1_BF_IECLKOOR -1
-#define TFA1_BF_ISTCLKOOR -1
-#define TFA1_BF_IEMWSRC -1
-#define TFA1_BF_ISTMWSRC -1
-#define TFA1_BF_IPOMWSRC -1
-#define TFA1_BF_IEMWSMU -1
-#define TFA1_BF_ISTMWSMU -1
-#define TFA1_BF_IPOMWSMU -1
-#define TFA1_BF_IEMWCFC -1
-#define TFA1_BF_ISTMWCFC -1
-#define TFA1_BF_IPOMWCFC -1
-#define TFA1_BF_CLKOOR -1
-#define TFA1_BF_MANWAIT1 -1
-#define TFA1_BF_MANWAIT2 -1
-#define TFA1_BF_MANMUTE -1
-#define TFA1_BF_IPCLKOOR -1
-#define TFA1_BF_ICLCLKOOR -1
-#define TFA1_BF_IPOSWS -1
-#define TFA1_BF_IESWS -1
-#define TFA1_BF_ISTSWS -1
-#define TFA1_BF_IESPKS -1
-#define TFA1_BF_ISTSPKS -1
-#define TFA1_BF_IPOSPKS -1
-#define TFA1_BF_IECLKS -1
-#define TFA1_BF_ISTCLKS -1
-#define TFA1_BF_IPOCLKS -1
-#define TFA1_BF_IEAMPS -1
-#define TFA1_BF_ISTAMPS -1
-#define TFA1_BF_IPOAMPS -1
-#define TFA1_BF_IELP0 -1
-#define TFA1_BF_ISTLP0 -1
-#define TFA1_BF_IPOLP0 -1
-#define TFA1_BF_IELP1 -1
-#define TFA1_BF_ISTLP1 -1
-#define TFA1_BF_IPOLP1 -1
-#define TFA1_BF_LP0 -1
-#define TFA1_BF_LP1 -1
-#define TFA1_BF_R25C -1
-#define TFA1_BF_SAMMODE -1
-
-/* TDM STATUS fields not available on TFA1 */
-#define TFA1_BF_TDMLUTER -1
-#define TFA1_BF_TDMERR -1
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+typedef struct TfaBfName {
+ unsigned short bfEnum;
+ char *bfName;
+} tfaBfName_t;
+
+typedef struct TfaIrqName {
+ unsigned short irqEnum;
+ char *irqName;
+} tfaIrqName_t;
+
+#include "tfa1_tfafieldnames.h"
+#include "tfa2_tfafieldnames_N1C.h"
+/* diffs for specific devices */
+#include "tfa9887_tfafieldnames.h"
+#include "tfa9890_tfafieldnames.h"
+#include "tfa9891_tfafieldnames.h"
+#include "tfa9872_tfafieldnames.h"
+#include "tfa9912_tfafieldnames.h"
+#include "tfa9896_tfafieldnames.h"
+#include "tfa9874_tfafieldnames.h"
+#include "tfa9878_tfafieldnames.h"
+#include "tfa9894_tfafieldnames.h"
+#include "tfa9894_tfafieldnames_N2.h"
+
+/* missing 'common' defs break the build but unused in TFA1 context */
+#define TFA1_BF_AMPINSEL -1
+#define TFA1_BF_MANSCONF -1
+#define TFA1_BF_MANCOLD -1
+#define TFA1_BF_INTSMUTE -1
+#define TFA1_BF_CFSMR -1
+#define TFA1_BF_CFSML -1
+#define TFA1_BF_DCMCCAPI -1
+#define TFA1_BF_DCMCCSB -1
+#define TFA1_BF_USERDEF -1
+#define TFA1_BF_MANSTATE -1
+#define TFA1_BF_MANOPER -1
+#define TFA1_BF_REFCKSEL -1
+#define TFA1_BF_VOLSEC -1
+#define TFA1_BF_FRACTDEL -1
+#define TFA1_BF_ACKDMG -1
+#define TFA1_BF_SSRIGHTE -1
+#define TFA1_BF_SSLEFTE -1
+#define TFA1_BF_R25CL -1
+#define TFA1_BF_R25CR -1
+#define TFA1_BF_SWPROFIL 0x8045 /*!< profile save */
+#define TFA1_BF_SWVSTEP 0x80a5 /*!< vstep save */
+
+/* missing 'common' defs break the build */
+#define TFA2_BF_CFSM -1
+
+
+/* MTP access uses registers
+ * defs are derived from corresponding bitfield names as used in the BF macros
+ */
+#define MTPKEY2 MTPK /* unlock key2 MTPK */
+#define MTP0 MTPOTC /* MTP data */
+#define MTP_CONTROL CIMTP /* copy i2c to mtp */
+
+/* interrupt enable register uses HW name in TFA2 */
+#define TFA2_BF_INTENVDDS TFA2_BF_IEVDDS
+
+
+/* TFA9891 specific bit field names */
+#define TFA1_BF_SAAMGAIN 0x2202
+#define TFA2_BF_SAAMGAIN -1
+
+/* TFA9872 specific bit field names */
+#define TFA2_BF_IELP0 TFA9872_BF_IELP0
+#define TFA2_BF_ISTLP0 TFA9872_BF_ISTLP0
+#define TFA2_BF_IPOLP0 TFA9872_BF_IPOLP0
+#define TFA2_BF_IELP1 TFA9872_BF_IELP1
+#define TFA2_BF_ISTLP1 TFA9872_BF_ISTLP1
+#define TFA2_BF_IPOLP1 TFA9872_BF_IPOLP1
+#define TFA2_BF_LP0 TFA9872_BF_LP0
+#define TFA2_BF_LP1 TFA9872_BF_LP1
+#define TFA2_BF_R25C TFA9872_BF_R25C
+#define TFA2_BF_SAMMODE TFA9872_BF_SAMMODE
+
+/* interrupt bit field names of TFA2 and TFA1 do not match */
+#define TFA1_BF_IEACS TFA1_BF_INTENACS
+#define TFA1_BF_IPOACS TFA1_BF_INTPOLACS
+#define TFA1_BF_ISTACS TFA1_BF_INTOACS
+#define TFA1_BF_ISTVDDS TFA1_BF_INTOVDDS
+#define TFA1_BF_ICLVDDS TFA1_BF_INTIVDDS
+#define TFA1_BF_IPOVDDS TFA1_BF_INTPOLVDDS
+#define TFA1_BF_IENOCLK TFA1_BF_INTENNOCLK
+#define TFA1_BF_ISTNOCLK TFA1_BF_INTONOCLK
+#define TFA1_BF_IPONOCLK TFA1_BF_INTPOLNOCLK
+
+/* interrupt bit fields not available on TFA1 */
+#define TFA1_BF_IECLKOOR -1
+#define TFA1_BF_ISTCLKOOR -1
+#define TFA1_BF_IEMWSRC -1
+#define TFA1_BF_ISTMWSRC -1
+#define TFA1_BF_IPOMWSRC -1
+#define TFA1_BF_IEMWSMU -1
+#define TFA1_BF_ISTMWSMU -1
+#define TFA1_BF_IPOMWSMU -1
+#define TFA1_BF_IEMWCFC -1
+#define TFA1_BF_ISTMWCFC -1
+#define TFA1_BF_IPOMWCFC -1
+#define TFA1_BF_CLKOOR -1
+#define TFA1_BF_MANWAIT1 -1
+#define TFA1_BF_MANWAIT2 -1
+#define TFA1_BF_MANMUTE -1
+#define TFA1_BF_IPCLKOOR -1
+#define TFA1_BF_ICLCLKOOR -1
+#define TFA1_BF_IPOSWS -1
+#define TFA1_BF_IESWS -1
+#define TFA1_BF_ISTSWS -1
+#define TFA1_BF_IESPKS -1
+#define TFA1_BF_ISTSPKS -1
+#define TFA1_BF_IPOSPKS -1
+#define TFA1_BF_IECLKS -1
+#define TFA1_BF_ISTCLKS -1
+#define TFA1_BF_IPOCLKS -1
+#define TFA1_BF_IEAMPS -1
+#define TFA1_BF_ISTAMPS -1
+#define TFA1_BF_IPOAMPS -1
+#define TFA1_BF_IELP0 -1
+#define TFA1_BF_ISTLP0 -1
+#define TFA1_BF_IPOLP0 -1
+#define TFA1_BF_IELP1 -1
+#define TFA1_BF_ISTLP1 -1
+#define TFA1_BF_IPOLP1 -1
+#define TFA1_BF_LP0 -1
+#define TFA1_BF_LP1 -1
+#define TFA1_BF_R25C -1
+#define TFA1_BF_SAMMODE -1
+
+/* TDM STATUS fields not available on TFA1 */
+#define TFA1_BF_TDMLUTER -1
+#define TFA1_BF_TDMERR -1
diff --git a/inc/tfa9912_tfafieldnames.h b/sound/soc/codecs/tfa9912_tfafieldnames.h
similarity index 78%
rename from inc/tfa9912_tfafieldnames.h
rename to sound/soc/codecs/tfa9912_tfafieldnames.h
index 36741f6..34043ec 100644
--- a/inc/tfa9912_tfafieldnames.h
+++ b/sound/soc/codecs/tfa9912_tfafieldnames.h
@@ -1,1769 +1,1769 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _TFA9912_TFAFIELDNAMES_H
-#define _TFA9912_TFAFIELDNAMES_H
-
-
-#define TFA9912_I2CVERSION 1.43
-
-typedef enum nxpTfa9912BfEnumList {
- TFA9912_BF_PWDN = 0x0000, /*!< Powerdown selection */
- TFA9912_BF_I2CR = 0x0010, /*!< I2C Reset - Auto clear */
- TFA9912_BF_CFE = 0x0020, /*!< Enable CoolFlux */
- TFA9912_BF_AMPE = 0x0030, /*!< Enables the Amplifier */
- TFA9912_BF_DCA = 0x0040, /*!< Activate DC-to-DC converter */
- TFA9912_BF_SBSL = 0x0050, /*!< Coolflux configured */
- TFA9912_BF_AMPC = 0x0060, /*!< CoolFlux controls amplifier */
- TFA9912_BF_INTP = 0x0071, /*!< Interrupt config */
- TFA9912_BF_FSSSEL= 0x0090, /*!< Audio sample reference */
- TFA9912_BF_BYPOCP= 0x00b0, /*!< Bypass OCP */
- TFA9912_BF_TSTOCP= 0x00c0, /*!< OCP testing control */
- TFA9912_BF_AMPINSEL= 0x0101, /*!< Amplifier input selection */
- TFA9912_BF_MANSCONF= 0x0120, /*!< I2C configured */
- TFA9912_BF_MANCOLD= 0x0130, /*!< Execute cold start */
- TFA9912_BF_MANAOOSC= 0x0140, /*!< Internal osc off at PWDN */
- TFA9912_BF_MANROBOD= 0x0150, /*!< Reaction on BOD */
- TFA9912_BF_BODE = 0x0160, /*!< BOD Enable */
- TFA9912_BF_BODHYS= 0x0170, /*!< BOD Hysteresis */
- TFA9912_BF_BODFILT= 0x0181, /*!< BOD filter */
- TFA9912_BF_BODTHLVL= 0x01a1, /*!< BOD threshold */
- TFA9912_BF_MUTETO= 0x01d0, /*!< Time out SB mute sequence */
- TFA9912_BF_RCVNS = 0x01e0, /*!< Noise shaper selection */
- TFA9912_BF_MANWDE= 0x01f0, /*!< Watchdog enable */
- TFA9912_BF_AUDFS = 0x0203, /*!< Sample rate (fs) */
- TFA9912_BF_INPLEV= 0x0240, /*!< TDM output attenuation */
- TFA9912_BF_FRACTDEL= 0x0255, /*!< V/I Fractional delay */
- TFA9912_BF_BYPHVBF= 0x02b0, /*!< Bypass HVBAT filter */
- TFA9912_BF_TDMC = 0x02c0, /*!< TDM Compatibility with TFA9872 */
- TFA9912_BF_ENBLADC10= 0x02e0, /*!< ADC10 Enable - I2C direct mode */
- TFA9912_BF_REV = 0x030f, /*!< Revision info */
- TFA9912_BF_REFCKEXT= 0x0401, /*!< PLL external ref clock */
- TFA9912_BF_REFCKSEL= 0x0420, /*!< PLL internal ref clock */
- TFA9912_BF_ENCFCKSEL= 0x0430, /*!< Coolflux DSP clock scaling, low power mode */
- TFA9912_BF_CFCKSEL= 0x0441, /*!< Coolflux DSP clock scaler selection for low power mode */
- TFA9912_BF_TDMINFSEL= 0x0460, /*!< TDM clock selection */
- TFA9912_BF_DISBLAUTOCLKSEL= 0x0470, /*!< Disable Automatic dsp clock source selection */
- TFA9912_BF_SELCLKSRC= 0x0480, /*!< I2C selection of DSP clock when auto select is disabled */
- TFA9912_BF_SELTIMSRC= 0x0490, /*!< I2C selection of Watchdog and Timer clock */
- TFA9912_BF_SSLEFTE= 0x0500, /*!< */
- TFA9912_BF_SPKSSEN= 0x0510, /*!< Enable speaker path */
- TFA9912_BF_VSLEFTE= 0x0520, /*!< */
- TFA9912_BF_VSRIGHTE= 0x0530, /*!< Voltage sense */
- TFA9912_BF_CSLEFTE= 0x0540, /*!< */
- TFA9912_BF_CSRIGHTE= 0x0550, /*!< Current sense */
- TFA9912_BF_SSPDME= 0x0560, /*!< Sub-system PDM */
- TFA9912_BF_PGALE = 0x0570, /*!< Enable PGA chop clock for left channel */
- TFA9912_BF_PGARE = 0x0580, /*!< Enable PGA chop clock */
- TFA9912_BF_SSTDME= 0x0590, /*!< Sub-system TDM */
- TFA9912_BF_SSPBSTE= 0x05a0, /*!< Sub-system boost */
- TFA9912_BF_SSADCE= 0x05b0, /*!< Sub-system ADC */
- TFA9912_BF_SSFAIME= 0x05c0, /*!< Sub-system FAIM */
- TFA9912_BF_SSCFTIME= 0x05d0, /*!< CF Sub-system timer */
- TFA9912_BF_SSCFWDTE= 0x05e0, /*!< CF Sub-system WDT */
- TFA9912_BF_FAIMVBGOVRRL= 0x05f0, /*!< Over rule of vbg for FaIM access */
- TFA9912_BF_SAMSPKSEL= 0x0600, /*!< Input selection for TAP/SAM */
- TFA9912_BF_PDM2IISEN= 0x0610, /*!< PDM2IIS Bridge enable */
- TFA9912_BF_TAPRSTBYPASS= 0x0620, /*!< Tap decimator reset bypass - Bypass the decimator reset from tapdec */
- TFA9912_BF_CARDECISEL0= 0x0631, /*!< Cardec input 0 sel */
- TFA9912_BF_CARDECISEL1= 0x0651, /*!< Cardec input sel */
- TFA9912_BF_TAPDECSEL= 0x0670, /*!< Select TAP/Cardec for TAP */
- TFA9912_BF_COMPCOUNT= 0x0680, /*!< Comparator o/p filter selection */
- TFA9912_BF_STARTUPMODE= 0x0691, /*!< Startup Mode Selection */
- TFA9912_BF_AUTOTAP= 0x06b0, /*!< Enable auto tap switching */
- TFA9912_BF_COMPINITIME= 0x06c1, /*!< Comparator initialization time to be used in Tap Machine */
- TFA9912_BF_ANAPINITIME= 0x06e1, /*!< Analog initialization time to be used in Tap Machine */
- TFA9912_BF_CCHKTH= 0x0707, /*!< Clock check Higher Threshold */
- TFA9912_BF_CCHKTL= 0x0787, /*!< Clock check Higher Threshold */
- TFA9912_BF_AMPOCRT= 0x0802, /*!< Amplifier on-off criteria for shutdown */
- TFA9912_BF_AMPTCRR= 0x0832, /*!< Amplifier on-off criteria for tap mode entry */
- TFA9912_BF_STGS = 0x0d00, /*!< PDM side tone gain selector */
- TFA9912_BF_STGAIN= 0x0d18, /*!< Side tone gain */
- TFA9912_BF_STSMUTE= 0x0da0, /*!< Side tone soft mute */
- TFA9912_BF_ST1C = 0x0db0, /*!< side tone one s complement */
- TFA9912_BF_CMFBEL= 0x0e80, /*!< CMFB enable left */
- TFA9912_BF_VDDS = 0x1000, /*!< POR */
- TFA9912_BF_PLLS = 0x1010, /*!< PLL lock */
- TFA9912_BF_OTDS = 0x1020, /*!< OTP alarm */
- TFA9912_BF_OVDS = 0x1030, /*!< OVP alarm */
- TFA9912_BF_UVDS = 0x1040, /*!< UVP alarm */
- TFA9912_BF_CLKS = 0x1050, /*!< Clocks stable */
- TFA9912_BF_MTPB = 0x1060, /*!< MTP busy */
- TFA9912_BF_NOCLK = 0x1070, /*!< Lost clock */
- TFA9912_BF_ACS = 0x1090, /*!< Cold Start */
- TFA9912_BF_SWS = 0x10a0, /*!< Amplifier engage */
- TFA9912_BF_WDS = 0x10b0, /*!< Watchdog */
- TFA9912_BF_AMPS = 0x10c0, /*!< Amplifier enable */
- TFA9912_BF_AREFS = 0x10d0, /*!< References enable */
- TFA9912_BF_ADCCR = 0x10e0, /*!< Control ADC */
- TFA9912_BF_BODNOK= 0x10f0, /*!< BOD */
- TFA9912_BF_DCIL = 0x1100, /*!< DCDC current limiting */
- TFA9912_BF_DCDCA = 0x1110, /*!< DCDC active */
- TFA9912_BF_DCOCPOK= 0x1120, /*!< DCDC OCP nmos */
- TFA9912_BF_DCPEAKCUR= 0x1130, /*!< Indicates current is max in DC-to-DC converter */
- TFA9912_BF_DCHVBAT= 0x1140, /*!< DCDC level 1x */
- TFA9912_BF_DCH114= 0x1150, /*!< DCDC level 1.14x */
- TFA9912_BF_DCH107= 0x1160, /*!< DCDC level 1.07x */
- TFA9912_BF_STMUTEB= 0x1170, /*!< side tone (un)mute busy */
- TFA9912_BF_STMUTE= 0x1180, /*!< side tone mute state */
- TFA9912_BF_TDMLUTER= 0x1190, /*!< TDM LUT error */
- TFA9912_BF_TDMSTAT= 0x11a2, /*!< TDM status bits */
- TFA9912_BF_TDMERR= 0x11d0, /*!< TDM error */
- TFA9912_BF_HAPTIC= 0x11e0, /*!< Status haptic driver */
- TFA9912_BF_OCPOAP= 0x1300, /*!< OCPOK pmos A */
- TFA9912_BF_OCPOAN= 0x1310, /*!< OCPOK nmos A */
- TFA9912_BF_OCPOBP= 0x1320, /*!< OCPOK pmos B */
- TFA9912_BF_OCPOBN= 0x1330, /*!< OCPOK nmos B */
- TFA9912_BF_CLIPAH= 0x1340, /*!< Clipping A to Vddp */
- TFA9912_BF_CLIPAL= 0x1350, /*!< Clipping A to gnd */
- TFA9912_BF_CLIPBH= 0x1360, /*!< Clipping B to Vddp */
- TFA9912_BF_CLIPBL= 0x1370, /*!< Clipping B to gnd */
- TFA9912_BF_OCDS = 0x1380, /*!< OCP amplifier */
- TFA9912_BF_CLIPS = 0x1390, /*!< Amplifier clipping */
- TFA9912_BF_TCMPTRG= 0x13a0, /*!< Status Tap comparator triggered */
- TFA9912_BF_TAPDET= 0x13b0, /*!< Status Tap detected */
- TFA9912_BF_MANWAIT1= 0x13c0, /*!< Wait HW I2C settings */
- TFA9912_BF_MANWAIT2= 0x13d0, /*!< Wait CF config */
- TFA9912_BF_MANMUTE= 0x13e0, /*!< Audio mute sequence */
- TFA9912_BF_MANOPER= 0x13f0, /*!< Operating state */
- TFA9912_BF_SPKSL = 0x1400, /*!< Left speaker status */
- TFA9912_BF_SPKS = 0x1410, /*!< Speaker status */
- TFA9912_BF_CLKOOR= 0x1420, /*!< External clock status */
- TFA9912_BF_MANSTATE= 0x1433, /*!< Device manager status */
- TFA9912_BF_DCMODE= 0x1471, /*!< DCDC mode status bits */
- TFA9912_BF_DSPCLKSRC= 0x1490, /*!< DSP clock source selected by manager */
- TFA9912_BF_STARTUPMODSTAT= 0x14a1, /*!< Startup Mode Selected by Manager(Read Only) */
- TFA9912_BF_TSPMSTATE= 0x14c3, /*!< Tap Machine State */
- TFA9912_BF_BATS = 0x1509, /*!< Battery voltage (V) */
- TFA9912_BF_TEMPS = 0x1608, /*!< IC Temperature (C) */
- TFA9912_BF_VDDPS = 0x1709, /*!< IC VDDP voltage ( 1023*VDDP/13 V) */
- TFA9912_BF_DCILCF= 0x17a0, /*!< DCDC current limiting for DSP */
- TFA9912_BF_TDMUC = 0x2000, /*!< Mode setting */
- TFA9912_BF_DIO4SEL= 0x2011, /*!< DIO4 Input selection */
- TFA9912_BF_TDME = 0x2040, /*!< Enable TDM interface */
- TFA9912_BF_TDMMODE= 0x2050, /*!< Slave/master */
- TFA9912_BF_TDMCLINV= 0x2060, /*!< Reception data to BCK clock */
- TFA9912_BF_TDMFSLN= 0x2073, /*!< FS length */
- TFA9912_BF_TDMFSPOL= 0x20b0, /*!< FS polarity */
- TFA9912_BF_TDMNBCK= 0x20c3, /*!< N-BCK's in FS */
- TFA9912_BF_TDMSLOTS= 0x2103, /*!< N-slots in Frame */
- TFA9912_BF_TDMSLLN= 0x2144, /*!< N-bits in slot */
- TFA9912_BF_TDMBRMG= 0x2194, /*!< N-bits remaining */
- TFA9912_BF_TDMDEL= 0x21e0, /*!< data delay to FS */
- TFA9912_BF_TDMADJ= 0x21f0, /*!< data adjustment */
- TFA9912_BF_TDMOOMP= 0x2201, /*!< Received audio compression */
- TFA9912_BF_TDMSSIZE= 0x2224, /*!< Sample size per slot */
- TFA9912_BF_TDMTXDFO= 0x2271, /*!< Format unused bits in a slot */
- TFA9912_BF_TDMTXUS0= 0x2291, /*!< Format unused slots GAINIO */
- TFA9912_BF_TDMTXUS1= 0x22b1, /*!< Format unused slots DIO1 */
- TFA9912_BF_TDMTXUS2= 0x22d1, /*!< Format unused slots DIO2 */
- TFA9912_BF_TDMGIE= 0x2300, /*!< Control gain (channel in 0) */
- TFA9912_BF_TDMDCE= 0x2310, /*!< Control audio left (channel in 1 ) */
- TFA9912_BF_TDMSPKE= 0x2320, /*!< Control audio right (channel in 2 ) */
- TFA9912_BF_TDMCSE= 0x2330, /*!< Current sense */
- TFA9912_BF_TDMVSE= 0x2340, /*!< Voltage sense */
- TFA9912_BF_TDMGOE= 0x2350, /*!< DSP Gainout */
- TFA9912_BF_TDMCF2E= 0x2360, /*!< DSP 2 */
- TFA9912_BF_TDMCF3E= 0x2370, /*!< DSP 3 */
- TFA9912_BF_TDMCFE= 0x2380, /*!< DSP */
- TFA9912_BF_TDMES6= 0x2390, /*!< Loopback of Audio left (channel 1) */
- TFA9912_BF_TDMES7= 0x23a0, /*!< Loopback of Audio right (channel 2) */
- TFA9912_BF_TDMCF4E= 0x23b0, /*!< AEC ref right control */
- TFA9912_BF_TDMPD1E= 0x23c0, /*!< PDM 1 control */
- TFA9912_BF_TDMPD2E= 0x23d0, /*!< PDM 2 control */
- TFA9912_BF_TDMGIN= 0x2401, /*!< IO gainin */
- TFA9912_BF_TDMLIO= 0x2421, /*!< IO audio left */
- TFA9912_BF_TDMRIO= 0x2441, /*!< IO audio right */
- TFA9912_BF_TDMCSIO= 0x2461, /*!< IO Current Sense */
- TFA9912_BF_TDMVSIO= 0x2481, /*!< IO voltage sense */
- TFA9912_BF_TDMGOIO= 0x24a1, /*!< IO gain out */
- TFA9912_BF_TDMCFIO2= 0x24c1, /*!< IO DSP 2 */
- TFA9912_BF_TDMCFIO3= 0x24e1, /*!< IO DSP 3 */
- TFA9912_BF_TDMCFIO= 0x2501, /*!< IO DSP */
- TFA9912_BF_TDMLPB6= 0x2521, /*!< IO Source 6 */
- TFA9912_BF_TDMLPB7= 0x2541, /*!< IO Source 7 */
- TFA9912_BF_TDMGS = 0x2603, /*!< Control gainin */
- TFA9912_BF_TDMDCS= 0x2643, /*!< tdm slot for audio left (channel 1) */
- TFA9912_BF_TDMSPKS= 0x2683, /*!< tdm slot for audio right (channel 2) */
- TFA9912_BF_TDMCSS= 0x26c3, /*!< Slot Position of Current Sense Out */
- TFA9912_BF_TDMVSS= 0x2703, /*!< Slot Position of Voltage sense */
- TFA9912_BF_TDMCGOS= 0x2743, /*!< Slot Position of GAIN out */
- TFA9912_BF_TDMCF2S= 0x2783, /*!< Slot Position DSPout2 */
- TFA9912_BF_TDMCF3S= 0x27c3, /*!< Slot Position DSPout3 */
- TFA9912_BF_TDMCFS= 0x2803, /*!< Slot Position of DSPout */
- TFA9912_BF_TDMEDAT6S= 0x2843, /*!< Slot Position of loopback channel left */
- TFA9912_BF_TDMEDAT7S= 0x2883, /*!< Slot Position of loopback channel right */
- TFA9912_BF_TDMTXUS3= 0x2901, /*!< Format unused slots D3 */
- TFA9912_BF_PDMSM = 0x3100, /*!< PDM control */
- TFA9912_BF_PDMSTSEL= 0x3110, /*!< PDM Decimator input selection */
- TFA9912_BF_PDMSTENBL= 0x3120, /*!< Side tone input enable */
- TFA9912_BF_PDMLSEL= 0x3130, /*!< PDM data selection for left channel during PDM direct mode */
- TFA9912_BF_PDMRSEL= 0x3140, /*!< PDM data selection for right channel during PDM direct mode */
- TFA9912_BF_MICVDDE= 0x3150, /*!< Enable MICVDD */
- TFA9912_BF_PDMCLRAT= 0x3201, /*!< PDM BCK/Fs ratio */
- TFA9912_BF_PDMGAIN= 0x3223, /*!< PDM gain */
- TFA9912_BF_PDMOSEL= 0x3263, /*!< PDM output selection - RE/FE data combination */
- TFA9912_BF_SELCFHAPD= 0x32a0, /*!< Select the source for haptic data output (not for customer) */
- TFA9912_BF_ISTVDDS= 0x4000, /*!< Status POR */
- TFA9912_BF_ISTPLLS= 0x4010, /*!< Status PLL lock */
- TFA9912_BF_ISTOTDS= 0x4020, /*!< Status OTP alarm */
- TFA9912_BF_ISTOVDS= 0x4030, /*!< Status OVP alarm */
- TFA9912_BF_ISTUVDS= 0x4040, /*!< Status UVP alarm */
- TFA9912_BF_ISTCLKS= 0x4050, /*!< Status clocks stable */
- TFA9912_BF_ISTMTPB= 0x4060, /*!< Status MTP busy */
- TFA9912_BF_ISTNOCLK= 0x4070, /*!< Status lost clock */
- TFA9912_BF_ISTSPKS= 0x4080, /*!< Status speaker error */
- TFA9912_BF_ISTACS= 0x4090, /*!< Status cold start */
- TFA9912_BF_ISTSWS= 0x40a0, /*!< Status amplifier engage */
- TFA9912_BF_ISTWDS= 0x40b0, /*!< Status watchdog */
- TFA9912_BF_ISTAMPS= 0x40c0, /*!< Status amplifier enable */
- TFA9912_BF_ISTAREFS= 0x40d0, /*!< Status Ref enable */
- TFA9912_BF_ISTADCCR= 0x40e0, /*!< Status Control ADC */
- TFA9912_BF_ISTBODNOK= 0x40f0, /*!< Status BOD */
- TFA9912_BF_ISTBSTCU= 0x4100, /*!< Status DCDC current limiting */
- TFA9912_BF_ISTBSTHI= 0x4110, /*!< Status DCDC active */
- TFA9912_BF_ISTBSTOC= 0x4120, /*!< Status DCDC OCP */
- TFA9912_BF_ISTBSTPKCUR= 0x4130, /*!< Status bst peakcur */
- TFA9912_BF_ISTBSTVC= 0x4140, /*!< Status DCDC level 1x */
- TFA9912_BF_ISTBST86= 0x4150, /*!< Status DCDC level 1.14x */
- TFA9912_BF_ISTBST93= 0x4160, /*!< Status DCDC level 1.07x */
- TFA9912_BF_ISTRCVLD= 0x4170, /*!< Status rcvldop ready */
- TFA9912_BF_ISTOCPL= 0x4180, /*!< Status ocp alarm left */
- TFA9912_BF_ISTOCPR= 0x4190, /*!< Status ocp alarm */
- TFA9912_BF_ISTMWSRC= 0x41a0, /*!< Status Waits HW I2C settings */
- TFA9912_BF_ISTMWCFC= 0x41b0, /*!< Status waits CF config */
- TFA9912_BF_ISTMWSMU= 0x41c0, /*!< Status Audio mute sequence */
- TFA9912_BF_ISTCFMER= 0x41d0, /*!< Status cfma error */
- TFA9912_BF_ISTCFMAC= 0x41e0, /*!< Status cfma ack */
- TFA9912_BF_ISTCLKOOR= 0x41f0, /*!< Status flag_clk_out_of_range */
- TFA9912_BF_ISTTDMER= 0x4200, /*!< Status tdm error */
- TFA9912_BF_ISTCLPL= 0x4210, /*!< Status clip left */
- TFA9912_BF_ISTCLPR= 0x4220, /*!< Status clip */
- TFA9912_BF_ISTOCPM= 0x4230, /*!< Status mic ocpok */
- TFA9912_BF_ISTLP1= 0x4250, /*!< Status low power mode1 */
- TFA9912_BF_ISTLA = 0x4260, /*!< Status low amplitude detection */
- TFA9912_BF_ISTVDDP= 0x4270, /*!< Status VDDP greater than VBAT */
- TFA9912_BF_ISTTAPDET= 0x4280, /*!< Status Tap detected */
- TFA9912_BF_ISTAUDMOD= 0x4290, /*!< Status Audio Mode activated */
- TFA9912_BF_ISTSAMMOD= 0x42a0, /*!< Status SAM Mode activated */
- TFA9912_BF_ISTTAPMOD= 0x42b0, /*!< Status Tap Mode Activated */
- TFA9912_BF_ISTTAPTRG= 0x42c0, /*!< Status Tap comparator triggered */
- TFA9912_BF_ICLVDDS= 0x4400, /*!< Clear POR */
- TFA9912_BF_ICLPLLS= 0x4410, /*!< Clear PLL lock */
- TFA9912_BF_ICLOTDS= 0x4420, /*!< Clear OTP alarm */
- TFA9912_BF_ICLOVDS= 0x4430, /*!< Clear OVP alarm */
- TFA9912_BF_ICLUVDS= 0x4440, /*!< Clear UVP alarm */
- TFA9912_BF_ICLCLKS= 0x4450, /*!< Clear clocks stable */
- TFA9912_BF_ICLMTPB= 0x4460, /*!< Clear mtp busy */
- TFA9912_BF_ICLNOCLK= 0x4470, /*!< Clear lost clk */
- TFA9912_BF_ICLSPKS= 0x4480, /*!< Clear speaker error */
- TFA9912_BF_ICLACS= 0x4490, /*!< Clear cold started */
- TFA9912_BF_ICLSWS= 0x44a0, /*!< Clear amplifier engage */
- TFA9912_BF_ICLWDS= 0x44b0, /*!< Clear watchdog */
- TFA9912_BF_ICLAMPS= 0x44c0, /*!< Clear enbl amp */
- TFA9912_BF_ICLAREFS= 0x44d0, /*!< Clear ref enable */
- TFA9912_BF_ICLADCCR= 0x44e0, /*!< Clear control ADC */
- TFA9912_BF_ICLBODNOK= 0x44f0, /*!< Clear BOD */
- TFA9912_BF_ICLBSTCU= 0x4500, /*!< Clear DCDC current limiting */
- TFA9912_BF_ICLBSTHI= 0x4510, /*!< Clear DCDC active */
- TFA9912_BF_ICLBSTOC= 0x4520, /*!< Clear DCDC OCP */
- TFA9912_BF_ICLBSTPC= 0x4530, /*!< Clear bst peakcur */
- TFA9912_BF_ICLBSTVC= 0x4540, /*!< Clear DCDC level 1x */
- TFA9912_BF_ICLBST86= 0x4550, /*!< Clear DCDC level 1.14x */
- TFA9912_BF_ICLBST93= 0x4560, /*!< Clear DCDC level 1.07x */
- TFA9912_BF_ICLRCVLD= 0x4570, /*!< Clear rcvldop ready */
- TFA9912_BF_ICLOCPL= 0x4580, /*!< Clear ocp alarm left */
- TFA9912_BF_ICLOCPR= 0x4590, /*!< Clear ocp alarm */
- TFA9912_BF_ICLMWSRC= 0x45a0, /*!< Clear wait HW I2C settings */
- TFA9912_BF_ICLMWCFC= 0x45b0, /*!< Clear wait cf config */
- TFA9912_BF_ICLMWSMU= 0x45c0, /*!< Clear audio mute sequence */
- TFA9912_BF_ICLCFMER= 0x45d0, /*!< Clear cfma err */
- TFA9912_BF_ICLCFMAC= 0x45e0, /*!< Clear cfma ack */
- TFA9912_BF_ICLCLKOOR= 0x45f0, /*!< Clear flag_clk_out_of_range */
- TFA9912_BF_ICLTDMER= 0x4600, /*!< Clear tdm error */
- TFA9912_BF_ICLCLPL= 0x4610, /*!< Clear clip left */
- TFA9912_BF_ICLCLP= 0x4620, /*!< Clear clip */
- TFA9912_BF_ICLOCPM= 0x4630, /*!< Clear mic ocpok */
- TFA9912_BF_ICLLP1= 0x4650, /*!< Clear low power mode1 */
- TFA9912_BF_ICLLA = 0x4660, /*!< Clear low amplitude detection */
- TFA9912_BF_ICLVDDP= 0x4670, /*!< Clear VDDP greater then VBAT */
- TFA9912_BF_ICLTAPDET= 0x4680, /*!< Clear Tap detected */
- TFA9912_BF_ICLAUDMOD= 0x4690, /*!< Clear Audio Mode activated */
- TFA9912_BF_ICLSAMMOD= 0x46a0, /*!< Clear SAM Mode activated */
- TFA9912_BF_ICLTAPMOD= 0x46b0, /*!< Clear Tap Mode Activated */
- TFA9912_BF_ICLTAPTRG= 0x46c0, /*!< Clear Comparator Interrupt */
- TFA9912_BF_IEVDDS= 0x4800, /*!< Enable por */
- TFA9912_BF_IEPLLS= 0x4810, /*!< Enable pll lock */
- TFA9912_BF_IEOTDS= 0x4820, /*!< Enable OTP alarm */
- TFA9912_BF_IEOVDS= 0x4830, /*!< Enable OVP alarm */
- TFA9912_BF_IEUVDS= 0x4840, /*!< Enable UVP alarm */
- TFA9912_BF_IECLKS= 0x4850, /*!< Enable clocks stable */
- TFA9912_BF_IEMTPB= 0x4860, /*!< Enable mtp busy */
- TFA9912_BF_IENOCLK= 0x4870, /*!< Enable lost clk */
- TFA9912_BF_IESPKS= 0x4880, /*!< Enable speaker error */
- TFA9912_BF_IEACS = 0x4890, /*!< Enable cold started */
- TFA9912_BF_IESWS = 0x48a0, /*!< Enable amplifier engage */
- TFA9912_BF_IEWDS = 0x48b0, /*!< Enable watchdog */
- TFA9912_BF_IEAMPS= 0x48c0, /*!< Enable enbl amp */
- TFA9912_BF_IEAREFS= 0x48d0, /*!< Enable ref enable */
- TFA9912_BF_IEADCCR= 0x48e0, /*!< Enable Control ADC */
- TFA9912_BF_IEBODNOK= 0x48f0, /*!< Enable BOD */
- TFA9912_BF_IEBSTCU= 0x4900, /*!< Enable DCDC current limiting */
- TFA9912_BF_IEBSTHI= 0x4910, /*!< Enable DCDC active */
- TFA9912_BF_IEBSTOC= 0x4920, /*!< Enable DCDC OCP */
- TFA9912_BF_IEBSTPC= 0x4930, /*!< Enable bst peakcur */
- TFA9912_BF_IEBSTVC= 0x4940, /*!< Enable DCDC level 1x */
- TFA9912_BF_IEBST86= 0x4950, /*!< Enable DCDC level 1.14x */
- TFA9912_BF_IEBST93= 0x4960, /*!< Enable DCDC level 1.07x */
- TFA9912_BF_IERCVLD= 0x4970, /*!< Enable rcvldop ready */
- TFA9912_BF_IEOCPL= 0x4980, /*!< Enable ocp alarm left */
- TFA9912_BF_IEOCPR= 0x4990, /*!< Enable ocp alarm */
- TFA9912_BF_IEMWSRC= 0x49a0, /*!< Enable waits HW I2C settings */
- TFA9912_BF_IEMWCFC= 0x49b0, /*!< Enable man wait cf config */
- TFA9912_BF_IEMWSMU= 0x49c0, /*!< Enable man Audio mute sequence */
- TFA9912_BF_IECFMER= 0x49d0, /*!< Enable cfma err */
- TFA9912_BF_IECFMAC= 0x49e0, /*!< Enable cfma ack */
- TFA9912_BF_IECLKOOR= 0x49f0, /*!< Enable flag_clk_out_of_range */
- TFA9912_BF_IETDMER= 0x4a00, /*!< Enable tdm error */
- TFA9912_BF_IECLPL= 0x4a10, /*!< Enable clip left */
- TFA9912_BF_IECLPR= 0x4a20, /*!< Enable clip */
- TFA9912_BF_IEOCPM1= 0x4a30, /*!< Enable mic ocpok */
- TFA9912_BF_IELP1 = 0x4a50, /*!< Enable low power mode1 */
- TFA9912_BF_IELA = 0x4a60, /*!< Enable low amplitude detection */
- TFA9912_BF_IEVDDP= 0x4a70, /*!< Enable VDDP greater than VBAT */
- TFA9912_BF_IETAPDET= 0x4a80, /*!< Enable Tap detected */
- TFA9912_BF_IEAUDMOD= 0x4a90, /*!< Enable Audio Mode activated */
- TFA9912_BF_IESAMMOD= 0x4aa0, /*!< Enable SAM Mode activated */
- TFA9912_BF_IETAPMOD= 0x4ab0, /*!< Enable Tap Mode Activated */
- TFA9912_BF_IETAPTRG= 0x4ac0, /*!< Enable comparator interrupt */
- TFA9912_BF_IPOVDDS= 0x4c00, /*!< Polarity por */
- TFA9912_BF_IPOPLLS= 0x4c10, /*!< Polarity pll lock */
- TFA9912_BF_IPOOTDS= 0x4c20, /*!< Polarity OTP alarm */
- TFA9912_BF_IPOOVDS= 0x4c30, /*!< Polarity OVP alarm */
- TFA9912_BF_IPOUVDS= 0x4c40, /*!< Polarity UVP alarm */
- TFA9912_BF_IPOCLKS= 0x4c50, /*!< Polarity clocks stable */
- TFA9912_BF_IPOMTPB= 0x4c60, /*!< Polarity mtp busy */
- TFA9912_BF_IPONOCLK= 0x4c70, /*!< Polarity lost clk */
- TFA9912_BF_IPOSPKS= 0x4c80, /*!< Polarity speaker error */
- TFA9912_BF_IPOACS= 0x4c90, /*!< Polarity cold started */
- TFA9912_BF_IPOSWS= 0x4ca0, /*!< Polarity amplifier engage */
- TFA9912_BF_IPOWDS= 0x4cb0, /*!< Polarity watchdog */
- TFA9912_BF_IPOAMPS= 0x4cc0, /*!< Polarity enbl amp */
- TFA9912_BF_IPOAREFS= 0x4cd0, /*!< Polarity ref enable */
- TFA9912_BF_IPOADCCR= 0x4ce0, /*!< Polarity Control ADC */
- TFA9912_BF_IPOBODNOK= 0x4cf0, /*!< Polarity BOD */
- TFA9912_BF_IPOBSTCU= 0x4d00, /*!< Polarity DCDC current limiting */
- TFA9912_BF_IPOBSTHI= 0x4d10, /*!< Polarity DCDC active */
- TFA9912_BF_IPOBSTOC= 0x4d20, /*!< Polarity DCDC OCP */
- TFA9912_BF_IPOBSTPC= 0x4d30, /*!< Polarity bst peakcur */
- TFA9912_BF_IPOBSTVC= 0x4d40, /*!< Polarity DCDC level 1x */
- TFA9912_BF_IPOBST86= 0x4d50, /*!< Polarity DCDC level 1.14x */
- TFA9912_BF_IPOBST93= 0x4d60, /*!< Polarity DCDC level 1.07x */
- TFA9912_BF_IPORCVLD= 0x4d70, /*!< Polarity rcvldop ready */
- TFA9912_BF_IPOOCPL= 0x4d80, /*!< Polarity ocp alarm left */
- TFA9912_BF_IPOOCPR= 0x4d90, /*!< Polarity ocp alarm */
- TFA9912_BF_IPOMWSRC= 0x4da0, /*!< Polarity waits HW I2C settings */
- TFA9912_BF_IPOMWCFC= 0x4db0, /*!< Polarity man wait cf config */
- TFA9912_BF_IPOMWSMU= 0x4dc0, /*!< Polarity man audio mute sequence */
- TFA9912_BF_IPOCFMER= 0x4dd0, /*!< Polarity cfma err */
- TFA9912_BF_IPOCFMAC= 0x4de0, /*!< Polarity cfma ack */
- TFA9912_BF_IPOCLKOOR= 0x4df0, /*!< Polarity flag_clk_out_of_range */
- TFA9912_BF_IPOTDMER= 0x4e00, /*!< Polarity tdm error */
- TFA9912_BF_IPOCLPL= 0x4e10, /*!< Polarity clip left */
- TFA9912_BF_IPOCLPR= 0x4e20, /*!< Polarity clip */
- TFA9912_BF_IPOOCPM= 0x4e30, /*!< Polarity mic ocpok */
- TFA9912_BF_IPOLP1= 0x4e50, /*!< Polarity low power mode1 */
- TFA9912_BF_IPOLA = 0x4e60, /*!< Polarity low amplitude detection */
- TFA9912_BF_IPOVDDP= 0x4e70, /*!< Polarity VDDP greater than VBAT */
- TFA9912_BF_IPOLTAPDET= 0x4e80, /*!< PolarityTap detected */
- TFA9912_BF_IPOLAUDMOD= 0x4e90, /*!< PolarityAudio Mode activated */
- TFA9912_BF_IPOLSAMMOD= 0x4ea0, /*!< PolaritySAM Mode activated */
- TFA9912_BF_IPOLTAPMOD= 0x4eb0, /*!< Polarity Tap Mode Activated */
- TFA9912_BF_IPOLTAPTRG= 0x4ec0, /*!< PolarityTap Comparator Trigger */
- TFA9912_BF_BSSCR = 0x5001, /*!< Battery Safeguard attack time */
- TFA9912_BF_BSST = 0x5023, /*!< Battery Safeguard threshold voltage level */
- TFA9912_BF_BSSRL = 0x5061, /*!< Battery Safeguard maximum reduction */
- TFA9912_BF_BSSRR = 0x5082, /*!< Battery Safeguard release time */
- TFA9912_BF_BSSHY = 0x50b1, /*!< Battery Safeguard hysteresis */
- TFA9912_BF_BSSAC = 0x50d0, /*!< Reset clipper - Auto clear */
- TFA9912_BF_BSSR = 0x50e0, /*!< Battery voltage read out */
- TFA9912_BF_BSSBY = 0x50f0, /*!< Bypass HW clipper */
- TFA9912_BF_BSSS = 0x5100, /*!< Vbat prot steepness */
- TFA9912_BF_INTSMUTE= 0x5110, /*!< Soft mute HW */
- TFA9912_BF_CFSML = 0x5120, /*!< Soft mute FW left */
- TFA9912_BF_CFSM = 0x5130, /*!< Soft mute FW */
- TFA9912_BF_HPFBYPL= 0x5140, /*!< Bypass HPF left */
- TFA9912_BF_HPFBYP= 0x5150, /*!< Bypass HPF */
- TFA9912_BF_DPSAL = 0x5160, /*!< Enable DPSA left */
- TFA9912_BF_DPSA = 0x5170, /*!< Enable DPSA */
- TFA9912_BF_VOL = 0x5187, /*!< FW volume control for primary audio channel */
- TFA9912_BF_HNDSFRCV= 0x5200, /*!< Selection receiver */
- TFA9912_BF_CLIPCTRL= 0x5222, /*!< Clip control setting */
- TFA9912_BF_AMPGAIN= 0x5257, /*!< Amplifier gain */
- TFA9912_BF_SLOPEE= 0x52d0, /*!< Enables slope control */
- TFA9912_BF_SLOPESET= 0x52e0, /*!< Slope speed setting (bin. coded) */
- TFA9912_BF_CFTAPPAT= 0x5c07, /*!< Coolflux tap pattern */
- TFA9912_BF_TAPDBGINFO= 0x5c83, /*!< Reserved */
- TFA9912_BF_TATPSTAT1= 0x5d0f, /*!< Tap Status 1 from CF FW */
- TFA9912_BF_TCOMPTHR= 0x5f03, /*!< Comparator threshold (in uV) */
- TFA9912_BF_PGAGAIN= 0x6081, /*!< PGA gain selection */
- TFA9912_BF_TDMSPKG= 0x6123, /*!< System gain (INPLEV 0) */
- TFA9912_BF_LPM1LVL= 0x6505, /*!< low power mode1 detector ctrl threshold for low_audio_lvl */
- TFA9912_BF_LPM1HLD= 0x6565, /*!< Low power mode1 detector, ctrl hold time before low audio is reckoned to be low audio */
- TFA9912_BF_LPM1DIS= 0x65c0, /*!< low power mode1 detector control */
- TFA9912_BF_DCDIS = 0x6630, /*!< DCDC */
- TFA9912_BF_TDMSRCMAP= 0x6801, /*!< tdm source mapping */
- TFA9912_BF_TDMSRCAS= 0x6821, /*!< frame a selection */
- TFA9912_BF_TDMSRCBS= 0x6841, /*!< frame b selection */
- TFA9912_BF_ANC1C = 0x68a0, /*!< ANC one s complement */
- TFA9912_BF_SAMMODE= 0x6901, /*!< Sam mode */
- TFA9912_BF_DCMCC = 0x7033, /*!< Max coil current */
- TFA9912_BF_DCCV = 0x7071, /*!< Slope compensation current, represents LxF (inductance x frequency) value */
- TFA9912_BF_DCIE = 0x7090, /*!< Adaptive boost mode */
- TFA9912_BF_DCSR = 0x70a0, /*!< Soft ramp up/down */
- TFA9912_BF_DCINSEL= 0x70c1, /*!< DCDC IIR input Selection */
- TFA9912_BF_DCPWM = 0x70f0, /*!< DCDC PWM only mode */
- TFA9912_BF_DCTRIP= 0x7504, /*!< Adaptive boost trip levels 1, effective only when boost_intelligent is set to 1 */
- TFA9912_BF_DCTRIP2= 0x7554, /*!< Adaptive boost trip level 2, effective only when boost_intelligent is set to 1 */
- TFA9912_BF_DCTRIPT= 0x75a4, /*!< Adaptive boost trip levels, effective only when boost_intelligent is set to 1 */
- TFA9912_BF_DCVOF = 0x7635, /*!< First boost voltage level */
- TFA9912_BF_DCVOS = 0x7695, /*!< Second boost voltage level */
- TFA9912_BF_RST = 0x9000, /*!< Reset */
- TFA9912_BF_DMEM = 0x9011, /*!< Target memory */
- TFA9912_BF_AIF = 0x9030, /*!< Auto increment */
- TFA9912_BF_CFINT = 0x9040, /*!< Interrupt - auto clear */
- TFA9912_BF_CFCGATE= 0x9050, /*!< Coolflux clock gating disabling control */
- TFA9912_BF_REQCMD= 0x9080, /*!< Firmware event request rpc command */
- TFA9912_BF_REQRST= 0x9090, /*!< Firmware event request reset restart */
- TFA9912_BF_REQMIPS= 0x90a0, /*!< Firmware event request short on mips */
- TFA9912_BF_REQMUTED= 0x90b0, /*!< Firmware event request mute sequence ready */
- TFA9912_BF_REQVOL= 0x90c0, /*!< Firmware event request volume ready */
- TFA9912_BF_REQDMG= 0x90d0, /*!< Firmware event request speaker damage detected */
- TFA9912_BF_REQCAL= 0x90e0, /*!< Firmware event request calibration completed */
- TFA9912_BF_REQRSV= 0x90f0, /*!< Firmware event request reserved */
- TFA9912_BF_MADD = 0x910f, /*!< Memory address */
- TFA9912_BF_MEMA = 0x920f, /*!< Activate memory access */
- TFA9912_BF_ERR = 0x9307, /*!< Error flags */
- TFA9912_BF_ACKCMD= 0x9380, /*!< Firmware event acknowledge rpc command */
- TFA9912_BF_ACKRST= 0x9390, /*!< Firmware event acknowledge reset restart */
- TFA9912_BF_ACKMIPS= 0x93a0, /*!< Firmware event acknowledge short on mips */
- TFA9912_BF_ACKMUTED= 0x93b0, /*!< Firmware event acknowledge mute sequence ready */
- TFA9912_BF_ACKVOL= 0x93c0, /*!< Firmware event acknowledge volume ready */
- TFA9912_BF_ACKDMG= 0x93d0, /*!< Firmware event acknowledge speaker damage detected */
- TFA9912_BF_ACKCAL= 0x93e0, /*!< Firmware event acknowledge calibration completed */
- TFA9912_BF_ACKRSV= 0x93f0, /*!< Firmware event acknowledge reserved */
- TFA9912_BF_MTPK = 0xa107, /*!< MTP KEY2 register */
- TFA9912_BF_KEY1LOCKED= 0xa200, /*!< Indicates KEY1 is locked */
- TFA9912_BF_KEY2LOCKED= 0xa210, /*!< Indicates KEY2 is locked */
- TFA9912_BF_CIMTP = 0xa360, /*!< Start copying data from I2C mtp registers to mtp */
- TFA9912_BF_MTPRDMSB= 0xa50f, /*!< MSB word of MTP manual read data */
- TFA9912_BF_MTPRDLSB= 0xa60f, /*!< LSB word of MTP manual read data */
- TFA9912_BF_EXTTS = 0xb108, /*!< External temperature (C) */
- TFA9912_BF_TROS = 0xb190, /*!< Select temp Speaker calibration */
- TFA9912_BF_SWPROFIL= 0xee0f, /*!< Software profile data */
- TFA9912_BF_SWVSTEP= 0xef0f, /*!< Software vstep information */
- TFA9912_BF_MTPOTC= 0xf000, /*!< Calibration schedule */
- TFA9912_BF_MTPEX = 0xf010, /*!< Calibration Ron executed */
- TFA9912_BF_DCMCCAPI= 0xf020, /*!< Calibration current limit DCDC */
- TFA9912_BF_DCMCCSB= 0xf030, /*!< Sign bit for delta calibration current limit DCDC */
- TFA9912_BF_DCMCCCL= 0xf042, /*!< Calibration delta current limit DCDC */
- TFA9912_BF_USERDEF= 0xf078, /*!< Reserved space for allowing customer to store speaker information */
- TFA9912_BF_R25C = 0xf40f, /*!< Ron resistance of speaker coil */
-} nxpTfa9912BfEnumList_t;
-#define TFA9912_NAMETABLE static tfaBfName_t Tfa9912DatasheetNames[]= {\
- { 0x0, "PWDN"}, /* Powerdown selection , */\
- { 0x10, "I2CR"}, /* I2C Reset - Auto clear , */\
- { 0x20, "CFE"}, /* Enable CoolFlux , */\
- { 0x30, "AMPE"}, /* Enables the Amplifier , */\
- { 0x40, "DCA"}, /* Activate DC-to-DC converter , */\
- { 0x50, "SBSL"}, /* Coolflux configured , */\
- { 0x60, "AMPC"}, /* CoolFlux controls amplifier , */\
- { 0x71, "INTP"}, /* Interrupt config , */\
- { 0x90, "FSSSEL"}, /* Audio sample reference , */\
- { 0xb0, "BYPOCP"}, /* Bypass OCP , */\
- { 0xc0, "TSTOCP"}, /* OCP testing control , */\
- { 0x101, "AMPINSEL"}, /* Amplifier input selection , */\
- { 0x120, "MANSCONF"}, /* I2C configured , */\
- { 0x130, "MANCOLD"}, /* Execute cold start , */\
- { 0x140, "MANAOOSC"}, /* Internal osc off at PWDN , */\
- { 0x150, "MANROBOD"}, /* Reaction on BOD , */\
- { 0x160, "BODE"}, /* BOD Enable , */\
- { 0x170, "BODHYS"}, /* BOD Hysteresis , */\
- { 0x181, "BODFILT"}, /* BOD filter , */\
- { 0x1a1, "BODTHLVL"}, /* BOD threshold , */\
- { 0x1d0, "MUTETO"}, /* Time out SB mute sequence , */\
- { 0x1e0, "RCVNS"}, /* Noise shaper selection , */\
- { 0x1f0, "MANWDE"}, /* Watchdog enable , */\
- { 0x203, "AUDFS"}, /* Sample rate (fs) , */\
- { 0x240, "INPLEV"}, /* TDM output attenuation , */\
- { 0x255, "FRACTDEL"}, /* V/I Fractional delay , */\
- { 0x2b0, "BYPHVBF"}, /* Bypass HVBAT filter , */\
- { 0x2c0, "TDMC"}, /* TDM Compatibility with TFA9872 , */\
- { 0x2e0, "ENBLADC10"}, /* ADC10 Enable - I2C direct mode , */\
- { 0x30f, "REV"}, /* Revision info , */\
- { 0x401, "REFCKEXT"}, /* PLL external ref clock , */\
- { 0x420, "REFCKSEL"}, /* PLL internal ref clock , */\
- { 0x430, "ENCFCKSEL"}, /* Coolflux DSP clock scaling, low power mode , */\
- { 0x441, "CFCKSEL"}, /* Coolflux DSP clock scaler selection for low power mode, */\
- { 0x460, "TDMINFSEL"}, /* TDM clock selection , */\
- { 0x470, "DISBLAUTOCLKSEL"}, /* Disable Automatic dsp clock source selection , */\
- { 0x480, "SELCLKSRC"}, /* I2C selection of DSP clock when auto select is disabled, */\
- { 0x490, "SELTIMSRC"}, /* I2C selection of Watchdog and Timer clock , */\
- { 0x500, "SSLEFTE"}, /* , */\
- { 0x510, "SPKSSEN"}, /* Enable speaker path , */\
- { 0x520, "VSLEFTE"}, /* , */\
- { 0x530, "VSRIGHTE"}, /* Voltage sense , */\
- { 0x540, "CSLEFTE"}, /* , */\
- { 0x550, "CSRIGHTE"}, /* Current sense , */\
- { 0x560, "SSPDME"}, /* Sub-system PDM , */\
- { 0x570, "PGALE"}, /* Enable PGA chop clock for left channel , */\
- { 0x580, "PGARE"}, /* Enable PGA chop clock , */\
- { 0x590, "SSTDME"}, /* Sub-system TDM , */\
- { 0x5a0, "SSPBSTE"}, /* Sub-system boost , */\
- { 0x5b0, "SSADCE"}, /* Sub-system ADC , */\
- { 0x5c0, "SSFAIME"}, /* Sub-system FAIM , */\
- { 0x5d0, "SSCFTIME"}, /* CF Sub-system timer , */\
- { 0x5e0, "SSCFWDTE"}, /* CF Sub-system WDT , */\
- { 0x5f0, "FAIMVBGOVRRL"}, /* Over rule of vbg for FaIM access , */\
- { 0x600, "SAMSPKSEL"}, /* Input selection for TAP/SAM , */\
- { 0x610, "PDM2IISEN"}, /* PDM2IIS Bridge enable , */\
- { 0x620, "TAPRSTBYPASS"}, /* Tap decimator reset bypass - Bypass the decimator reset from tapdec, */\
- { 0x631, "CARDECISEL0"}, /* Cardec input 0 sel , */\
- { 0x651, "CARDECISEL1"}, /* Cardec input sel , */\
- { 0x670, "TAPDECSEL"}, /* Select TAP/Cardec for TAP , */\
- { 0x680, "COMPCOUNT"}, /* Comparator o/p filter selection , */\
- { 0x691, "STARTUPMODE"}, /* Startup Mode Selection , */\
- { 0x6b0, "AUTOTAP"}, /* Enable auto tap switching , */\
- { 0x6c1, "COMPINITIME"}, /* Comparator initialization time to be used in Tap Machine, */\
- { 0x6e1, "ANAPINITIME"}, /* Analog initialization time to be used in Tap Machine, */\
- { 0x707, "CCHKTH"}, /* Clock check Higher Threshold , */\
- { 0x787, "CCHKTL"}, /* Clock check Higher Threshold , */\
- { 0x802, "AMPOCRT"}, /* Amplifier on-off criteria for shutdown , */\
- { 0x832, "AMPTCRR"}, /* Amplifier on-off criteria for tap mode entry , */\
- { 0xd00, "STGS"}, /* PDM side tone gain selector , */\
- { 0xd18, "STGAIN"}, /* Side tone gain , */\
- { 0xda0, "STSMUTE"}, /* Side tone soft mute , */\
- { 0xdb0, "ST1C"}, /* side tone one s complement , */\
- { 0xe80, "CMFBEL"}, /* CMFB enable left , */\
- { 0x1000, "VDDS"}, /* POR , */\
- { 0x1010, "PLLS"}, /* PLL lock , */\
- { 0x1020, "OTDS"}, /* OTP alarm , */\
- { 0x1030, "OVDS"}, /* OVP alarm , */\
- { 0x1040, "UVDS"}, /* UVP alarm , */\
- { 0x1050, "CLKS"}, /* Clocks stable , */\
- { 0x1060, "MTPB"}, /* MTP busy , */\
- { 0x1070, "NOCLK"}, /* Lost clock , */\
- { 0x1090, "ACS"}, /* Cold Start , */\
- { 0x10a0, "SWS"}, /* Amplifier engage , */\
- { 0x10b0, "WDS"}, /* Watchdog , */\
- { 0x10c0, "AMPS"}, /* Amplifier enable , */\
- { 0x10d0, "AREFS"}, /* References enable , */\
- { 0x10e0, "ADCCR"}, /* Control ADC , */\
- { 0x10f0, "BODNOK"}, /* BOD , */\
- { 0x1100, "DCIL"}, /* DCDC current limiting , */\
- { 0x1110, "DCDCA"}, /* DCDC active , */\
- { 0x1120, "DCOCPOK"}, /* DCDC OCP nmos , */\
- { 0x1130, "DCPEAKCUR"}, /* Indicates current is max in DC-to-DC converter , */\
- { 0x1140, "DCHVBAT"}, /* DCDC level 1x , */\
- { 0x1150, "DCH114"}, /* DCDC level 1.14x , */\
- { 0x1160, "DCH107"}, /* DCDC level 1.07x , */\
- { 0x1170, "STMUTEB"}, /* side tone (un)mute busy , */\
- { 0x1180, "STMUTE"}, /* side tone mute state , */\
- { 0x1190, "TDMLUTER"}, /* TDM LUT error , */\
- { 0x11a2, "TDMSTAT"}, /* TDM status bits , */\
- { 0x11d0, "TDMERR"}, /* TDM error , */\
- { 0x11e0, "HAPTIC"}, /* Status haptic driver , */\
- { 0x1300, "OCPOAP"}, /* OCPOK pmos A , */\
- { 0x1310, "OCPOAN"}, /* OCPOK nmos A , */\
- { 0x1320, "OCPOBP"}, /* OCPOK pmos B , */\
- { 0x1330, "OCPOBN"}, /* OCPOK nmos B , */\
- { 0x1340, "CLIPAH"}, /* Clipping A to Vddp , */\
- { 0x1350, "CLIPAL"}, /* Clipping A to gnd , */\
- { 0x1360, "CLIPBH"}, /* Clipping B to Vddp , */\
- { 0x1370, "CLIPBL"}, /* Clipping B to gnd , */\
- { 0x1380, "OCDS"}, /* OCP amplifier , */\
- { 0x1390, "CLIPS"}, /* Amplifier clipping , */\
- { 0x13a0, "TCMPTRG"}, /* Status Tap comparator triggered , */\
- { 0x13b0, "TAPDET"}, /* Status Tap detected , */\
- { 0x13c0, "MANWAIT1"}, /* Wait HW I2C settings , */\
- { 0x13d0, "MANWAIT2"}, /* Wait CF config , */\
- { 0x13e0, "MANMUTE"}, /* Audio mute sequence , */\
- { 0x13f0, "MANOPER"}, /* Operating state , */\
- { 0x1400, "SPKSL"}, /* Left speaker status , */\
- { 0x1410, "SPKS"}, /* Speaker status , */\
- { 0x1420, "CLKOOR"}, /* External clock status , */\
- { 0x1433, "MANSTATE"}, /* Device manager status , */\
- { 0x1471, "DCMODE"}, /* DCDC mode status bits , */\
- { 0x1490, "DSPCLKSRC"}, /* DSP clock source selected by manager , */\
- { 0x14a1, "STARTUPMODSTAT"}, /* Startup Mode Selected by Manager(Read Only) , */\
- { 0x14c3, "TSPMSTATE"}, /* Tap Machine State , */\
- { 0x1509, "BATS"}, /* Battery voltage (V) , */\
- { 0x1608, "TEMPS"}, /* IC Temperature (C) , */\
- { 0x1709, "VDDPS"}, /* IC VDDP voltage ( 1023*VDDP/13 V) , */\
- { 0x17a0, "DCILCF"}, /* DCDC current limiting for DSP , */\
- { 0x2000, "TDMUC"}, /* Mode setting , */\
- { 0x2011, "DIO4SEL"}, /* DIO4 Input selection , */\
- { 0x2040, "TDME"}, /* Enable TDM interface , */\
- { 0x2050, "TDMMODE"}, /* Slave/master , */\
- { 0x2060, "TDMCLINV"}, /* Reception data to BCK clock , */\
- { 0x2073, "TDMFSLN"}, /* FS length , */\
- { 0x20b0, "TDMFSPOL"}, /* FS polarity , */\
- { 0x20c3, "TDMNBCK"}, /* N-BCK's in FS , */\
- { 0x2103, "TDMSLOTS"}, /* N-slots in Frame , */\
- { 0x2144, "TDMSLLN"}, /* N-bits in slot , */\
- { 0x2194, "TDMBRMG"}, /* N-bits remaining , */\
- { 0x21e0, "TDMDEL"}, /* data delay to FS , */\
- { 0x21f0, "TDMADJ"}, /* data adjustment , */\
- { 0x2201, "TDMOOMP"}, /* Received audio compression , */\
- { 0x2224, "TDMSSIZE"}, /* Sample size per slot , */\
- { 0x2271, "TDMTXDFO"}, /* Format unused bits in a slot , */\
- { 0x2291, "TDMTXUS0"}, /* Format unused slots GAINIO , */\
- { 0x22b1, "TDMTXUS1"}, /* Format unused slots DIO1 , */\
- { 0x22d1, "TDMTXUS2"}, /* Format unused slots DIO2 , */\
- { 0x2300, "TDMGIE"}, /* Control gain (channel in 0) , */\
- { 0x2310, "TDMDCE"}, /* Control audio left (channel in 1 ) , */\
- { 0x2320, "TDMSPKE"}, /* Control audio right (channel in 2 ) , */\
- { 0x2330, "TDMCSE"}, /* Current sense , */\
- { 0x2340, "TDMVSE"}, /* Voltage sense , */\
- { 0x2350, "TDMGOE"}, /* DSP Gainout , */\
- { 0x2360, "TDMCF2E"}, /* DSP 2 , */\
- { 0x2370, "TDMCF3E"}, /* DSP 3 , */\
- { 0x2380, "TDMCFE"}, /* DSP , */\
- { 0x2390, "TDMES6"}, /* Loopback of Audio left (channel 1) , */\
- { 0x23a0, "TDMES7"}, /* Loopback of Audio right (channel 2) , */\
- { 0x23b0, "TDMCF4E"}, /* AEC ref right control , */\
- { 0x23c0, "TDMPD1E"}, /* PDM 1 control , */\
- { 0x23d0, "TDMPD2E"}, /* PDM 2 control , */\
- { 0x2401, "TDMGIN"}, /* IO gainin , */\
- { 0x2421, "TDMLIO"}, /* IO audio left , */\
- { 0x2441, "TDMRIO"}, /* IO audio right , */\
- { 0x2461, "TDMCSIO"}, /* IO Current Sense , */\
- { 0x2481, "TDMVSIO"}, /* IO voltage sense , */\
- { 0x24a1, "TDMGOIO"}, /* IO gain out , */\
- { 0x24c1, "TDMCFIO2"}, /* IO DSP 2 , */\
- { 0x24e1, "TDMCFIO3"}, /* IO DSP 3 , */\
- { 0x2501, "TDMCFIO"}, /* IO DSP , */\
- { 0x2521, "TDMLPB6"}, /* IO Source 6 , */\
- { 0x2541, "TDMLPB7"}, /* IO Source 7 , */\
- { 0x2603, "TDMGS"}, /* Control gainin , */\
- { 0x2643, "TDMDCS"}, /* tdm slot for audio left (channel 1) , */\
- { 0x2683, "TDMSPKS"}, /* tdm slot for audio right (channel 2) , */\
- { 0x26c3, "TDMCSS"}, /* Slot Position of Current Sense Out , */\
- { 0x2703, "TDMVSS"}, /* Slot Position of Voltage sense , */\
- { 0x2743, "TDMCGOS"}, /* Slot Position of GAIN out , */\
- { 0x2783, "TDMCF2S"}, /* Slot Position DSPout2 , */\
- { 0x27c3, "TDMCF3S"}, /* Slot Position DSPout3 , */\
- { 0x2803, "TDMCFS"}, /* Slot Position of DSPout , */\
- { 0x2843, "TDMEDAT6S"}, /* Slot Position of loopback channel left , */\
- { 0x2883, "TDMEDAT7S"}, /* Slot Position of loopback channel right , */\
- { 0x2901, "TDMTXUS3"}, /* Format unused slots D3 , */\
- { 0x3100, "PDMSM"}, /* PDM control , */\
- { 0x3110, "PDMSTSEL"}, /* PDM Decimator input selection , */\
- { 0x3120, "PDMSTENBL"}, /* Side tone input enable , */\
- { 0x3130, "PDMLSEL"}, /* PDM data selection for left channel during PDM direct mode, */\
- { 0x3140, "PDMRSEL"}, /* PDM data selection for right channel during PDM direct mode, */\
- { 0x3150, "MICVDDE"}, /* Enable MICVDD , */\
- { 0x3201, "PDMCLRAT"}, /* PDM BCK/Fs ratio , */\
- { 0x3223, "PDMGAIN"}, /* PDM gain , */\
- { 0x3263, "PDMOSEL"}, /* PDM output selection - RE/FE data combination , */\
- { 0x32a0, "SELCFHAPD"}, /* Select the source for haptic data output (not for customer), */\
- { 0x4000, "ISTVDDS"}, /* Status POR , */\
- { 0x4010, "ISTPLLS"}, /* Status PLL lock , */\
- { 0x4020, "ISTOTDS"}, /* Status OTP alarm , */\
- { 0x4030, "ISTOVDS"}, /* Status OVP alarm , */\
- { 0x4040, "ISTUVDS"}, /* Status UVP alarm , */\
- { 0x4050, "ISTCLKS"}, /* Status clocks stable , */\
- { 0x4060, "ISTMTPB"}, /* Status MTP busy , */\
- { 0x4070, "ISTNOCLK"}, /* Status lost clock , */\
- { 0x4080, "ISTSPKS"}, /* Status speaker error , */\
- { 0x4090, "ISTACS"}, /* Status cold start , */\
- { 0x40a0, "ISTSWS"}, /* Status amplifier engage , */\
- { 0x40b0, "ISTWDS"}, /* Status watchdog , */\
- { 0x40c0, "ISTAMPS"}, /* Status amplifier enable , */\
- { 0x40d0, "ISTAREFS"}, /* Status Ref enable , */\
- { 0x40e0, "ISTADCCR"}, /* Status Control ADC , */\
- { 0x40f0, "ISTBODNOK"}, /* Status BOD , */\
- { 0x4100, "ISTBSTCU"}, /* Status DCDC current limiting , */\
- { 0x4110, "ISTBSTHI"}, /* Status DCDC active , */\
- { 0x4120, "ISTBSTOC"}, /* Status DCDC OCP , */\
- { 0x4130, "ISTBSTPKCUR"}, /* Status bst peakcur , */\
- { 0x4140, "ISTBSTVC"}, /* Status DCDC level 1x , */\
- { 0x4150, "ISTBST86"}, /* Status DCDC level 1.14x , */\
- { 0x4160, "ISTBST93"}, /* Status DCDC level 1.07x , */\
- { 0x4170, "ISTRCVLD"}, /* Status rcvldop ready , */\
- { 0x4180, "ISTOCPL"}, /* Status ocp alarm left , */\
- { 0x4190, "ISTOCPR"}, /* Status ocp alarm , */\
- { 0x41a0, "ISTMWSRC"}, /* Status Waits HW I2C settings , */\
- { 0x41b0, "ISTMWCFC"}, /* Status waits CF config , */\
- { 0x41c0, "ISTMWSMU"}, /* Status Audio mute sequence , */\
- { 0x41d0, "ISTCFMER"}, /* Status cfma error , */\
- { 0x41e0, "ISTCFMAC"}, /* Status cfma ack , */\
- { 0x41f0, "ISTCLKOOR"}, /* Status flag_clk_out_of_range , */\
- { 0x4200, "ISTTDMER"}, /* Status tdm error , */\
- { 0x4210, "ISTCLPL"}, /* Status clip left , */\
- { 0x4220, "ISTCLPR"}, /* Status clip , */\
- { 0x4230, "ISTOCPM"}, /* Status mic ocpok , */\
- { 0x4250, "ISTLP1"}, /* Status low power mode1 , */\
- { 0x4260, "ISTLA"}, /* Status low amplitude detection , */\
- { 0x4270, "ISTVDDP"}, /* Status VDDP greater than VBAT , */\
- { 0x4280, "ISTTAPDET"}, /* Status Tap detected , */\
- { 0x4290, "ISTAUDMOD"}, /* Status Audio Mode activated , */\
- { 0x42a0, "ISTSAMMOD"}, /* Status SAM Mode activated , */\
- { 0x42b0, "ISTTAPMOD"}, /* Status Tap Mode Activated , */\
- { 0x42c0, "ISTTAPTRG"}, /* Status Tap comparator triggered , */\
- { 0x4400, "ICLVDDS"}, /* Clear POR , */\
- { 0x4410, "ICLPLLS"}, /* Clear PLL lock , */\
- { 0x4420, "ICLOTDS"}, /* Clear OTP alarm , */\
- { 0x4430, "ICLOVDS"}, /* Clear OVP alarm , */\
- { 0x4440, "ICLUVDS"}, /* Clear UVP alarm , */\
- { 0x4450, "ICLCLKS"}, /* Clear clocks stable , */\
- { 0x4460, "ICLMTPB"}, /* Clear mtp busy , */\
- { 0x4470, "ICLNOCLK"}, /* Clear lost clk , */\
- { 0x4480, "ICLSPKS"}, /* Clear speaker error , */\
- { 0x4490, "ICLACS"}, /* Clear cold started , */\
- { 0x44a0, "ICLSWS"}, /* Clear amplifier engage , */\
- { 0x44b0, "ICLWDS"}, /* Clear watchdog , */\
- { 0x44c0, "ICLAMPS"}, /* Clear enbl amp , */\
- { 0x44d0, "ICLAREFS"}, /* Clear ref enable , */\
- { 0x44e0, "ICLADCCR"}, /* Clear control ADC , */\
- { 0x44f0, "ICLBODNOK"}, /* Clear BOD , */\
- { 0x4500, "ICLBSTCU"}, /* Clear DCDC current limiting , */\
- { 0x4510, "ICLBSTHI"}, /* Clear DCDC active , */\
- { 0x4520, "ICLBSTOC"}, /* Clear DCDC OCP , */\
- { 0x4530, "ICLBSTPC"}, /* Clear bst peakcur , */\
- { 0x4540, "ICLBSTVC"}, /* Clear DCDC level 1x , */\
- { 0x4550, "ICLBST86"}, /* Clear DCDC level 1.14x , */\
- { 0x4560, "ICLBST93"}, /* Clear DCDC level 1.07x , */\
- { 0x4570, "ICLRCVLD"}, /* Clear rcvldop ready , */\
- { 0x4580, "ICLOCPL"}, /* Clear ocp alarm left , */\
- { 0x4590, "ICLOCPR"}, /* Clear ocp alarm , */\
- { 0x45a0, "ICLMWSRC"}, /* Clear wait HW I2C settings , */\
- { 0x45b0, "ICLMWCFC"}, /* Clear wait cf config , */\
- { 0x45c0, "ICLMWSMU"}, /* Clear audio mute sequence , */\
- { 0x45d0, "ICLCFMER"}, /* Clear cfma err , */\
- { 0x45e0, "ICLCFMAC"}, /* Clear cfma ack , */\
- { 0x45f0, "ICLCLKOOR"}, /* Clear flag_clk_out_of_range , */\
- { 0x4600, "ICLTDMER"}, /* Clear tdm error , */\
- { 0x4610, "ICLCLPL"}, /* Clear clip left , */\
- { 0x4620, "ICLCLP"}, /* Clear clip , */\
- { 0x4630, "ICLOCPM"}, /* Clear mic ocpok , */\
- { 0x4650, "ICLLP1"}, /* Clear low power mode1 , */\
- { 0x4660, "ICLLA"}, /* Clear low amplitude detection , */\
- { 0x4670, "ICLVDDP"}, /* Clear VDDP greater then VBAT , */\
- { 0x4680, "ICLTAPDET"}, /* Clear Tap detected , */\
- { 0x4690, "ICLAUDMOD"}, /* Clear Audio Mode activated , */\
- { 0x46a0, "ICLSAMMOD"}, /* Clear SAM Mode activated , */\
- { 0x46b0, "ICLTAPMOD"}, /* Clear Tap Mode Activated , */\
- { 0x46c0, "ICLTAPTRG"}, /* Clear Comparator Interrupt , */\
- { 0x4800, "IEVDDS"}, /* Enable por , */\
- { 0x4810, "IEPLLS"}, /* Enable pll lock , */\
- { 0x4820, "IEOTDS"}, /* Enable OTP alarm , */\
- { 0x4830, "IEOVDS"}, /* Enable OVP alarm , */\
- { 0x4840, "IEUVDS"}, /* Enable UVP alarm , */\
- { 0x4850, "IECLKS"}, /* Enable clocks stable , */\
- { 0x4860, "IEMTPB"}, /* Enable mtp busy , */\
- { 0x4870, "IENOCLK"}, /* Enable lost clk , */\
- { 0x4880, "IESPKS"}, /* Enable speaker error , */\
- { 0x4890, "IEACS"}, /* Enable cold started , */\
- { 0x48a0, "IESWS"}, /* Enable amplifier engage , */\
- { 0x48b0, "IEWDS"}, /* Enable watchdog , */\
- { 0x48c0, "IEAMPS"}, /* Enable enbl amp , */\
- { 0x48d0, "IEAREFS"}, /* Enable ref enable , */\
- { 0x48e0, "IEADCCR"}, /* Enable Control ADC , */\
- { 0x48f0, "IEBODNOK"}, /* Enable BOD , */\
- { 0x4900, "IEBSTCU"}, /* Enable DCDC current limiting , */\
- { 0x4910, "IEBSTHI"}, /* Enable DCDC active , */\
- { 0x4920, "IEBSTOC"}, /* Enable DCDC OCP , */\
- { 0x4930, "IEBSTPC"}, /* Enable bst peakcur , */\
- { 0x4940, "IEBSTVC"}, /* Enable DCDC level 1x , */\
- { 0x4950, "IEBST86"}, /* Enable DCDC level 1.14x , */\
- { 0x4960, "IEBST93"}, /* Enable DCDC level 1.07x , */\
- { 0x4970, "IERCVLD"}, /* Enable rcvldop ready , */\
- { 0x4980, "IEOCPL"}, /* Enable ocp alarm left , */\
- { 0x4990, "IEOCPR"}, /* Enable ocp alarm , */\
- { 0x49a0, "IEMWSRC"}, /* Enable waits HW I2C settings , */\
- { 0x49b0, "IEMWCFC"}, /* Enable man wait cf config , */\
- { 0x49c0, "IEMWSMU"}, /* Enable man Audio mute sequence , */\
- { 0x49d0, "IECFMER"}, /* Enable cfma err , */\
- { 0x49e0, "IECFMAC"}, /* Enable cfma ack , */\
- { 0x49f0, "IECLKOOR"}, /* Enable flag_clk_out_of_range , */\
- { 0x4a00, "IETDMER"}, /* Enable tdm error , */\
- { 0x4a10, "IECLPL"}, /* Enable clip left , */\
- { 0x4a20, "IECLPR"}, /* Enable clip , */\
- { 0x4a30, "IEOCPM1"}, /* Enable mic ocpok , */\
- { 0x4a50, "IELP1"}, /* Enable low power mode1 , */\
- { 0x4a60, "IELA"}, /* Enable low amplitude detection , */\
- { 0x4a70, "IEVDDP"}, /* Enable VDDP greater than VBAT , */\
- { 0x4a80, "IETAPDET"}, /* Enable Tap detected , */\
- { 0x4a90, "IEAUDMOD"}, /* Enable Audio Mode activated , */\
- { 0x4aa0, "IESAMMOD"}, /* Enable SAM Mode activated , */\
- { 0x4ab0, "IETAPMOD"}, /* Enable Tap Mode Activated , */\
- { 0x4ac0, "IETAPTRG"}, /* Enable comparator interrupt , */\
- { 0x4c00, "IPOVDDS"}, /* Polarity por , */\
- { 0x4c10, "IPOPLLS"}, /* Polarity pll lock , */\
- { 0x4c20, "IPOOTDS"}, /* Polarity OTP alarm , */\
- { 0x4c30, "IPOOVDS"}, /* Polarity OVP alarm , */\
- { 0x4c40, "IPOUVDS"}, /* Polarity UVP alarm , */\
- { 0x4c50, "IPOCLKS"}, /* Polarity clocks stable , */\
- { 0x4c60, "IPOMTPB"}, /* Polarity mtp busy , */\
- { 0x4c70, "IPONOCLK"}, /* Polarity lost clk , */\
- { 0x4c80, "IPOSPKS"}, /* Polarity speaker error , */\
- { 0x4c90, "IPOACS"}, /* Polarity cold started , */\
- { 0x4ca0, "IPOSWS"}, /* Polarity amplifier engage , */\
- { 0x4cb0, "IPOWDS"}, /* Polarity watchdog , */\
- { 0x4cc0, "IPOAMPS"}, /* Polarity enbl amp , */\
- { 0x4cd0, "IPOAREFS"}, /* Polarity ref enable , */\
- { 0x4ce0, "IPOADCCR"}, /* Polarity Control ADC , */\
- { 0x4cf0, "IPOBODNOK"}, /* Polarity BOD , */\
- { 0x4d00, "IPOBSTCU"}, /* Polarity DCDC current limiting , */\
- { 0x4d10, "IPOBSTHI"}, /* Polarity DCDC active , */\
- { 0x4d20, "IPOBSTOC"}, /* Polarity DCDC OCP , */\
- { 0x4d30, "IPOBSTPC"}, /* Polarity bst peakcur , */\
- { 0x4d40, "IPOBSTVC"}, /* Polarity DCDC level 1x , */\
- { 0x4d50, "IPOBST86"}, /* Polarity DCDC level 1.14x , */\
- { 0x4d60, "IPOBST93"}, /* Polarity DCDC level 1.07x , */\
- { 0x4d70, "IPORCVLD"}, /* Polarity rcvldop ready , */\
- { 0x4d80, "IPOOCPL"}, /* Polarity ocp alarm left , */\
- { 0x4d90, "IPOOCPR"}, /* Polarity ocp alarm , */\
- { 0x4da0, "IPOMWSRC"}, /* Polarity waits HW I2C settings , */\
- { 0x4db0, "IPOMWCFC"}, /* Polarity man wait cf config , */\
- { 0x4dc0, "IPOMWSMU"}, /* Polarity man audio mute sequence , */\
- { 0x4dd0, "IPOCFMER"}, /* Polarity cfma err , */\
- { 0x4de0, "IPOCFMAC"}, /* Polarity cfma ack , */\
- { 0x4df0, "IPOCLKOOR"}, /* Polarity flag_clk_out_of_range , */\
- { 0x4e00, "IPOTDMER"}, /* Polarity tdm error , */\
- { 0x4e10, "IPOCLPL"}, /* Polarity clip left , */\
- { 0x4e20, "IPOCLPR"}, /* Polarity clip , */\
- { 0x4e30, "IPOOCPM"}, /* Polarity mic ocpok , */\
- { 0x4e50, "IPOLP1"}, /* Polarity low power mode1 , */\
- { 0x4e60, "IPOLA"}, /* Polarity low amplitude detection , */\
- { 0x4e70, "IPOVDDP"}, /* Polarity VDDP greater than VBAT , */\
- { 0x4e80, "IPOLTAPDET"}, /* PolarityTap detected , */\
- { 0x4e90, "IPOLAUDMOD"}, /* PolarityAudio Mode activated , */\
- { 0x4ea0, "IPOLSAMMOD"}, /* PolaritySAM Mode activated , */\
- { 0x4eb0, "IPOLTAPMOD"}, /* Polarity Tap Mode Activated , */\
- { 0x4ec0, "IPOLTAPTRG"}, /* PolarityTap Comparator Trigger , */\
- { 0x5001, "BSSCR"}, /* Battery Safeguard attack time , */\
- { 0x5023, "BSST"}, /* Battery Safeguard threshold voltage level , */\
- { 0x5061, "BSSRL"}, /* Battery Safeguard maximum reduction , */\
- { 0x5082, "BSSRR"}, /* Battery Safeguard release time , */\
- { 0x50b1, "BSSHY"}, /* Battery Safeguard hysteresis , */\
- { 0x50d0, "BSSAC"}, /* Reset clipper - Auto clear , */\
- { 0x50e0, "BSSR"}, /* Battery voltage read out , */\
- { 0x50f0, "BSSBY"}, /* Bypass HW clipper , */\
- { 0x5100, "BSSS"}, /* Vbat prot steepness , */\
- { 0x5110, "INTSMUTE"}, /* Soft mute HW , */\
- { 0x5120, "CFSML"}, /* Soft mute FW left , */\
- { 0x5130, "CFSM"}, /* Soft mute FW , */\
- { 0x5140, "HPFBYPL"}, /* Bypass HPF left , */\
- { 0x5150, "HPFBYP"}, /* Bypass HPF , */\
- { 0x5160, "DPSAL"}, /* Enable DPSA left , */\
- { 0x5170, "DPSA"}, /* Enable DPSA , */\
- { 0x5187, "VOL"}, /* FW volume control for primary audio channel , */\
- { 0x5200, "HNDSFRCV"}, /* Selection receiver , */\
- { 0x5222, "CLIPCTRL"}, /* Clip control setting , */\
- { 0x5257, "AMPGAIN"}, /* Amplifier gain , */\
- { 0x52d0, "SLOPEE"}, /* Enables slope control , */\
- { 0x52e0, "SLOPESET"}, /* Slope speed setting (bin. coded) , */\
- { 0x5c07, "CFTAPPAT"}, /* Coolflux tap pattern , */\
- { 0x5c83, "TAPDBGINFO"}, /* Reserved , */\
- { 0x5d0f, "TATPSTAT1"}, /* Tap Status 1 from CF FW , */\
- { 0x5f03, "TCOMPTHR"}, /* Comparator threshold (in uV) , */\
- { 0x6081, "PGAGAIN"}, /* PGA gain selection , */\
- { 0x6123, "TDMSPKG"}, /* System gain (INPLEV 0) , */\
- { 0x6505, "LPM1LVL"}, /* low power mode1 detector ctrl threshold for low_audio_lvl , */\
- { 0x6565, "LPM1HLD"}, /* Low power mode1 detector, ctrl hold time before low audio is reckoned to be low audio, */\
- { 0x65c0, "LPM1DIS"}, /* low power mode1 detector control , */\
- { 0x6630, "DCDIS"}, /* DCDC , */\
- { 0x6801, "TDMSRCMAP"}, /* tdm source mapping , */\
- { 0x6821, "TDMSRCAS"}, /* frame a selection , */\
- { 0x6841, "TDMSRCBS"}, /* frame b selection , */\
- { 0x68a0, "ANC1C"}, /* ANC one s complement , */\
- { 0x6901, "SAMMODE"}, /* Sam mode , */\
- { 0x7033, "DCMCC"}, /* Max coil current , */\
- { 0x7071, "DCCV"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
- { 0x7090, "DCIE"}, /* Adaptive boost mode , */\
- { 0x70a0, "DCSR"}, /* Soft ramp up/down , */\
- { 0x70c1, "DCINSEL"}, /* DCDC IIR input Selection , */\
- { 0x70f0, "DCPWM"}, /* DCDC PWM only mode , */\
- { 0x7504, "DCTRIP"}, /* Adaptive boost trip levels 1, effective only when boost_intelligent is set to 1, */\
- { 0x7554, "DCTRIP2"}, /* Adaptive boost trip level 2, effective only when boost_intelligent is set to 1, */\
- { 0x75a4, "DCTRIPT"}, /* Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
- { 0x7635, "DCVOF"}, /* First boost voltage level , */\
- { 0x7695, "DCVOS"}, /* Second boost voltage level , */\
- { 0x9000, "RST"}, /* Reset , */\
- { 0x9011, "DMEM"}, /* Target memory , */\
- { 0x9030, "AIF"}, /* Auto increment , */\
- { 0x9040, "CFINT"}, /* Interrupt - auto clear , */\
- { 0x9050, "CFCGATE"}, /* Coolflux clock gating disabling control , */\
- { 0x9080, "REQCMD"}, /* Firmware event request rpc command , */\
- { 0x9090, "REQRST"}, /* Firmware event request reset restart , */\
- { 0x90a0, "REQMIPS"}, /* Firmware event request short on mips , */\
- { 0x90b0, "REQMUTED"}, /* Firmware event request mute sequence ready , */\
- { 0x90c0, "REQVOL"}, /* Firmware event request volume ready , */\
- { 0x90d0, "REQDMG"}, /* Firmware event request speaker damage detected , */\
- { 0x90e0, "REQCAL"}, /* Firmware event request calibration completed , */\
- { 0x90f0, "REQRSV"}, /* Firmware event request reserved , */\
- { 0x910f, "MADD"}, /* Memory address , */\
- { 0x920f, "MEMA"}, /* Activate memory access , */\
- { 0x9307, "ERR"}, /* Error flags , */\
- { 0x9380, "ACKCMD"}, /* Firmware event acknowledge rpc command , */\
- { 0x9390, "ACKRST"}, /* Firmware event acknowledge reset restart , */\
- { 0x93a0, "ACKMIPS"}, /* Firmware event acknowledge short on mips , */\
- { 0x93b0, "ACKMUTED"}, /* Firmware event acknowledge mute sequence ready , */\
- { 0x93c0, "ACKVOL"}, /* Firmware event acknowledge volume ready , */\
- { 0x93d0, "ACKDMG"}, /* Firmware event acknowledge speaker damage detected, */\
- { 0x93e0, "ACKCAL"}, /* Firmware event acknowledge calibration completed , */\
- { 0x93f0, "ACKRSV"}, /* Firmware event acknowledge reserved , */\
- { 0xa107, "MTPK"}, /* MTP KEY2 register , */\
- { 0xa200, "KEY1LOCKED"}, /* Indicates KEY1 is locked , */\
- { 0xa210, "KEY2LOCKED"}, /* Indicates KEY2 is locked , */\
- { 0xa360, "CIMTP"}, /* Start copying data from I2C mtp registers to mtp , */\
- { 0xa50f, "MTPRDMSB"}, /* MSB word of MTP manual read data , */\
- { 0xa60f, "MTPRDLSB"}, /* LSB word of MTP manual read data , */\
- { 0xb108, "EXTTS"}, /* External temperature (C) , */\
- { 0xb190, "TROS"}, /* Select temp Speaker calibration , */\
- { 0xee0f, "SWPROFIL"}, /* Software profile data , */\
- { 0xef0f, "SWVSTEP"}, /* Software vstep information , */\
- { 0xf000, "MTPOTC"}, /* Calibration schedule , */\
- { 0xf010, "MTPEX"}, /* Calibration Ron executed , */\
- { 0xf020, "DCMCCAPI"}, /* Calibration current limit DCDC , */\
- { 0xf030, "DCMCCSB"}, /* Sign bit for delta calibration current limit DCDC , */\
- { 0xf042, "DCMCCCL"}, /* Calibration delta current limit DCDC , */\
- { 0xf078, "USERDEF"}, /* Reserved space for allowing customer to store speaker information, */\
- { 0xf40f, "R25C"}, /* Ron resistance of speaker coil , */\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-
-#define TFA9912_BITNAMETABLE static tfaBfName_t Tfa9912BitNames[]= {\
- { 0x0, "powerdown"}, /* Powerdown selection , */\
- { 0x10, "reset"}, /* I2C Reset - Auto clear , */\
- { 0x20, "enbl_coolflux"}, /* Enable CoolFlux , */\
- { 0x30, "enbl_amplifier"}, /* Enables the Amplifier , */\
- { 0x40, "enbl_boost"}, /* Activate DC-to-DC converter , */\
- { 0x50, "coolflux_configured"}, /* Coolflux configured , */\
- { 0x60, "sel_enbl_amplifier"}, /* CoolFlux controls amplifier , */\
- { 0x71, "int_pad_io"}, /* Interrupt config , */\
- { 0x90, "fs_pulse_sel"}, /* Audio sample reference , */\
- { 0xb0, "bypass_ocp"}, /* Bypass OCP , */\
- { 0xc0, "test_ocp"}, /* OCP testing control , */\
- { 0x101, "vamp_sel"}, /* Amplifier input selection , */\
- { 0x120, "src_set_configured"}, /* I2C configured , */\
- { 0x130, "execute_cold_start"}, /* Execute cold start , */\
- { 0x140, "enbl_fro8m_auto_off"}, /* Internal osc off at PWDN , */\
- { 0x150, "man_enbl_brown_out"}, /* Reaction on BOD , */\
- { 0x160, "enbl_bod"}, /* BOD Enable , */\
- { 0x170, "enbl_bod_hyst"}, /* BOD Hysteresis , */\
- { 0x181, "bod_delay"}, /* BOD filter , */\
- { 0x1a1, "bod_lvlsel"}, /* BOD threshold , */\
- { 0x1d0, "disable_mute_time_out"}, /* Time out SB mute sequence , */\
- { 0x1e0, "pwm_sel_rcv_ns"}, /* Noise shaper selection , */\
- { 0x1f0, "man_enbl_watchdog"}, /* Watchdog enable , */\
- { 0x203, "audio_fs"}, /* Sample rate (fs) , */\
- { 0x240, "input_level"}, /* TDM output attenuation , */\
- { 0x255, "cs_frac_delay"}, /* V/I Fractional delay , */\
- { 0x2b0, "bypass_hvbat_filter"}, /* Bypass HVBAT filter , */\
- { 0x2c0, "tdm_tfa9872_compatible"}, /* TDM Compatibility with TFA9872 , */\
- { 0x2d0, "sel_hysteresis"}, /* Select hysteresis for clock range detector , */\
- { 0x2e0, "enbl_adc10"}, /* ADC10 Enable - I2C direct mode , */\
- { 0x30f, "device_rev"}, /* Revision info , */\
- { 0x401, "pll_clkin_sel"}, /* PLL external ref clock , */\
- { 0x420, "pll_clkin_sel_osc"}, /* PLL internal ref clock , */\
- { 0x430, "cf_clock_scaling"}, /* Coolflux DSP clock scaling, low power mode , */\
- { 0x441, "sel_cf_clock"}, /* Coolflux DSP clock scaler selection for low power mode, */\
- { 0x460, "tdm_intf_sel"}, /* TDM clock selection , */\
- { 0x470, "disable_auto_sel_refclk"}, /* Disable Automatic dsp clock source selection , */\
- { 0x480, "sel_clk_src"}, /* I2C selection of DSP clock when auto select is disabled, */\
- { 0x490, "wdt_tim_clk_src"}, /* I2C selection of Watchdog and Timer clock , */\
- { 0x510, "enbl_spkr_ss"}, /* Enable speaker path , */\
- { 0x530, "enbl_volsense"}, /* Voltage sense , */\
- { 0x550, "enbl_cursense"}, /* Current sense , */\
- { 0x560, "enbl_pdm_ss"}, /* Sub-system PDM , */\
- { 0x580, "enbl_pga_chop"}, /* Enable PGA chop clock , */\
- { 0x590, "enbl_tdm_ss"}, /* Sub-system TDM , */\
- { 0x5a0, "enbl_bst_ss"}, /* Sub-system boost , */\
- { 0x5b0, "enbl_adc10_ss"}, /* Sub-system ADC , */\
- { 0x5c0, "enbl_faim_ss"}, /* Sub-system FAIM , */\
- { 0x5d0, "enbl_tim_clk"}, /* CF Sub-system timer , */\
- { 0x5e0, "enbl_wdt_clk"}, /* CF Sub-system WDT , */\
- { 0x5f0, "faim_enable_vbg"}, /* Over rule of vbg for FaIM access , */\
- { 0x600, "aux_spkr_sel"}, /* Input selection for TAP/SAM , */\
- { 0x620, "bypass_tapdec_reset"}, /* Tap decimator reset bypass - Bypass the decimator reset from tapdec, */\
- { 0x631, "car_dec_in_sel0"}, /* Cardec input 0 sel , */\
- { 0x651, "car_dec_in_sel1"}, /* Cardec input sel , */\
- { 0x670, "tapdec_sel"}, /* Select TAP/Cardec for TAP , */\
- { 0x680, "comp_count"}, /* Comparator o/p filter selection , */\
- { 0x691, "startup_mode"}, /* Startup Mode Selection , */\
- { 0x6b0, "enable_auto_tap_switching"}, /* Enable auto tap switching , */\
- { 0x6c1, "comp_init_time"}, /* Comparator initialization time to be used in Tap Machine, */\
- { 0x6e1, "ana_init_time"}, /* Analog initialization time to be used in Tap Machine, */\
- { 0x707, "clkchk_th_hi"}, /* Clock check Higher Threshold , */\
- { 0x787, "clkchk_th_lo"}, /* Clock check Higher Threshold , */\
- { 0x802, "ctrl_on2off_criterion"}, /* Amplifier on-off criteria for shutdown , */\
- { 0x832, "ctrl_on2tap_criterion"}, /* Amplifier on-off criteria for tap mode entry , */\
- { 0xd00, "side_tone_gain_sel"}, /* PDM side tone gain selector , */\
- { 0xd18, "side_tone_gain"}, /* Side tone gain , */\
- { 0xda0, "mute_side_tone"}, /* Side tone soft mute , */\
- { 0xdb0, "side_tone_1scomplement"}, /* side tone one s complement , */\
- { 0xe07, "ctrl_digtoana"}, /* Spare control from digital to analog , */\
- { 0xf0f, "hidden_code"}, /* 5A6Bh, 23147d to access registers (default for engineering), */\
- { 0x1000, "flag_por"}, /* POR , */\
- { 0x1010, "flag_pll_lock"}, /* PLL lock , */\
- { 0x1020, "flag_otpok"}, /* OTP alarm , */\
- { 0x1030, "flag_ovpok"}, /* OVP alarm , */\
- { 0x1040, "flag_uvpok"}, /* UVP alarm , */\
- { 0x1050, "flag_clocks_stable"}, /* Clocks stable , */\
- { 0x1060, "flag_mtp_busy"}, /* MTP busy , */\
- { 0x1070, "flag_lost_clk"}, /* Lost clock , */\
- { 0x1090, "flag_cold_started"}, /* Cold Start , */\
- { 0x10a0, "flag_engage"}, /* Amplifier engage , */\
- { 0x10b0, "flag_watchdog_reset"}, /* Watchdog , */\
- { 0x10c0, "flag_enbl_amp"}, /* Amplifier enable , */\
- { 0x10d0, "flag_enbl_ref"}, /* References enable , */\
- { 0x10e0, "flag_adc10_ready"}, /* Control ADC , */\
- { 0x10f0, "flag_bod_vddd_nok"}, /* BOD , */\
- { 0x1100, "flag_bst_bstcur"}, /* DCDC current limiting , */\
- { 0x1110, "flag_bst_hiz"}, /* DCDC active , */\
- { 0x1120, "flag_bst_ocpok"}, /* DCDC OCP nmos , */\
- { 0x1130, "flag_bst_peakcur"}, /* Indicates current is max in DC-to-DC converter , */\
- { 0x1140, "flag_bst_voutcomp"}, /* DCDC level 1x , */\
- { 0x1150, "flag_bst_voutcomp86"}, /* DCDC level 1.14x , */\
- { 0x1160, "flag_bst_voutcomp93"}, /* DCDC level 1.07x , */\
- { 0x1170, "flag_soft_mute_busy"}, /* side tone (un)mute busy , */\
- { 0x1180, "flag_soft_mute_state"}, /* side tone mute state , */\
- { 0x1190, "flag_tdm_lut_error"}, /* TDM LUT error , */\
- { 0x11a2, "flag_tdm_status"}, /* TDM status bits , */\
- { 0x11d0, "flag_tdm_error"}, /* TDM error , */\
- { 0x1300, "flag_ocpokap"}, /* OCPOK pmos A , */\
- { 0x1310, "flag_ocpokan"}, /* OCPOK nmos A , */\
- { 0x1320, "flag_ocpokbp"}, /* OCPOK pmos B , */\
- { 0x1330, "flag_ocpokbn"}, /* OCPOK nmos B , */\
- { 0x1340, "flag_clipa_high"}, /* Clipping A to Vddp , */\
- { 0x1350, "flag_clipa_low"}, /* Clipping A to gnd , */\
- { 0x1360, "flag_clipb_high"}, /* Clipping B to Vddp , */\
- { 0x1370, "flag_clipb_low"}, /* Clipping B to gnd , */\
- { 0x1380, "flag_ocp_alarm"}, /* OCP amplifier , */\
- { 0x1390, "flag_clip"}, /* Amplifier clipping , */\
- { 0x13a0, "flag_tap_comp_trig"}, /* Status Tap comparator triggered , */\
- { 0x13b0, "flag_cf_tapdetected"}, /* Status Tap detected , */\
- { 0x13c0, "flag_man_wait_src_settings"}, /* Wait HW I2C settings , */\
- { 0x13d0, "flag_man_wait_cf_config"}, /* Wait CF config , */\
- { 0x13e0, "flag_man_start_mute_audio"}, /* Audio mute sequence , */\
- { 0x1410, "flag_cf_speakererror"}, /* Speaker status , */\
- { 0x1420, "flag_clk_out_of_range"}, /* External clock status , */\
- { 0x1433, "man_state"}, /* Device manager status , */\
- { 0x1471, "status_bst_mode"}, /* DCDC mode status bits , */\
- { 0x1490, "man_dsp_clk_src"}, /* DSP clock source selected by manager , */\
- { 0x14a1, "man_startup_mode"}, /* Startup Mode Selected by Manager(Read Only) , */\
- { 0x14c3, "tap_machine_state"}, /* Tap Machine State , */\
- { 0x1509, "bat_adc"}, /* Battery voltage (V) , */\
- { 0x1608, "temp_adc"}, /* IC Temperature (C) , */\
- { 0x1709, "vddp_adc"}, /* IC VDDP voltage ( 1023*VDDP/13 V) , */\
- { 0x17a0, "flag_bst_bstcur_cf"}, /* DCDC current limiting for DSP , */\
- { 0x2000, "tdm_usecase"}, /* Mode setting , */\
- { 0x2011, "dio4_input_sel"}, /* DIO4 Input selection , */\
- { 0x2040, "tdm_enable"}, /* Enable TDM interface , */\
- { 0x2060, "tdm_clk_inversion"}, /* Reception data to BCK clock , */\
- { 0x2073, "tdm_fs_ws_length"}, /* FS length , */\
- { 0x20b0, "tdm_fs_ws_polarity"}, /* FS polarity , */\
- { 0x20c3, "tdm_nbck"}, /* N-BCK's in FS , */\
- { 0x2103, "tdm_nb_of_slots"}, /* N-slots in Frame , */\
- { 0x2144, "tdm_slot_length"}, /* N-bits in slot , */\
- { 0x2194, "tdm_bits_remaining"}, /* N-bits remaining , */\
- { 0x21e0, "tdm_data_delay"}, /* data delay to FS , */\
- { 0x21f0, "tdm_data_adjustment"}, /* data adjustment , */\
- { 0x2201, "tdm_audio_sample_compression"}, /* Received audio compression , */\
- { 0x2224, "tdm_sample_size"}, /* Sample size per slot , */\
- { 0x2271, "tdm_txdata_format"}, /* Format unused bits in a slot , */\
- { 0x2291, "tdm_txdata_format_unused_slot_sd0"}, /* Format unused slots GAINIO , */\
- { 0x22b1, "tdm_txdata_format_unused_slot_sd1"}, /* Format unused slots DIO1 , */\
- { 0x22d1, "tdm_txdata_format_unused_slot_sd2"}, /* Format unused slots DIO2 , */\
- { 0x2300, "tdm_sink0_enable"}, /* Control gain (channel in 0) , */\
- { 0x2310, "tdm_sink1_enable"}, /* Control audio left (channel in 1 ) , */\
- { 0x2320, "tdm_sink2_enable"}, /* Control audio right (channel in 2 ) , */\
- { 0x2330, "tdm_source0_enable"}, /* Current sense , */\
- { 0x2340, "tdm_source1_enable"}, /* Voltage sense , */\
- { 0x2350, "tdm_source2_enable"}, /* DSP Gainout , */\
- { 0x2360, "tdm_source3_enable"}, /* DSP 2 , */\
- { 0x2370, "tdm_source4_enable"}, /* DSP 3 , */\
- { 0x2380, "tdm_source5_enable"}, /* DSP , */\
- { 0x2390, "tdm_source6_enable"}, /* Loopback of Audio left (channel 1) , */\
- { 0x23a0, "tdm_source7_enable"}, /* Loopback of Audio right (channel 2) , */\
- { 0x2401, "tdm_sink0_io"}, /* IO gainin , */\
- { 0x2421, "tdm_sink1_io"}, /* IO audio left , */\
- { 0x2441, "tdm_sink2_io"}, /* IO audio right , */\
- { 0x2461, "tdm_source0_io"}, /* IO Current Sense , */\
- { 0x2481, "tdm_source1_io"}, /* IO voltage sense , */\
- { 0x24a1, "tdm_source2_io"}, /* IO gain out , */\
- { 0x24c1, "tdm_source3_io"}, /* IO DSP 2 , */\
- { 0x24e1, "tdm_source4_io"}, /* IO DSP 3 , */\
- { 0x2501, "tdm_source5_io"}, /* IO DSP , */\
- { 0x2521, "tdm_source6_io"}, /* IO Source 6 , */\
- { 0x2541, "tdm_source7_io"}, /* IO Source 7 , */\
- { 0x2603, "tdm_sink0_slot"}, /* Control gainin , */\
- { 0x2643, "tdm_sink1_slot"}, /* tdm slot for audio left (channel 1) , */\
- { 0x2683, "tdm_sink2_slot"}, /* tdm slot for audio right (channel 2) , */\
- { 0x26c3, "tdm_source0_slot"}, /* Slot Position of Current Sense Out , */\
- { 0x2703, "tdm_source1_slot"}, /* Slot Position of Voltage sense , */\
- { 0x2743, "tdm_source2_slot"}, /* Slot Position of GAIN out , */\
- { 0x2783, "tdm_source3_slot"}, /* Slot Position DSPout2 , */\
- { 0x27c3, "tdm_source4_slot"}, /* Slot Position DSPout3 , */\
- { 0x2803, "tdm_source5_slot"}, /* Slot Position of DSPout , */\
- { 0x2843, "tdm_source6_slot"}, /* Slot Position of loopback channel left , */\
- { 0x2883, "tdm_source7_slot"}, /* Slot Position of loopback channel right , */\
- { 0x2901, "tdm_txdata_format_unused_slot_sd3"}, /* Format unused slots D3 , */\
- { 0x3100, "pdm_mode"}, /* PDM control , */\
- { 0x3110, "pdm_input_sel"}, /* PDM Decimator input selection , */\
- { 0x3120, "enbl_pdm_side_tone"}, /* Side tone input enable , */\
- { 0x3201, "pdm_nbck"}, /* PDM BCK/Fs ratio , */\
- { 0x4000, "int_out_flag_por"}, /* Status POR , */\
- { 0x4010, "int_out_flag_pll_lock"}, /* Status PLL lock , */\
- { 0x4020, "int_out_flag_otpok"}, /* Status OTP alarm , */\
- { 0x4030, "int_out_flag_ovpok"}, /* Status OVP alarm , */\
- { 0x4040, "int_out_flag_uvpok"}, /* Status UVP alarm , */\
- { 0x4050, "int_out_flag_clocks_stable"}, /* Status clocks stable , */\
- { 0x4060, "int_out_flag_mtp_busy"}, /* Status MTP busy , */\
- { 0x4070, "int_out_flag_lost_clk"}, /* Status lost clock , */\
- { 0x4080, "int_out_flag_cf_speakererror"}, /* Status speaker error , */\
- { 0x4090, "int_out_flag_cold_started"}, /* Status cold start , */\
- { 0x40a0, "int_out_flag_engage"}, /* Status amplifier engage , */\
- { 0x40b0, "int_out_flag_watchdog_reset"}, /* Status watchdog , */\
- { 0x40c0, "int_out_flag_enbl_amp"}, /* Status amplifier enable , */\
- { 0x40d0, "int_out_flag_enbl_ref"}, /* Status Ref enable , */\
- { 0x40e0, "int_out_flag_adc10_ready"}, /* Status Control ADC , */\
- { 0x40f0, "int_out_flag_bod_vddd_nok"}, /* Status BOD , */\
- { 0x4100, "int_out_flag_bst_bstcur"}, /* Status DCDC current limiting , */\
- { 0x4110, "int_out_flag_bst_hiz"}, /* Status DCDC active , */\
- { 0x4120, "int_out_flag_bst_ocpok"}, /* Status DCDC OCP , */\
- { 0x4130, "int_out_flag_bst_peakcur"}, /* Status bst peakcur , */\
- { 0x4140, "int_out_flag_bst_voutcomp"}, /* Status DCDC level 1x , */\
- { 0x4150, "int_out_flag_bst_voutcomp86"}, /* Status DCDC level 1.14x , */\
- { 0x4160, "int_out_flag_bst_voutcomp93"}, /* Status DCDC level 1.07x , */\
- { 0x4190, "int_out_flag_ocp_alarm"}, /* Status ocp alarm , */\
- { 0x41a0, "int_out_flag_man_wait_src_settings"}, /* Status Waits HW I2C settings , */\
- { 0x41b0, "int_out_flag_man_wait_cf_config"}, /* Status waits CF config , */\
- { 0x41c0, "int_out_flag_man_start_mute_audio"}, /* Status Audio mute sequence , */\
- { 0x41d0, "int_out_flag_cfma_err"}, /* Status cfma error , */\
- { 0x41e0, "int_out_flag_cfma_ack"}, /* Status cfma ack , */\
- { 0x41f0, "int_out_flag_clk_out_of_range"}, /* Status flag_clk_out_of_range , */\
- { 0x4200, "int_out_flag_tdm_error"}, /* Status tdm error , */\
- { 0x4220, "int_out_flag_clip"}, /* Status clip , */\
- { 0x4250, "int_out_flag_lp_detect_mode1"}, /* Status low power mode1 , */\
- { 0x4260, "int_out_flag_low_amplitude"}, /* Status low amplitude detection , */\
- { 0x4270, "int_out_flag_vddp_gt_vbat"}, /* Status VDDP greater than VBAT , */\
- { 0x4280, "int_out_newtap"}, /* Status Tap detected , */\
- { 0x4290, "int_out_audiomodeactive"}, /* Status Audio Mode activated , */\
- { 0x42a0, "int_out_sammodeactive"}, /* Status SAM Mode activated , */\
- { 0x42b0, "int_out_tapmodeactive"}, /* Status Tap Mode Activated , */\
- { 0x42c0, "int_out_flag_tap_comp_trig"}, /* Status Tap comparator triggered , */\
- { 0x4400, "int_in_flag_por"}, /* Clear POR , */\
- { 0x4410, "int_in_flag_pll_lock"}, /* Clear PLL lock , */\
- { 0x4420, "int_in_flag_otpok"}, /* Clear OTP alarm , */\
- { 0x4430, "int_in_flag_ovpok"}, /* Clear OVP alarm , */\
- { 0x4440, "int_in_flag_uvpok"}, /* Clear UVP alarm , */\
- { 0x4450, "int_in_flag_clocks_stable"}, /* Clear clocks stable , */\
- { 0x4460, "int_in_flag_mtp_busy"}, /* Clear mtp busy , */\
- { 0x4470, "int_in_flag_lost_clk"}, /* Clear lost clk , */\
- { 0x4480, "int_in_flag_cf_speakererror"}, /* Clear speaker error , */\
- { 0x4490, "int_in_flag_cold_started"}, /* Clear cold started , */\
- { 0x44a0, "int_in_flag_engage"}, /* Clear amplifier engage , */\
- { 0x44b0, "int_in_flag_watchdog_reset"}, /* Clear watchdog , */\
- { 0x44c0, "int_in_flag_enbl_amp"}, /* Clear enbl amp , */\
- { 0x44d0, "int_in_flag_enbl_ref"}, /* Clear ref enable , */\
- { 0x44e0, "int_in_flag_adc10_ready"}, /* Clear control ADC , */\
- { 0x44f0, "int_in_flag_bod_vddd_nok"}, /* Clear BOD , */\
- { 0x4500, "int_in_flag_bst_bstcur"}, /* Clear DCDC current limiting , */\
- { 0x4510, "int_in_flag_bst_hiz"}, /* Clear DCDC active , */\
- { 0x4520, "int_in_flag_bst_ocpok"}, /* Clear DCDC OCP , */\
- { 0x4530, "int_in_flag_bst_peakcur"}, /* Clear bst peakcur , */\
- { 0x4540, "int_in_flag_bst_voutcomp"}, /* Clear DCDC level 1x , */\
- { 0x4550, "int_in_flag_bst_voutcomp86"}, /* Clear DCDC level 1.14x , */\
- { 0x4560, "int_in_flag_bst_voutcomp93"}, /* Clear DCDC level 1.07x , */\
- { 0x4590, "int_in_flag_ocp_alarm"}, /* Clear ocp alarm , */\
- { 0x45a0, "int_in_flag_man_wait_src_settings"}, /* Clear wait HW I2C settings , */\
- { 0x45b0, "int_in_flag_man_wait_cf_config"}, /* Clear wait cf config , */\
- { 0x45c0, "int_in_flag_man_start_mute_audio"}, /* Clear audio mute sequence , */\
- { 0x45d0, "int_in_flag_cfma_err"}, /* Clear cfma err , */\
- { 0x45e0, "int_in_flag_cfma_ack"}, /* Clear cfma ack , */\
- { 0x45f0, "int_in_flag_clk_out_of_range"}, /* Clear flag_clk_out_of_range , */\
- { 0x4600, "int_in_flag_tdm_error"}, /* Clear tdm error , */\
- { 0x4620, "int_in_flag_clip"}, /* Clear clip , */\
- { 0x4650, "int_in_flag_lp_detect_mode1"}, /* Clear low power mode1 , */\
- { 0x4660, "int_in_flag_low_amplitude"}, /* Clear low amplitude detection , */\
- { 0x4670, "int_in_flag_vddp_gt_vbat"}, /* Clear VDDP greater then VBAT , */\
- { 0x4680, "int_in_newtap"}, /* Clear Tap detected , */\
- { 0x4690, "int_in_audiomodeactive"}, /* Clear Audio Mode activated , */\
- { 0x46a0, "int_in_sammodeactive"}, /* Clear SAM Mode activated , */\
- { 0x46b0, "int_in_tapmodeactive"}, /* Clear Tap Mode Activated , */\
- { 0x46c0, "int_in_flag_tap_comp_trig"}, /* Clear Comparator Interrupt , */\
- { 0x4800, "int_enable_flag_por"}, /* Enable por , */\
- { 0x4810, "int_enable_flag_pll_lock"}, /* Enable pll lock , */\
- { 0x4820, "int_enable_flag_otpok"}, /* Enable OTP alarm , */\
- { 0x4830, "int_enable_flag_ovpok"}, /* Enable OVP alarm , */\
- { 0x4840, "int_enable_flag_uvpok"}, /* Enable UVP alarm , */\
- { 0x4850, "int_enable_flag_clocks_stable"}, /* Enable clocks stable , */\
- { 0x4860, "int_enable_flag_mtp_busy"}, /* Enable mtp busy , */\
- { 0x4870, "int_enable_flag_lost_clk"}, /* Enable lost clk , */\
- { 0x4880, "int_enable_flag_cf_speakererror"}, /* Enable speaker error , */\
- { 0x4890, "int_enable_flag_cold_started"}, /* Enable cold started , */\
- { 0x48a0, "int_enable_flag_engage"}, /* Enable amplifier engage , */\
- { 0x48b0, "int_enable_flag_watchdog_reset"}, /* Enable watchdog , */\
- { 0x48c0, "int_enable_flag_enbl_amp"}, /* Enable enbl amp , */\
- { 0x48d0, "int_enable_flag_enbl_ref"}, /* Enable ref enable , */\
- { 0x48e0, "int_enable_flag_adc10_ready"}, /* Enable Control ADC , */\
- { 0x48f0, "int_enable_flag_bod_vddd_nok"}, /* Enable BOD , */\
- { 0x4900, "int_enable_flag_bst_bstcur"}, /* Enable DCDC current limiting , */\
- { 0x4910, "int_enable_flag_bst_hiz"}, /* Enable DCDC active , */\
- { 0x4920, "int_enable_flag_bst_ocpok"}, /* Enable DCDC OCP , */\
- { 0x4930, "int_enable_flag_bst_peakcur"}, /* Enable bst peakcur , */\
- { 0x4940, "int_enable_flag_bst_voutcomp"}, /* Enable DCDC level 1x , */\
- { 0x4950, "int_enable_flag_bst_voutcomp86"}, /* Enable DCDC level 1.14x , */\
- { 0x4960, "int_enable_flag_bst_voutcomp93"}, /* Enable DCDC level 1.07x , */\
- { 0x4990, "int_enable_flag_ocp_alarm"}, /* Enable ocp alarm , */\
- { 0x49a0, "int_enable_flag_man_wait_src_settings"}, /* Enable waits HW I2C settings , */\
- { 0x49b0, "int_enable_flag_man_wait_cf_config"}, /* Enable man wait cf config , */\
- { 0x49c0, "int_enable_flag_man_start_mute_audio"}, /* Enable man Audio mute sequence , */\
- { 0x49d0, "int_enable_flag_cfma_err"}, /* Enable cfma err , */\
- { 0x49e0, "int_enable_flag_cfma_ack"}, /* Enable cfma ack , */\
- { 0x49f0, "int_enable_flag_clk_out_of_range"}, /* Enable flag_clk_out_of_range , */\
- { 0x4a00, "int_enable_flag_tdm_error"}, /* Enable tdm error , */\
- { 0x4a20, "int_enable_flag_clip"}, /* Enable clip , */\
- { 0x4a50, "int_enable_flag_lp_detect_mode1"}, /* Enable low power mode1 , */\
- { 0x4a60, "int_enable_flag_low_amplitude"}, /* Enable low amplitude detection , */\
- { 0x4a70, "int_enable_flag_vddp_gt_vbat"}, /* Enable VDDP greater than VBAT , */\
- { 0x4a80, "int_enable_newtap"}, /* Enable Tap detected , */\
- { 0x4a90, "int_enable_audiomodeactive"}, /* Enable Audio Mode activated , */\
- { 0x4aa0, "int_enable_sammodeactive"}, /* Enable SAM Mode activated , */\
- { 0x4ab0, "int_enable_tapmodeactive"}, /* Enable Tap Mode Activated , */\
- { 0x4ac0, "int_enable_flag_tap_comp_trig"}, /* Enable comparator interrupt , */\
- { 0x4c00, "int_polarity_flag_por"}, /* Polarity por , */\
- { 0x4c10, "int_polarity_flag_pll_lock"}, /* Polarity pll lock , */\
- { 0x4c20, "int_polarity_flag_otpok"}, /* Polarity OTP alarm , */\
- { 0x4c30, "int_polarity_flag_ovpok"}, /* Polarity OVP alarm , */\
- { 0x4c40, "int_polarity_flag_uvpok"}, /* Polarity UVP alarm , */\
- { 0x4c50, "int_polarity_flag_clocks_stable"}, /* Polarity clocks stable , */\
- { 0x4c60, "int_polarity_flag_mtp_busy"}, /* Polarity mtp busy , */\
- { 0x4c70, "int_polarity_flag_lost_clk"}, /* Polarity lost clk , */\
- { 0x4c80, "int_polarity_flag_cf_speakererror"}, /* Polarity speaker error , */\
- { 0x4c90, "int_polarity_flag_cold_started"}, /* Polarity cold started , */\
- { 0x4ca0, "int_polarity_flag_engage"}, /* Polarity amplifier engage , */\
- { 0x4cb0, "int_polarity_flag_watchdog_reset"}, /* Polarity watchdog , */\
- { 0x4cc0, "int_polarity_flag_enbl_amp"}, /* Polarity enbl amp , */\
- { 0x4cd0, "int_polarity_flag_enbl_ref"}, /* Polarity ref enable , */\
- { 0x4ce0, "int_polarity_flag_adc10_ready"}, /* Polarity Control ADC , */\
- { 0x4cf0, "int_polarity_flag_bod_vddd_nok"}, /* Polarity BOD , */\
- { 0x4d00, "int_polarity_flag_bst_bstcur"}, /* Polarity DCDC current limiting , */\
- { 0x4d10, "int_polarity_flag_bst_hiz"}, /* Polarity DCDC active , */\
- { 0x4d20, "int_polarity_flag_bst_ocpok"}, /* Polarity DCDC OCP , */\
- { 0x4d30, "int_polarity_flag_bst_peakcur"}, /* Polarity bst peakcur , */\
- { 0x4d40, "int_polarity_flag_bst_voutcomp"}, /* Polarity DCDC level 1x , */\
- { 0x4d50, "int_polarity_flag_bst_voutcomp86"}, /* Polarity DCDC level 1.14x , */\
- { 0x4d60, "int_polarity_flag_bst_voutcomp93"}, /* Polarity DCDC level 1.07x , */\
- { 0x4d90, "int_polarity_flag_ocp_alarm"}, /* Polarity ocp alarm , */\
- { 0x4da0, "int_polarity_flag_man_wait_src_settings"}, /* Polarity waits HW I2C settings , */\
- { 0x4db0, "int_polarity_flag_man_wait_cf_config"}, /* Polarity man wait cf config , */\
- { 0x4dc0, "int_polarity_flag_man_start_mute_audio"}, /* Polarity man audio mute sequence , */\
- { 0x4dd0, "int_polarity_flag_cfma_err"}, /* Polarity cfma err , */\
- { 0x4de0, "int_polarity_flag_cfma_ack"}, /* Polarity cfma ack , */\
- { 0x4df0, "int_polarity_flag_clk_out_of_range"}, /* Polarity flag_clk_out_of_range , */\
- { 0x4e00, "int_polarity_flag_tdm_error"}, /* Polarity tdm error , */\
- { 0x4e20, "int_polarity_flag_clip"}, /* Polarity clip , */\
- { 0x4e50, "int_polarity_flag_lp_detect_mode1"}, /* Polarity low power mode1 , */\
- { 0x4e60, "int_polarity_flag_low_amplitude"}, /* Polarity low amplitude detection , */\
- { 0x4e70, "int_polarity_flag_vddp_gt_vbat"}, /* Polarity VDDP greater than VBAT , */\
- { 0x4e80, "int_polarity_newtap"}, /* PolarityTap detected , */\
- { 0x4e90, "int_polarity_audiomodeactive"}, /* PolarityAudio Mode activated , */\
- { 0x4ea0, "int_polarity_sammodeactive"}, /* PolaritySAM Mode activated , */\
- { 0x4eb0, "int_polarity_tapmodeactive"}, /* Polarity Tap Mode Activated , */\
- { 0x4ec0, "int_polarity_flag_tap_comp_trig"}, /* PolarityTap Comparator Trigger , */\
- { 0x5001, "vbat_prot_attack_time"}, /* Battery Safeguard attack time , */\
- { 0x5023, "vbat_prot_thlevel"}, /* Battery Safeguard threshold voltage level , */\
- { 0x5061, "vbat_prot_max_reduct"}, /* Battery Safeguard maximum reduction , */\
- { 0x5082, "vbat_prot_release_time"}, /* Battery Safeguard release time , */\
- { 0x50b1, "vbat_prot_hysterese"}, /* Battery Safeguard hysteresis , */\
- { 0x50d0, "rst_min_vbat"}, /* Reset clipper - Auto clear , */\
- { 0x50e0, "sel_vbat"}, /* Battery voltage read out , */\
- { 0x50f0, "bypass_clipper"}, /* Bypass HW clipper , */\
- { 0x5100, "batsense_steepness"}, /* Vbat prot steepness , */\
- { 0x5110, "soft_mute"}, /* Soft mute HW , */\
- { 0x5130, "cf_mute"}, /* Soft mute FW , */\
- { 0x5150, "bypass_hp"}, /* Bypass HPF , */\
- { 0x5170, "enbl_dpsa"}, /* Enable DPSA , */\
- { 0x5187, "cf_volume"}, /* FW volume control for primary audio channel , */\
- { 0x5222, "ctrl_cc"}, /* Clip control setting , */\
- { 0x5257, "gain"}, /* Amplifier gain , */\
- { 0x52d0, "ctrl_slopectrl"}, /* Enables slope control , */\
- { 0x52e0, "ctrl_slope"}, /* Slope speed setting (bin. coded) , */\
- { 0x5301, "dpsa_level"}, /* DPSA threshold levels , */\
- { 0x5321, "dpsa_release"}, /* DPSA Release time , */\
- { 0x5340, "clipfast"}, /* Clock selection for HW clipper for Battery Safeguard, */\
- { 0x5350, "bypass_lp"}, /* Bypass the low power filter inside temperature sensor, */\
- { 0x5360, "enbl_low_latency"}, /* CF low latency outputs for add module , */\
- { 0x5400, "first_order_mode"}, /* Overrule to 1st order mode of control stage when clipping, */\
- { 0x5410, "bypass_ctrlloop"}, /* Switch amplifier into open loop configuration , */\
- { 0x5430, "icomp_engage"}, /* Engage of icomp , */\
- { 0x5440, "ctrl_kickback"}, /* Prevent double pulses of output stage , */\
- { 0x5450, "icomp_engage_overrule"}, /* To overrule the functional icomp_engage signal during validation, */\
- { 0x5503, "ctrl_dem"}, /* Enable DEM icomp and DEM one bit dac , */\
- { 0x5543, "ctrl_dem_mismatch"}, /* Enable DEM icomp mismatch for testing , */\
- { 0x5582, "dpsa_drive"}, /* Drive setting (bin. coded) - I2C direct mode , */\
- { 0x570a, "enbl_amp"}, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually , */\
- { 0x57b0, "enbl_engage"}, /* Enables/engage power stage and control loop - I2C direct mode, */\
- { 0x57c0, "enbl_engage_pst"}, /* Enables/engage power stage and control loop , */\
- { 0x5810, "hard_mute"}, /* Hard mute - PWM , */\
- { 0x5820, "pwm_shape"}, /* PWM shape , */\
- { 0x5844, "pwm_delay"}, /* PWM delay bits to set the delay, clock is 1/(k*2048*fs), */\
- { 0x5890, "reclock_pwm"}, /* Reclock the pwm signal inside analog , */\
- { 0x58a0, "reclock_voltsense"}, /* Reclock the voltage sense pwm signal , */\
- { 0x58c0, "enbl_pwm_phase_shift"}, /* Control for pwm phase shift , */\
- { 0x5c07, "flag_cf_tap_pattern"}, /* Coolflux tap pattern , */\
- { 0x5c83, "tap_debug_info"}, /* Reserved , */\
- { 0x5d0f, "tap_status_1"}, /* Tap Status 1 from CF FW , */\
- { 0x5f03, "tap_comp_threshold"}, /* Comparator threshold (in uV) , */\
- { 0x6081, "pga_gain_set"}, /* PGA gain selection , */\
- { 0x60b0, "pga_lowpass_enable"}, /* Lowpass enable , */\
- { 0x60c0, "pga_pwr_enable"}, /* PGA power enable , */\
- { 0x60d0, "pga_switch_enable"}, /* PGA switch enable , */\
- { 0x60e0, "pga_switch_aux_enable"}, /* Switch enable aux , */\
- { 0x6123, "ctrl_att"}, /* System gain (INPLEV 0) , */\
- { 0x6265, "zero_lvl"}, /* ctrl threshold for zero X-ing , */\
- { 0x62c1, "ctrl_fb_resistor"}, /* Select amplifier feedback resistor connection , */\
- { 0x62e1, "lownoisegain_mode"}, /* ctrl select mode , */\
- { 0x6305, "threshold_lvl"}, /* ctrl threshold for low_audio_lvl , */\
- { 0x6365, "hold_time"}, /* ctrl hold time before low audio is reckoned to be low audio, */\
- { 0x6405, "lpm1_cal_offset"}, /* low power mode1 detector ctrl cal_offset from gain module , */\
- { 0x6465, "lpm1_zero_lvl"}, /* low power mode1 detector ctrl threshold for zero X-ing , */\
- { 0x64e1, "lpm1_mode"}, /* low power mode1 detector ctrl select mode , */\
- { 0x6505, "lpm1_threshold_lvl"}, /* low power mode1 detector ctrl threshold for low_audio_lvl , */\
- { 0x6565, "lpm1_hold_time"}, /* Low power mode1 detector, ctrl hold time before low audio is reckoned to be low audio, */\
- { 0x65c0, "disable_low_power_mode"}, /* low power mode1 detector control , */\
- { 0x6600, "dcdc_pfm20khz_limit"}, /* DCDC in PFM mode pwm mode is activated each 50us to force a pwm pulse, */\
- { 0x6611, "dcdc_ctrl_maxzercnt"}, /* DCDC. Number of zero current flags to count before going to pfm mode, */\
- { 0x6630, "dcdcoff_mode"}, /* DCDC , */\
- { 0x6656, "dcdc_vbat_delta_detect"}, /* Threshold before booster is reacting on a delta Vbat (in PFM mode) by temporarily switching to PWM mode, */\
- { 0x66c0, "dcdc_ignore_vbat"}, /* Ignore an increase on Vbat , */\
- { 0x6700, "enbl_minion"}, /* Enables minion (small) power stage - direct ctrl , */\
- { 0x6713, "vth_vddpvbat"}, /* select vddp-vbat thres signal , */\
- { 0x6750, "lpen_vddpvbat"}, /* select vddp-vbat filtered vs unfiltered compare , */\
- { 0x6761, "ctrl_rfb"}, /* Feedback resistor selection - I2C direct mode , */\
- { 0x6801, "tdm_source_mapping"}, /* tdm source mapping , */\
- { 0x6821, "tdm_sourcea_frame_sel"}, /* frame a selection , */\
- { 0x6841, "tdm_sourceb_frame_sel"}, /* frame b selection , */\
- { 0x6901, "sam_mode"}, /* Sam mode , */\
- { 0x6931, "pdmdat_h_sel"}, /* pdm out value when pdm_clk is higth , */\
- { 0x6951, "pdmdat_l_sel"}, /* pdm out value when pdm_clk is low , */\
- { 0x6970, "cs_sam_set"}, /* Enable SAM input for current sense - I2C Direct Mode, */\
- { 0x6980, "cs_adc_nortz"}, /* Return to zero for current sense ADC , */\
- { 0x6990, "sam_spkr_sel"}, /* SAM o/p sel during SAM and audio , */\
- { 0x6b00, "disable_engage"}, /* Disable auto engage , */\
- { 0x6c02, "ns_hp2ln_criterion"}, /* 0..7 zeroes at ns as threshold to swap from high_power to low_noise, */\
- { 0x6c32, "ns_ln2hp_criterion"}, /* 0..7 zeroes at ns as threshold to swap from low_noise to high_power, */\
- { 0x6c60, "sel_clip_pwms"}, /* To select clip-flags , */\
- { 0x6c72, "pwms_clip_lvl"}, /* To set the amount of pwm pulse that may be skipped before clip-flag is triggered. , */\
- { 0x6ca5, "spare_out"}, /* spare_out , */\
- { 0x6d0f, "spare_in"}, /* spare_in , */\
- { 0x6e10, "flag_lp_detect_mode1"}, /* low power mode 1 detection , */\
- { 0x6e20, "flag_low_amplitude"}, /* low amplitude detection , */\
- { 0x6e30, "flag_vddp_gt_vbat"}, /* vddp greater than vbat , */\
- { 0x7033, "boost_cur"}, /* Max coil current , */\
- { 0x7071, "bst_slpcmplvl"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
- { 0x7090, "boost_intel"}, /* Adaptive boost mode , */\
- { 0x70a0, "boost_speed"}, /* Soft ramp up/down , */\
- { 0x70c1, "dcdc_sel"}, /* DCDC IIR input Selection , */\
- { 0x70f0, "dcdc_pwmonly"}, /* DCDC PWM only mode , */\
- { 0x7104, "bst_drive"}, /* Binary coded drive setting for boost converter power stage, */\
- { 0x7151, "bst_scalecur"}, /* For testing direct control scale current , */\
- { 0x7174, "bst_slopecur"}, /* For testing direct control slope current - I2C direct mode, */\
- { 0x71c1, "bst_slope"}, /* Boost slope speed , */\
- { 0x71e0, "bst_bypass_bstcur"}, /* Bypass control for boost current settings , */\
- { 0x71f0, "bst_bypass_bstfoldback"}, /* Bypass control for boost foldback , */\
- { 0x7200, "enbl_bst_engage"}, /* Enable power stage dcdc controller - I2C direct mode, */\
- { 0x7210, "enbl_bst_hizcom"}, /* Enable hiz comparator - I2C direct mode , */\
- { 0x7220, "enbl_bst_peak2avg"}, /* Enable boost peak2avg functionality , */\
- { 0x7230, "enbl_bst_peakcur"}, /* Enable peak current - I2C direct mode , */\
- { 0x7240, "enbl_bst_power"}, /* Enable line of the powerstage - I2C direct mode , */\
- { 0x7250, "enbl_bst_slopecur"}, /* Enable bit of max-current dac - I2C direct mode , */\
- { 0x7260, "enbl_bst_voutcomp"}, /* Enable vout comparators - I2C direct mode , */\
- { 0x7270, "enbl_bst_voutcomp86"}, /* Enable vout-86 comparators - I2C direct mode , */\
- { 0x7280, "enbl_bst_voutcomp93"}, /* Enable vout-93 comparators - I2C direct mode , */\
- { 0x7290, "enbl_bst_windac"}, /* Enable window dac - I2C direct mode , */\
- { 0x72a5, "bst_windac"}, /* for testing direct control windac - I2C direct mode, */\
- { 0x7300, "boost_alg"}, /* Control for boost adaptive loop gain , */\
- { 0x7311, "boost_loopgain"}, /* DCDC boost loopgain setting , */\
- { 0x7331, "bst_freq"}, /* DCDC boost frequency control , */\
- { 0x7430, "boost_track"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
- { 0x7494, "boost_hold_time"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
- { 0x74e0, "sel_dcdc_envelope_8fs"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
- { 0x74f0, "ignore_flag_voutcomp86"}, /* Ignore flag_voutcomp86 , */\
- { 0x7504, "boost_trip_lvl_1st"}, /* Adaptive boost trip levels 1, effective only when boost_intelligent is set to 1, */\
- { 0x7554, "boost_trip_lvl_2nd"}, /* Adaptive boost trip level 2, effective only when boost_intelligent is set to 1, */\
- { 0x75a4, "boost_trip_lvl_track"}, /* Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
- { 0x7602, "track_decay"}, /* DCDC Boost decay speed after a peak value, effective only when boost_track is set to 1, */\
- { 0x7635, "frst_boost_voltage"}, /* First boost voltage level , */\
- { 0x7695, "scnd_boost_voltage"}, /* Second boost voltage level , */\
- { 0x7720, "pga_test_ldo_bypass"}, /* bypass internal PGA LDO , */\
- { 0x8001, "sel_clk_cs"}, /* Current sense clock duty cycle control , */\
- { 0x8021, "micadc_speed"}, /* Current sense clock for MiCADC selection - 32/44.1/48 KHz Fs band only, */\
- { 0x8050, "cs_gain_control"}, /* Current sense gain control , */\
- { 0x8060, "cs_bypass_gc"}, /* Bypasses the CS gain correction , */\
- { 0x8087, "cs_gain"}, /* Current sense gain , */\
- { 0x8200, "enbl_cmfb"}, /* Current sense common mode feedback control , */\
- { 0x8210, "invertpwm"}, /* Current sense common mode feedback pwm invert control, */\
- { 0x8222, "cmfb_gain"}, /* Current sense common mode feedback control gain , */\
- { 0x8256, "cmfb_offset"}, /* Current sense common mode feedback control offset , */\
- { 0x8305, "cs_ktemp"}, /* First order temperature compensation coefficient , */\
- { 0x8364, "cs_ktemp2"}, /* Second order temperature compensation coefficient , */\
- { 0x8400, "cs_adc_bsoinv"}, /* Bitstream inversion for current sense ADC , */\
- { 0x8421, "cs_adc_hifreq"}, /* Frequency mode current sense ADC , */\
- { 0x8453, "cs_adc_offset"}, /* Micadc ADC offset setting , */\
- { 0x8490, "cs_adc_slowdel"}, /* Select delay for current sense ADC (internal decision circuitry), */\
- { 0x84a4, "cs_adc_gain"}, /* Gain setting for current sense ADC (two's complement), */\
- { 0x8500, "cs_resonator_enable"}, /* Enable for resonator to improve SRN , */\
- { 0x8510, "cs_classd_tran_skip"}, /* Skip current sense connection during a classD amplifier transition, */\
- { 0x8530, "cs_inn_short"}, /* Short current sense negative to common mode , */\
- { 0x8540, "cs_inp_short"}, /* Short current sense positive to common mode , */\
- { 0x8550, "cs_ldo_bypass"}, /* Bypass current sense LDO , */\
- { 0x8560, "cs_ldo_pulldown"}, /* Pull down current sense LDO, only valid if left_enbl_cs_ldo is high, */\
- { 0x8574, "cs_ldo_voset"}, /* Current sense LDO voltage level setting (two's complement), */\
- { 0x8700, "enbl_cs_adc"}, /* Enable current sense ADC - I2C direct mode , */\
- { 0x8710, "enbl_cs_inn1"}, /* Enable connection of current sense negative1 - I2C direct mode, */\
- { 0x8720, "enbl_cs_inn2"}, /* Enable connection of current sense negative2 - I2C direct mode, */\
- { 0x8730, "enbl_cs_inp1"}, /* Enable connection of current sense positive1 , */\
- { 0x8740, "enbl_cs_inp2"}, /* Enable connection of current sense positive2 - I2C direct mode, */\
- { 0x8750, "enbl_cs_ldo"}, /* Enable current sense LDO - I2C direct mode , */\
- { 0x8760, "enbl_cs_nofloating_n"}, /* Connect current sense negative to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */\
- { 0x8770, "enbl_cs_nofloating_p"}, /* Connect current sense positive to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */\
- { 0x8780, "enbl_cs_vbatldo"}, /* Enable of current sense LDO -- I2C direct mode , */\
- { 0x8800, "volsense_pwm_sel"}, /* Voltage sense PWM source selection control , */\
- { 0x8810, "vol_cur_sense_dc_offset"}, /* voltage and current sense decimator offset control, */\
- { 0x8902, "cursense_comp_delay"}, /* To align compensation signal with current sense signal, */\
- { 0x8930, "cursense_comp_sign"}, /* To change polarity of compensation for current sense compensation, */\
- { 0x8940, "enbl_cursense_comp"}, /* To enable current sense compensation , */\
- { 0x9000, "cf_rst_dsp"}, /* Reset , */\
- { 0x9011, "cf_dmem"}, /* Target memory , */\
- { 0x9030, "cf_aif"}, /* Auto increment , */\
- { 0x9040, "cf_int"}, /* Interrupt - auto clear , */\
- { 0x9050, "cf_cgate_off"}, /* Coolflux clock gating disabling control , */\
- { 0x9080, "cf_req_cmd"}, /* Firmware event request rpc command , */\
- { 0x9090, "cf_req_reset"}, /* Firmware event request reset restart , */\
- { 0x90a0, "cf_req_mips"}, /* Firmware event request short on mips , */\
- { 0x90b0, "cf_req_mute_ready"}, /* Firmware event request mute sequence ready , */\
- { 0x90c0, "cf_req_volume_ready"}, /* Firmware event request volume ready , */\
- { 0x90d0, "cf_req_damage"}, /* Firmware event request speaker damage detected , */\
- { 0x90e0, "cf_req_calibrate_ready"}, /* Firmware event request calibration completed , */\
- { 0x90f0, "cf_req_reserved"}, /* Firmware event request reserved , */\
- { 0x910f, "cf_madd"}, /* Memory address , */\
- { 0x920f, "cf_mema"}, /* Activate memory access , */\
- { 0x9307, "cf_err"}, /* Error flags , */\
- { 0x9380, "cf_ack_cmd"}, /* Firmware event acknowledge rpc command , */\
- { 0x9390, "cf_ack_reset"}, /* Firmware event acknowledge reset restart , */\
- { 0x93a0, "cf_ack_mips"}, /* Firmware event acknowledge short on mips , */\
- { 0x93b0, "cf_ack_mute_ready"}, /* Firmware event acknowledge mute sequence ready , */\
- { 0x93c0, "cf_ack_volume_ready"}, /* Firmware event acknowledge volume ready , */\
- { 0x93d0, "cf_ack_damage"}, /* Firmware event acknowledge speaker damage detected, */\
- { 0x93e0, "cf_ack_calibrate_ready"}, /* Firmware event acknowledge calibration completed , */\
- { 0x93f0, "cf_ack_reserved"}, /* Firmware event acknowledge reserved , */\
- { 0xa007, "mtpkey1"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
- { 0xa107, "mtpkey2"}, /* MTP KEY2 register , */\
- { 0xa200, "key01_locked"}, /* Indicates KEY1 is locked , */\
- { 0xa210, "key02_locked"}, /* Indicates KEY2 is locked , */\
- { 0xa302, "mtp_man_address_in"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
- { 0xa330, "man_copy_mtp_to_iic"}, /* Start copying single word from mtp to I2C mtp register, */\
- { 0xa340, "man_copy_iic_to_mtp"}, /* Start copying single word from I2C mtp register to mtp, */\
- { 0xa350, "auto_copy_mtp_to_iic"}, /* Start copying all the data from mtp to I2C mtp registers, */\
- { 0xa360, "auto_copy_iic_to_mtp"}, /* Start copying data from I2C mtp registers to mtp , */\
- { 0xa400, "faim_set_clkws"}, /* Sets the FaIM controller clock wait state register, */\
- { 0xa410, "faim_sel_evenrows"}, /* All even rows of the FaIM are selected, active high, */\
- { 0xa420, "faim_sel_oddrows"}, /* All odd rows of the FaIM are selected, all rows in combination with sel_evenrows, */\
- { 0xa430, "faim_program_only"}, /* Skip the erase access at wr_faim command (write-program-marginread), */\
- { 0xa440, "faim_erase_only"}, /* Skip the program access at wr_faim command (write-erase-marginread), */\
- { 0xa50f, "mtp_man_data_out_msb"}, /* MSB word of MTP manual read data , */\
- { 0xa60f, "mtp_man_data_out_lsb"}, /* LSB word of MTP manual read data , */\
- { 0xa70f, "mtp_man_data_in_msb"}, /* MSB word of write data for MTP manual write , */\
- { 0xa80f, "mtp_man_data_in_lsb"}, /* LSB word of write data for MTP manual write , */\
- { 0xb010, "bypass_ocpcounter"}, /* Bypass OCP Counter , */\
- { 0xb020, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
- { 0xb030, "bypass_ovp"}, /* Bypass OVP , */\
- { 0xb040, "bypass_uvp"}, /* Bypass UVP , */\
- { 0xb050, "bypass_otp"}, /* Bypass OTP , */\
- { 0xb060, "bypass_lost_clk"}, /* Bypass lost clock detector , */\
- { 0xb070, "ctrl_vpalarm"}, /* vpalarm (uvp ovp handling) , */\
- { 0xb087, "ocp_threshold"}, /* OCP threshold level , */\
- { 0xb108, "ext_temp"}, /* External temperature (C) , */\
- { 0xb190, "ext_temp_sel"}, /* Select temp Speaker calibration , */\
- { 0xc000, "use_direct_ctrls"}, /* Direct control to overrule several functions for testing, */\
- { 0xc010, "rst_datapath"}, /* Direct control for datapath reset , */\
- { 0xc020, "rst_cgu"}, /* Direct control for cgu reset , */\
- { 0xc038, "enbl_ref"}, /* Switch on the analog references, each part of the references can be switched on/off individually - - I2C direct mode, */\
- { 0xc0d0, "enbl_ringo"}, /* Enable the ring oscillator for test purpose , */\
- { 0xc0e0, "use_direct_clk_ctrl"}, /* Direct clock control to overrule several functions for testing, */\
- { 0xc0f0, "use_direct_pll_ctrl"}, /* Direct PLL control to overrule several functions for testing, */\
- { 0xc100, "enbl_tsense"}, /* Temperature sensor enable control - I2C direct mode, */\
- { 0xc110, "tsense_hibias"}, /* Bit to set the biasing in temp sensor to high - I2C direct mode, */\
- { 0xc120, "enbl_flag_vbg"}, /* Enable flagging of bandgap out of control , */\
- { 0xc130, "tap_comp_enable"}, /* Tap Comparator enable control - I2C direct mode , */\
- { 0xc140, "tap_comp_switch_enable"}, /* Tap Comparator Switch enable control - I2C direct mode, */\
- { 0xc150, "tap_comp_switch_aux_enable"}, /* Tap Comparator Switch enable control - I2C direct mode, */\
- { 0xc161, "tap_comp_test_enable"}, /* Comparator threshold - fine value , */\
- { 0xc180, "curdist_enable"}, /* Enable control - I2C direct mode , */\
- { 0xc190, "vbg2i_enbl"}, /* Enable control - I2C direct mode , */\
- { 0xc1a0, "bg_filt_bypass_enbl"}, /* Enable control , */\
- { 0xc20f, "abist_offset"}, /* Offset control for ABIST testing (two's complement), */\
- { 0xc300, "bypasslatch"}, /* Bypass latch , */\
- { 0xc311, "sourcea"}, /* Set OUTA to , */\
- { 0xc331, "sourceb"}, /* Set OUTB to , */\
- { 0xc350, "inverta"}, /* Invert pwma test signal , */\
- { 0xc360, "invertb"}, /* Invert pwmb test signal , */\
- { 0xc374, "pulselength"}, /* Pulse length setting test input for amplifier (clock d - k*2048*fs), */\
- { 0xc3c0, "tdm_enable_loopback"}, /* TDM loopback test , */\
- { 0xc3d0, "test_abistfft_enbl"}, /* FFT Coolflux , */\
- { 0xc3e0, "test_pwr_switch"}, /* Test mode for digital power switches core sw/mem sw/micvdd sw, */\
- { 0xc400, "bst_bypasslatch"}, /* Bypass latch in boost converter , */\
- { 0xc411, "bst_source"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
- { 0xc430, "bst_invertb"}, /* Invert pwmbst test signal , */\
- { 0xc444, "bst_pulselength"}, /* Pulse length setting test input for boost converter , */\
- { 0xc490, "test_bst_ctrlsthv"}, /* Test mode for boost control stage , */\
- { 0xc4a0, "test_bst_iddq"}, /* IDDQ testing in power stage of boost converter , */\
- { 0xc4b0, "test_bst_rdson"}, /* RDSON testing - boost power stage , */\
- { 0xc4c0, "test_bst_cvi"}, /* CVI testing - boost power stage , */\
- { 0xc4d0, "test_bst_ocp"}, /* Boost OCP. For old ocp (ctrl_reversebst is 0), For new ocp (ctrl_reversebst is 1), */\
- { 0xc4e0, "test_bst_sense"}, /* Test option for the sense NMOS in booster for current mode control., */\
- { 0xc500, "test_cvi"}, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */\
- { 0xc510, "test_discrete"}, /* Test function noise measurement , */\
- { 0xc520, "test_iddq"}, /* Set the power stages in iddq mode for gate stress., */\
- { 0xc540, "test_rdson"}, /* Analog BIST, switch to enable Rdson measurement , */\
- { 0xc550, "test_sdelta"}, /* Analog BIST, noise test , */\
- { 0xc560, "bypass_fro8"}, /* Bypass fro8 with pdm_clk , */\
- { 0xc570, "test_enbl_cs"}, /* Enable for digimux mode of current sense , */\
- { 0xc5b0, "pga_test_enable"}, /* Enable PGA test mode , */\
- { 0xc5c0, "pga_test_offset_enable"}, /* Enable PGA test offset , */\
- { 0xc5d0, "pga_test_shortinput_enable"}, /* Enable PGA test short input , */\
- { 0xc600, "enbl_pwm_dcc"}, /* Enables direct control of pwm duty cycle for DCDC power stage, */\
- { 0xc613, "pwm_dcc_cnt"}, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */\
- { 0xc650, "enbl_ldo_stress"}, /* Enable stress of internal supply voltages powerstages, */\
- { 0xc660, "enbl_powerswitch"}, /* Vddd core power switch control - overrules the manager control, */\
- { 0xc707, "digimuxa_sel"}, /* DigimuxA input selection control routed to DIO4 (see Digimux list for details), */\
- { 0xc787, "digimuxb_sel"}, /* DigimuxB input selection control routed to DIO3 (see Digimux list for details), */\
- { 0xc807, "digimuxc_sel"}, /* DigimuxC input selection control routed to TDO (see Digimux list for details), */\
- { 0xc901, "dio1_ehs"}, /* Speed/load setting for DIO1 IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
- { 0xc921, "dio2_ehs"}, /* Speed/load setting for DIO2 IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
- { 0xc941, "dio3_ehs"}, /* Speed/load setting for DIO3 cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
- { 0xc961, "dio4_ehs"}, /* Speed/load setting for DIO4 IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
- { 0xc981, "spdmo_ehs"}, /* Speed/load setting for PDMO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
- { 0xc9a1, "tdo_ehs"}, /* Speed/load setting for TDM IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
- { 0xc9c0, "int_ehs"}, /* Slew Rate INT IO cell, clk or data mode range (see IIC3V3 IO cell datasheet), */\
- { 0xc9d0, "pdmclk_ehs"}, /* Slew RateBCK2/PDMCLK IO cell, clk or data mode range (see IIC3V3 IO cell datasheet), */\
- { 0xc9e0, "fs2_ehs"}, /* Slew Rate DS2 IO cell, clk or data mode range (see IIC3V3 IO cell datasheet), */\
- { 0xc9f0, "hs_mode"}, /* I2C high speed mode control , */\
- { 0xca00, "enbl_anamux1"}, /* Enable anamux1 , */\
- { 0xca10, "enbl_anamux2"}, /* Enable anamux2 , */\
- { 0xca20, "enbl_anamux3"}, /* Enable anamux3 , */\
- { 0xca30, "enbl_anamux4"}, /* Enable anamux4 , */\
- { 0xca74, "anamux1"}, /* Anamux selection control - anamux on TEST1 , */\
- { 0xcb04, "anamux2"}, /* Anamux selection control - anamux on TEST2 , */\
- { 0xcb54, "anamux3"}, /* Anamux selection control - anamux on TEST3 , */\
- { 0xcba4, "anamux4"}, /* Anamux selection control - anamux on TEST4 , */\
- { 0xcc05, "pll_seli_lbw"}, /* PLL SELI - Low B/W PLL control mode or I2C direct PLL control mode only, */\
- { 0xcc64, "pll_selp_lbw"}, /* PLL SELP - Low B/W PLL control mode or I2C direct PLL control mode only, */\
- { 0xccb3, "pll_selr_lbw"}, /* PLL SELR - Low B/W PLL control mode or I2C direct PLL control mode only, */\
- { 0xccf0, "sel_user_pll_bw"}, /* PLL Low Bandwidth Mode control , */\
- { 0xcdf0, "pll_frm"}, /* PLL free running mode control; 1 in TCB direct control mode, else this control bit, */\
- { 0xce09, "pll_ndec"}, /* PLL NDEC - I2C direct PLL control mode only , */\
- { 0xcea0, "pll_mdec_msb"}, /* MSB of pll_mdec - I2C direct PLL control mode only, */\
- { 0xceb0, "enbl_pll"}, /* Enables PLL in I2C direct PLL control mode only , */\
- { 0xcec0, "enbl_fro8"}, /* Enables FRO8M in I2C direct control mode only , */\
- { 0xced0, "pll_bypass"}, /* PLL bypass control in I2C direct PLL control mode only, */\
- { 0xcee0, "pll_directi"}, /* PLL directi control in I2C direct PLL control mode only, */\
- { 0xcef0, "pll_directo"}, /* PLL directo control in I2C direct PLL control mode only, */\
- { 0xcf0f, "pll_mdec_lsb"}, /* Bits 15..0 of PLL MDEC are I2C direct PLL control mode only, */\
- { 0xd006, "pll_pdec"}, /* PLL PDEC - I2C direct PLL control mode only , */\
- { 0xd10f, "tsig_freq_lsb"}, /* Internal sinus test generator frequency control , */\
- { 0xd202, "tsig_freq_msb"}, /* Select internal sinus test generator, frequency control msb bits, */\
- { 0xd230, "inject_tsig"}, /* Control bit to switch to internal sinus test generator, */\
- { 0xd283, "tsig_gain"}, /* Test signal gain , */\
- { 0xd300, "adc10_reset"}, /* Reset for ADC10 - I2C direct control mode , */\
- { 0xd311, "adc10_test"}, /* Test mode selection signal for ADC10 - I2C direct control mode, */\
- { 0xd332, "adc10_sel"}, /* Select the input to convert for ADC10 - I2C direct control mode, */\
- { 0xd364, "adc10_prog_sample"}, /* ADC10 program sample setting - I2C direct control mode, */\
- { 0xd3b0, "adc10_enbl"}, /* Enable ADC10 - I2C direct control mode , */\
- { 0xd3c0, "bypass_lp_vbat"}, /* Bypass control for Low pass filter in batt sensor , */\
- { 0xd409, "data_adc10_tempbat"}, /* ADC 10 data output data for testing , */\
- { 0xd507, "ctrl_digtoana_hidden"}, /* Spare digital to analog control bits - Hidden , */\
- { 0xd580, "enbl_clk_range_chk"}, /* Clock out of range , */\
- { 0xd601, "clkdiv_dsp_sel"}, /* DSP clock divider selection in direct clock control mode, */\
- { 0xd621, "clkdiv_audio_sel"}, /* Audio clock divider selection in direct clock control mode, */\
- { 0xd641, "clkdiv_muxa_sel"}, /* DCDC MUXA clock divider selection in direct clock control mode, */\
- { 0xd661, "clkdiv_muxb_sel"}, /* DCDC MUXB clock divider selection in direct clock control mode, */\
- { 0xd681, "dsp_tap_clk"}, /* Dsp clock frequency selection in TAP mode; , */\
- { 0xd6a1, "sel_wdt_clk"}, /* Watch dog clock post divider value , */\
- { 0xd6c1, "sel_tim_clk"}, /* Timer clock post divider value , */\
- { 0xd700, "ads1_ehs"}, /* Slew Rate ADS1 IO cell, clk or data mode range (see IIC3V3 IO cell datasheet), */\
- { 0xd710, "ads2_ehs"}, /* Slew Rate ADS2 IO cell, clk or data mode range (see IIC3V3 IO cell datasheet), */\
- { 0xd822, "test_parametric_io"}, /* test io parametric , */\
- { 0xd850, "ctrl_bst_clk_lp1"}, /* boost clock control in low power mode1 , */\
- { 0xd861, "test_spare_out1"}, /* test spare out 1 , */\
- { 0xd880, "bst_dcmbst"}, /* dcm boost - I2C direct mode , */\
- { 0xd8a1, "force_pga_clock"}, /* force pga clock , */\
- { 0xd8c3, "test_spare_out2"}, /* test spare out 1 , */\
- { 0xd900, "overrules_usercase"}, /* Overrule Mode control use , */\
- { 0xd910, "ovr_switch_ref"}, /* Overrule Value , */\
- { 0xd920, "ovr_enbl_pll"}, /* Overrule Value , */\
- { 0xd930, "ovr_switch_amp"}, /* Overrule Value , */\
- { 0xd940, "ovr_enbl_clk_cs"}, /* Overrule Value , */\
- { 0xd951, "ovr_sel_clk_cs"}, /* CS clock selection overrule , */\
- { 0xd970, "ovr_switch_cs"}, /* Overrule Value , */\
- { 0xd980, "ovr_enbl_csvs_ss"}, /* Overrule Value , */\
- { 0xd990, "ovr_enbl_comp"}, /* Overrule Value , */\
- { 0xed00, "enbl_fro8cal"}, /* Enable FRO calibration , */\
- { 0xed10, "start_fro8_calibration"}, /* Start FRO8 Calibration , */\
- { 0xed20, "fro8_calibration_done"}, /* FRO8 Calibration done - Read Only , */\
- { 0xed45, "fro8_auto_trim_val"}, /* Calibration value from Auto Calibration block, to be written into MTP - Read Only, */\
- { 0xee0f, "sw_profile"}, /* Software profile data , */\
- { 0xef0f, "sw_vstep"}, /* Software vstep information , */\
- { 0xf000, "calibration_onetime"}, /* Calibration schedule , */\
- { 0xf010, "calibr_ron_done"}, /* Calibration Ron executed , */\
- { 0xf020, "calibr_dcdc_api_calibrate"}, /* Calibration current limit DCDC , */\
- { 0xf030, "calibr_dcdc_delta_sign"}, /* Sign bit for delta calibration current limit DCDC , */\
- { 0xf042, "calibr_dcdc_delta"}, /* Calibration delta current limit DCDC , */\
- { 0xf078, "calibr_speaker_info"}, /* Reserved space for allowing customer to store speaker information, */\
- { 0xf105, "calibr_vout_offset"}, /* DCDC offset calibration 2's complement (key1 protected), */\
- { 0xf163, "spare_mtp1_9_6"}, /* HW gain module - left channel (2's complement) , */\
- { 0xf1a5, "spare_mtp1_15_10"}, /* Offset for amplifier, HW gain module - left channel (2's complement), */\
- { 0xf203, "calibr_gain"}, /* HW gain module (2's complement) , */\
- { 0xf245, "calibr_offset"}, /* Offset for amplifier, HW gain module (2's complement), */\
- { 0xf2a3, "spare_mtp2_13_10"}, /* Trimming of LDO (2.7V) , */\
- { 0xf307, "spare_mtp3_7_0"}, /* SPARE , */\
- { 0xf387, "calibr_gain_cs"}, /* Current sense gain (signed two's complement format), */\
- { 0xf40f, "calibr_R25C"}, /* Ron resistance of speaker coil , */\
- { 0xf50f, "spare_mtp5_15_0"}, /* SPARE , */\
- { 0xf600, "mtp_lock_enbl_coolflux"}, /* Disable function dcdcoff_mode , */\
- { 0xf610, "mtp_pwm_delay_enbl_clk_auto_gating"}, /* Auto clock gating on pwm_delay , */\
- { 0xf620, "mtp_ocp_enbl_clk_auto_gating"}, /* Auto clock gating on module ocp , */\
- { 0xf630, "mtp_disable_clk_a_gating"}, /* Disable clock_a gating , */\
- { 0xf642, "spare_mtp6_6_3"}, /* SPARE , */\
- { 0xf686, "spare_mtp6_14_8"}, /* Offset of left amplifier level shifter B , */\
- { 0xf706, "ctrl_offset_a"}, /* Offset of level shifter A , */\
- { 0xf786, "ctrl_offset_b"}, /* Offset of amplifier level shifter B , */\
- { 0xf806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
- { 0xf870, "htol_iic_addr_en"}, /* HTOL I2C address enable control , */\
- { 0xf884, "calibr_temp_offset"}, /* Temperature offset 2's compliment (key1 protected), */\
- { 0xf8d2, "calibr_temp_gain"}, /* Temperature gain 2's compliment (key1 protected) , */\
- { 0xf910, "disable_sam_mode"}, /* Disable sam mode , */\
- { 0xf920, "mtp_lock_bypass_clipper"}, /* Disable function bypass_clipper , */\
- { 0xf930, "mtp_lock_max_dcdc_voltage"}, /* Disable programming of max dcdc boost voltage , */\
- { 0xf943, "calibr_vbg_trim"}, /* Bandgap trimming control , */\
- { 0xf987, "type_bits_fw"}, /* MTP-control FW - See Firmware I2C API document for details, */\
- { 0xfa0f, "mtpdataA"}, /* MTPdataA (key1 protected) , */\
- { 0xfb0f, "mtpdataB"}, /* MTPdataB (key1 protected) , */\
- { 0xfc0f, "mtpdataC"}, /* MTPdataC (key1 protected) , */\
- { 0xfd0f, "mtpdataD"}, /* MTPdataD (key1 protected) , */\
- { 0xfe0f, "mtpdataE"}, /* MTPdataE (key1 protected) , */\
- { 0xff05, "fro8_trim"}, /* 8 MHz oscillator trim code , */\
- { 0xff61, "fro8_short_nwell_r"}, /* Short 4 or 6 n-well resistors , */\
- { 0xff81, "fro8_boost_i"}, /* Self bias current selection , */\
- { 0xffff,"Unknown bitfield enum" } /* not found */\
-};
-
-enum tfa9912_irq {
- tfa9912_irq_stvdds = 0,
- tfa9912_irq_stplls = 1,
- tfa9912_irq_stotds = 2,
- tfa9912_irq_stovds = 3,
- tfa9912_irq_stuvds = 4,
- tfa9912_irq_stclks = 5,
- tfa9912_irq_stmtpb = 6,
- tfa9912_irq_stnoclk = 7,
- tfa9912_irq_stspks = 8,
- tfa9912_irq_stacs = 9,
- tfa9912_irq_stsws = 10,
- tfa9912_irq_stwds = 11,
- tfa9912_irq_stamps = 12,
- tfa9912_irq_starefs = 13,
- tfa9912_irq_stadccr = 14,
- tfa9912_irq_stbodnok = 15,
- tfa9912_irq_stbstcu = 16,
- tfa9912_irq_stbsthi = 17,
- tfa9912_irq_stbstoc = 18,
- tfa9912_irq_stbstpkcur = 19,
- tfa9912_irq_stbstvc = 20,
- tfa9912_irq_stbst86 = 21,
- tfa9912_irq_stbst93 = 22,
- tfa9912_irq_strcvld = 23,
- tfa9912_irq_stocpl = 24,
- tfa9912_irq_stocpr = 25,
- tfa9912_irq_stmwsrc = 26,
- tfa9912_irq_stmwcfc = 27,
- tfa9912_irq_stmwsmu = 28,
- tfa9912_irq_stcfmer = 29,
- tfa9912_irq_stcfmac = 30,
- tfa9912_irq_stclkoor = 31,
- tfa9912_irq_sttdmer = 32,
- tfa9912_irq_stclpl = 33,
- tfa9912_irq_stclpr = 34,
- tfa9912_irq_stocpm = 35,
- tfa9912_irq_stlp1 = 37,
- tfa9912_irq_stla = 38,
- tfa9912_irq_stvddp = 39,
- tfa9912_irq_sttapdet = 40,
- tfa9912_irq_staudmod = 41,
- tfa9912_irq_stsammod = 42,
- tfa9912_irq_sttapmod = 43,
- tfa9912_irq_sttaptrg = 44,
- tfa9912_irq_max = 45,
- tfa9912_irq_all = -1 /* all irqs */};
-
-#define TFA9912_IRQ_NAMETABLE static tfaIrqName_t Tfa9912IrqNames[]= {\
- { 0, "STVDDS"},\
- { 1, "STPLLS"},\
- { 2, "STOTDS"},\
- { 3, "STOVDS"},\
- { 4, "STUVDS"},\
- { 5, "STCLKS"},\
- { 6, "STMTPB"},\
- { 7, "STNOCLK"},\
- { 8, "STSPKS"},\
- { 9, "STACS"},\
- { 10, "STSWS"},\
- { 11, "STWDS"},\
- { 12, "STAMPS"},\
- { 13, "STAREFS"},\
- { 14, "STADCCR"},\
- { 15, "STBODNOK"},\
- { 16, "STBSTCU"},\
- { 17, "STBSTHI"},\
- { 18, "STBSTOC"},\
- { 19, "STBSTPKCUR"},\
- { 20, "STBSTVC"},\
- { 21, "STBST86"},\
- { 22, "STBST93"},\
- { 23, "STRCVLD"},\
- { 24, "STOCPL"},\
- { 25, "STOCPR"},\
- { 26, "STMWSRC"},\
- { 27, "STMWCFC"},\
- { 28, "STMWSMU"},\
- { 29, "STCFMER"},\
- { 30, "STCFMAC"},\
- { 31, "STCLKOOR"},\
- { 32, "STTDMER"},\
- { 33, "STCLPL"},\
- { 34, "STCLPR"},\
- { 35, "STOCPM"},\
- { 36, "36"},\
- { 37, "STLP1"},\
- { 38, "STLA"},\
- { 39, "STVDDP"},\
- { 40, "STTAPDET"},\
- { 41, "STAUDMOD"},\
- { 42, "STSAMMOD"},\
- { 43, "STTAPMOD"},\
- { 44, "STTAPTRG"},\
- { 45, "45"},\
-};
-#endif /* _TFA9912_TFAFIELDNAMES_H */
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _TFA9912_TFAFIELDNAMES_H
+#define _TFA9912_TFAFIELDNAMES_H
+
+
+#define TFA9912_I2CVERSION 1.43
+
+typedef enum nxpTfa9912BfEnumList {
+ TFA9912_BF_PWDN = 0x0000, /*!< Powerdown selection */
+ TFA9912_BF_I2CR = 0x0010, /*!< I2C Reset - Auto clear */
+ TFA9912_BF_CFE = 0x0020, /*!< Enable CoolFlux */
+ TFA9912_BF_AMPE = 0x0030, /*!< Enables the Amplifier */
+ TFA9912_BF_DCA = 0x0040, /*!< Activate DC-to-DC converter */
+ TFA9912_BF_SBSL = 0x0050, /*!< Coolflux configured */
+ TFA9912_BF_AMPC = 0x0060, /*!< CoolFlux controls amplifier */
+ TFA9912_BF_INTP = 0x0071, /*!< Interrupt config */
+ TFA9912_BF_FSSSEL = 0x0090, /*!< Audio sample reference */
+ TFA9912_BF_BYPOCP = 0x00b0, /*!< Bypass OCP */
+ TFA9912_BF_TSTOCP = 0x00c0, /*!< OCP testing control */
+ TFA9912_BF_AMPINSEL = 0x0101, /*!< Amplifier input selection */
+ TFA9912_BF_MANSCONF = 0x0120, /*!< I2C configured */
+ TFA9912_BF_MANCOLD = 0x0130, /*!< Execute cold start */
+ TFA9912_BF_MANAOOSC = 0x0140, /*!< Internal osc off at PWDN */
+ TFA9912_BF_MANROBOD = 0x0150, /*!< Reaction on BOD */
+ TFA9912_BF_BODE = 0x0160, /*!< BOD Enable */
+ TFA9912_BF_BODHYS = 0x0170, /*!< BOD Hysteresis */
+ TFA9912_BF_BODFILT = 0x0181, /*!< BOD filter */
+ TFA9912_BF_BODTHLVL = 0x01a1, /*!< BOD threshold */
+ TFA9912_BF_MUTETO = 0x01d0, /*!< Time out SB mute sequence */
+ TFA9912_BF_RCVNS = 0x01e0, /*!< Noise shaper selection */
+ TFA9912_BF_MANWDE = 0x01f0, /*!< Watchdog enable */
+ TFA9912_BF_AUDFS = 0x0203, /*!< Sample rate (fs) */
+ TFA9912_BF_INPLEV = 0x0240, /*!< TDM output attenuation */
+ TFA9912_BF_FRACTDEL = 0x0255, /*!< V/I Fractional delay */
+ TFA9912_BF_BYPHVBF = 0x02b0, /*!< Bypass HVBAT filter */
+ TFA9912_BF_TDMC = 0x02c0, /*!< TDM Compatibility with TFA9872 */
+ TFA9912_BF_ENBLADC10 = 0x02e0, /*!< ADC10 Enable - I2C direct mode */
+ TFA9912_BF_REV = 0x030f, /*!< Revision info */
+ TFA9912_BF_REFCKEXT = 0x0401, /*!< PLL external ref clock */
+ TFA9912_BF_REFCKSEL = 0x0420, /*!< PLL internal ref clock */
+ TFA9912_BF_ENCFCKSEL = 0x0430, /*!< Coolflux DSP clock scaling, low power mode */
+ TFA9912_BF_CFCKSEL = 0x0441, /*!< Coolflux DSP clock scaler selection for low power mode */
+ TFA9912_BF_TDMINFSEL = 0x0460, /*!< TDM clock selection */
+ TFA9912_BF_DISBLAUTOCLKSEL = 0x0470, /*!< Disable Automatic dsp clock source selection */
+ TFA9912_BF_SELCLKSRC = 0x0480, /*!< I2C selection of DSP clock when auto select is disabled */
+ TFA9912_BF_SELTIMSRC = 0x0490, /*!< I2C selection of Watchdog and Timer clock */
+ TFA9912_BF_SSLEFTE = 0x0500, /*!< */
+ TFA9912_BF_SPKSSEN = 0x0510, /*!< Enable speaker path */
+ TFA9912_BF_VSLEFTE = 0x0520, /*!< */
+ TFA9912_BF_VSRIGHTE = 0x0530, /*!< Voltage sense */
+ TFA9912_BF_CSLEFTE = 0x0540, /*!< */
+ TFA9912_BF_CSRIGHTE = 0x0550, /*!< Current sense */
+ TFA9912_BF_SSPDME = 0x0560, /*!< Sub-system PDM */
+ TFA9912_BF_PGALE = 0x0570, /*!< Enable PGA chop clock for left channel */
+ TFA9912_BF_PGARE = 0x0580, /*!< Enable PGA chop clock */
+ TFA9912_BF_SSTDME = 0x0590, /*!< Sub-system TDM */
+ TFA9912_BF_SSPBSTE = 0x05a0, /*!< Sub-system boost */
+ TFA9912_BF_SSADCE = 0x05b0, /*!< Sub-system ADC */
+ TFA9912_BF_SSFAIME = 0x05c0, /*!< Sub-system FAIM */
+ TFA9912_BF_SSCFTIME = 0x05d0, /*!< CF Sub-system timer */
+ TFA9912_BF_SSCFWDTE = 0x05e0, /*!< CF Sub-system WDT */
+ TFA9912_BF_FAIMVBGOVRRL = 0x05f0, /*!< Over rule of vbg for FaIM access */
+ TFA9912_BF_SAMSPKSEL = 0x0600, /*!< Input selection for TAP/SAM */
+ TFA9912_BF_PDM2IISEN = 0x0610, /*!< PDM2IIS Bridge enable */
+ TFA9912_BF_TAPRSTBYPASS = 0x0620, /*!< Tap decimator reset bypass - Bypass the decimator reset from tapdec */
+ TFA9912_BF_CARDECISEL0 = 0x0631, /*!< Cardec input 0 sel */
+ TFA9912_BF_CARDECISEL1 = 0x0651, /*!< Cardec input sel */
+ TFA9912_BF_TAPDECSEL = 0x0670, /*!< Select TAP/Cardec for TAP */
+ TFA9912_BF_COMPCOUNT = 0x0680, /*!< Comparator o/p filter selection */
+ TFA9912_BF_STARTUPMODE = 0x0691, /*!< Startup Mode Selection */
+ TFA9912_BF_AUTOTAP = 0x06b0, /*!< Enable auto tap switching */
+ TFA9912_BF_COMPINITIME = 0x06c1, /*!< Comparator initialization time to be used in Tap Machine */
+ TFA9912_BF_ANAPINITIME = 0x06e1, /*!< Analog initialization time to be used in Tap Machine */
+ TFA9912_BF_CCHKTH = 0x0707, /*!< Clock check Higher Threshold */
+ TFA9912_BF_CCHKTL = 0x0787, /*!< Clock check Higher Threshold */
+ TFA9912_BF_AMPOCRT = 0x0802, /*!< Amplifier on-off criteria for shutdown */
+ TFA9912_BF_AMPTCRR = 0x0832, /*!< Amplifier on-off criteria for tap mode entry */
+ TFA9912_BF_STGS = 0x0d00, /*!< PDM side tone gain selector */
+ TFA9912_BF_STGAIN = 0x0d18, /*!< Side tone gain */
+ TFA9912_BF_STSMUTE = 0x0da0, /*!< Side tone soft mute */
+ TFA9912_BF_ST1C = 0x0db0, /*!< side tone one s complement */
+ TFA9912_BF_CMFBEL = 0x0e80, /*!< CMFB enable left */
+ TFA9912_BF_VDDS = 0x1000, /*!< POR */
+ TFA9912_BF_PLLS = 0x1010, /*!< PLL lock */
+ TFA9912_BF_OTDS = 0x1020, /*!< OTP alarm */
+ TFA9912_BF_OVDS = 0x1030, /*!< OVP alarm */
+ TFA9912_BF_UVDS = 0x1040, /*!< UVP alarm */
+ TFA9912_BF_CLKS = 0x1050, /*!< Clocks stable */
+ TFA9912_BF_MTPB = 0x1060, /*!< MTP busy */
+ TFA9912_BF_NOCLK = 0x1070, /*!< Lost clock */
+ TFA9912_BF_ACS = 0x1090, /*!< Cold Start */
+ TFA9912_BF_SWS = 0x10a0, /*!< Amplifier engage */
+ TFA9912_BF_WDS = 0x10b0, /*!< Watchdog */
+ TFA9912_BF_AMPS = 0x10c0, /*!< Amplifier enable */
+ TFA9912_BF_AREFS = 0x10d0, /*!< References enable */
+ TFA9912_BF_ADCCR = 0x10e0, /*!< Control ADC */
+ TFA9912_BF_BODNOK = 0x10f0, /*!< BOD */
+ TFA9912_BF_DCIL = 0x1100, /*!< DCDC current limiting */
+ TFA9912_BF_DCDCA = 0x1110, /*!< DCDC active */
+ TFA9912_BF_DCOCPOK = 0x1120, /*!< DCDC OCP nmos */
+ TFA9912_BF_DCPEAKCUR = 0x1130, /*!< Indicates current is max in DC-to-DC converter */
+ TFA9912_BF_DCHVBAT = 0x1140, /*!< DCDC level 1x */
+ TFA9912_BF_DCH114 = 0x1150, /*!< DCDC level 1.14x */
+ TFA9912_BF_DCH107 = 0x1160, /*!< DCDC level 1.07x */
+ TFA9912_BF_STMUTEB = 0x1170, /*!< side tone (un)mute busy */
+ TFA9912_BF_STMUTE = 0x1180, /*!< side tone mute state */
+ TFA9912_BF_TDMLUTER = 0x1190, /*!< TDM LUT error */
+ TFA9912_BF_TDMSTAT = 0x11a2, /*!< TDM status bits */
+ TFA9912_BF_TDMERR = 0x11d0, /*!< TDM error */
+ TFA9912_BF_HAPTIC = 0x11e0, /*!< Status haptic driver */
+ TFA9912_BF_OCPOAP = 0x1300, /*!< OCPOK pmos A */
+ TFA9912_BF_OCPOAN = 0x1310, /*!< OCPOK nmos A */
+ TFA9912_BF_OCPOBP = 0x1320, /*!< OCPOK pmos B */
+ TFA9912_BF_OCPOBN = 0x1330, /*!< OCPOK nmos B */
+ TFA9912_BF_CLIPAH = 0x1340, /*!< Clipping A to Vddp */
+ TFA9912_BF_CLIPAL = 0x1350, /*!< Clipping A to gnd */
+ TFA9912_BF_CLIPBH = 0x1360, /*!< Clipping B to Vddp */
+ TFA9912_BF_CLIPBL = 0x1370, /*!< Clipping B to gnd */
+ TFA9912_BF_OCDS = 0x1380, /*!< OCP amplifier */
+ TFA9912_BF_CLIPS = 0x1390, /*!< Amplifier clipping */
+ TFA9912_BF_TCMPTRG = 0x13a0, /*!< Status Tap comparator triggered */
+ TFA9912_BF_TAPDET = 0x13b0, /*!< Status Tap detected */
+ TFA9912_BF_MANWAIT1 = 0x13c0, /*!< Wait HW I2C settings */
+ TFA9912_BF_MANWAIT2 = 0x13d0, /*!< Wait CF config */
+ TFA9912_BF_MANMUTE = 0x13e0, /*!< Audio mute sequence */
+ TFA9912_BF_MANOPER = 0x13f0, /*!< Operating state */
+ TFA9912_BF_SPKSL = 0x1400, /*!< Left speaker status */
+ TFA9912_BF_SPKS = 0x1410, /*!< Speaker status */
+ TFA9912_BF_CLKOOR = 0x1420, /*!< External clock status */
+ TFA9912_BF_MANSTATE = 0x1433, /*!< Device manager status */
+ TFA9912_BF_DCMODE = 0x1471, /*!< DCDC mode status bits */
+ TFA9912_BF_DSPCLKSRC = 0x1490, /*!< DSP clock source selected by manager */
+ TFA9912_BF_STARTUPMODSTAT = 0x14a1, /*!< Startup Mode Selected by Manager(Read Only) */
+ TFA9912_BF_TSPMSTATE = 0x14c3, /*!< Tap Machine State */
+ TFA9912_BF_BATS = 0x1509, /*!< Battery voltage (V) */
+ TFA9912_BF_TEMPS = 0x1608, /*!< IC Temperature (C) */
+ TFA9912_BF_VDDPS = 0x1709, /*!< IC VDDP voltage ( 1023*VDDP/13 V) */
+ TFA9912_BF_DCILCF = 0x17a0, /*!< DCDC current limiting for DSP */
+ TFA9912_BF_TDMUC = 0x2000, /*!< Mode setting */
+ TFA9912_BF_DIO4SEL = 0x2011, /*!< DIO4 Input selection */
+ TFA9912_BF_TDME = 0x2040, /*!< Enable TDM interface */
+ TFA9912_BF_TDMMODE = 0x2050, /*!< Slave/master */
+ TFA9912_BF_TDMCLINV = 0x2060, /*!< Reception data to BCK clock */
+ TFA9912_BF_TDMFSLN = 0x2073, /*!< FS length */
+ TFA9912_BF_TDMFSPOL = 0x20b0, /*!< FS polarity */
+ TFA9912_BF_TDMNBCK = 0x20c3, /*!< N-BCK's in FS */
+ TFA9912_BF_TDMSLOTS = 0x2103, /*!< N-slots in Frame */
+ TFA9912_BF_TDMSLLN = 0x2144, /*!< N-bits in slot */
+ TFA9912_BF_TDMBRMG = 0x2194, /*!< N-bits remaining */
+ TFA9912_BF_TDMDEL = 0x21e0, /*!< data delay to FS */
+ TFA9912_BF_TDMADJ = 0x21f0, /*!< data adjustment */
+ TFA9912_BF_TDMOOMP = 0x2201, /*!< Received audio compression */
+ TFA9912_BF_TDMSSIZE = 0x2224, /*!< Sample size per slot */
+ TFA9912_BF_TDMTXDFO = 0x2271, /*!< Format unused bits in a slot */
+ TFA9912_BF_TDMTXUS0 = 0x2291, /*!< Format unused slots GAINIO */
+ TFA9912_BF_TDMTXUS1 = 0x22b1, /*!< Format unused slots DIO1 */
+ TFA9912_BF_TDMTXUS2 = 0x22d1, /*!< Format unused slots DIO2 */
+ TFA9912_BF_TDMGIE = 0x2300, /*!< Control gain (channel in 0) */
+ TFA9912_BF_TDMDCE = 0x2310, /*!< Control audio left (channel in 1 ) */
+ TFA9912_BF_TDMSPKE = 0x2320, /*!< Control audio right (channel in 2 ) */
+ TFA9912_BF_TDMCSE = 0x2330, /*!< Current sense */
+ TFA9912_BF_TDMVSE = 0x2340, /*!< Voltage sense */
+ TFA9912_BF_TDMGOE = 0x2350, /*!< DSP Gainout */
+ TFA9912_BF_TDMCF2E = 0x2360, /*!< DSP 2 */
+ TFA9912_BF_TDMCF3E = 0x2370, /*!< DSP 3 */
+ TFA9912_BF_TDMCFE = 0x2380, /*!< DSP */
+ TFA9912_BF_TDMES6 = 0x2390, /*!< Loopback of Audio left (channel 1) */
+ TFA9912_BF_TDMES7 = 0x23a0, /*!< Loopback of Audio right (channel 2) */
+ TFA9912_BF_TDMCF4E = 0x23b0, /*!< AEC ref right control */
+ TFA9912_BF_TDMPD1E = 0x23c0, /*!< PDM 1 control */
+ TFA9912_BF_TDMPD2E = 0x23d0, /*!< PDM 2 control */
+ TFA9912_BF_TDMGIN = 0x2401, /*!< IO gainin */
+ TFA9912_BF_TDMLIO = 0x2421, /*!< IO audio left */
+ TFA9912_BF_TDMRIO = 0x2441, /*!< IO audio right */
+ TFA9912_BF_TDMCSIO = 0x2461, /*!< IO Current Sense */
+ TFA9912_BF_TDMVSIO = 0x2481, /*!< IO voltage sense */
+ TFA9912_BF_TDMGOIO = 0x24a1, /*!< IO gain out */
+ TFA9912_BF_TDMCFIO2 = 0x24c1, /*!< IO DSP 2 */
+ TFA9912_BF_TDMCFIO3 = 0x24e1, /*!< IO DSP 3 */
+ TFA9912_BF_TDMCFIO = 0x2501, /*!< IO DSP */
+ TFA9912_BF_TDMLPB6 = 0x2521, /*!< IO Source 6 */
+ TFA9912_BF_TDMLPB7 = 0x2541, /*!< IO Source 7 */
+ TFA9912_BF_TDMGS = 0x2603, /*!< Control gainin */
+ TFA9912_BF_TDMDCS = 0x2643, /*!< tdm slot for audio left (channel 1) */
+ TFA9912_BF_TDMSPKS = 0x2683, /*!< tdm slot for audio right (channel 2) */
+ TFA9912_BF_TDMCSS = 0x26c3, /*!< Slot Position of Current Sense Out */
+ TFA9912_BF_TDMVSS = 0x2703, /*!< Slot Position of Voltage sense */
+ TFA9912_BF_TDMCGOS = 0x2743, /*!< Slot Position of GAIN out */
+ TFA9912_BF_TDMCF2S = 0x2783, /*!< Slot Position DSPout2 */
+ TFA9912_BF_TDMCF3S = 0x27c3, /*!< Slot Position DSPout3 */
+ TFA9912_BF_TDMCFS = 0x2803, /*!< Slot Position of DSPout */
+ TFA9912_BF_TDMEDAT6S = 0x2843, /*!< Slot Position of loopback channel left */
+ TFA9912_BF_TDMEDAT7S = 0x2883, /*!< Slot Position of loopback channel right */
+ TFA9912_BF_TDMTXUS3 = 0x2901, /*!< Format unused slots D3 */
+ TFA9912_BF_PDMSM = 0x3100, /*!< PDM control */
+ TFA9912_BF_PDMSTSEL = 0x3110, /*!< PDM Decimator input selection */
+ TFA9912_BF_PDMSTENBL = 0x3120, /*!< Side tone input enable */
+ TFA9912_BF_PDMLSEL = 0x3130, /*!< PDM data selection for left channel during PDM direct mode */
+ TFA9912_BF_PDMRSEL = 0x3140, /*!< PDM data selection for right channel during PDM direct mode */
+ TFA9912_BF_MICVDDE = 0x3150, /*!< Enable MICVDD */
+ TFA9912_BF_PDMCLRAT = 0x3201, /*!< PDM BCK/Fs ratio */
+ TFA9912_BF_PDMGAIN = 0x3223, /*!< PDM gain */
+ TFA9912_BF_PDMOSEL = 0x3263, /*!< PDM output selection - RE/FE data combination */
+ TFA9912_BF_SELCFHAPD = 0x32a0, /*!< Select the source for haptic data output (not for customer) */
+ TFA9912_BF_ISTVDDS = 0x4000, /*!< Status POR */
+ TFA9912_BF_ISTPLLS = 0x4010, /*!< Status PLL lock */
+ TFA9912_BF_ISTOTDS = 0x4020, /*!< Status OTP alarm */
+ TFA9912_BF_ISTOVDS = 0x4030, /*!< Status OVP alarm */
+ TFA9912_BF_ISTUVDS = 0x4040, /*!< Status UVP alarm */
+ TFA9912_BF_ISTCLKS = 0x4050, /*!< Status clocks stable */
+ TFA9912_BF_ISTMTPB = 0x4060, /*!< Status MTP busy */
+ TFA9912_BF_ISTNOCLK = 0x4070, /*!< Status lost clock */
+ TFA9912_BF_ISTSPKS = 0x4080, /*!< Status speaker error */
+ TFA9912_BF_ISTACS = 0x4090, /*!< Status cold start */
+ TFA9912_BF_ISTSWS = 0x40a0, /*!< Status amplifier engage */
+ TFA9912_BF_ISTWDS = 0x40b0, /*!< Status watchdog */
+ TFA9912_BF_ISTAMPS = 0x40c0, /*!< Status amplifier enable */
+ TFA9912_BF_ISTAREFS = 0x40d0, /*!< Status Ref enable */
+ TFA9912_BF_ISTADCCR = 0x40e0, /*!< Status Control ADC */
+ TFA9912_BF_ISTBODNOK = 0x40f0, /*!< Status BOD */
+ TFA9912_BF_ISTBSTCU = 0x4100, /*!< Status DCDC current limiting */
+ TFA9912_BF_ISTBSTHI = 0x4110, /*!< Status DCDC active */
+ TFA9912_BF_ISTBSTOC = 0x4120, /*!< Status DCDC OCP */
+ TFA9912_BF_ISTBSTPKCUR = 0x4130, /*!< Status bst peakcur */
+ TFA9912_BF_ISTBSTVC = 0x4140, /*!< Status DCDC level 1x */
+ TFA9912_BF_ISTBST86 = 0x4150, /*!< Status DCDC level 1.14x */
+ TFA9912_BF_ISTBST93 = 0x4160, /*!< Status DCDC level 1.07x */
+ TFA9912_BF_ISTRCVLD = 0x4170, /*!< Status rcvldop ready */
+ TFA9912_BF_ISTOCPL = 0x4180, /*!< Status ocp alarm left */
+ TFA9912_BF_ISTOCPR = 0x4190, /*!< Status ocp alarm */
+ TFA9912_BF_ISTMWSRC = 0x41a0, /*!< Status Waits HW I2C settings */
+ TFA9912_BF_ISTMWCFC = 0x41b0, /*!< Status waits CF config */
+ TFA9912_BF_ISTMWSMU = 0x41c0, /*!< Status Audio mute sequence */
+ TFA9912_BF_ISTCFMER = 0x41d0, /*!< Status cfma error */
+ TFA9912_BF_ISTCFMAC = 0x41e0, /*!< Status cfma ack */
+ TFA9912_BF_ISTCLKOOR = 0x41f0, /*!< Status flag_clk_out_of_range */
+ TFA9912_BF_ISTTDMER = 0x4200, /*!< Status tdm error */
+ TFA9912_BF_ISTCLPL = 0x4210, /*!< Status clip left */
+ TFA9912_BF_ISTCLPR = 0x4220, /*!< Status clip */
+ TFA9912_BF_ISTOCPM = 0x4230, /*!< Status mic ocpok */
+ TFA9912_BF_ISTLP1 = 0x4250, /*!< Status low power mode1 */
+ TFA9912_BF_ISTLA = 0x4260, /*!< Status low amplitude detection */
+ TFA9912_BF_ISTVDDP = 0x4270, /*!< Status VDDP greater than VBAT */
+ TFA9912_BF_ISTTAPDET = 0x4280, /*!< Status Tap detected */
+ TFA9912_BF_ISTAUDMOD = 0x4290, /*!< Status Audio Mode activated */
+ TFA9912_BF_ISTSAMMOD = 0x42a0, /*!< Status SAM Mode activated */
+ TFA9912_BF_ISTTAPMOD = 0x42b0, /*!< Status Tap Mode Activated */
+ TFA9912_BF_ISTTAPTRG = 0x42c0, /*!< Status Tap comparator triggered */
+ TFA9912_BF_ICLVDDS = 0x4400, /*!< Clear POR */
+ TFA9912_BF_ICLPLLS = 0x4410, /*!< Clear PLL lock */
+ TFA9912_BF_ICLOTDS = 0x4420, /*!< Clear OTP alarm */
+ TFA9912_BF_ICLOVDS = 0x4430, /*!< Clear OVP alarm */
+ TFA9912_BF_ICLUVDS = 0x4440, /*!< Clear UVP alarm */
+ TFA9912_BF_ICLCLKS = 0x4450, /*!< Clear clocks stable */
+ TFA9912_BF_ICLMTPB = 0x4460, /*!< Clear mtp busy */
+ TFA9912_BF_ICLNOCLK = 0x4470, /*!< Clear lost clk */
+ TFA9912_BF_ICLSPKS = 0x4480, /*!< Clear speaker error */
+ TFA9912_BF_ICLACS = 0x4490, /*!< Clear cold started */
+ TFA9912_BF_ICLSWS = 0x44a0, /*!< Clear amplifier engage */
+ TFA9912_BF_ICLWDS = 0x44b0, /*!< Clear watchdog */
+ TFA9912_BF_ICLAMPS = 0x44c0, /*!< Clear enbl amp */
+ TFA9912_BF_ICLAREFS = 0x44d0, /*!< Clear ref enable */
+ TFA9912_BF_ICLADCCR = 0x44e0, /*!< Clear control ADC */
+ TFA9912_BF_ICLBODNOK = 0x44f0, /*!< Clear BOD */
+ TFA9912_BF_ICLBSTCU = 0x4500, /*!< Clear DCDC current limiting */
+ TFA9912_BF_ICLBSTHI = 0x4510, /*!< Clear DCDC active */
+ TFA9912_BF_ICLBSTOC = 0x4520, /*!< Clear DCDC OCP */
+ TFA9912_BF_ICLBSTPC = 0x4530, /*!< Clear bst peakcur */
+ TFA9912_BF_ICLBSTVC = 0x4540, /*!< Clear DCDC level 1x */
+ TFA9912_BF_ICLBST86 = 0x4550, /*!< Clear DCDC level 1.14x */
+ TFA9912_BF_ICLBST93 = 0x4560, /*!< Clear DCDC level 1.07x */
+ TFA9912_BF_ICLRCVLD = 0x4570, /*!< Clear rcvldop ready */
+ TFA9912_BF_ICLOCPL = 0x4580, /*!< Clear ocp alarm left */
+ TFA9912_BF_ICLOCPR = 0x4590, /*!< Clear ocp alarm */
+ TFA9912_BF_ICLMWSRC = 0x45a0, /*!< Clear wait HW I2C settings */
+ TFA9912_BF_ICLMWCFC = 0x45b0, /*!< Clear wait cf config */
+ TFA9912_BF_ICLMWSMU = 0x45c0, /*!< Clear audio mute sequence */
+ TFA9912_BF_ICLCFMER = 0x45d0, /*!< Clear cfma err */
+ TFA9912_BF_ICLCFMAC = 0x45e0, /*!< Clear cfma ack */
+ TFA9912_BF_ICLCLKOOR = 0x45f0, /*!< Clear flag_clk_out_of_range */
+ TFA9912_BF_ICLTDMER = 0x4600, /*!< Clear tdm error */
+ TFA9912_BF_ICLCLPL = 0x4610, /*!< Clear clip left */
+ TFA9912_BF_ICLCLP = 0x4620, /*!< Clear clip */
+ TFA9912_BF_ICLOCPM = 0x4630, /*!< Clear mic ocpok */
+ TFA9912_BF_ICLLP1 = 0x4650, /*!< Clear low power mode1 */
+ TFA9912_BF_ICLLA = 0x4660, /*!< Clear low amplitude detection */
+ TFA9912_BF_ICLVDDP = 0x4670, /*!< Clear VDDP greater then VBAT */
+ TFA9912_BF_ICLTAPDET = 0x4680, /*!< Clear Tap detected */
+ TFA9912_BF_ICLAUDMOD = 0x4690, /*!< Clear Audio Mode activated */
+ TFA9912_BF_ICLSAMMOD = 0x46a0, /*!< Clear SAM Mode activated */
+ TFA9912_BF_ICLTAPMOD = 0x46b0, /*!< Clear Tap Mode Activated */
+ TFA9912_BF_ICLTAPTRG = 0x46c0, /*!< Clear Comparator Interrupt */
+ TFA9912_BF_IEVDDS = 0x4800, /*!< Enable por */
+ TFA9912_BF_IEPLLS = 0x4810, /*!< Enable pll lock */
+ TFA9912_BF_IEOTDS = 0x4820, /*!< Enable OTP alarm */
+ TFA9912_BF_IEOVDS = 0x4830, /*!< Enable OVP alarm */
+ TFA9912_BF_IEUVDS = 0x4840, /*!< Enable UVP alarm */
+ TFA9912_BF_IECLKS = 0x4850, /*!< Enable clocks stable */
+ TFA9912_BF_IEMTPB = 0x4860, /*!< Enable mtp busy */
+ TFA9912_BF_IENOCLK = 0x4870, /*!< Enable lost clk */
+ TFA9912_BF_IESPKS = 0x4880, /*!< Enable speaker error */
+ TFA9912_BF_IEACS = 0x4890, /*!< Enable cold started */
+ TFA9912_BF_IESWS = 0x48a0, /*!< Enable amplifier engage */
+ TFA9912_BF_IEWDS = 0x48b0, /*!< Enable watchdog */
+ TFA9912_BF_IEAMPS = 0x48c0, /*!< Enable enbl amp */
+ TFA9912_BF_IEAREFS = 0x48d0, /*!< Enable ref enable */
+ TFA9912_BF_IEADCCR = 0x48e0, /*!< Enable Control ADC */
+ TFA9912_BF_IEBODNOK = 0x48f0, /*!< Enable BOD */
+ TFA9912_BF_IEBSTCU = 0x4900, /*!< Enable DCDC current limiting */
+ TFA9912_BF_IEBSTHI = 0x4910, /*!< Enable DCDC active */
+ TFA9912_BF_IEBSTOC = 0x4920, /*!< Enable DCDC OCP */
+ TFA9912_BF_IEBSTPC = 0x4930, /*!< Enable bst peakcur */
+ TFA9912_BF_IEBSTVC = 0x4940, /*!< Enable DCDC level 1x */
+ TFA9912_BF_IEBST86 = 0x4950, /*!< Enable DCDC level 1.14x */
+ TFA9912_BF_IEBST93 = 0x4960, /*!< Enable DCDC level 1.07x */
+ TFA9912_BF_IERCVLD = 0x4970, /*!< Enable rcvldop ready */
+ TFA9912_BF_IEOCPL = 0x4980, /*!< Enable ocp alarm left */
+ TFA9912_BF_IEOCPR = 0x4990, /*!< Enable ocp alarm */
+ TFA9912_BF_IEMWSRC = 0x49a0, /*!< Enable waits HW I2C settings */
+ TFA9912_BF_IEMWCFC = 0x49b0, /*!< Enable man wait cf config */
+ TFA9912_BF_IEMWSMU = 0x49c0, /*!< Enable man Audio mute sequence */
+ TFA9912_BF_IECFMER = 0x49d0, /*!< Enable cfma err */
+ TFA9912_BF_IECFMAC = 0x49e0, /*!< Enable cfma ack */
+ TFA9912_BF_IECLKOOR = 0x49f0, /*!< Enable flag_clk_out_of_range */
+ TFA9912_BF_IETDMER = 0x4a00, /*!< Enable tdm error */
+ TFA9912_BF_IECLPL = 0x4a10, /*!< Enable clip left */
+ TFA9912_BF_IECLPR = 0x4a20, /*!< Enable clip */
+ TFA9912_BF_IEOCPM1 = 0x4a30, /*!< Enable mic ocpok */
+ TFA9912_BF_IELP1 = 0x4a50, /*!< Enable low power mode1 */
+ TFA9912_BF_IELA = 0x4a60, /*!< Enable low amplitude detection */
+ TFA9912_BF_IEVDDP = 0x4a70, /*!< Enable VDDP greater than VBAT */
+ TFA9912_BF_IETAPDET = 0x4a80, /*!< Enable Tap detected */
+ TFA9912_BF_IEAUDMOD = 0x4a90, /*!< Enable Audio Mode activated */
+ TFA9912_BF_IESAMMOD = 0x4aa0, /*!< Enable SAM Mode activated */
+ TFA9912_BF_IETAPMOD = 0x4ab0, /*!< Enable Tap Mode Activated */
+ TFA9912_BF_IETAPTRG = 0x4ac0, /*!< Enable comparator interrupt */
+ TFA9912_BF_IPOVDDS = 0x4c00, /*!< Polarity por */
+ TFA9912_BF_IPOPLLS = 0x4c10, /*!< Polarity pll lock */
+ TFA9912_BF_IPOOTDS = 0x4c20, /*!< Polarity OTP alarm */
+ TFA9912_BF_IPOOVDS = 0x4c30, /*!< Polarity OVP alarm */
+ TFA9912_BF_IPOUVDS = 0x4c40, /*!< Polarity UVP alarm */
+ TFA9912_BF_IPOCLKS = 0x4c50, /*!< Polarity clocks stable */
+ TFA9912_BF_IPOMTPB = 0x4c60, /*!< Polarity mtp busy */
+ TFA9912_BF_IPONOCLK = 0x4c70, /*!< Polarity lost clk */
+ TFA9912_BF_IPOSPKS = 0x4c80, /*!< Polarity speaker error */
+ TFA9912_BF_IPOACS = 0x4c90, /*!< Polarity cold started */
+ TFA9912_BF_IPOSWS = 0x4ca0, /*!< Polarity amplifier engage */
+ TFA9912_BF_IPOWDS = 0x4cb0, /*!< Polarity watchdog */
+ TFA9912_BF_IPOAMPS = 0x4cc0, /*!< Polarity enbl amp */
+ TFA9912_BF_IPOAREFS = 0x4cd0, /*!< Polarity ref enable */
+ TFA9912_BF_IPOADCCR = 0x4ce0, /*!< Polarity Control ADC */
+ TFA9912_BF_IPOBODNOK = 0x4cf0, /*!< Polarity BOD */
+ TFA9912_BF_IPOBSTCU = 0x4d00, /*!< Polarity DCDC current limiting */
+ TFA9912_BF_IPOBSTHI = 0x4d10, /*!< Polarity DCDC active */
+ TFA9912_BF_IPOBSTOC = 0x4d20, /*!< Polarity DCDC OCP */
+ TFA9912_BF_IPOBSTPC = 0x4d30, /*!< Polarity bst peakcur */
+ TFA9912_BF_IPOBSTVC = 0x4d40, /*!< Polarity DCDC level 1x */
+ TFA9912_BF_IPOBST86 = 0x4d50, /*!< Polarity DCDC level 1.14x */
+ TFA9912_BF_IPOBST93 = 0x4d60, /*!< Polarity DCDC level 1.07x */
+ TFA9912_BF_IPORCVLD = 0x4d70, /*!< Polarity rcvldop ready */
+ TFA9912_BF_IPOOCPL = 0x4d80, /*!< Polarity ocp alarm left */
+ TFA9912_BF_IPOOCPR = 0x4d90, /*!< Polarity ocp alarm */
+ TFA9912_BF_IPOMWSRC = 0x4da0, /*!< Polarity waits HW I2C settings */
+ TFA9912_BF_IPOMWCFC = 0x4db0, /*!< Polarity man wait cf config */
+ TFA9912_BF_IPOMWSMU = 0x4dc0, /*!< Polarity man audio mute sequence */
+ TFA9912_BF_IPOCFMER = 0x4dd0, /*!< Polarity cfma err */
+ TFA9912_BF_IPOCFMAC = 0x4de0, /*!< Polarity cfma ack */
+ TFA9912_BF_IPOCLKOOR = 0x4df0, /*!< Polarity flag_clk_out_of_range */
+ TFA9912_BF_IPOTDMER = 0x4e00, /*!< Polarity tdm error */
+ TFA9912_BF_IPOCLPL = 0x4e10, /*!< Polarity clip left */
+ TFA9912_BF_IPOCLPR = 0x4e20, /*!< Polarity clip */
+ TFA9912_BF_IPOOCPM = 0x4e30, /*!< Polarity mic ocpok */
+ TFA9912_BF_IPOLP1 = 0x4e50, /*!< Polarity low power mode1 */
+ TFA9912_BF_IPOLA = 0x4e60, /*!< Polarity low amplitude detection */
+ TFA9912_BF_IPOVDDP = 0x4e70, /*!< Polarity VDDP greater than VBAT */
+ TFA9912_BF_IPOLTAPDET = 0x4e80, /*!< PolarityTap detected */
+ TFA9912_BF_IPOLAUDMOD = 0x4e90, /*!< PolarityAudio Mode activated */
+ TFA9912_BF_IPOLSAMMOD = 0x4ea0, /*!< PolaritySAM Mode activated */
+ TFA9912_BF_IPOLTAPMOD = 0x4eb0, /*!< Polarity Tap Mode Activated */
+ TFA9912_BF_IPOLTAPTRG = 0x4ec0, /*!< PolarityTap Comparator Trigger */
+ TFA9912_BF_BSSCR = 0x5001, /*!< Battery Safeguard attack time */
+ TFA9912_BF_BSST = 0x5023, /*!< Battery Safeguard threshold voltage level */
+ TFA9912_BF_BSSRL = 0x5061, /*!< Battery Safeguard maximum reduction */
+ TFA9912_BF_BSSRR = 0x5082, /*!< Battery Safeguard release time */
+ TFA9912_BF_BSSHY = 0x50b1, /*!< Battery Safeguard hysteresis */
+ TFA9912_BF_BSSAC = 0x50d0, /*!< Reset clipper - Auto clear */
+ TFA9912_BF_BSSR = 0x50e0, /*!< Battery voltage read out */
+ TFA9912_BF_BSSBY = 0x50f0, /*!< Bypass HW clipper */
+ TFA9912_BF_BSSS = 0x5100, /*!< Vbat prot steepness */
+ TFA9912_BF_INTSMUTE = 0x5110, /*!< Soft mute HW */
+ TFA9912_BF_CFSML = 0x5120, /*!< Soft mute FW left */
+ TFA9912_BF_CFSM = 0x5130, /*!< Soft mute FW */
+ TFA9912_BF_HPFBYPL = 0x5140, /*!< Bypass HPF left */
+ TFA9912_BF_HPFBYP = 0x5150, /*!< Bypass HPF */
+ TFA9912_BF_DPSAL = 0x5160, /*!< Enable DPSA left */
+ TFA9912_BF_DPSA = 0x5170, /*!< Enable DPSA */
+ TFA9912_BF_VOL = 0x5187, /*!< FW volume control for primary audio channel */
+ TFA9912_BF_HNDSFRCV = 0x5200, /*!< Selection receiver */
+ TFA9912_BF_CLIPCTRL = 0x5222, /*!< Clip control setting */
+ TFA9912_BF_AMPGAIN = 0x5257, /*!< Amplifier gain */
+ TFA9912_BF_SLOPEE = 0x52d0, /*!< Enables slope control */
+ TFA9912_BF_SLOPESET = 0x52e0, /*!< Slope speed setting (bin. coded) */
+ TFA9912_BF_CFTAPPAT = 0x5c07, /*!< Coolflux tap pattern */
+ TFA9912_BF_TAPDBGINFO = 0x5c83, /*!< Reserved */
+ TFA9912_BF_TATPSTAT1 = 0x5d0f, /*!< Tap Status 1 from CF FW */
+ TFA9912_BF_TCOMPTHR = 0x5f03, /*!< Comparator threshold (in uV) */
+ TFA9912_BF_PGAGAIN = 0x6081, /*!< PGA gain selection */
+ TFA9912_BF_TDMSPKG = 0x6123, /*!< System gain (INPLEV 0) */
+ TFA9912_BF_LPM1LVL = 0x6505, /*!< low power mode1 detector ctrl threshold for low_audio_lvl */
+ TFA9912_BF_LPM1HLD = 0x6565, /*!< Low power mode1 detector, ctrl hold time before low audio is reckoned to be low audio */
+ TFA9912_BF_LPM1DIS = 0x65c0, /*!< low power mode1 detector control */
+ TFA9912_BF_DCDIS = 0x6630, /*!< DCDC */
+ TFA9912_BF_TDMSRCMAP = 0x6801, /*!< tdm source mapping */
+ TFA9912_BF_TDMSRCAS = 0x6821, /*!< frame a selection */
+ TFA9912_BF_TDMSRCBS = 0x6841, /*!< frame b selection */
+ TFA9912_BF_ANC1C = 0x68a0, /*!< ANC one s complement */
+ TFA9912_BF_SAMMODE = 0x6901, /*!< Sam mode */
+ TFA9912_BF_DCMCC = 0x7033, /*!< Max coil current */
+ TFA9912_BF_DCCV = 0x7071, /*!< Slope compensation current, represents LxF (inductance x frequency) value */
+ TFA9912_BF_DCIE = 0x7090, /*!< Adaptive boost mode */
+ TFA9912_BF_DCSR = 0x70a0, /*!< Soft ramp up/down */
+ TFA9912_BF_DCINSEL = 0x70c1, /*!< DCDC IIR input Selection */
+ TFA9912_BF_DCPWM = 0x70f0, /*!< DCDC PWM only mode */
+ TFA9912_BF_DCTRIP = 0x7504, /*!< Adaptive boost trip levels 1, effective only when boost_intelligent is set to 1 */
+ TFA9912_BF_DCTRIP2 = 0x7554, /*!< Adaptive boost trip level 2, effective only when boost_intelligent is set to 1 */
+ TFA9912_BF_DCTRIPT = 0x75a4, /*!< Adaptive boost trip levels, effective only when boost_intelligent is set to 1 */
+ TFA9912_BF_DCVOF = 0x7635, /*!< First boost voltage level */
+ TFA9912_BF_DCVOS = 0x7695, /*!< Second boost voltage level */
+ TFA9912_BF_RST = 0x9000, /*!< Reset */
+ TFA9912_BF_DMEM = 0x9011, /*!< Target memory */
+ TFA9912_BF_AIF = 0x9030, /*!< Auto increment */
+ TFA9912_BF_CFINT = 0x9040, /*!< Interrupt - auto clear */
+ TFA9912_BF_CFCGATE = 0x9050, /*!< Coolflux clock gating disabling control */
+ TFA9912_BF_REQCMD = 0x9080, /*!< Firmware event request rpc command */
+ TFA9912_BF_REQRST = 0x9090, /*!< Firmware event request reset restart */
+ TFA9912_BF_REQMIPS = 0x90a0, /*!< Firmware event request short on mips */
+ TFA9912_BF_REQMUTED = 0x90b0, /*!< Firmware event request mute sequence ready */
+ TFA9912_BF_REQVOL = 0x90c0, /*!< Firmware event request volume ready */
+ TFA9912_BF_REQDMG = 0x90d0, /*!< Firmware event request speaker damage detected */
+ TFA9912_BF_REQCAL = 0x90e0, /*!< Firmware event request calibration completed */
+ TFA9912_BF_REQRSV = 0x90f0, /*!< Firmware event request reserved */
+ TFA9912_BF_MADD = 0x910f, /*!< Memory address */
+ TFA9912_BF_MEMA = 0x920f, /*!< Activate memory access */
+ TFA9912_BF_ERR = 0x9307, /*!< Error flags */
+ TFA9912_BF_ACKCMD = 0x9380, /*!< Firmware event acknowledge rpc command */
+ TFA9912_BF_ACKRST = 0x9390, /*!< Firmware event acknowledge reset restart */
+ TFA9912_BF_ACKMIPS = 0x93a0, /*!< Firmware event acknowledge short on mips */
+ TFA9912_BF_ACKMUTED = 0x93b0, /*!< Firmware event acknowledge mute sequence ready */
+ TFA9912_BF_ACKVOL = 0x93c0, /*!< Firmware event acknowledge volume ready */
+ TFA9912_BF_ACKDMG = 0x93d0, /*!< Firmware event acknowledge speaker damage detected */
+ TFA9912_BF_ACKCAL = 0x93e0, /*!< Firmware event acknowledge calibration completed */
+ TFA9912_BF_ACKRSV = 0x93f0, /*!< Firmware event acknowledge reserved */
+ TFA9912_BF_MTPK = 0xa107, /*!< MTP KEY2 register */
+ TFA9912_BF_KEY1LOCKED = 0xa200, /*!< Indicates KEY1 is locked */
+ TFA9912_BF_KEY2LOCKED = 0xa210, /*!< Indicates KEY2 is locked */
+ TFA9912_BF_CIMTP = 0xa360, /*!< Start copying data from I2C mtp registers to mtp */
+ TFA9912_BF_MTPRDMSB = 0xa50f, /*!< MSB word of MTP manual read data */
+ TFA9912_BF_MTPRDLSB = 0xa60f, /*!< LSB word of MTP manual read data */
+ TFA9912_BF_EXTTS = 0xb108, /*!< External temperature (C) */
+ TFA9912_BF_TROS = 0xb190, /*!< Select temp Speaker calibration */
+ TFA9912_BF_SWPROFIL = 0xee0f, /*!< Software profile data */
+ TFA9912_BF_SWVSTEP = 0xef0f, /*!< Software vstep information */
+ TFA9912_BF_MTPOTC = 0xf000, /*!< Calibration schedule */
+ TFA9912_BF_MTPEX = 0xf010, /*!< Calibration Ron executed */
+ TFA9912_BF_DCMCCAPI = 0xf020, /*!< Calibration current limit DCDC */
+ TFA9912_BF_DCMCCSB = 0xf030, /*!< Sign bit for delta calibration current limit DCDC */
+ TFA9912_BF_DCMCCCL = 0xf042, /*!< Calibration delta current limit DCDC */
+ TFA9912_BF_USERDEF = 0xf078, /*!< Reserved space for allowing customer to store speaker information */
+ TFA9912_BF_R25C = 0xf40f, /*!< Ron resistance of speaker coil */
+} nxpTfa9912BfEnumList_t;
+#define TFA9912_NAMETABLE static tfaBfName_t Tfa9912DatasheetNames[] = {\
+ { 0x0, "PWDN"}, /* Powerdown selection , */\
+ { 0x10, "I2CR"}, /* I2C Reset - Auto clear , */\
+ { 0x20, "CFE"}, /* Enable CoolFlux , */\
+ { 0x30, "AMPE"}, /* Enables the Amplifier , */\
+ { 0x40, "DCA"}, /* Activate DC-to-DC converter , */\
+ { 0x50, "SBSL"}, /* Coolflux configured , */\
+ { 0x60, "AMPC"}, /* CoolFlux controls amplifier , */\
+ { 0x71, "INTP"}, /* Interrupt config , */\
+ { 0x90, "FSSSEL"}, /* Audio sample reference , */\
+ { 0xb0, "BYPOCP"}, /* Bypass OCP , */\
+ { 0xc0, "TSTOCP"}, /* OCP testing control , */\
+ { 0x101, "AMPINSEL"}, /* Amplifier input selection , */\
+ { 0x120, "MANSCONF"}, /* I2C configured , */\
+ { 0x130, "MANCOLD"}, /* Execute cold start , */\
+ { 0x140, "MANAOOSC"}, /* Internal osc off at PWDN , */\
+ { 0x150, "MANROBOD"}, /* Reaction on BOD , */\
+ { 0x160, "BODE"}, /* BOD Enable , */\
+ { 0x170, "BODHYS"}, /* BOD Hysteresis , */\
+ { 0x181, "BODFILT"}, /* BOD filter , */\
+ { 0x1a1, "BODTHLVL"}, /* BOD threshold , */\
+ { 0x1d0, "MUTETO"}, /* Time out SB mute sequence , */\
+ { 0x1e0, "RCVNS"}, /* Noise shaper selection , */\
+ { 0x1f0, "MANWDE"}, /* Watchdog enable , */\
+ { 0x203, "AUDFS"}, /* Sample rate (fs) , */\
+ { 0x240, "INPLEV"}, /* TDM output attenuation , */\
+ { 0x255, "FRACTDEL"}, /* V/I Fractional delay , */\
+ { 0x2b0, "BYPHVBF"}, /* Bypass HVBAT filter , */\
+ { 0x2c0, "TDMC"}, /* TDM Compatibility with TFA9872 , */\
+ { 0x2e0, "ENBLADC10"}, /* ADC10 Enable - I2C direct mode , */\
+ { 0x30f, "REV"}, /* Revision info , */\
+ { 0x401, "REFCKEXT"}, /* PLL external ref clock , */\
+ { 0x420, "REFCKSEL"}, /* PLL internal ref clock , */\
+ { 0x430, "ENCFCKSEL"}, /* Coolflux DSP clock scaling, low power mode , */\
+ { 0x441, "CFCKSEL"}, /* Coolflux DSP clock scaler selection for low power mode, */\
+ { 0x460, "TDMINFSEL"}, /* TDM clock selection , */\
+ { 0x470, "DISBLAUTOCLKSEL"}, /* Disable Automatic dsp clock source selection , */\
+ { 0x480, "SELCLKSRC"}, /* I2C selection of DSP clock when auto select is disabled, */\
+ { 0x490, "SELTIMSRC"}, /* I2C selection of Watchdog and Timer clock , */\
+ { 0x500, "SSLEFTE"}, /* , */\
+ { 0x510, "SPKSSEN"}, /* Enable speaker path , */\
+ { 0x520, "VSLEFTE"}, /* , */\
+ { 0x530, "VSRIGHTE"}, /* Voltage sense , */\
+ { 0x540, "CSLEFTE"}, /* , */\
+ { 0x550, "CSRIGHTE"}, /* Current sense , */\
+ { 0x560, "SSPDME"}, /* Sub-system PDM , */\
+ { 0x570, "PGALE"}, /* Enable PGA chop clock for left channel , */\
+ { 0x580, "PGARE"}, /* Enable PGA chop clock , */\
+ { 0x590, "SSTDME"}, /* Sub-system TDM , */\
+ { 0x5a0, "SSPBSTE"}, /* Sub-system boost , */\
+ { 0x5b0, "SSADCE"}, /* Sub-system ADC , */\
+ { 0x5c0, "SSFAIME"}, /* Sub-system FAIM , */\
+ { 0x5d0, "SSCFTIME"}, /* CF Sub-system timer , */\
+ { 0x5e0, "SSCFWDTE"}, /* CF Sub-system WDT , */\
+ { 0x5f0, "FAIMVBGOVRRL"}, /* Over rule of vbg for FaIM access , */\
+ { 0x600, "SAMSPKSEL"}, /* Input selection for TAP/SAM , */\
+ { 0x610, "PDM2IISEN"}, /* PDM2IIS Bridge enable , */\
+ { 0x620, "TAPRSTBYPASS"}, /* Tap decimator reset bypass - Bypass the decimator reset from tapdec, */\
+ { 0x631, "CARDECISEL0"}, /* Cardec input 0 sel , */\
+ { 0x651, "CARDECISEL1"}, /* Cardec input sel , */\
+ { 0x670, "TAPDECSEL"}, /* Select TAP/Cardec for TAP , */\
+ { 0x680, "COMPCOUNT"}, /* Comparator o/p filter selection , */\
+ { 0x691, "STARTUPMODE"}, /* Startup Mode Selection , */\
+ { 0x6b0, "AUTOTAP"}, /* Enable auto tap switching , */\
+ { 0x6c1, "COMPINITIME"}, /* Comparator initialization time to be used in Tap Machine, */\
+ { 0x6e1, "ANAPINITIME"}, /* Analog initialization time to be used in Tap Machine, */\
+ { 0x707, "CCHKTH"}, /* Clock check Higher Threshold , */\
+ { 0x787, "CCHKTL"}, /* Clock check Higher Threshold , */\
+ { 0x802, "AMPOCRT"}, /* Amplifier on-off criteria for shutdown , */\
+ { 0x832, "AMPTCRR"}, /* Amplifier on-off criteria for tap mode entry , */\
+ { 0xd00, "STGS"}, /* PDM side tone gain selector , */\
+ { 0xd18, "STGAIN"}, /* Side tone gain , */\
+ { 0xda0, "STSMUTE"}, /* Side tone soft mute , */\
+ { 0xdb0, "ST1C"}, /* side tone one s complement , */\
+ { 0xe80, "CMFBEL"}, /* CMFB enable left , */\
+ { 0x1000, "VDDS"}, /* POR , */\
+ { 0x1010, "PLLS"}, /* PLL lock , */\
+ { 0x1020, "OTDS"}, /* OTP alarm , */\
+ { 0x1030, "OVDS"}, /* OVP alarm , */\
+ { 0x1040, "UVDS"}, /* UVP alarm , */\
+ { 0x1050, "CLKS"}, /* Clocks stable , */\
+ { 0x1060, "MTPB"}, /* MTP busy , */\
+ { 0x1070, "NOCLK"}, /* Lost clock , */\
+ { 0x1090, "ACS"}, /* Cold Start , */\
+ { 0x10a0, "SWS"}, /* Amplifier engage , */\
+ { 0x10b0, "WDS"}, /* Watchdog , */\
+ { 0x10c0, "AMPS"}, /* Amplifier enable , */\
+ { 0x10d0, "AREFS"}, /* References enable , */\
+ { 0x10e0, "ADCCR"}, /* Control ADC , */\
+ { 0x10f0, "BODNOK"}, /* BOD , */\
+ { 0x1100, "DCIL"}, /* DCDC current limiting , */\
+ { 0x1110, "DCDCA"}, /* DCDC active , */\
+ { 0x1120, "DCOCPOK"}, /* DCDC OCP nmos , */\
+ { 0x1130, "DCPEAKCUR"}, /* Indicates current is max in DC-to-DC converter , */\
+ { 0x1140, "DCHVBAT"}, /* DCDC level 1x , */\
+ { 0x1150, "DCH114"}, /* DCDC level 1.14x , */\
+ { 0x1160, "DCH107"}, /* DCDC level 1.07x , */\
+ { 0x1170, "STMUTEB"}, /* side tone (un)mute busy , */\
+ { 0x1180, "STMUTE"}, /* side tone mute state , */\
+ { 0x1190, "TDMLUTER"}, /* TDM LUT error , */\
+ { 0x11a2, "TDMSTAT"}, /* TDM status bits , */\
+ { 0x11d0, "TDMERR"}, /* TDM error , */\
+ { 0x11e0, "HAPTIC"}, /* Status haptic driver , */\
+ { 0x1300, "OCPOAP"}, /* OCPOK pmos A , */\
+ { 0x1310, "OCPOAN"}, /* OCPOK nmos A , */\
+ { 0x1320, "OCPOBP"}, /* OCPOK pmos B , */\
+ { 0x1330, "OCPOBN"}, /* OCPOK nmos B , */\
+ { 0x1340, "CLIPAH"}, /* Clipping A to Vddp , */\
+ { 0x1350, "CLIPAL"}, /* Clipping A to gnd , */\
+ { 0x1360, "CLIPBH"}, /* Clipping B to Vddp , */\
+ { 0x1370, "CLIPBL"}, /* Clipping B to gnd , */\
+ { 0x1380, "OCDS"}, /* OCP amplifier , */\
+ { 0x1390, "CLIPS"}, /* Amplifier clipping , */\
+ { 0x13a0, "TCMPTRG"}, /* Status Tap comparator triggered , */\
+ { 0x13b0, "TAPDET"}, /* Status Tap detected , */\
+ { 0x13c0, "MANWAIT1"}, /* Wait HW I2C settings , */\
+ { 0x13d0, "MANWAIT2"}, /* Wait CF config , */\
+ { 0x13e0, "MANMUTE"}, /* Audio mute sequence , */\
+ { 0x13f0, "MANOPER"}, /* Operating state , */\
+ { 0x1400, "SPKSL"}, /* Left speaker status , */\
+ { 0x1410, "SPKS"}, /* Speaker status , */\
+ { 0x1420, "CLKOOR"}, /* External clock status , */\
+ { 0x1433, "MANSTATE"}, /* Device manager status , */\
+ { 0x1471, "DCMODE"}, /* DCDC mode status bits , */\
+ { 0x1490, "DSPCLKSRC"}, /* DSP clock source selected by manager , */\
+ { 0x14a1, "STARTUPMODSTAT"}, /* Startup Mode Selected by Manager(Read Only) , */\
+ { 0x14c3, "TSPMSTATE"}, /* Tap Machine State , */\
+ { 0x1509, "BATS"}, /* Battery voltage (V) , */\
+ { 0x1608, "TEMPS"}, /* IC Temperature (C) , */\
+ { 0x1709, "VDDPS"}, /* IC VDDP voltage ( 1023*VDDP/13 V) , */\
+ { 0x17a0, "DCILCF"}, /* DCDC current limiting for DSP , */\
+ { 0x2000, "TDMUC"}, /* Mode setting , */\
+ { 0x2011, "DIO4SEL"}, /* DIO4 Input selection , */\
+ { 0x2040, "TDME"}, /* Enable TDM interface , */\
+ { 0x2050, "TDMMODE"}, /* Slave/master , */\
+ { 0x2060, "TDMCLINV"}, /* Reception data to BCK clock , */\
+ { 0x2073, "TDMFSLN"}, /* FS length , */\
+ { 0x20b0, "TDMFSPOL"}, /* FS polarity , */\
+ { 0x20c3, "TDMNBCK"}, /* N-BCK's in FS , */\
+ { 0x2103, "TDMSLOTS"}, /* N-slots in Frame , */\
+ { 0x2144, "TDMSLLN"}, /* N-bits in slot , */\
+ { 0x2194, "TDMBRMG"}, /* N-bits remaining , */\
+ { 0x21e0, "TDMDEL"}, /* data delay to FS , */\
+ { 0x21f0, "TDMADJ"}, /* data adjustment , */\
+ { 0x2201, "TDMOOMP"}, /* Received audio compression , */\
+ { 0x2224, "TDMSSIZE"}, /* Sample size per slot , */\
+ { 0x2271, "TDMTXDFO"}, /* Format unused bits in a slot , */\
+ { 0x2291, "TDMTXUS0"}, /* Format unused slots GAINIO , */\
+ { 0x22b1, "TDMTXUS1"}, /* Format unused slots DIO1 , */\
+ { 0x22d1, "TDMTXUS2"}, /* Format unused slots DIO2 , */\
+ { 0x2300, "TDMGIE"}, /* Control gain (channel in 0) , */\
+ { 0x2310, "TDMDCE"}, /* Control audio left (channel in 1 ) , */\
+ { 0x2320, "TDMSPKE"}, /* Control audio right (channel in 2 ) , */\
+ { 0x2330, "TDMCSE"}, /* Current sense , */\
+ { 0x2340, "TDMVSE"}, /* Voltage sense , */\
+ { 0x2350, "TDMGOE"}, /* DSP Gainout , */\
+ { 0x2360, "TDMCF2E"}, /* DSP 2 , */\
+ { 0x2370, "TDMCF3E"}, /* DSP 3 , */\
+ { 0x2380, "TDMCFE"}, /* DSP , */\
+ { 0x2390, "TDMES6"}, /* Loopback of Audio left (channel 1) , */\
+ { 0x23a0, "TDMES7"}, /* Loopback of Audio right (channel 2) , */\
+ { 0x23b0, "TDMCF4E"}, /* AEC ref right control , */\
+ { 0x23c0, "TDMPD1E"}, /* PDM 1 control , */\
+ { 0x23d0, "TDMPD2E"}, /* PDM 2 control , */\
+ { 0x2401, "TDMGIN"}, /* IO gainin , */\
+ { 0x2421, "TDMLIO"}, /* IO audio left , */\
+ { 0x2441, "TDMRIO"}, /* IO audio right , */\
+ { 0x2461, "TDMCSIO"}, /* IO Current Sense , */\
+ { 0x2481, "TDMVSIO"}, /* IO voltage sense , */\
+ { 0x24a1, "TDMGOIO"}, /* IO gain out , */\
+ { 0x24c1, "TDMCFIO2"}, /* IO DSP 2 , */\
+ { 0x24e1, "TDMCFIO3"}, /* IO DSP 3 , */\
+ { 0x2501, "TDMCFIO"}, /* IO DSP , */\
+ { 0x2521, "TDMLPB6"}, /* IO Source 6 , */\
+ { 0x2541, "TDMLPB7"}, /* IO Source 7 , */\
+ { 0x2603, "TDMGS"}, /* Control gainin , */\
+ { 0x2643, "TDMDCS"}, /* tdm slot for audio left (channel 1) , */\
+ { 0x2683, "TDMSPKS"}, /* tdm slot for audio right (channel 2) , */\
+ { 0x26c3, "TDMCSS"}, /* Slot Position of Current Sense Out , */\
+ { 0x2703, "TDMVSS"}, /* Slot Position of Voltage sense , */\
+ { 0x2743, "TDMCGOS"}, /* Slot Position of GAIN out , */\
+ { 0x2783, "TDMCF2S"}, /* Slot Position DSPout2 , */\
+ { 0x27c3, "TDMCF3S"}, /* Slot Position DSPout3 , */\
+ { 0x2803, "TDMCFS"}, /* Slot Position of DSPout , */\
+ { 0x2843, "TDMEDAT6S"}, /* Slot Position of loopback channel left , */\
+ { 0x2883, "TDMEDAT7S"}, /* Slot Position of loopback channel right , */\
+ { 0x2901, "TDMTXUS3"}, /* Format unused slots D3 , */\
+ { 0x3100, "PDMSM"}, /* PDM control , */\
+ { 0x3110, "PDMSTSEL"}, /* PDM Decimator input selection , */\
+ { 0x3120, "PDMSTENBL"}, /* Side tone input enable , */\
+ { 0x3130, "PDMLSEL"}, /* PDM data selection for left channel during PDM direct mode, */\
+ { 0x3140, "PDMRSEL"}, /* PDM data selection for right channel during PDM direct mode, */\
+ { 0x3150, "MICVDDE"}, /* Enable MICVDD , */\
+ { 0x3201, "PDMCLRAT"}, /* PDM BCK/Fs ratio , */\
+ { 0x3223, "PDMGAIN"}, /* PDM gain , */\
+ { 0x3263, "PDMOSEL"}, /* PDM output selection - RE/FE data combination , */\
+ { 0x32a0, "SELCFHAPD"}, /* Select the source for haptic data output (not for customer), */\
+ { 0x4000, "ISTVDDS"}, /* Status POR , */\
+ { 0x4010, "ISTPLLS"}, /* Status PLL lock , */\
+ { 0x4020, "ISTOTDS"}, /* Status OTP alarm , */\
+ { 0x4030, "ISTOVDS"}, /* Status OVP alarm , */\
+ { 0x4040, "ISTUVDS"}, /* Status UVP alarm , */\
+ { 0x4050, "ISTCLKS"}, /* Status clocks stable , */\
+ { 0x4060, "ISTMTPB"}, /* Status MTP busy , */\
+ { 0x4070, "ISTNOCLK"}, /* Status lost clock , */\
+ { 0x4080, "ISTSPKS"}, /* Status speaker error , */\
+ { 0x4090, "ISTACS"}, /* Status cold start , */\
+ { 0x40a0, "ISTSWS"}, /* Status amplifier engage , */\
+ { 0x40b0, "ISTWDS"}, /* Status watchdog , */\
+ { 0x40c0, "ISTAMPS"}, /* Status amplifier enable , */\
+ { 0x40d0, "ISTAREFS"}, /* Status Ref enable , */\
+ { 0x40e0, "ISTADCCR"}, /* Status Control ADC , */\
+ { 0x40f0, "ISTBODNOK"}, /* Status BOD , */\
+ { 0x4100, "ISTBSTCU"}, /* Status DCDC current limiting , */\
+ { 0x4110, "ISTBSTHI"}, /* Status DCDC active , */\
+ { 0x4120, "ISTBSTOC"}, /* Status DCDC OCP , */\
+ { 0x4130, "ISTBSTPKCUR"}, /* Status bst peakcur , */\
+ { 0x4140, "ISTBSTVC"}, /* Status DCDC level 1x , */\
+ { 0x4150, "ISTBST86"}, /* Status DCDC level 1.14x , */\
+ { 0x4160, "ISTBST93"}, /* Status DCDC level 1.07x , */\
+ { 0x4170, "ISTRCVLD"}, /* Status rcvldop ready , */\
+ { 0x4180, "ISTOCPL"}, /* Status ocp alarm left , */\
+ { 0x4190, "ISTOCPR"}, /* Status ocp alarm , */\
+ { 0x41a0, "ISTMWSRC"}, /* Status Waits HW I2C settings , */\
+ { 0x41b0, "ISTMWCFC"}, /* Status waits CF config , */\
+ { 0x41c0, "ISTMWSMU"}, /* Status Audio mute sequence , */\
+ { 0x41d0, "ISTCFMER"}, /* Status cfma error , */\
+ { 0x41e0, "ISTCFMAC"}, /* Status cfma ack , */\
+ { 0x41f0, "ISTCLKOOR"}, /* Status flag_clk_out_of_range , */\
+ { 0x4200, "ISTTDMER"}, /* Status tdm error , */\
+ { 0x4210, "ISTCLPL"}, /* Status clip left , */\
+ { 0x4220, "ISTCLPR"}, /* Status clip , */\
+ { 0x4230, "ISTOCPM"}, /* Status mic ocpok , */\
+ { 0x4250, "ISTLP1"}, /* Status low power mode1 , */\
+ { 0x4260, "ISTLA"}, /* Status low amplitude detection , */\
+ { 0x4270, "ISTVDDP"}, /* Status VDDP greater than VBAT , */\
+ { 0x4280, "ISTTAPDET"}, /* Status Tap detected , */\
+ { 0x4290, "ISTAUDMOD"}, /* Status Audio Mode activated , */\
+ { 0x42a0, "ISTSAMMOD"}, /* Status SAM Mode activated , */\
+ { 0x42b0, "ISTTAPMOD"}, /* Status Tap Mode Activated , */\
+ { 0x42c0, "ISTTAPTRG"}, /* Status Tap comparator triggered , */\
+ { 0x4400, "ICLVDDS"}, /* Clear POR , */\
+ { 0x4410, "ICLPLLS"}, /* Clear PLL lock , */\
+ { 0x4420, "ICLOTDS"}, /* Clear OTP alarm , */\
+ { 0x4430, "ICLOVDS"}, /* Clear OVP alarm , */\
+ { 0x4440, "ICLUVDS"}, /* Clear UVP alarm , */\
+ { 0x4450, "ICLCLKS"}, /* Clear clocks stable , */\
+ { 0x4460, "ICLMTPB"}, /* Clear mtp busy , */\
+ { 0x4470, "ICLNOCLK"}, /* Clear lost clk , */\
+ { 0x4480, "ICLSPKS"}, /* Clear speaker error , */\
+ { 0x4490, "ICLACS"}, /* Clear cold started , */\
+ { 0x44a0, "ICLSWS"}, /* Clear amplifier engage , */\
+ { 0x44b0, "ICLWDS"}, /* Clear watchdog , */\
+ { 0x44c0, "ICLAMPS"}, /* Clear enbl amp , */\
+ { 0x44d0, "ICLAREFS"}, /* Clear ref enable , */\
+ { 0x44e0, "ICLADCCR"}, /* Clear control ADC , */\
+ { 0x44f0, "ICLBODNOK"}, /* Clear BOD , */\
+ { 0x4500, "ICLBSTCU"}, /* Clear DCDC current limiting , */\
+ { 0x4510, "ICLBSTHI"}, /* Clear DCDC active , */\
+ { 0x4520, "ICLBSTOC"}, /* Clear DCDC OCP , */\
+ { 0x4530, "ICLBSTPC"}, /* Clear bst peakcur , */\
+ { 0x4540, "ICLBSTVC"}, /* Clear DCDC level 1x , */\
+ { 0x4550, "ICLBST86"}, /* Clear DCDC level 1.14x , */\
+ { 0x4560, "ICLBST93"}, /* Clear DCDC level 1.07x , */\
+ { 0x4570, "ICLRCVLD"}, /* Clear rcvldop ready , */\
+ { 0x4580, "ICLOCPL"}, /* Clear ocp alarm left , */\
+ { 0x4590, "ICLOCPR"}, /* Clear ocp alarm , */\
+ { 0x45a0, "ICLMWSRC"}, /* Clear wait HW I2C settings , */\
+ { 0x45b0, "ICLMWCFC"}, /* Clear wait cf config , */\
+ { 0x45c0, "ICLMWSMU"}, /* Clear audio mute sequence , */\
+ { 0x45d0, "ICLCFMER"}, /* Clear cfma err , */\
+ { 0x45e0, "ICLCFMAC"}, /* Clear cfma ack , */\
+ { 0x45f0, "ICLCLKOOR"}, /* Clear flag_clk_out_of_range , */\
+ { 0x4600, "ICLTDMER"}, /* Clear tdm error , */\
+ { 0x4610, "ICLCLPL"}, /* Clear clip left , */\
+ { 0x4620, "ICLCLP"}, /* Clear clip , */\
+ { 0x4630, "ICLOCPM"}, /* Clear mic ocpok , */\
+ { 0x4650, "ICLLP1"}, /* Clear low power mode1 , */\
+ { 0x4660, "ICLLA"}, /* Clear low amplitude detection , */\
+ { 0x4670, "ICLVDDP"}, /* Clear VDDP greater then VBAT , */\
+ { 0x4680, "ICLTAPDET"}, /* Clear Tap detected , */\
+ { 0x4690, "ICLAUDMOD"}, /* Clear Audio Mode activated , */\
+ { 0x46a0, "ICLSAMMOD"}, /* Clear SAM Mode activated , */\
+ { 0x46b0, "ICLTAPMOD"}, /* Clear Tap Mode Activated , */\
+ { 0x46c0, "ICLTAPTRG"}, /* Clear Comparator Interrupt , */\
+ { 0x4800, "IEVDDS"}, /* Enable por , */\
+ { 0x4810, "IEPLLS"}, /* Enable pll lock , */\
+ { 0x4820, "IEOTDS"}, /* Enable OTP alarm , */\
+ { 0x4830, "IEOVDS"}, /* Enable OVP alarm , */\
+ { 0x4840, "IEUVDS"}, /* Enable UVP alarm , */\
+ { 0x4850, "IECLKS"}, /* Enable clocks stable , */\
+ { 0x4860, "IEMTPB"}, /* Enable mtp busy , */\
+ { 0x4870, "IENOCLK"}, /* Enable lost clk , */\
+ { 0x4880, "IESPKS"}, /* Enable speaker error , */\
+ { 0x4890, "IEACS"}, /* Enable cold started , */\
+ { 0x48a0, "IESWS"}, /* Enable amplifier engage , */\
+ { 0x48b0, "IEWDS"}, /* Enable watchdog , */\
+ { 0x48c0, "IEAMPS"}, /* Enable enbl amp , */\
+ { 0x48d0, "IEAREFS"}, /* Enable ref enable , */\
+ { 0x48e0, "IEADCCR"}, /* Enable Control ADC , */\
+ { 0x48f0, "IEBODNOK"}, /* Enable BOD , */\
+ { 0x4900, "IEBSTCU"}, /* Enable DCDC current limiting , */\
+ { 0x4910, "IEBSTHI"}, /* Enable DCDC active , */\
+ { 0x4920, "IEBSTOC"}, /* Enable DCDC OCP , */\
+ { 0x4930, "IEBSTPC"}, /* Enable bst peakcur , */\
+ { 0x4940, "IEBSTVC"}, /* Enable DCDC level 1x , */\
+ { 0x4950, "IEBST86"}, /* Enable DCDC level 1.14x , */\
+ { 0x4960, "IEBST93"}, /* Enable DCDC level 1.07x , */\
+ { 0x4970, "IERCVLD"}, /* Enable rcvldop ready , */\
+ { 0x4980, "IEOCPL"}, /* Enable ocp alarm left , */\
+ { 0x4990, "IEOCPR"}, /* Enable ocp alarm , */\
+ { 0x49a0, "IEMWSRC"}, /* Enable waits HW I2C settings , */\
+ { 0x49b0, "IEMWCFC"}, /* Enable man wait cf config , */\
+ { 0x49c0, "IEMWSMU"}, /* Enable man Audio mute sequence , */\
+ { 0x49d0, "IECFMER"}, /* Enable cfma err , */\
+ { 0x49e0, "IECFMAC"}, /* Enable cfma ack , */\
+ { 0x49f0, "IECLKOOR"}, /* Enable flag_clk_out_of_range , */\
+ { 0x4a00, "IETDMER"}, /* Enable tdm error , */\
+ { 0x4a10, "IECLPL"}, /* Enable clip left , */\
+ { 0x4a20, "IECLPR"}, /* Enable clip , */\
+ { 0x4a30, "IEOCPM1"}, /* Enable mic ocpok , */\
+ { 0x4a50, "IELP1"}, /* Enable low power mode1 , */\
+ { 0x4a60, "IELA"}, /* Enable low amplitude detection , */\
+ { 0x4a70, "IEVDDP"}, /* Enable VDDP greater than VBAT , */\
+ { 0x4a80, "IETAPDET"}, /* Enable Tap detected , */\
+ { 0x4a90, "IEAUDMOD"}, /* Enable Audio Mode activated , */\
+ { 0x4aa0, "IESAMMOD"}, /* Enable SAM Mode activated , */\
+ { 0x4ab0, "IETAPMOD"}, /* Enable Tap Mode Activated , */\
+ { 0x4ac0, "IETAPTRG"}, /* Enable comparator interrupt , */\
+ { 0x4c00, "IPOVDDS"}, /* Polarity por , */\
+ { 0x4c10, "IPOPLLS"}, /* Polarity pll lock , */\
+ { 0x4c20, "IPOOTDS"}, /* Polarity OTP alarm , */\
+ { 0x4c30, "IPOOVDS"}, /* Polarity OVP alarm , */\
+ { 0x4c40, "IPOUVDS"}, /* Polarity UVP alarm , */\
+ { 0x4c50, "IPOCLKS"}, /* Polarity clocks stable , */\
+ { 0x4c60, "IPOMTPB"}, /* Polarity mtp busy , */\
+ { 0x4c70, "IPONOCLK"}, /* Polarity lost clk , */\
+ { 0x4c80, "IPOSPKS"}, /* Polarity speaker error , */\
+ { 0x4c90, "IPOACS"}, /* Polarity cold started , */\
+ { 0x4ca0, "IPOSWS"}, /* Polarity amplifier engage , */\
+ { 0x4cb0, "IPOWDS"}, /* Polarity watchdog , */\
+ { 0x4cc0, "IPOAMPS"}, /* Polarity enbl amp , */\
+ { 0x4cd0, "IPOAREFS"}, /* Polarity ref enable , */\
+ { 0x4ce0, "IPOADCCR"}, /* Polarity Control ADC , */\
+ { 0x4cf0, "IPOBODNOK"}, /* Polarity BOD , */\
+ { 0x4d00, "IPOBSTCU"}, /* Polarity DCDC current limiting , */\
+ { 0x4d10, "IPOBSTHI"}, /* Polarity DCDC active , */\
+ { 0x4d20, "IPOBSTOC"}, /* Polarity DCDC OCP , */\
+ { 0x4d30, "IPOBSTPC"}, /* Polarity bst peakcur , */\
+ { 0x4d40, "IPOBSTVC"}, /* Polarity DCDC level 1x , */\
+ { 0x4d50, "IPOBST86"}, /* Polarity DCDC level 1.14x , */\
+ { 0x4d60, "IPOBST93"}, /* Polarity DCDC level 1.07x , */\
+ { 0x4d70, "IPORCVLD"}, /* Polarity rcvldop ready , */\
+ { 0x4d80, "IPOOCPL"}, /* Polarity ocp alarm left , */\
+ { 0x4d90, "IPOOCPR"}, /* Polarity ocp alarm , */\
+ { 0x4da0, "IPOMWSRC"}, /* Polarity waits HW I2C settings , */\
+ { 0x4db0, "IPOMWCFC"}, /* Polarity man wait cf config , */\
+ { 0x4dc0, "IPOMWSMU"}, /* Polarity man audio mute sequence , */\
+ { 0x4dd0, "IPOCFMER"}, /* Polarity cfma err , */\
+ { 0x4de0, "IPOCFMAC"}, /* Polarity cfma ack , */\
+ { 0x4df0, "IPOCLKOOR"}, /* Polarity flag_clk_out_of_range , */\
+ { 0x4e00, "IPOTDMER"}, /* Polarity tdm error , */\
+ { 0x4e10, "IPOCLPL"}, /* Polarity clip left , */\
+ { 0x4e20, "IPOCLPR"}, /* Polarity clip , */\
+ { 0x4e30, "IPOOCPM"}, /* Polarity mic ocpok , */\
+ { 0x4e50, "IPOLP1"}, /* Polarity low power mode1 , */\
+ { 0x4e60, "IPOLA"}, /* Polarity low amplitude detection , */\
+ { 0x4e70, "IPOVDDP"}, /* Polarity VDDP greater than VBAT , */\
+ { 0x4e80, "IPOLTAPDET"}, /* PolarityTap detected , */\
+ { 0x4e90, "IPOLAUDMOD"}, /* PolarityAudio Mode activated , */\
+ { 0x4ea0, "IPOLSAMMOD"}, /* PolaritySAM Mode activated , */\
+ { 0x4eb0, "IPOLTAPMOD"}, /* Polarity Tap Mode Activated , */\
+ { 0x4ec0, "IPOLTAPTRG"}, /* PolarityTap Comparator Trigger , */\
+ { 0x5001, "BSSCR"}, /* Battery Safeguard attack time , */\
+ { 0x5023, "BSST"}, /* Battery Safeguard threshold voltage level , */\
+ { 0x5061, "BSSRL"}, /* Battery Safeguard maximum reduction , */\
+ { 0x5082, "BSSRR"}, /* Battery Safeguard release time , */\
+ { 0x50b1, "BSSHY"}, /* Battery Safeguard hysteresis , */\
+ { 0x50d0, "BSSAC"}, /* Reset clipper - Auto clear , */\
+ { 0x50e0, "BSSR"}, /* Battery voltage read out , */\
+ { 0x50f0, "BSSBY"}, /* Bypass HW clipper , */\
+ { 0x5100, "BSSS"}, /* Vbat prot steepness , */\
+ { 0x5110, "INTSMUTE"}, /* Soft mute HW , */\
+ { 0x5120, "CFSML"}, /* Soft mute FW left , */\
+ { 0x5130, "CFSM"}, /* Soft mute FW , */\
+ { 0x5140, "HPFBYPL"}, /* Bypass HPF left , */\
+ { 0x5150, "HPFBYP"}, /* Bypass HPF , */\
+ { 0x5160, "DPSAL"}, /* Enable DPSA left , */\
+ { 0x5170, "DPSA"}, /* Enable DPSA , */\
+ { 0x5187, "VOL"}, /* FW volume control for primary audio channel , */\
+ { 0x5200, "HNDSFRCV"}, /* Selection receiver , */\
+ { 0x5222, "CLIPCTRL"}, /* Clip control setting , */\
+ { 0x5257, "AMPGAIN"}, /* Amplifier gain , */\
+ { 0x52d0, "SLOPEE"}, /* Enables slope control , */\
+ { 0x52e0, "SLOPESET"}, /* Slope speed setting (bin. coded) , */\
+ { 0x5c07, "CFTAPPAT"}, /* Coolflux tap pattern , */\
+ { 0x5c83, "TAPDBGINFO"}, /* Reserved , */\
+ { 0x5d0f, "TATPSTAT1"}, /* Tap Status 1 from CF FW , */\
+ { 0x5f03, "TCOMPTHR"}, /* Comparator threshold (in uV) , */\
+ { 0x6081, "PGAGAIN"}, /* PGA gain selection , */\
+ { 0x6123, "TDMSPKG"}, /* System gain (INPLEV 0) , */\
+ { 0x6505, "LPM1LVL"}, /* low power mode1 detector ctrl threshold for low_audio_lvl , */\
+ { 0x6565, "LPM1HLD"}, /* Low power mode1 detector, ctrl hold time before low audio is reckoned to be low audio, */\
+ { 0x65c0, "LPM1DIS"}, /* low power mode1 detector control , */\
+ { 0x6630, "DCDIS"}, /* DCDC , */\
+ { 0x6801, "TDMSRCMAP"}, /* tdm source mapping , */\
+ { 0x6821, "TDMSRCAS"}, /* frame a selection , */\
+ { 0x6841, "TDMSRCBS"}, /* frame b selection , */\
+ { 0x68a0, "ANC1C"}, /* ANC one s complement , */\
+ { 0x6901, "SAMMODE"}, /* Sam mode , */\
+ { 0x7033, "DCMCC"}, /* Max coil current , */\
+ { 0x7071, "DCCV"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
+ { 0x7090, "DCIE"}, /* Adaptive boost mode , */\
+ { 0x70a0, "DCSR"}, /* Soft ramp up/down , */\
+ { 0x70c1, "DCINSEL"}, /* DCDC IIR input Selection , */\
+ { 0x70f0, "DCPWM"}, /* DCDC PWM only mode , */\
+ { 0x7504, "DCTRIP"}, /* Adaptive boost trip levels 1, effective only when boost_intelligent is set to 1, */\
+ { 0x7554, "DCTRIP2"}, /* Adaptive boost trip level 2, effective only when boost_intelligent is set to 1, */\
+ { 0x75a4, "DCTRIPT"}, /* Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
+ { 0x7635, "DCVOF"}, /* First boost voltage level , */\
+ { 0x7695, "DCVOS"}, /* Second boost voltage level , */\
+ { 0x9000, "RST"}, /* Reset , */\
+ { 0x9011, "DMEM"}, /* Target memory , */\
+ { 0x9030, "AIF"}, /* Auto increment , */\
+ { 0x9040, "CFINT"}, /* Interrupt - auto clear , */\
+ { 0x9050, "CFCGATE"}, /* Coolflux clock gating disabling control , */\
+ { 0x9080, "REQCMD"}, /* Firmware event request rpc command , */\
+ { 0x9090, "REQRST"}, /* Firmware event request reset restart , */\
+ { 0x90a0, "REQMIPS"}, /* Firmware event request short on mips , */\
+ { 0x90b0, "REQMUTED"}, /* Firmware event request mute sequence ready , */\
+ { 0x90c0, "REQVOL"}, /* Firmware event request volume ready , */\
+ { 0x90d0, "REQDMG"}, /* Firmware event request speaker damage detected , */\
+ { 0x90e0, "REQCAL"}, /* Firmware event request calibration completed , */\
+ { 0x90f0, "REQRSV"}, /* Firmware event request reserved , */\
+ { 0x910f, "MADD"}, /* Memory address , */\
+ { 0x920f, "MEMA"}, /* Activate memory access , */\
+ { 0x9307, "ERR"}, /* Error flags , */\
+ { 0x9380, "ACKCMD"}, /* Firmware event acknowledge rpc command , */\
+ { 0x9390, "ACKRST"}, /* Firmware event acknowledge reset restart , */\
+ { 0x93a0, "ACKMIPS"}, /* Firmware event acknowledge short on mips , */\
+ { 0x93b0, "ACKMUTED"}, /* Firmware event acknowledge mute sequence ready , */\
+ { 0x93c0, "ACKVOL"}, /* Firmware event acknowledge volume ready , */\
+ { 0x93d0, "ACKDMG"}, /* Firmware event acknowledge speaker damage detected, */\
+ { 0x93e0, "ACKCAL"}, /* Firmware event acknowledge calibration completed , */\
+ { 0x93f0, "ACKRSV"}, /* Firmware event acknowledge reserved , */\
+ { 0xa107, "MTPK"}, /* MTP KEY2 register , */\
+ { 0xa200, "KEY1LOCKED"}, /* Indicates KEY1 is locked , */\
+ { 0xa210, "KEY2LOCKED"}, /* Indicates KEY2 is locked , */\
+ { 0xa360, "CIMTP"}, /* Start copying data from I2C mtp registers to mtp , */\
+ { 0xa50f, "MTPRDMSB"}, /* MSB word of MTP manual read data , */\
+ { 0xa60f, "MTPRDLSB"}, /* LSB word of MTP manual read data , */\
+ { 0xb108, "EXTTS"}, /* External temperature (C) , */\
+ { 0xb190, "TROS"}, /* Select temp Speaker calibration , */\
+ { 0xee0f, "SWPROFIL"}, /* Software profile data , */\
+ { 0xef0f, "SWVSTEP"}, /* Software vstep information , */\
+ { 0xf000, "MTPOTC"}, /* Calibration schedule , */\
+ { 0xf010, "MTPEX"}, /* Calibration Ron executed , */\
+ { 0xf020, "DCMCCAPI"}, /* Calibration current limit DCDC , */\
+ { 0xf030, "DCMCCSB"}, /* Sign bit for delta calibration current limit DCDC , */\
+ { 0xf042, "DCMCCCL"}, /* Calibration delta current limit DCDC , */\
+ { 0xf078, "USERDEF"}, /* Reserved space for allowing customer to store speaker information, */\
+ { 0xf40f, "R25C"}, /* Ron resistance of speaker coil , */\
+ { 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+
+#define TFA9912_BITNAMETABLE static tfaBfName_t Tfa9912BitNames[] = {\
+ { 0x0, "powerdown"}, /* Powerdown selection , */\
+ { 0x10, "reset"}, /* I2C Reset - Auto clear , */\
+ { 0x20, "enbl_coolflux"}, /* Enable CoolFlux , */\
+ { 0x30, "enbl_amplifier"}, /* Enables the Amplifier , */\
+ { 0x40, "enbl_boost"}, /* Activate DC-to-DC converter , */\
+ { 0x50, "coolflux_configured"}, /* Coolflux configured , */\
+ { 0x60, "sel_enbl_amplifier"}, /* CoolFlux controls amplifier , */\
+ { 0x71, "int_pad_io"}, /* Interrupt config , */\
+ { 0x90, "fs_pulse_sel"}, /* Audio sample reference , */\
+ { 0xb0, "bypass_ocp"}, /* Bypass OCP , */\
+ { 0xc0, "test_ocp"}, /* OCP testing control , */\
+ { 0x101, "vamp_sel"}, /* Amplifier input selection , */\
+ { 0x120, "src_set_configured"}, /* I2C configured , */\
+ { 0x130, "execute_cold_start"}, /* Execute cold start , */\
+ { 0x140, "enbl_fro8m_auto_off"}, /* Internal osc off at PWDN , */\
+ { 0x150, "man_enbl_brown_out"}, /* Reaction on BOD , */\
+ { 0x160, "enbl_bod"}, /* BOD Enable , */\
+ { 0x170, "enbl_bod_hyst"}, /* BOD Hysteresis , */\
+ { 0x181, "bod_delay"}, /* BOD filter , */\
+ { 0x1a1, "bod_lvlsel"}, /* BOD threshold , */\
+ { 0x1d0, "disable_mute_time_out"}, /* Time out SB mute sequence , */\
+ { 0x1e0, "pwm_sel_rcv_ns"}, /* Noise shaper selection , */\
+ { 0x1f0, "man_enbl_watchdog"}, /* Watchdog enable , */\
+ { 0x203, "audio_fs"}, /* Sample rate (fs) , */\
+ { 0x240, "input_level"}, /* TDM output attenuation , */\
+ { 0x255, "cs_frac_delay"}, /* V/I Fractional delay , */\
+ { 0x2b0, "bypass_hvbat_filter"}, /* Bypass HVBAT filter , */\
+ { 0x2c0, "tdm_tfa9872_compatible"}, /* TDM Compatibility with TFA9872 , */\
+ { 0x2d0, "sel_hysteresis"}, /* Select hysteresis for clock range detector , */\
+ { 0x2e0, "enbl_adc10"}, /* ADC10 Enable - I2C direct mode , */\
+ { 0x30f, "device_rev"}, /* Revision info , */\
+ { 0x401, "pll_clkin_sel"}, /* PLL external ref clock , */\
+ { 0x420, "pll_clkin_sel_osc"}, /* PLL internal ref clock , */\
+ { 0x430, "cf_clock_scaling"}, /* Coolflux DSP clock scaling, low power mode , */\
+ { 0x441, "sel_cf_clock"}, /* Coolflux DSP clock scaler selection for low power mode, */\
+ { 0x460, "tdm_intf_sel"}, /* TDM clock selection , */\
+ { 0x470, "disable_auto_sel_refclk"}, /* Disable Automatic dsp clock source selection , */\
+ { 0x480, "sel_clk_src"}, /* I2C selection of DSP clock when auto select is disabled, */\
+ { 0x490, "wdt_tim_clk_src"}, /* I2C selection of Watchdog and Timer clock , */\
+ { 0x510, "enbl_spkr_ss"}, /* Enable speaker path , */\
+ { 0x530, "enbl_volsense"}, /* Voltage sense , */\
+ { 0x550, "enbl_cursense"}, /* Current sense , */\
+ { 0x560, "enbl_pdm_ss"}, /* Sub-system PDM , */\
+ { 0x580, "enbl_pga_chop"}, /* Enable PGA chop clock , */\
+ { 0x590, "enbl_tdm_ss"}, /* Sub-system TDM , */\
+ { 0x5a0, "enbl_bst_ss"}, /* Sub-system boost , */\
+ { 0x5b0, "enbl_adc10_ss"}, /* Sub-system ADC , */\
+ { 0x5c0, "enbl_faim_ss"}, /* Sub-system FAIM , */\
+ { 0x5d0, "enbl_tim_clk"}, /* CF Sub-system timer , */\
+ { 0x5e0, "enbl_wdt_clk"}, /* CF Sub-system WDT , */\
+ { 0x5f0, "faim_enable_vbg"}, /* Over rule of vbg for FaIM access , */\
+ { 0x600, "aux_spkr_sel"}, /* Input selection for TAP/SAM , */\
+ { 0x620, "bypass_tapdec_reset"}, /* Tap decimator reset bypass - Bypass the decimator reset from tapdec, */\
+ { 0x631, "car_dec_in_sel0"}, /* Cardec input 0 sel , */\
+ { 0x651, "car_dec_in_sel1"}, /* Cardec input sel , */\
+ { 0x670, "tapdec_sel"}, /* Select TAP/Cardec for TAP , */\
+ { 0x680, "comp_count"}, /* Comparator o/p filter selection , */\
+ { 0x691, "startup_mode"}, /* Startup Mode Selection , */\
+ { 0x6b0, "enable_auto_tap_switching"}, /* Enable auto tap switching , */\
+ { 0x6c1, "comp_init_time"}, /* Comparator initialization time to be used in Tap Machine, */\
+ { 0x6e1, "ana_init_time"}, /* Analog initialization time to be used in Tap Machine, */\
+ { 0x707, "clkchk_th_hi"}, /* Clock check Higher Threshold , */\
+ { 0x787, "clkchk_th_lo"}, /* Clock check Higher Threshold , */\
+ { 0x802, "ctrl_on2off_criterion"}, /* Amplifier on-off criteria for shutdown , */\
+ { 0x832, "ctrl_on2tap_criterion"}, /* Amplifier on-off criteria for tap mode entry , */\
+ { 0xd00, "side_tone_gain_sel"}, /* PDM side tone gain selector , */\
+ { 0xd18, "side_tone_gain"}, /* Side tone gain , */\
+ { 0xda0, "mute_side_tone"}, /* Side tone soft mute , */\
+ { 0xdb0, "side_tone_1scomplement"}, /* side tone one s complement , */\
+ { 0xe07, "ctrl_digtoana"}, /* Spare control from digital to analog , */\
+ { 0xf0f, "hidden_code"}, /* 5A6Bh, 23147d to access registers (default for engineering), */\
+ { 0x1000, "flag_por"}, /* POR , */\
+ { 0x1010, "flag_pll_lock"}, /* PLL lock , */\
+ { 0x1020, "flag_otpok"}, /* OTP alarm , */\
+ { 0x1030, "flag_ovpok"}, /* OVP alarm , */\
+ { 0x1040, "flag_uvpok"}, /* UVP alarm , */\
+ { 0x1050, "flag_clocks_stable"}, /* Clocks stable , */\
+ { 0x1060, "flag_mtp_busy"}, /* MTP busy , */\
+ { 0x1070, "flag_lost_clk"}, /* Lost clock , */\
+ { 0x1090, "flag_cold_started"}, /* Cold Start , */\
+ { 0x10a0, "flag_engage"}, /* Amplifier engage , */\
+ { 0x10b0, "flag_watchdog_reset"}, /* Watchdog , */\
+ { 0x10c0, "flag_enbl_amp"}, /* Amplifier enable , */\
+ { 0x10d0, "flag_enbl_ref"}, /* References enable , */\
+ { 0x10e0, "flag_adc10_ready"}, /* Control ADC , */\
+ { 0x10f0, "flag_bod_vddd_nok"}, /* BOD , */\
+ { 0x1100, "flag_bst_bstcur"}, /* DCDC current limiting , */\
+ { 0x1110, "flag_bst_hiz"}, /* DCDC active , */\
+ { 0x1120, "flag_bst_ocpok"}, /* DCDC OCP nmos , */\
+ { 0x1130, "flag_bst_peakcur"}, /* Indicates current is max in DC-to-DC converter , */\
+ { 0x1140, "flag_bst_voutcomp"}, /* DCDC level 1x , */\
+ { 0x1150, "flag_bst_voutcomp86"}, /* DCDC level 1.14x , */\
+ { 0x1160, "flag_bst_voutcomp93"}, /* DCDC level 1.07x , */\
+ { 0x1170, "flag_soft_mute_busy"}, /* side tone (un)mute busy , */\
+ { 0x1180, "flag_soft_mute_state"}, /* side tone mute state , */\
+ { 0x1190, "flag_tdm_lut_error"}, /* TDM LUT error , */\
+ { 0x11a2, "flag_tdm_status"}, /* TDM status bits , */\
+ { 0x11d0, "flag_tdm_error"}, /* TDM error , */\
+ { 0x1300, "flag_ocpokap"}, /* OCPOK pmos A , */\
+ { 0x1310, "flag_ocpokan"}, /* OCPOK nmos A , */\
+ { 0x1320, "flag_ocpokbp"}, /* OCPOK pmos B , */\
+ { 0x1330, "flag_ocpokbn"}, /* OCPOK nmos B , */\
+ { 0x1340, "flag_clipa_high"}, /* Clipping A to Vddp , */\
+ { 0x1350, "flag_clipa_low"}, /* Clipping A to gnd , */\
+ { 0x1360, "flag_clipb_high"}, /* Clipping B to Vddp , */\
+ { 0x1370, "flag_clipb_low"}, /* Clipping B to gnd , */\
+ { 0x1380, "flag_ocp_alarm"}, /* OCP amplifier , */\
+ { 0x1390, "flag_clip"}, /* Amplifier clipping , */\
+ { 0x13a0, "flag_tap_comp_trig"}, /* Status Tap comparator triggered , */\
+ { 0x13b0, "flag_cf_tapdetected"}, /* Status Tap detected , */\
+ { 0x13c0, "flag_man_wait_src_settings"}, /* Wait HW I2C settings , */\
+ { 0x13d0, "flag_man_wait_cf_config"}, /* Wait CF config , */\
+ { 0x13e0, "flag_man_start_mute_audio"}, /* Audio mute sequence , */\
+ { 0x1410, "flag_cf_speakererror"}, /* Speaker status , */\
+ { 0x1420, "flag_clk_out_of_range"}, /* External clock status , */\
+ { 0x1433, "man_state"}, /* Device manager status , */\
+ { 0x1471, "status_bst_mode"}, /* DCDC mode status bits , */\
+ { 0x1490, "man_dsp_clk_src"}, /* DSP clock source selected by manager , */\
+ { 0x14a1, "man_startup_mode"}, /* Startup Mode Selected by Manager(Read Only) , */\
+ { 0x14c3, "tap_machine_state"}, /* Tap Machine State , */\
+ { 0x1509, "bat_adc"}, /* Battery voltage (V) , */\
+ { 0x1608, "temp_adc"}, /* IC Temperature (C) , */\
+ { 0x1709, "vddp_adc"}, /* IC VDDP voltage ( 1023*VDDP/13 V) , */\
+ { 0x17a0, "flag_bst_bstcur_cf"}, /* DCDC current limiting for DSP , */\
+ { 0x2000, "tdm_usecase"}, /* Mode setting , */\
+ { 0x2011, "dio4_input_sel"}, /* DIO4 Input selection , */\
+ { 0x2040, "tdm_enable"}, /* Enable TDM interface , */\
+ { 0x2060, "tdm_clk_inversion"}, /* Reception data to BCK clock , */\
+ { 0x2073, "tdm_fs_ws_length"}, /* FS length , */\
+ { 0x20b0, "tdm_fs_ws_polarity"}, /* FS polarity , */\
+ { 0x20c3, "tdm_nbck"}, /* N-BCK's in FS , */\
+ { 0x2103, "tdm_nb_of_slots"}, /* N-slots in Frame , */\
+ { 0x2144, "tdm_slot_length"}, /* N-bits in slot , */\
+ { 0x2194, "tdm_bits_remaining"}, /* N-bits remaining , */\
+ { 0x21e0, "tdm_data_delay"}, /* data delay to FS , */\
+ { 0x21f0, "tdm_data_adjustment"}, /* data adjustment , */\
+ { 0x2201, "tdm_audio_sample_compression"}, /* Received audio compression , */\
+ { 0x2224, "tdm_sample_size"}, /* Sample size per slot , */\
+ { 0x2271, "tdm_txdata_format"}, /* Format unused bits in a slot , */\
+ { 0x2291, "tdm_txdata_format_unused_slot_sd0"}, /* Format unused slots GAINIO , */\
+ { 0x22b1, "tdm_txdata_format_unused_slot_sd1"}, /* Format unused slots DIO1 , */\
+ { 0x22d1, "tdm_txdata_format_unused_slot_sd2"}, /* Format unused slots DIO2 , */\
+ { 0x2300, "tdm_sink0_enable"}, /* Control gain (channel in 0) , */\
+ { 0x2310, "tdm_sink1_enable"}, /* Control audio left (channel in 1 ) , */\
+ { 0x2320, "tdm_sink2_enable"}, /* Control audio right (channel in 2 ) , */\
+ { 0x2330, "tdm_source0_enable"}, /* Current sense , */\
+ { 0x2340, "tdm_source1_enable"}, /* Voltage sense , */\
+ { 0x2350, "tdm_source2_enable"}, /* DSP Gainout , */\
+ { 0x2360, "tdm_source3_enable"}, /* DSP 2 , */\
+ { 0x2370, "tdm_source4_enable"}, /* DSP 3 , */\
+ { 0x2380, "tdm_source5_enable"}, /* DSP , */\
+ { 0x2390, "tdm_source6_enable"}, /* Loopback of Audio left (channel 1) , */\
+ { 0x23a0, "tdm_source7_enable"}, /* Loopback of Audio right (channel 2) , */\
+ { 0x2401, "tdm_sink0_io"}, /* IO gainin , */\
+ { 0x2421, "tdm_sink1_io"}, /* IO audio left , */\
+ { 0x2441, "tdm_sink2_io"}, /* IO audio right , */\
+ { 0x2461, "tdm_source0_io"}, /* IO Current Sense , */\
+ { 0x2481, "tdm_source1_io"}, /* IO voltage sense , */\
+ { 0x24a1, "tdm_source2_io"}, /* IO gain out , */\
+ { 0x24c1, "tdm_source3_io"}, /* IO DSP 2 , */\
+ { 0x24e1, "tdm_source4_io"}, /* IO DSP 3 , */\
+ { 0x2501, "tdm_source5_io"}, /* IO DSP , */\
+ { 0x2521, "tdm_source6_io"}, /* IO Source 6 , */\
+ { 0x2541, "tdm_source7_io"}, /* IO Source 7 , */\
+ { 0x2603, "tdm_sink0_slot"}, /* Control gainin , */\
+ { 0x2643, "tdm_sink1_slot"}, /* tdm slot for audio left (channel 1) , */\
+ { 0x2683, "tdm_sink2_slot"}, /* tdm slot for audio right (channel 2) , */\
+ { 0x26c3, "tdm_source0_slot"}, /* Slot Position of Current Sense Out , */\
+ { 0x2703, "tdm_source1_slot"}, /* Slot Position of Voltage sense , */\
+ { 0x2743, "tdm_source2_slot"}, /* Slot Position of GAIN out , */\
+ { 0x2783, "tdm_source3_slot"}, /* Slot Position DSPout2 , */\
+ { 0x27c3, "tdm_source4_slot"}, /* Slot Position DSPout3 , */\
+ { 0x2803, "tdm_source5_slot"}, /* Slot Position of DSPout , */\
+ { 0x2843, "tdm_source6_slot"}, /* Slot Position of loopback channel left , */\
+ { 0x2883, "tdm_source7_slot"}, /* Slot Position of loopback channel right , */\
+ { 0x2901, "tdm_txdata_format_unused_slot_sd3"}, /* Format unused slots D3 , */\
+ { 0x3100, "pdm_mode"}, /* PDM control , */\
+ { 0x3110, "pdm_input_sel"}, /* PDM Decimator input selection , */\
+ { 0x3120, "enbl_pdm_side_tone"}, /* Side tone input enable , */\
+ { 0x3201, "pdm_nbck"}, /* PDM BCK/Fs ratio , */\
+ { 0x4000, "int_out_flag_por"}, /* Status POR , */\
+ { 0x4010, "int_out_flag_pll_lock"}, /* Status PLL lock , */\
+ { 0x4020, "int_out_flag_otpok"}, /* Status OTP alarm , */\
+ { 0x4030, "int_out_flag_ovpok"}, /* Status OVP alarm , */\
+ { 0x4040, "int_out_flag_uvpok"}, /* Status UVP alarm , */\
+ { 0x4050, "int_out_flag_clocks_stable"}, /* Status clocks stable , */\
+ { 0x4060, "int_out_flag_mtp_busy"}, /* Status MTP busy , */\
+ { 0x4070, "int_out_flag_lost_clk"}, /* Status lost clock , */\
+ { 0x4080, "int_out_flag_cf_speakererror"}, /* Status speaker error , */\
+ { 0x4090, "int_out_flag_cold_started"}, /* Status cold start , */\
+ { 0x40a0, "int_out_flag_engage"}, /* Status amplifier engage , */\
+ { 0x40b0, "int_out_flag_watchdog_reset"}, /* Status watchdog , */\
+ { 0x40c0, "int_out_flag_enbl_amp"}, /* Status amplifier enable , */\
+ { 0x40d0, "int_out_flag_enbl_ref"}, /* Status Ref enable , */\
+ { 0x40e0, "int_out_flag_adc10_ready"}, /* Status Control ADC , */\
+ { 0x40f0, "int_out_flag_bod_vddd_nok"}, /* Status BOD , */\
+ { 0x4100, "int_out_flag_bst_bstcur"}, /* Status DCDC current limiting , */\
+ { 0x4110, "int_out_flag_bst_hiz"}, /* Status DCDC active , */\
+ { 0x4120, "int_out_flag_bst_ocpok"}, /* Status DCDC OCP , */\
+ { 0x4130, "int_out_flag_bst_peakcur"}, /* Status bst peakcur , */\
+ { 0x4140, "int_out_flag_bst_voutcomp"}, /* Status DCDC level 1x , */\
+ { 0x4150, "int_out_flag_bst_voutcomp86"}, /* Status DCDC level 1.14x , */\
+ { 0x4160, "int_out_flag_bst_voutcomp93"}, /* Status DCDC level 1.07x , */\
+ { 0x4190, "int_out_flag_ocp_alarm"}, /* Status ocp alarm , */\
+ { 0x41a0, "int_out_flag_man_wait_src_settings"}, /* Status Waits HW I2C settings , */\
+ { 0x41b0, "int_out_flag_man_wait_cf_config"}, /* Status waits CF config , */\
+ { 0x41c0, "int_out_flag_man_start_mute_audio"}, /* Status Audio mute sequence , */\
+ { 0x41d0, "int_out_flag_cfma_err"}, /* Status cfma error , */\
+ { 0x41e0, "int_out_flag_cfma_ack"}, /* Status cfma ack , */\
+ { 0x41f0, "int_out_flag_clk_out_of_range"}, /* Status flag_clk_out_of_range , */\
+ { 0x4200, "int_out_flag_tdm_error"}, /* Status tdm error , */\
+ { 0x4220, "int_out_flag_clip"}, /* Status clip , */\
+ { 0x4250, "int_out_flag_lp_detect_mode1"}, /* Status low power mode1 , */\
+ { 0x4260, "int_out_flag_low_amplitude"}, /* Status low amplitude detection , */\
+ { 0x4270, "int_out_flag_vddp_gt_vbat"}, /* Status VDDP greater than VBAT , */\
+ { 0x4280, "int_out_newtap"}, /* Status Tap detected , */\
+ { 0x4290, "int_out_audiomodeactive"}, /* Status Audio Mode activated , */\
+ { 0x42a0, "int_out_sammodeactive"}, /* Status SAM Mode activated , */\
+ { 0x42b0, "int_out_tapmodeactive"}, /* Status Tap Mode Activated , */\
+ { 0x42c0, "int_out_flag_tap_comp_trig"}, /* Status Tap comparator triggered , */\
+ { 0x4400, "int_in_flag_por"}, /* Clear POR , */\
+ { 0x4410, "int_in_flag_pll_lock"}, /* Clear PLL lock , */\
+ { 0x4420, "int_in_flag_otpok"}, /* Clear OTP alarm , */\
+ { 0x4430, "int_in_flag_ovpok"}, /* Clear OVP alarm , */\
+ { 0x4440, "int_in_flag_uvpok"}, /* Clear UVP alarm , */\
+ { 0x4450, "int_in_flag_clocks_stable"}, /* Clear clocks stable , */\
+ { 0x4460, "int_in_flag_mtp_busy"}, /* Clear mtp busy , */\
+ { 0x4470, "int_in_flag_lost_clk"}, /* Clear lost clk , */\
+ { 0x4480, "int_in_flag_cf_speakererror"}, /* Clear speaker error , */\
+ { 0x4490, "int_in_flag_cold_started"}, /* Clear cold started , */\
+ { 0x44a0, "int_in_flag_engage"}, /* Clear amplifier engage , */\
+ { 0x44b0, "int_in_flag_watchdog_reset"}, /* Clear watchdog , */\
+ { 0x44c0, "int_in_flag_enbl_amp"}, /* Clear enbl amp , */\
+ { 0x44d0, "int_in_flag_enbl_ref"}, /* Clear ref enable , */\
+ { 0x44e0, "int_in_flag_adc10_ready"}, /* Clear control ADC , */\
+ { 0x44f0, "int_in_flag_bod_vddd_nok"}, /* Clear BOD , */\
+ { 0x4500, "int_in_flag_bst_bstcur"}, /* Clear DCDC current limiting , */\
+ { 0x4510, "int_in_flag_bst_hiz"}, /* Clear DCDC active , */\
+ { 0x4520, "int_in_flag_bst_ocpok"}, /* Clear DCDC OCP , */\
+ { 0x4530, "int_in_flag_bst_peakcur"}, /* Clear bst peakcur , */\
+ { 0x4540, "int_in_flag_bst_voutcomp"}, /* Clear DCDC level 1x , */\
+ { 0x4550, "int_in_flag_bst_voutcomp86"}, /* Clear DCDC level 1.14x , */\
+ { 0x4560, "int_in_flag_bst_voutcomp93"}, /* Clear DCDC level 1.07x , */\
+ { 0x4590, "int_in_flag_ocp_alarm"}, /* Clear ocp alarm , */\
+ { 0x45a0, "int_in_flag_man_wait_src_settings"}, /* Clear wait HW I2C settings , */\
+ { 0x45b0, "int_in_flag_man_wait_cf_config"}, /* Clear wait cf config , */\
+ { 0x45c0, "int_in_flag_man_start_mute_audio"}, /* Clear audio mute sequence , */\
+ { 0x45d0, "int_in_flag_cfma_err"}, /* Clear cfma err , */\
+ { 0x45e0, "int_in_flag_cfma_ack"}, /* Clear cfma ack , */\
+ { 0x45f0, "int_in_flag_clk_out_of_range"}, /* Clear flag_clk_out_of_range , */\
+ { 0x4600, "int_in_flag_tdm_error"}, /* Clear tdm error , */\
+ { 0x4620, "int_in_flag_clip"}, /* Clear clip , */\
+ { 0x4650, "int_in_flag_lp_detect_mode1"}, /* Clear low power mode1 , */\
+ { 0x4660, "int_in_flag_low_amplitude"}, /* Clear low amplitude detection , */\
+ { 0x4670, "int_in_flag_vddp_gt_vbat"}, /* Clear VDDP greater then VBAT , */\
+ { 0x4680, "int_in_newtap"}, /* Clear Tap detected , */\
+ { 0x4690, "int_in_audiomodeactive"}, /* Clear Audio Mode activated , */\
+ { 0x46a0, "int_in_sammodeactive"}, /* Clear SAM Mode activated , */\
+ { 0x46b0, "int_in_tapmodeactive"}, /* Clear Tap Mode Activated , */\
+ { 0x46c0, "int_in_flag_tap_comp_trig"}, /* Clear Comparator Interrupt , */\
+ { 0x4800, "int_enable_flag_por"}, /* Enable por , */\
+ { 0x4810, "int_enable_flag_pll_lock"}, /* Enable pll lock , */\
+ { 0x4820, "int_enable_flag_otpok"}, /* Enable OTP alarm , */\
+ { 0x4830, "int_enable_flag_ovpok"}, /* Enable OVP alarm , */\
+ { 0x4840, "int_enable_flag_uvpok"}, /* Enable UVP alarm , */\
+ { 0x4850, "int_enable_flag_clocks_stable"}, /* Enable clocks stable , */\
+ { 0x4860, "int_enable_flag_mtp_busy"}, /* Enable mtp busy , */\
+ { 0x4870, "int_enable_flag_lost_clk"}, /* Enable lost clk , */\
+ { 0x4880, "int_enable_flag_cf_speakererror"}, /* Enable speaker error , */\
+ { 0x4890, "int_enable_flag_cold_started"}, /* Enable cold started , */\
+ { 0x48a0, "int_enable_flag_engage"}, /* Enable amplifier engage , */\
+ { 0x48b0, "int_enable_flag_watchdog_reset"}, /* Enable watchdog , */\
+ { 0x48c0, "int_enable_flag_enbl_amp"}, /* Enable enbl amp , */\
+ { 0x48d0, "int_enable_flag_enbl_ref"}, /* Enable ref enable , */\
+ { 0x48e0, "int_enable_flag_adc10_ready"}, /* Enable Control ADC , */\
+ { 0x48f0, "int_enable_flag_bod_vddd_nok"}, /* Enable BOD , */\
+ { 0x4900, "int_enable_flag_bst_bstcur"}, /* Enable DCDC current limiting , */\
+ { 0x4910, "int_enable_flag_bst_hiz"}, /* Enable DCDC active , */\
+ { 0x4920, "int_enable_flag_bst_ocpok"}, /* Enable DCDC OCP , */\
+ { 0x4930, "int_enable_flag_bst_peakcur"}, /* Enable bst peakcur , */\
+ { 0x4940, "int_enable_flag_bst_voutcomp"}, /* Enable DCDC level 1x , */\
+ { 0x4950, "int_enable_flag_bst_voutcomp86"}, /* Enable DCDC level 1.14x , */\
+ { 0x4960, "int_enable_flag_bst_voutcomp93"}, /* Enable DCDC level 1.07x , */\
+ { 0x4990, "int_enable_flag_ocp_alarm"}, /* Enable ocp alarm , */\
+ { 0x49a0, "int_enable_flag_man_wait_src_settings"}, /* Enable waits HW I2C settings , */\
+ { 0x49b0, "int_enable_flag_man_wait_cf_config"}, /* Enable man wait cf config , */\
+ { 0x49c0, "int_enable_flag_man_start_mute_audio"}, /* Enable man Audio mute sequence , */\
+ { 0x49d0, "int_enable_flag_cfma_err"}, /* Enable cfma err , */\
+ { 0x49e0, "int_enable_flag_cfma_ack"}, /* Enable cfma ack , */\
+ { 0x49f0, "int_enable_flag_clk_out_of_range"}, /* Enable flag_clk_out_of_range , */\
+ { 0x4a00, "int_enable_flag_tdm_error"}, /* Enable tdm error , */\
+ { 0x4a20, "int_enable_flag_clip"}, /* Enable clip , */\
+ { 0x4a50, "int_enable_flag_lp_detect_mode1"}, /* Enable low power mode1 , */\
+ { 0x4a60, "int_enable_flag_low_amplitude"}, /* Enable low amplitude detection , */\
+ { 0x4a70, "int_enable_flag_vddp_gt_vbat"}, /* Enable VDDP greater than VBAT , */\
+ { 0x4a80, "int_enable_newtap"}, /* Enable Tap detected , */\
+ { 0x4a90, "int_enable_audiomodeactive"}, /* Enable Audio Mode activated , */\
+ { 0x4aa0, "int_enable_sammodeactive"}, /* Enable SAM Mode activated , */\
+ { 0x4ab0, "int_enable_tapmodeactive"}, /* Enable Tap Mode Activated , */\
+ { 0x4ac0, "int_enable_flag_tap_comp_trig"}, /* Enable comparator interrupt , */\
+ { 0x4c00, "int_polarity_flag_por"}, /* Polarity por , */\
+ { 0x4c10, "int_polarity_flag_pll_lock"}, /* Polarity pll lock , */\
+ { 0x4c20, "int_polarity_flag_otpok"}, /* Polarity OTP alarm , */\
+ { 0x4c30, "int_polarity_flag_ovpok"}, /* Polarity OVP alarm , */\
+ { 0x4c40, "int_polarity_flag_uvpok"}, /* Polarity UVP alarm , */\
+ { 0x4c50, "int_polarity_flag_clocks_stable"}, /* Polarity clocks stable , */\
+ { 0x4c60, "int_polarity_flag_mtp_busy"}, /* Polarity mtp busy , */\
+ { 0x4c70, "int_polarity_flag_lost_clk"}, /* Polarity lost clk , */\
+ { 0x4c80, "int_polarity_flag_cf_speakererror"}, /* Polarity speaker error , */\
+ { 0x4c90, "int_polarity_flag_cold_started"}, /* Polarity cold started , */\
+ { 0x4ca0, "int_polarity_flag_engage"}, /* Polarity amplifier engage , */\
+ { 0x4cb0, "int_polarity_flag_watchdog_reset"}, /* Polarity watchdog , */\
+ { 0x4cc0, "int_polarity_flag_enbl_amp"}, /* Polarity enbl amp , */\
+ { 0x4cd0, "int_polarity_flag_enbl_ref"}, /* Polarity ref enable , */\
+ { 0x4ce0, "int_polarity_flag_adc10_ready"}, /* Polarity Control ADC , */\
+ { 0x4cf0, "int_polarity_flag_bod_vddd_nok"}, /* Polarity BOD , */\
+ { 0x4d00, "int_polarity_flag_bst_bstcur"}, /* Polarity DCDC current limiting , */\
+ { 0x4d10, "int_polarity_flag_bst_hiz"}, /* Polarity DCDC active , */\
+ { 0x4d20, "int_polarity_flag_bst_ocpok"}, /* Polarity DCDC OCP , */\
+ { 0x4d30, "int_polarity_flag_bst_peakcur"}, /* Polarity bst peakcur , */\
+ { 0x4d40, "int_polarity_flag_bst_voutcomp"}, /* Polarity DCDC level 1x , */\
+ { 0x4d50, "int_polarity_flag_bst_voutcomp86"}, /* Polarity DCDC level 1.14x , */\
+ { 0x4d60, "int_polarity_flag_bst_voutcomp93"}, /* Polarity DCDC level 1.07x , */\
+ { 0x4d90, "int_polarity_flag_ocp_alarm"}, /* Polarity ocp alarm , */\
+ { 0x4da0, "int_polarity_flag_man_wait_src_settings"}, /* Polarity waits HW I2C settings , */\
+ { 0x4db0, "int_polarity_flag_man_wait_cf_config"}, /* Polarity man wait cf config , */\
+ { 0x4dc0, "int_polarity_flag_man_start_mute_audio"}, /* Polarity man audio mute sequence , */\
+ { 0x4dd0, "int_polarity_flag_cfma_err"}, /* Polarity cfma err , */\
+ { 0x4de0, "int_polarity_flag_cfma_ack"}, /* Polarity cfma ack , */\
+ { 0x4df0, "int_polarity_flag_clk_out_of_range"}, /* Polarity flag_clk_out_of_range , */\
+ { 0x4e00, "int_polarity_flag_tdm_error"}, /* Polarity tdm error , */\
+ { 0x4e20, "int_polarity_flag_clip"}, /* Polarity clip , */\
+ { 0x4e50, "int_polarity_flag_lp_detect_mode1"}, /* Polarity low power mode1 , */\
+ { 0x4e60, "int_polarity_flag_low_amplitude"}, /* Polarity low amplitude detection , */\
+ { 0x4e70, "int_polarity_flag_vddp_gt_vbat"}, /* Polarity VDDP greater than VBAT , */\
+ { 0x4e80, "int_polarity_newtap"}, /* PolarityTap detected , */\
+ { 0x4e90, "int_polarity_audiomodeactive"}, /* PolarityAudio Mode activated , */\
+ { 0x4ea0, "int_polarity_sammodeactive"}, /* PolaritySAM Mode activated , */\
+ { 0x4eb0, "int_polarity_tapmodeactive"}, /* Polarity Tap Mode Activated , */\
+ { 0x4ec0, "int_polarity_flag_tap_comp_trig"}, /* PolarityTap Comparator Trigger , */\
+ { 0x5001, "vbat_prot_attack_time"}, /* Battery Safeguard attack time , */\
+ { 0x5023, "vbat_prot_thlevel"}, /* Battery Safeguard threshold voltage level , */\
+ { 0x5061, "vbat_prot_max_reduct"}, /* Battery Safeguard maximum reduction , */\
+ { 0x5082, "vbat_prot_release_time"}, /* Battery Safeguard release time , */\
+ { 0x50b1, "vbat_prot_hysterese"}, /* Battery Safeguard hysteresis , */\
+ { 0x50d0, "rst_min_vbat"}, /* Reset clipper - Auto clear , */\
+ { 0x50e0, "sel_vbat"}, /* Battery voltage read out , */\
+ { 0x50f0, "bypass_clipper"}, /* Bypass HW clipper , */\
+ { 0x5100, "batsense_steepness"}, /* Vbat prot steepness , */\
+ { 0x5110, "soft_mute"}, /* Soft mute HW , */\
+ { 0x5130, "cf_mute"}, /* Soft mute FW , */\
+ { 0x5150, "bypass_hp"}, /* Bypass HPF , */\
+ { 0x5170, "enbl_dpsa"}, /* Enable DPSA , */\
+ { 0x5187, "cf_volume"}, /* FW volume control for primary audio channel , */\
+ { 0x5222, "ctrl_cc"}, /* Clip control setting , */\
+ { 0x5257, "gain"}, /* Amplifier gain , */\
+ { 0x52d0, "ctrl_slopectrl"}, /* Enables slope control , */\
+ { 0x52e0, "ctrl_slope"}, /* Slope speed setting (bin. coded) , */\
+ { 0x5301, "dpsa_level"}, /* DPSA threshold levels , */\
+ { 0x5321, "dpsa_release"}, /* DPSA Release time , */\
+ { 0x5340, "clipfast"}, /* Clock selection for HW clipper for Battery Safeguard, */\
+ { 0x5350, "bypass_lp"}, /* Bypass the low power filter inside temperature sensor, */\
+ { 0x5360, "enbl_low_latency"}, /* CF low latency outputs for add module , */\
+ { 0x5400, "first_order_mode"}, /* Overrule to 1st order mode of control stage when clipping, */\
+ { 0x5410, "bypass_ctrlloop"}, /* Switch amplifier into open loop configuration , */\
+ { 0x5430, "icomp_engage"}, /* Engage of icomp , */\
+ { 0x5440, "ctrl_kickback"}, /* Prevent double pulses of output stage , */\
+ { 0x5450, "icomp_engage_overrule"}, /* To overrule the functional icomp_engage signal during validation, */\
+ { 0x5503, "ctrl_dem"}, /* Enable DEM icomp and DEM one bit dac , */\
+ { 0x5543, "ctrl_dem_mismatch"}, /* Enable DEM icomp mismatch for testing , */\
+ { 0x5582, "dpsa_drive"}, /* Drive setting (bin. coded) - I2C direct mode , */\
+ { 0x570a, "enbl_amp"}, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually , */\
+ { 0x57b0, "enbl_engage"}, /* Enables/engage power stage and control loop - I2C direct mode, */\
+ { 0x57c0, "enbl_engage_pst"}, /* Enables/engage power stage and control loop , */\
+ { 0x5810, "hard_mute"}, /* Hard mute - PWM , */\
+ { 0x5820, "pwm_shape"}, /* PWM shape , */\
+ { 0x5844, "pwm_delay"}, /* PWM delay bits to set the delay, clock is 1/(k*2048*fs), */\
+ { 0x5890, "reclock_pwm"}, /* Reclock the pwm signal inside analog , */\
+ { 0x58a0, "reclock_voltsense"}, /* Reclock the voltage sense pwm signal , */\
+ { 0x58c0, "enbl_pwm_phase_shift"}, /* Control for pwm phase shift , */\
+ { 0x5c07, "flag_cf_tap_pattern"}, /* Coolflux tap pattern , */\
+ { 0x5c83, "tap_debug_info"}, /* Reserved , */\
+ { 0x5d0f, "tap_status_1"}, /* Tap Status 1 from CF FW , */\
+ { 0x5f03, "tap_comp_threshold"}, /* Comparator threshold (in uV) , */\
+ { 0x6081, "pga_gain_set"}, /* PGA gain selection , */\
+ { 0x60b0, "pga_lowpass_enable"}, /* Lowpass enable , */\
+ { 0x60c0, "pga_pwr_enable"}, /* PGA power enable , */\
+ { 0x60d0, "pga_switch_enable"}, /* PGA switch enable , */\
+ { 0x60e0, "pga_switch_aux_enable"}, /* Switch enable aux , */\
+ { 0x6123, "ctrl_att"}, /* System gain (INPLEV 0) , */\
+ { 0x6265, "zero_lvl"}, /* ctrl threshold for zero X-ing , */\
+ { 0x62c1, "ctrl_fb_resistor"}, /* Select amplifier feedback resistor connection , */\
+ { 0x62e1, "lownoisegain_mode"}, /* ctrl select mode , */\
+ { 0x6305, "threshold_lvl"}, /* ctrl threshold for low_audio_lvl , */\
+ { 0x6365, "hold_time"}, /* ctrl hold time before low audio is reckoned to be low audio, */\
+ { 0x6405, "lpm1_cal_offset"}, /* low power mode1 detector ctrl cal_offset from gain module , */\
+ { 0x6465, "lpm1_zero_lvl"}, /* low power mode1 detector ctrl threshold for zero X-ing , */\
+ { 0x64e1, "lpm1_mode"}, /* low power mode1 detector ctrl select mode , */\
+ { 0x6505, "lpm1_threshold_lvl"}, /* low power mode1 detector ctrl threshold for low_audio_lvl , */\
+ { 0x6565, "lpm1_hold_time"}, /* Low power mode1 detector, ctrl hold time before low audio is reckoned to be low audio, */\
+ { 0x65c0, "disable_low_power_mode"}, /* low power mode1 detector control , */\
+ { 0x6600, "dcdc_pfm20khz_limit"}, /* DCDC in PFM mode pwm mode is activated each 50us to force a pwm pulse, */\
+ { 0x6611, "dcdc_ctrl_maxzercnt"}, /* DCDC. Number of zero current flags to count before going to pfm mode, */\
+ { 0x6630, "dcdcoff_mode"}, /* DCDC , */\
+ { 0x6656, "dcdc_vbat_delta_detect"}, /* Threshold before booster is reacting on a delta Vbat (in PFM mode) by temporarily switching to PWM mode, */\
+ { 0x66c0, "dcdc_ignore_vbat"}, /* Ignore an increase on Vbat , */\
+ { 0x6700, "enbl_minion"}, /* Enables minion (small) power stage - direct ctrl , */\
+ { 0x6713, "vth_vddpvbat"}, /* select vddp-vbat thres signal , */\
+ { 0x6750, "lpen_vddpvbat"}, /* select vddp-vbat filtered vs unfiltered compare , */\
+ { 0x6761, "ctrl_rfb"}, /* Feedback resistor selection - I2C direct mode , */\
+ { 0x6801, "tdm_source_mapping"}, /* tdm source mapping , */\
+ { 0x6821, "tdm_sourcea_frame_sel"}, /* frame a selection , */\
+ { 0x6841, "tdm_sourceb_frame_sel"}, /* frame b selection , */\
+ { 0x6901, "sam_mode"}, /* Sam mode , */\
+ { 0x6931, "pdmdat_h_sel"}, /* pdm out value when pdm_clk is higth , */\
+ { 0x6951, "pdmdat_l_sel"}, /* pdm out value when pdm_clk is low , */\
+ { 0x6970, "cs_sam_set"}, /* Enable SAM input for current sense - I2C Direct Mode, */\
+ { 0x6980, "cs_adc_nortz"}, /* Return to zero for current sense ADC , */\
+ { 0x6990, "sam_spkr_sel"}, /* SAM o/p sel during SAM and audio , */\
+ { 0x6b00, "disable_engage"}, /* Disable auto engage , */\
+ { 0x6c02, "ns_hp2ln_criterion"}, /* 0..7 zeroes at ns as threshold to swap from high_power to low_noise, */\
+ { 0x6c32, "ns_ln2hp_criterion"}, /* 0..7 zeroes at ns as threshold to swap from low_noise to high_power, */\
+ { 0x6c60, "sel_clip_pwms"}, /* To select clip-flags , */\
+ { 0x6c72, "pwms_clip_lvl"}, /* To set the amount of pwm pulse that may be skipped before clip-flag is triggered. , */\
+ { 0x6ca5, "spare_out"}, /* spare_out , */\
+ { 0x6d0f, "spare_in"}, /* spare_in , */\
+ { 0x6e10, "flag_lp_detect_mode1"}, /* low power mode 1 detection , */\
+ { 0x6e20, "flag_low_amplitude"}, /* low amplitude detection , */\
+ { 0x6e30, "flag_vddp_gt_vbat"}, /* vddp greater than vbat , */\
+ { 0x7033, "boost_cur"}, /* Max coil current , */\
+ { 0x7071, "bst_slpcmplvl"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
+ { 0x7090, "boost_intel"}, /* Adaptive boost mode , */\
+ { 0x70a0, "boost_speed"}, /* Soft ramp up/down , */\
+ { 0x70c1, "dcdc_sel"}, /* DCDC IIR input Selection , */\
+ { 0x70f0, "dcdc_pwmonly"}, /* DCDC PWM only mode , */\
+ { 0x7104, "bst_drive"}, /* Binary coded drive setting for boost converter power stage, */\
+ { 0x7151, "bst_scalecur"}, /* For testing direct control scale current , */\
+ { 0x7174, "bst_slopecur"}, /* For testing direct control slope current - I2C direct mode, */\
+ { 0x71c1, "bst_slope"}, /* Boost slope speed , */\
+ { 0x71e0, "bst_bypass_bstcur"}, /* Bypass control for boost current settings , */\
+ { 0x71f0, "bst_bypass_bstfoldback"}, /* Bypass control for boost foldback , */\
+ { 0x7200, "enbl_bst_engage"}, /* Enable power stage dcdc controller - I2C direct mode, */\
+ { 0x7210, "enbl_bst_hizcom"}, /* Enable hiz comparator - I2C direct mode , */\
+ { 0x7220, "enbl_bst_peak2avg"}, /* Enable boost peak2avg functionality , */\
+ { 0x7230, "enbl_bst_peakcur"}, /* Enable peak current - I2C direct mode , */\
+ { 0x7240, "enbl_bst_power"}, /* Enable line of the powerstage - I2C direct mode , */\
+ { 0x7250, "enbl_bst_slopecur"}, /* Enable bit of max-current dac - I2C direct mode , */\
+ { 0x7260, "enbl_bst_voutcomp"}, /* Enable vout comparators - I2C direct mode , */\
+ { 0x7270, "enbl_bst_voutcomp86"}, /* Enable vout-86 comparators - I2C direct mode , */\
+ { 0x7280, "enbl_bst_voutcomp93"}, /* Enable vout-93 comparators - I2C direct mode , */\
+ { 0x7290, "enbl_bst_windac"}, /* Enable window dac - I2C direct mode , */\
+ { 0x72a5, "bst_windac"}, /* for testing direct control windac - I2C direct mode, */\
+ { 0x7300, "boost_alg"}, /* Control for boost adaptive loop gain , */\
+ { 0x7311, "boost_loopgain"}, /* DCDC boost loopgain setting , */\
+ { 0x7331, "bst_freq"}, /* DCDC boost frequency control , */\
+ { 0x7430, "boost_track"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
+ { 0x7494, "boost_hold_time"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
+ { 0x74e0, "sel_dcdc_envelope_8fs"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
+ { 0x74f0, "ignore_flag_voutcomp86"}, /* Ignore flag_voutcomp86 , */\
+ { 0x7504, "boost_trip_lvl_1st"}, /* Adaptive boost trip levels 1, effective only when boost_intelligent is set to 1, */\
+ { 0x7554, "boost_trip_lvl_2nd"}, /* Adaptive boost trip level 2, effective only when boost_intelligent is set to 1, */\
+ { 0x75a4, "boost_trip_lvl_track"}, /* Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
+ { 0x7602, "track_decay"}, /* DCDC Boost decay speed after a peak value, effective only when boost_track is set to 1, */\
+ { 0x7635, "frst_boost_voltage"}, /* First boost voltage level , */\
+ { 0x7695, "scnd_boost_voltage"}, /* Second boost voltage level , */\
+ { 0x7720, "pga_test_ldo_bypass"}, /* bypass internal PGA LDO , */\
+ { 0x8001, "sel_clk_cs"}, /* Current sense clock duty cycle control , */\
+ { 0x8021, "micadc_speed"}, /* Current sense clock for MiCADC selection - 32/44.1/48 KHz Fs band only, */\
+ { 0x8050, "cs_gain_control"}, /* Current sense gain control , */\
+ { 0x8060, "cs_bypass_gc"}, /* Bypasses the CS gain correction , */\
+ { 0x8087, "cs_gain"}, /* Current sense gain , */\
+ { 0x8200, "enbl_cmfb"}, /* Current sense common mode feedback control , */\
+ { 0x8210, "invertpwm"}, /* Current sense common mode feedback pwm invert control, */\
+ { 0x8222, "cmfb_gain"}, /* Current sense common mode feedback control gain , */\
+ { 0x8256, "cmfb_offset"}, /* Current sense common mode feedback control offset , */\
+ { 0x8305, "cs_ktemp"}, /* First order temperature compensation coefficient , */\
+ { 0x8364, "cs_ktemp2"}, /* Second order temperature compensation coefficient , */\
+ { 0x8400, "cs_adc_bsoinv"}, /* Bitstream inversion for current sense ADC , */\
+ { 0x8421, "cs_adc_hifreq"}, /* Frequency mode current sense ADC , */\
+ { 0x8453, "cs_adc_offset"}, /* Micadc ADC offset setting , */\
+ { 0x8490, "cs_adc_slowdel"}, /* Select delay for current sense ADC (internal decision circuitry), */\
+ { 0x84a4, "cs_adc_gain"}, /* Gain setting for current sense ADC (two's complement), */\
+ { 0x8500, "cs_resonator_enable"}, /* Enable for resonator to improve SRN , */\
+ { 0x8510, "cs_classd_tran_skip"}, /* Skip current sense connection during a classD amplifier transition, */\
+ { 0x8530, "cs_inn_short"}, /* Short current sense negative to common mode , */\
+ { 0x8540, "cs_inp_short"}, /* Short current sense positive to common mode , */\
+ { 0x8550, "cs_ldo_bypass"}, /* Bypass current sense LDO , */\
+ { 0x8560, "cs_ldo_pulldown"}, /* Pull down current sense LDO, only valid if left_enbl_cs_ldo is high, */\
+ { 0x8574, "cs_ldo_voset"}, /* Current sense LDO voltage level setting (two's complement), */\
+ { 0x8700, "enbl_cs_adc"}, /* Enable current sense ADC - I2C direct mode , */\
+ { 0x8710, "enbl_cs_inn1"}, /* Enable connection of current sense negative1 - I2C direct mode, */\
+ { 0x8720, "enbl_cs_inn2"}, /* Enable connection of current sense negative2 - I2C direct mode, */\
+ { 0x8730, "enbl_cs_inp1"}, /* Enable connection of current sense positive1 , */\
+ { 0x8740, "enbl_cs_inp2"}, /* Enable connection of current sense positive2 - I2C direct mode, */\
+ { 0x8750, "enbl_cs_ldo"}, /* Enable current sense LDO - I2C direct mode , */\
+ { 0x8760, "enbl_cs_nofloating_n"}, /* Connect current sense negative to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */\
+ { 0x8770, "enbl_cs_nofloating_p"}, /* Connect current sense positive to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */\
+ { 0x8780, "enbl_cs_vbatldo"}, /* Enable of current sense LDO -- I2C direct mode , */\
+ { 0x8800, "volsense_pwm_sel"}, /* Voltage sense PWM source selection control , */\
+ { 0x8810, "vol_cur_sense_dc_offset"}, /* voltage and current sense decimator offset control, */\
+ { 0x8902, "cursense_comp_delay"}, /* To align compensation signal with current sense signal, */\
+ { 0x8930, "cursense_comp_sign"}, /* To change polarity of compensation for current sense compensation, */\
+ { 0x8940, "enbl_cursense_comp"}, /* To enable current sense compensation , */\
+ { 0x9000, "cf_rst_dsp"}, /* Reset , */\
+ { 0x9011, "cf_dmem"}, /* Target memory , */\
+ { 0x9030, "cf_aif"}, /* Auto increment , */\
+ { 0x9040, "cf_int"}, /* Interrupt - auto clear , */\
+ { 0x9050, "cf_cgate_off"}, /* Coolflux clock gating disabling control , */\
+ { 0x9080, "cf_req_cmd"}, /* Firmware event request rpc command , */\
+ { 0x9090, "cf_req_reset"}, /* Firmware event request reset restart , */\
+ { 0x90a0, "cf_req_mips"}, /* Firmware event request short on mips , */\
+ { 0x90b0, "cf_req_mute_ready"}, /* Firmware event request mute sequence ready , */\
+ { 0x90c0, "cf_req_volume_ready"}, /* Firmware event request volume ready , */\
+ { 0x90d0, "cf_req_damage"}, /* Firmware event request speaker damage detected , */\
+ { 0x90e0, "cf_req_calibrate_ready"}, /* Firmware event request calibration completed , */\
+ { 0x90f0, "cf_req_reserved"}, /* Firmware event request reserved , */\
+ { 0x910f, "cf_madd"}, /* Memory address , */\
+ { 0x920f, "cf_mema"}, /* Activate memory access , */\
+ { 0x9307, "cf_err"}, /* Error flags , */\
+ { 0x9380, "cf_ack_cmd"}, /* Firmware event acknowledge rpc command , */\
+ { 0x9390, "cf_ack_reset"}, /* Firmware event acknowledge reset restart , */\
+ { 0x93a0, "cf_ack_mips"}, /* Firmware event acknowledge short on mips , */\
+ { 0x93b0, "cf_ack_mute_ready"}, /* Firmware event acknowledge mute sequence ready , */\
+ { 0x93c0, "cf_ack_volume_ready"}, /* Firmware event acknowledge volume ready , */\
+ { 0x93d0, "cf_ack_damage"}, /* Firmware event acknowledge speaker damage detected, */\
+ { 0x93e0, "cf_ack_calibrate_ready"}, /* Firmware event acknowledge calibration completed , */\
+ { 0x93f0, "cf_ack_reserved"}, /* Firmware event acknowledge reserved , */\
+ { 0xa007, "mtpkey1"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
+ { 0xa107, "mtpkey2"}, /* MTP KEY2 register , */\
+ { 0xa200, "key01_locked"}, /* Indicates KEY1 is locked , */\
+ { 0xa210, "key02_locked"}, /* Indicates KEY2 is locked , */\
+ { 0xa302, "mtp_man_address_in"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
+ { 0xa330, "man_copy_mtp_to_iic"}, /* Start copying single word from mtp to I2C mtp register, */\
+ { 0xa340, "man_copy_iic_to_mtp"}, /* Start copying single word from I2C mtp register to mtp, */\
+ { 0xa350, "auto_copy_mtp_to_iic"}, /* Start copying all the data from mtp to I2C mtp registers, */\
+ { 0xa360, "auto_copy_iic_to_mtp"}, /* Start copying data from I2C mtp registers to mtp , */\
+ { 0xa400, "faim_set_clkws"}, /* Sets the FaIM controller clock wait state register, */\
+ { 0xa410, "faim_sel_evenrows"}, /* All even rows of the FaIM are selected, active high, */\
+ { 0xa420, "faim_sel_oddrows"}, /* All odd rows of the FaIM are selected, all rows in combination with sel_evenrows, */\
+ { 0xa430, "faim_program_only"}, /* Skip the erase access at wr_faim command (write-program-marginread), */\
+ { 0xa440, "faim_erase_only"}, /* Skip the program access at wr_faim command (write-erase-marginread), */\
+ { 0xa50f, "mtp_man_data_out_msb"}, /* MSB word of MTP manual read data , */\
+ { 0xa60f, "mtp_man_data_out_lsb"}, /* LSB word of MTP manual read data , */\
+ { 0xa70f, "mtp_man_data_in_msb"}, /* MSB word of write data for MTP manual write , */\
+ { 0xa80f, "mtp_man_data_in_lsb"}, /* LSB word of write data for MTP manual write , */\
+ { 0xb010, "bypass_ocpcounter"}, /* Bypass OCP Counter , */\
+ { 0xb020, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
+ { 0xb030, "bypass_ovp"}, /* Bypass OVP , */\
+ { 0xb040, "bypass_uvp"}, /* Bypass UVP , */\
+ { 0xb050, "bypass_otp"}, /* Bypass OTP , */\
+ { 0xb060, "bypass_lost_clk"}, /* Bypass lost clock detector , */\
+ { 0xb070, "ctrl_vpalarm"}, /* vpalarm (uvp ovp handling) , */\
+ { 0xb087, "ocp_threshold"}, /* OCP threshold level , */\
+ { 0xb108, "ext_temp"}, /* External temperature (C) , */\
+ { 0xb190, "ext_temp_sel"}, /* Select temp Speaker calibration , */\
+ { 0xc000, "use_direct_ctrls"}, /* Direct control to overrule several functions for testing, */\
+ { 0xc010, "rst_datapath"}, /* Direct control for datapath reset , */\
+ { 0xc020, "rst_cgu"}, /* Direct control for cgu reset , */\
+ { 0xc038, "enbl_ref"}, /* Switch on the analog references, each part of the references can be switched on/off individually - - I2C direct mode, */\
+ { 0xc0d0, "enbl_ringo"}, /* Enable the ring oscillator for test purpose , */\
+ { 0xc0e0, "use_direct_clk_ctrl"}, /* Direct clock control to overrule several functions for testing, */\
+ { 0xc0f0, "use_direct_pll_ctrl"}, /* Direct PLL control to overrule several functions for testing, */\
+ { 0xc100, "enbl_tsense"}, /* Temperature sensor enable control - I2C direct mode, */\
+ { 0xc110, "tsense_hibias"}, /* Bit to set the biasing in temp sensor to high - I2C direct mode, */\
+ { 0xc120, "enbl_flag_vbg"}, /* Enable flagging of bandgap out of control , */\
+ { 0xc130, "tap_comp_enable"}, /* Tap Comparator enable control - I2C direct mode , */\
+ { 0xc140, "tap_comp_switch_enable"}, /* Tap Comparator Switch enable control - I2C direct mode, */\
+ { 0xc150, "tap_comp_switch_aux_enable"}, /* Tap Comparator Switch enable control - I2C direct mode, */\
+ { 0xc161, "tap_comp_test_enable"}, /* Comparator threshold - fine value , */\
+ { 0xc180, "curdist_enable"}, /* Enable control - I2C direct mode , */\
+ { 0xc190, "vbg2i_enbl"}, /* Enable control - I2C direct mode , */\
+ { 0xc1a0, "bg_filt_bypass_enbl"}, /* Enable control , */\
+ { 0xc20f, "abist_offset"}, /* Offset control for ABIST testing (two's complement), */\
+ { 0xc300, "bypasslatch"}, /* Bypass latch , */\
+ { 0xc311, "sourcea"}, /* Set OUTA to , */\
+ { 0xc331, "sourceb"}, /* Set OUTB to , */\
+ { 0xc350, "inverta"}, /* Invert pwma test signal , */\
+ { 0xc360, "invertb"}, /* Invert pwmb test signal , */\
+ { 0xc374, "pulselength"}, /* Pulse length setting test input for amplifier (clock d - k*2048*fs), */\
+ { 0xc3c0, "tdm_enable_loopback"}, /* TDM loopback test , */\
+ { 0xc3d0, "test_abistfft_enbl"}, /* FFT Coolflux , */\
+ { 0xc3e0, "test_pwr_switch"}, /* Test mode for digital power switches core sw/mem sw/micvdd sw, */\
+ { 0xc400, "bst_bypasslatch"}, /* Bypass latch in boost converter , */\
+ { 0xc411, "bst_source"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
+ { 0xc430, "bst_invertb"}, /* Invert pwmbst test signal , */\
+ { 0xc444, "bst_pulselength"}, /* Pulse length setting test input for boost converter , */\
+ { 0xc490, "test_bst_ctrlsthv"}, /* Test mode for boost control stage , */\
+ { 0xc4a0, "test_bst_iddq"}, /* IDDQ testing in power stage of boost converter , */\
+ { 0xc4b0, "test_bst_rdson"}, /* RDSON testing - boost power stage , */\
+ { 0xc4c0, "test_bst_cvi"}, /* CVI testing - boost power stage , */\
+ { 0xc4d0, "test_bst_ocp"}, /* Boost OCP. For old ocp (ctrl_reversebst is 0), For new ocp (ctrl_reversebst is 1), */\
+ { 0xc4e0, "test_bst_sense"}, /* Test option for the sense NMOS in booster for current mode control., */\
+ { 0xc500, "test_cvi"}, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */\
+ { 0xc510, "test_discrete"}, /* Test function noise measurement , */\
+ { 0xc520, "test_iddq"}, /* Set the power stages in iddq mode for gate stress., */\
+ { 0xc540, "test_rdson"}, /* Analog BIST, switch to enable Rdson measurement , */\
+ { 0xc550, "test_sdelta"}, /* Analog BIST, noise test , */\
+ { 0xc560, "bypass_fro8"}, /* Bypass fro8 with pdm_clk , */\
+ { 0xc570, "test_enbl_cs"}, /* Enable for digimux mode of current sense , */\
+ { 0xc5b0, "pga_test_enable"}, /* Enable PGA test mode , */\
+ { 0xc5c0, "pga_test_offset_enable"}, /* Enable PGA test offset , */\
+ { 0xc5d0, "pga_test_shortinput_enable"}, /* Enable PGA test short input , */\
+ { 0xc600, "enbl_pwm_dcc"}, /* Enables direct control of pwm duty cycle for DCDC power stage, */\
+ { 0xc613, "pwm_dcc_cnt"}, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */\
+ { 0xc650, "enbl_ldo_stress"}, /* Enable stress of internal supply voltages powerstages, */\
+ { 0xc660, "enbl_powerswitch"}, /* Vddd core power switch control - overrules the manager control, */\
+ { 0xc707, "digimuxa_sel"}, /* DigimuxA input selection control routed to DIO4 (see Digimux list for details), */\
+ { 0xc787, "digimuxb_sel"}, /* DigimuxB input selection control routed to DIO3 (see Digimux list for details), */\
+ { 0xc807, "digimuxc_sel"}, /* DigimuxC input selection control routed to TDO (see Digimux list for details), */\
+ { 0xc901, "dio1_ehs"}, /* Speed/load setting for DIO1 IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
+ { 0xc921, "dio2_ehs"}, /* Speed/load setting for DIO2 IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
+ { 0xc941, "dio3_ehs"}, /* Speed/load setting for DIO3 cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
+ { 0xc961, "dio4_ehs"}, /* Speed/load setting for DIO4 IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
+ { 0xc981, "spdmo_ehs"}, /* Speed/load setting for PDMO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
+ { 0xc9a1, "tdo_ehs"}, /* Speed/load setting for TDM IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
+ { 0xc9c0, "int_ehs"}, /* Slew Rate INT IO cell, clk or data mode range (see IIC3V3 IO cell datasheet), */\
+ { 0xc9d0, "pdmclk_ehs"}, /* Slew RateBCK2/PDMCLK IO cell, clk or data mode range (see IIC3V3 IO cell datasheet), */\
+ { 0xc9e0, "fs2_ehs"}, /* Slew Rate DS2 IO cell, clk or data mode range (see IIC3V3 IO cell datasheet), */\
+ { 0xc9f0, "hs_mode"}, /* I2C high speed mode control , */\
+ { 0xca00, "enbl_anamux1"}, /* Enable anamux1 , */\
+ { 0xca10, "enbl_anamux2"}, /* Enable anamux2 , */\
+ { 0xca20, "enbl_anamux3"}, /* Enable anamux3 , */\
+ { 0xca30, "enbl_anamux4"}, /* Enable anamux4 , */\
+ { 0xca74, "anamux1"}, /* Anamux selection control - anamux on TEST1 , */\
+ { 0xcb04, "anamux2"}, /* Anamux selection control - anamux on TEST2 , */\
+ { 0xcb54, "anamux3"}, /* Anamux selection control - anamux on TEST3 , */\
+ { 0xcba4, "anamux4"}, /* Anamux selection control - anamux on TEST4 , */\
+ { 0xcc05, "pll_seli_lbw"}, /* PLL SELI - Low B/W PLL control mode or I2C direct PLL control mode only, */\
+ { 0xcc64, "pll_selp_lbw"}, /* PLL SELP - Low B/W PLL control mode or I2C direct PLL control mode only, */\
+ { 0xccb3, "pll_selr_lbw"}, /* PLL SELR - Low B/W PLL control mode or I2C direct PLL control mode only, */\
+ { 0xccf0, "sel_user_pll_bw"}, /* PLL Low Bandwidth Mode control , */\
+ { 0xcdf0, "pll_frm"}, /* PLL free running mode control; 1 in TCB direct control mode, else this control bit, */\
+ { 0xce09, "pll_ndec"}, /* PLL NDEC - I2C direct PLL control mode only , */\
+ { 0xcea0, "pll_mdec_msb"}, /* MSB of pll_mdec - I2C direct PLL control mode only, */\
+ { 0xceb0, "enbl_pll"}, /* Enables PLL in I2C direct PLL control mode only , */\
+ { 0xcec0, "enbl_fro8"}, /* Enables FRO8M in I2C direct control mode only , */\
+ { 0xced0, "pll_bypass"}, /* PLL bypass control in I2C direct PLL control mode only, */\
+ { 0xcee0, "pll_directi"}, /* PLL directi control in I2C direct PLL control mode only, */\
+ { 0xcef0, "pll_directo"}, /* PLL directo control in I2C direct PLL control mode only, */\
+ { 0xcf0f, "pll_mdec_lsb"}, /* Bits 15..0 of PLL MDEC are I2C direct PLL control mode only, */\
+ { 0xd006, "pll_pdec"}, /* PLL PDEC - I2C direct PLL control mode only , */\
+ { 0xd10f, "tsig_freq_lsb"}, /* Internal sinus test generator frequency control , */\
+ { 0xd202, "tsig_freq_msb"}, /* Select internal sinus test generator, frequency control msb bits, */\
+ { 0xd230, "inject_tsig"}, /* Control bit to switch to internal sinus test generator, */\
+ { 0xd283, "tsig_gain"}, /* Test signal gain , */\
+ { 0xd300, "adc10_reset"}, /* Reset for ADC10 - I2C direct control mode , */\
+ { 0xd311, "adc10_test"}, /* Test mode selection signal for ADC10 - I2C direct control mode, */\
+ { 0xd332, "adc10_sel"}, /* Select the input to convert for ADC10 - I2C direct control mode, */\
+ { 0xd364, "adc10_prog_sample"}, /* ADC10 program sample setting - I2C direct control mode, */\
+ { 0xd3b0, "adc10_enbl"}, /* Enable ADC10 - I2C direct control mode , */\
+ { 0xd3c0, "bypass_lp_vbat"}, /* Bypass control for Low pass filter in batt sensor , */\
+ { 0xd409, "data_adc10_tempbat"}, /* ADC 10 data output data for testing , */\
+ { 0xd507, "ctrl_digtoana_hidden"}, /* Spare digital to analog control bits - Hidden , */\
+ { 0xd580, "enbl_clk_range_chk"}, /* Clock out of range , */\
+ { 0xd601, "clkdiv_dsp_sel"}, /* DSP clock divider selection in direct clock control mode, */\
+ { 0xd621, "clkdiv_audio_sel"}, /* Audio clock divider selection in direct clock control mode, */\
+ { 0xd641, "clkdiv_muxa_sel"}, /* DCDC MUXA clock divider selection in direct clock control mode, */\
+ { 0xd661, "clkdiv_muxb_sel"}, /* DCDC MUXB clock divider selection in direct clock control mode, */\
+ { 0xd681, "dsp_tap_clk"}, /* Dsp clock frequency selection in TAP mode; , */\
+ { 0xd6a1, "sel_wdt_clk"}, /* Watch dog clock post divider value , */\
+ { 0xd6c1, "sel_tim_clk"}, /* Timer clock post divider value , */\
+ { 0xd700, "ads1_ehs"}, /* Slew Rate ADS1 IO cell, clk or data mode range (see IIC3V3 IO cell datasheet), */\
+ { 0xd710, "ads2_ehs"}, /* Slew Rate ADS2 IO cell, clk or data mode range (see IIC3V3 IO cell datasheet), */\
+ { 0xd822, "test_parametric_io"}, /* test io parametric , */\
+ { 0xd850, "ctrl_bst_clk_lp1"}, /* boost clock control in low power mode1 , */\
+ { 0xd861, "test_spare_out1"}, /* test spare out 1 , */\
+ { 0xd880, "bst_dcmbst"}, /* dcm boost - I2C direct mode , */\
+ { 0xd8a1, "force_pga_clock"}, /* force pga clock , */\
+ { 0xd8c3, "test_spare_out2"}, /* test spare out 1 , */\
+ { 0xd900, "overrules_usercase"}, /* Overrule Mode control use , */\
+ { 0xd910, "ovr_switch_ref"}, /* Overrule Value , */\
+ { 0xd920, "ovr_enbl_pll"}, /* Overrule Value , */\
+ { 0xd930, "ovr_switch_amp"}, /* Overrule Value , */\
+ { 0xd940, "ovr_enbl_clk_cs"}, /* Overrule Value , */\
+ { 0xd951, "ovr_sel_clk_cs"}, /* CS clock selection overrule , */\
+ { 0xd970, "ovr_switch_cs"}, /* Overrule Value , */\
+ { 0xd980, "ovr_enbl_csvs_ss"}, /* Overrule Value , */\
+ { 0xd990, "ovr_enbl_comp"}, /* Overrule Value , */\
+ { 0xed00, "enbl_fro8cal"}, /* Enable FRO calibration , */\
+ { 0xed10, "start_fro8_calibration"}, /* Start FRO8 Calibration , */\
+ { 0xed20, "fro8_calibration_done"}, /* FRO8 Calibration done - Read Only , */\
+ { 0xed45, "fro8_auto_trim_val"}, /* Calibration value from Auto Calibration block, to be written into MTP - Read Only, */\
+ { 0xee0f, "sw_profile"}, /* Software profile data , */\
+ { 0xef0f, "sw_vstep"}, /* Software vstep information , */\
+ { 0xf000, "calibration_onetime"}, /* Calibration schedule , */\
+ { 0xf010, "calibr_ron_done"}, /* Calibration Ron executed , */\
+ { 0xf020, "calibr_dcdc_api_calibrate"}, /* Calibration current limit DCDC , */\
+ { 0xf030, "calibr_dcdc_delta_sign"}, /* Sign bit for delta calibration current limit DCDC , */\
+ { 0xf042, "calibr_dcdc_delta"}, /* Calibration delta current limit DCDC , */\
+ { 0xf078, "calibr_speaker_info"}, /* Reserved space for allowing customer to store speaker information, */\
+ { 0xf105, "calibr_vout_offset"}, /* DCDC offset calibration 2's complement (key1 protected), */\
+ { 0xf163, "spare_mtp1_9_6"}, /* HW gain module - left channel (2's complement) , */\
+ { 0xf1a5, "spare_mtp1_15_10"}, /* Offset for amplifier, HW gain module - left channel (2's complement), */\
+ { 0xf203, "calibr_gain"}, /* HW gain module (2's complement) , */\
+ { 0xf245, "calibr_offset"}, /* Offset for amplifier, HW gain module (2's complement), */\
+ { 0xf2a3, "spare_mtp2_13_10"}, /* Trimming of LDO (2.7V) , */\
+ { 0xf307, "spare_mtp3_7_0"}, /* SPARE , */\
+ { 0xf387, "calibr_gain_cs"}, /* Current sense gain (signed two's complement format), */\
+ { 0xf40f, "calibr_R25C"}, /* Ron resistance of speaker coil , */\
+ { 0xf50f, "spare_mtp5_15_0"}, /* SPARE , */\
+ { 0xf600, "mtp_lock_enbl_coolflux"}, /* Disable function dcdcoff_mode , */\
+ { 0xf610, "mtp_pwm_delay_enbl_clk_auto_gating"}, /* Auto clock gating on pwm_delay , */\
+ { 0xf620, "mtp_ocp_enbl_clk_auto_gating"}, /* Auto clock gating on module ocp , */\
+ { 0xf630, "mtp_disable_clk_a_gating"}, /* Disable clock_a gating , */\
+ { 0xf642, "spare_mtp6_6_3"}, /* SPARE , */\
+ { 0xf686, "spare_mtp6_14_8"}, /* Offset of left amplifier level shifter B , */\
+ { 0xf706, "ctrl_offset_a"}, /* Offset of level shifter A , */\
+ { 0xf786, "ctrl_offset_b"}, /* Offset of amplifier level shifter B , */\
+ { 0xf806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
+ { 0xf870, "htol_iic_addr_en"}, /* HTOL I2C address enable control , */\
+ { 0xf884, "calibr_temp_offset"}, /* Temperature offset 2's compliment (key1 protected), */\
+ { 0xf8d2, "calibr_temp_gain"}, /* Temperature gain 2's compliment (key1 protected) , */\
+ { 0xf910, "disable_sam_mode"}, /* Disable sam mode , */\
+ { 0xf920, "mtp_lock_bypass_clipper"}, /* Disable function bypass_clipper , */\
+ { 0xf930, "mtp_lock_max_dcdc_voltage"}, /* Disable programming of max dcdc boost voltage , */\
+ { 0xf943, "calibr_vbg_trim"}, /* Bandgap trimming control , */\
+ { 0xf987, "type_bits_fw"}, /* MTP-control FW - See Firmware I2C API document for details, */\
+ { 0xfa0f, "mtpdataA"}, /* MTPdataA (key1 protected) , */\
+ { 0xfb0f, "mtpdataB"}, /* MTPdataB (key1 protected) , */\
+ { 0xfc0f, "mtpdataC"}, /* MTPdataC (key1 protected) , */\
+ { 0xfd0f, "mtpdataD"}, /* MTPdataD (key1 protected) , */\
+ { 0xfe0f, "mtpdataE"}, /* MTPdataE (key1 protected) , */\
+ { 0xff05, "fro8_trim"}, /* 8 MHz oscillator trim code , */\
+ { 0xff61, "fro8_short_nwell_r"}, /* Short 4 or 6 n-well resistors , */\
+ { 0xff81, "fro8_boost_i"}, /* Self bias current selection , */\
+ { 0xffff, "Unknown bitfield enum" } /* not found */\
+};
+
+enum tfa9912_irq {
+ tfa9912_irq_stvdds = 0,
+ tfa9912_irq_stplls = 1,
+ tfa9912_irq_stotds = 2,
+ tfa9912_irq_stovds = 3,
+ tfa9912_irq_stuvds = 4,
+ tfa9912_irq_stclks = 5,
+ tfa9912_irq_stmtpb = 6,
+ tfa9912_irq_stnoclk = 7,
+ tfa9912_irq_stspks = 8,
+ tfa9912_irq_stacs = 9,
+ tfa9912_irq_stsws = 10,
+ tfa9912_irq_stwds = 11,
+ tfa9912_irq_stamps = 12,
+ tfa9912_irq_starefs = 13,
+ tfa9912_irq_stadccr = 14,
+ tfa9912_irq_stbodnok = 15,
+ tfa9912_irq_stbstcu = 16,
+ tfa9912_irq_stbsthi = 17,
+ tfa9912_irq_stbstoc = 18,
+ tfa9912_irq_stbstpkcur = 19,
+ tfa9912_irq_stbstvc = 20,
+ tfa9912_irq_stbst86 = 21,
+ tfa9912_irq_stbst93 = 22,
+ tfa9912_irq_strcvld = 23,
+ tfa9912_irq_stocpl = 24,
+ tfa9912_irq_stocpr = 25,
+ tfa9912_irq_stmwsrc = 26,
+ tfa9912_irq_stmwcfc = 27,
+ tfa9912_irq_stmwsmu = 28,
+ tfa9912_irq_stcfmer = 29,
+ tfa9912_irq_stcfmac = 30,
+ tfa9912_irq_stclkoor = 31,
+ tfa9912_irq_sttdmer = 32,
+ tfa9912_irq_stclpl = 33,
+ tfa9912_irq_stclpr = 34,
+ tfa9912_irq_stocpm = 35,
+ tfa9912_irq_stlp1 = 37,
+ tfa9912_irq_stla = 38,
+ tfa9912_irq_stvddp = 39,
+ tfa9912_irq_sttapdet = 40,
+ tfa9912_irq_staudmod = 41,
+ tfa9912_irq_stsammod = 42,
+ tfa9912_irq_sttapmod = 43,
+ tfa9912_irq_sttaptrg = 44,
+ tfa9912_irq_max = 45,
+ tfa9912_irq_all = -1 /* all irqs */};
+
+#define TFA9912_IRQ_NAMETABLE static tfaIrqName_t Tfa9912IrqNames[] = {\
+ { 0, "STVDDS"},\
+ { 1, "STPLLS"},\
+ { 2, "STOTDS"},\
+ { 3, "STOVDS"},\
+ { 4, "STUVDS"},\
+ { 5, "STCLKS"},\
+ { 6, "STMTPB"},\
+ { 7, "STNOCLK"},\
+ { 8, "STSPKS"},\
+ { 9, "STACS"},\
+ { 10, "STSWS"},\
+ { 11, "STWDS"},\
+ { 12, "STAMPS"},\
+ { 13, "STAREFS"},\
+ { 14, "STADCCR"},\
+ { 15, "STBODNOK"},\
+ { 16, "STBSTCU"},\
+ { 17, "STBSTHI"},\
+ { 18, "STBSTOC"},\
+ { 19, "STBSTPKCUR"},\
+ { 20, "STBSTVC"},\
+ { 21, "STBST86"},\
+ { 22, "STBST93"},\
+ { 23, "STRCVLD"},\
+ { 24, "STOCPL"},\
+ { 25, "STOCPR"},\
+ { 26, "STMWSRC"},\
+ { 27, "STMWCFC"},\
+ { 28, "STMWSMU"},\
+ { 29, "STCFMER"},\
+ { 30, "STCFMAC"},\
+ { 31, "STCLKOOR"},\
+ { 32, "STTDMER"},\
+ { 33, "STCLPL"},\
+ { 34, "STCLPR"},\
+ { 35, "STOCPM"},\
+ { 36, "36"},\
+ { 37, "STLP1"},\
+ { 38, "STLA"},\
+ { 39, "STVDDP"},\
+ { 40, "STTAPDET"},\
+ { 41, "STAUDMOD"},\
+ { 42, "STSAMMOD"},\
+ { 43, "STTAPMOD"},\
+ { 44, "STTAPTRG"},\
+ { 45, "45"},\
+};
+#endif /* _TFA9912_TFAFIELDNAMES_H */
diff --git a/src/tfa_container.c b/sound/soc/codecs/tfa_container.c
similarity index 87%
rename from src/tfa_container.c
rename to sound/soc/codecs/tfa_container.c
index 84f080e..0cea84f 100644
--- a/src/tfa_container.c
+++ b/sound/soc/codecs/tfa_container.c
@@ -1,2376 +1,2410 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include "dbgprint.h"
-#include "tfa_container.h"
-#include "tfa.h"
-#include "tfa98xx_tfafieldnames.h"
-#include "tfa_internal.h"
-
- /* defines */
-#define MODULE_BIQUADFILTERBANK 2
-#define BIQUAD_COEFF_SIZE 6
-
-/* module globals */
-static uint8_t gslave_address = 0; /* This is used to SET the slave with the --slave option */
-
-static int float_to_int(uint32_t x)
-{
- unsigned e = (0x7F + 31) - ((*(unsigned *)&x & 0x7F800000) >> 23);
- unsigned m = 0x80000000 | (*(unsigned *)&x << 8);
- return -(int)((m >> e) & -(e < 32));
-}
-
-/*
- * check the container file
-*/
-enum tfa_error tfa_load_cnt(void *cnt, int length)
-{
- nxpTfaContainer_t *cntbuf = (nxpTfaContainer_t *)cnt;
-
- if (length > TFA_MAX_CNT_LENGTH) {
- pr_err("incorrect length\n");
- return tfa_error_container;
- }
-
- if (HDR(cntbuf->id[0], cntbuf->id[1]) == 0) {
- pr_err("header is 0\n");
- return tfa_error_container;
- }
-
- if ((HDR(cntbuf->id[0], cntbuf->id[1])) != paramsHdr) {
- pr_err("wrong header type: 0x%02x 0x%02x\n", cntbuf->id[0], cntbuf->id[1]);
- return tfa_error_container;
- }
-
- if (cntbuf->size == 0) {
- pr_err("data size is 0\n");
- return tfa_error_container;
- }
-
- /* check CRC */
- if (tfaContCrcCheckContainer(cntbuf)) {
- pr_err("CRC error\n");
- return tfa_error_container;
- }
-
- /* check sub version level */
- if ((cntbuf->subversion[1] != NXPTFA_PM_SUBVERSION) &&
- (cntbuf->subversion[0] != '0')) {
- pr_err("container sub-version not supported: %c%c\n",
- cntbuf->subversion[0], cntbuf->subversion[1]);
- return tfa_error_container;
- }
-
- return tfa_error_ok;
-}
-
-/*
- * Dump the contents of the file header
- */
-void tfaContShowHeader(nxpTfaHeader_t *hdr) {
- char _id[2];
-
- pr_debug("File header\n");
-
- _id[1] = hdr->id >> 8;
- _id[0] = hdr->id & 0xff;
- pr_debug("\tid:%.2s version:%.2s subversion:%.2s\n", _id,
- hdr->version, hdr->subversion);
- pr_debug("\tsize:%d CRC:0x%08x \n", hdr->size, hdr->CRC);
- pr_debug("\tcustomer:%.8s application:%.8s type:%.8s\n", hdr->customer,
- hdr->application, hdr->type);
-}
-
-/*
- * return device list dsc from index
- */
-nxpTfaDeviceList_t *tfaContGetDevList(nxpTfaContainer_t *cont, int dev_idx)
-{
- uint8_t *base = (uint8_t *)cont;
-
- if (cont == NULL)
- return NULL;
-
- if ((dev_idx < 0) || (dev_idx >= cont->ndev))
- return NULL;
-
- if (cont->index[dev_idx].type != dscDevice)
- return NULL;
-
- base += cont->index[dev_idx].offset;
- return (nxpTfaDeviceList_t *)base;
-}
-
-/*
- * get the Nth profile for the Nth device
- */
-nxpTfaProfileList_t *tfaContGetDevProfList(nxpTfaContainer_t * cont, int devIdx, int profIdx)
-{
- nxpTfaDeviceList_t *dev;
- int idx, hit;
- uint8_t *base = (uint8_t *)cont;
-
- dev = tfaContGetDevList(cont, devIdx);
- if (dev) {
- for (idx = 0, hit = 0; idx < dev->length; idx++) {
- if (dev->list[idx].type == dscProfile) {
- if (profIdx == hit++)
- return (nxpTfaProfileList_t *)(dev->list[idx].offset + base);
- }
- }
- }
-
- return NULL;
-}
-
-/*
- * get the number of profiles for the Nth device
- */
-int tfa_cnt_get_dev_nprof(struct tfa_device *tfa)
-{
- nxpTfaDeviceList_t *dev;
- int idx, nprof = 0;
-
- if (tfa->cnt == NULL)
- return 0;
-
- if ((tfa->dev_idx < 0) || (tfa->dev_idx >= tfa->cnt->ndev))
- return 0;
-
- dev = tfaContGetDevList(tfa->cnt, tfa->dev_idx);
- if (dev) {
- for (idx = 0; idx < dev->length; idx++) {
- if (dev->list[idx].type == dscProfile) {
- nprof++;
- }
- }
- }
-
- return nprof;
-}
-
-/*
- * get the Nth lifedata for the Nth device
- */
-nxpTfaLiveDataList_t *tfaContGetDevLiveDataList(nxpTfaContainer_t * cont, int devIdx,
- int lifeDataIdx)
-{
- nxpTfaDeviceList_t *dev;
- int idx, hit;
- uint8_t *base = (uint8_t *)cont;
-
- dev = tfaContGetDevList(cont, devIdx);
- if (dev) {
- for (idx = 0, hit = 0; idx < dev->length; idx++) {
- if (dev->list[idx].type == dscLiveData) {
- if (lifeDataIdx == hit++)
- return (nxpTfaLiveDataList_t *)
- (dev->list[idx].offset + base);
- }
- }
- }
-
- return NULL;
-}
-
-/*
- * Get the max volume step associated with Nth profile for the Nth device
- */
-int tfacont_get_max_vstep(struct tfa_device *tfa, int prof_idx) {
- nxpTfaVolumeStep2File_t *vp;
- struct nxpTfaVolumeStepMax2File *vp3;
- int vstep_count = 0;
- vp = (nxpTfaVolumeStep2File_t *)tfacont_getfiledata(tfa, prof_idx, volstepHdr);
- if (vp == NULL)
- return 0;
- /* check the header type to load different NrOfVStep appropriately */
- if (tfa->tfa_family == 2) {
- /* this is actually tfa2, so re-read the buffer*/
- vp3 = (struct nxpTfaVolumeStepMax2File *)
- tfacont_getfiledata(tfa, prof_idx, volstepHdr);
- if (vp3) {
- vstep_count = vp3->NrOfVsteps;
- }
- }
- else {
- /* this is max1*/
- if (vp) {
- vstep_count = vp->vsteps;
- }
- }
- return vstep_count;
-}
-
-/**
- * Get the file contents associated with the device or profile
- * Search within the device tree, if not found, search within the profile
- * tree. There can only be one type of file within profile or device.
- */
-nxpTfaFileDsc_t *tfacont_getfiledata(struct tfa_device *tfa, int prof_idx, enum nxpTfaHeaderType type)
-{
- nxpTfaDeviceList_t *dev;
- nxpTfaProfileList_t *prof;
- nxpTfaFileDsc_t *file;
- nxpTfaHeader_t *hdr;
- unsigned int i;
-
- if (tfa->cnt == NULL) {
- pr_err("invalid pointer to container file\n");
- return NULL;
- }
-
- dev = tfaContGetDevList(tfa->cnt, tfa->dev_idx);
- if (dev == NULL) {
- pr_err("invalid pointer to container file device list\n");
- return NULL;
- }
-
- /* process the device list until a file type is encountered */
- for (i = 0; i < dev->length; i++) {
- if (dev->list[i].type == dscFile) {
- file = (nxpTfaFileDsc_t *)(dev->list[i].offset + (uint8_t *)tfa->cnt);
- if (file != NULL) {
- hdr = (nxpTfaHeader_t *)file->data;
- /* check for file type */
- if (hdr->id == type) {
- return (nxpTfaFileDsc_t *)&file->data;
- }
- }
- }
- }
-
- /* File not found in device tree.
- * So, look in the profile list until the file type is encountered
- */
- prof = tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx);
- if (prof == NULL) {
- pr_err("invalid pointer to container file profile list\n");
- return NULL;
- }
-
- for (i = 0; i < prof->length; i++) {
- if (prof->list[i].type == dscFile) {
- file = (nxpTfaFileDsc_t *)(prof->list[i].offset + (uint8_t *)tfa->cnt);
- if (file != NULL) {
- hdr = (nxpTfaHeader_t *)file->data;
- if (hdr != NULL) {
- /* check for file type */
- if (hdr->id == type) {
- return (nxpTfaFileDsc_t *)&file->data;
- }
- }
- }
- }
- }
-
- if (tfa->verbose)
- pr_debug("%s: no file found of type %d\n", __FUNCTION__, type);
-
- return NULL;
-}
-
-/*
- * write a parameter file to the device
- */
-static enum Tfa98xx_Error tfaContWriteVstep(struct tfa_device *tfa, nxpTfaVolumeStep2File_t *vp, int vstep)
-{
- enum Tfa98xx_Error err;
- unsigned short vol;
-
- if (vstep < vp->vsteps) {
- /* vol = (unsigned short)(voldB / (-0.5f)); */
- vol = (unsigned short)(-2 * float_to_int(*((uint32_t *)&vp->vstep[vstep].attenuation)));
- if (vol > 255) /* restricted to 8 bits */
- vol = 255;
-
- err = tfa98xx_set_volume_level(tfa, vol);
- if (err != Tfa98xx_Error_Ok)
- return err;
-
- err = tfa98xx_dsp_write_preset(tfa, sizeof(vp->vstep[0].preset), vp->vstep[vstep].preset);
- if (err != Tfa98xx_Error_Ok)
- return err;
- err = tfa_cont_write_filterbank(tfa, vp->vstep[vstep].filter);
-
- }
- else {
- pr_err("Incorrect volume given. The value vstep[%d] >= %d\n", vstep, vp->vsteps);
- err = Tfa98xx_Error_Bad_Parameter;
- }
-
- if (tfa->verbose) pr_debug("vstep[%d][%d]\n", tfa->dev_idx, vstep);
-
- return err;
-}
-
-static struct nxpTfaVolumeStepMessageInfo *
-tfaContGetmsgInfoFromReg(struct nxpTfaVolumeStepRegisterInfo *regInfo)
-{
- char *p = (char*)regInfo;
- p += sizeof(regInfo->NrOfRegisters) + (regInfo->NrOfRegisters * sizeof(uint32_t));
- return (struct nxpTfaVolumeStepMessageInfo*) p;
-}
-
-static int
-tfaContGetmsgLen(struct nxpTfaVolumeStepMessageInfo *msgInfo)
-{
- return (msgInfo->MessageLength.b[0] << 16) + (msgInfo->MessageLength.b[1] << 8) + msgInfo->MessageLength.b[2];
-}
-
-static struct nxpTfaVolumeStepMessageInfo *
-tfaContGetNextmsgInfo(struct nxpTfaVolumeStepMessageInfo *msgInfo)
-{
- char *p = (char*)msgInfo;
- int msgLen = tfaContGetmsgLen(msgInfo);
- int type = msgInfo->MessageType;
-
- p += sizeof(msgInfo->MessageType) + sizeof(msgInfo->MessageLength);
- if (type == 3)
- p += msgLen;
- else
- p += msgLen * 3;
-
- return (struct nxpTfaVolumeStepMessageInfo*) p;
-}
-
-static struct nxpTfaVolumeStepRegisterInfo*
-tfaContGetNextRegFromEndInfo(struct nxpTfaVolumeStepMessageInfo *msgInfo)
-{
- char *p = (char*)msgInfo;
- p += sizeof(msgInfo->NrOfMessages);
- return (struct nxpTfaVolumeStepRegisterInfo*) p;
-
-}
-
-static struct nxpTfaVolumeStepRegisterInfo*
-tfaContGetRegForVstep(nxpTfaVolumeStepMax2File_t *vp, int idx)
-{
- int i, j, nrMessage;
-
- struct nxpTfaVolumeStepRegisterInfo *regInfo
- = (struct nxpTfaVolumeStepRegisterInfo*) vp->vstepsBin;
- struct nxpTfaVolumeStepMessageInfo *msgInfo = NULL;
-
- for (i = 0; i < idx; i++) {
- msgInfo = tfaContGetmsgInfoFromReg(regInfo);
- nrMessage = msgInfo->NrOfMessages;
-
- for (j = 0; j < nrMessage; j++) {
- msgInfo = tfaContGetNextmsgInfo(msgInfo);
- }
- regInfo = tfaContGetNextRegFromEndInfo(msgInfo);
- }
-
- return regInfo;
-}
-
-#pragma pack (push, 1)
-struct tfa_partial_msg_block {
- uint8_t offset;
- uint16_t change;
- uint8_t update[16][3];
-};
-#pragma pack (pop)
-
-static enum Tfa98xx_Error tfaContWriteVstepMax2_One(struct tfa_device *tfa, struct nxpTfaVolumeStepMessageInfo *new_msg,
- struct nxpTfaVolumeStepMessageInfo *old_msg, int enable_partial_update)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- int len = (tfaContGetmsgLen(new_msg) - 1) * 3;
- char *buf = (char*)new_msg->ParameterData;
- uint8_t *partial = NULL;
- uint8_t cmdid[3];
- int use_partial_coeff = 0;
-
- if (enable_partial_update) {
- if (new_msg->MessageType != old_msg->MessageType) {
- pr_debug("Message type differ - Disable Partial Update\n");
- enable_partial_update = 0;
- }
- else if (tfaContGetmsgLen(new_msg) != tfaContGetmsgLen(old_msg)) {
- pr_debug("Message Length differ - Disable Partial Update\n");
- enable_partial_update = 0;
- }
- }
-
- if ((enable_partial_update) && (new_msg->MessageType == 1)) {
- /* No patial updates for message type 1 (Coefficients) */
- enable_partial_update = 0;
- if ((tfa->rev & 0xff) == 0x88) {
- use_partial_coeff = 1;
- }
- else if ((tfa->rev & 0xff) == 0x13) {
- use_partial_coeff = 1;
- }
- }
-
- /* Change Message Len to the actual buffer len */
- memcpy(cmdid, new_msg->CmdId, sizeof(cmdid));
-
- /* The algoparams and mbdrc msg id will be changed to the reset type when SBSL=0
- * if SBSL=1 the msg will remain unchanged. It's up to the tuning engineer to choose the 'without_reset'
- * types inside the vstep. In other words: the reset msg is applied during SBSL==0 else it remains unchanged.
- */
- if (tfa_needs_reset(tfa) == 1) {
- if (new_msg->MessageType == 0) {
- cmdid[2] = SB_PARAM_SET_ALGO_PARAMS;
- if (tfa->verbose)
- pr_debug("P-ID for SetAlgoParams modified!\n");
- }
- else if (new_msg->MessageType == 2) {
- cmdid[2] = SB_PARAM_SET_MBDRC;
- if (tfa->verbose)
- pr_debug("P-ID for SetMBDrc modified!\n");
- }
- }
-
- /*
- * +sizeof(struct tfa_partial_msg_block) will allow to fit one
- * additonnal partial block If the partial update goes over the len of
- * a regular message ,we can safely write our block and check afterward
- * that we are over the size of a usual update
- */
- if (enable_partial_update) {
- partial = kmem_cache_alloc(tfa->cachep, GFP_KERNEL);
- if (!partial)
- pr_debug("Partial update memory error - Disabling\n");
- }
-
- if (partial) {
- uint8_t offset = 0, i = 0;
- uint16_t *change;
- uint8_t *n = new_msg->ParameterData;
- uint8_t *o = old_msg->ParameterData;
- uint8_t *p = partial;
- uint8_t* trim = partial;
-
- /* set dspFiltersReset */
- *p++ = 0x02;
- *p++ = 0x00;
- *p++ = 0x00;
-
- while ((o < (old_msg->ParameterData + len)) &&
- (p < (partial + len - 3))) {
- if ((offset == 0xff) ||
- (memcmp(n, o, 3 * sizeof(uint8_t)))) {
- *p++ = offset;
- change = (uint16_t*)p;
- *change = 0;
- p += 2;
-
- for (i = 0;
- (i < 16) && (o < (old_msg->ParameterData + len));
- i++, n += 3, o += 3) {
- if (memcmp(n, o, 3 * sizeof(uint8_t))) {
- *change |= BIT(i);
- memcpy(p, n, 3);
- p += 3;
- trim = p;
- }
- }
-
- offset = 0;
- *change = cpu_to_be16(*change);
- }
- else {
- n += 3;
- o += 3;
- offset++;
- }
- }
-
- if (trim == partial) {
- pr_debug("No Change in message - discarding %d bytes\n", len);
- len = 0;
-
- }
- else if (trim < (partial + len - 3)) {
- pr_debug("Using partial update: %d -> %d bytes\n", len, (int)(trim - partial + 3));
-
- /* Add the termination marker */
- memset(trim, 0x00, 3);
- trim += 3;
-
- /* Signal This will be a partial update */
- cmdid[2] |= BIT(6);
- buf = (char*)partial;
- len = (int)(trim - partial);
- }
- else {
- pr_debug("Partial too big - use regular update\n");
- }
- }
-
- if (use_partial_coeff) {
- err = dsp_partial_coefficients(tfa, old_msg->ParameterData, new_msg->ParameterData);
- }
- else if (len) {
- uint8_t *buffer;
-
- if (tfa->verbose)
- pr_debug("Command-ID used: 0x%02x%02x%02x \n", cmdid[0], cmdid[1], cmdid[2]);
-
- buffer = kmem_cache_alloc(tfa->cachep, GFP_KERNEL);
- if (buffer == NULL) {
- err = Tfa98xx_Error_Fail;
- }
- else {
- memcpy(&buffer[0], cmdid, 3);
- memcpy(&buffer[3], buf, len);
- err = dsp_msg(tfa, 3 + len, (char *)buffer);
- kmem_cache_free(tfa->cachep, buffer);
- }
- }
-
- if (partial)
- kmem_cache_free(tfa->cachep, partial);
-
- return err;
-}
-
-static enum Tfa98xx_Error tfaContWriteVstepMax2(struct tfa_device *tfa, nxpTfaVolumeStepMax2File_t *vp, int vstep_idx, int vstep_msg_idx)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- struct nxpTfaVolumeStepRegisterInfo *regInfo = NULL;
- struct nxpTfaVolumeStepMessageInfo *msgInfo = NULL, *p_msgInfo = NULL;
- nxpTfaBitfield_t bitF;
- int i, nrMessages, enp = tfa->partial_enable;
-
- if (vstep_idx >= vp->NrOfVsteps) {
- pr_debug("Volumestep %d is not available \n", vstep_idx);
- return Tfa98xx_Error_Bad_Parameter;
- }
-
- if (tfa->p_regInfo == NULL) {
- if (tfa->verbose)
- pr_debug("Inital vstep write\n");
- enp = 0;
- }
-
- regInfo = tfaContGetRegForVstep(vp, vstep_idx);
-
- msgInfo = tfaContGetmsgInfoFromReg(regInfo);
- nrMessages = msgInfo->NrOfMessages;
-
- if (enp) {
- p_msgInfo = tfaContGetmsgInfoFromReg(tfa->p_regInfo);
- if (nrMessages != p_msgInfo->NrOfMessages) {
- pr_debug("Message different - Disable partial update\n");
- enp = 0;
- }
- }
-
- for (i = 0; i < nrMessages; i++) {
- /* Messagetype(3) is Smartstudio Info! Dont send this! */
- if (msgInfo->MessageType == 3) {
- /* MessageLength is in bytes */
- msgInfo = tfaContGetNextmsgInfo(msgInfo);
- if (enp)
- p_msgInfo = tfaContGetNextmsgInfo(p_msgInfo);
- continue;
- }
-
- /* If no vstepMsgIndex is passed on, all message needs to be send */
- if ((vstep_msg_idx >= TFA_MAX_VSTEP_MSG_MARKER) || (vstep_msg_idx == i)) {
- err = tfaContWriteVstepMax2_One(tfa, msgInfo, p_msgInfo, enp);
- if (err != Tfa98xx_Error_Ok) {
- /*
- * Force a full update for the next write
- * As the current status of the DSP is unknown
- */
- tfa->p_regInfo = NULL;
- return err;
- }
- }
-
- msgInfo = tfaContGetNextmsgInfo(msgInfo);
- if (enp)
- p_msgInfo = tfaContGetNextmsgInfo(p_msgInfo);
- }
-
- tfa->p_regInfo = regInfo;
-
- for (i = 0; i < regInfo->NrOfRegisters * 2; i++) {
- /* Byte swap the datasheetname */
- bitF.field = (uint16_t)(regInfo->registerInfo[i] >> 8) | (regInfo->registerInfo[i] << 8);
- i++;
- bitF.value = (uint16_t)regInfo->registerInfo[i] >> 8;
- err = tfaRunWriteBitfield(tfa, bitF);
- if (err != Tfa98xx_Error_Ok)
- return err;
- }
-
- /* Save the current vstep */
- tfa_dev_set_swvstep(tfa, (unsigned short)vstep_idx);
-
- return err;
-}
-
-/*
- * Write DRC message to the dsp
- * If needed modify the cmd-id
- */
-
-enum Tfa98xx_Error tfaContWriteDrcFile(struct tfa_device *tfa, int size, uint8_t data[])
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- uint8_t *msg = NULL;
-
- msg = kmem_cache_alloc(tfa->cachep, GFP_KERNEL);
- if (msg == NULL)
- return Tfa98xx_Error_Fail;
- memcpy(msg, data, size);
-
- if (TFA_GET_BF(tfa, SBSL) == 0) {
- /* Only do this when not set already */
- if (msg[2] != SB_PARAM_SET_MBDRC) {
- msg[2] = SB_PARAM_SET_MBDRC;
-
- if (tfa->verbose) {
- pr_debug("P-ID for SetMBDrc modified!: ");
- pr_debug("Command-ID used: 0x%02x%02x%02x \n",
- msg[0], msg[1], msg[2]);
- }
- }
- }
-
- /* Send cmdId + payload to dsp */
- err = dsp_msg(tfa, size, (const char *)msg);
-
- kmem_cache_free(tfa->cachep, msg);
-
- return err;
-}
-
-
-/*
- * write a parameter file to the device
- * The VstepIndex and VstepMsgIndex are only used to write a specific msg from the vstep file.
- */
-enum Tfa98xx_Error tfaContWriteFile(struct tfa_device *tfa, nxpTfaFileDsc_t *file, int vstep_idx, int vstep_msg_idx)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- nxpTfaHeader_t *hdr = (nxpTfaHeader_t *)file->data;
- nxpTfaHeaderType_t type;
- int size, i;
- char subVerString[8] = { 0 };
- int subversion = 0;
-
- if (tfa->verbose) {
- tfaContShowHeader(hdr);
- }
-
- type = (nxpTfaHeaderType_t)hdr->id;
- if ((type == msgHdr) || ((type == volstepHdr) && (tfa->tfa_family == 2)))
- {
- subVerString[0] = hdr->subversion[0];
- subVerString[1] = hdr->subversion[1];
- subVerString[2] = '\0';
-
- sscanf(subVerString, "%d", &subversion);
-
- if ((subversion > 0) &&
- (((hdr->customer[0]) == 'A') && ((hdr->customer[1]) == 'P') &&
- ((hdr->customer[2]) == 'I') && ((hdr->customer[3]) == 'V')))
- {
- if (tfa->is_probus_device)
- {
- /* Temporary workaround (example: For climax --calibrate scenario for probus devices) */
- err = tfaGetFwApiVersion(tfa, (unsigned char *)&tfa->fw_itf_ver[0]);
- if (err) {
- pr_debug("[%s] cannot get FWAPI error = %d \n", __FUNCTION__, err);
- return err;
- }
- for (i = 0; i<3; i++)
- {
- if (tfa->fw_itf_ver[i] != hdr->customer[i + 4]) //+4 to skip "?PIV" string part in the .msg file.
- {
- ERRORMSG("Error: tfaContWriteFile: Expected FW API version = %d.%d.%d, Msg File version: %d.%d.%d \n",
- tfa->fw_itf_ver[0],
- tfa->fw_itf_ver[1],
- tfa->fw_itf_ver[2],
- hdr->customer[4],
- hdr->customer[5],
- hdr->customer[6]);
- return Tfa98xx_Error_Bad_Parameter;
- }
- }
- }
- else if ((tfa->fw_itf_ver[2] != hdr->customer[4]) || (tfa->fw_itf_ver[1] != hdr->customer[5]) || ((tfa->fw_itf_ver[0] >> 6) & 0x03) != hdr->customer[6])
- {
-
- ERRORMSG("Error: tfaContWriteFile: Expected FW API version = %d.%d.%d, Msg File version: %d.%d.%d \n",
- (tfa->fw_itf_ver[2]) & 0xff,
- (tfa->fw_itf_ver[1]) & 0xff,
- (tfa->fw_itf_ver[0] >> 6) & 0x03,
- hdr->customer[4],
- hdr->customer[5],
- hdr->customer[6]);
- return Tfa98xx_Error_Bad_Parameter;
- }
- }
- }
-
- switch (type) {
- case msgHdr: /* generic DSP message */
- size = hdr->size - sizeof(nxpTfaMsgFile_t);
- err = dsp_msg(tfa, size, (const char *)((nxpTfaMsgFile_t *)hdr)->data);
- break;
- case volstepHdr:
- if (tfa->tfa_family == 2) {
- err = tfaContWriteVstepMax2(tfa, (nxpTfaVolumeStepMax2File_t *)hdr, vstep_idx, vstep_msg_idx);
- }
- else {
- err = tfaContWriteVstep(tfa, (nxpTfaVolumeStep2File_t *)hdr, vstep_idx);
- }
- break;
- case speakerHdr:
- if (tfa->tfa_family == 2) {
- /* Remove header and xml_id */
- size = hdr->size - sizeof(struct nxpTfaSpkHeader) - sizeof(struct nxpTfaFWVer);
-
- err = dsp_msg(tfa, size,
- (const char *)(((nxpTfaSpeakerFile_t *)hdr)->data + (sizeof(struct nxpTfaFWVer))));
- }
- else {
- size = hdr->size - sizeof(nxpTfaSpeakerFile_t);
- err = tfa98xx_dsp_write_speaker_parameters(tfa, size,
- (const unsigned char *)((nxpTfaSpeakerFile_t *)hdr)->data);
- }
- break;
- case presetHdr:
- size = hdr->size - sizeof(nxpTfaPreset_t);
- err = tfa98xx_dsp_write_preset(tfa, size, (const unsigned char *)((nxpTfaPreset_t *)hdr)->data);
- break;
- case equalizerHdr:
- err = tfa_cont_write_filterbank(tfa, ((nxpTfaEqualizerFile_t *)hdr)->filter);
- break;
- case patchHdr:
- size = hdr->size - sizeof(nxpTfaPatch_t); // size is total length
- err = tfa_dsp_patch(tfa, size, (const unsigned char *)((nxpTfaPatch_t *)hdr)->data);
- break;
- case configHdr:
- size = hdr->size - sizeof(nxpTfaConfig_t);
- err = tfa98xx_dsp_write_config(tfa, size, (const unsigned char *)((nxpTfaConfig_t *)hdr)->data);
- break;
- case drcHdr:
- if (hdr->version[0] == NXPTFA_DR3_VERSION) {
- /* Size is total size - hdrsize(36) - xmlversion(3) */
- size = hdr->size - sizeof(nxpTfaDrc2_t);
- err = tfaContWriteDrcFile(tfa, size, ((nxpTfaDrc2_t *)hdr)->data);
- }
- else {
- /*
- * The DRC file is split as:
- * 36 bytes for generic header (customer, application, and type)
- * 127x3 (381) bytes first block contains the device and sample rate
- * independent settings
- * 127x3 (381) bytes block the device and sample rate specific values.
- * The second block can always be recalculated from the first block,
- * if vlsCal and the sample rate are known.
- */
- //size = hdr->size - sizeof(nxpTfaDrc_t);
- size = 381; /* fixed size for first block */
-
- //+381 is done to only send the second part of the drc block
- err = tfa98xx_dsp_write_drc(tfa, size, ((const unsigned char *)((nxpTfaDrc_t *)hdr)->data + 381));
- }
- break;
- case infoHdr:
- /* Ignore */
- break;
- default:
- pr_err("Header is of unknown type: 0x%x\n", type);
- return Tfa98xx_Error_Bad_Parameter;
- }
-
- return err;
-}
-
-/**
- * get the 1st of this dsc type this devicelist
- */
-static nxpTfaDescPtr_t *tfa_cnt_get_dsc(nxpTfaContainer_t *cnt, nxpTfaDescriptorType_t type, int dev_idx)
-{
- nxpTfaDeviceList_t *dev = tfaContDevice(cnt, dev_idx);
- nxpTfaDescPtr_t *_this;
- int i;
-
- if (!dev) {
- return NULL;
- }
- /* process the list until a the type is encountered */
- for (i = 0; i < dev->length; i++) {
- if (dev->list[i].type == (uint32_t)type) {
- _this = (nxpTfaDescPtr_t *)(dev->list[i].offset + (uint8_t *)cnt);
- return _this;
- }
-
- }
-
- return NULL;
-}
-
-/**
- * get the device type from the patch in this devicelist
- * - find the patch file for this devidx
- * - return the devid from the patch or 0 if not found
- */
-int tfa_cnt_get_devid(nxpTfaContainer_t *cnt, int dev_idx)
-{
- nxpTfaPatch_t *patchfile;
- nxpTfaDescPtr_t *patchdsc;
- uint8_t *patchheader;
- unsigned short devid, checkaddress;
- int checkvalue;
-
- patchdsc = tfa_cnt_get_dsc(cnt, dscPatch, dev_idx);
- if (!patchdsc) /* no patch for this device, assume non-i2c */
- return 0;
- patchdsc += 2; /* first the filename dsc and filesize, so skip them */
- patchfile = (nxpTfaPatch_t *)patchdsc;
-
- patchheader = patchfile->data;
-
- checkaddress = (patchheader[1] << 8) + patchheader[2];
- checkvalue =
- (patchheader[3] << 16) + (patchheader[4] << 8) + patchheader[5];
-
- devid = patchheader[0];
-
- if (checkaddress == 0xFFFF && checkvalue != 0xFFFFFF && checkvalue != 0) {
- devid = patchheader[5] << 8 | patchheader[0]; /* full revid */
- }
-
- return devid;
-}
-
-/**
- * get the firmware version from the patch in this devicelist
- */
-int tfa_cnt_get_patch_version(struct tfa_device *tfa)
-{
- nxpTfaPatch_t *patchfile;
- nxpTfaDescPtr_t *patchdsc;
- uint8_t *data;
- int size, version;
-
- if (tfa->cnt == NULL)
- return -1;
-
- patchdsc = tfa_cnt_get_dsc(tfa->cnt, dscPatch, tfa->dev_idx);
- patchdsc += 2; /* first the filename dsc and filesize, so skip them */
- patchfile = (nxpTfaPatch_t *)patchdsc;
-
- size = patchfile->hdr.size - sizeof(nxpTfaPatch_t);
- data = patchfile->data;
-
- version = (data[size - 3] << 16) + (data[size - 2] << 8) + data[size - 1];
-
- return version;
-}
-
-
-/*
- * get the slave for the device if it exists
- */
-enum Tfa98xx_Error tfaContGetSlave(struct tfa_device *tfa, uint8_t *slave_addr)
-{
- nxpTfaDeviceList_t *dev = NULL;
-
- /* Make sure the cnt file is loaded */
- if (tfa->cnt != NULL) {
- dev = tfaContDevice(tfa->cnt, tfa->dev_idx);
- }
-
- if (dev == NULL) {
- /* Check if slave argument is used! */
- if (gslave_address == 0) {
- return Tfa98xx_Error_Bad_Parameter;
- }
- else {
- *slave_addr = gslave_address;
- return Tfa98xx_Error_Ok;
- }
- }
-
- *slave_addr = dev->dev;
- return Tfa98xx_Error_Ok;
-}
-
-/* If no container file is given, we can always have used the slave argument */
-void tfaContSetSlave(uint8_t slave_addr)
-{
- gslave_address = slave_addr;
-}
-
-/*
- * lookup slave and return device index
- */
-int tfa_cont_get_idx(struct tfa_device *tfa)
-{
- nxpTfaDeviceList_t *dev = NULL;
- int i;
-
- for (i = 0; i < tfa->cnt->ndev; i++) {
- dev = tfaContDevice(tfa->cnt, i);
- if (dev->dev == tfa->slave_address)
- break;
-
- }
- if (i == tfa->cnt->ndev)
- return -1;
-
- return i;
-}
-
-/*
- * write a bit field
- */
-enum Tfa98xx_Error tfaRunWriteBitfield(struct tfa_device *tfa, nxpTfaBitfield_t bf)
-{
- enum Tfa98xx_Error error;
- uint16_t value;
- union {
- uint16_t field;
- nxpTfaBfEnum_t Enum;
- } bfUni;
-
- value = bf.value;
- bfUni.field = bf.field;
-#ifdef TFA_DEBUG
- if (tfa->verbose)
- pr_debug("bitfield: %s=0x%x (0x%x[%d..%d]=0x%x)\n", tfaContBfName(bfUni.field, tfa->rev), value,
- bfUni.Enum.address, bfUni.Enum.pos, bfUni.Enum.pos + bfUni.Enum.len, value);
-#endif
- error = tfa_set_bf(tfa, bfUni.field, value);
-
- return error;
-}
-
-/*
- * read a bit field
- */
-enum Tfa98xx_Error tfaRunReadBitfield(struct tfa_device *tfa, nxpTfaBitfield_t *bf)
-{
- enum Tfa98xx_Error error;
- union {
- uint16_t field;
- nxpTfaBfEnum_t Enum;
- } bfUni;
- uint16_t regvalue, msk;
-
- bfUni.field = bf->field;
-
- error = reg_read(tfa, (unsigned char)(bfUni.Enum.address), ®value);
- if (error) return error;
-
- msk = ((1 << (bfUni.Enum.len + 1)) - 1) << bfUni.Enum.pos;
-
- regvalue &= msk;
- bf->value = regvalue >> bfUni.Enum.pos;
-
- return error;
-}
-
-/*
- dsp mem direct write
- */
-static enum Tfa98xx_Error tfaRunWriteDspMem(struct tfa_device *tfa, nxpTfaDspMem_t *cfmem)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- int i;
-
- for (i = 0; i < cfmem->size; i++) {
- if (tfa->verbose)
- pr_debug("dsp mem (%d): 0x%02x=0x%04x\n", cfmem->type, cfmem->address, cfmem->words[i]);
-
- error = mem_write(tfa, cfmem->address++, cfmem->words[i], cfmem->type);
- if (error) return error;
- }
-
- return error;
-}
-
-/*
- * write filter payload to DSP
- * note that the data is in an aligned union for all filter variants
- * the aa data is used but it's the same for all of them
- */
-static enum Tfa98xx_Error tfaRunWriteFilter(struct tfa_device *tfa, nxpTfaContBiquad_t *bq)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- enum Tfa98xx_DMEM dmem;
- uint16_t address;
- uint8_t data[3 * 3 + sizeof(bq->aa.bytes)];
- int i, channel = 0, runs = 1;
- int8_t saved_index = bq->aa.index; /* This is used to set back the index */
-
- /* Channel=1 is primary, Channel=2 is secondary*/
- if (bq->aa.index > 100) {
- bq->aa.index -= 100;
- channel = 2;
- }
- else if (bq->aa.index > 50) {
- bq->aa.index -= 50;
- channel = 1;
- }
- else if ((tfa->rev & 0xff) == 0x88) {
- runs = 2;
- }
-
- if (tfa->verbose) {
- if (channel == 2)
- pr_debug("filter[%d,S]", bq->aa.index);
- else if (channel == 1)
- pr_debug("filter[%d,P]", bq->aa.index);
- else
- pr_debug("filter[%d]", bq->aa.index);
- }
-
- for (i = 0; i < runs; i++) {
- if (runs == 2)
- channel++;
-
- /* get the target address for the filter on this device */
- dmem = tfa98xx_filter_mem(tfa, bq->aa.index, &address, channel);
- if (dmem == Tfa98xx_DMEM_ERR) {
- if (tfa->verbose) {
- pr_debug("Warning: XFilter settings are applied via msg file (ini filter[x] format is skipped).\n");
- }
- /* Dont exit with an error here, We could continue without problems */
- return Tfa98xx_Error_Ok;
- }
-
- /* send a DSP memory message that targets the devices specific memory for the filter
- * msg params: which_mem, start_offset, num_words
- */
- memset(data, 0, 3 * 3);
- data[2] = dmem; /* output[0] = which_mem */
- data[4] = address >> 8; /* output[1] = start_offset */
- data[5] = address & 0xff;
- data[8] = sizeof(bq->aa.bytes) / 3; /*output[2] = num_words */
- memcpy(&data[9], bq->aa.bytes, sizeof(bq->aa.bytes)); /* payload */
-
- if (tfa->tfa_family == 2) {
- error = tfa_dsp_cmd_id_write(tfa, MODULE_FRAMEWORK, FW_PAR_ID_SET_MEMORY, sizeof(data), data);
- }
- else {
- error = tfa_dsp_cmd_id_write(tfa, MODULE_FRAMEWORK, 4 /* param */, sizeof(data), data);
- }
- }
-
-#ifdef TFA_DEBUG
- if (tfa->verbose) {
- if (bq->aa.index == 13) {
- pr_debug("=%d,%.0f,%.2f \n",
- bq->in.type, bq->in.cutOffFreq, bq->in.leakage);
- }
- else if (bq->aa.index >= 10 && bq->aa.index <= 12) {
- pr_debug("=%d,%.0f,%.1f,%.1f \n", bq->aa.type,
- bq->aa.cutOffFreq, bq->aa.rippleDb, bq->aa.rolloff);
- }
- else {
- pr_debug("= unsupported filter index \n");
- }
- }
-#endif
-
- /* Because we can load the same filters multiple times
- * For example: When we switch profile we re-write in operating mode.
- * We then need to remember the index (primary, secondary or both)
- */
- bq->aa.index = saved_index;
-
- return error;
-}
-
-/*
- * write the register based on the input address, value and mask
- * only the part that is masked will be updated
- */
-static enum Tfa98xx_Error tfaRunWriteRegister(struct tfa_device *tfa, nxpTfaRegpatch_t *reg)
-{
- enum Tfa98xx_Error error;
- uint16_t value, newvalue;
-
- if (tfa->verbose)
- pr_debug("register: 0x%02x=0x%04x (msk=0x%04x)\n", reg->address, reg->value, reg->mask);
-
- error = reg_read(tfa, reg->address, &value);
- if (error) return error;
-
- value &= ~reg->mask;
- newvalue = reg->value & reg->mask;
-
- value |= newvalue;
- error = reg_write(tfa, reg->address, value);
-
- return error;
-
-}
-
-// write reg and bitfield items in the devicelist to the target
-enum Tfa98xx_Error tfaContWriteRegsDev(struct tfa_device *tfa)
-{
- nxpTfaDeviceList_t *dev = tfaContDevice(tfa->cnt, tfa->dev_idx);
- nxpTfaBitfield_t *bitF;
- int i;
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
-
- if (!dev) {
- return Tfa98xx_Error_Bad_Parameter;
- }
-
- /* process the list until a patch, file of profile is encountered */
- for (i = 0; i < dev->length; i++) {
- if (dev->list[i].type == dscPatch ||
- dev->list[i].type == dscFile ||
- dev->list[i].type == dscProfile) break;
-
- if (dev->list[i].type == dscBitfield) {
- bitF = (nxpTfaBitfield_t *)(dev->list[i].offset + (uint8_t *)tfa->cnt);
- err = tfaRunWriteBitfield(tfa, *bitF);
- }
- if (dev->list[i].type == dscRegister) {
- err = tfaRunWriteRegister(tfa, (nxpTfaRegpatch_t *)(dev->list[i].offset + (char*)tfa->cnt));
- }
-
- if (err) break;
- }
-
- return err;
-}
-
-// write reg and bitfield items in the profilelist the target
-enum Tfa98xx_Error tfaContWriteRegsProf(struct tfa_device *tfa, int prof_idx)
-{
- nxpTfaProfileList_t *prof = tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx);
- nxpTfaBitfield_t *bitf;
- unsigned int i;
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
-
- if (!prof) {
- return Tfa98xx_Error_Bad_Parameter;
- }
-
- if (tfa->verbose)
- pr_debug("----- profile: %s (%d) -----\n", tfaContGetString(tfa->cnt, &prof->name), prof_idx);
-
- /* process the list until the end of the profile or the default section */
- for (i = 0; i < prof->length; i++) {
- /* We only want to write the values before the default section when we switch profile */
- if (prof->list[i].type == dscDefault)
- break;
-
- if (prof->list[i].type == dscBitfield) {
- bitf = (nxpTfaBitfield_t *)(prof->list[i].offset + (uint8_t *)tfa->cnt);
- err = tfaRunWriteBitfield(tfa, *bitf);
- }
- if (prof->list[i].type == dscRegister) {
- err = tfaRunWriteRegister(tfa, (nxpTfaRegpatch_t *)(prof->list[i].offset + (char*)tfa->cnt));
- }
- if (err) break;
- }
- return err;
-}
-
-// write patchfile in the devicelist to the target
-enum Tfa98xx_Error tfaContWritePatch(struct tfa_device *tfa)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- nxpTfaDeviceList_t *dev = tfaContDevice(tfa->cnt, tfa->dev_idx);
- nxpTfaFileDsc_t *file;
- nxpTfaPatch_t *patchfile;
- int size, i;
-
- if (!dev) {
- return Tfa98xx_Error_Bad_Parameter;
- }
- /* process the list until a patch is encountered */
- for (i = 0; i < dev->length; i++) {
- if (dev->list[i].type == dscPatch) {
- file = (nxpTfaFileDsc_t *)(dev->list[i].offset + (uint8_t *)tfa->cnt);
- patchfile = (nxpTfaPatch_t *)&file->data;
- if (tfa->verbose) tfaContShowHeader(&patchfile->hdr);
- size = patchfile->hdr.size - sizeof(nxpTfaPatch_t); // size is total length
- err = tfa_dsp_patch(tfa, size, (const unsigned char *)patchfile->data);
- if (err) return err;
- }
- }
-
- return Tfa98xx_Error_Ok;
-}
-
-/**
- * Create a buffer which can be used to send to the dsp.
- */
-static void create_dsp_buffer_msg(struct tfa_device *tfa, nxpTfaMsg_t *msg, char *buffer, int *size)
-{
- int i, nr = 0;
-
- (void)tfa;
-
- /* Copy cmdId. Remember that the cmdId is reversed */
- buffer[nr++] = msg->cmdId[2];
- buffer[nr++] = msg->cmdId[1];
- buffer[nr++] = msg->cmdId[0];
-
- /* Copy the data to the buffer */
- for (i = 0; i < msg->msg_size; i++) {
- buffer[nr++] = (uint8_t)((msg->data[i] >> 16) & 0xffff);
- buffer[nr++] = (uint8_t)((msg->data[i] >> 8) & 0xff);
- buffer[nr++] = (uint8_t)(msg->data[i] & 0xff);
- }
-
- *size = nr;
-}
-
-// write all param files in the devicelist to the target
-enum Tfa98xx_Error tfaContWriteFiles(struct tfa_device *tfa)
-{
- nxpTfaDeviceList_t *dev = tfaContDevice(tfa->cnt, tfa->dev_idx);
- nxpTfaFileDsc_t *file;
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- char buffer[(MEMTRACK_MAX_WORDS * 3) + 3] = { 0 }; //every word requires 3 and 3 is the msg
- int i, size = 0;
-
- if (!dev) {
- return Tfa98xx_Error_Bad_Parameter;
- }
- /* process the list and write all files */
- for (i = 0; i < dev->length; i++) {
- if (dev->list[i].type == dscFile) {
- file = (nxpTfaFileDsc_t *)(dev->list[i].offset + (uint8_t *)tfa->cnt);
- if (tfaContWriteFile(tfa, file, 0, TFA_MAX_VSTEP_MSG_MARKER)) {
- return Tfa98xx_Error_Bad_Parameter;
- }
- }
-
- if (dev->list[i].type == dscSetInputSelect ||
- dev->list[i].type == dscSetOutputSelect ||
- dev->list[i].type == dscSetProgramConfig ||
- dev->list[i].type == dscSetLagW ||
- dev->list[i].type == dscSetGains ||
- dev->list[i].type == dscSetvBatFactors ||
- dev->list[i].type == dscSetSensesCal ||
- dev->list[i].type == dscSetSensesDelay ||
- dev->list[i].type == dscSetMBDrc ||
- dev->list[i].type == dscSetFwkUseCase ||
- dev->list[i].type == dscSetVddpConfig) {
- create_dsp_buffer_msg(tfa, (nxpTfaMsg_t *)
- (dev->list[i].offset + (char*)tfa->cnt), buffer, &size);
- if (tfa->verbose) {
- pr_debug("command: %s=0x%02x%02x%02x \n",
- tfaContGetCommandString(dev->list[i].type),
- (unsigned char)buffer[0], (unsigned char)buffer[1], (unsigned char)buffer[2]);
- }
-
- err = dsp_msg(tfa, size, buffer);
- }
-
- if (dev->list[i].type == dscCmd) {
- size = *(uint16_t *)(dev->list[i].offset + (char*)tfa->cnt);
-
- err = dsp_msg(tfa, size, dev->list[i].offset + 2 + (char*)tfa->cnt);
- if (tfa->verbose) {
- const char *cmd_id = dev->list[i].offset + 2 + (char*)tfa->cnt;
- pr_debug("Writing cmd=0x%02x%02x%02x \n", (uint8_t)cmd_id[0], (uint8_t)cmd_id[1], (uint8_t)cmd_id[2]);
- }
- }
- if (err != Tfa98xx_Error_Ok)
- break;
-
- if (dev->list[i].type == dscCfMem) {
- err = tfaRunWriteDspMem(tfa, (nxpTfaDspMem_t *)(dev->list[i].offset + (uint8_t *)tfa->cnt));
- }
-
- if (err != Tfa98xx_Error_Ok)
- break;
- }
-
- return err;
-}
-
-/*
- * write all param files in the profilelist to the target
- * this is used during startup when maybe ACS is set
- */
-enum Tfa98xx_Error tfaContWriteFilesProf(struct tfa_device *tfa, int prof_idx, int vstep_idx)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- nxpTfaProfileList_t *prof = tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx);
- char buffer[(MEMTRACK_MAX_WORDS * 3) + 3] = { 0 }; //every word requires 3 and 3 is the msg
- unsigned int i;
- nxpTfaFileDsc_t *file;
- nxpTfaPatch_t *patchfile;
- int size;
-
- if (!prof) {
- return Tfa98xx_Error_Bad_Parameter;
- }
-
- /* process the list and write all files */
- for (i = 0; i < prof->length; i++) {
- switch (prof->list[i].type) {
- case dscFile:
- file = (nxpTfaFileDsc_t *)(prof->list[i].offset + (uint8_t *)tfa->cnt);
- err = tfaContWriteFile(tfa, file, vstep_idx, TFA_MAX_VSTEP_MSG_MARKER);
- break;
- case dscPatch:
- file = (nxpTfaFileDsc_t *)(prof->list[i].offset + (uint8_t *)tfa->cnt);
- patchfile = (nxpTfaPatch_t *)&file->data;
- if (tfa->verbose) tfaContShowHeader(&patchfile->hdr);
- size = patchfile->hdr.size - sizeof(nxpTfaPatch_t); // size is total length
- err = tfa_dsp_patch(tfa, size, (const unsigned char *)patchfile->data);
- break;
- case dscCfMem:
- err = tfaRunWriteDspMem(tfa, (nxpTfaDspMem_t *)(prof->list[i].offset + (uint8_t *)tfa->cnt));
- break;
- case dscSetInputSelect:
- case dscSetOutputSelect:
- case dscSetProgramConfig:
- case dscSetLagW:
- case dscSetGains:
- case dscSetvBatFactors:
- case dscSetSensesCal:
- case dscSetSensesDelay:
- case dscSetMBDrc:
- case dscSetFwkUseCase:
- case dscSetVddpConfig:
- create_dsp_buffer_msg(tfa, (nxpTfaMsg_t *)
- (prof->list[i].offset + (uint8_t *)tfa->cnt), buffer, &size);
- if (tfa->verbose) {
- pr_debug("command: %s=0x%02x%02x%02x \n",
- tfaContGetCommandString(prof->list[i].type),
- (unsigned char)buffer[0], (unsigned char)buffer[1], (unsigned char)buffer[2]);
- }
-
- err = dsp_msg(tfa, size, buffer);
- break;
- default:
- /* ignore any other type */
- break;
- }
- }
-
- return err;
-}
-
-static enum Tfa98xx_Error tfaContWriteItem(struct tfa_device *tfa, nxpTfaDescPtr_t * dsc)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- nxpTfaRegpatch_t *reg;
- nxpTfaMode_t *cas;
- nxpTfaBitfield_t *bitf;
-
- // When no DSP should only write to HW registers.
- if (tfa->ext_dsp == 0 && !(dsc->type == dscBitfield || dsc->type == dscRegister)) {
- return Tfa98xx_Error_Ok;
- }
-
- switch (dsc->type) {
- case dscDefault:
- case dscDevice: // ignore
- case dscProfile: // profile list
- break;
- case dscRegister: // register patch
- reg = (nxpTfaRegpatch_t *)(dsc->offset + (uint8_t *)tfa->cnt);
- return tfaRunWriteRegister(tfa, reg);
- //pr_debug("$0x%2x=0x%02x,0x%02x\n", reg->address, reg->mask, reg->value);
- break;
- case dscString: // ascii: zero terminated string
- pr_debug(";string: %s\n", tfaContGetString(tfa->cnt, dsc));
- break;
- case dscFile: // filename + file contents
- case dscPatch:
- break;
- case dscMode:
- cas = (nxpTfaMode_t *)(dsc->offset + (uint8_t *)tfa->cnt);
- if (cas->value == Tfa98xx_Mode_RCV)
- tfa98xx_select_mode(tfa, Tfa98xx_Mode_RCV);
- else
- tfa98xx_select_mode(tfa, Tfa98xx_Mode_Normal);
- break;
- case dscCfMem:
- err = tfaRunWriteDspMem(tfa, (nxpTfaDspMem_t *)(dsc->offset + (uint8_t *)tfa->cnt));
- break;
- case dscBitfield:
- bitf = (nxpTfaBitfield_t *)(dsc->offset + (uint8_t *)tfa->cnt);
- return tfaRunWriteBitfield(tfa, *bitf);
- break;
- case dscFilter:
- return tfaRunWriteFilter(tfa, (nxpTfaContBiquad_t *)(dsc->offset + (uint8_t *)tfa->cnt));
- break;
- }
-
- return err;
-}
-
-static unsigned int tfa98xx_sr_from_field(unsigned int field)
-{
- switch (field) {
- case 0:
- return 8000;
- case 1:
- return 11025;
- case 2:
- return 12000;
- case 3:
- return 16000;
- case 4:
- return 22050;
- case 5:
- return 24000;
- case 6:
- return 32000;
- case 7:
- return 44100;
- case 8:
- return 48000;
- default:
- return 0;
- }
-}
-
-enum Tfa98xx_Error tfa_write_filters(struct tfa_device *tfa, int prof_idx)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- nxpTfaProfileList_t *prof = tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx);
- unsigned int i;
- int status;
-
- if (!prof) {
- return Tfa98xx_Error_Bad_Parameter;
- }
-
- if (tfa->verbose) {
- pr_debug("----- profile: %s (%d) -----\n", tfaContGetString(tfa->cnt, &prof->name), prof_idx);
- pr_debug("Waiting for CLKS... \n");
- }
-
- for (i = 10; i > 0; i--) {
- err = tfa98xx_dsp_system_stable(tfa, &status);
- if (status)
- break;
- else
- msleep_interruptible(10);
- }
-
- if (i == 0) {
- if (tfa->verbose)
- pr_err("Unable to write filters, CLKS=0 \n");
-
- return Tfa98xx_Error_StateTimedOut;
- }
-
- /* process the list until the end of the profile or the default section */
- for (i = 0; i < prof->length; i++) {
- if (prof->list[i].type == dscFilter) {
- if (tfaContWriteItem(tfa, &prof->list[i]) != Tfa98xx_Error_Ok)
- return Tfa98xx_Error_Bad_Parameter;
- }
- }
-
- return err;
-}
-
-unsigned int tfa98xx_get_profile_sr(struct tfa_device *tfa, unsigned int prof_idx)
-{
- nxpTfaBitfield_t *bitf;
- unsigned int i;
- nxpTfaDeviceList_t *dev;
- nxpTfaProfileList_t *prof;
- int fs_profile = -1;
-
- dev = tfaContDevice(tfa->cnt, tfa->dev_idx);
- if (!dev)
- return 0;
-
- prof = tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx);
- if (!prof)
- return 0;
-
- /* Check profile fields first */
- for (i = 0; i < prof->length; i++) {
- if (prof->list[i].type == dscDefault)
- break;
-
- /* check for profile settingd (AUDFS) */
- if (prof->list[i].type == dscBitfield) {
- bitf = (nxpTfaBitfield_t *)(prof->list[i].offset + (uint8_t *)tfa->cnt);
- if (bitf->field == TFA_FAM(tfa, AUDFS)) {
- fs_profile = bitf->value;
- break;
- }
- }
- }
-
- if (tfa->verbose)
- pr_debug("%s - profile fs: 0x%x = %dHz (%d - %d)\n",
- __FUNCTION__, fs_profile,
- tfa98xx_sr_from_field(fs_profile),
- tfa->dev_idx, prof_idx);
-
- if (fs_profile != -1)
- return tfa98xx_sr_from_field(fs_profile);
-
- /* Check for container default setting */
- /* process the list until a patch, file of profile is encountered */
- for (i = 0; i < dev->length; i++) {
- if (dev->list[i].type == dscPatch ||
- dev->list[i].type == dscFile ||
- dev->list[i].type == dscProfile)
- break;
-
- if (dev->list[i].type == dscBitfield) {
- bitf = (nxpTfaBitfield_t *)(dev->list[i].offset + (uint8_t *)tfa->cnt);
- if (bitf->field == TFA_FAM(tfa, AUDFS)) {
- fs_profile = bitf->value;
- break;
- }
- }
- /* Ignore register case */
- }
-
- if (tfa->verbose)
- pr_debug("%s - default fs: 0x%x = %dHz (%d - %d)\n",
- __FUNCTION__, fs_profile,
- tfa98xx_sr_from_field(fs_profile),
- tfa->dev_idx, prof_idx);
-
- if (fs_profile != -1)
- return tfa98xx_sr_from_field(fs_profile);
-
- return 48000; /* default of HW */
-}
-
-static enum Tfa98xx_Error get_sample_rate_info(struct tfa_device *tfa, nxpTfaProfileList_t *prof, nxpTfaProfileList_t *previous_prof, int fs_previous_profile)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- nxpTfaBitfield_t *bitf;
- unsigned int i;
- int fs_default_profile = 8; /* default is 48kHz */
- int fs_next_profile = 8; /* default is 48kHz */
-
-
- /* ---------- default settings previous profile ---------- */
- for (i = 0; i < previous_prof->length; i++) {
- /* Search for the default section */
- if (i == 0) {
- while (previous_prof->list[i].type != dscDefault && i < previous_prof->length) {
- i++;
- }
- i++;
- }
-
- /* Only if we found the default section search for AUDFS */
- if (i < previous_prof->length) {
- if (previous_prof->list[i].type == dscBitfield) {
- bitf = (nxpTfaBitfield_t *)(previous_prof->list[i].offset + (uint8_t *)tfa->cnt);
- if (bitf->field == TFA_FAM(tfa, AUDFS)) {
- fs_default_profile = bitf->value;
- break;
- }
- }
- }
- }
-
- /* ---------- settings next profile ---------- */
- for (i = 0; i < prof->length; i++) {
- /* We only want to write the values before the default section */
- if (prof->list[i].type == dscDefault)
- break;
- /* search for AUDFS */
- if (prof->list[i].type == dscBitfield) {
- bitf = (nxpTfaBitfield_t *)(prof->list[i].offset + (uint8_t *)tfa->cnt);
- if (bitf->field == TFA_FAM(tfa, AUDFS)) {
- fs_next_profile = bitf->value;
- break;
- }
- }
- }
-
- /* Enable if needed for debugging!
- if (tfa->verbose) {
- pr_debug("sample rate from the previous profile: %d \n", fs_previous_profile);
- pr_debug("sample rate in the default section: %d \n", fs_default_profile);
- pr_debug("sample rate for the next profile: %d \n", fs_next_profile);
- }
- */
-
- if (fs_next_profile != fs_default_profile) {
- if (tfa->verbose)
- pr_debug("Writing delay tables for AUDFS=%d \n", fs_next_profile);
-
- /* If the AUDFS from the next profile is not the same as
- * the AUDFS from the default we need to write new delay tables
- */
- err = tfa98xx_dsp_write_tables(tfa, fs_next_profile);
- }
- else if (fs_default_profile != fs_previous_profile) {
- if (tfa->verbose)
- pr_debug("Writing delay tables for AUDFS=%d \n", fs_default_profile);
-
- /* But if we do not have a new AUDFS in the next profile and
- * the AUDFS from the default profile is not the same as the AUDFS
- * from the previous profile we also need to write new delay tables
- */
- err = tfa98xx_dsp_write_tables(tfa, fs_default_profile);
- }
-
- return err;
-}
-
-/*
- * process all items in the profilelist
- * NOTE an error return during processing will leave the device muted
- *
- */
-enum Tfa98xx_Error tfaContWriteProfile(struct tfa_device *tfa, int prof_idx, int vstep_idx)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- nxpTfaProfileList_t *prof = tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx);
- nxpTfaProfileList_t *previous_prof = tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, tfa_dev_get_swprof(tfa));
- char buffer[(MEMTRACK_MAX_WORDS * 4) + 4] = { 0 }; //every word requires 3 or 4 bytes, and 3 or 4 is the msg
- unsigned int i, k = 0, j = 0, tries = 0;
- nxpTfaFileDsc_t *file;
- int size = 0, ready, fs_previous_profile = 8; /* default fs is 48kHz*/
-
- if (!prof || !previous_prof) {
- pr_err("Error trying to get the (previous) swprofile \n");
- return Tfa98xx_Error_Bad_Parameter;
- }
-
- if (tfa->verbose) {
- tfa98xx_trace_printk("device:%s profile:%s vstep:%d\n", tfaContDeviceName(tfa->cnt, tfa->dev_idx),
- tfaContProfileName(tfa->cnt, tfa->dev_idx, prof_idx), vstep_idx);
- }
-
- /* We only make a power cycle when the profiles are not in the same group */
- if (prof->group == previous_prof->group && prof->group != 0) {
- if (tfa->verbose) {
- pr_debug("The new profile (%s) is in the same group as the current profile (%s) \n",
- tfaContGetString(tfa->cnt, &prof->name), tfaContGetString(tfa->cnt, &previous_prof->name));
- }
- }
- else {
- /* mute */
- err = tfaRunMute(tfa);
- if (err) return err;
-
- /* Get current sample rate before we start switching */
- fs_previous_profile = TFA_GET_BF(tfa, AUDFS);
-
- /* clear SBSL to make sure we stay in initCF state */
- if (tfa->tfa_family == 2) {
- TFA_SET_BF_VOLATILE(tfa, SBSL, 0);
- }
-
- /* When we switch profile we first power down the subsystem
- * This should only be done when we are in operating mode
- */
- if (((tfa->tfa_family == 2) && (TFA_GET_BF(tfa, MANSTATE) >= 6)) || (tfa->tfa_family != 2)) {
- err = tfa98xx_powerdown(tfa, 1);
- if (err) return err;
-
- /* Wait until we are in PLL powerdown */
- do {
- err = tfa98xx_dsp_system_stable(tfa, &ready);
- if (!ready)
- break;
- else
- msleep_interruptible(10); /* wait 10ms to avoid busload */
- tries++;
- } while (tries <= 100);
-
- if (tries > 100) {
- pr_debug("Wait for PLL powerdown timed out!\n");
- return Tfa98xx_Error_StateTimedOut;
- }
- }
- else {
- pr_debug("No need to go to powerdown now \n");
- }
- }
-
- /* set all bitfield settings */
- /* First set all default settings */
- if (tfa->verbose) {
- pr_debug("---------- default settings profile: %s (%d) ---------- \n",
- tfaContGetString(tfa->cnt, &previous_prof->name), tfa_dev_get_swprof(tfa));
- }
-
- err = show_current_state(tfa);
-
- /* Loop profile length */
- for (i = 0; i < previous_prof->length; i++) {
- /* Search for the default section */
- if (i == 0) {
- while (previous_prof->list[i].type != dscDefault && i < previous_prof->length) {
- i++;
- }
- i++;
- }
-
- /* Only if we found the default section try writing the items */
- if (i < previous_prof->length) {
- if (tfaContWriteItem(tfa, &previous_prof->list[i]) != Tfa98xx_Error_Ok)
- return Tfa98xx_Error_Bad_Parameter;
- }
- }
-
- if (tfa->verbose)
- pr_debug("---------- new settings profile: %s (%d) ---------- \n",
- tfaContGetString(tfa->cnt, &prof->name), prof_idx);
-
- /* set new settings */
- for (i = 0; i < prof->length; i++) {
- /* Remember where we currently are with writing items*/
- j = i;
-
- /* We only want to write the values before the default section when we switch profile */
- /* process and write all non-file items */
- switch (prof->list[i].type) {
- case dscFile:
- case dscPatch:
- case dscSetInputSelect:
- case dscSetOutputSelect:
- case dscSetProgramConfig:
- case dscSetLagW:
- case dscSetGains:
- case dscSetvBatFactors:
- case dscSetSensesCal:
- case dscSetSensesDelay:
- case dscSetMBDrc:
- case dscSetFwkUseCase:
- case dscSetVddpConfig:
- case dscCmd:
- case dscFilter:
- case dscDefault:
- /* When one of these files are found, we exit */
- i = prof->length;
- break;
- default:
- err = tfaContWriteItem(tfa, &prof->list[i]);
- if (err != Tfa98xx_Error_Ok)
- return Tfa98xx_Error_Bad_Parameter;
- break;
- }
- }
-
- if (prof->group != previous_prof->group || prof->group == 0) {
- if (tfa->tfa_family == 2)
- TFA_SET_BF_VOLATILE(tfa, MANSCONF, 1);
-
- /* Leave powerdown state */
- err = tfa_cf_powerup(tfa);
- if (err) return err;
-
- err = show_current_state(tfa);
-
- if (tfa->tfa_family == 2) {
- /* Reset SBSL to 0 (workaround of enbl_powerswitch=0) */
- TFA_SET_BF_VOLATILE(tfa, SBSL, 0);
- /* Sending commands to DSP we need to make sure RST is 0 (otherwise we get no response)*/
- TFA_SET_BF(tfa, RST, 0);
- }
- }
-
- /* Check if there are sample rate changes */
- err = get_sample_rate_info(tfa, prof, previous_prof, fs_previous_profile);
- if (err) return err;
-
-
- /* Write files from previous profile (default section)
- * Should only be used for the patch&trap patch (file)
- */
- if (tfa->ext_dsp != 0) {
- if (tfa->tfa_family == 2) {
- for (i = 0; i < previous_prof->length; i++) {
- /* Search for the default section */
- if (i == 0) {
- while (previous_prof->list[i].type != dscDefault && i < previous_prof->length) {
- i++;
- }
- i++;
- }
-
- /* Only if we found the default section try writing the file */
- if (i < previous_prof->length) {
- if (previous_prof->list[i].type == dscFile || previous_prof->list[i].type == dscPatch) {
- /* Only write this once */
- if (tfa->verbose && k == 0) {
- pr_debug("---------- files default profile: %s (%d) ---------- \n",
- tfaContGetString(tfa->cnt, &previous_prof->name), prof_idx);
- k++;
- }
- file = (nxpTfaFileDsc_t *)(previous_prof->list[i].offset + (uint8_t *)tfa->cnt);
- err = tfaContWriteFile(tfa, file, vstep_idx, TFA_MAX_VSTEP_MSG_MARKER);
- }
- }
- }
- }
-
- if (tfa->verbose) {
- pr_debug("---------- files new profile: %s (%d) ---------- \n",
- tfaContGetString(tfa->cnt, &prof->name), prof_idx);
- }
- }
-
- /* write everything until end or the default section starts
- * Start where we currenly left */
- for (i = j; i < prof->length; i++) {
- /* We only want to write the values before the default section when we switch profile */
-
- if (prof->list[i].type == dscDefault) {
- break;
- }
-
- switch (prof->list[i].type) {
- case dscFile:
- case dscPatch:
- /* For tiberius stereo 1 device does not have a dsp! */
- if (tfa->ext_dsp != 0) {
- file = (nxpTfaFileDsc_t *)(prof->list[i].offset + (uint8_t *)tfa->cnt);
- err = tfaContWriteFile(tfa, file, vstep_idx, TFA_MAX_VSTEP_MSG_MARKER);
- }
- break;
- case dscSetInputSelect:
- case dscSetOutputSelect:
- case dscSetProgramConfig:
- case dscSetLagW:
- case dscSetGains:
- case dscSetvBatFactors:
- case dscSetSensesCal:
- case dscSetSensesDelay:
- case dscSetMBDrc:
- case dscSetFwkUseCase:
- case dscSetVddpConfig:
- /* For tiberius stereo 1 device does not have a dsp! */
- if (tfa->ext_dsp != 0) {
- create_dsp_buffer_msg(tfa, (nxpTfaMsg_t *)
- (prof->list[i].offset + (char*)tfa->cnt), buffer, &size);
- err = dsp_msg(tfa, size, buffer);
-
- if (tfa->verbose) {
- pr_debug("command: %s=0x%02x%02x%02x \n",
- tfaContGetCommandString(prof->list[i].type),
- (unsigned char)buffer[0], (unsigned char)buffer[1], (unsigned char)buffer[2]);
- }
- }
- break;
- case dscCmd:
- /* For tiberius stereo 1 device does not have a dsp! */
- if (tfa->ext_dsp != 0) {
- size = *(uint16_t *)(prof->list[i].offset + (char*)tfa->cnt);
- err = dsp_msg(tfa, size, prof->list[i].offset + 2 + (char*)tfa->cnt);
- if (tfa->verbose) {
- const char *cmd_id = prof->list[i].offset + 2 + (char*)tfa->cnt;
- pr_debug("Writing cmd=0x%02x%02x%02x \n", (uint8_t)cmd_id[0], (uint8_t)cmd_id[1], (uint8_t)cmd_id[2]);
- }
- }
- break;
- default:
- /* This allows us to write bitfield, registers or xmem after files */
- if (tfaContWriteItem(tfa, &prof->list[i]) != Tfa98xx_Error_Ok) {
- return Tfa98xx_Error_Bad_Parameter;
- }
- break;
- }
-
- if (err != Tfa98xx_Error_Ok) {
- return err;
- }
- }
-
- if ((prof->group != previous_prof->group || prof->group == 0) && (tfa->tfa_family == 2)) {
- if (TFA_GET_BF(tfa, REFCKSEL) == 0) {
- /* set SBSL to go to operation mode */
- TFA_SET_BF_VOLATILE(tfa, SBSL, 1);
- }
- }
-
- return err;
-}
-
-/*
- * process only vstep in the profilelist
- *
- */
-enum Tfa98xx_Error tfaContWriteFilesVstep(struct tfa_device *tfa, int prof_idx, int vstep_idx)
-{
- nxpTfaProfileList_t *prof = tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx);
- unsigned int i;
- nxpTfaFileDsc_t *file;
- nxpTfaHeader_t *hdr;
- nxpTfaHeaderType_t type;
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
-
- if (!prof)
- return Tfa98xx_Error_Bad_Parameter;
-
- if (tfa->verbose)
- tfa98xx_trace_printk("device:%s profile:%s vstep:%d\n", tfaContDeviceName(tfa->cnt, tfa->dev_idx),
- tfaContProfileName(tfa->cnt, tfa->dev_idx, prof_idx), vstep_idx);
-
- /* write vstep file only! */
- for (i = 0; i < prof->length; i++) {
- if (prof->list[i].type == dscFile) {
- file = (nxpTfaFileDsc_t *)(prof->list[i].offset + (uint8_t *)tfa->cnt);
- hdr = (nxpTfaHeader_t *)file->data;
- type = (nxpTfaHeaderType_t)hdr->id;
-
- switch (type) {
- case volstepHdr:
- if (tfaContWriteFile(tfa, file, vstep_idx, TFA_MAX_VSTEP_MSG_MARKER))
- return Tfa98xx_Error_Bad_Parameter;
- break;
- default:
- break;
- }
- }
- }
-
- return err;
-}
-
-char *tfaContGetString(nxpTfaContainer_t *cnt, nxpTfaDescPtr_t *dsc)
-{
- if (dsc->type != dscString)
- return "Undefined string";
-
- return dsc->offset + (char*)cnt;
-}
-
-char *tfaContGetCommandString(uint32_t type)
-{
- if (type == dscSetInputSelect)
- return "SetInputSelector";
- else if (type == dscSetOutputSelect)
- return "SetOutputSelector";
- else if (type == dscSetProgramConfig)
- return "SetProgramConfig";
- else if (type == dscSetLagW)
- return "SetLagW";
- else if (type == dscSetGains)
- return "SetGains";
- else if (type == dscSetvBatFactors)
- return "SetvBatFactors";
- else if (type == dscSetSensesCal)
- return "SetSensesCal";
- else if (type == dscSetSensesDelay)
- return "SetSensesDelay";
- else if (type == dscSetMBDrc)
- return "SetMBDrc";
- else if (type == dscSetFwkUseCase)
- return "SetFwkUseCase";
- else if (type == dscSetVddpConfig)
- return "SetVddpConfig";
- else if (type == dscFilter)
- return "filter";
- else
- return "Undefined string";
-}
-
-/*
- * Get the name of the device at a certain index in the container file
- * return device name
- */
-char *tfaContDeviceName(nxpTfaContainer_t *cnt, int dev_idx)
-{
- nxpTfaDeviceList_t *dev;
-
- dev = tfaContDevice(cnt, dev_idx);
- if (dev == NULL)
- return "!ERROR!";
-
- return tfaContGetString(cnt, &dev->name);
-}
-
-/*
- * Get the application name from the container file application field
- * note that the input stringbuffer should be sizeof(application field)+1
- *
- */
-int tfa_cnt_get_app_name(struct tfa_device *tfa, char *name)
-{
- unsigned int i;
- int len = 0;
-
- for (i = 0; i < sizeof(tfa->cnt->application); i++) {
- if (isalnum(tfa->cnt->application[i])) /* copy char if valid */
- name[len++] = tfa->cnt->application[i];
- if (tfa->cnt->application[i] == '\0')
- break;
- }
- name[len++] = '\0';
-
- return len;
-}
-
-/*
- * Get profile index of the calibration profile.
- * Returns: (profile index) if found, (-2) if no
- * calibration profile is found or (-1) on error
- */
-int tfaContGetCalProfile(struct tfa_device *tfa)
-{
- int prof, cal_idx = -2;
-
- if ((tfa->dev_idx < 0) || (tfa->dev_idx >= tfa->cnt->ndev))
- return -1;
-
- /* search for the calibration profile in the list of profiles */
- for (prof = 0; prof < tfa->cnt->nprof; prof++) {
- if (strstr(tfaContProfileName(tfa->cnt, tfa->dev_idx, prof), ".cal") != NULL) {
- cal_idx = prof;
- pr_debug("Using calibration profile: '%s'\n", tfaContProfileName(tfa->cnt, tfa->dev_idx, prof));
- break;
- }
- }
-
- return cal_idx;
-}
-
-/**
- * Is the profile a tap profile
- */
-int tfaContIsTapProfile(struct tfa_device *tfa, int prof_idx)
-{
- if ((tfa->dev_idx < 0) || (tfa->dev_idx >= tfa->cnt->ndev))
- return -1;
-
- /* Check if next profile is tap profile */
- if (strstr(tfaContProfileName(tfa->cnt, tfa->dev_idx, prof_idx), ".tap") != NULL) {
- pr_debug("Using Tap profile: '%s'\n", tfaContProfileName(tfa->cnt, tfa->dev_idx, prof_idx));
- return 1;
- }
-
- return 0;
-}
-
-/*
- * Get the name of the profile at certain index for a device in the container file
- * return profile name
- */
-char *tfaContProfileName(nxpTfaContainer_t *cnt, int dev_idx, int prof_idx)
-{
- nxpTfaProfileList_t *prof = NULL;
-
- /* the Nth profiles for this device */
- prof = tfaContGetDevProfList(cnt, dev_idx, prof_idx);
-
- /* If the index is out of bound */
- if (prof == NULL)
- return "NONE";
-
- return tfaContGetString(cnt, &prof->name);
-}
-
-/*
- * return 1st profile list
- */
-nxpTfaProfileList_t *tfaContGet1stProfList(nxpTfaContainer_t * cont)
-{
- nxpTfaProfileList_t *prof;
- uint8_t *b = (uint8_t *)cont;
-
- int maxdev = 0;
- nxpTfaDeviceList_t *dev;
-
- // get nr of devlists
- maxdev = cont->ndev;
- // get last devlist
- dev = tfaContGetDevList(cont, maxdev - 1);
- if (dev == NULL)
- return NULL;
- // the 1st profile starts after the last device list
- b = (uint8_t *)dev + sizeof(nxpTfaDeviceList_t) + dev->length * (sizeof(nxpTfaDescPtr_t));
- prof = (nxpTfaProfileList_t *)b;
- return prof;
-}
-
-/*
- * return 1st livedata list
- */
-nxpTfaLiveDataList_t *tfaContGet1stLiveDataList(nxpTfaContainer_t * cont)
-{
- nxpTfaLiveDataList_t *ldata;
- nxpTfaProfileList_t *prof;
- nxpTfaDeviceList_t *dev;
- uint8_t *b = (uint8_t *)cont;
- int maxdev, maxprof;
-
- // get nr of devlists+1
- maxdev = cont->ndev;
- // get nr of proflists
- maxprof = cont->nprof;
-
- // get last devlist
- dev = tfaContGetDevList(cont, maxdev - 1);
- // the 1st livedata starts after the last device list
- b = (uint8_t *)dev + sizeof(nxpTfaDeviceList_t) +
- dev->length * (sizeof(nxpTfaDescPtr_t));
-
- while (maxprof != 0) {
- // get last proflist
- prof = (nxpTfaProfileList_t *)b;
- b += sizeof(nxpTfaProfileList_t) +
- ((prof->length - 1) * (sizeof(nxpTfaDescPtr_t)));
- maxprof--;
- }
-
- /* Else the marker falls off */
- b += 4; //bytes
-
- ldata = (nxpTfaLiveDataList_t *)b;
- return ldata;
-}
-
-/*
- * return the device list pointer
- */
-nxpTfaDeviceList_t *tfaContDevice(nxpTfaContainer_t *cnt, int dev_idx)
-{
- return tfaContGetDevList(cnt, dev_idx);
-}
-
-/*
- * return the next profile:
- * - assume that all profiles are adjacent
- * - calculate the total length of the input
- * - the input profile + its length is the next profile
- */
-nxpTfaProfileList_t* tfaContNextProfile(nxpTfaProfileList_t* prof) {
- uint8_t *this, *next; /* byte pointers for byte pointer arithmetic */
- nxpTfaProfileList_t* nextprof;
- int listlength; /* total length of list in bytes */
-
- if (prof == NULL)
- return NULL;
-
- if (prof->ID != TFA_PROFID)
- return NULL; /* invalid input */
-
- this = (uint8_t *)prof;
- /* nr of items in the list, length includes name dsc so - 1*/
- listlength = (prof->length - 1) * sizeof(nxpTfaDescPtr_t);
- /* the sizeof(nxpTfaProfileList_t) includes the list[0] length */
- next = this + listlength + sizeof(nxpTfaProfileList_t);// - sizeof(nxpTfaDescPtr_t);
- nextprof = (nxpTfaProfileList_t *)next;
-
- if (nextprof->ID != TFA_PROFID)
- return NULL;
-
- return nextprof;
-}
-
-/*
- * return the next livedata
- */
-nxpTfaLiveDataList_t* tfaContNextLiveData(nxpTfaLiveDataList_t* livedata) {
- nxpTfaLiveDataList_t* nextlivedata = (nxpTfaLiveDataList_t *)((char*)livedata + (livedata->length * 4) +
- sizeof(nxpTfaLiveDataList_t) - 4);
-
- if (nextlivedata->ID == TFA_LIVEDATAID)
- return nextlivedata;
-
- return NULL;
-}
-
-/*
- * check CRC for container
- * CRC is calculated over the bytes following the CRC field
- *
- * return non zero value on error
- */
-int tfaContCrcCheckContainer(nxpTfaContainer_t *cont)
-{
- uint8_t *base;
- size_t size;
- uint32_t crc;
-
- base = (uint8_t *)&cont->CRC + 4; // ptr to bytes following the CRC field
- size = (size_t)(cont->size - (base - (uint8_t *)cont)); // nr of bytes following the CRC field
- crc = ~crc32_le(~0u, base, size);
-
- return crc != cont->CRC;
-}
-
-static void get_all_features_from_cnt(struct tfa_device *tfa, int *hw_feature_register, int sw_feature_register[2])
-{
- nxpTfaFeatures_t *features;
- int i;
-
- nxpTfaDeviceList_t *dev = tfaContDevice(tfa->cnt, tfa->dev_idx);
-
- /* Init values in case no keyword is defined in cnt file: */
- *hw_feature_register = -1;
- sw_feature_register[0] = -1;
- sw_feature_register[1] = -1;
-
- if (dev == NULL)
- return;
-
- // process the device list
- for (i = 0; i < dev->length; i++) {
- if (dev->list[i].type == dscFeatures) {
- features = (nxpTfaFeatures_t *)(dev->list[i].offset + (uint8_t *)tfa->cnt);
- *hw_feature_register = features->value[0];
- sw_feature_register[0] = features->value[1];
- sw_feature_register[1] = features->value[2];
- break;
- }
- }
-}
-
-/* wrapper function */
-void get_hw_features_from_cnt(struct tfa_device *tfa, int *hw_feature_register)
-{
- int sw_feature_register[2];
- get_all_features_from_cnt(tfa, hw_feature_register, sw_feature_register);
-}
-
-/* wrapper function */
-void get_sw_features_from_cnt(struct tfa_device *tfa, int sw_feature_register[2])
-{
- int hw_feature_register;
- get_all_features_from_cnt(tfa, &hw_feature_register, sw_feature_register);
-}
-
-enum Tfa98xx_Error tfa98xx_factory_trimmer(struct tfa_device *tfa)
-{
- return (tfa->dev_ops.factory_trimmer)(tfa);
-}
-
-enum Tfa98xx_Error tfa_set_filters(struct tfa_device *tfa, int prof_idx)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- nxpTfaProfileList_t *prof = tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx);
- unsigned int i;
-
- if (!prof)
- return Tfa98xx_Error_Bad_Parameter;
-
- /* If we are in powerdown there is no need to set filters */
- if (TFA_GET_BF(tfa, PWDN) == 1)
- return Tfa98xx_Error_Ok;
-
- /* loop the profile to find filter settings */
- for (i = 0; i < prof->length; i++) {
- /* We only want to write the values before the default section */
- if (prof->list[i].type == dscDefault)
- break;
-
- /* write all filter settings */
- if (prof->list[i].type == dscFilter) {
- if (tfaContWriteItem(tfa, &prof->list[i]) != Tfa98xx_Error_Ok)
- return err;
- }
- }
-
- return err;
-}
-
-int tfa_tib_dsp_msgmulti(struct tfa_device *tfa, int length, const char *buffer)
-{
- uint8_t *buf = (uint8_t *)buffer;
- static uint8_t *blob = NULL, *blobptr; /* TODO: not multi-thread safe */
- static int total = 0; /* TODO: not multi-thread safe */
- int post_len = 0;
-
- /* checks for 24b_BE or 32_LE */
- int len_word_in_bytes = (tfa->convert_dsp32) ? 4 : 3;
- /* TODO: get rid of these magic constants max size should depend on the tfa device type */
- int tfadsp_max_msg_size = (tfa->convert_dsp32) ? 5336 : 4000;
-
- /* No data found*/
- if (length == -1 && blob == NULL) {
- return -1;
- }
-
- if (length == -1) {
- int i;
- /* set last length field to zero */
- for (i = total; i < (total + len_word_in_bytes); i++) {
- blob[i] = 0;
- }
- total += len_word_in_bytes;
- memcpy(buf, blob, total);
-
- kfree(blob);
- blob = NULL; /* Set to NULL pointer, otherwise no new malloc is done! */
- return total;
- }
-
- if (blob == NULL) {
- if (tfa->verbose)
- pr_debug("%s, Creating the multi-message \n\n", __FUNCTION__);
-
- blob = kmalloc(tfadsp_max_msg_size, GFP_KERNEL);
- /* add command ID for multi-msg = 0x008015 */
- if (tfa->convert_dsp32) {
- blob[0] = 0x15;
- blob[1] = 0x80;
- blob[2] = 0x0;
- blob[3] = 0x0;
- }
- else {
- blob[0] = 0x0;
- blob[1] = 0x80;
- blob[2] = 0x15;
- }
- blobptr = blob;
- blobptr += len_word_in_bytes;
- total = len_word_in_bytes;
- }
-
- if (tfa->verbose) {
- pr_debug("%s, id:0x%02x%02x%02x, length:%d \n", __FUNCTION__, buf[0], buf[1], buf[2], length);
- }
-
- /* check total message size after concatination */
- post_len = total + length + (2 * len_word_in_bytes);
- if (post_len > tfadsp_max_msg_size) {
- //pr_debug("New multi-message too large! (%d >= %d (max.)), current length: %d\n", post_len, tfadsp_max_msg_size, total);
- return Tfa98xx_Error_Buffer_too_small;
- }
-
- /* add length field (length in words) to the multi message */
- if (tfa->convert_dsp32) {
- *blobptr++ = (uint8_t)((length / len_word_in_bytes) & 0xff); /* lsb */
- *blobptr++ = (uint8_t)(((length / len_word_in_bytes) & 0xff00) >> 8); /* msb */
- *blobptr++ = 0x0;
- *blobptr++ = 0x0;
- }
- else {
- *blobptr++ = 0x0;
- *blobptr++ = (uint8_t)(((length / len_word_in_bytes) & 0xff00) >> 8); /* msb */
- *blobptr++ = (uint8_t)((length / len_word_in_bytes) & 0xff); /* lsb */
- }
- memcpy(blobptr, buf, length);
- blobptr += length;
- total += (length + len_word_in_bytes);
-
- /* SetRe25 message is always the last message of the multi-msg */
- if (tfa->convert_dsp32) {
- if (buf[1] == 0x81 && buf[0] == SB_PARAM_SET_RE25C) {
- return 1; /* 1 means last message is done! */
- }
- }
- else {
- if (buf[1] == 0x81 && buf[2] == SB_PARAM_SET_RE25C) {
- return 1; /* 1 means last message is done! */
- }
- }
-
- return 0;
-}
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include "dbgprint.h"
+#include "tfa_container.h"
+#include "tfa.h"
+#include "tfa98xx_tfafieldnames.h"
+#include "tfa_internal.h"
+
+ /* defines */
+#define MODULE_BIQUADFILTERBANK 2
+#define BIQUAD_COEFF_SIZE 6
+#define ERR -1
+
+/* module globals */
+/* This is used to SET the slave with the --slave option */
+static uint8_t gslave_address;
+
+static int float_to_int(uint32_t x)
+{
+ unsigned int e = (0x7F + 31) - ((*(unsigned int *)&x & 0x7F800000) >> 23);
+ unsigned int m = 0x80000000 | (*(unsigned int *)&x << 8);
+
+ return -(int)((m >> e) & -(e < 32));
+}
+
+/*
+ * check the container file
+ */
+enum tfa_error tfa_load_cnt(void *cnt, int length)
+{
+ nxpTfaContainer_t *cntbuf = (nxpTfaContainer_t *)cnt;
+
+ if (length > TFA_MAX_CNT_LENGTH) {
+ pr_err("incorrect length\n");
+ return tfa_error_container;
+ }
+
+ if (HDR(cntbuf->id[0], cntbuf->id[1]) == 0) {
+ pr_err("header is 0\n");
+ return tfa_error_container;
+ }
+
+ if ((HDR(cntbuf->id[0], cntbuf->id[1])) != paramsHdr) {
+ pr_err("wrong header type: 0x%02x 0x%02x\n",
+ cntbuf->id[0], cntbuf->id[1]);
+ return tfa_error_container;
+ }
+
+ if (cntbuf->size == 0) {
+ pr_err("data size is 0\n");
+ return tfa_error_container;
+ }
+
+ /* check CRC */
+ if (tfaContCrcCheckContainer(cntbuf)) {
+ pr_err("CRC error\n");
+ return tfa_error_container;
+ }
+
+ /* check sub version level */
+ if ((cntbuf->subversion[1] != NXPTFA_PM_SUBVERSION) &&
+ (cntbuf->subversion[0] != '0')) {
+ pr_err("container sub-version not supported: %c%c\n",
+ cntbuf->subversion[0], cntbuf->subversion[1]);
+ return tfa_error_container;
+ }
+
+ return tfa_error_ok;
+}
+
+/*
+ * Dump the contents of the file header
+ */
+void tfaContShowHeader(nxpTfaHeader_t *hdr)
+{
+ char _id[2];
+
+ pr_debug("File header\n");
+
+ _id[1] = hdr->id >> 8;
+ _id[0] = hdr->id & 0xff;
+ pr_debug("\tid:%.2s version:%.2s subversion:%.2s\n", _id,
+ hdr->version, hdr->subversion);
+ pr_debug("\tsize:%d CRC:0x%08x \n", hdr->size, hdr->CRC);
+ pr_debug("\tcustomer:%.8s application:%.8s type:%.8s\n", hdr->customer,
+ hdr->application, hdr->type);
+}
+
+/*
+ * return device list dsc from index
+ */
+nxpTfaDeviceList_t *tfaContGetDevList(nxpTfaContainer_t *cont, int dev_idx)
+{
+ uint8_t *base = (uint8_t *)cont;
+
+ if (cont == NULL)
+ return NULL;
+
+ if ((dev_idx < 0) || (dev_idx >= cont->ndev))
+ return NULL;
+
+ if (cont->index[dev_idx].type != dscDevice)
+ return NULL;
+
+ base += cont->index[dev_idx].offset;
+ return (nxpTfaDeviceList_t *)base;
+}
+
+/*
+ * get the Nth profile for the Nth device
+ */
+nxpTfaProfileList_t *tfaContGetDevProfList(nxpTfaContainer_t *cont,
+ int devIdx, int profIdx)
+{
+ nxpTfaDeviceList_t *dev;
+ int idx, hit;
+ uint8_t *base = (uint8_t *)cont;
+
+ dev = tfaContGetDevList(cont, devIdx);
+ if (dev) {
+ for (idx = 0, hit = 0; idx < dev->length; idx++) {
+ if (dev->list[idx].type == dscProfile) {
+ if (profIdx == hit++)
+ return (nxpTfaProfileList_t *)(dev->list[idx].offset + base);
+ }
+ }
+ }
+
+ return NULL;
+}
+
+/*
+ * get the number of profiles for the Nth device
+ */
+int tfa_cnt_get_dev_nprof(struct tfa_device *tfa)
+{
+ nxpTfaDeviceList_t *dev;
+ int idx, nprof = 0;
+
+ if (tfa->cnt == NULL)
+ return 0;
+
+ if ((tfa->dev_idx < 0) || (tfa->dev_idx >= tfa->cnt->ndev))
+ return 0;
+
+ dev = tfaContGetDevList(tfa->cnt, tfa->dev_idx);
+ if (dev) {
+ for (idx = 0; idx < dev->length; idx++) {
+ if (dev->list[idx].type == dscProfile) {
+ nprof++;
+ }
+ }
+ }
+
+ return nprof;
+}
+
+/*
+ * get the Nth lifedata for the Nth device
+ */
+nxpTfaLiveDataList_t *tfaContGetDevLiveDataList(nxpTfaContainer_t *cont,
+ int devIdx, int lifeDataIdx)
+{
+ nxpTfaDeviceList_t *dev;
+ int idx, hit;
+ uint8_t *base = (uint8_t *)cont;
+
+ dev = tfaContGetDevList(cont, devIdx);
+ if (dev) {
+ for (idx = 0, hit = 0; idx < dev->length; idx++) {
+ if (dev->list[idx].type == dscLiveData) {
+ if (lifeDataIdx == hit++)
+ return (nxpTfaLiveDataList_t *)
+ (dev->list[idx].offset + base);
+ }
+ }
+ }
+
+ return NULL;
+}
+
+/*
+ * Get the max volume step associated with Nth profile for the Nth device
+ */
+int tfacont_get_max_vstep(struct tfa_device *tfa, int prof_idx)
+{
+ nxpTfaVolumeStep2File_t *vp;
+ struct nxpTfaVolumeStepMax2File *vp3;
+ int vstep_count = 0;
+ vp = (nxpTfaVolumeStep2File_t *)tfacont_getfiledata(tfa, prof_idx,
+ volstepHdr);
+ if (vp == NULL)
+ return 0;
+ /* check the header type to load different NrOfVStep appropriately */
+ if (tfa->tfa_family == 2) {
+ /* this is actually tfa2, so re-read the buffer*/
+ vp3 = (struct nxpTfaVolumeStepMax2File *)
+ tfacont_getfiledata(tfa, prof_idx, volstepHdr);
+ if (vp3) {
+ vstep_count = vp3->NrOfVsteps;
+ }
+ } else {
+ /* this is max1*/
+ if (vp) {
+ vstep_count = vp->vsteps;
+ }
+ }
+ return vstep_count;
+}
+
+/**
+ * Get the file contents associated with the device or profile
+ * Search within the device tree, if not found, search within the profile
+ * tree. There can only be one type of file within profile or device.
+ */
+nxpTfaFileDsc_t *tfacont_getfiledata(struct tfa_device *tfa,
+ int prof_idx, enum nxpTfaHeaderType type)
+{
+ nxpTfaDeviceList_t *dev;
+ nxpTfaProfileList_t *prof;
+ nxpTfaFileDsc_t *file;
+ nxpTfaHeader_t *hdr;
+ unsigned int i;
+
+ if (tfa->cnt == NULL) {
+ pr_err("invalid pointer to container file\n");
+ return NULL;
+ }
+
+ dev = tfaContGetDevList(tfa->cnt, tfa->dev_idx);
+ if (dev == NULL) {
+ pr_err("invalid pointer to container file device list\n");
+ return NULL;
+ }
+
+ /* process the device list until a file type is encountered */
+ for (i = 0; i < dev->length; i++) {
+ if (dev->list[i].type == dscFile) {
+ file = (nxpTfaFileDsc_t *)(dev->list[i].offset + (uint8_t *)tfa->cnt);
+ if (file != NULL) {
+ hdr = (nxpTfaHeader_t *)file->data;
+ /* check for file type */
+ if (hdr->id == type) {
+ return (nxpTfaFileDsc_t *)&file->data;
+ }
+ }
+ }
+ }
+
+ /* File not found in device tree.
+ * So, look in the profile list until the file type is encountered
+ */
+ prof = tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx);
+ if (prof == NULL) {
+ pr_err("invalid pointer to container file profile list\n");
+ return NULL;
+ }
+
+ for (i = 0; i < prof->length; i++) {
+ if (prof->list[i].type == dscFile) {
+ file = (nxpTfaFileDsc_t *)(prof->list[i].offset + (uint8_t *)tfa->cnt);
+ if (file != NULL) {
+ hdr = (nxpTfaHeader_t *)file->data;
+ if (hdr != NULL) {
+ /* check for file type */
+ if (hdr->id == type) {
+ return (nxpTfaFileDsc_t *)&file->data;
+ }
+ }
+ }
+ }
+ }
+
+ if (tfa->verbose)
+ pr_debug("%s: no file found of type %d\n", __FUNCTION__, type);
+
+ return NULL;
+}
+
+/*
+ * write a parameter file to the device
+ */
+static enum Tfa98xx_Error tfaContWriteVstep(struct tfa_device *tfa,
+ nxpTfaVolumeStep2File_t *vp, int vstep)
+{
+ enum Tfa98xx_Error err;
+ unsigned short vol;
+
+ if (vstep < vp->vsteps) {
+ /* vol = (unsigned short)(voldB / (-0.5f)); */
+ vol = (unsigned short)(-2 * float_to_int(*((uint32_t *)&vp->vstep[vstep].attenuation)));
+ if (vol > 255) /* restricted to 8 bits */
+ vol = 255;
+
+ err = tfa98xx_set_volume_level(tfa, vol);
+ if (err != Tfa98xx_Error_Ok)
+ return err;
+
+ err = tfa98xx_dsp_write_preset(tfa, sizeof(vp->vstep[0].preset), vp->vstep[vstep].preset);
+ if (err != Tfa98xx_Error_Ok)
+ return err;
+ err = tfa_cont_write_filterbank(tfa, vp->vstep[vstep].filter);
+
+ } else {
+ pr_err("Incorrect volume given. The value vstep[%d] >= %d\n", vstep, vp->vsteps);
+ err = Tfa98xx_Error_Bad_Parameter;
+ }
+
+ if (tfa->verbose)
+ pr_debug("vstep[%d][%d]\n", tfa->dev_idx, vstep);
+
+ return err;
+}
+
+static struct nxpTfaVolumeStepMessageInfo *
+tfaContGetmsgInfoFromReg(struct nxpTfaVolumeStepRegisterInfo *regInfo)
+{
+ char *p = (char *)regInfo;
+ p += sizeof(regInfo->NrOfRegisters) + (regInfo->NrOfRegisters * sizeof(uint32_t));
+ return (struct nxpTfaVolumeStepMessageInfo *) p;
+}
+
+static int
+tfaContGetmsgLen(struct nxpTfaVolumeStepMessageInfo *msgInfo)
+{
+ return (msgInfo->MessageLength.b[0] << 16) +
+ (msgInfo->MessageLength.b[1] << 8) + msgInfo->MessageLength.b[2];
+}
+
+static struct nxpTfaVolumeStepMessageInfo *
+tfaContGetNextmsgInfo(struct nxpTfaVolumeStepMessageInfo *msgInfo)
+{
+ char *p = (char *)msgInfo;
+ int msgLen = tfaContGetmsgLen(msgInfo);
+ int type = msgInfo->MessageType;
+
+ p += sizeof(msgInfo->MessageType) + sizeof(msgInfo->MessageLength);
+ if (type == 3)
+ p += msgLen;
+ else
+ p += msgLen * 3;
+
+ return (struct nxpTfaVolumeStepMessageInfo *) p;
+}
+
+static struct nxpTfaVolumeStepRegisterInfo*
+tfaContGetNextRegFromEndInfo(struct nxpTfaVolumeStepMessageInfo *msgInfo)
+{
+ char *p = (char *)msgInfo;
+ p += sizeof(msgInfo->NrOfMessages);
+ return (struct nxpTfaVolumeStepRegisterInfo *) p;
+
+}
+
+static struct nxpTfaVolumeStepRegisterInfo*
+tfaContGetRegForVstep(nxpTfaVolumeStepMax2File_t *vp, int idx)
+{
+ int i, j, nrMessage;
+
+ struct nxpTfaVolumeStepRegisterInfo *regInfo
+ = (struct nxpTfaVolumeStepRegisterInfo *) vp->vstepsBin;
+ struct nxpTfaVolumeStepMessageInfo *msgInfo = NULL;
+
+ for (i = 0; i < idx; i++) {
+ msgInfo = tfaContGetmsgInfoFromReg(regInfo);
+ nrMessage = msgInfo->NrOfMessages;
+
+ for (j = 0; j < nrMessage; j++) {
+ msgInfo = tfaContGetNextmsgInfo(msgInfo);
+ }
+ regInfo = tfaContGetNextRegFromEndInfo(msgInfo);
+ }
+
+ return regInfo;
+}
+
+#pragma pack (push, 1)
+struct tfa_partial_msg_block {
+ uint8_t offset;
+ uint16_t change;
+ uint8_t update[16][3];
+};
+#pragma pack (pop)
+
+static enum Tfa98xx_Error tfaContWriteVstepMax2_One(struct tfa_device *tfa,
+ struct nxpTfaVolumeStepMessageInfo *new_msg,
+ struct nxpTfaVolumeStepMessageInfo *old_msg,
+ int enable_partial_update)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ int len = (tfaContGetmsgLen(new_msg) - 1) * 3;
+ char *buf = (char *)new_msg->ParameterData;
+ uint8_t *partial = NULL;
+ uint8_t cmdid[3];
+ int use_partial_coeff = 0;
+
+ if (enable_partial_update) {
+ if (new_msg->MessageType != old_msg->MessageType) {
+ pr_debug("Message type differ - Disable Partial Update\n");
+ enable_partial_update = 0;
+ } else if (tfaContGetmsgLen(new_msg) != tfaContGetmsgLen(old_msg)) {
+ pr_debug("Message Length differ - Disable Partial Update\n");
+ enable_partial_update = 0;
+ }
+ }
+
+ if ((enable_partial_update) && (new_msg->MessageType == 1)) {
+ /* No patial updates for message type 1 (Coefficients) */
+ enable_partial_update = 0;
+ if ((tfa->rev & 0xff) == 0x88)
+ use_partial_coeff = 1;
+ else if ((tfa->rev & 0xff) == 0x13)
+ use_partial_coeff = 1;
+ }
+
+ /* Change Message Len to the actual buffer len */
+ memcpy(cmdid, new_msg->CmdId, sizeof(cmdid));
+
+ /* The algoparams and mbdrc msg id will be changed to the reset type when SBSL=0
+ * if SBSL=1 the msg will remain unchanged. It's up to the tuning engineer to choose the 'without_reset'
+ * types inside the vstep. In other words: the reset msg is applied during SBSL==0 else it remains unchanged.
+ */
+ if (tfa_needs_reset(tfa) == 1) {
+ if (new_msg->MessageType == 0) {
+ cmdid[2] = SB_PARAM_SET_ALGO_PARAMS;
+ if (tfa->verbose)
+ pr_debug("P-ID for SetAlgoParams modified!\n");
+ } else if (new_msg->MessageType == 2) {
+ cmdid[2] = SB_PARAM_SET_MBDRC;
+ if (tfa->verbose)
+ pr_debug("P-ID for SetMBDrc modified!\n");
+ }
+ }
+
+ /*
+ * +sizeof(struct tfa_partial_msg_block) will allow to fit one
+ * additonnal partial block If the partial update goes over the len of
+ * a regular message ,we can safely write our block and check afterward
+ * that we are over the size of a usual update
+ */
+ if (enable_partial_update) {
+ partial = kmem_cache_alloc(tfa->cachep, GFP_KERNEL);
+ if (!partial)
+ pr_debug("Partial update memory error - Disabling\n");
+ }
+
+ if (partial) {
+ uint8_t offset = 0, i = 0;
+ uint16_t *change;
+ uint8_t *n = new_msg->ParameterData;
+ uint8_t *o = old_msg->ParameterData;
+ uint8_t *p = partial;
+ uint8_t *trim = partial;
+
+ /* set dspFiltersReset */
+ *p++ = 0x02;
+ *p++ = 0x00;
+ *p++ = 0x00;
+
+ while ((o < (old_msg->ParameterData + len)) &&
+ (p < (partial + len - 3))) {
+ if ((offset == 0xff) ||
+ (memcmp(n, o, 3 * sizeof(uint8_t)))) {
+ *p++ = offset;
+ change = (uint16_t *)p;
+ *change = 0;
+ p += 2;
+
+ for (i = 0;
+ (i < 16) && (o < (old_msg->ParameterData + len));
+ i++, n += 3, o += 3) {
+ if (memcmp(n, o, 3 * sizeof(uint8_t))) {
+ *change |= BIT(i);
+ memcpy(p, n, 3);
+ p += 3;
+ trim = p;
+ }
+ }
+
+ offset = 0;
+ *change = cpu_to_be16(*change);
+ } else {
+ n += 3;
+ o += 3;
+ offset++;
+ }
+ }
+
+ if (trim == partial) {
+ pr_debug("No Change in message - discarding %d bytes\n", len);
+ len = 0;
+
+ } else if (trim < (partial + len - 3)) {
+ pr_debug("Using partial update: %d -> %d bytes\n", len, (int)(trim - partial + 3));
+
+ /* Add the termination marker */
+ memset(trim, 0x00, 3);
+ trim += 3;
+
+ /* Signal This will be a partial update */
+ cmdid[2] |= BIT(6);
+ buf = (char *)partial;
+ len = (int)(trim - partial);
+ } else {
+ pr_debug("Partial too big - use regular update\n");
+ }
+ }
+
+ if (use_partial_coeff) {
+ err = dsp_partial_coefficients(tfa, old_msg->ParameterData, new_msg->ParameterData);
+ } else if (len) {
+ uint8_t *buffer;
+
+ if (tfa->verbose)
+ pr_debug("Command-ID used: 0x%02x%02x%02x \n", cmdid[0], cmdid[1], cmdid[2]);
+
+ buffer = kmem_cache_alloc(tfa->cachep, GFP_KERNEL);
+ if (buffer == NULL) {
+ err = Tfa98xx_Error_Fail;
+ } else {
+ memcpy(&buffer[0], cmdid, 3);
+ memcpy(&buffer[3], buf, len);
+ err = dsp_msg(tfa, 3 + len, (char *)buffer);
+ kmem_cache_free(tfa->cachep, buffer);
+ }
+ }
+
+ if (partial)
+ kmem_cache_free(tfa->cachep, partial);
+
+ return err;
+}
+
+static enum Tfa98xx_Error tfaContWriteVstepMax2(struct tfa_device *tfa,
+ nxpTfaVolumeStepMax2File_t *vp, int vstep_idx,
+ int vstep_msg_idx)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ struct nxpTfaVolumeStepRegisterInfo *regInfo = NULL;
+ struct nxpTfaVolumeStepMessageInfo *msgInfo = NULL, *p_msgInfo = NULL;
+ nxpTfaBitfield_t bitF;
+ int i, nrMessages, enp = tfa->partial_enable;
+
+ if (vstep_idx >= vp->NrOfVsteps) {
+ pr_debug("Volumestep %d is not available \n", vstep_idx);
+ return Tfa98xx_Error_Bad_Parameter;
+ }
+
+ if (tfa->p_regInfo == NULL) {
+ if (tfa->verbose)
+ pr_debug("Inital vstep write\n");
+ enp = 0;
+ }
+
+ regInfo = tfaContGetRegForVstep(vp, vstep_idx);
+
+ msgInfo = tfaContGetmsgInfoFromReg(regInfo);
+ nrMessages = msgInfo->NrOfMessages;
+
+ if (enp) {
+ p_msgInfo = tfaContGetmsgInfoFromReg(tfa->p_regInfo);
+ if (nrMessages != p_msgInfo->NrOfMessages) {
+ pr_debug("Message different - Disable partial update\n");
+ enp = 0;
+ }
+ }
+
+ for (i = 0; i < nrMessages; i++) {
+ /* Messagetype(3) is Smartstudio Info! Dont send this! */
+ if (msgInfo->MessageType == 3) {
+ /* MessageLength is in bytes */
+ msgInfo = tfaContGetNextmsgInfo(msgInfo);
+ if (enp)
+ p_msgInfo = tfaContGetNextmsgInfo(p_msgInfo);
+ continue;
+ }
+
+ /* If no vstepMsgIndex is passed on, all message needs to be send */
+ if ((vstep_msg_idx >= TFA_MAX_VSTEP_MSG_MARKER) || (vstep_msg_idx == i)) {
+ err = tfaContWriteVstepMax2_One(tfa, msgInfo, p_msgInfo, enp);
+ if (err != Tfa98xx_Error_Ok) {
+ /*
+ * Force a full update for the next write
+ * As the current status of the DSP is unknown
+ */
+ tfa->p_regInfo = NULL;
+ return err;
+ }
+ }
+
+ msgInfo = tfaContGetNextmsgInfo(msgInfo);
+ if (enp)
+ p_msgInfo = tfaContGetNextmsgInfo(p_msgInfo);
+ }
+
+ tfa->p_regInfo = regInfo;
+
+ for (i = 0; i < regInfo->NrOfRegisters * 2; i++) {
+ /* Byte swap the datasheetname */
+ bitF.field = (uint16_t)(regInfo->registerInfo[i] >> 8) | (regInfo->registerInfo[i] << 8);
+ i++;
+ bitF.value = (uint16_t)regInfo->registerInfo[i] >> 8;
+ err = tfaRunWriteBitfield(tfa, bitF);
+ if (err != Tfa98xx_Error_Ok)
+ return err;
+ }
+
+ /* Save the current vstep */
+ tfa_dev_set_swvstep(tfa, (unsigned short)vstep_idx);
+
+ return err;
+}
+
+/*
+ * Write DRC message to the dsp
+ * If needed modify the cmd-id
+ */
+
+enum Tfa98xx_Error tfaContWriteDrcFile(struct tfa_device *tfa,
+ int size, uint8_t data[])
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ uint8_t *msg = NULL;
+
+ msg = kmem_cache_alloc(tfa->cachep, GFP_KERNEL);
+ if (msg == NULL)
+ return Tfa98xx_Error_Fail;
+ memcpy(msg, data, size);
+
+ if (TFA_GET_BF(tfa, SBSL) == 0) {
+ /* Only do this when not set already */
+ if (msg[2] != SB_PARAM_SET_MBDRC) {
+ msg[2] = SB_PARAM_SET_MBDRC;
+
+ if (tfa->verbose) {
+ pr_debug("P-ID for SetMBDrc modified!: ");
+ pr_debug("Command-ID used: 0x%02x%02x%02x \n",
+ msg[0], msg[1], msg[2]);
+ }
+ }
+ }
+
+ /* Send cmdId + payload to dsp */
+ err = dsp_msg(tfa, size, (const char *)msg);
+
+ kmem_cache_free(tfa->cachep, msg);
+
+ return err;
+}
+
+
+/*
+ * write a parameter file to the device
+ * The VstepIndex and VstepMsgIndex are only used to write a specific msg from the vstep file.
+ */
+enum Tfa98xx_Error tfaContWriteFile(struct tfa_device *tfa,
+ nxpTfaFileDsc_t *file, int vstep_idx, int vstep_msg_idx)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ nxpTfaHeader_t *hdr = (nxpTfaHeader_t *)file->data;
+ nxpTfaHeaderType_t type;
+ int size, i;
+ char subVerString[8] = { 0 };
+ int subversion = 0;
+
+ if (tfa->verbose) {
+ tfaContShowHeader(hdr);
+ }
+
+ type = (nxpTfaHeaderType_t)hdr->id;
+ if ((type == msgHdr) || ((type == volstepHdr) && (tfa->tfa_family == 2))) {
+ subVerString[0] = hdr->subversion[0];
+ subVerString[1] = hdr->subversion[1];
+ subVerString[2] = '\0';
+
+ sscanf(subVerString, "%d", &subversion);
+
+ if ((subversion > 0) &&
+ (((hdr->customer[0]) == 'A') && ((hdr->customer[1]) == 'P') &&
+ ((hdr->customer[2]) == 'I') && ((hdr->customer[3]) == 'V'))) {
+ if (tfa->is_probus_device) {
+ /* Temporary workaround (example: For climax --calibrate
+ * scenario for probus devices)
+ */
+ err = tfaGetFwApiVersion(tfa,
+ (unsigned char *)&tfa->fw_itf_ver[0]);
+ if (err) {
+ pr_debug("[%s] cannot get FWAPI error = %d \n",
+ __FUNCTION__, err);
+ return err;
+ }
+ for (i = 0; i < 3; i++) {
+ //+4 to skip "?PIV" string part in the .msg file.
+ if (tfa->fw_itf_ver[i] != hdr->customer[i + 4]) {
+ ERRORMSG("Error: tfaContWriteFile: Expected FW API \
+ version = %d.%d.%d, Msg File version: %d.%d.%d \n",
+ tfa->fw_itf_ver[0],
+ tfa->fw_itf_ver[1],
+ tfa->fw_itf_ver[2],
+ hdr->customer[4],
+ hdr->customer[5],
+ hdr->customer[6]);
+ return Tfa98xx_Error_Bad_Parameter;
+ }
+ }
+ } else if ((tfa->fw_itf_ver[2] != hdr->customer[4]) ||
+ (tfa->fw_itf_ver[1] != hdr->customer[5]) ||
+ ((tfa->fw_itf_ver[0] >> 6) & 0x03) != hdr->customer[6]) {
+
+ ERRORMSG("Error: tfaContWriteFile: Expected FW API version = %d.%d.%d, Msg File version: %d.%d.%d \n",
+ (tfa->fw_itf_ver[2]) & 0xff,
+ (tfa->fw_itf_ver[1]) & 0xff,
+ (tfa->fw_itf_ver[0] >> 6) & 0x03,
+ hdr->customer[4],
+ hdr->customer[5],
+ hdr->customer[6]);
+ return Tfa98xx_Error_Bad_Parameter;
+ }
+ }
+ }
+
+ switch (type) {
+ case msgHdr: /* generic DSP message */
+ size = hdr->size - sizeof(nxpTfaMsgFile_t);
+ err = dsp_msg(tfa, size, (const char *)((nxpTfaMsgFile_t *)hdr)->data);
+ break;
+ case volstepHdr:
+ if (tfa->tfa_family == 2) {
+ err = tfaContWriteVstepMax2(tfa,
+ (nxpTfaVolumeStepMax2File_t *)hdr,
+ vstep_idx, vstep_msg_idx);
+ } else {
+ err = tfaContWriteVstep(tfa, (nxpTfaVolumeStep2File_t *)hdr,
+ vstep_idx);
+ }
+ break;
+ case speakerHdr:
+ if (tfa->tfa_family == 2) {
+ /* Remove header and xml_id */
+ size = hdr->size - sizeof(struct nxpTfaSpkHeader)
+ - sizeof(struct nxpTfaFWVer);
+
+ err = dsp_msg(tfa, size,
+ (const char *)(((nxpTfaSpeakerFile_t *)hdr)->data +
+ (sizeof(struct nxpTfaFWVer))));
+ } else {
+ size = hdr->size - sizeof(nxpTfaSpeakerFile_t);
+ err = tfa98xx_dsp_write_speaker_parameters(tfa, size,
+ (const unsigned char *)((nxpTfaSpeakerFile_t *)hdr)->data);
+ }
+ break;
+ case presetHdr:
+ size = hdr->size - sizeof(nxpTfaPreset_t);
+ err = tfa98xx_dsp_write_preset(tfa, size,
+ (const unsigned char *)((nxpTfaPreset_t *)hdr)->data);
+ break;
+ case equalizerHdr:
+ err = tfa_cont_write_filterbank(tfa, ((nxpTfaEqualizerFile_t *)hdr)->filter);
+ break;
+ case patchHdr:
+ size = hdr->size - sizeof(nxpTfaPatch_t); // size is total length
+ err = tfa_dsp_patch(tfa, size, (const unsigned char *)((nxpTfaPatch_t *)hdr)->data);
+ break;
+ case configHdr:
+ size = hdr->size - sizeof(nxpTfaConfig_t);
+ err = tfa98xx_dsp_write_config(tfa, size,
+ (const unsigned char *)((nxpTfaConfig_t *)hdr)->data);
+ break;
+ case drcHdr:
+ if (hdr->version[0] == NXPTFA_DR3_VERSION) {
+ /* Size is total size - hdrsize(36) - xmlversion(3) */
+ size = hdr->size - sizeof(nxpTfaDrc2_t);
+ err = tfaContWriteDrcFile(tfa, size, ((nxpTfaDrc2_t *)hdr)->data);
+ } else {
+ /*
+ * The DRC file is split as:
+ * 36 bytes for generic header (customer, application, and type)
+ * 127x3 (381) bytes first block contains the device and sample rate
+ * independent settings
+ * 127x3 (381) bytes block the device and sample rate specific values.
+ * The second block can always be recalculated from the first block,
+ * if vlsCal and the sample rate are known.
+ */
+ //size = hdr->size - sizeof(nxpTfaDrc_t);
+ size = 381; /* fixed size for first block */
+
+ //+381 is done to only send the second part of the drc block
+ err = tfa98xx_dsp_write_drc(tfa, size,
+ ((const unsigned char *)((nxpTfaDrc_t *)hdr)->data + 381));
+ }
+ break;
+ case infoHdr:
+ /* Ignore */
+ break;
+ default:
+ pr_err("Header is of unknown type: 0x%x\n", type);
+ return Tfa98xx_Error_Bad_Parameter;
+ }
+
+ return err;
+}
+
+/**
+ * get the 1st of this dsc type this devicelist
+ */
+static nxpTfaDescPtr_t *tfa_cnt_get_dsc(nxpTfaContainer_t *cnt, nxpTfaDescriptorType_t type, int dev_idx)
+{
+ nxpTfaDeviceList_t *dev = tfaContDevice(cnt, dev_idx);
+ nxpTfaDescPtr_t *_this;
+ int i;
+
+ if (!dev) {
+ return NULL;
+ }
+ /* process the list until a the type is encountered */
+ for (i = 0; i < dev->length; i++) {
+ if (dev->list[i].type == (uint32_t)type) {
+ _this = (nxpTfaDescPtr_t *)(dev->list[i].offset + (uint8_t *)cnt);
+ return _this;
+ }
+
+ }
+
+ return NULL;
+}
+
+/**
+ * get the device type from the patch in this devicelist
+ * - find the patch file for this devidx
+ * - return the devid from the patch or 0 if not found
+ */
+int tfa_cnt_get_devid(nxpTfaContainer_t *cnt, int dev_idx)
+{
+ nxpTfaPatch_t *patchfile;
+ nxpTfaDescPtr_t *patchdsc;
+ uint8_t *patchheader;
+ unsigned short devid, checkaddress;
+ int checkvalue;
+
+ patchdsc = tfa_cnt_get_dsc(cnt, dscPatch, dev_idx);
+ if (!patchdsc) /* no patch for this device, assume non-i2c */
+ return 0;
+ patchdsc += 2; /* first the filename dsc and filesize, so skip them */
+ patchfile = (nxpTfaPatch_t *)patchdsc;
+
+ patchheader = patchfile->data;
+
+ checkaddress = (patchheader[1] << 8) + patchheader[2];
+ checkvalue =
+ (patchheader[3] << 16) + (patchheader[4] << 8) + patchheader[5];
+
+ devid = patchheader[0];
+
+ if (checkaddress == 0xFFFF && checkvalue != 0xFFFFFF && checkvalue != 0) {
+ devid = patchheader[5] << 8 | patchheader[0]; /* full revid */
+ }
+
+ return devid;
+}
+
+/**
+ * get the firmware version from the patch in this devicelist
+ */
+int tfa_cnt_get_patch_version(struct tfa_device *tfa)
+{
+ nxpTfaPatch_t *patchfile;
+ nxpTfaDescPtr_t *patchdsc;
+ uint8_t *data;
+ int size, version;
+
+ if (tfa->cnt == NULL)
+ return ERR;
+
+ patchdsc = tfa_cnt_get_dsc(tfa->cnt, dscPatch, tfa->dev_idx);
+ patchdsc += 2; /* first the filename dsc and filesize, so skip them */
+ patchfile = (nxpTfaPatch_t *)patchdsc;
+
+ size = patchfile->hdr.size - sizeof(nxpTfaPatch_t);
+ data = patchfile->data;
+
+ version = (data[size - 3] << 16) + (data[size - 2] << 8) + data[size - 1];
+
+ return version;
+}
+
+
+/*
+ * get the slave for the device if it exists
+ */
+enum Tfa98xx_Error tfaContGetSlave(struct tfa_device *tfa, uint8_t *slave_addr)
+{
+ nxpTfaDeviceList_t *dev = NULL;
+
+ /* Make sure the cnt file is loaded */
+ if (tfa->cnt != NULL) {
+ dev = tfaContDevice(tfa->cnt, tfa->dev_idx);
+ }
+
+ if (dev == NULL) {
+ /* Check if slave argument is used! */
+ if (gslave_address == 0) {
+ return Tfa98xx_Error_Bad_Parameter;
+ } else {
+ *slave_addr = gslave_address;
+ return Tfa98xx_Error_Ok;
+ }
+ }
+
+ *slave_addr = dev->dev;
+ return Tfa98xx_Error_Ok;
+}
+
+/* If no container file is given, we can always have used the slave argument */
+void tfaContSetSlave(uint8_t slave_addr)
+{
+ gslave_address = slave_addr;
+}
+
+/*
+ * lookup slave and return device index
+ */
+int tfa_cont_get_idx(struct tfa_device *tfa)
+{
+ nxpTfaDeviceList_t *dev = NULL;
+ int i;
+
+ for (i = 0; i < tfa->cnt->ndev; i++) {
+ dev = tfaContDevice(tfa->cnt, i);
+ if (dev->dev == tfa->slave_address)
+ break;
+
+ }
+ if (i == tfa->cnt->ndev)
+ return ERR;
+
+ return i;
+}
+
+/*
+ * write a bit field
+ */
+enum Tfa98xx_Error tfaRunWriteBitfield(struct tfa_device *tfa, nxpTfaBitfield_t bf)
+{
+ enum Tfa98xx_Error error;
+ uint16_t value;
+ union {
+ uint16_t field;
+ nxpTfaBfEnum_t Enum;
+ } bfUni;
+
+ value = bf.value;
+ bfUni.field = bf.field;
+#ifdef TFA_DEBUG
+ if (tfa->verbose)
+ pr_debug("bitfield: %s=0x%x (0x%x[%d..%d]=0x%x)\n", tfaContBfName(bfUni.field, tfa->rev), value,
+ bfUni.Enum.address, bfUni.Enum.pos, bfUni.Enum.pos + bfUni.Enum.len, value);
+#endif
+ error = tfa_set_bf(tfa, bfUni.field, value);
+
+ return error;
+}
+
+/*
+ * read a bit field
+ */
+enum Tfa98xx_Error tfaRunReadBitfield(struct tfa_device *tfa, nxpTfaBitfield_t *bf)
+{
+ enum Tfa98xx_Error error;
+ union {
+ uint16_t field;
+ nxpTfaBfEnum_t Enum;
+ } bfUni;
+ uint16_t regvalue, msk;
+
+ bfUni.field = bf->field;
+
+ error = reg_read(tfa, (unsigned char)(bfUni.Enum.address), ®value);
+ if (error)
+ return error;
+
+ msk = ((1 << (bfUni.Enum.len + 1)) - 1) << bfUni.Enum.pos;
+
+ regvalue &= msk;
+ bf->value = regvalue >> bfUni.Enum.pos;
+
+ return error;
+}
+
+/*
+ dsp mem direct write
+ */
+static enum Tfa98xx_Error tfaRunWriteDspMem(struct tfa_device *tfa, nxpTfaDspMem_t *cfmem)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ int i;
+
+ for (i = 0; i < cfmem->size; i++) {
+ if (tfa->verbose)
+ pr_debug("dsp mem (%d): 0x%02x=0x%04x\n", cfmem->type, cfmem->address, cfmem->words[i]);
+
+ error = mem_write(tfa, cfmem->address++, cfmem->words[i], cfmem->type);
+ if (error)
+ return error;
+ }
+
+ return error;
+}
+
+/*
+ * write filter payload to DSP
+ * note that the data is in an aligned union for all filter variants
+ * the aa data is used but it's the same for all of them
+ */
+static enum Tfa98xx_Error tfaRunWriteFilter(struct tfa_device *tfa, nxpTfaContBiquad_t *bq)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ enum Tfa98xx_DMEM dmem;
+ uint16_t address;
+ uint8_t data[3 * 3 + sizeof(bq->aa.bytes)];
+ int i, channel = 0, runs = 1;
+ int8_t saved_index = bq->aa.index; /* This is used to set back the index */
+
+ /* Channel=1 is primary, Channel=2 is secondary*/
+ if (bq->aa.index > 100) {
+ bq->aa.index -= 100;
+ channel = 2;
+ } else if (bq->aa.index > 50) {
+ bq->aa.index -= 50;
+ channel = 1;
+ } else if ((tfa->rev & 0xff) == 0x88) {
+ runs = 2;
+ }
+
+ if (tfa->verbose) {
+ if (channel == 2)
+ pr_debug("filter[%d,S]", bq->aa.index);
+ else if (channel == 1)
+ pr_debug("filter[%d,P]", bq->aa.index);
+ else
+ pr_debug("filter[%d]", bq->aa.index);
+ }
+
+ for (i = 0; i < runs; i++) {
+ if (runs == 2)
+ channel++;
+
+ /* get the target address for the filter on this device */
+ dmem = tfa98xx_filter_mem(tfa, bq->aa.index, &address, channel);
+ if (dmem == Tfa98xx_DMEM_ERR) {
+ if (tfa->verbose) {
+ pr_debug("Warning: XFilter settings are applied via msg file (ini filter[x] format is skipped).\n");
+ }
+ /* Dont exit with an error here, We could continue without problems */
+ return Tfa98xx_Error_Ok;
+ }
+
+ /* send a DSP memory message that targets the devices specific memory for the filter
+ * msg params: which_mem, start_offset, num_words
+ */
+ memset(data, 0, 3 * 3);
+ data[2] = dmem; /* output[0] = which_mem */
+ data[4] = address >> 8; /* output[1] = start_offset */
+ data[5] = address & 0xff;
+ data[8] = sizeof(bq->aa.bytes) / 3; /*output[2] = num_words */
+ memcpy(&data[9], bq->aa.bytes, sizeof(bq->aa.bytes)); /* payload */
+
+ if (tfa->tfa_family == 2)
+ error = tfa_dsp_cmd_id_write(tfa, MODULE_FRAMEWORK, FW_PAR_ID_SET_MEMORY, sizeof(data), data);
+ else
+ error = tfa_dsp_cmd_id_write(tfa, MODULE_FRAMEWORK, 4 /* param */, sizeof(data), data);
+ }
+
+#ifdef TFA_DEBUG
+ if (tfa->verbose) {
+ if (bq->aa.index == 13) {
+ pr_debug("=%d,%.0f,%.2f \n",
+ bq->in.type, bq->in.cutOffFreq, bq->in.leakage);
+ } else if (bq->aa.index >= 10 && bq->aa.index <= 12) {
+ pr_debug("=%d,%.0f,%.1f,%.1f \n", bq->aa.type,
+ bq->aa.cutOffFreq, bq->aa.rippleDb, bq->aa.rolloff);
+ } else {
+ pr_debug("= unsupported filter index \n");
+ }
+ }
+#endif
+
+ /* Because we can load the same filters multiple times
+ * For example: When we switch profile we re-write in operating mode.
+ * We then need to remember the index (primary, secondary or both)
+ */
+ bq->aa.index = saved_index;
+
+ return error;
+}
+
+/*
+ * write the register based on the input address, value and mask
+ * only the part that is masked will be updated
+ */
+static enum Tfa98xx_Error tfaRunWriteRegister(struct tfa_device *tfa, nxpTfaRegpatch_t *reg)
+{
+ enum Tfa98xx_Error error;
+ uint16_t value, newvalue;
+
+ if (tfa->verbose)
+ pr_debug("register: 0x%02x=0x%04x (msk=0x%04x)\n", reg->address, reg->value, reg->mask);
+
+ error = reg_read(tfa, reg->address, &value);
+ if (error)
+ return error;
+
+ value &= ~reg->mask;
+ newvalue = reg->value & reg->mask;
+
+ value |= newvalue;
+ error = reg_write(tfa, reg->address, value);
+
+ return error;
+
+}
+
+// write reg and bitfield items in the devicelist to the target
+enum Tfa98xx_Error tfaContWriteRegsDev(struct tfa_device *tfa)
+{
+ nxpTfaDeviceList_t *dev = tfaContDevice(tfa->cnt, tfa->dev_idx);
+ nxpTfaBitfield_t *bitF;
+ int i;
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+
+ if (!dev) {
+ return Tfa98xx_Error_Bad_Parameter;
+ }
+
+ /* process the list until a patch, file of profile is encountered */
+ for (i = 0; i < dev->length; i++) {
+ if (dev->list[i].type == dscPatch ||
+ dev->list[i].type == dscFile ||
+ dev->list[i].type == dscProfile)
+ break;
+
+ if (dev->list[i].type == dscBitfield) {
+ bitF = (nxpTfaBitfield_t *)(dev->list[i].offset + (uint8_t *)tfa->cnt);
+ err = tfaRunWriteBitfield(tfa, *bitF);
+ }
+ if (dev->list[i].type == dscRegister) {
+ err = tfaRunWriteRegister(tfa, (nxpTfaRegpatch_t *)(dev->list[i].offset + (char *)tfa->cnt));
+ }
+
+ if (err)
+ break;
+ }
+
+ return err;
+}
+
+// write reg and bitfield items in the profilelist the target
+enum Tfa98xx_Error tfaContWriteRegsProf(struct tfa_device *tfa, int prof_idx)
+{
+ nxpTfaProfileList_t *prof = tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx);
+ nxpTfaBitfield_t *bitf;
+ unsigned int i;
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+
+ if (!prof) {
+ return Tfa98xx_Error_Bad_Parameter;
+ }
+
+ if (tfa->verbose)
+ pr_debug("----- profile: %s (%d) -----\n", tfaContGetString(tfa->cnt, &prof->name), prof_idx);
+
+ /* process the list until the end of the profile or the default section */
+ for (i = 0; i < prof->length; i++) {
+ /* We only want to write the values before the default section when we switch profile */
+ if (prof->list[i].type == dscDefault)
+ break;
+
+ if (prof->list[i].type == dscBitfield) {
+ bitf = (nxpTfaBitfield_t *)(prof->list[i].offset + (uint8_t *)tfa->cnt);
+ err = tfaRunWriteBitfield(tfa, *bitf);
+ }
+ if (prof->list[i].type == dscRegister) {
+ err = tfaRunWriteRegister(tfa, (nxpTfaRegpatch_t *)(prof->list[i].offset + (char *)tfa->cnt));
+ }
+ if (err)
+ break;
+ }
+ return err;
+}
+
+// write patchfile in the devicelist to the target
+enum Tfa98xx_Error tfaContWritePatch(struct tfa_device *tfa)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ nxpTfaDeviceList_t *dev = tfaContDevice(tfa->cnt, tfa->dev_idx);
+ nxpTfaFileDsc_t *file;
+ nxpTfaPatch_t *patchfile;
+ int size, i;
+
+ if (!dev) {
+ return Tfa98xx_Error_Bad_Parameter;
+ }
+ /* process the list until a patch is encountered */
+ for (i = 0; i < dev->length; i++) {
+ if (dev->list[i].type == dscPatch) {
+ file = (nxpTfaFileDsc_t *)(dev->list[i].offset + (uint8_t *)tfa->cnt);
+ patchfile = (nxpTfaPatch_t *)&file->data;
+ if (tfa->verbose)
+ tfaContShowHeader(&patchfile->hdr);
+ size = patchfile->hdr.size - sizeof(nxpTfaPatch_t); // size is total length
+ err = tfa_dsp_patch(tfa, size, (const unsigned char *)patchfile->data);
+ if (err)
+ return err;
+ }
+ }
+
+ return Tfa98xx_Error_Ok;
+}
+
+/**
+ * Create a buffer which can be used to send to the dsp.
+ */
+static void create_dsp_buffer_msg(struct tfa_device *tfa, nxpTfaMsg_t *msg, char *buffer, int *size)
+{
+ int i, nr = 0;
+
+ (void)tfa;
+
+ /* Copy cmdId. Remember that the cmdId is reversed */
+ buffer[nr++] = msg->cmdId[2];
+ buffer[nr++] = msg->cmdId[1];
+ buffer[nr++] = msg->cmdId[0];
+
+ /* Copy the data to the buffer */
+ for (i = 0; i < msg->msg_size; i++) {
+ buffer[nr++] = (uint8_t)((msg->data[i] >> 16) & 0xffff);
+ buffer[nr++] = (uint8_t)((msg->data[i] >> 8) & 0xff);
+ buffer[nr++] = (uint8_t)(msg->data[i] & 0xff);
+ }
+
+ *size = nr;
+}
+
+// write all param files in the devicelist to the target
+enum Tfa98xx_Error tfaContWriteFiles(struct tfa_device *tfa)
+{
+ nxpTfaDeviceList_t *dev = tfaContDevice(tfa->cnt, tfa->dev_idx);
+ nxpTfaFileDsc_t *file;
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ char buffer[(MEMTRACK_MAX_WORDS * 3) + 3] = { 0 }; //every word requires 3 and 3 is the msg
+ int i, size = 0;
+
+ if (!dev) {
+ return Tfa98xx_Error_Bad_Parameter;
+ }
+ /* process the list and write all files */
+ for (i = 0; i < dev->length; i++) {
+ if (dev->list[i].type == dscFile) {
+ file = (nxpTfaFileDsc_t *)(dev->list[i].offset + (uint8_t *)tfa->cnt);
+ if (tfaContWriteFile(tfa, file, 0, TFA_MAX_VSTEP_MSG_MARKER)) {
+ return Tfa98xx_Error_Bad_Parameter;
+ }
+ }
+
+ if (dev->list[i].type == dscSetInputSelect ||
+ dev->list[i].type == dscSetOutputSelect ||
+ dev->list[i].type == dscSetProgramConfig ||
+ dev->list[i].type == dscSetLagW ||
+ dev->list[i].type == dscSetGains ||
+ dev->list[i].type == dscSetvBatFactors ||
+ dev->list[i].type == dscSetSensesCal ||
+ dev->list[i].type == dscSetSensesDelay ||
+ dev->list[i].type == dscSetMBDrc ||
+ dev->list[i].type == dscSetFwkUseCase ||
+ dev->list[i].type == dscSetVddpConfig) {
+ create_dsp_buffer_msg(tfa, (nxpTfaMsg_t *)
+ (dev->list[i].offset + (char *)tfa->cnt), buffer, &size);
+ if (tfa->verbose) {
+ pr_debug("command: %s=0x%02x%02x%02x \n",
+ tfaContGetCommandString(dev->list[i].type),
+ (unsigned char)buffer[0], (unsigned char)buffer[1], (unsigned char)buffer[2]);
+ }
+
+ err = dsp_msg(tfa, size, buffer);
+ }
+
+ if (dev->list[i].type == dscCmd) {
+ size = *(uint16_t *)(dev->list[i].offset + (char *)tfa->cnt);
+
+ err = dsp_msg(tfa, size, dev->list[i].offset + 2 + (char *)tfa->cnt);
+ if (tfa->verbose) {
+ const char *cmd_id = dev->list[i].offset + 2 + (char *)tfa->cnt;
+ pr_debug("Writing cmd=0x%02x%02x%02x \n", (uint8_t)cmd_id[0], (uint8_t)cmd_id[1], (uint8_t)cmd_id[2]);
+ }
+ }
+ if (err != Tfa98xx_Error_Ok)
+ break;
+
+ if (dev->list[i].type == dscCfMem) {
+ err = tfaRunWriteDspMem(tfa, (nxpTfaDspMem_t *)(dev->list[i].offset + (uint8_t *)tfa->cnt));
+ }
+
+ if (err != Tfa98xx_Error_Ok)
+ break;
+ }
+
+ return err;
+}
+
+/*
+ * write all param files in the profilelist to the target
+ * this is used during startup when maybe ACS is set
+ */
+enum Tfa98xx_Error tfaContWriteFilesProf(struct tfa_device *tfa, int prof_idx, int vstep_idx)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ nxpTfaProfileList_t *prof = tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx);
+ char buffer[(MEMTRACK_MAX_WORDS * 3) + 3] = { 0 }; //every word requires 3 and 3 is the msg
+ unsigned int i;
+ nxpTfaFileDsc_t *file;
+ nxpTfaPatch_t *patchfile;
+ int size;
+
+ if (!prof) {
+ return Tfa98xx_Error_Bad_Parameter;
+ }
+
+ /* process the list and write all files */
+ for (i = 0; i < prof->length; i++) {
+ switch (prof->list[i].type) {
+ case dscFile:
+ file = (nxpTfaFileDsc_t *)(prof->list[i].offset + (uint8_t *)tfa->cnt);
+ err = tfaContWriteFile(tfa, file, vstep_idx, TFA_MAX_VSTEP_MSG_MARKER);
+ break;
+ case dscPatch:
+ file = (nxpTfaFileDsc_t *)(prof->list[i].offset + (uint8_t *)tfa->cnt);
+ patchfile = (nxpTfaPatch_t *)&file->data;
+ if (tfa->verbose)
+ tfaContShowHeader(&patchfile->hdr);
+ size = patchfile->hdr.size - sizeof(nxpTfaPatch_t); // size is total length
+ err = tfa_dsp_patch(tfa, size, (const unsigned char *)patchfile->data);
+ break;
+ case dscCfMem:
+ err = tfaRunWriteDspMem(tfa, (nxpTfaDspMem_t *)(prof->list[i].offset + (uint8_t *)tfa->cnt));
+ break;
+ case dscSetInputSelect:
+ case dscSetOutputSelect:
+ case dscSetProgramConfig:
+ case dscSetLagW:
+ case dscSetGains:
+ case dscSetvBatFactors:
+ case dscSetSensesCal:
+ case dscSetSensesDelay:
+ case dscSetMBDrc:
+ case dscSetFwkUseCase:
+ case dscSetVddpConfig:
+ create_dsp_buffer_msg(tfa, (nxpTfaMsg_t *)
+ (prof->list[i].offset + (uint8_t *)tfa->cnt), buffer, &size);
+ if (tfa->verbose) {
+ pr_debug("command: %s=0x%02x%02x%02x \n",
+ tfaContGetCommandString(prof->list[i].type),
+ (unsigned char)buffer[0], (unsigned char)buffer[1], (unsigned char)buffer[2]);
+ }
+
+ err = dsp_msg(tfa, size, buffer);
+ break;
+ default:
+ /* ignore any other type */
+ break;
+ }
+ }
+
+ return err;
+}
+
+static enum Tfa98xx_Error tfaContWriteItem(struct tfa_device *tfa, nxpTfaDescPtr_t *dsc)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ nxpTfaRegpatch_t *reg;
+ nxpTfaMode_t *cas;
+ nxpTfaBitfield_t *bitf;
+
+ // When no DSP should only write to HW registers.
+ if (tfa->ext_dsp == 0 && !(dsc->type == dscBitfield || dsc->type == dscRegister)) {
+ return Tfa98xx_Error_Ok;
+ }
+
+ switch (dsc->type) {
+ case dscDefault:
+ case dscDevice: // ignore
+ case dscProfile: // profile list
+ break;
+ case dscRegister: // register patch
+ reg = (nxpTfaRegpatch_t *)(dsc->offset + (uint8_t *)tfa->cnt);
+ return tfaRunWriteRegister(tfa, reg);
+ //pr_debug("$0x%2x=0x%02x,0x%02x\n", reg->address, reg->mask, reg->value);
+ break;
+ case dscString: // ascii: zero terminated string
+ pr_debug(";string: %s\n", tfaContGetString(tfa->cnt, dsc));
+ break;
+ case dscFile: // filename + file contents
+ case dscPatch:
+ break;
+ case dscMode:
+ cas = (nxpTfaMode_t *)(dsc->offset + (uint8_t *)tfa->cnt);
+ if (cas->value == Tfa98xx_Mode_RCV)
+ tfa98xx_select_mode(tfa, Tfa98xx_Mode_RCV);
+ else
+ tfa98xx_select_mode(tfa, Tfa98xx_Mode_Normal);
+ break;
+ case dscCfMem:
+ err = tfaRunWriteDspMem(tfa, (nxpTfaDspMem_t *)(dsc->offset + (uint8_t *)tfa->cnt));
+ break;
+ case dscBitfield:
+ bitf = (nxpTfaBitfield_t *)(dsc->offset + (uint8_t *)tfa->cnt);
+ return tfaRunWriteBitfield(tfa, *bitf);
+ break;
+ case dscFilter:
+ return tfaRunWriteFilter(tfa, (nxpTfaContBiquad_t *)(dsc->offset + (uint8_t *)tfa->cnt));
+ break;
+ }
+
+ return err;
+}
+
+static unsigned int tfa98xx_sr_from_field(unsigned int field)
+{
+ switch (field) {
+ case 0:
+ return 8000;
+ case 1:
+ return 11025;
+ case 2:
+ return 12000;
+ case 3:
+ return 16000;
+ case 4:
+ return 22050;
+ case 5:
+ return 24000;
+ case 6:
+ return 32000;
+ case 7:
+ return 44100;
+ case 8:
+ return 48000;
+ default:
+ return 0;
+ }
+}
+
+enum Tfa98xx_Error tfa_write_filters(struct tfa_device *tfa, int prof_idx)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ nxpTfaProfileList_t *prof = tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx);
+ unsigned int i;
+ int status;
+
+ if (!prof) {
+ return Tfa98xx_Error_Bad_Parameter;
+ }
+
+ if (tfa->verbose) {
+ pr_debug("----- profile: %s (%d) -----\n", tfaContGetString(tfa->cnt, &prof->name), prof_idx);
+ pr_debug("Waiting for CLKS... \n");
+ }
+
+ for (i = 10; i > 0; i--) {
+ err = tfa98xx_dsp_system_stable(tfa, &status);
+ if (status)
+ break;
+ else
+ msleep_interruptible(10);
+ }
+
+ if (i == 0) {
+ if (tfa->verbose)
+ pr_err("Unable to write filters, CLKS=0 \n");
+
+ return Tfa98xx_Error_StateTimedOut;
+ }
+
+ /* process the list until the end of the profile or the default section */
+ for (i = 0; i < prof->length; i++) {
+ if (prof->list[i].type == dscFilter) {
+ if (tfaContWriteItem(tfa, &prof->list[i]) != Tfa98xx_Error_Ok)
+ return Tfa98xx_Error_Bad_Parameter;
+ }
+ }
+
+ return err;
+}
+
+unsigned int tfa98xx_get_profile_sr(struct tfa_device *tfa, unsigned int prof_idx)
+{
+ nxpTfaBitfield_t *bitf;
+ unsigned int i;
+ nxpTfaDeviceList_t *dev;
+ nxpTfaProfileList_t *prof;
+ int fs_profile = -1;
+
+ dev = tfaContDevice(tfa->cnt, tfa->dev_idx);
+ if (!dev)
+ return 0;
+
+ prof = tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx);
+ if (!prof)
+ return 0;
+
+ /* Check profile fields first */
+ for (i = 0; i < prof->length; i++) {
+ if (prof->list[i].type == dscDefault)
+ break;
+
+ /* check for profile settingd (AUDFS) */
+ if (prof->list[i].type == dscBitfield) {
+ bitf = (nxpTfaBitfield_t *)(prof->list[i].offset + (uint8_t *)tfa->cnt);
+ if (bitf->field == TFA_FAM(tfa, AUDFS)) {
+ fs_profile = bitf->value;
+ break;
+ }
+ }
+ }
+
+ if (tfa->verbose)
+ pr_debug("%s - profile fs: 0x%x = %dHz (%d - %d)\n",
+ __FUNCTION__, fs_profile,
+ tfa98xx_sr_from_field(fs_profile),
+ tfa->dev_idx, prof_idx);
+
+ if (fs_profile != -1)
+ return tfa98xx_sr_from_field(fs_profile);
+
+ /* Check for container default setting */
+ /* process the list until a patch, file of profile is encountered */
+ for (i = 0; i < dev->length; i++) {
+ if (dev->list[i].type == dscPatch ||
+ dev->list[i].type == dscFile ||
+ dev->list[i].type == dscProfile)
+ break;
+
+ if (dev->list[i].type == dscBitfield) {
+ bitf = (nxpTfaBitfield_t *)(dev->list[i].offset + (uint8_t *)tfa->cnt);
+ if (bitf->field == TFA_FAM(tfa, AUDFS)) {
+ fs_profile = bitf->value;
+ break;
+ }
+ }
+ /* Ignore register case */
+ }
+
+ if (tfa->verbose)
+ pr_debug("%s - default fs: 0x%x = %dHz (%d - %d)\n",
+ __FUNCTION__, fs_profile,
+ tfa98xx_sr_from_field(fs_profile),
+ tfa->dev_idx, prof_idx);
+
+ if (fs_profile != -1)
+ return tfa98xx_sr_from_field(fs_profile);
+
+ return 48000; /* default of HW */
+}
+
+static enum Tfa98xx_Error get_sample_rate_info(struct tfa_device *tfa, nxpTfaProfileList_t *prof, nxpTfaProfileList_t *previous_prof, int fs_previous_profile)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ nxpTfaBitfield_t *bitf;
+ unsigned int i;
+ int fs_default_profile = 8; /* default is 48kHz */
+ int fs_next_profile = 8; /* default is 48kHz */
+
+
+ /* ---------- default settings previous profile ---------- */
+ for (i = 0; i < previous_prof->length; i++) {
+ /* Search for the default section */
+ if (i == 0) {
+ while (previous_prof->list[i].type != dscDefault && i < previous_prof->length) {
+ i++;
+ }
+ i++;
+ }
+
+ /* Only if we found the default section search for AUDFS */
+ if (i < previous_prof->length) {
+ if (previous_prof->list[i].type == dscBitfield) {
+ bitf = (nxpTfaBitfield_t *)(previous_prof->list[i].offset + (uint8_t *)tfa->cnt);
+ if (bitf->field == TFA_FAM(tfa, AUDFS)) {
+ fs_default_profile = bitf->value;
+ break;
+ }
+ }
+ }
+ }
+
+ /* ---------- settings next profile ---------- */
+ for (i = 0; i < prof->length; i++) {
+ /* We only want to write the values before the default section */
+ if (prof->list[i].type == dscDefault)
+ break;
+ /* search for AUDFS */
+ if (prof->list[i].type == dscBitfield) {
+ bitf = (nxpTfaBitfield_t *)(prof->list[i].offset + (uint8_t *)tfa->cnt);
+ if (bitf->field == TFA_FAM(tfa, AUDFS)) {
+ fs_next_profile = bitf->value;
+ break;
+ }
+ }
+ }
+
+ /* Enable if needed for debugging!
+ if (tfa->verbose) {
+ pr_debug("sample rate from the previous profile: %d \n", fs_previous_profile);
+ pr_debug("sample rate in the default section: %d \n", fs_default_profile);
+ pr_debug("sample rate for the next profile: %d \n", fs_next_profile);
+ }
+ */
+
+ if (fs_next_profile != fs_default_profile) {
+ if (tfa->verbose)
+ pr_debug("Writing delay tables for AUDFS=%d \n", fs_next_profile);
+
+ /* If the AUDFS from the next profile is not the same as
+ * the AUDFS from the default we need to write new delay tables
+ */
+ err = tfa98xx_dsp_write_tables(tfa, fs_next_profile);
+ } else if (fs_default_profile != fs_previous_profile) {
+ if (tfa->verbose)
+ pr_debug("Writing delay tables for AUDFS=%d \n", fs_default_profile);
+
+ /* But if we do not have a new AUDFS in the next profile and
+ * the AUDFS from the default profile is not the same as the AUDFS
+ * from the previous profile we also need to write new delay tables
+ */
+ err = tfa98xx_dsp_write_tables(tfa, fs_default_profile);
+ }
+
+ return err;
+}
+
+/*
+ * process all items in the profilelist
+ * NOTE an error return during processing will leave the device muted
+ *
+ */
+enum Tfa98xx_Error tfaContWriteProfile(struct tfa_device *tfa, int prof_idx, int vstep_idx)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ nxpTfaProfileList_t *prof = tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx);
+ nxpTfaProfileList_t *previous_prof = tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, tfa_dev_get_swprof(tfa));
+ char buffer[(MEMTRACK_MAX_WORDS * 4) + 4] = { 0 }; //every word requires 3 or 4 bytes, and 3 or 4 is the msg
+ unsigned int i, k = 0, j = 0, tries = 0;
+ nxpTfaFileDsc_t *file;
+ int size = 0, ready, fs_previous_profile = 8; /* default fs is 48kHz*/
+
+ if (!prof || !previous_prof) {
+ pr_err("Error trying to get the (previous) swprofile \n");
+ return Tfa98xx_Error_Bad_Parameter;
+ }
+
+ if (tfa->verbose) {
+ tfa98xx_trace_printk("device:%s profile:%s vstep:%d\n", tfaContDeviceName(tfa->cnt, tfa->dev_idx),
+ tfaContProfileName(tfa->cnt, tfa->dev_idx, prof_idx), vstep_idx);
+ }
+
+ /* We only make a power cycle when the profiles are not in the same group */
+ if (prof->group == previous_prof->group && prof->group != 0) {
+ if (tfa->verbose) {
+ pr_debug("The new profile (%s) is in the same group as the current profile (%s) \n",
+ tfaContGetString(tfa->cnt, &prof->name), tfaContGetString(tfa->cnt, &previous_prof->name));
+ }
+ } else {
+ /* mute */
+ err = tfaRunMute(tfa);
+ if (err)
+ return err;
+
+ /* Get current sample rate before we start switching */
+ fs_previous_profile = TFA_GET_BF(tfa, AUDFS);
+
+ /* clear SBSL to make sure we stay in initCF state */
+ if (tfa->tfa_family == 2) {
+ TFA_SET_BF_VOLATILE(tfa, SBSL, 0);
+ }
+
+ /* When we switch profile we first power down the subsystem
+ * This should only be done when we are in operating mode
+ */
+ if (((tfa->tfa_family == 2) && (TFA_GET_BF(tfa, MANSTATE) >= 6)) || (tfa->tfa_family != 2)) {
+ err = tfa98xx_powerdown(tfa, 1);
+ if (err)
+ return err;
+
+ /* Wait until we are in PLL powerdown */
+ do {
+ err = tfa98xx_dsp_system_stable(tfa, &ready);
+ if (!ready)
+ break;
+ else
+ msleep_interruptible(10); /* wait 10ms to avoid busload */
+ tries++;
+ } while (tries <= 100);
+
+ if (tries > 100) {
+ pr_debug("Wait for PLL powerdown timed out!\n");
+ return Tfa98xx_Error_StateTimedOut;
+ }
+ } else {
+ pr_debug("No need to go to powerdown now \n");
+ }
+ }
+
+ /* set all bitfield settings */
+ /* First set all default settings */
+ if (tfa->verbose) {
+ pr_debug("---------- default settings profile: %s (%d) ---------- \n",
+ tfaContGetString(tfa->cnt, &previous_prof->name), tfa_dev_get_swprof(tfa));
+ }
+
+ err = show_current_state(tfa);
+
+ /* Loop profile length */
+ for (i = 0; i < previous_prof->length; i++) {
+ /* Search for the default section */
+ if (i == 0) {
+ while (previous_prof->list[i].type != dscDefault && i < previous_prof->length) {
+ i++;
+ }
+ i++;
+ }
+
+ /* Only if we found the default section try writing the items */
+ if (i < previous_prof->length) {
+ if (tfaContWriteItem(tfa, &previous_prof->list[i]) != Tfa98xx_Error_Ok)
+ return Tfa98xx_Error_Bad_Parameter;
+ }
+ }
+
+ if (tfa->verbose)
+ pr_debug("---------- new settings profile: %s (%d) ---------- \n",
+ tfaContGetString(tfa->cnt, &prof->name), prof_idx);
+
+ /* set new settings */
+ for (i = 0; i < prof->length; i++) {
+ /* Remember where we currently are with writing items*/
+ j = i;
+
+ /* We only want to write the values before the default section when we switch profile */
+ /* process and write all non-file items */
+ switch (prof->list[i].type) {
+ case dscFile:
+ case dscPatch:
+ case dscSetInputSelect:
+ case dscSetOutputSelect:
+ case dscSetProgramConfig:
+ case dscSetLagW:
+ case dscSetGains:
+ case dscSetvBatFactors:
+ case dscSetSensesCal:
+ case dscSetSensesDelay:
+ case dscSetMBDrc:
+ case dscSetFwkUseCase:
+ case dscSetVddpConfig:
+ case dscCmd:
+ case dscFilter:
+ case dscDefault:
+ /* When one of these files are found, we exit */
+ i = prof->length;
+ break;
+ default:
+ err = tfaContWriteItem(tfa, &prof->list[i]);
+ if (err != Tfa98xx_Error_Ok)
+ return Tfa98xx_Error_Bad_Parameter;
+ break;
+ }
+ }
+
+ if (prof->group != previous_prof->group || prof->group == 0) {
+ if (tfa->tfa_family == 2)
+ TFA_SET_BF_VOLATILE(tfa, MANSCONF, 1);
+
+ /* Leave powerdown state */
+ err = tfa_cf_powerup(tfa);
+ if (err)
+ return err;
+
+ err = show_current_state(tfa);
+
+ if (tfa->tfa_family == 2) {
+ /* Reset SBSL to 0 (workaround of enbl_powerswitch=0) */
+ TFA_SET_BF_VOLATILE(tfa, SBSL, 0);
+ /* Sending commands to DSP we need to make sure RST is 0 (otherwise we get no response)*/
+ TFA_SET_BF(tfa, RST, 0);
+ }
+ }
+
+ /* Check if there are sample rate changes */
+ err = get_sample_rate_info(tfa, prof, previous_prof, fs_previous_profile);
+ if (err)
+ return err;
+
+
+ /* Write files from previous profile (default section)
+ * Should only be used for the patch&trap patch (file)
+ */
+ if (tfa->ext_dsp != 0) {
+ if (tfa->tfa_family == 2) {
+ for (i = 0; i < previous_prof->length; i++) {
+ /* Search for the default section */
+ if (i == 0) {
+ while (previous_prof->list[i].type != dscDefault && i < previous_prof->length) {
+ i++;
+ }
+ i++;
+ }
+
+ /* Only if we found the default section try writing the file */
+ if (i < previous_prof->length) {
+ if (previous_prof->list[i].type == dscFile || previous_prof->list[i].type == dscPatch) {
+ /* Only write this once */
+ if (tfa->verbose && k == 0) {
+ pr_debug("---------- files default profile: %s (%d) ---------- \n",
+ tfaContGetString(tfa->cnt, &previous_prof->name), prof_idx);
+ k++;
+ }
+ file = (nxpTfaFileDsc_t *)(previous_prof->list[i].offset + (uint8_t *)tfa->cnt);
+ err = tfaContWriteFile(tfa, file, vstep_idx, TFA_MAX_VSTEP_MSG_MARKER);
+ }
+ }
+ }
+ }
+
+ if (tfa->verbose) {
+ pr_debug("---------- files new profile: %s (%d) ---------- \n",
+ tfaContGetString(tfa->cnt, &prof->name), prof_idx);
+ }
+ }
+
+ /* write everything until end or the default section starts
+ * Start where we currenly left */
+ for (i = j; i < prof->length; i++) {
+ /* We only want to write the values before the default section when we switch profile */
+
+ if (prof->list[i].type == dscDefault) {
+ break;
+ }
+
+ switch (prof->list[i].type) {
+ case dscFile:
+ case dscPatch:
+ /* For tiberius stereo 1 device does not have a dsp! */
+ if (tfa->ext_dsp != 0) {
+ file = (nxpTfaFileDsc_t *)(prof->list[i].offset + (uint8_t *)tfa->cnt);
+ err = tfaContWriteFile(tfa, file, vstep_idx, TFA_MAX_VSTEP_MSG_MARKER);
+ }
+ break;
+ case dscSetInputSelect:
+ case dscSetOutputSelect:
+ case dscSetProgramConfig:
+ case dscSetLagW:
+ case dscSetGains:
+ case dscSetvBatFactors:
+ case dscSetSensesCal:
+ case dscSetSensesDelay:
+ case dscSetMBDrc:
+ case dscSetFwkUseCase:
+ case dscSetVddpConfig:
+ /* For tiberius stereo 1 device does not have a dsp! */
+ if (tfa->ext_dsp != 0) {
+ create_dsp_buffer_msg(tfa, (nxpTfaMsg_t *)
+ (prof->list[i].offset + (char *)tfa->cnt), buffer, &size);
+ err = dsp_msg(tfa, size, buffer);
+
+ if (tfa->verbose) {
+ pr_debug("command: %s=0x%02x%02x%02x \n",
+ tfaContGetCommandString(prof->list[i].type),
+ (unsigned char)buffer[0], (unsigned char)buffer[1], (unsigned char)buffer[2]);
+ }
+ }
+ break;
+ case dscCmd:
+ /* For tiberius stereo 1 device does not have a dsp! */
+ if (tfa->ext_dsp != 0) {
+ size = *(uint16_t *)(prof->list[i].offset + (char *)tfa->cnt);
+ err = dsp_msg(tfa, size, prof->list[i].offset + 2 + (char *)tfa->cnt);
+ if (tfa->verbose) {
+ const char *cmd_id = prof->list[i].offset + 2 + (char *)tfa->cnt;
+ pr_debug("Writing cmd=0x%02x%02x%02x \n", (uint8_t)cmd_id[0], (uint8_t)cmd_id[1], (uint8_t)cmd_id[2]);
+ }
+ }
+ break;
+ default:
+ /* This allows us to write bitfield, registers or xmem after files */
+ if (tfaContWriteItem(tfa, &prof->list[i]) != Tfa98xx_Error_Ok) {
+ return Tfa98xx_Error_Bad_Parameter;
+ }
+ break;
+ }
+
+ if (err != Tfa98xx_Error_Ok) {
+ return err;
+ }
+ }
+
+ if ((prof->group != previous_prof->group || prof->group == 0) && (tfa->tfa_family == 2)) {
+ if (TFA_GET_BF(tfa, REFCKSEL) == 0) {
+ /* set SBSL to go to operation mode */
+ TFA_SET_BF_VOLATILE(tfa, SBSL, 1);
+ }
+ }
+
+ return err;
+}
+
+/*
+ * process only vstep in the profilelist
+ *
+ */
+enum Tfa98xx_Error tfaContWriteFilesVstep(struct tfa_device *tfa, int prof_idx, int vstep_idx)
+{
+ nxpTfaProfileList_t *prof = tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx);
+ unsigned int i;
+ nxpTfaFileDsc_t *file;
+ nxpTfaHeader_t *hdr;
+ nxpTfaHeaderType_t type;
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+
+ if (!prof)
+ return Tfa98xx_Error_Bad_Parameter;
+
+ if (tfa->verbose)
+ tfa98xx_trace_printk("device:%s profile:%s vstep:%d\n", tfaContDeviceName(tfa->cnt, tfa->dev_idx),
+ tfaContProfileName(tfa->cnt, tfa->dev_idx, prof_idx), vstep_idx);
+
+ /* write vstep file only! */
+ for (i = 0; i < prof->length; i++) {
+ if (prof->list[i].type == dscFile) {
+ file = (nxpTfaFileDsc_t *)(prof->list[i].offset + (uint8_t *)tfa->cnt);
+ hdr = (nxpTfaHeader_t *)file->data;
+ type = (nxpTfaHeaderType_t)hdr->id;
+
+ switch (type) {
+ case volstepHdr:
+ if (tfaContWriteFile(tfa, file, vstep_idx, TFA_MAX_VSTEP_MSG_MARKER))
+ return Tfa98xx_Error_Bad_Parameter;
+ break;
+ default:
+ break;
+ }
+ }
+ }
+
+ return err;
+}
+
+char *tfaContGetString(nxpTfaContainer_t *cnt, nxpTfaDescPtr_t *dsc)
+{
+ if (dsc->type != dscString)
+ return "Undefined string";
+
+ return dsc->offset + (char *)cnt;
+}
+
+char *tfaContGetCommandString(uint32_t type)
+{
+ if (type == dscSetInputSelect)
+ return "SetInputSelector";
+ else if (type == dscSetOutputSelect)
+ return "SetOutputSelector";
+ else if (type == dscSetProgramConfig)
+ return "SetProgramConfig";
+ else if (type == dscSetLagW)
+ return "SetLagW";
+ else if (type == dscSetGains)
+ return "SetGains";
+ else if (type == dscSetvBatFactors)
+ return "SetvBatFactors";
+ else if (type == dscSetSensesCal)
+ return "SetSensesCal";
+ else if (type == dscSetSensesDelay)
+ return "SetSensesDelay";
+ else if (type == dscSetMBDrc)
+ return "SetMBDrc";
+ else if (type == dscSetFwkUseCase)
+ return "SetFwkUseCase";
+ else if (type == dscSetVddpConfig)
+ return "SetVddpConfig";
+ else if (type == dscFilter)
+ return "filter";
+ else
+ return "Undefined string";
+}
+
+/*
+ * Get the name of the device at a certain index in the container file
+ * return device name
+ */
+char *tfaContDeviceName(nxpTfaContainer_t *cnt, int dev_idx)
+{
+ nxpTfaDeviceList_t *dev;
+
+ dev = tfaContDevice(cnt, dev_idx);
+ if (dev == NULL)
+ return "!ERROR!";
+
+ return tfaContGetString(cnt, &dev->name);
+}
+
+/*
+ * Get the application name from the container file application field
+ * note that the input stringbuffer should be sizeof(application field)+1
+ *
+ */
+int tfa_cnt_get_app_name(struct tfa_device *tfa, char *name)
+{
+ unsigned int i;
+ int len = 0;
+
+ for (i = 0; i < sizeof(tfa->cnt->application); i++) {
+ if (isalnum(tfa->cnt->application[i])) /* copy char if valid */
+ name[len++] = tfa->cnt->application[i];
+ if (tfa->cnt->application[i] == '\0')
+ break;
+ }
+ name[len++] = '\0';
+
+ return len;
+}
+
+/*
+ * Get profile index of the calibration profile.
+ * Returns: (profile index) if found, (-2) if no
+ * calibration profile is found or (-1) on error
+ */
+int tfaContGetCalProfile(struct tfa_device *tfa)
+{
+ int prof, cal_idx = -2;
+
+ if ((tfa->dev_idx < 0) || (tfa->dev_idx >= tfa->cnt->ndev))
+ return ERR;
+
+ /* search for the calibration profile in the list of profiles */
+ for (prof = 0; prof < tfa->cnt->nprof; prof++) {
+ if (strstr(tfaContProfileName(tfa->cnt,
+ tfa->dev_idx, prof), ".cal") != NULL) {
+ cal_idx = prof;
+ pr_debug("Using calibration profile: '%s'\n",
+ tfaContProfileName(tfa->cnt, tfa->dev_idx, prof));
+ break;
+ }
+ }
+
+ return cal_idx;
+}
+
+/**
+ * Is the profile a tap profile
+ */
+int tfaContIsTapProfile(struct tfa_device *tfa, int prof_idx)
+{
+ if ((tfa->dev_idx < 0) || (tfa->dev_idx >= tfa->cnt->ndev))
+ return ERR;
+
+ /* Check if next profile is tap profile */
+ if (strstr(tfaContProfileName(tfa->cnt,
+ tfa->dev_idx, prof_idx), ".tap") != NULL) {
+ pr_debug("Using Tap profile: '%s'\n",
+ tfaContProfileName(tfa->cnt, tfa->dev_idx, prof_idx));
+ return 1;
+ }
+
+ return 0;
+}
+
+/*
+ * Get the name of the profile at certain index for a device in the container
+ * file return profile name
+ */
+char *tfaContProfileName(nxpTfaContainer_t *cnt, int dev_idx, int prof_idx)
+{
+ nxpTfaProfileList_t *prof = NULL;
+
+ /* the Nth profiles for this device */
+ prof = tfaContGetDevProfList(cnt, dev_idx, prof_idx);
+
+ /* If the index is out of bound */
+ if (prof == NULL)
+ return "NONE";
+
+ return tfaContGetString(cnt, &prof->name);
+}
+
+/*
+ * return 1st profile list
+ */
+nxpTfaProfileList_t *tfaContGet1stProfList(nxpTfaContainer_t *cont)
+{
+ nxpTfaProfileList_t *prof;
+ uint8_t *b = (uint8_t *)cont;
+
+ int maxdev = 0;
+ nxpTfaDeviceList_t *dev;
+
+ // get nr of devlists
+ maxdev = cont->ndev;
+ // get last devlist
+ dev = tfaContGetDevList(cont, maxdev - 1);
+ if (dev == NULL)
+ return NULL;
+ // the 1st profile starts after the last device list
+ b = (uint8_t *)dev + sizeof(nxpTfaDeviceList_t) +
+ dev->length * (sizeof(nxpTfaDescPtr_t));
+ prof = (nxpTfaProfileList_t *)b;
+ return prof;
+}
+
+/*
+ * return 1st livedata list
+ */
+nxpTfaLiveDataList_t *tfaContGet1stLiveDataList(nxpTfaContainer_t *cont)
+{
+ nxpTfaLiveDataList_t *ldata;
+ nxpTfaProfileList_t *prof;
+ nxpTfaDeviceList_t *dev;
+ uint8_t *b = (uint8_t *)cont;
+ int maxdev, maxprof;
+
+ // get nr of devlists+1
+ maxdev = cont->ndev;
+ // get nr of proflists
+ maxprof = cont->nprof;
+
+ // get last devlist
+ dev = tfaContGetDevList(cont, maxdev - 1);
+ // the 1st livedata starts after the last device list
+ b = (uint8_t *)dev + sizeof(nxpTfaDeviceList_t) +
+ dev->length * (sizeof(nxpTfaDescPtr_t));
+
+ while (maxprof != 0) {
+ // get last proflist
+ prof = (nxpTfaProfileList_t *)b;
+ b += sizeof(nxpTfaProfileList_t) +
+ ((prof->length - 1) * (sizeof(nxpTfaDescPtr_t)));
+ maxprof--;
+ }
+
+ /* Else the marker falls off */
+ b += 4; //bytes
+
+ ldata = (nxpTfaLiveDataList_t *)b;
+ return ldata;
+}
+
+/*
+ * return the device list pointer
+ */
+nxpTfaDeviceList_t *tfaContDevice(nxpTfaContainer_t *cnt, int dev_idx)
+{
+ return tfaContGetDevList(cnt, dev_idx);
+}
+
+/*
+ * return the next profile:
+ * - assume that all profiles are adjacent
+ * - calculate the total length of the input
+ * - the input profile + its length is the next profile
+ */
+nxpTfaProfileList_t *tfaContNextProfile(nxpTfaProfileList_t *prof)
+{
+ uint8_t *this, *next; /* byte pointers for byte pointer arithmetic */
+ nxpTfaProfileList_t *nextprof;
+ int listlength; /* total length of list in bytes */
+
+ if (prof == NULL)
+ return NULL;
+
+ if (prof->ID != TFA_PROFID)
+ return NULL; /* invalid input */
+
+ this = (uint8_t *)prof;
+ /* nr of items in the list, length includes name dsc so - 1*/
+ listlength = (prof->length - 1) * sizeof(nxpTfaDescPtr_t);
+ /* the sizeof(nxpTfaProfileList_t) includes the list[0] length */
+ next = this + listlength +
+ sizeof(nxpTfaProfileList_t);// - sizeof(nxpTfaDescPtr_t);
+ nextprof = (nxpTfaProfileList_t *)next;
+
+ if (nextprof->ID != TFA_PROFID)
+ return NULL;
+
+ return nextprof;
+}
+
+/*
+ * return the next livedata
+ */
+nxpTfaLiveDataList_t *tfaContNextLiveData(nxpTfaLiveDataList_t *livedata)
+{
+ nxpTfaLiveDataList_t *nextlivedata = (nxpTfaLiveDataList_t *)
+ ((char *)livedata + (livedata->length * 4) +
+ sizeof(nxpTfaLiveDataList_t) - 4);
+
+ if (nextlivedata->ID == TFA_LIVEDATAID)
+ return nextlivedata;
+
+ return NULL;
+}
+
+/*
+ * check CRC for container
+ * CRC is calculated over the bytes following the CRC field
+ *
+ * return non zero value on error
+ */
+int tfaContCrcCheckContainer(nxpTfaContainer_t *cont)
+{
+ uint8_t *base;
+ size_t size;
+ uint32_t crc;
+ // ptr to bytes following the CRC field
+ base = (uint8_t *)&cont->CRC + 4;
+ // nr of bytes following the CRC field
+ size = (size_t)(cont->size - (base - (uint8_t *)cont));
+ crc = ~crc32_le(~0u, base, size);
+
+ return crc != cont->CRC;
+}
+
+static void get_all_features_from_cnt(struct tfa_device *tfa,
+ int *hw_feature_register, int sw_feature_register[2])
+{
+ nxpTfaFeatures_t *features;
+ int i;
+
+ nxpTfaDeviceList_t *dev = tfaContDevice(tfa->cnt, tfa->dev_idx);
+
+ /* Init values in case no keyword is defined in cnt file: */
+ *hw_feature_register = -1;
+ sw_feature_register[0] = -1;
+ sw_feature_register[1] = -1;
+
+ if (dev == NULL)
+ return;
+
+ // process the device list
+ for (i = 0; i < dev->length; i++) {
+ if (dev->list[i].type == dscFeatures) {
+ features = (nxpTfaFeatures_t *)(dev->list[i].offset +
+ (uint8_t *)tfa->cnt);
+ *hw_feature_register = features->value[0];
+ sw_feature_register[0] = features->value[1];
+ sw_feature_register[1] = features->value[2];
+ break;
+ }
+ }
+}
+
+/* wrapper function */
+void get_hw_features_from_cnt(struct tfa_device *tfa, int *hw_feature_register)
+{
+ int sw_feature_register[2];
+ get_all_features_from_cnt(tfa, hw_feature_register, sw_feature_register);
+}
+
+/* wrapper function */
+void get_sw_features_from_cnt(struct tfa_device *tfa,
+ int sw_feature_register[2])
+{
+ int hw_feature_register;
+ get_all_features_from_cnt(tfa, &hw_feature_register, sw_feature_register);
+}
+
+enum Tfa98xx_Error tfa98xx_factory_trimmer(struct tfa_device *tfa)
+{
+ return (tfa->dev_ops.factory_trimmer)(tfa);
+}
+
+enum Tfa98xx_Error tfa_set_filters(struct tfa_device *tfa, int prof_idx)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ nxpTfaProfileList_t *prof = tfaContGetDevProfList(tfa->cnt,
+ tfa->dev_idx, prof_idx);
+ unsigned int i;
+
+ if (!prof)
+ return Tfa98xx_Error_Bad_Parameter;
+
+ /* If we are in powerdown there is no need to set filters */
+ if (TFA_GET_BF(tfa, PWDN) == 1)
+ return Tfa98xx_Error_Ok;
+
+ /* loop the profile to find filter settings */
+ for (i = 0; i < prof->length; i++) {
+ /* We only want to write the values before the default section */
+ if (prof->list[i].type == dscDefault)
+ break;
+
+ /* write all filter settings */
+ if (prof->list[i].type == dscFilter) {
+ if (tfaContWriteItem(tfa, &prof->list[i]) != Tfa98xx_Error_Ok)
+ return err;
+ }
+ }
+
+ return err;
+}
+
+int tfa_tib_dsp_msgmulti(struct tfa_device *tfa, int length,
+ const char *buffer)
+{
+ uint8_t *buf = (uint8_t *)buffer;
+ static uint8_t *blob = NULL, *blobptr; /* TODO: not multi-thread safe */
+ static int total; /* TODO: not multi-thread safe */
+ int post_len = 0;
+
+ /* checks for 24b_BE or 32_LE */
+ int len_word_in_bytes = (tfa->convert_dsp32) ? 4 : 3;
+ /*
+ * TODO: get rid of these magic constants max size should depend
+ * on the tfa device type
+ */
+ int tfadsp_max_msg_size = (tfa->convert_dsp32) ? 5336 : 4000;
+
+ /* No data found*/
+ if (length == -1 && blob == NULL) {
+ return ERR;
+ }
+
+ if (length == -1) {
+ int i;
+ /* set last length field to zero */
+ for (i = total; i < (total + len_word_in_bytes); i++) {
+ blob[i] = 0;
+ }
+ total += len_word_in_bytes;
+ memcpy(buf, blob, total);
+
+ kfree(blob);
+ /* Set to NULL pointer, otherwise no new malloc is done! */
+ blob = NULL;
+ return total;
+ }
+
+ if (blob == NULL) {
+ if (tfa->verbose)
+ pr_debug("%s, Creating the multi-message \n\n", __FUNCTION__);
+
+ blob = kmalloc(tfadsp_max_msg_size, GFP_KERNEL);
+ /* add command ID for multi-msg = 0x008015 */
+ if (tfa->convert_dsp32) {
+ blob[0] = 0x15;
+ blob[1] = 0x80;
+ blob[2] = 0x0;
+ blob[3] = 0x0;
+ } else {
+ blob[0] = 0x0;
+ blob[1] = 0x80;
+ blob[2] = 0x15;
+ }
+ blobptr = blob;
+ blobptr += len_word_in_bytes;
+ total = len_word_in_bytes;
+ }
+
+ if (tfa->verbose) {
+ pr_debug("%s, id:0x%02x%02x%02x, length:%d \n", __FUNCTION__,
+ buf[0], buf[1], buf[2], length);
+ }
+
+ /* check total message size after concatination */
+ post_len = total + length + (2 * len_word_in_bytes);
+ if (post_len > tfadsp_max_msg_size) {
+ /* pr_debug("New multi-message too large! (%d >= %d (max.)),
+ current length: %d\n", post_len, tfadsp_max_msg_size, total); */
+ return Tfa98xx_Error_Buffer_too_small;
+ }
+
+ /* add length field (length in words) to the multi message */
+ if (tfa->convert_dsp32) {
+ *blobptr++ = (uint8_t)((length / len_word_in_bytes) & 0xff); /* lsb */
+ *blobptr++ = (uint8_t)(((length / len_word_in_bytes) & 0xff00) >> 8); /* msb */
+ *blobptr++ = 0x0;
+ *blobptr++ = 0x0;
+ } else {
+ *blobptr++ = 0x0;
+ /* msb */
+ *blobptr++ = (uint8_t)(((length / len_word_in_bytes) & 0xff00) >> 8);
+ /* lsb */
+ *blobptr++ = (uint8_t)((length / len_word_in_bytes) & 0xff);
+ }
+ memcpy(blobptr, buf, length);
+ blobptr += length;
+ total += (length + len_word_in_bytes);
+
+ /* SetRe25 message is always the last message of the multi-msg */
+ if (tfa->convert_dsp32) {
+ if (buf[1] == 0x81 && buf[0] == SB_PARAM_SET_RE25C)
+ return 1; /* 1 means last message is done! */
+ } else {
+ if (buf[1] == 0x81 && buf[2] == SB_PARAM_SET_RE25C)
+ return 1; /* 1 means last message is done! */
+ }
+
+ return 0;
+}
diff --git a/inc/tfa_container.h b/sound/soc/codecs/tfa_container.h
similarity index 98%
rename from inc/tfa_container.h
rename to sound/soc/codecs/tfa_container.h
index d357f95..bc22865 100644
--- a/inc/tfa_container.h
+++ b/sound/soc/codecs/tfa_container.h
@@ -1,350 +1,350 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef TFACONTAINER_H_
-#define TFACONTAINER_H_
-
-/* static limits */
-#define TFACONT_MAXDEVS (4) /* maximum nr of devices */
-#define TFACONT_MAXPROFS (16) /* maximum nr of profiles */
-
-#include "tfa98xx_parameters.h"
-
-/**
-* Pass the container buffer, initialize and allocate internal memory.
-*
-* @param cnt pointer to the start of the buffer holding the container file
-* @param length of the data in bytes
-* @return
-* - tfa_error_ok if normal
-* - tfa_error_container invalid container data
-* - tfa_error_bad_param invalid parameter
-*
-*/
-enum tfa_error tfa_load_cnt(void *cnt, int length);
-
-/**
- * Return the descriptor string
- * @param cnt pointer to the container struct
- * @param dsc pointer to nxpTfa descriptor
- * @return descriptor string
- */
-char *tfaContGetString(nxpTfaContainer_t *cnt, nxpTfaDescPtr_t *dsc);
-
-/**
- * Gets the string for the given command type number
- * @param type number representing a command
- * @return string of a command
- */
-char *tfaContGetCommandString(uint32_t type);
-
-/**
- * get the device type from the patch in this devicelist
- * - find the patch file for this devidx
- * - return the devid from the patch or 0 if not found
- * @param cnt pointer to container file
- * @param dev_idx device index
- * @return descriptor string
- */
-int tfa_cnt_get_devid(nxpTfaContainer_t *cnt, int dev_idx);
-
-/**
- * Get the slave for the device if it exists.
- * @param tfa the device struct pointer
- * @param slave_addr the index of the device
- * @return Tfa98xx_Error
- */
-enum Tfa98xx_Error tfaContGetSlave(struct tfa_device *tfa, uint8_t *slave_addr);
-
-void tfaContSetSlave(uint8_t slave_addr);
-
-/**
- * Get the index for a skave address.
- * @param tfa the device struct pointer
- * @return the device index
- */
-int tfa_cont_get_idx(struct tfa_device *tfa);
-
-/**
- * Write reg and bitfield items in the devicelist to the target.
- * @param tfa the device struct pointer
- * @return Tfa98xx_Error
- */
-enum Tfa98xx_Error tfaContWriteRegsDev(struct tfa_device *tfa);
-
-/**
- * Write reg and bitfield items in the profilelist to the target.
- * @param tfa the device struct pointer
- * @param prof_idx the profile index
- * @return Tfa98xx_Error
- */
-enum Tfa98xx_Error tfaContWriteRegsProf(struct tfa_device *tfa, int prof_idx);
-
-/**
- * Write a patchfile in the devicelist to the target.
- * @param tfa the device struct pointer
- * @return Tfa98xx_Error
- */
-enum Tfa98xx_Error tfaContWritePatch(struct tfa_device *tfa);
-
-/**
- * Write all param files in the devicelist to the target.
- * @param tfa the device struct pointer
- * @return Tfa98xx_Error
- */
-enum Tfa98xx_Error tfaContWriteFiles(struct tfa_device *tfa);
-
-/**
- * Get sample rate from passed profile index
- * @param tfa the device struct pointer
- * @param prof_idx the index of the profile
- * @return sample rate value
- */
-unsigned int tfa98xx_get_profile_sr(struct tfa_device *tfa, unsigned int prof_idx);
-
-/**
- * Get the device name string
- * @param cnt the pointer to the container struct
- * @param dev_idx the index of the device
- * @return device name string or error string if not found
- */
-char *tfaContDeviceName(nxpTfaContainer_t *cnt, int dev_idx);
-
-/**
- * Get the application name from the container file application field
- * @param tfa the device struct pointer
- * @param name the input stringbuffer with size: sizeof(application field)+1
- * @return actual string length
- */
-int tfa_cnt_get_app_name(struct tfa_device *tfa, char *name);
-
-/**
- * Get profile index of the calibration profile
- * @param tfa the device struct pointer
- * @return profile index, -2 if no calibration profile is found or -1 on error
- */
-int tfaContGetCalProfile(struct tfa_device *tfa);
-
-/**
- * Is the profile a tap profile ?
- * @param tfa the device struct pointer
- * @param prof_idx the index of the profile
- * @return 1 if the profile is a tap profile or 0 if not
- */
-int tfaContIsTapProfile(struct tfa_device *tfa, int prof_idx);
-
-/**
- * Get the name of the profile at certain index for a device in the container file
- * @param cnt the pointer to the container struct
- * @param dev_idx the index of the device
- * @param prof_idx the index of the profile
- * @return profile name string or error string if not found
- */
-char *tfaContProfileName(nxpTfaContainer_t *cnt, int dev_idx, int prof_idx);
-
-/**
- * Process all items in the profilelist
- * NOTE an error return during processing will leave the device muted
- * @param tfa the device struct pointer
- * @param prof_idx index of the profile
- * @param vstep_idx index of the vstep
- * @return Tfa98xx_Error
- */
-enum Tfa98xx_Error tfaContWriteProfile(struct tfa_device *tfa, int prof_idx, int vstep_idx);
-
-/**
- * Specify the speaker configurations (cmd id) (Left, right, both, none)
- * @param dev_idx index of the device
- * @param configuration name string of the configuration
- */
-void tfa98xx_set_spkr_select(int dev_idx, char *configuration);
-
-enum Tfa98xx_Error tfa_cont_write_filterbank(struct tfa_device *tfa, nxpTfaFilter_t *filter);
-
-/**
- * Write all param files in the profilelist to the target
- * this is used during startup when maybe ACS is set
- * @param tfa the device struct pointer
- * @param prof_idx the index of the profile
- * @param vstep_idx the index of the vstep
- * @return Tfa98xx_Error
- */
-enum Tfa98xx_Error tfaContWriteFilesProf(struct tfa_device *tfa, int prof_idx, int vstep_idx);
-enum Tfa98xx_Error tfaContWriteFilesVstep(struct tfa_device *tfa, int prof_idx, int vstep_idx);
-enum Tfa98xx_Error tfaContWriteDrcFile(struct tfa_device *tfa, int size, uint8_t data[]);
-
-/**
- * Get the device list dsc from the tfaContainer
- * @param cont pointer to the tfaContainer
- * @param dev_idx the index of the device
- * @return device list pointer
- */
-nxpTfaDeviceList_t *tfaContGetDevList(nxpTfaContainer_t *cont, int dev_idx);
-
-/**
- * Get the Nth profile for the Nth device
- * @param cont pointer to the tfaContainer
- * @param dev_idx the index of the device
- * @param prof_idx the index of the profile
- * @return profile list pointer
- */
-nxpTfaProfileList_t *tfaContGetDevProfList(nxpTfaContainer_t *cont, int dev_idx, int prof_idx);
-
-/**
- * Get the number of profiles for device from contaienr
- * @param cont pointer to the tfaContainer
- * @param dev_idx the index of the device
- * @return device list pointer
- */
-int tfa_cnt_get_dev_nprof(struct tfa_device *tfa);
-
-
-/**
- * Get the Nth livedata for the Nth device
- * @param cont pointer to the tfaContainer
- * @param dev_idx the index of the device
- * @param livedata_idx the index of the livedata
- * @return livedata list pointer
- */
-nxpTfaLiveDataList_t *tfaContGetDevLiveDataList(nxpTfaContainer_t *cont, int dev_idx, int livedata_idx);
-
-/**
- * Check CRC for container
- * @param cont pointer to the tfaContainer
- * @return error value 0 on error
- */
-int tfaContCrcCheckContainer(nxpTfaContainer_t *cont);
-
-/**
- * Get the device list pointer
- * @param cnt pointer to the container struct
- * @param dev_idx the index of the device
- * @return pointer to device list
- */
-nxpTfaDeviceList_t *tfaContDevice(nxpTfaContainer_t *cnt, int dev_idx);
-
-/**
- * Return the pointer to the first profile in a list from the tfaContainer
- * @param cont pointer to the tfaContainer
- * @return pointer to first profile in profile list
- */
-nxpTfaProfileList_t *tfaContGet1stProfList(nxpTfaContainer_t *cont);
-
-/**
- * Return the pointer to the next profile in a list
- * @param prof is the pointer to the profile list
- * @return profile list pointer
- */
-nxpTfaProfileList_t* tfaContNextProfile(nxpTfaProfileList_t *prof);
-
-/**
- * Return the pointer to the first livedata in a list from the tfaContainer
- * @param cont pointer to the tfaContainer
- * @return pointer to first livedata in profile list
- */
-nxpTfaLiveDataList_t *tfaContGet1stLiveDataList(nxpTfaContainer_t *cont);
-
-/**
- * Return the pointer to the next livedata in a list
- * @param livedata_idx is the pointer to the livedata list
- * @return livedata list pointer
- */
-nxpTfaLiveDataList_t* tfaContNextLiveData(nxpTfaLiveDataList_t *livedata_idx);
-
-/**
- * Write a bit field
- * @param tfa the device struct pointer
- * @param bf bitfield to write
- * @return Tfa98xx_Error
- */
-enum Tfa98xx_Error tfaRunWriteBitfield(struct tfa_device *tfa, nxpTfaBitfield_t bf);
-
-/**
- * Write a parameter file to the device
- * @param tfa the device struct pointer
- * @param file filedescriptor pointer
- * @param vstep_idx index to vstep
- * @param vstep_msg_idx index to vstep message
- * @return Tfa98xx_Error
- */
-enum Tfa98xx_Error tfaContWriteFile(struct tfa_device *tfa, nxpTfaFileDsc_t *file, int vstep_idx, int vstep_msg_idx);
-
-/**
- * Get the max volume step associated with Nth profile for the Nth device
- * @param tfa the device struct pointer
- * @param prof_idx profile index
- * @return the number of vsteps
- */
-int tfacont_get_max_vstep(struct tfa_device *tfa, int prof_idx);
-
-/**
- * Get the file contents associated with the device or profile
- * Search within the device tree, if not found, search within the profile
- * tree. There can only be one type of file within profile or device.
- * @param tfa the device struct pointer
- * @param prof_idx I2C profile index in the device
- * @param type file type
- * @return 0 NULL if file type is not found
- * @return 1 file contents
- */
-nxpTfaFileDsc_t *tfacont_getfiledata(struct tfa_device *tfa, int prof_idx, enum nxpTfaHeaderType type);
-
-/**
- * Dump the contents of the file header
- * @param hdr pointer to file header data
- */
-void tfaContShowHeader(nxpTfaHeader_t *hdr);
-
-/**
- * Read a bit field
- * @param tfa the device struct pointer
- * @param bf bitfield to read out
- * @return Tfa98xx_Error
- */
-enum Tfa98xx_Error tfaRunReadBitfield(struct tfa_device *tfa, nxpTfaBitfield_t *bf);
-
-/**
- * Get hw feature bits from container file
- * @param tfa the device struct pointer
- * @param hw_feature_register pointer to where hw features are stored
- */
-void get_hw_features_from_cnt(struct tfa_device *tfa, int *hw_feature_register);
-
-/**
- * Get sw feature bits from container file
- * @param tfa the device struct pointer
- * @param sw_feature_register pointer to where sw features are stored
- */
-void get_sw_features_from_cnt(struct tfa_device *tfa, int sw_feature_register[2]);
-
-/**
- * Factory trimming for the Boost converter
- * check if there is a correction needed
- * @param tfa the device struct pointer
- */
-enum Tfa98xx_Error tfa98xx_factory_trimmer(struct tfa_device *tfa);
-
-/**
- * Search for filters settings and if found then write them to the device
- * @param tfa the device struct pointer
- * @param prof_idx profile to look in
- * @return Tfa98xx_Error
- */
-enum Tfa98xx_Error tfa_set_filters(struct tfa_device *tfa, int prof_idx);
-
-/**
- * Get the firmware version from the patch in the container file
- * @param tfa the device struct pointer
- * @return firmware version
- */
-int tfa_cnt_get_patch_version(struct tfa_device *tfa);
-
-int tfa_tib_dsp_msgmulti(struct tfa_device *tfa, int length, const char *buffer);
-
-#endif /* TFACONTAINER_H_ */
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef TFACONTAINER_H_
+#define TFACONTAINER_H_
+
+/* static limits */
+#define TFACONT_MAXDEVS (4) /* maximum nr of devices */
+#define TFACONT_MAXPROFS (16) /* maximum nr of profiles */
+
+#include "tfa98xx_parameters.h"
+
+/**
+* Pass the container buffer, initialize and allocate internal memory.
+*
+* @param cnt pointer to the start of the buffer holding the container file
+* @param length of the data in bytes
+* @return
+* - tfa_error_ok if normal
+* - tfa_error_container invalid container data
+* - tfa_error_bad_param invalid parameter
+*
+*/
+enum tfa_error tfa_load_cnt(void *cnt, int length);
+
+/**
+ * Return the descriptor string
+ * @param cnt pointer to the container struct
+ * @param dsc pointer to nxpTfa descriptor
+ * @return descriptor string
+ */
+char *tfaContGetString(nxpTfaContainer_t *cnt, nxpTfaDescPtr_t *dsc);
+
+/**
+ * Gets the string for the given command type number
+ * @param type number representing a command
+ * @return string of a command
+ */
+char *tfaContGetCommandString(uint32_t type);
+
+/**
+ * get the device type from the patch in this devicelist
+ * - find the patch file for this devidx
+ * - return the devid from the patch or 0 if not found
+ * @param cnt pointer to container file
+ * @param dev_idx device index
+ * @return descriptor string
+ */
+int tfa_cnt_get_devid(nxpTfaContainer_t *cnt, int dev_idx);
+
+/**
+ * Get the slave for the device if it exists.
+ * @param tfa the device struct pointer
+ * @param slave_addr the index of the device
+ * @return Tfa98xx_Error
+ */
+enum Tfa98xx_Error tfaContGetSlave(struct tfa_device *tfa, uint8_t *slave_addr);
+
+void tfaContSetSlave(uint8_t slave_addr);
+
+/**
+ * Get the index for a skave address.
+ * @param tfa the device struct pointer
+ * @return the device index
+ */
+int tfa_cont_get_idx(struct tfa_device *tfa);
+
+/**
+ * Write reg and bitfield items in the devicelist to the target.
+ * @param tfa the device struct pointer
+ * @return Tfa98xx_Error
+ */
+enum Tfa98xx_Error tfaContWriteRegsDev(struct tfa_device *tfa);
+
+/**
+ * Write reg and bitfield items in the profilelist to the target.
+ * @param tfa the device struct pointer
+ * @param prof_idx the profile index
+ * @return Tfa98xx_Error
+ */
+enum Tfa98xx_Error tfaContWriteRegsProf(struct tfa_device *tfa, int prof_idx);
+
+/**
+ * Write a patchfile in the devicelist to the target.
+ * @param tfa the device struct pointer
+ * @return Tfa98xx_Error
+ */
+enum Tfa98xx_Error tfaContWritePatch(struct tfa_device *tfa);
+
+/**
+ * Write all param files in the devicelist to the target.
+ * @param tfa the device struct pointer
+ * @return Tfa98xx_Error
+ */
+enum Tfa98xx_Error tfaContWriteFiles(struct tfa_device *tfa);
+
+/**
+ * Get sample rate from passed profile index
+ * @param tfa the device struct pointer
+ * @param prof_idx the index of the profile
+ * @return sample rate value
+ */
+unsigned int tfa98xx_get_profile_sr(struct tfa_device *tfa, unsigned int prof_idx);
+
+/**
+ * Get the device name string
+ * @param cnt the pointer to the container struct
+ * @param dev_idx the index of the device
+ * @return device name string or error string if not found
+ */
+char *tfaContDeviceName(nxpTfaContainer_t *cnt, int dev_idx);
+
+/**
+ * Get the application name from the container file application field
+ * @param tfa the device struct pointer
+ * @param name the input stringbuffer with size: sizeof(application field)+1
+ * @return actual string length
+ */
+int tfa_cnt_get_app_name(struct tfa_device *tfa, char *name);
+
+/**
+ * Get profile index of the calibration profile
+ * @param tfa the device struct pointer
+ * @return profile index, -2 if no calibration profile is found or -1 on error
+ */
+int tfaContGetCalProfile(struct tfa_device *tfa);
+
+/**
+ * Is the profile a tap profile ?
+ * @param tfa the device struct pointer
+ * @param prof_idx the index of the profile
+ * @return 1 if the profile is a tap profile or 0 if not
+ */
+int tfaContIsTapProfile(struct tfa_device *tfa, int prof_idx);
+
+/**
+ * Get the name of the profile at certain index for a device in the container file
+ * @param cnt the pointer to the container struct
+ * @param dev_idx the index of the device
+ * @param prof_idx the index of the profile
+ * @return profile name string or error string if not found
+ */
+char *tfaContProfileName(nxpTfaContainer_t *cnt, int dev_idx, int prof_idx);
+
+/**
+ * Process all items in the profilelist
+ * NOTE an error return during processing will leave the device muted
+ * @param tfa the device struct pointer
+ * @param prof_idx index of the profile
+ * @param vstep_idx index of the vstep
+ * @return Tfa98xx_Error
+ */
+enum Tfa98xx_Error tfaContWriteProfile(struct tfa_device *tfa, int prof_idx, int vstep_idx);
+
+/**
+ * Specify the speaker configurations (cmd id) (Left, right, both, none)
+ * @param dev_idx index of the device
+ * @param configuration name string of the configuration
+ */
+void tfa98xx_set_spkr_select(int dev_idx, char *configuration);
+
+enum Tfa98xx_Error tfa_cont_write_filterbank(struct tfa_device *tfa, nxpTfaFilter_t *filter);
+
+/**
+ * Write all param files in the profilelist to the target
+ * this is used during startup when maybe ACS is set
+ * @param tfa the device struct pointer
+ * @param prof_idx the index of the profile
+ * @param vstep_idx the index of the vstep
+ * @return Tfa98xx_Error
+ */
+enum Tfa98xx_Error tfaContWriteFilesProf(struct tfa_device *tfa, int prof_idx, int vstep_idx);
+enum Tfa98xx_Error tfaContWriteFilesVstep(struct tfa_device *tfa, int prof_idx, int vstep_idx);
+enum Tfa98xx_Error tfaContWriteDrcFile(struct tfa_device *tfa, int size, uint8_t data[]);
+
+/**
+ * Get the device list dsc from the tfaContainer
+ * @param cont pointer to the tfaContainer
+ * @param dev_idx the index of the device
+ * @return device list pointer
+ */
+nxpTfaDeviceList_t *tfaContGetDevList(nxpTfaContainer_t *cont, int dev_idx);
+
+/**
+ * Get the Nth profile for the Nth device
+ * @param cont pointer to the tfaContainer
+ * @param dev_idx the index of the device
+ * @param prof_idx the index of the profile
+ * @return profile list pointer
+ */
+nxpTfaProfileList_t *tfaContGetDevProfList(nxpTfaContainer_t *cont, int dev_idx, int prof_idx);
+
+/**
+ * Get the number of profiles for device from contaienr
+ * @param cont pointer to the tfaContainer
+ * @param dev_idx the index of the device
+ * @return device list pointer
+ */
+int tfa_cnt_get_dev_nprof(struct tfa_device *tfa);
+
+
+/**
+ * Get the Nth livedata for the Nth device
+ * @param cont pointer to the tfaContainer
+ * @param dev_idx the index of the device
+ * @param livedata_idx the index of the livedata
+ * @return livedata list pointer
+ */
+nxpTfaLiveDataList_t *tfaContGetDevLiveDataList(nxpTfaContainer_t *cont, int dev_idx, int livedata_idx);
+
+/**
+ * Check CRC for container
+ * @param cont pointer to the tfaContainer
+ * @return error value 0 on error
+ */
+int tfaContCrcCheckContainer(nxpTfaContainer_t *cont);
+
+/**
+ * Get the device list pointer
+ * @param cnt pointer to the container struct
+ * @param dev_idx the index of the device
+ * @return pointer to device list
+ */
+nxpTfaDeviceList_t *tfaContDevice(nxpTfaContainer_t *cnt, int dev_idx);
+
+/**
+ * Return the pointer to the first profile in a list from the tfaContainer
+ * @param cont pointer to the tfaContainer
+ * @return pointer to first profile in profile list
+ */
+nxpTfaProfileList_t *tfaContGet1stProfList(nxpTfaContainer_t *cont);
+
+/**
+ * Return the pointer to the next profile in a list
+ * @param prof is the pointer to the profile list
+ * @return profile list pointer
+ */
+nxpTfaProfileList_t *tfaContNextProfile(nxpTfaProfileList_t *prof);
+
+/**
+ * Return the pointer to the first livedata in a list from the tfaContainer
+ * @param cont pointer to the tfaContainer
+ * @return pointer to first livedata in profile list
+ */
+nxpTfaLiveDataList_t *tfaContGet1stLiveDataList(nxpTfaContainer_t *cont);
+
+/**
+ * Return the pointer to the next livedata in a list
+ * @param livedata_idx is the pointer to the livedata list
+ * @return livedata list pointer
+ */
+nxpTfaLiveDataList_t *tfaContNextLiveData(nxpTfaLiveDataList_t *livedata_idx);
+
+/**
+ * Write a bit field
+ * @param tfa the device struct pointer
+ * @param bf bitfield to write
+ * @return Tfa98xx_Error
+ */
+enum Tfa98xx_Error tfaRunWriteBitfield(struct tfa_device *tfa, nxpTfaBitfield_t bf);
+
+/**
+ * Write a parameter file to the device
+ * @param tfa the device struct pointer
+ * @param file filedescriptor pointer
+ * @param vstep_idx index to vstep
+ * @param vstep_msg_idx index to vstep message
+ * @return Tfa98xx_Error
+ */
+enum Tfa98xx_Error tfaContWriteFile(struct tfa_device *tfa, nxpTfaFileDsc_t *file, int vstep_idx, int vstep_msg_idx);
+
+/**
+ * Get the max volume step associated with Nth profile for the Nth device
+ * @param tfa the device struct pointer
+ * @param prof_idx profile index
+ * @return the number of vsteps
+ */
+int tfacont_get_max_vstep(struct tfa_device *tfa, int prof_idx);
+
+/**
+ * Get the file contents associated with the device or profile
+ * Search within the device tree, if not found, search within the profile
+ * tree. There can only be one type of file within profile or device.
+ * @param tfa the device struct pointer
+ * @param prof_idx I2C profile index in the device
+ * @param type file type
+ * @return 0 NULL if file type is not found
+ * @return 1 file contents
+ */
+nxpTfaFileDsc_t *tfacont_getfiledata(struct tfa_device *tfa, int prof_idx, enum nxpTfaHeaderType type);
+
+/**
+ * Dump the contents of the file header
+ * @param hdr pointer to file header data
+ */
+void tfaContShowHeader(nxpTfaHeader_t *hdr);
+
+/**
+ * Read a bit field
+ * @param tfa the device struct pointer
+ * @param bf bitfield to read out
+ * @return Tfa98xx_Error
+ */
+enum Tfa98xx_Error tfaRunReadBitfield(struct tfa_device *tfa, nxpTfaBitfield_t *bf);
+
+/**
+ * Get hw feature bits from container file
+ * @param tfa the device struct pointer
+ * @param hw_feature_register pointer to where hw features are stored
+ */
+void get_hw_features_from_cnt(struct tfa_device *tfa, int *hw_feature_register);
+
+/**
+ * Get sw feature bits from container file
+ * @param tfa the device struct pointer
+ * @param sw_feature_register pointer to where sw features are stored
+ */
+void get_sw_features_from_cnt(struct tfa_device *tfa, int sw_feature_register[2]);
+
+/**
+ * Factory trimming for the Boost converter
+ * check if there is a correction needed
+ * @param tfa the device struct pointer
+ */
+enum Tfa98xx_Error tfa98xx_factory_trimmer(struct tfa_device *tfa);
+
+/**
+ * Search for filters settings and if found then write them to the device
+ * @param tfa the device struct pointer
+ * @param prof_idx profile to look in
+ * @return Tfa98xx_Error
+ */
+enum Tfa98xx_Error tfa_set_filters(struct tfa_device *tfa, int prof_idx);
+
+/**
+ * Get the firmware version from the patch in the container file
+ * @param tfa the device struct pointer
+ * @return firmware version
+ */
+int tfa_cnt_get_patch_version(struct tfa_device *tfa);
+
+int tfa_tib_dsp_msgmulti(struct tfa_device *tfa, int length, const char *buffer);
+
+#endif /* TFACONTAINER_H_ */
diff --git a/inc/tfa_device.h b/sound/soc/codecs/tfa_device.h
similarity index 84%
rename from inc/tfa_device.h
rename to sound/soc/codecs/tfa_device.h
index fe87e24..18151d4 100644
--- a/inc/tfa_device.h
+++ b/sound/soc/codecs/tfa_device.h
@@ -1,291 +1,298 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-/**\file
- *
- * The tfa_device interface controls a single I2C device instance by
- * referencing to the device specific context provided by means of the
- * tfa_device structure pointer.
- * Multiple instances of tfa_device structures will be created and maintained
- * by the caller.
- *
- * The API is functionally grouped as:
- * - tfa_dev basic codec interface to probe, start/stop and control the device state
- * - access to internal MTP storage
- * - abstraction for interrupt bits and handling
- * - container reading support
- */
-#ifndef __TFA_DEVICE_H__
-#define __TFA_DEVICE_H__
-
-#include "config.h"
-
-struct tfa_device;
-
-/*
- * hw/sw feature bit settings in MTP
- */
-enum featureSupport {
- supportNotSet, /**< default means not set yet */
- supportNo, /**< no support */
- supportYes /**< supported */
-};
-/*
- * supported Digital Audio Interfaces bitmap
- */
-enum Tfa98xx_DAI {
- Tfa98xx_DAI_I2S = 0x01, /**< I2S only */
- Tfa98xx_DAI_TDM = 0x02, /**< TDM, I2S */
- Tfa98xx_DAI_PDM = 0x04, /**< PDM */
- };
-
-/*
- * device ops function structure
- */
-struct tfa_device_ops {
- enum Tfa98xx_Error(*dsp_msg)(struct tfa_device *tfa, int length, const char *buf);
- enum Tfa98xx_Error(*dsp_msg_read)(struct tfa_device *tfa, int length, unsigned char *bytes);
- enum Tfa98xx_Error(*reg_read)(struct tfa_device *tfa, unsigned char subaddress, unsigned short *value);
- enum Tfa98xx_Error(*reg_write)(struct tfa_device *tfa, unsigned char subaddress, unsigned short value);
- enum Tfa98xx_Error(*mem_read)(struct tfa_device *tfa, unsigned int start_offset, int num_words, int *pValues);
- enum Tfa98xx_Error(*mem_write)(struct tfa_device *tfa, unsigned short address, int value, int memtype);
-
- enum Tfa98xx_Error (*tfa_init)(struct tfa_device *tfa); /**< init typically for loading optimal settings */
- enum Tfa98xx_Error (*dsp_reset)(struct tfa_device *tfa, int state); /**< reset the coolflux dsp */
- enum Tfa98xx_Error (*dsp_system_stable)(struct tfa_device *tfa, int *ready); /**< ready when clocks are stable to allow DSP subsystem access */
- enum Tfa98xx_Error (*dsp_write_tables)(struct tfa_device *tfa, int sample_rate); /**< write the device/type specific delaytables */
- enum Tfa98xx_Error (*auto_copy_mtp_to_iic)(struct tfa_device *tfa); /**< Set auto_copy_mtp_to_iic */
- enum Tfa98xx_Error (*factory_trimmer)(struct tfa_device *tfa); /**< Factory trimming for the Boost converter */
- int (*set_swprof)(struct tfa_device *tfa, unsigned short new_value); /**< Set the sw profile in the struct and the hw register */
- int (*get_swprof)(struct tfa_device *tfa); /**< Get the sw profile from the hw register */
- int(*set_swvstep)(struct tfa_device *tfa, unsigned short new_value); /**< Set the sw vstep in the struct and the hw register */
- int(*get_swvstep)(struct tfa_device *tfa); /**< Get the sw vstep from the hw register */
- int(*get_mtpb)(struct tfa_device *tfa); /**< get status of MTB busy bit*/
- enum Tfa98xx_Error (*set_mute)(struct tfa_device *tfa, int mute); /**< set mute */
- enum Tfa98xx_Error (*faim_protect)(struct tfa_device *tfa, int state); /**< Protect FAIM from being corrupted */
- enum Tfa98xx_Error(*set_osc_powerdown)(struct tfa_device *tfa, int state); /**< Allow to change internal osc. gating settings */
- enum Tfa98xx_Error(*update_lpm)(struct tfa_device *tfa, int state); /**< Allow to change lowpowermode settings */
-};
-
-/**
- * Device states and modifier flags to allow a device/type independent fine
- * grained control of the internal state.\n
- * Values below 0x10 are referred to as base states which can be or-ed with
- * state modifiers, from 0x10 and higher.
- *
- */
-enum tfa_state {
- TFA_STATE_UNKNOWN, /**< unknown or invalid */
- TFA_STATE_POWERDOWN, /**< PLL in powerdown, Algo is up/warm */
- TFA_STATE_INIT_HW, /**< load I2C/PLL hardware setting (~wait2srcsettings) */
- TFA_STATE_INIT_CF, /**< coolflux HW access possible (~initcf) */
- TFA_STATE_INIT_FW, /**< DSP framework active (~patch loaded) */
- TFA_STATE_OPERATING, /**< Amp and Algo running */
- TFA_STATE_FAULT, /**< An alarm or error occurred */
- TFA_STATE_RESET, /**< I2C reset and ACS set */
- /* --sticky state modifiers-- */
- TFA_STATE_MUTE=0x10, /**< Algo & Amp mute */
- TFA_STATE_UNMUTE=0x20, /**< Algo & Amp unmute */
- TFA_STATE_CLOCK_ALWAYS=0x40, /**< PLL connect to internal oscillator */
- TFA_STATE_CLOCK_AUDIO=0x80, /**< PLL connect to audio clock (BCK/FS) */
- TFA_STATE_LOW_POWER=0x100, /**< lowest possible power state */
-};
-
-/**
- * This is the main tfa device context structure, it will carry all information
- * that is needed to handle a single I2C device instance.
- * All functions dealing with the device will need access to the fields herein.
- */
-struct tfa_device {
- int dev_idx; /**< device container index */
- int in_use;
- int buffer_size; /**< lowest level max buffer size */
- int has_msg; /**< support direct dsp messaging */
- unsigned char slave_address; /**< I2C slave address (not shifted) */
- unsigned short rev; /**< full revid of this device */
- unsigned char tfa_family; /**< tfa1/tfa2 */
- enum featureSupport supportDrc;
- enum featureSupport supportFramework;
- enum featureSupport support_saam;
- int sw_feature_bits[2]; /**< cached copy of sw feature bits */
- int hw_feature_bits; /**< cached copy of hw feature bits */
- int profile; /**< active profile */
- int vstep; /**< active vstep */
- unsigned char spkr_count;
- unsigned char spkr_select;
- unsigned char support_tcoef;/**< legacy tfa9887, will be removed */
- enum Tfa98xx_DAI daimap; /**< supported audio interface types */
- int mohm[3]; /**< speaker calibration values in milli ohms -1 is error */
- struct tfa_device_ops dev_ops;
- uint16_t interrupt_enable[3];
- uint16_t interrupt_status[3];
- int ext_dsp; /**< respond to external DSP: -1:none, 0:no_dsp, 1:cold, 2:warm */
- int bus; /* TODO fix ext_dsp and bus handling */
- int tfadsp_event; /**< enum tfadsp_event_en is for external registry */
- int verbose; /**< verbosity level for debug print output */
- enum tfa_state state; /**< last known state or-ed with optional state_modifier */
- struct nxpTfaContainer *cnt;/**< the loaded container file */
- struct nxpTfaVolumeStepRegisterInfo *p_regInfo; /**< remember vstep for partial updates */
- int partial_enable; /**< enable partial updates */
- void *data; /**< typically pointing to Linux driver structure owning this device */
- int convert_dsp32; /**< convert 24 bit DSP messages to 32 bit */
- int sync_iv_delay; /**< synchronize I/V delay at cold start */
- int is_probus_device; /**< probus device: device without internal DSP */
- int advance_keys_handling;
- int needs_reset; /**< add the reset trigger for SetAlgoParams and SetMBDrc commands */
- struct kmem_cache *cachep; /**< Memory allocator handle */
- char fw_itf_ver[4]; /* Firmware ITF version */
-};
-
-/**
- * The tfa_dev_probe is called before accessing any device accessing functions.
- * Access to the tfa device register 3 is attempted and will record the
- * returned id for further use. If no device responds the function will abort.
- * The recorded id will by used by the query functions to fill the remaining
- * relevant data fields of the device structure.
- * Data such as MTP features that requires device access will only be read when
- * explicitly called and the result will be then cached in the struct.
- *
- * A structure pointer passed to this device needs to refer to existing memory
- * space allocated by the caller.
- *
- * @param slave = I2C slave address of the target device (not shifted)
- * @param tfa struct = points to memory that holds the context for this device
- * instance
- *
- * @return
- * - 0 if the I2C device responded to a read of register address 3\n
- * when the device responds but with an unknown id a warning will be printed
- * - -1 if no response from the I2C device
- *
- */
-int tfa_dev_probe(int slave, struct tfa_device *tfa);
-
-/**
- * Start this instance at the profile and vstep as provided.
- * The profile and vstep will be loaded first in case the current value differs
- * from the requested values.
- * Note that this call will not change the mute state of the tfa, which means
- * that of this instance was called in muted state the caller will have to
- * unmute in order to get audio.
- *
- * @param tfa struct = pointer to context of this device instance
- * @param profile the selected profile to run
- * @param vstep the selected vstep to use
- * @return tfa_error enum
- */
-enum tfa_error tfa_dev_start(struct tfa_device *tfa, int profile, int vstep);
-
-
-/**
- * Stop audio for this instance as gracefully as possible.
- * Audio will be muted and the PLL will be shutdown together with any other
- * device/type specific settings needed to prevent audio artifacts or
- * workarounds.
- *
- * Note that this call will change state of the tfa to mute and powered down.
- *
- * @param tfa struct = pointer to context of this device instance
- * @return tfa_error enum
- */
-enum tfa_error tfa_dev_stop(struct tfa_device *tfa);
-
-/**
- * This interface allows a device/type independent fine grained control of the
- * internal state of the instance.
- * Whenever a base state is requested an attempt is made to actively bring the device
- * into this state. However this may depend on external conditions beyond control of
- * this software layer. Therefore in case the state cannot be set an erro will
- * be returned and the current state remains unchanged.
- * The base states, lower values below 0x10, are all mutually exclusive, they higher ones
- * can also function as a sticky modifier which means for example that operating
- * state could be in either muted or unmuted state. Or in case of init_cf it can be
- * internal clock (always) or external audio clock.
- * This function is intended to be used for device mute/unmute synchronization
- * when called from higher layers. Mostly internal calls will use this to control
- * the startup and profile transitions in a device/type independent way.
- *
- * @param tfa struct = pointer to context of this device instance
- * @param state struct = desired device state after function return
- * @return tfa_error enum
- */
-enum tfa_error tfa_dev_set_state(struct tfa_device *tfa, enum tfa_state state,int is_calibration);
-
-/**
- * Retrieve the current state of this instance in an active way.
- * The state field in tfa structure will reflect the result unless an error is
- * returned.
- * Note that the hardware state may change on external events an as such this
- * field should be treated as volatile.
- *
- * @param tfa struct = pointer to context of this device instance
- * @return tfa_error enum
- *
- */
-enum tfa_state tfa_dev_get_state(struct tfa_device *tfa);
-
-
-/*****************************************************************************/
-/*****************************************************************************/
-/**
- * MTP support functions
- */
-enum tfa_mtp {
- TFA_MTP_OTC, /**< */
- TFA_MTP_EX, /**< */
- TFA_MTP_RE25, /**< */
- TFA_MTP_RE25_PRIM, /**< */
- TFA_MTP_RE25_SEC, /**< */
- TFA_MTP_LOCK, /**< */
-};
-
-/**
- *
- */
-int tfa_dev_mtp_get(struct tfa_device *tfa, enum tfa_mtp item);
-
-/**
- *
- */
-enum tfa_error tfa_dev_mtp_set(struct tfa_device *tfa, enum tfa_mtp item, int value);
-
-
-//irq
-/* tfa2 interrupt support
- * !!! enum tfa9912_irq !!!*/
-/*
- * interrupt bit function to clear
- */
-int tfa_irq_clear(struct tfa_device *tfa, int bit);
-/*
- * return state of irq or -1 if illegal bit
- */
-int tfa_irq_get(struct tfa_device *tfa, int bit);
-/*
- * interrupt bit function that operates on the shadow regs in the handle
- */
-int tfa_irq_ena(struct tfa_device *tfa, int bit, int state);
-/*
- * interrupt bit function that sets the polarity
- */
-int tfa_irq_set_pol(struct tfa_device *tfa, int bit, int state);
-
-/*
- * mask interrupts by disabling them
- */
-int tfa_irq_mask(struct tfa_device *tfa);
-/*
- * unmask interrupts by enabling them again
- */
-int tfa_irq_unmask(struct tfa_device *tfa);
-//cnt read
-//debug?
-
-#endif /* __TFA_DEVICE_H__ */
-
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/**\file
+ *
+ * The tfa_device interface controls a single I2C device instance by
+ * referencing to the device specific context provided by means of the
+ * tfa_device structure pointer.
+ * Multiple instances of tfa_device structures will be created and maintained
+ * by the caller.
+ *
+ * The API is functionally grouped as:
+ * - tfa_dev basic codec interface to probe, start/stop and control the device
+ * - state access to internal MTP storage
+ * - abstraction for interrupt bits and handling
+ * - container reading support
+ */
+#ifndef __TFA_DEVICE_H__
+#define __TFA_DEVICE_H__
+
+#include "config.h"
+
+struct tfa_device;
+
+/*
+ * hw/sw feature bit settings in MTP
+ */
+enum featureSupport {
+ supportNotSet, /**< default means not set yet */
+ supportNo, /**< no support */
+ supportYes /**< supported */
+};
+/*
+ * supported Digital Audio Interfaces bitmap
+ */
+enum Tfa98xx_DAI {
+ Tfa98xx_DAI_I2S = 0x01, /**< I2S only */
+ Tfa98xx_DAI_TDM = 0x02, /**< TDM, I2S */
+ Tfa98xx_DAI_PDM = 0x04, /**< PDM */
+};
+
+/*
+ * device ops function structure
+ */
+struct tfa_device_ops {
+ enum Tfa98xx_Error(*dsp_msg)(struct tfa_device *tfa, int length,
+ const char *buf);
+ enum Tfa98xx_Error(*dsp_msg_read)(struct tfa_device *tfa, int length,
+ unsigned char *bytes);
+ enum Tfa98xx_Error(*reg_read)(struct tfa_device *tfa,
+ unsigned char subaddress, unsigned short *value);
+ enum Tfa98xx_Error(*reg_write)(struct tfa_device *tfa,
+ unsigned char subaddress, unsigned short value);
+ enum Tfa98xx_Error(*mem_read)(struct tfa_device *tfa,
+ unsigned int start_offset, int num_words, int *pValues);
+ enum Tfa98xx_Error(*mem_write)(struct tfa_device *tfa,
+ unsigned short address, int value, int memtype);
+
+ enum Tfa98xx_Error (*tfa_init)(struct tfa_device *tfa); /**< init typically for loading optimal settings */
+ enum Tfa98xx_Error (*dsp_reset)(struct tfa_device *tfa, int state); /**< reset the coolflux dsp */
+ enum Tfa98xx_Error (*dsp_system_stable)(struct tfa_device *tfa, int *ready); /**< ready when clocks are stable to allow DSP subsystem access */
+ enum Tfa98xx_Error (*dsp_write_tables)(struct tfa_device *tfa, int sample_rate); /**< write the device/type specific delaytables */
+ enum Tfa98xx_Error (*auto_copy_mtp_to_iic)(struct tfa_device *tfa); /**< Set auto_copy_mtp_to_iic */
+ enum Tfa98xx_Error (*factory_trimmer)(struct tfa_device *tfa); /**< Factory trimming for the Boost converter */
+ int (*set_swprof)(struct tfa_device *tfa, unsigned short new_value); /**< Set the sw profile in the struct and the hw register */
+ int (*get_swprof)(struct tfa_device *tfa); /**< Get the sw profile from the hw register */
+ int(*set_swvstep)(struct tfa_device *tfa, unsigned short new_value); /**< Set the sw vstep in the struct and the hw register */
+ int(*get_swvstep)(struct tfa_device *tfa); /**< Get the sw vstep from the hw register */
+ int(*get_mtpb)(struct tfa_device *tfa); /**< get status of MTB busy bit*/
+ enum Tfa98xx_Error (*set_mute)(struct tfa_device *tfa, int mute); /**< set mute */
+ enum Tfa98xx_Error (*faim_protect)(struct tfa_device *tfa, int state); /**< Protect FAIM from being corrupted */
+ enum Tfa98xx_Error(*set_osc_powerdown)(struct tfa_device *tfa, int state); /**< Allow to change internal osc. gating settings */
+ enum Tfa98xx_Error(*update_lpm)(struct tfa_device *tfa, int state); /**< Allow to change lowpowermode settings */
+};
+
+/**
+ * Device states and modifier flags to allow a device/type independent fine
+ * grained control of the internal state.\n
+ * Values below 0x10 are referred to as base states which can be or-ed with
+ * state modifiers, from 0x10 and higher.
+ *
+ */
+enum tfa_state {
+ TFA_STATE_UNKNOWN, /**< unknown or invalid */
+ TFA_STATE_POWERDOWN, /**< PLL in powerdown, Algo is up/warm */
+ TFA_STATE_INIT_HW, /**< load I2C/PLL hardware setting (~wait2srcsettings) */
+ TFA_STATE_INIT_CF, /**< coolflux HW access possible (~initcf) */
+ TFA_STATE_INIT_FW, /**< DSP framework active (~patch loaded) */
+ TFA_STATE_OPERATING, /**< Amp and Algo running */
+ TFA_STATE_FAULT, /**< An alarm or error occurred */
+ TFA_STATE_RESET, /**< I2C reset and ACS set */
+ /* --sticky state modifiers-- */
+ TFA_STATE_MUTE = 0x10, /**< Algo & Amp mute */
+ TFA_STATE_UNMUTE = 0x20, /**< Algo & Amp unmute */
+ TFA_STATE_CLOCK_ALWAYS = 0x40, /**< PLL connect to internal oscillator */
+ TFA_STATE_CLOCK_AUDIO = 0x80, /**< PLL connect to audio clock (BCK/FS) */
+ TFA_STATE_LOW_POWER = 0x100, /**< lowest possible power state */
+};
+
+/**
+ * This is the main tfa device context structure, it will carry all information
+ * that is needed to handle a single I2C device instance.
+ * All functions dealing with the device will need access to the fields herein.
+ */
+struct tfa_device {
+ int dev_idx; /**< device container index */
+ int in_use;
+ int buffer_size; /**< lowest level max buffer size */
+ int has_msg; /**< support direct dsp messaging */
+ unsigned char slave_address; /**< I2C slave address (not shifted) */
+ unsigned short rev; /**< full revid of this device */
+ unsigned char tfa_family; /**< tfa1/tfa2 */
+ enum featureSupport supportDrc;
+ enum featureSupport supportFramework;
+ enum featureSupport support_saam;
+ int sw_feature_bits[2]; /**< cached copy of sw feature bits */
+ int hw_feature_bits; /**< cached copy of hw feature bits */
+ int profile; /**< active profile */
+ int vstep; /**< active vstep */
+ unsigned char spkr_count;
+ unsigned char spkr_select;
+ unsigned char support_tcoef;/**< legacy tfa9887, will be removed */
+ enum Tfa98xx_DAI daimap; /**< supported audio interface types */
+ int mohm[3]; /**< speaker calibration values in milli ohms -1 is error */
+ struct tfa_device_ops dev_ops;
+ uint16_t interrupt_enable[3];
+ uint16_t interrupt_status[3];
+ int ext_dsp; /**< respond to external DSP: -1:none, 0:no_dsp, 1:cold, 2:warm */
+ int bus; /* TODO fix ext_dsp and bus handling */
+ int tfadsp_event; /**< enum tfadsp_event_en is for external registry */
+ int verbose; /**< verbosity level for debug print output */
+ enum tfa_state state; /**< last known state or-ed with optional state_modifier */
+ struct nxpTfaContainer *cnt;/**< the loaded container file */
+ struct nxpTfaVolumeStepRegisterInfo *p_regInfo; /**< remember vstep for partial updates */
+ int partial_enable; /**< enable partial updates */
+ void *data; /**< typically pointing to Linux driver structure owning this device */
+ int convert_dsp32; /**< convert 24 bit DSP messages to 32 bit */
+ int sync_iv_delay; /**< synchronize I/V delay at cold start */
+ int is_probus_device; /**< probus device: device without internal DSP */
+ int advance_keys_handling;
+ int needs_reset; /**< add the reset trigger for SetAlgoParams and SetMBDrc commands */
+ struct kmem_cache *cachep; /**< Memory allocator handle */
+ char fw_itf_ver[4]; /* Firmware ITF version */
+};
+
+/**
+ * The tfa_dev_probe is called before accessing any device accessing functions.
+ * Access to the tfa device register 3 is attempted and will record the
+ * returned id for further use. If no device responds the function will abort.
+ * The recorded id will by used by the query functions to fill the remaining
+ * relevant data fields of the device structure.
+ * Data such as MTP features that requires device access will only be read when
+ * explicitly called and the result will be then cached in the struct.
+ *
+ * A structure pointer passed to this device needs to refer to existing memory
+ * space allocated by the caller.
+ *
+ * @param slave = I2C slave address of the target device (not shifted)
+ * @param tfa struct = points to memory that holds the context for this device
+ * instance
+ *
+ * @return
+ * - 0 if the I2C device responded to a read of register address 3\n
+ * when the device responds but with an unknown id a warning will be printed
+ * - -1 if no response from the I2C device
+ *
+ */
+int tfa_dev_probe(int slave, struct tfa_device *tfa);
+
+/**
+ * Start this instance at the profile and vstep as provided.
+ * The profile and vstep will be loaded first in case the current value differs
+ * from the requested values.
+ * Note that this call will not change the mute state of the tfa, which means
+ * that of this instance was called in muted state the caller will have to
+ * unmute in order to get audio.
+ *
+ * @param tfa struct = pointer to context of this device instance
+ * @param profile the selected profile to run
+ * @param vstep the selected vstep to use
+ * @return tfa_error enum
+ */
+enum tfa_error tfa_dev_start(struct tfa_device *tfa, int profile, int vstep);
+
+
+/**
+ * Stop audio for this instance as gracefully as possible.
+ * Audio will be muted and the PLL will be shutdown together with any other
+ * device/type specific settings needed to prevent audio artifacts or
+ * workarounds.
+ *
+ * Note that this call will change state of the tfa to mute and powered down.
+ *
+ * @param tfa struct = pointer to context of this device instance
+ * @return tfa_error enum
+ */
+enum tfa_error tfa_dev_stop(struct tfa_device *tfa);
+
+/**
+ * This interface allows a device/type independent fine grained control of the
+ * internal state of the instance.
+ * Whenever a base state is requested an attempt is made to actively bring the device
+ * into this state. However this may depend on external conditions beyond control of
+ * this software layer. Therefore in case the state cannot be set an erro will
+ * be returned and the current state remains unchanged.
+ * The base states, lower values below 0x10, are all mutually exclusive, they higher ones
+ * can also function as a sticky modifier which means for example that operating
+ * state could be in either muted or unmuted state. Or in case of init_cf it can be
+ * internal clock (always) or external audio clock.
+ * This function is intended to be used for device mute/unmute synchronization
+ * when called from higher layers. Mostly internal calls will use this to control
+ * the startup and profile transitions in a device/type independent way.
+ *
+ * @param tfa struct = pointer to context of this device instance
+ * @param state struct = desired device state after function return
+ * @return tfa_error enum
+ */
+enum tfa_error tfa_dev_set_state(struct tfa_device *tfa, enum tfa_state state,
+ int is_calibration);
+
+/**
+ * Retrieve the current state of this instance in an active way.
+ * The state field in tfa structure will reflect the result unless an error is
+ * returned.
+ * Note that the hardware state may change on external events an as such this
+ * field should be treated as volatile.
+ *
+ * @param tfa struct = pointer to context of this device instance
+ * @return tfa_error enum
+ *
+ */
+enum tfa_state tfa_dev_get_state(struct tfa_device *tfa);
+
+
+/*****************************************************************************/
+/*****************************************************************************/
+/**
+ * MTP support functions
+ */
+enum tfa_mtp {
+ TFA_MTP_OTC, /**< */
+ TFA_MTP_EX, /**< */
+ TFA_MTP_RE25, /**< */
+ TFA_MTP_RE25_PRIM, /**< */
+ TFA_MTP_RE25_SEC, /**< */
+ TFA_MTP_LOCK, /**< */
+};
+
+/**
+ *
+ */
+int tfa_dev_mtp_get(struct tfa_device *tfa, enum tfa_mtp item);
+
+/**
+ *
+ */
+enum tfa_error tfa_dev_mtp_set(struct tfa_device *tfa, enum tfa_mtp item, int value);
+
+
+//irq
+/* tfa2 interrupt support
+ * !!! enum tfa9912_irq !!!*/
+/*
+ * interrupt bit function to clear
+ */
+int tfa_irq_clear(struct tfa_device *tfa, int bit);
+/*
+ * return state of irq or -1 if illegal bit
+ */
+int tfa_irq_get(struct tfa_device *tfa, int bit);
+/*
+ * interrupt bit function that operates on the shadow regs in the handle
+ */
+int tfa_irq_ena(struct tfa_device *tfa, int bit, int state);
+/*
+ * interrupt bit function that sets the polarity
+ */
+int tfa_irq_set_pol(struct tfa_device *tfa, int bit, int state);
+
+/*
+ * mask interrupts by disabling them
+ */
+int tfa_irq_mask(struct tfa_device *tfa);
+/*
+ * unmask interrupts by enabling them again
+ */
+int tfa_irq_unmask(struct tfa_device *tfa);
+//cnt read
+//debug?
+
+#endif /* __TFA_DEVICE_H__ */
+
diff --git a/src/tfa_dsp.c b/sound/soc/codecs/tfa_dsp.c
similarity index 92%
rename from src/tfa_dsp.c
rename to sound/soc/codecs/tfa_dsp.c
index c2ba271..9530d35 100644
--- a/src/tfa_dsp.c
+++ b/sound/soc/codecs/tfa_dsp.c
@@ -1,4139 +1,4142 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include "dbgprint.h"
-#include "tfa_container.h"
-#include "tfa.h"
-#include "tfa98xx_tfafieldnames.h"
-#include "tfa_internal.h"
-
- /* handle macro for bitfield */
-#define TFA_MK_BF(reg, pos, len) ((reg<<8)|(pos<<4)|(len-1))
-
-/* abstract family for register */
-#define FAM_TFA98XX_CF_CONTROLS (TFA_FAM(tfa,RST) >> 8)
-#define FAM_TFA98XX_CF_MEM (TFA_FAM(tfa,MEMA)>> 8)
-#define FAM_TFA98XX_MTP0 (TFA_FAM(tfa,MTPOTC) >> 8)
-#define FAM_TFA98xx_INT_EN (TFA_FAM(tfa,INTENVDDS) >> 8)
-
-#define CF_STATUS_I2C_CMD_ACK 0x01
-
-/* Defines below are used for irq function (this removed the genregs include) */
-#define TFA98XX_INTERRUPT_ENABLE_REG1 0x48
-#define TFA98XX_INTERRUPT_IN_REG1 0x44
-#define TFA98XX_INTERRUPT_OUT_REG1 0x40
-#define TFA98XX_STATUS_POLARITY_REG1 0x4c
-#define TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_MSK 0x2
-#define TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC_MSK 0x1
-#define TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_POS 1
-#define TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC_POS 0
-
-void tfanone_ops(struct tfa_device_ops *ops);
-void tfa9872_ops(struct tfa_device_ops *ops);
-void tfa9874_ops(struct tfa_device_ops *ops);
-void tfa9878_ops(struct tfa_device_ops *ops);
-void tfa9912_ops(struct tfa_device_ops *ops);
-void tfa9888_ops(struct tfa_device_ops *ops);
-void tfa9891_ops(struct tfa_device_ops *ops);
-void tfa9897_ops(struct tfa_device_ops *ops);
-void tfa9896_ops(struct tfa_device_ops *ops);
-void tfa9890_ops(struct tfa_device_ops *ops);
-void tfa9895_ops(struct tfa_device_ops *ops);
-void tfa9894_ops(struct tfa_device_ops *ops);
-
-#ifndef MIN
-#define MIN(A,B) (A<B?A:B)
-#endif
-
-/* retry values */
-#define CFSTABLE_TRIES 10
-#define AMPOFFWAIT_TRIES 50
-#define MTPBWAIT_TRIES 50
-#define MTPEX_WAIT_NTRIES 50
-
-/* calibration done executed */
-#define TFA_MTPEX_POS TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_POS /**/
-
-int tfa_get_calibration_info(struct tfa_device *tfa, int channel)
-{
- return tfa->mohm[channel];
-}
-
-/* return sign extended tap pattern */
-int tfa_get_tap_pattern(struct tfa_device *tfa)
-{
- int value = tfa_get_bf(tfa, TFA9912_BF_CFTAPPAT);
- int bitshift;
- uint8_t field_len = 1 + (TFA9912_BF_CFTAPPAT & 0x0f); /* length of bitfield */
-
- bitshift = 8 * sizeof(int) - field_len;
- /* signextend */
- value = (value << bitshift) >> bitshift;
-
- return value;
-}
-/*
- * interrupt bit function to clear
- */
-int tfa_irq_clear(struct tfa_device *tfa, enum tfa9912_irq bit)
-{
- unsigned char reg;
-
- /* make bitfield enum */
- if (bit == tfa9912_irq_all) {
- /* operate on all bits */
- for (reg = TFA98XX_INTERRUPT_IN_REG1; reg < TFA98XX_INTERRUPT_IN_REG1 + 3; reg++)
- reg_write(tfa, reg, 0xffff); /* all bits */
- }
- else if (bit < tfa9912_irq_max) {
- reg = (unsigned char)(TFA98XX_INTERRUPT_IN_REG1 + (bit >> 4));
- reg_write(tfa, reg, 1 << (bit & 0x0f)); /* only this bit */
- }
- else
- return -1;
-
- return 0;
-}
-/*
- * return state of irq or -1 if illegal bit
- */
-int tfa_irq_get(struct tfa_device *tfa, enum tfa9912_irq bit)
-{
- uint16_t value;
- int reg, mask;
-
- if (bit < tfa9912_irq_max) {
- /* only this bit */
- reg = TFA98XX_INTERRUPT_OUT_REG1 + (bit >> 4);
- mask = 1 << (bit & 0x0f);
- reg_read(tfa, (unsigned char)reg, &value);
- }
- else
- return -1;
-
- return (value & mask) != 0;
-}
-/*
- * interrupt bit function that operates on the shadow regs in the handle
- */
-
-int tfa_irq_ena(struct tfa_device *tfa, enum tfa9912_irq bit, int state)
-{
- uint16_t value, new_value;
- int reg = 0, mask;
- /* */
- if (bit == tfa9912_irq_all) {
- /* operate on all bits */
- for (reg = TFA98XX_INTERRUPT_ENABLE_REG1; reg <= TFA98XX_INTERRUPT_ENABLE_REG1 + tfa9912_irq_max / 16; reg++) {
- reg_write(tfa, (unsigned char)reg, state ? 0xffff : 0); /* all bits */
- tfa->interrupt_enable[reg - TFA98XX_INTERRUPT_ENABLE_REG1] = state ? 0xffff : 0; /* all bits */
- }
- }
- else if (bit < tfa9912_irq_max) {
- /* only this bit */
- reg = TFA98XX_INTERRUPT_ENABLE_REG1 + (bit >> 4);
- mask = 1 << (bit & 0x0f);
- reg_read(tfa, (unsigned char)reg, &value);
- if (state) //set
- new_value = (uint16_t)(value | mask);
- else // clear
- new_value = value & ~mask;
- if (new_value != value) {
- reg_write(tfa, (unsigned char)reg, new_value); /* only this bit */
- tfa->interrupt_enable[reg - TFA98XX_INTERRUPT_ENABLE_REG1] = new_value;
- }
- }
- else
- return -1;
-
- return 0;
-}
-
-/*
- * mask interrupts by disabling them
- */
-int tfa_irq_mask(struct tfa_device *tfa)
-{
- int reg;
-
- /* operate on all bits */
- for (reg = TFA98XX_INTERRUPT_ENABLE_REG1; reg <= TFA98XX_INTERRUPT_ENABLE_REG1 + tfa9912_irq_max / 16; reg++)
- reg_write(tfa, (unsigned char)reg, 0);
-
- return 0;
-}
-
-/*
- * unmask interrupts by enabling them again
- */
-int tfa_irq_unmask(struct tfa_device *tfa)
-{
- int reg;
-
- /* operate on all bits */
- for (reg = TFA98XX_INTERRUPT_ENABLE_REG1; reg <= TFA98XX_INTERRUPT_ENABLE_REG1 + tfa9912_irq_max / 16; reg++)
- reg_write(tfa, (unsigned char)reg, tfa->interrupt_enable[reg - TFA98XX_INTERRUPT_ENABLE_REG1]);
-
- return 0;
-}
-
-/*
- * interrupt bit function that sets the polarity
- */
-
-int tfa_irq_set_pol(struct tfa_device *tfa, enum tfa9912_irq bit, int state)
-{
- uint16_t value, new_value;
- int reg = 0, mask;
-
- if (bit == tfa9912_irq_all) {
- /* operate on all bits */
- for (reg = TFA98XX_STATUS_POLARITY_REG1; reg <= TFA98XX_STATUS_POLARITY_REG1 + tfa9912_irq_max / 16; reg++) {
- reg_write(tfa, (unsigned char)reg, state ? 0xffff : 0); /* all bits */
- }
- }
- else if (bit < tfa9912_irq_max) {
- /* only this bit */
- reg = TFA98XX_STATUS_POLARITY_REG1 + (bit >> 4);
- mask = 1 << (bit & 0x0f);
- reg_read(tfa, (unsigned char)reg, &value);
- if (state) /* Active High */
- new_value = (uint16_t)(value | mask);
- else /* Active Low */
- new_value = value & ~mask;
- if (new_value != value) {
- reg_write(tfa, (unsigned char)reg, new_value); /* only this bit */
- }
- }
- else
- return -1;
-
- return 0;
-}
-
-/*
- * set device info and register device ops
- */
-void tfa_set_query_info(struct tfa_device *tfa)
-{
- /* invalidate device struct cached values */
- tfa->hw_feature_bits = -1;
- tfa->sw_feature_bits[0] = -1;
- tfa->sw_feature_bits[1] = -1;
- tfa->profile = -1;
- tfa->vstep = -1;
- /* defaults */
- tfa->is_probus_device = 0;
- tfa->advance_keys_handling = 0; /*artf65038*/
- tfa->tfa_family = 1;
- tfa->daimap = Tfa98xx_DAI_I2S; /* all others */
- tfa->spkr_count = 1;
- tfa->spkr_select = 0;
- tfa->support_tcoef = supportYes;
- tfa->supportDrc = supportNotSet;
- tfa->support_saam = supportNotSet;
- tfa->ext_dsp = -1; /* respond to external DSP: -1:none, 0:no_dsp, 1:cold, 2:warm */
- tfa->bus = 0;
- tfa->partial_enable = 0;
- tfa->convert_dsp32 = 0;
- tfa->sync_iv_delay = 0;
-
- /* TODO use the getfeatures() for retrieving the features [artf103523]
- tfa->supportDrc = supportNotSet;*/
-
- switch (tfa->rev & 0xff) {
- case 0: /* tfanone : non-i2c external DSP device */
- /* e.g. qc adsp */
- tfa->supportDrc = supportYes;
- tfa->tfa_family = 0;
- tfa->spkr_count = 0;
- tfa->daimap = 0;
- tfanone_ops(&tfa->dev_ops); /* register device operations via tfa hal*/
- tfa->bus = 1;
- break;
- case 0x72:
- /* tfa9872 */
- tfa->supportDrc = supportYes;
- tfa->tfa_family = 2;
- tfa->spkr_count = 1;
- tfa->is_probus_device = 1;
- tfa->daimap = Tfa98xx_DAI_TDM;
- tfa9872_ops(&tfa->dev_ops); /* register device operations */
- break;
- case 0x74:
- /* tfa9874 */
- tfa->supportDrc = supportYes;
- tfa->tfa_family = 2;
- tfa->spkr_count = 1;
- tfa->is_probus_device = 1;
- tfa->daimap = Tfa98xx_DAI_TDM;
- tfa9874_ops(&tfa->dev_ops); /* register device operations */
- break;
- case 0x78:
- /* tfa9878 */
- tfa->supportDrc = supportYes;
- tfa->tfa_family = 2;
- tfa->spkr_count = 1;
- tfa->is_probus_device = 1;
- tfa->advance_keys_handling = 1; /*artf65038*/
- tfa->daimap = Tfa98xx_DAI_TDM;
- tfa9878_ops(&tfa->dev_ops); /* register device operations */
- break;
- case 0x88:
- /* tfa9888 */
- tfa->tfa_family = 2;
- tfa->spkr_count = 2;
- tfa->daimap = Tfa98xx_DAI_TDM;
- tfa9888_ops(&tfa->dev_ops); /* register device operations */
- break;
- case 0x97:
- /* tfa9897 */
- tfa->supportDrc = supportNo;
- tfa->spkr_count = 1;
- tfa->daimap = Tfa98xx_DAI_TDM;
- tfa9897_ops(&tfa->dev_ops); /* register device operations */
- break;
- case 0x96:
- /* tfa9896 */
- tfa->supportDrc = supportNo;
- tfa->spkr_count = 1;
- tfa->daimap = Tfa98xx_DAI_TDM;
- tfa9896_ops(&tfa->dev_ops); /* register device operations */
- break;
- case 0x92:
- /* tfa9891 */
- tfa->spkr_count = 1;
- tfa->daimap = (Tfa98xx_DAI_PDM | Tfa98xx_DAI_I2S);
- tfa9891_ops(&tfa->dev_ops); /* register device operations */
- break;
- case 0x91:
- /* tfa9890B */
- tfa->spkr_count = 1;
- tfa->daimap = (Tfa98xx_DAI_PDM | Tfa98xx_DAI_I2S);
- break;
- case 0x80:
- case 0x81:
- /* tfa9890 */
- tfa->spkr_count = 1;
- tfa->daimap = Tfa98xx_DAI_I2S;
- tfa->supportDrc = supportNo;
- tfa->supportFramework = supportNo;
- tfa9890_ops(&tfa->dev_ops); /* register device operations */
- break;
- case 0x12:
- /* tfa9895 */
- tfa->spkr_count = 1;
- tfa->daimap = Tfa98xx_DAI_I2S;
- tfa9895_ops(&tfa->dev_ops); /* register device operations */
- break;
- case 0x13:
- /* tfa9912 */
- tfa->tfa_family = 2;
- tfa->spkr_count = 1;
- tfa->daimap = Tfa98xx_DAI_TDM;
- tfa9912_ops(&tfa->dev_ops); /* register device operations */
- break;
- case 0x94:
- /* tfa9894 */
- tfa->tfa_family = 2;
- tfa->spkr_count = 1;
- tfa->daimap = Tfa98xx_DAI_TDM;
- tfa9894_ops(&tfa->dev_ops); /* register device operations */
- break;
-
- default:
- pr_err("unknown device type : 0x%02x\n", tfa->rev);
- _ASSERT(0);
- break;
- }
-}
-
-/*
- * lookup the device type and return the family type
- */
-int tfa98xx_dev2family(int dev_type)
-{
- /* only look at the die ID part (lsb byte) */
- switch (dev_type & 0xff) {
- case 0x12:
- case 0x80:
- case 0x81:
- case 0x91:
- case 0x92:
- case 0x97:
- case 0x96:
- return 1;
- case 0x88:
- case 0x72:
- case 0x13:
- case 0x74:
- case 0x94:
- return 2;
- case 0x50:
- return 3;
- default:
- return 0;
- }
-}
-
-/*
- * return the target address for the filter on this device
-
- filter_index:
- [0..9] reserved for EQ (not deployed, calc. is available)
- [10..12] anti-alias filter
- [13] integrator filter
-
- */
-enum Tfa98xx_DMEM tfa98xx_filter_mem(struct tfa_device *tfa, int filter_index, unsigned short *address, int channel)
-{
- enum Tfa98xx_DMEM dmem = -1;
- int idx;
- unsigned short bq_table[7][4] = {
- /* index: 10, 11, 12, 13 */
- {346,351,356,288}, //87 BRA_MAX_MRA4-2_7.00
- {346,351,356,288}, //90 BRA_MAX_MRA6_9.02
- {467,472,477,409}, //95 BRA_MAX_MRA7_10.02
- {406,411,416,348}, //97 BRA_MAX_MRA9_12.01
- {467,472,477,409}, //91 BRA_MAX_MRAA_13.02
- {8832, 8837, 8842, 8847}, //88 part1
- {8853, 8858, 8863, 8868} //88 part2
- /* Since the 88 is stereo we have 2 parts.
- * Every index has 5 values except index 13 this one has 6 values
- */
- };
-
- if ((10 <= filter_index) && (filter_index <= 13)) {
- dmem = Tfa98xx_DMEM_YMEM; /* for all devices */
- idx = filter_index - 10;
-
- switch (tfa->rev & 0xff) { // only compare lower byte
- case 0x12:
- *address = bq_table[2][idx];
- break;
- case 0x97:
- *address = bq_table[3][idx];
- break;
- case 0x96:
- *address = bq_table[3][idx];
- break;
- case 0x80:
- case 0x81: // for the RAM version
- case 0x91:
- *address = bq_table[1][idx];
- break;
- case 0x92:
- *address = bq_table[4][idx];
- break;
- case 0x88:
- /* Channel 1 = primary, 2 = secondary */
- if (channel == 1)
- *address = bq_table[5][idx];
- else
- *address = bq_table[6][idx];
- break;
- case 0x72:
- case 0x74:
- case 0x13:
- default:
- /* unsupported case, possibly intermediate version */
- return -1;
- _ASSERT(0);
- }
- }
- return dmem;
-}
-
-/************************ query functions ********************************************************/
-/**
-* return revision
-* Used by the LTT
-*/
-void tfa98xx_rev(int *major, int *minor, int *revision)
-{
- char version_str[] = TFA98XX_API_REV_STR;
- sscanf(version_str, "v%d.%d.%d", major, minor, revision);
-}
-
-/**
- * tfa_supported_speakers
- * returns the number of the supported speaker count
- */
-enum Tfa98xx_Error tfa_supported_speakers(struct tfa_device *tfa, int* spkr_count)
-{
- if (tfa->in_use == 0)
- return Tfa98xx_Error_NotOpen;
- else
- *spkr_count = tfa->spkr_count;
-
- return Tfa98xx_Error_Ok;
-}
-
-/*
- * tfa98xx_supported_saam
- * returns the supportedspeaker as microphone feature
- */
-enum Tfa98xx_Error tfa98xx_supported_saam(struct tfa_device *tfa, enum Tfa98xx_saam *saam)
-{
- int features;
- enum Tfa98xx_Error error;
-
- if (tfa->support_saam == supportNotSet) {
- error = tfa98xx_dsp_get_hw_feature_bits(tfa, &features);
- if (error != Tfa98xx_Error_Ok)
- return error;
- tfa->support_saam =
- (features & 0x8000) ? supportYes : supportNo; /* SAAM is bit15 */
- }
- *saam = tfa->support_saam == supportYes ? Tfa98xx_saam : Tfa98xx_saam_none;
-
- return Tfa98xx_Error_Ok;
-}
-
-/*
- * tfa98xx_compare_features
- * Obtains features_from_MTP and features_from_cnt
- */
-enum Tfa98xx_Error tfa98xx_compare_features(struct tfa_device *tfa, int features_from_MTP[3], int features_from_cnt[3])
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- uint32_t value;
- uint16_t mtpbf;
- unsigned char bytes[3 * 2];
- int status;
-
- tfa98xx_dsp_system_stable(tfa, &status);
- if (!status)
- return Tfa98xx_Error_NoClock; // Only test when we have a clock.
-
- /* Set proper MTP location per device: */
- if (tfa->tfa_family == 1) {
- mtpbf = 0x850f; /* MTP5 for tfa1,16 bits */
- }
- else {
- mtpbf = 0xf907; /* MTP9 for tfa2, 8 bits */
- }
-
- /* Read HW features from MTP: */
- value = tfa_read_reg(tfa, mtpbf) & 0xffff;
- features_from_MTP[0] = tfa->hw_feature_bits = value;
-
- /* Read SW features: */
- error = tfa_dsp_cmd_id_write_read(tfa, MODULE_FRAMEWORK, FW_PAR_ID_GET_FEATURE_INFO, sizeof(bytes), bytes);
- if (error != Tfa98xx_Error_Ok)
- return error; /* old ROM code may respond with Tfa98xx_Error_RpcParamId */
-
- tfa98xx_convert_bytes2data(sizeof(bytes), bytes, &features_from_MTP[1]);
-
- /* check if feature bits from MTP match feature bits from cnt file: */
- get_hw_features_from_cnt(tfa, &features_from_cnt[0]);
- get_sw_features_from_cnt(tfa, &features_from_cnt[1]);
-
- return error;
-}
-
-/********************************* device specific ops ************************************************/
-/* the wrapper for DspReset, in case of full */
-enum Tfa98xx_Error tfa98xx_dsp_reset(struct tfa_device *tfa, int state)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
-
- error = (tfa->dev_ops.dsp_reset)(tfa, state);
-
- return error;
-}
-
-/* the ops wrapper for tfa98xx_dsp_SystemStable */
-enum Tfa98xx_Error tfa98xx_dsp_system_stable(struct tfa_device *tfa, int *ready)
-{
- return (tfa->dev_ops.dsp_system_stable)(tfa, ready);
-}
-
-/* the ops wrapper for tfa98xx_dsp_system_stable */
-enum Tfa98xx_Error tfa98xx_auto_copy_mtp_to_iic(struct tfa_device *tfa)
-{
- return (tfa->dev_ops.auto_copy_mtp_to_iic)(tfa);
-}
-
-/* the ops wrapper for tfa98xx_faim_protect */
-enum Tfa98xx_Error tfa98xx_faim_protect(struct tfa_device *tfa, int state)
-{
- return (tfa->dev_ops.faim_protect)(tfa, state);
-}
-
-/*
- * bring the device into a state similar to reset
- */
-enum Tfa98xx_Error tfa98xx_init(struct tfa_device *tfa)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- uint16_t value = 0;
-
- /* reset all i2C registers to default
- * Write the register directly to avoid the read in the bitfield function.
- * The I2CR bit may overwrite the full register because it is reset anyway.
- * This will save a reg read transaction.
- */
- TFA_SET_BF_VALUE(tfa, I2CR, 1, &value);
- TFA_WRITE_REG(tfa, I2CR, value);
-
- /* Put DSP in reset */
- tfa98xx_dsp_reset(tfa, 1); /* in pair of tfaRunStartDSP() */
-
- /* some other registers must be set for optimal amplifier behaviour
- * This is implemented in a file specific for the type number
- */
- if (tfa->dev_ops.tfa_init)
- error = (tfa->dev_ops.tfa_init)(tfa);
-
- return error;
-}
-
-enum Tfa98xx_Error tfa98xx_dsp_write_tables(struct tfa_device *tfa, int sample_rate)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
-
- error = (tfa->dev_ops.dsp_write_tables)(tfa, sample_rate);
-
- return error;
-}
-
-/** Set internal oscillator into power down mode.
-*
-* @param[in] tfa device description structure
-* @param[in] state new state 0 - oscillator is on, 1 oscillator is off.
-*
-* @return Tfa98xx_Error_Ok when successfull, error otherwise.
-*/
-enum Tfa98xx_Error tfa98xx_set_osc_powerdown(struct tfa_device *tfa, int state)
-{
- if (tfa->dev_ops.set_osc_powerdown) {
- return tfa->dev_ops.set_osc_powerdown(tfa, state);
- }
-
- return Tfa98xx_Error_Not_Implemented;
-}
-
-/** update low power mode of the device.
-*
-* @param[in] tfa device description structure
-* @param[in] state new state 0 - LPMODE is on, 1 LPMODE is off.
-*
-* @return Tfa98xx_Error_Ok when successfull, error otherwise.
-*/
-enum Tfa98xx_Error tfa98xx_update_lpm(struct tfa_device *tfa, int state)
-{
- if (tfa->dev_ops.update_lpm) {
- return tfa->dev_ops.update_lpm(tfa, state);
- }
-
- return Tfa98xx_Error_Not_Implemented;
-}
-/** Check presence of powerswitch=1 in configuration and optimal setting.
-*
-* @param[in] tfa device description structure
-*
-* @return -1 when error, 0 or 1 depends on switch settings.
-*/
-int tfa98xx_powerswitch_is_enabled(struct tfa_device *tfa)
-{
- uint16_t value;
- enum Tfa98xx_Error ret;
-
- if (((tfa->rev & 0xff) == 0x13) || ((tfa->rev & 0xff) == 0x88)) {
- ret = reg_read(tfa, 0xc6, &value);
- if (ret != Tfa98xx_Error_Ok) {
- return -1;
- }
- /* PLMA5539: Check actual value of powerswitch. TODO: regmap v1.40 should make this bit public. */
-
- return (int)(value & (1u << 6));
- }
-
- return 1;
-}
-
-/********************* new tfa2 *********************************************************************/
-/* newly added messaging for tfa2 tfa1? */
-enum Tfa98xx_Error tfa98xx_dsp_get_memory(struct tfa_device *tfa, int memoryType,
- int offset, int length, unsigned char bytes[])
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- char msg[4 * 3];
- int nr = 0;
-
- msg[nr++] = 8;
- msg[nr++] = MODULE_FRAMEWORK + 128;
- msg[nr++] = FW_PAR_ID_GET_MEMORY;
-
- msg[nr++] = 0;
- msg[nr++] = 0;
- msg[nr++] = (char)memoryType;
-
- msg[nr++] = 0;
- msg[nr++] = (offset >> 8) & 0xff;
- msg[nr++] = offset & 0xff;
-
- msg[nr++] = 0;
- msg[nr++] = (length >> 8) & 0xff;
- msg[nr++] = length & 0xff;
-
- /* send msg */
- error = dsp_msg(tfa, nr, (char *)msg);
-
- if (error != Tfa98xx_Error_Ok)
- return error;
-
- /* read the data from the device (length * 3) */
- error = dsp_msg_read(tfa, length * 3, bytes);
-
- return error;
-}
-
-enum Tfa98xx_Error tfa98xx_dsp_set_memory(struct tfa_device *tfa, int memoryType,
- int offset, int length, int value)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- int nr = 0;
- char msg[5 * 3];
-
- msg[nr++] = 8;
- msg[nr++] = MODULE_FRAMEWORK + 128;
- msg[nr++] = FW_PAR_ID_SET_MEMORY;
-
- msg[nr++] = 0;
- msg[nr++] = 0;
- msg[nr++] = (char)memoryType;
-
- msg[nr++] = 0;
- msg[nr++] = (offset >> 8) & 0xff;
- msg[nr++] = offset & 0xff;
-
- msg[nr++] = 0;
- msg[nr++] = (length >> 8) & 0xff;
- msg[nr++] = length & 0xff;
-
- msg[nr++] = (value >> 16) & 0xff;
- msg[nr++] = (value >> 8) & 0xff;
- msg[nr++] = value & 0xff;
-
- /* send msg */
- error = dsp_msg(tfa, nr, (char *)msg);
-
- return error;
-}
-/****************************** calibration support **************************/
-/*
- * get/set the mtp with user controllable values
- *
- * check if the relevant clocks are available
- */
-enum Tfa98xx_Error tfa98xx_get_mtp(struct tfa_device *tfa, uint16_t *value)
-{
- int status;
- int result;
-
- /* not possible if PLL in powerdown */
- if (TFA_GET_BF(tfa, PWDN)) {
- pr_debug("PLL in powerdown\n");
- return Tfa98xx_Error_NoClock;
- }
-
- tfa98xx_dsp_system_stable(tfa, &status);
- if (status == 0) {
- pr_debug("PLL not running\n");
- return Tfa98xx_Error_NoClock;
- }
-
- result = TFA_READ_REG(tfa, MTP0);
- if (result < 0) {
- return -result;
- }
- *value = (uint16_t)result;
-
- return Tfa98xx_Error_Ok;
-}
-
-/*
- * lock or unlock KEY2
- * lock = 1 will lock
- * lock = 0 will unlock
- *
- * note that on return all the hidden key will be off
- */
-void tfa98xx_key2(struct tfa_device *tfa, int lock)
-{
- /* unhide lock registers */
- reg_write(tfa, (tfa->tfa_family == 1) ? 0x40 : 0x0F, 0x5A6B);
- /* lock/unlock key2 MTPK */
- TFA_WRITE_REG(tfa, MTPKEY2, lock ? 0 : 0x5A);
- /* unhide lock registers */
- if (!tfa->advance_keys_handling) /*artf65038*/
- reg_write(tfa, (tfa->tfa_family == 1) ? 0x40 : 0x0F, 0);
-}
-void tfa2_manual_mtp_cpy(struct tfa_device *tfa, uint16_t reg_row_to_keep, uint16_t reg_row_to_set, uint8_t row)///MCH_TO_TEST
-{
- uint16_t value;
- int loop = 0;
- enum Tfa98xx_Error error;
- /* Assure FAIM is enabled (enable it when neccesery) */
- if (tfa->is_probus_device)
- {
- error = tfa98xx_faim_protect(tfa, 1);
- if (tfa->verbose) {
- pr_debug("FAIM enabled (err:%d).\n", error);
- }
- }
- reg_read(tfa, (unsigned char)reg_row_to_keep, &value);
- if (!row)
- {
- reg_write(tfa, 0xA7, value);
- reg_write(tfa, 0xA8, reg_row_to_set);
- }
- else
- {
- reg_write(tfa, 0xA7, reg_row_to_set);
- reg_write(tfa, 0xA8, value);
- }
- reg_write(tfa, 0xA3, 0x10 | row);
- if (tfa->is_probus_device)
- {
- /* Assure FAIM is enabled (enable it when neccesery) */
- for (loop = 0; loop < 100 /*x10ms*/; loop++) {
- msleep_interruptible(10); /* wait 10ms to avoid busload */
- if (tfa_dev_get_mtpb(tfa) == 0)
- break;
- }
- error = tfa98xx_faim_protect(tfa, 0);
- if (tfa->verbose) {
- pr_debug("FAIM disabled (err:%d).\n", error);
- }
- }
-}
-
-enum Tfa98xx_Error tfa98xx_set_mtp(struct tfa_device *tfa, uint16_t value, uint16_t mask)
-{
- unsigned short mtp_old, mtp_new;
- int loop, status;
- enum Tfa98xx_Error error;
-
- error = tfa98xx_get_mtp(tfa, &mtp_old);
-
- if (error != Tfa98xx_Error_Ok)
- return error;
-
- mtp_new = (value & mask) | (mtp_old & ~mask);
-
- if (mtp_old == mtp_new) /* no change */ {
- if (tfa->verbose)
- pr_info("No change in MTP. Value not written! \n");
- return Tfa98xx_Error_Ok;
- }
- error = tfa98xx_update_lpm(tfa, 1);
- if (error) {
- return error;
- }
- /* Assure FAIM is enabled (enable it when neccesery) */
- error = tfa98xx_faim_protect(tfa, 1);
- if (error) {
- return error;
- }
- if (tfa->verbose) {
- pr_debug("MTP clock enabled.\n");
- }
-
- /* assure that the clock is up, else we can't write MTP */
- error = tfa98xx_dsp_system_stable(tfa, &status);
- if (error) {
- return error;
- }
- if (status == 0) {
- return Tfa98xx_Error_NoClock;
- }
-
- tfa98xx_key2(tfa, 0); /* unlock */
- TFA_WRITE_REG(tfa, MTP0, mtp_new); /* write to i2c shadow reg */
- /* CIMTP=1 start copying all the data from i2c regs_mtp to mtp*/
- if (tfa->tfa_family == 2)
- tfa2_manual_mtp_cpy(tfa, 0xF1, mtp_new, 0);
- else
- TFA_SET_BF(tfa, CIMTP, 1);
- /* wait until MTP write is done */
- error = Tfa98xx_Error_StateTimedOut;
- for (loop = 0; loop < 100 /*x10ms*/; loop++) {
- msleep_interruptible(10); /* wait 10ms to avoid busload */
- if (tfa_dev_get_mtpb(tfa) == 0) {
- error = Tfa98xx_Error_Ok;
- break;
- }
- }
- tfa98xx_key2(tfa, 1); /* lock */
- /* MTP setting failed due to timeout ?*/
- if (error) {
- tfa98xx_faim_protect(tfa, 0);
- return error;
- }
-
- /* Disable the FAIM, if this is neccessary */
- error = tfa98xx_faim_protect(tfa, 0);
- if (error) {
- return error;
- }
- if (tfa->verbose) {
- pr_debug("MTP clock disabled.\n");
- }
- error = tfa98xx_update_lpm(tfa, 0);
- if (error) {
- return error;
- }
- return error;
-}
-/*
- * clear mtpex
- * set ACS
- * start tfa
- */
-int tfa_calibrate(struct tfa_device *tfa)
-{
- enum Tfa98xx_Error error;
-
- /* clear mtpex */
- error = tfa98xx_set_mtp(tfa, 0, TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_MSK);
- if (error)
- return error;
-
- /* set RST=1 to put the DSP in Reset */
- TFA_SET_BF(tfa, RST, 1);
-
- /* set ACS/coldboot state */
- error = tfaRunColdboot(tfa, 1);
-
- /* start tfa by playing */
- return error;
-}
-
-static short twos(short x)
-{
- return (x < 0) ? x + 512 : x;
-}
-
-void tfa98xx_set_exttemp(struct tfa_device *tfa, short ext_temp)
-{
- if ((-256 <= ext_temp) && (ext_temp <= 255)) {
- /* make twos complement */
- pr_debug("Using ext temp %d C\n", twos(ext_temp));
- TFA_SET_BF(tfa, TROS, 1);
- TFA_SET_BF(tfa, EXTTS, twos(ext_temp));
- }
- else {
- pr_debug("Clearing ext temp settings\n");
- TFA_SET_BF(tfa, TROS, 0);
- }
-}
-short tfa98xx_get_exttemp(struct tfa_device *tfa)
-{
- short ext_temp = (short)TFA_GET_BF(tfa, EXTTS);
- return (twos(ext_temp));
-}
-
-/************************** tfa simple bitfield interfacing ***************************************/
-/* convenience functions */
-enum Tfa98xx_Error tfa98xx_set_volume_level(struct tfa_device *tfa, unsigned short vol)
-{
- if (tfa->in_use == 0)
- return Tfa98xx_Error_NotOpen;
-
- if (vol > 255) /* restricted to 8 bits */
- vol = 255;
-
- /* 0x00 -> 0.0 dB
- * 0x01 -> -0.5 dB
- * ...
- * 0xFE -> -127dB
- * 0xFF -> muted
- */
-
- /* volume value is in the top 8 bits of the register */
- return -TFA_SET_BF(tfa, VOL, (uint16_t)vol);
-}
-
-static enum Tfa98xx_Error
-tfa98xx_set_mute_tfa2(struct tfa_device *tfa, enum Tfa98xx_Mute mute)
-{
- enum Tfa98xx_Error error;
-
- if (tfa->dev_ops.set_mute == NULL)
- return Tfa98xx_Error_Not_Supported;
-
- switch (mute) {
- case Tfa98xx_Mute_Off:
- error = tfa->dev_ops.set_mute(tfa, 0);
- TFA_SET_BF(tfa, AMPE, 1);
- break;
- case Tfa98xx_Mute_Amplifier:
- case Tfa98xx_Mute_Digital:
- error = tfa->dev_ops.set_mute(tfa, 1);
- TFA_SET_BF(tfa, AMPE, 0);
- break;
- default:
- return Tfa98xx_Error_Bad_Parameter;
- }
-
- return error;
-}
-
-static enum Tfa98xx_Error
-tfa98xx_set_mute_tfa1(struct tfa_device *tfa, enum Tfa98xx_Mute mute)
-{
- enum Tfa98xx_Error error;
- unsigned short audioctrl_value;
- unsigned short sysctrl_value;
- int value;
-
- value = TFA_READ_REG(tfa, CFSM); /* audio control register */
- if (value < 0)
- return -value;
- audioctrl_value = (unsigned short)value;
- value = TFA_READ_REG(tfa, AMPE); /* system control register */
- if (value < 0)
- return -value;
- sysctrl_value = (unsigned short)value;
-
- switch (mute) {
- case Tfa98xx_Mute_Off:
- /* previous state can be digital or amplifier mute,
- * clear the cf_mute and set the enbl_amplifier bits
- *
- * To reduce PLOP at power on it is needed to switch the
- * amplifier on with the DCDC in follower mode
- * (enbl_boost = 0 ?).
- * This workaround is also needed when toggling the
- * powerdown bit!
- */
- TFA_SET_BF_VALUE(tfa, CFSM, 0, &audioctrl_value);
- TFA_SET_BF_VALUE(tfa, AMPE, 1, &sysctrl_value);
- TFA_SET_BF_VALUE(tfa, DCA, 1, &sysctrl_value);
- break;
- case Tfa98xx_Mute_Digital:
- /* expect the amplifier to run */
- /* set the cf_mute bit */
- TFA_SET_BF_VALUE(tfa, CFSM, 1, &audioctrl_value);
- /* set the enbl_amplifier bit */
- TFA_SET_BF_VALUE(tfa, AMPE, 1, &sysctrl_value);
- /* clear active mode */
- TFA_SET_BF_VALUE(tfa, DCA, 0, &sysctrl_value);
- break;
- case Tfa98xx_Mute_Amplifier:
- /* clear the cf_mute bit */
- TFA_SET_BF_VALUE(tfa, CFSM, 0, &audioctrl_value);
- /* clear the enbl_amplifier bit and active mode */
- TFA_SET_BF_VALUE(tfa, AMPE, 0, &sysctrl_value);
- TFA_SET_BF_VALUE(tfa, DCA, 0, &sysctrl_value);
- break;
- default:
- return Tfa98xx_Error_Bad_Parameter;
- }
-
- error = -TFA_WRITE_REG(tfa, CFSM, audioctrl_value);
- if (error)
- return error;
- error = -TFA_WRITE_REG(tfa, AMPE, sysctrl_value);
- return error;
-}
-
-enum Tfa98xx_Error
- tfa98xx_set_mute(struct tfa_device *tfa, enum Tfa98xx_Mute mute)
-{
- if (tfa->in_use == 0) {
- pr_err("device is not opened \n");
- return Tfa98xx_Error_NotOpen;
- }
-
- if (tfa->tfa_family == 1)
- return tfa98xx_set_mute_tfa1(tfa, mute);
- else
- return tfa98xx_set_mute_tfa2(tfa, mute);
-}
-
-/****************** patching **********************************************************/
-static enum Tfa98xx_Error
-tfa98xx_process_patch_file(struct tfa_device *tfa, int length,
- const unsigned char *bytes)
-{
- unsigned short size;
- int index = 0;
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
-
- while (index < length) {
- size = bytes[index] + bytes[index + 1] * 256;
- index += 2;
- if ((index + size) > length) {
- /* outside the buffer, error in the input data */
- return Tfa98xx_Error_Bad_Parameter;
- }
-
- if (size > tfa->buffer_size) {
- /* too big, must fit buffer */
- return Tfa98xx_Error_Bad_Parameter;
- }
-
- error = tfa98xx_write_raw(tfa, size, &bytes[index]);
- if (error != Tfa98xx_Error_Ok)
- break;
- index += size;
- }
- return error;
-}
-
-
-
-/* the patch contains a header with the following
- * IC revision register: 1 byte, 0xFF means don't care
- * XMEM address to check: 2 bytes, big endian, 0xFFFF means don't care
- * XMEM value to expect: 3 bytes, big endian
- */
-static enum Tfa98xx_Error
-tfa98xx_check_ic_rom_version(struct tfa_device *tfa, const unsigned char patchheader[])
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- unsigned short checkrev, revid;
- unsigned char lsb_revid;
- unsigned short checkaddress;
- int checkvalue;
- int value = 0;
- int status;
- checkrev = patchheader[0];
- lsb_revid = tfa->rev & 0xff; /* only compare lower byte */
-
- if ((checkrev != 0xFF) && (checkrev != lsb_revid))
- return Tfa98xx_Error_Not_Supported;
-
- checkaddress = (patchheader[1] << 8) + patchheader[2];
- checkvalue =
- (patchheader[3] << 16) + (patchheader[4] << 8) + patchheader[5];
- if (checkaddress != 0xFFFF) {
- /* before reading XMEM, check if we can access the DSP */
- error = tfa98xx_dsp_system_stable(tfa, &status);
- if (error == Tfa98xx_Error_Ok) {
- if (!status) {
- /* DSP subsys not running */
- error = Tfa98xx_Error_DSP_not_running;
- }
- }
- /* read register to check the correct ROM version */
- if (error == Tfa98xx_Error_Ok) {
- error = mem_read(tfa, checkaddress, 1, &value);
- }
- if (error == Tfa98xx_Error_Ok) {
- if (value != checkvalue) {
- pr_err("patch file romid type check failed [0x%04x]: expected 0x%02x, actual 0x%02x\n",
- checkaddress, value, checkvalue);
- error = Tfa98xx_Error_Not_Supported;
- }
- }
- }
- else { /* == 0xffff */
- /* check if the revid subtype is in there */
- if (checkvalue != 0xFFFFFF && checkvalue != 0) {
- revid = patchheader[5] << 8 | patchheader[0]; /* full revid */
- if (revid != tfa->rev) {
- pr_err("patch file device type check failed: expected 0x%02x, actual 0x%02x\n",
- tfa->rev, revid);
- return Tfa98xx_Error_Not_Supported;
- }
- }
- }
-
- return error;
-}
-
-
-#define PATCH_HEADER_LENGTH 6
-enum Tfa98xx_Error
- tfa_dsp_patch(struct tfa_device *tfa, int patchLength,
- const unsigned char *patchBytes)
-{
- enum Tfa98xx_Error error;
- int status;
- if (tfa->in_use == 0)
- return Tfa98xx_Error_NotOpen;
-
- if (patchLength < PATCH_HEADER_LENGTH)
- return Tfa98xx_Error_Bad_Parameter;
-
- error = tfa98xx_check_ic_rom_version(tfa, patchBytes);
- if (Tfa98xx_Error_Ok != error) {
- return error;
- }
- tfa98xx_dsp_system_stable(tfa, &status);
- if (!status)
- return Tfa98xx_Error_NoClock; // Only test when we have a clock.
- /******MCH_TO_TEST**************/
- if (error == Tfa98xx_Error_Ok) {
- error = tfaRunColdboot(tfa, 1);
- if (error)
- return Tfa98xx_Error_DSP_not_running;
- }
- /**************************/
- error =
- tfa98xx_process_patch_file(tfa, patchLength - PATCH_HEADER_LENGTH,
- patchBytes + PATCH_HEADER_LENGTH);
-
- return error;
-}
-
-/****************** end patching **********************************************************/
-
-TFA_INTERNAL enum Tfa98xx_Error
-tfa98xx_wait_result(struct tfa_device *tfa, int wait_retry_count)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- int cf_status; /* the contents of the CF_STATUS register */
- int tries = 0;
- do {
- cf_status = TFA_GET_BF(tfa, ACK);
- if (cf_status < 0)
- error = -cf_status;
- tries++;
- }
- // i2c_cmd_ack
- /* don't wait forever, DSP is pretty quick to respond (< 1ms) */
- while ((error == Tfa98xx_Error_Ok) && ((cf_status & CF_STATUS_I2C_CMD_ACK) == 0)
- && (tries < wait_retry_count));
- if (tries >= wait_retry_count) {
- /* something wrong with communication with DSP */
- error = Tfa98xx_Error_DSP_not_running;
- }
- return error;
-}
-
-/*
- * * support functions for data conversion
- */
- /**
- convert memory bytes to signed 24 bit integers
- input: bytes contains "num_bytes" byte elements
- output: data contains "num_bytes/3" int24 elements
- */
-void tfa98xx_convert_bytes2data(int num_bytes, const unsigned char bytes[],
- int data[])
-{
- int i; /* index for data */
- int k; /* index for bytes */
- int d;
- int num_data = num_bytes / 3;
- _ASSERT((num_bytes % 3) == 0);
- for (i = 0, k = 0; i < num_data; ++i, k += 3) {
- d = (bytes[k] << 16) | (bytes[k + 1] << 8) | (bytes[k + 2]);
- _ASSERT(d >= 0);
- _ASSERT(d < (1 << 24)); /* max 24 bits in use */
- if (bytes[k] & 0x80) /* sign bit was set */
- d = -((1 << 24) - d);
-
- data[i] = d;
- }
-}
-
-
-/**
- convert signed 32 bit integers to 24 bit aligned bytes
- input: data contains "num_data" int elements
- output: bytes contains "3 * num_data" byte elements
-*/
-void tfa98xx_convert_data2bytes(int num_data, const int data[],
- unsigned char bytes[])
-{
- int i; /* index for data */
- int k; /* index for bytes */
- int d;
- /* note: cannot just take the lowest 3 bytes from the 32 bit
- * integer, because also need to take care of clipping any
- * value > 2&23 */
- for (i = 0, k = 0; i < num_data; ++i, k += 3) {
- if (data[i] >= 0)
- d = MIN(data[i], (1 << 23) - 1);
- else {
- /* 2's complement */
- d = (1 << 24) - MIN(-data[i], 1 << 23);
- }
- _ASSERT(d >= 0);
- _ASSERT(d < (1 << 24)); /* max 24 bits in use */
- bytes[k] = (d >> 16) & 0xFF; /* MSB */
- bytes[k + 1] = (d >> 8) & 0xFF;
- bytes[k + 2] = (d) & 0xFF; /* LSB */
- }
-}
-
-/*
- * DSP RPC message support functions
- * depending on framework to be up and running
- * need base i2c of memaccess (tfa1=0x70/tfa2=0x90)
- */
-
-
- /* write dsp messages in function tfa_dsp_msg() */
- /* note the 'old' write_parameter() was more efficient because all i2c was in one burst transaction */
-
- //TODO properly handle bitfields: state should be restored! (now it will change eg dmesg field to xmem)
-enum Tfa98xx_Error tfa_dsp_msg_write(struct tfa_device *tfa, int length, const char *buffer)
-{
- int offset = 0;
- int chunk_size = ROUND_DOWN(tfa->buffer_size, 3); /* XMEM word size */
- int remaining_bytes = length;
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- uint16_t cfctl;
- int value;
-
- value = TFA_READ_REG(tfa, DMEM);
- if (value < 0) {
- error = -value;
- return error;
- }
- cfctl = (uint16_t)value;
- /* assume no I2C errors from here */
-
- TFA_SET_BF_VALUE(tfa, DMEM, (uint16_t)Tfa98xx_DMEM_XMEM, &cfctl); /* set cf ctl to DMEM */
- TFA_SET_BF_VALUE(tfa, AIF, 0, &cfctl); /* set to autoincrement */
- TFA_WRITE_REG(tfa, DMEM, cfctl);
-
- /* xmem[1] is start of message
- * direct write to register to save cycles avoiding read-modify-write
- */
- TFA_WRITE_REG(tfa, MADD, 1);
-
- /* due to autoincrement in cf_ctrl, next write will happen at
- * the next address */
- while ((error == Tfa98xx_Error_Ok) && (remaining_bytes > 0)) {
- if (remaining_bytes < chunk_size)
- chunk_size = remaining_bytes;
- /* else chunk_size remains at initialize value above */
- error = tfa98xx_write_data(tfa, FAM_TFA98XX_CF_MEM,
- chunk_size, (const unsigned char *)buffer + offset);
- remaining_bytes -= chunk_size;
- offset += chunk_size;
- }
-
- /* notify the DSP */
- if (error == Tfa98xx_Error_Ok) {
- /* cf_int=0, cf_aif=0, cf_dmem=XMEM=01, cf_rst_dsp=0 */
- /* set the cf_req1 and cf_int bit */
- TFA_SET_BF_VALUE(tfa, REQCMD, 0x01, &cfctl); /* bit 0 */
- TFA_SET_BF_VALUE(tfa, CFINT, 1, &cfctl);
- error = -TFA_WRITE_REG(tfa, CFINT, cfctl);
- }
-
- return error;
-}
-
-enum Tfa98xx_Error tfa_dsp_msg_write_id(struct tfa_device *tfa, int length, const char *buffer, uint8_t cmdid[3])
-{
- int offset = 0;
- int chunk_size = ROUND_DOWN(tfa->buffer_size, 3); /* XMEM word size */
- int remaining_bytes = length;
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- uint16_t cfctl;
- int value;
-
- value = TFA_READ_REG(tfa, DMEM);
- if (value < 0) {
- error = -value;
- return error;
- }
- cfctl = (uint16_t)value;
- /* assume no I2C errors from here */
-
- TFA_SET_BF_VALUE(tfa, DMEM, (uint16_t)Tfa98xx_DMEM_XMEM, &cfctl); /* set cf ctl to DMEM */
- TFA_SET_BF_VALUE(tfa, AIF, 0, &cfctl); /* set to autoincrement */
- TFA_WRITE_REG(tfa, DMEM, cfctl);
-
- /* xmem[1] is start of message
- * direct write to register to save cycles avoiding read-modify-write
- */
- TFA_WRITE_REG(tfa, MADD, 1);
-
- /* write cmd-id */
- error = tfa98xx_write_data(tfa, FAM_TFA98XX_CF_MEM, 3, (const unsigned char *)cmdid);
-
- /* due to autoincrement in cf_ctrl, next write will happen at
- * the next address */
- while ((error == Tfa98xx_Error_Ok) && (remaining_bytes > 0)) {
- if (remaining_bytes < chunk_size)
- chunk_size = remaining_bytes;
- /* else chunk_size remains at initialize value above */
- error = tfa98xx_write_data(tfa, FAM_TFA98XX_CF_MEM,
- chunk_size, (const unsigned char *)buffer + offset);
- remaining_bytes -= chunk_size;
- offset += chunk_size;
- }
-
- /* notify the DSP */
- if (error == Tfa98xx_Error_Ok) {
- /* cf_int=0, cf_aif=0, cf_dmem=XMEM=01, cf_rst_dsp=0 */
- /* set the cf_req1 and cf_int bit */
- TFA_SET_BF_VALUE(tfa, REQCMD, 0x01, &cfctl); /* bit 0 */
- TFA_SET_BF_VALUE(tfa, CFINT, 1, &cfctl);
- error = -TFA_WRITE_REG(tfa, CFINT, cfctl);
- }
-
- return error;
-}
-
-/*
-* status function used by tfa_dsp_msg() to retrieve command/msg status:
-* return a <0 status of the DSP did not ACK.
-*/
-enum Tfa98xx_Error tfa_dsp_msg_status(struct tfa_device *tfa, int *pRpcStatus)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
-
- error = tfa98xx_wait_result(tfa, 2); /* 2 is only one try */
- if (error == Tfa98xx_Error_DSP_not_running) {
- *pRpcStatus = -1;
- return Tfa98xx_Error_Ok;
- }
- else if (error != Tfa98xx_Error_Ok)
- return error;
-
- error = tfa98xx_check_rpc_status(tfa, pRpcStatus);
-
- return error;
-}
-
-const char* tfa98xx_get_i2c_status_id_string(int status)
-{
- const char* p_id_str;
-
- switch (status)
- {
- case Tfa98xx_DSP_Not_Running:
- p_id_str = "No response from DSP";
- break;
- case Tfa98xx_I2C_Req_Done:
- p_id_str = "Ok";
- break;
- case Tfa98xx_I2C_Req_Busy:
- p_id_str = "Request is being processed";
- break;
- case Tfa98xx_I2C_Req_Invalid_M_ID:
- p_id_str = "Provided M-ID does not fit in valid rang [0..2]";
- break;
- case Tfa98xx_I2C_Req_Invalid_P_ID:
- p_id_str = "Provided P-ID is not valid in the given M-ID context";
- break;
- case Tfa98xx_I2C_Req_Invalid_CC:
- p_id_str = "Invalid channel configuration bits (SC|DS|DP|DC) combination";
- break;
- case Tfa98xx_I2C_Req_Invalid_Seq:
- p_id_str = "Invalid sequence of commands, in case the DSP expects some commands in a specific order";
- break;
- case Tfa98xx_I2C_Req_Invalid_Param:
- p_id_str = "Generic error, invalid parameter";
- break;
- case Tfa98xx_I2C_Req_Buffer_Overflow:
- p_id_str = "I2C buffer has overflowed: host has sent too many parameters, memory integrity is not guaranteed";
- break;
- case Tfa98xx_I2C_Req_Calib_Busy:
- p_id_str = "Calibration not completed";
- break;
- case Tfa98xx_I2C_Req_Calib_Failed:
- p_id_str = "Calibration failed";
- break;
-
- default:
- p_id_str = "Unspecified error";
- }
-
- return p_id_str;
-}
-
-enum Tfa98xx_Error tfa_dsp_msg_read(struct tfa_device *tfa, int length, unsigned char *bytes)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- int burst_size; /* number of words per burst size */
- int bytes_per_word = 3;
- int num_bytes;
- int offset = 0;
- unsigned short start_offset = 2; /* msg starts @xmem[2] ,[1]=cmd */
-
- if (length > TFA2_MAX_PARAM_SIZE)
- return Tfa98xx_Error_Bad_Parameter;
-
- TFA_SET_BF(tfa, DMEM, (uint16_t)Tfa98xx_DMEM_XMEM);
- error = -TFA_WRITE_REG(tfa, MADD, start_offset);
- if (error != Tfa98xx_Error_Ok)
- return error;
-
- num_bytes = length; /* input param */
- while (num_bytes > 0) {
- burst_size = ROUND_DOWN(tfa->buffer_size, bytes_per_word);
- if (num_bytes < burst_size)
- burst_size = num_bytes;
- error = tfa98xx_read_data(tfa, FAM_TFA98XX_CF_MEM, burst_size, bytes + offset);
- if (error != Tfa98xx_Error_Ok)
- return error;
-
- num_bytes -= burst_size;
- offset += burst_size;
- }
-
- return error;
-}
-
-enum Tfa98xx_Error dsp_msg(struct tfa_device *tfa, int length24, const char *buf24)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- int lastmessage = 0;
- uint8_t *blob;
- int i;
- int *intbuf = NULL;
- char* buf = (char *)buf24;
- int length = length24;
-
- if (tfa->convert_dsp32) {
- int idx = 0;
-
- length = 4 * length24 / 3;
- intbuf = kmem_cache_alloc(tfa->cachep, GFP_KERNEL);
- buf = (char *)intbuf;
-
- /* convert 24 bit DSP messages to a 32 bit integer */
- for (i = 0; i < length24; i += 3) {
- int tmp = (buf24[i] << 16) + (buf24[i + 1] << 8) + buf24[i + 2];
- /* Sign extend to 32-bit from 24-bit */
- intbuf[idx++] = ((int32_t)tmp << 8) >> 8;
- }
- }
-
- /* Only create multi-msg when the dsp is cold */
- if (tfa->ext_dsp == 1) {
- /* Creating the multi-msg */
- error = tfa_tib_dsp_msgmulti(tfa, length, buf);
- if (error == Tfa98xx_Error_Fail)
- return Tfa98xx_Error_Fail;
-
- /* if the buffer is full we need to send the existing message and add the current message */
- if (error == Tfa98xx_Error_Buffer_too_small) {
- int len;
-
- /* (a) send the existing (full) message */
- blob = kmalloc(64 * 1024, GFP_KERNEL); // max length is 64k
- len = tfa_tib_dsp_msgmulti(tfa, -1, (const char*)blob);
- if (tfa->verbose) {
- pr_debug("Multi-message buffer full. Sending multi-message, length=%d \n", len);
- }
- if (tfa->has_msg == 0) /* via i2c */ {
- /* Send tot the target selected */
- error = (tfa->dev_ops.dsp_msg)(tfa, len, (const char*)blob);
- }
- else { /* via msg hal */
- error = tfa98xx_write_dsp(tfa, len, (const char*)blob);
- }
- kfree(blob);
-
- /* (b) add the current DSP message to a new multi-message */
- error = tfa_tib_dsp_msgmulti(tfa, length, buf);
- if (error == Tfa98xx_Error_Fail) {
- return Tfa98xx_Error_Fail;
- }
- }
-
- lastmessage = error;
-
- /* When the lastmessage is done we can send the multi-msg to the target */
- if (lastmessage == 1) {
-
- /* Get the full multi-msg data */
- blob = kmalloc(64 * 1024, GFP_KERNEL); //max length is 64k
- length = tfa_tib_dsp_msgmulti(tfa, -1, (const char*)blob);
-
- if (tfa->verbose)
- pr_debug("Last message for the multi-message received. Multi-message length=%d \n", length);
-
- if (tfa->has_msg == 0) /* via i2c */ {
- /* Send tot the target selected */
- error = (tfa->dev_ops.dsp_msg)(tfa, length, (const char*)blob);
- }
- else { /* via msg hal */
- error = tfa98xx_write_dsp(tfa, length, (const char*)blob);
- }
-
- kfree(blob); /* Free the kmalloc blob */
- lastmessage = 0; /* reset to be able to re-start */
- }
- }
- else {
- if (tfa->has_msg == 0) /* via i2c */ {
- error = (tfa->dev_ops.dsp_msg)(tfa, length, buf);
- }
- else { /* via msg hal */
- error = tfa98xx_write_dsp(tfa, length, (const char*)buf);
- }
- }
-
- if (error != Tfa98xx_Error_Ok)
- error = (enum Tfa98xx_Error) (error + Tfa98xx_Error_RpcBase); /* Get actual error code from softDSP */
-
- /* DSP verbose has argument 0x04 */
- if ((tfa->verbose & 0x04) != 0) {
- pr_debug("DSP w [%d]: ", length);
- for (i = 0; i < length; i++)
- pr_debug("0x%02x ", (uint8_t)buf[i]);
- pr_debug("\n");
- }
-
- if (tfa->convert_dsp32) {
- kmem_cache_free(tfa->cachep, intbuf);
- }
-
- return error;
-}
-
-enum Tfa98xx_Error dsp_msg_read(struct tfa_device *tfa, int length24, unsigned char *bytes24)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- int i;
- int length = length24;
- unsigned char *bytes = bytes24;
-
- if (tfa->convert_dsp32) {
- length = 4 * length24 / 3;
- bytes = kmem_cache_alloc(tfa->cachep, GFP_KERNEL);
- }
-
- if (tfa->has_msg == 0) /* via i2c */ {
- error = (tfa->dev_ops.dsp_msg_read)(tfa, length, bytes);
- }
- else { /* via msg hal */
- error = tfa98xx_read_dsp(tfa, length, bytes);
- }
-
- if (error != Tfa98xx_Error_Ok)
- error = (enum Tfa98xx_Error) (error + Tfa98xx_Error_RpcBase); /* Get actual error code from softDSP */
-
- /* DSP verbose has argument 0x04 */
- if ((tfa->verbose & 0x04) != 0) {
- pr_debug("DSP R [%d]: ", length);
- for (i = 0; i < length; i++)
- pr_debug("0x%02x ", (uint8_t)bytes[i]);
- pr_debug("\n");
- }
-
- if (tfa->convert_dsp32) {
- int idx = 0;
-
- /* convert 32 bit LE to 24 bit BE */
- for (i = 0; i < length; i += 4) {
- bytes24[idx++] = bytes[i + 2];
- bytes24[idx++] = bytes[i + 1];
- bytes24[idx++] = bytes[i + 0];
- }
-
- kmem_cache_free(tfa->cachep, bytes);
- }
-
- return error;
-}
-
-enum Tfa98xx_Error reg_read(struct tfa_device *tfa, unsigned char subaddress, unsigned short *value)
-{
- enum Tfa98xx_Error error;
-
- error = (tfa->dev_ops.reg_read)(tfa, subaddress, value);
- if (error != Tfa98xx_Error_Ok)
- error = (enum Tfa98xx_Error) (error + Tfa98xx_Error_RpcBase); /* Get actual error code from softDSP */
-
- return error;
-}
-
-enum Tfa98xx_Error reg_write(struct tfa_device *tfa, unsigned char subaddress, unsigned short value)
-{
- enum Tfa98xx_Error error;
-
- error = (tfa->dev_ops.reg_write)(tfa, subaddress, value);
- if (error != Tfa98xx_Error_Ok)
- error = (enum Tfa98xx_Error) (error + Tfa98xx_Error_RpcBase); /* Get actual error code from softDSP */
-
- return error;
-}
-
-enum Tfa98xx_Error mem_read(struct tfa_device *tfa, unsigned int start_offset, int num_words, int *pValues)
-{
- enum Tfa98xx_Error error;
-
- error = (tfa->dev_ops.mem_read)(tfa, start_offset, num_words, pValues);
- if (error != Tfa98xx_Error_Ok)
- error = (enum Tfa98xx_Error) (error + Tfa98xx_Error_RpcBase); /* Get actual error code from softDSP */
-
- return error;
-}
-
-enum Tfa98xx_Error mem_write(struct tfa_device *tfa, unsigned short address, int value, int memtype)
-{
- enum Tfa98xx_Error error;
-
- error = (tfa->dev_ops.mem_write)(tfa, address, value, memtype);
- if (error != Tfa98xx_Error_Ok)
- error = (enum Tfa98xx_Error) (error + Tfa98xx_Error_RpcBase); /* Get actual error code from softDSP */
-
- return error;
-}
-
-
-/*
- * write/read raw msg functions :
- * the buffer is provided in little endian format, each word occupying 3 bytes, length is in bytes.
- * The functions will return immediately and do not not wait for DSP reponse.
- */
-#define MAX_WORDS (300)
-enum Tfa98xx_Error tfa_dsp_msg(struct tfa_device *tfa, int length, const char *buf)
-{
- enum Tfa98xx_Error error;
- int tries, rpc_status = Tfa98xx_I2C_Req_Done;
-
- /* write the message and notify the DSP */
- error = tfa_dsp_msg_write(tfa, length, buf);
- if (error != Tfa98xx_Error_Ok)
- return error;
-
- /* get the result from the DSP (polling) */
- for (tries = TFA98XX_WAITRESULT_NTRIES; tries > 0; tries--) {
- error = tfa_dsp_msg_status(tfa, &rpc_status);
- if (error == Tfa98xx_Error_Ok && rpc_status == Tfa98xx_I2C_Req_Done)
- break;
- /* If the rpc status is a specific error we want to know it.
- * If it is busy or not running it should retry
- */
- if (rpc_status != Tfa98xx_I2C_Req_Busy && rpc_status != Tfa98xx_DSP_Not_Running)
- break;
- }
-
- if (rpc_status != Tfa98xx_I2C_Req_Done) {
- /* DSP RPC call returned an error */
- error = (enum Tfa98xx_Error) (rpc_status + Tfa98xx_Error_RpcBase);
- pr_debug("DSP msg status: %d (%s)\n", rpc_status, tfa98xx_get_i2c_status_id_string(rpc_status));
- }
- return error;
-}
-
-/**
- * write/read raw msg functions:
- * the buffer is provided in little endian format, each word occupying 3 bytes, length is in bytes.
- * The functions will return immediately and do not not wait for DSP reponse.
- * An ID is added to modify the command-ID
- */
-enum Tfa98xx_Error tfa_dsp_msg_id(struct tfa_device *tfa, int length, const char *buf, uint8_t cmdid[3])
-{
- enum Tfa98xx_Error error;
- int tries, rpc_status = Tfa98xx_I2C_Req_Done;
-
- /* write the message and notify the DSP */
- error = tfa_dsp_msg_write_id(tfa, length, buf, cmdid);
- if (error != Tfa98xx_Error_Ok)
- return error;
-
- /* get the result from the DSP (polling) */
- for (tries = TFA98XX_WAITRESULT_NTRIES; tries > 0; tries--) {
- error = tfa_dsp_msg_status(tfa, &rpc_status);
- if (error == Tfa98xx_Error_Ok && rpc_status == Tfa98xx_I2C_Req_Done)
- break;
- }
-
- if (rpc_status != Tfa98xx_I2C_Req_Done) {
- /* DSP RPC call returned an error */
- error = (enum Tfa98xx_Error) (rpc_status + Tfa98xx_Error_RpcBase);
- pr_debug("DSP msg status: %d (%s)\n", rpc_status, tfa98xx_get_i2c_status_id_string(rpc_status));
- }
- return error;
-}
-
-/* read the return code for the RPC call */
-TFA_INTERNAL enum Tfa98xx_Error
-tfa98xx_check_rpc_status(struct tfa_device *tfa, int *pRpcStatus)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- /* the value to sent to the * CF_CONTROLS register: cf_req=00000000,
- * cf_int=0, cf_aif=0, cf_dmem=XMEM=01, cf_rst_dsp=0 */
- unsigned short cf_ctrl = 0x0002;
- /* memory address to be accessed (0: Status, 1: ID, 2: parameters) */
- unsigned short cf_mad = 0x0000;
-
- if (tfa->in_use == 0)
- return Tfa98xx_Error_NotOpen;
- if (pRpcStatus == NULL)
- return Tfa98xx_Error_Bad_Parameter;
-
- /* 1) write DMEM=XMEM to the DSP XMEM */
- {
- /* minimize the number of I2C transactions by making use of the autoincrement in I2C */
- unsigned char buffer[4];
- /* first the data for CF_CONTROLS */
- buffer[0] = (unsigned char)((cf_ctrl >> 8) & 0xFF);
- buffer[1] = (unsigned char)(cf_ctrl & 0xFF);
- /* write the contents of CF_MAD which is the subaddress following CF_CONTROLS */
- buffer[2] = (unsigned char)((cf_mad >> 8) & 0xFF);
- buffer[3] = (unsigned char)(cf_mad & 0xFF);
- error = tfa98xx_write_data(tfa, FAM_TFA98XX_CF_CONTROLS, sizeof(buffer), buffer);
- }
- if (error == Tfa98xx_Error_Ok) {
- /* read 1 word (24 bit) from XMEM */
- error = tfa98xx_dsp_read_mem(tfa, 0, 1, pRpcStatus);
- }
-
- return error;
-}
-
-/***************************** xmem only **********************************/
-enum Tfa98xx_Error
- tfa98xx_dsp_read_mem(struct tfa_device *tfa,
- unsigned int start_offset, int num_words, int *pValues)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- unsigned char *bytes;
- int burst_size; /* number of words per burst size */
- const int bytes_per_word = 3;
- int dmem;
- int num_bytes;
- int *p;
-
- bytes = (unsigned char *)kmem_cache_alloc(tfa->cachep, GFP_KERNEL);
- if (bytes == NULL)
- return Tfa98xx_Error_Fail;
-
- /* If no offset is given, assume XMEM! */
- if (((start_offset >> 16) & 0xf) > 0)
- dmem = (start_offset >> 16) & 0xf;
- else
- dmem = Tfa98xx_DMEM_XMEM;
-
- /* Remove offset from adress */
- start_offset = start_offset & 0xffff;
- num_bytes = num_words * bytes_per_word;
- p = pValues;
-
- TFA_SET_BF(tfa, DMEM, (uint16_t)dmem);
- error = -TFA_WRITE_REG(tfa, MADD, (unsigned short)start_offset);
- if (error != Tfa98xx_Error_Ok)
- goto tfa98xx_dsp_read_mem_exit;
-
- for (; num_bytes > 0;) {
- burst_size = ROUND_DOWN(tfa->buffer_size, bytes_per_word);
- if (num_bytes < burst_size)
- burst_size = num_bytes;
-
- _ASSERT(burst_size <= sizeof(bytes));
- error = tfa98xx_read_data(tfa, FAM_TFA98XX_CF_MEM, burst_size, bytes);
- if (error != Tfa98xx_Error_Ok)
- goto tfa98xx_dsp_read_mem_exit;
-
- tfa98xx_convert_bytes2data(burst_size, bytes, p);
-
- num_bytes -= burst_size;
- p += burst_size / bytes_per_word;
- }
-
-tfa98xx_dsp_read_mem_exit:
- kmem_cache_free(tfa->cachep, bytes);
-
- return error;
-}
-
-
-enum Tfa98xx_Error
- tfa98xx_dsp_write_mem_word(struct tfa_device *tfa, unsigned short address, int value, int memtype)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- unsigned char bytes[3];
-
- TFA_SET_BF(tfa, DMEM, (uint16_t)memtype);
-
- error = -TFA_WRITE_REG(tfa, MADD, address);
- if (error != Tfa98xx_Error_Ok)
- return error;
-
- tfa98xx_convert_data2bytes(1, &value, bytes);
- error = tfa98xx_write_data(tfa, FAM_TFA98XX_CF_MEM, 3, bytes);
-
- return error;
-}
-
-enum Tfa98xx_Error tfa_cont_write_filterbank(struct tfa_device *tfa, nxpTfaFilter_t *filter)
-{
- unsigned char biquad_index;
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
-
- for (biquad_index = 0; biquad_index < 10; biquad_index++) {
- if (filter[biquad_index].enabled) {
- error = tfa_dsp_cmd_id_write(tfa, MODULE_BIQUADFILTERBANK,
- biquad_index + 1, //start @1
- sizeof(filter[biquad_index].biquad.bytes),
- filter[biquad_index].biquad.bytes);
- }
- else {
- error = Tfa98xx_DspBiquad_Disable(tfa, biquad_index + 1);
- }
- if (error) return error;
-
- }
-
- return error;
-}
-
-enum Tfa98xx_Error
- Tfa98xx_DspBiquad_Disable(struct tfa_device *tfa, int biquad_index)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- int coeff_buffer[BIQUAD_COEFF_SIZE];
- unsigned char bytes[3 + BIQUAD_COEFF_SIZE * 3];
- int nr = 0;
-
- if (biquad_index > TFA98XX_BIQUAD_NUM)
- return Tfa98xx_Error_Bad_Parameter;
- if (biquad_index < 1)
- return Tfa98xx_Error_Bad_Parameter;
-
- /* make opcode */
- bytes[nr++] = 0;
- bytes[nr++] = MODULE_BIQUADFILTERBANK + 128;
- bytes[nr++] = (unsigned char)biquad_index;
-
-
- /* set in correct order and format for the DSP */
- coeff_buffer[0] = (int)-8388608; /* -1.0f */
- coeff_buffer[1] = 0;
- coeff_buffer[2] = 0;
- coeff_buffer[3] = 0;
- coeff_buffer[4] = 0;
- coeff_buffer[5] = 0;
-
- /* convert to packed 24 */
- tfa98xx_convert_data2bytes(BIQUAD_COEFF_SIZE, coeff_buffer, &bytes[nr]);
- nr += BIQUAD_COEFF_SIZE * 3;
-
- error = dsp_msg(tfa, nr, (char *)bytes);
-
- return error;
-}
-
-/* wrapper for dsp_msg that adds opcode */
-enum Tfa98xx_Error tfa_dsp_cmd_id_write(struct tfa_device *tfa,
- unsigned char module_id,
- unsigned char param_id, int num_bytes,
- const unsigned char data[])
-{
- enum Tfa98xx_Error error;
- unsigned char *buffer;
- int nr = 0;
-
- buffer = kmem_cache_alloc(tfa->cachep, GFP_KERNEL);
- if (buffer == NULL)
- return Tfa98xx_Error_Fail;
-
- buffer[nr++] = tfa->spkr_select;
- buffer[nr++] = module_id + 128;
- buffer[nr++] = param_id;
-
- memcpy(&buffer[nr], data, num_bytes);
- nr += num_bytes;
-
- error = dsp_msg(tfa, nr, (char *)buffer);
-
- kmem_cache_free(tfa->cachep, buffer);
-
- return error;
-}
-
-/* wrapper for dsp_msg that adds opcode */
-/* this is as the former tfa98xx_dsp_get_param() */
-enum Tfa98xx_Error tfa_dsp_cmd_id_write_read(struct tfa_device *tfa,
- unsigned char module_id,
- unsigned char param_id, int num_bytes,
- unsigned char data[])
-{
- enum Tfa98xx_Error error;
- unsigned char buffer[3];
- int nr = 0;
-
- if (num_bytes <= 0) {
- pr_debug("Error: The number of READ bytes is smaller or equal to 0! \n");
- return Tfa98xx_Error_Fail;
- }
-
- if ((tfa->is_probus_device) && (tfa->cnt->ndev == 1) &&
- (param_id == SB_PARAM_GET_RE25C ||
- param_id == SB_PARAM_GET_LSMODEL ||
- param_id == SB_PARAM_GET_ALGO_PARAMS)) {
- /* Modifying the ID for GetRe25C */
- buffer[nr++] = 4;
- }
- else {
- buffer[nr++] = tfa->spkr_select;
- }
- buffer[nr++] = module_id + 128;
- buffer[nr++] = param_id;
-
- error = dsp_msg(tfa, nr, (char *)buffer);
- if (error != Tfa98xx_Error_Ok)
- return error;
-
- /* read the data from the dsp */
- error = dsp_msg_read(tfa, num_bytes, data);
- return error;
-}
-
-/* wrapper for dsp_msg that adds opcode and 3 bytes required for coefs */
-enum Tfa98xx_Error tfa_dsp_cmd_id_coefs(struct tfa_device *tfa,
- unsigned char module_id,
- unsigned char param_id, int num_bytes,
- unsigned char data[])
-{
- enum Tfa98xx_Error error;
- unsigned char buffer[2 * 3];
- int nr = 0;
-
- buffer[nr++] = tfa->spkr_select;
- buffer[nr++] = module_id + 128;
- buffer[nr++] = param_id;
-
- buffer[nr++] = 0;
- buffer[nr++] = 0;
- buffer[nr++] = 0;
-
- error = dsp_msg(tfa, nr, (char *)buffer);
- if (error != Tfa98xx_Error_Ok)
- return error;
-
- /* read the data from the dsp */
- error = dsp_msg_read(tfa, num_bytes, data);
-
- return error;
-}
-
-/* wrapper for dsp_msg that adds opcode and 3 bytes required for MBDrcDynamics */
-enum Tfa98xx_Error tfa_dsp_cmd_id_MBDrc_dynamics(struct tfa_device *tfa,
- unsigned char module_id,
- unsigned char param_id, int index_subband,
- int num_bytes, unsigned char data[])
-{
- enum Tfa98xx_Error error;
- unsigned char buffer[2 * 3];
- int nr = 0;
-
- buffer[nr++] = tfa->spkr_select;
- buffer[nr++] = module_id + 128;
- buffer[nr++] = param_id;
-
- buffer[nr++] = 0;
- buffer[nr++] = 0;
- buffer[nr++] = (unsigned char)index_subband;
-
- error = dsp_msg(tfa, nr, (char *)buffer);
- if (error != Tfa98xx_Error_Ok)
- return error;
-
- /* read the data from the dsp */
- error = dsp_msg_read(tfa, num_bytes, data);
-
- return error;
-}
-
-enum Tfa98xx_Error
- tfa98xx_dsp_write_preset(struct tfa_device *tfa, int length,
- const unsigned char *p_preset_bytes)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- if (p_preset_bytes != NULL) {
- /* by design: keep the data opaque and no
- * interpreting/calculation */
- error = tfa_dsp_cmd_id_write(tfa, MODULE_SPEAKERBOOST,
- SB_PARAM_SET_PRESET, length,
- p_preset_bytes);
- }
- else {
- error = Tfa98xx_Error_Bad_Parameter;
- }
- return error;
-}
-
-/*
- * get features from MTP
- */
-enum Tfa98xx_Error
- tfa98xx_dsp_get_hw_feature_bits(struct tfa_device *tfa, int *features)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- uint32_t value;
- uint16_t mtpbf;
-
- /* return the cache data if it's valid */
- if (tfa->hw_feature_bits != -1) {
- *features = tfa->hw_feature_bits;
- }
- else {
- /* for tfa1 check if we have clock */
- if (tfa->tfa_family == 1) {
- int status;
- tfa98xx_dsp_system_stable(tfa, &status);
- if (!status) {
- get_hw_features_from_cnt(tfa, features);
- /* skip reading MTP: */
- return (*features == -1) ? Tfa98xx_Error_Fail : Tfa98xx_Error_Ok;
- }
- mtpbf = 0x850f; /* MTP5 for tfa1,16 bits */
- }
- else
- mtpbf = 0xf907; /* MTP9 for tfa2, 8 bits */
- value = tfa_read_reg(tfa, mtpbf) & 0xffff;
- *features = tfa->hw_feature_bits = value;
- }
-
- return error;
-}
-
-enum Tfa98xx_Error
- tfa98xx_dsp_get_sw_feature_bits(struct tfa_device *tfa, int features[2])
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- const int byte_size = 2 * 3;
- unsigned char bytes[2 * 3];
-
- /* return the cache data if it's valid */
- if (tfa->sw_feature_bits[0] != -1) {
- features[0] = tfa->sw_feature_bits[0];
- features[1] = tfa->sw_feature_bits[1];
- }
- else {
- /* for tfa1 check if we have clock */
- if (tfa->tfa_family == 1) {
- int status;
- tfa98xx_dsp_system_stable(tfa, &status);
- if (!status) {
- get_sw_features_from_cnt(tfa, features);
- /* skip reading MTP: */
- return (features[0] == -1) ? Tfa98xx_Error_Fail : Tfa98xx_Error_Ok;
- }
- }
- error = tfa_dsp_cmd_id_write_read(tfa, MODULE_FRAMEWORK,
- FW_PAR_ID_GET_FEATURE_INFO, byte_size, bytes);
-
- if (error != Tfa98xx_Error_Ok) {
- /* old ROM code may respond with Tfa98xx_Error_RpcParamId */
- return error;
- }
-
- tfa98xx_convert_bytes2data(byte_size, bytes, features);
- }
- return error;
-}
-
-enum Tfa98xx_Error tfa98xx_dsp_get_state_info(struct tfa_device *tfa, unsigned char bytes[], unsigned int *statesize)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- int bSupportFramework = 0;
- unsigned int stateSize = 9;
-
- err = tfa98xx_dsp_support_framework(tfa, &bSupportFramework);
- if (err == Tfa98xx_Error_Ok) {
- if (bSupportFramework) {
- err = tfa_dsp_cmd_id_write_read(tfa, MODULE_FRAMEWORK,
- FW_PARAM_GET_STATE, 3 * stateSize, bytes);
- }
- else {
- /* old ROM code, ask SpeakerBoost and only do first portion */
- stateSize = 8;
- err = tfa_dsp_cmd_id_write_read(tfa, MODULE_SPEAKERBOOST,
- SB_PARAM_GET_STATE, 3 * stateSize, bytes);
- }
- }
-
- *statesize = stateSize;
-
- return err;
-}
-
-enum Tfa98xx_Error tfa98xx_dsp_support_drc(struct tfa_device *tfa, int *pbSupportDrc)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
-
- *pbSupportDrc = 0;
-
- if (tfa->in_use == 0)
- return Tfa98xx_Error_NotOpen;
- if (tfa->supportDrc != supportNotSet) {
- *pbSupportDrc = (tfa->supportDrc == supportYes);
- }
- else {
- int featureBits[2];
-
- error = tfa98xx_dsp_get_sw_feature_bits(tfa, featureBits);
- if (error == Tfa98xx_Error_Ok) {
- /* easy case: new API available */
- /* bit=0 means DRC enabled */
- *pbSupportDrc = (featureBits[0] & FEATURE1_DRC) == 0;
- }
- else if (error == Tfa98xx_Error_RpcParamId) {
- /* older ROM code, doesn't support it */
- *pbSupportDrc = 0;
- error = Tfa98xx_Error_Ok;
- }
- /* else some other error, return transparently */
- /* pbSupportDrc only changed when error == Tfa98xx_Error_Ok */
-
- if (error == Tfa98xx_Error_Ok) {
- tfa->supportDrc = *pbSupportDrc ? supportYes : supportNo;
- }
- }
- return error;
-}
-
-enum Tfa98xx_Error
- tfa98xx_dsp_support_framework(struct tfa_device *tfa, int *pbSupportFramework)
-{
- int featureBits[2] = { 0, 0 };
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
-
- _ASSERT(pbSupportFramework != 0);
-
- if (tfa->in_use == 0)
- return Tfa98xx_Error_NotOpen;
-
- if (tfa->supportFramework != supportNotSet) {
- if (tfa->supportFramework == supportNo)
- *pbSupportFramework = 0;
- else
- *pbSupportFramework = 1;
- }
- else {
- error = tfa98xx_dsp_get_sw_feature_bits(tfa, featureBits);
- if (error == Tfa98xx_Error_Ok) {
- *pbSupportFramework = 1;
- tfa->supportFramework = supportYes;
- }
- else {
- *pbSupportFramework = 0;
- tfa->supportFramework = supportNo;
- error = Tfa98xx_Error_Ok;
- }
- }
-
- /* *pbSupportFramework only changed when error == Tfa98xx_Error_Ok */
- return error;
-}
-
-enum Tfa98xx_Error
- tfa98xx_dsp_write_speaker_parameters(struct tfa_device *tfa,
- int length, const unsigned char *p_speaker_bytes)
-{
- enum Tfa98xx_Error error;
- int bSupportDrc;
-
- if (p_speaker_bytes != NULL) {
- /* by design: keep the data opaque and no
- * interpreting/calculation */
- /* Use long WaitResult retry count */
- error = tfa_dsp_cmd_id_write(
- tfa,
- MODULE_SPEAKERBOOST,
- SB_PARAM_SET_LSMODEL, length,
- p_speaker_bytes);
- }
- else {
- error = Tfa98xx_Error_Bad_Parameter;
- }
-
- if (error != Tfa98xx_Error_Ok)
- return error;
-
- error = tfa98xx_dsp_support_drc(tfa, &bSupportDrc);
- if (error != Tfa98xx_Error_Ok)
- return error;
-
- if (bSupportDrc) {
- /* Need to set AgcGainInsert back to PRE,
- * as the SetConfig forces it to POST */
- uint8_t bytes[3] = { 0, 0, 0 };
-
- error = tfa_dsp_cmd_id_write(tfa,
- MODULE_SPEAKERBOOST,
- SB_PARAM_SET_AGCINS,
- 3,
- bytes);
- }
-
- return error;
-}
-
-enum Tfa98xx_Error
- tfa98xx_dsp_write_config(struct tfa_device *tfa, int length,
- const unsigned char *p_config_bytes)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- int bSupportDrc;
-
- error = tfa_dsp_cmd_id_write(tfa,
- MODULE_SPEAKERBOOST,
- SB_PARAM_SET_CONFIG, length,
- p_config_bytes);
- if (error != Tfa98xx_Error_Ok)
- return error;
-
- error = tfa98xx_dsp_support_drc(tfa, &bSupportDrc);
- if (error != Tfa98xx_Error_Ok)
- return error;
-
- if (bSupportDrc) {
- /* Need to set AgcGainInsert back to PRE,
- * as the SetConfig forces it to POST */
- uint8_t bytes[3] = { 0, 0, 0 };
-
- error = tfa_dsp_cmd_id_write(tfa,
- MODULE_SPEAKERBOOST,
- SB_PARAM_SET_AGCINS,
- 3,
- bytes);
- }
-
- return error;
-}
-
-/* load all the parameters for the DRC settings from a file */
-enum Tfa98xx_Error tfa98xx_dsp_write_drc(struct tfa_device *tfa,
- int length, const unsigned char *p_drc_bytes)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- if (p_drc_bytes != NULL) {
- error = tfa_dsp_cmd_id_write(tfa,
- MODULE_SPEAKERBOOST,
- SB_PARAM_SET_DRC, length,
- p_drc_bytes);
-
- }
- else {
- error = Tfa98xx_Error_Bad_Parameter;
- }
- return error;
-}
-
-enum Tfa98xx_Error tfa98xx_powerdown(struct tfa_device *tfa, int powerdown)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
-
- if (tfa->in_use == 0)
- return Tfa98xx_Error_NotOpen;
-
- error = TFA_SET_BF(tfa, PWDN, (uint16_t)powerdown);
-
- if (powerdown) {
- /* Workaround for ticket PLMA5337 */
- if (tfa->tfa_family == 2) {
- TFA_SET_BF_VOLATILE(tfa, AMPE, 0);
- }
- }
-
- return error;
-}
-
-enum Tfa98xx_Error
- tfa98xx_select_mode(struct tfa_device *tfa, enum Tfa98xx_Mode mode)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
-
- if (tfa->in_use == 0)
- return Tfa98xx_Error_NotOpen;
-
- if (error == Tfa98xx_Error_Ok) {
- switch (mode) {
-
- default:
- error = Tfa98xx_Error_Bad_Parameter;
- }
- }
-
- return error;
-}
-
-int tfa_set_bf(struct tfa_device *tfa, const uint16_t bf, const uint16_t value)
-{
- enum Tfa98xx_Error err;
- uint16_t regvalue, msk, oldvalue;
-
- /*
- * bitfield enum:
- * - 0..3 : len
- * - 4..7 : pos
- * - 8..15 : address
- */
- uint8_t len = bf & 0x0f;
- uint8_t pos = (bf >> 4) & 0x0f;
- uint8_t address = (bf >> 8) & 0xff;
-
- err = reg_read(tfa, address, ®value);
- if (err) {
- pr_err("Error getting bf :%d \n", -err);
- return -err;
- }
-
- oldvalue = regvalue;
- msk = ((1 << (len + 1)) - 1) << pos;
- regvalue &= ~msk;
- regvalue |= value << pos;
-
- /* Only write when the current register value is not the same as the new value */
- if (oldvalue != regvalue) {
- err = reg_write(tfa, address, regvalue);
- if (err) {
- pr_err("Error setting bf :%d \n", -err);
- return -err;
- }
- }
-
- return 0;
-}
-
-int tfa_set_bf_volatile(struct tfa_device *tfa, const uint16_t bf, const uint16_t value)
-{
- enum Tfa98xx_Error err;
- uint16_t regvalue, msk;
-
- /*
- * bitfield enum:
- * - 0..3 : len
- * - 4..7 : pos
- * - 8..15 : address
- */
- uint8_t len = bf & 0x0f;
- uint8_t pos = (bf >> 4) & 0x0f;
- uint8_t address = (bf >> 8) & 0xff;
-
- err = reg_read(tfa, address, ®value);
- if (err) {
- pr_err("Error getting bf :%d \n", -err);
- return -err;
- }
-
- msk = ((1 << (len + 1)) - 1) << pos;
- regvalue &= ~msk;
- regvalue |= value << pos;
-
- err = reg_write(tfa, address, regvalue);
- if (err) {
- pr_err("Error setting bf :%d \n", -err);
- return -err;
- }
-
- return 0;
-}
-
-int tfa_get_bf(struct tfa_device *tfa, const uint16_t bf)
-{
- enum Tfa98xx_Error err;
- uint16_t regvalue, msk;
- uint16_t value;
-
- /*
- * bitfield enum:
- * - 0..3 : len
- * - 4..7 : pos
- * - 8..15 : address
- */
- uint8_t len = bf & 0x0f;
- uint8_t pos = (bf >> 4) & 0x0f;
- uint8_t address = (bf >> 8) & 0xff;
-
- err = reg_read(tfa, address, ®value);
- if (err) {
- pr_err("Error getting bf :%d \n", -err);
- return -err;
- }
-
- msk = ((1 << (len + 1)) - 1) << pos;
- regvalue &= msk;
- value = regvalue >> pos;
-
- return value;
-}
-
-int tfa_set_bf_value(const uint16_t bf, const uint16_t bf_value, uint16_t *p_reg_value)
-{
- uint16_t regvalue, msk;
-
- /*
- * bitfield enum:
- * - 0..3 : len
- * - 4..7 : pos
- * - 8..15 : address
- */
- uint8_t len = bf & 0x0f;
- uint8_t pos = (bf >> 4) & 0x0f;
-
- regvalue = *p_reg_value;
-
- msk = ((1 << (len + 1)) - 1) << pos;
- regvalue &= ~msk;
- regvalue |= bf_value << pos;
-
- *p_reg_value = regvalue;
-
- return 0;
-}
-
-uint16_t tfa_get_bf_value(const uint16_t bf, const uint16_t reg_value)
-{
- uint16_t msk, value;
-
- /*
- * bitfield enum:
- * - 0..3 : len
- * - 4..7 : pos
- * - 8..15 : address
- */
- uint8_t len = bf & 0x0f;
- uint8_t pos = (bf >> 4) & 0x0f;
-
- msk = ((1 << (len + 1)) - 1) << pos;
- value = (reg_value & msk) >> pos;
-
- return value;
-}
-
-
-int tfa_write_reg(struct tfa_device *tfa, const uint16_t bf, const uint16_t reg_value)
-{
- enum Tfa98xx_Error err;
-
- /* bitfield enum - 8..15 : address */
- uint8_t address = (bf >> 8) & 0xff;
-
- err = reg_write(tfa, address, reg_value);
- if (err)
- return -err;
-
- return 0;
-}
-
-int tfa_read_reg(struct tfa_device *tfa, const uint16_t bf)
-{
- enum Tfa98xx_Error err;
- uint16_t regvalue;
-
- /* bitfield enum - 8..15 : address */
- uint8_t address = (bf >> 8) & 0xff;
-
- err = reg_read(tfa, address, ®value);
- if (err)
- return -err;
-
- return regvalue;
-}
-
-/*
- * powerup the coolflux subsystem and wait for it
- */
-enum Tfa98xx_Error tfa_cf_powerup(struct tfa_device *tfa)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- int tries, status;
-
- /* power on the sub system */
- TFA_SET_BF_VOLATILE(tfa, PWDN, 0);
-
- // wait until everything is stable, in case clock has been off
- if (tfa->verbose)
- pr_info("Waiting for DSP system stable...\n");
- for (tries = CFSTABLE_TRIES; tries > 0; tries--) {
- err = tfa98xx_dsp_system_stable(tfa, &status);
- _ASSERT(err == Tfa98xx_Error_Ok);
- if (status)
- break;
- else
- msleep_interruptible(10); /* wait 10ms to avoid busload */
- }
- if (tries == 0) {// timedout
- pr_err("DSP subsystem start timed out\n");
- return Tfa98xx_Error_StateTimedOut;
- }
-
- return err;
-}
-
-/*
- * Enable/Disable the I2S output for TFA1 devices
- * without TDM interface
- */
-static enum Tfa98xx_Error tfa98xx_aec_output(struct tfa_device *tfa, int enable)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
-
- if ((tfa->daimap & Tfa98xx_DAI_TDM) == Tfa98xx_DAI_TDM)
- return err;
-
- if (tfa->tfa_family == 1)
- err = -tfa_set_bf(tfa, TFA1_BF_I2SDOE, (enable != 0));
- else {
- pr_err("I2SDOE on unsupported family\n");
- err = Tfa98xx_Error_Not_Supported;
- }
-
- return err;
-}
-
-/*
- * Print the current state of the hardware manager
- * Device manager status information, man_state from TFA9888_N1B_I2C_regmap_V12
- */
-int is_94_N2_device(struct tfa_device *tfa)
-{
- return ((((tfa->rev) & 0xff) == 0x94) && (((tfa->rev >> 8) & 0xff) > 0x1a));
-}
-enum Tfa98xx_Error show_current_state(struct tfa_device *tfa)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- int manstate = -1;
-
- if (tfa->tfa_family == 2 && tfa->verbose) {
- if (is_94_N2_device(tfa))
- manstate = tfa_get_bf(tfa, TFA9894N2_BF_MANSTATE);
- else
- manstate = TFA_GET_BF(tfa, MANSTATE);
- if (manstate < 0)
- return -manstate;
-
- pr_debug("Current HW manager state: ");
-
- switch (manstate) {
- case 0: pr_debug("power_down_state \n");
- break;
- case 1: pr_debug("wait_for_source_settings_state \n");
- break;
- case 2: pr_debug("connnect_pll_input_state \n");
- break;
- case 3: pr_debug("disconnect_pll_input_state \n");
- break;
- case 4: pr_debug("enable_pll_state \n");
- break;
- case 5: pr_debug("enable_cgu_state \n");
- break;
- case 6: pr_debug("init_cf_state \n");
- break;
- case 7: pr_debug("enable_amplifier_state \n");
- break;
- case 8: pr_debug("alarm_state \n");
- break;
- case 9: pr_debug("operating_state \n");
- break;
- case 10: pr_debug("mute_audio_state \n");
- break;
- case 11: pr_debug("disable_cgu_pll_state \n");
- break;
- default:
- pr_debug("Unable to find current state \n");
- break;
- }
- }
-
- return err;
-}
-
-enum Tfa98xx_Error tfaGetFwApiVersion(struct tfa_device *tfa, unsigned char *pFirmwareVersion)
-{
- enum Tfa98xx_Error err = 0;
- char cmd_buf[4];
- int cmd_len, res_len;
-
- if (tfa == NULL)
- return Tfa98xx_Error_Bad_Parameter;
- if (!tfa->is_probus_device)
- {
- err = mem_read(tfa, FW_VAR_API_VERSION, 1, (int *)pFirmwareVersion);
- if (err) {
- pr_debug("%s Error: Unable to get API Version from DSP \n", __FUNCTION__);
- return err;
- }
- }
- else
- {
- cmd_len = 0x03;
-
- /* GetAPI: Command is 0x00 0x80 0xFE */
- cmd_buf[0] = 0x00;
- cmd_buf[1] = 0x80;
- cmd_buf[2] = 0xFE;
-
- /* Write the command.*/
-
- err = tfa98xx_write_dsp(tfa, cmd_len, (const char *)cmd_buf);
-
- /* Read the API Value.*/
- if (err == 0)
- {
- res_len = 3;
- err = tfa98xx_read_dsp(tfa, res_len, (unsigned char *)pFirmwareVersion);
-
- }
- }
- return err;
-
-}
-
-
-/*
- * start the speakerboost algorithm
- * this implies a full system startup when the system was not already started
- *
- */
-enum Tfa98xx_Error tfaRunSpeakerBoost(struct tfa_device *tfa, int force, int profile)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- int value;
-
- if (force) {
- err = tfaRunColdStartup(tfa, profile);
- if (err) return err;
- }
-
- /* Returns 1 when device is "cold" and 0 when device is warm */
- value = tfa_is_cold(tfa);
-
- pr_debug("Startup of device [%s] is a %sstart\n", tfaContDeviceName(tfa->cnt, tfa->dev_idx), value ? "cold" : "warm");
- /* cold start and not tap profile */
- if (value) {
- /* Run startup and write all files */
- err = tfaRunSpeakerStartup(tfa, force, profile);
- if (err) return err;
-
- /* Save the current profile and set the vstep to 0 */
- /* This needs to be overwriten even in CF bypass */
- tfa_dev_set_swprof(tfa, (unsigned short)profile);
- tfa_dev_set_swvstep(tfa, 0);
-
- /* Synchonize I/V delay on 96/97 at cold start */
- if ((tfa->tfa_family == 1) && (tfa->daimap == Tfa98xx_DAI_TDM))
- tfa->sync_iv_delay = 1;
- }
-
- return err;
-}
-
-enum Tfa98xx_Error tfaRunSpeakerStartup(struct tfa_device *tfa, int force, int profile)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
-
- if (!force) { // in case of force CF already runnning
- err = tfaRunStartup(tfa, profile);
- PRINT_ASSERT(err);
- if (err)
- return err;
-
- /* Startup with CF in bypass then return here */
- if (tfa_cf_enabled(tfa) == 0)
- return err;
-
- /* respond to external DSP: -1:none, 0:no_dsp, 1:cold, 2:warm */
- if (tfa->ext_dsp == -1) {
- err = tfaRunStartDSP(tfa);
- if (err)
- return err;
- }
- }
-
- /* Set auto_copy_mtp_to_iic (bit 5 of A3) to 1 */
- tfa98xx_auto_copy_mtp_to_iic(tfa);
-
- err = tfaGetFwApiVersion(tfa, (unsigned char *)&tfa->fw_itf_ver[0]);
- if (err) {
- pr_debug("[%s] cannot get FWAPI error = %d \n", __FUNCTION__, err);
- return err;
- }
- /* write all the files from the device list */
- err = tfaContWriteFiles(tfa);
- if (err) {
- pr_debug("[%s] tfaContWriteFiles error = %d \n", __FUNCTION__, err);
- return err;
- }
-
- /* write all the files from the profile list (use volumstep 0) */
- err = tfaContWriteFilesProf(tfa, profile, 0);
- if (err) {
- pr_debug("[%s] tfaContWriteFilesProf error = %d \n", __FUNCTION__, err);
- return err;
- }
-
- return err;
-}
-
-/*
- * Run calibration
- */
-enum Tfa98xx_Error tfaRunSpeakerCalibration(struct tfa_device *tfa)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- int calibrateDone;
-
- /* return if there is no audio running */
- if ((tfa->tfa_family == 2) && TFA_GET_BF(tfa, NOCLK))
- return Tfa98xx_Error_NoClock;
-
- /* When MTPOTC is set (cal=once) unlock key2 */
- if (TFA_GET_BF(tfa, MTPOTC) == 1) {
- tfa98xx_key2(tfa, 0);
- }
-
- /* await calibration, this should return ok */
- err = tfaRunWaitCalibration(tfa, &calibrateDone);
- if (err == Tfa98xx_Error_Ok) {
- err = tfa_dsp_get_calibration_impedance(tfa);
- PRINT_ASSERT(err);
- }
-
- /* When MTPOTC is set (cal=once) re-lock key2 */
- if (TFA_GET_BF(tfa, MTPOTC) == 1) {
- tfa98xx_key2(tfa, 1);
- }
-
- return err;
-}
-
-enum Tfa98xx_Error tfaRunColdboot(struct tfa_device *tfa, int state)
-{
-#define CF_CONTROL 0x8100
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- int tries = 10;
-
- /* repeat set ACS bit until set as requested */
- while (state != TFA_GET_BF(tfa, ACS)) {
- /* set colstarted in CF_CONTROL to force ACS */
- err = mem_write(tfa, CF_CONTROL, state, Tfa98xx_DMEM_IOMEM);
- PRINT_ASSERT(err);
-
- if (tries-- == 0) {
- pr_debug("coldboot (ACS) did not %s\n", state ? "set" : "clear");
- return Tfa98xx_Error_Other;
- }
- }
-
- return err;
-}
-
-
-
-/*
- * load the patch if any
- * else tell no loaded
- */
-static enum Tfa98xx_Error tfa_run_load_patch(struct tfa_device *tfa)
-{
- return tfaContWritePatch(tfa);
-}
-
-/*
- * this will load the patch witch will implicitly start the DSP
- * if no patch is available the DPS is started immediately
- */
-enum Tfa98xx_Error tfaRunStartDSP(struct tfa_device *tfa)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
-
- err = tfa_run_load_patch(tfa);
- if (err) { /* patch load is fatal so return immediately*/
- return err;
- }
-
- /* Clear count_boot, should be reset to 0 before the DSP reset is released */
- err = mem_write(tfa, 512, 0, Tfa98xx_DMEM_XMEM);
- PRINT_ASSERT(err);
-
- /* Reset DSP once for sure after initializing */
- if (err == Tfa98xx_Error_Ok) {
- err = tfa98xx_dsp_reset(tfa, 0);
- PRINT_ASSERT(err);
- }
-
- /* Sample rate is needed to set the correct tables */
- err = tfa98xx_dsp_write_tables(tfa, TFA_GET_BF(tfa, AUDFS));
- PRINT_ASSERT(err);
-
- return err;
-}
-
-/*
- * start the clocks and wait until the AMP is switching
- * on return the DSP sub system will be ready for loading
- */
-enum Tfa98xx_Error tfaRunStartup(struct tfa_device *tfa, int profile)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- nxpTfaDeviceList_t *dev = tfaContDevice(tfa->cnt, tfa->dev_idx);
- int i, noinit = 0, audfs = 0, fractdel = 0;
-
- if (dev == NULL)
- return Tfa98xx_Error_Fail;
-
- if (dev->bus) /* no i2c device, do nothing */
- return Tfa98xx_Error_Ok;
-
- /* process the device list to see if the user implemented the noinit */
- for (i = 0; i < dev->length; i++) {
- if (dev->list[i].type == dscNoInit) {
- noinit = 1;
- break;
- }
- }
-
- if (!noinit) {
- /* Read AUDFS & FRACTDEL prior to (re)init. */
- audfs = TFA_GET_BF(tfa, AUDFS);
- fractdel = TFA_GET_BF(tfa, FRACTDEL);
- /* load the optimal TFA98XX in HW settings */
- err = tfa98xx_init(tfa);
- PRINT_ASSERT(err);
-
- /* Restore audfs & fractdel after coldboot, so we can calibrate with correct fs setting.
- * in case something else was given in cnt file, profile below will apply this. */
- TFA_SET_BF(tfa, AUDFS, audfs);
- TFA_SET_BF(tfa, FRACTDEL, fractdel);
- }
- else {
- pr_debug("\nWarning: No init keyword found in the cnt file. Init is skipped! \n");
- }
-
- /* I2S settings to define the audio input properties
- * these must be set before the subsys is up */
- // this will run the list until a non-register item is encountered
- err = tfaContWriteRegsDev(tfa); // write device register settings
- PRINT_ASSERT(err);
- // also write register the settings from the default profile
- // NOTE we may still have ACS=1 so we can switch sample rate here
- err = tfaContWriteRegsProf(tfa, profile);
- PRINT_ASSERT(err);
-
- /* Factory trimming for the Boost converter */
- tfa98xx_factory_trimmer(tfa);
-
- /* Go to the initCF state */
- tfa_dev_set_state(tfa, TFA_STATE_INIT_CF, strstr(tfaContProfileName(tfa->cnt, tfa->dev_idx, profile), ".cal") != NULL);
-
- err = show_current_state(tfa);
-
- return err;
-}
-
-/*
- * run the startup/init sequence and set ACS bit
- */
-enum Tfa98xx_Error tfaRunColdStartup(struct tfa_device *tfa, int profile)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
-
- err = tfaRunStartup(tfa, profile);
- PRINT_ASSERT(err);
- if (err)
- return err;
-
- if (!tfa->is_probus_device) {
- /* force cold boot */
- err = tfaRunColdboot(tfa, 1); // set ACS
- PRINT_ASSERT(err);
- if (err)
- return err;
- }
-
- /* start */
- err = tfaRunStartDSP(tfa);
- PRINT_ASSERT(err);
-
- return err;
-}
-
-/*
- *
- */
-enum Tfa98xx_Error tfaRunMute(struct tfa_device *tfa)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- int status;
- int tries = 0;
-
- /* signal the TFA98XX to mute */
- if (tfa->tfa_family == 1) {
- err = tfa98xx_set_mute(tfa, Tfa98xx_Mute_Amplifier);
-
- if (err == Tfa98xx_Error_Ok) {
- /* now wait for the amplifier to turn off */
- do {
- status = TFA_GET_BF(tfa, SWS);
- if (status != 0)
- msleep_interruptible(10); /* wait 10ms to avoid busload */
- else
- break;
- tries++;
- } while (tries < AMPOFFWAIT_TRIES);
-
-
- if (tfa->verbose)
- pr_debug("-------------------- muted --------------------\n");
-
- /*The amplifier is always switching*/
- if (tries == AMPOFFWAIT_TRIES)
- return Tfa98xx_Error_Other;
- }
- }
-
- return err;
-}
-/*
- *
- */
-enum Tfa98xx_Error tfaRunUnmute(struct tfa_device *tfa)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
-
- /* signal the TFA98XX to mute */
- err = tfa98xx_set_mute(tfa, Tfa98xx_Mute_Off);
-
- if (tfa->verbose)
- pr_debug("-------------------unmuted ------------------\n");
-
- return err;
-}
-
-static void individual_calibration_results(struct tfa_device *tfa)
-{
- int value_P, value_S;
-
- /* Read the calibration result in xmem (529=primary channel) (530=secondary channel) */
- mem_read(tfa, 529, 1, &value_P);
- mem_read(tfa, 530, 1, &value_S);
-
- if (value_P != 1 && value_S != 1)
- pr_debug("Calibration failed on both channels! \n");
- else if (value_P != 1) {
- pr_debug("Calibration failed on Primary (Left) channel! \n");
- TFA_SET_BF_VOLATILE(tfa, SSLEFTE, 0); /* Disable the sound for the left speaker */
- }
- else if (value_S != 1) {
- pr_debug("Calibration failed on Secondary (Right) channel! \n");
- TFA_SET_BF_VOLATILE(tfa, SSRIGHTE, 0); /* Disable the sound for the right speaker */
- }
-
- TFA_SET_BF_VOLATILE(tfa, AMPINSEL, 0); /* Set amplifier input to TDM */
- TFA_SET_BF_VOLATILE(tfa, SBSL, 1);
-}
-
-/*
- * wait for calibrateDone
- */
-enum Tfa98xx_Error tfaRunWaitCalibration(struct tfa_device *tfa, int *calibrateDone)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- int tries = 0, mtp_busy = 1, tries_mtp_busy = 0;
-
- *calibrateDone = 0;
-
- /* in case of calibrate once wait for MTPEX */
- if (TFA_GET_BF(tfa, MTPOTC)) {
- // Check if MTP_busy is clear!
- while (tries_mtp_busy < MTPBWAIT_TRIES)
- {
- mtp_busy = tfa_dev_get_mtpb(tfa);
- if (mtp_busy == 1)
- msleep_interruptible(10); /* wait 10ms to avoid busload */
- else
- break;
- tries_mtp_busy++;
- }
-
- if (tries_mtp_busy < MTPBWAIT_TRIES) {
- /* Because of the msleep TFA98XX_API_WAITRESULT_NTRIES is way to long!
- * Setting this to 25 will take it atleast 25*50ms = 1.25 sec
- */
- while ((*calibrateDone == 0) && (tries < MTPEX_WAIT_NTRIES)) {
- *calibrateDone = TFA_GET_BF(tfa, MTPEX);
- if (*calibrateDone == 1)
- break;
- msleep_interruptible(50); /* wait 50ms to avoid busload */
- tries++;
- }
-
- if (tries >= MTPEX_WAIT_NTRIES) {
- tries = TFA98XX_API_WAITRESULT_NTRIES;
- }
- }
- else {
- pr_err("MTP bussy after %d tries\n", MTPBWAIT_TRIES);
- }
- }
-
- /* poll xmem for calibrate always
- * calibrateDone = 0 means "calibrating",
- * calibrateDone = -1 (or 0xFFFFFF) means "fails"
- * calibrateDone = 1 means calibration done
- */
- while ((*calibrateDone != 1) && (tries < TFA98XX_API_WAITRESULT_NTRIES)) {
- err = mem_read(tfa, TFA_FW_XMEM_CALIBRATION_DONE, 1, calibrateDone);
- if (*calibrateDone == -1)
- break;
- tries++;
- }
-
- if (*calibrateDone != 1) {
- pr_err("Calibration failed! \n");
- err = Tfa98xx_Error_Bad_Parameter;
- }
- else if (tries == TFA98XX_API_WAITRESULT_NTRIES) {
- pr_debug("Calibration has timedout! \n");
- err = Tfa98xx_Error_StateTimedOut;
- }
- else if (tries_mtp_busy == 1000) {
- pr_err("Calibrate Failed: MTP_busy stays high! \n");
- err = Tfa98xx_Error_StateTimedOut;
- }
-
- /* Give reason why calibration failed! */
- if (err != Tfa98xx_Error_Ok) {
- if ((tfa->tfa_family == 2) && (TFA_GET_BF(tfa, REFCKSEL) == 1)) {
- pr_err("Unable to calibrate the device with the internal clock! \n");
- }
- }
-
- /* Check which speaker calibration failed. Only for 88C */
- if ((err != Tfa98xx_Error_Ok) && ((tfa->rev & 0x0FFF) == 0xc88)) {
- individual_calibration_results(tfa);
- }
-
- return err;
-}
-
-/*
- * tfa_dev_start will only do the basics: Going from powerdown to operating or a profile switch.
- * for calibrating or akoustic shock handling use the tfa98xxCalibration function.
- */
-enum tfa_error tfa_dev_start(struct tfa_device *tfa, int next_profile, int vstep)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- int active_profile = -1;
-
- /* Get currentprofile */
- active_profile = tfa_dev_get_swprof(tfa);
- if (active_profile == 0xff)
- active_profile = -1;
-
- /* TfaRun_SpeakerBoost implies un-mute */
- pr_debug("Active_profile:%s, next_profile:%s\n",
- tfaContProfileName(tfa->cnt, tfa->dev_idx, active_profile),
- tfaContProfileName(tfa->cnt, tfa->dev_idx, next_profile));
-
- err = show_current_state(tfa);
-
- if (tfa->tfa_family == 1) { /* TODO move this to ini file */
- /* Enable I2S output on TFA1 devices without TDM */
- err = tfa98xx_aec_output(tfa, 1);
- if (err != Tfa98xx_Error_Ok)
- goto error_exit;
- }
-
- if (tfa->bus != 0) { /* non i2c */
-#ifndef __KERNEL__
- tfadsp_fw_start(tfa, next_profile, vstep);
-#endif /* __KERNEL__ */
- }
- else {
- /* Check if we need coldstart or ACS is set */
- err = tfaRunSpeakerBoost(tfa, 0, next_profile);
- if (err != Tfa98xx_Error_Ok)
- goto error_exit;
-
- /* Make sure internal oscillator is running for DSP devices (non-dsp and max1 this is no-op) */
- tfa98xx_set_osc_powerdown(tfa, 0);
-
- /* Go to the Operating state */
- tfa_dev_set_state(tfa, TFA_STATE_OPERATING | TFA_STATE_MUTE, 0);
- }
- active_profile = tfa_dev_get_swprof(tfa);
-
- /* Profile switching */
- if ((next_profile != active_profile && active_profile >= 0)) {
- err = tfaContWriteProfile(tfa, next_profile, vstep);
- if (err != Tfa98xx_Error_Ok)
- goto error_exit;
- }
-
- /* If the profile contains the .standby suffix go to powerdown
- * else we should be in operating state
- */
- if (strstr(tfaContProfileName(tfa->cnt, tfa->dev_idx, next_profile), ".standby") != NULL) {
- tfa_dev_set_swprof(tfa, (unsigned short)next_profile);
- tfa_dev_set_swvstep(tfa, (unsigned short)vstep);
- goto error_exit;
- }
-
- err = show_current_state(tfa);
-
- if ((TFA_GET_BF(tfa, CFE) != 0) && (vstep != tfa->vstep) && (vstep != -1)) {
- err = tfaContWriteFilesVstep(tfa, next_profile, vstep);
- if (err != Tfa98xx_Error_Ok)
- goto error_exit;
- }
-
- /* Always search and apply filters after a startup */
- err = tfa_set_filters(tfa, next_profile);
- if (err != Tfa98xx_Error_Ok)
- goto error_exit;
-
- tfa_dev_set_swprof(tfa, (unsigned short)next_profile);
- tfa_dev_set_swvstep(tfa, (unsigned short)vstep);
-
- /* PLMA5539: Gives information about current setting of powerswitch */
- if (tfa->verbose) {
- if (!tfa98xx_powerswitch_is_enabled(tfa))
- pr_info("Device start without powerswitch enabled!\n");
- }
-
-error_exit:
- show_current_state(tfa);
-
- return err;
-}
-
-enum tfa_error tfa_dev_stop(struct tfa_device *tfa)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
-
- /* mute */
- tfaRunMute(tfa);
-
- /* Make sure internal oscillator is not running for DSP devices (non-dsp and max1 this is no-op) */
- tfa98xx_set_osc_powerdown(tfa, 1);
-
- /* powerdown CF */
- err = tfa98xx_powerdown(tfa, 1);
- if (err != Tfa98xx_Error_Ok)
- return err;
-
- /* disable I2S output on TFA1 devices without TDM */
- err = tfa98xx_aec_output(tfa, 0);
-
- return err;
-}
-
-/*
- * int registers and coldboot dsp
- */
-int tfa_reset(struct tfa_device *tfa)
-{
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- int state = -1;
- int retry_cnt = 0;
-
- /* Check device state. Print warning if reset is done from other state than powerdown (when verbose) */
- state = tfa_dev_get_state(tfa);
- if (tfa->verbose) {
- if (((tfa->tfa_family == 1) && state != TFA_STATE_RESET) ||
- ((tfa->tfa_family == 2) && state != TFA_STATE_POWERDOWN)) {
- pr_info("WARNING: Device reset should be performed in POWERDOWN state\n");
- }
- }
-
- /* Split TFA1 behavior from TFA2*/
- if (tfa->tfa_family == 1) {
- err = TFA_SET_BF(tfa, I2CR, 1);
- if (err)
- return err;
- err = tfa98xx_powerdown(tfa, 0);
- if (err)
- return err;
- err = tfa_cf_powerup(tfa);
- if (err)
- return err;
- err = tfaRunColdboot(tfa, 1);
- if (err)
- return err;
- err = TFA_SET_BF(tfa, I2CR, 1);
- }
- else {
- /* Probus devices needs extra protection to ensure proper reset
- behavior, this step is valid only in state other than powerdown */
- if (tfa->is_probus_device && state != TFA_STATE_POWERDOWN) {
- err = TFA_SET_BF_VOLATILE(tfa, AMPE, 0);
- if (err)
- return err;
- err = tfa98xx_powerdown(tfa, 1);
- if (err)
- return err;
- }
-
- err = TFA_SET_BF_VOLATILE(tfa, I2CR, 1);
- if (err)
- return err;
-
- /* Restore MANSCONF to POR state */
- err = TFA_SET_BF_VOLATILE(tfa, MANSCONF, 0);
- if (err)
- return err;
-
- /* Probus devices HW are already reseted here,
- Last step is to send init message to softDSP */
- if (tfa->is_probus_device) {
- if (tfa->ext_dsp > 0) {
- err = tfa98xx_init_dsp(tfa);
- /* ext_dsp status from warm to cold after reset */
- if (tfa->ext_dsp == 2) {
- tfa->ext_dsp = 1;
- }
- }
- }
- else {
- /* Restore MANCOLD to POR state */
- TFA_SET_BF_VOLATILE(tfa, MANCOLD, 1);
-
- /* Coolflux has to be powered on to ensure proper ACS
- bit state */
-
- /* Powerup CF to access CF io */
- err = tfa98xx_powerdown(tfa, 0);
- if (err)
- return err;
-
- /* For clock */
- err = tfa_cf_powerup(tfa);
- if (err)
- return err;
-
- /* Force cold boot */
- err = tfaRunColdboot(tfa, 1); /* Set ACS */
- if (err)
- return err;
-
- /* Set PWDN = 1, this will transfer device into powerdown state */
- err = TFA_SET_BF_VOLATILE(tfa, PWDN, 1);
- if (err)
- return err;
-
- /* 88 needs SBSL on top of PWDN bit to start transition,
- for 92 and 94 this doesn't matter */
- err = TFA_SET_BF_VOLATILE(tfa, SBSL, 1);
- if (err)
- return err;
-
- /* Powerdown state should be reached within 1ms */
- for (retry_cnt = 0; retry_cnt < TFA98XX_WAITRESULT_NTRIES; retry_cnt++) {
- if (is_94_N2_device(tfa))
- state = tfa_get_bf(tfa, TFA9894N2_BF_MANSTATE);
- else
- state = TFA_GET_BF(tfa, MANSTATE);
- if (state < 0) {
- return err;
- }
-
- /* Check for MANSTATE=Powerdown (0) */
- if (state == 0)
- break;
- msleep_interruptible(2);
- }
-
- /* Reset all I2C registers to default values,
- now device state is consistent, same as after powerup */
- err = TFA_SET_BF(tfa, I2CR, 1);
- }
- }
-
- return err;
-}
-
-/*
- * Write all the bytes specified by num_bytes and data
- */
-enum Tfa98xx_Error
- tfa98xx_write_data(struct tfa_device *tfa,
- unsigned char subaddress, int num_bytes,
- const unsigned char data[])
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- /* subaddress followed by data */
- const int bytes2write = num_bytes + 1;
- unsigned char *write_data;
-
- if (num_bytes > TFA2_MAX_PARAM_SIZE)
- return Tfa98xx_Error_Bad_Parameter;
-
- write_data = (unsigned char *)kmem_cache_alloc(tfa->cachep, GFP_KERNEL);
- if (write_data == NULL)
- return Tfa98xx_Error_Fail;
-
- write_data[0] = subaddress;
- memcpy(&write_data[1], data, num_bytes);
-
- error = tfa98xx_write_raw(tfa, bytes2write, write_data);
-
- kmem_cache_free(tfa->cachep, write_data);
- return error;
-}
-
-/*
- * fill the calibration value as milli ohms in the struct
- *
- * assume that the device has been calibrated
- */
-enum Tfa98xx_Error tfa_dsp_get_calibration_impedance(struct tfa_device *tfa)
-{
- enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
- unsigned char bytes[3 * 2] = { 0 };
- int nr_bytes, i, data[2], calibrateDone, spkr_count = 0, cal_idx = 0;
- unsigned int scaled_data;
- int tries = 0;
-
- error = tfa_supported_speakers(tfa, &spkr_count);
-
- if (tfa_dev_mtp_get(tfa, TFA_MTP_OTC)) {
- pr_debug("Getting calibration values from MTP\n");
-
- if ((tfa->rev & 0xFF) == 0x88) {
- for (i = 0; i < spkr_count; i++) {
- if (i == 0)
- tfa->mohm[i] = tfa_dev_mtp_get(tfa, TFA_MTP_RE25_PRIM);
- else
- tfa->mohm[i] = tfa_dev_mtp_get(tfa, TFA_MTP_RE25_SEC);
- }
- }
- else {
- tfa->mohm[0] = tfa_dev_mtp_get(tfa, TFA_MTP_RE25);
- }
- }
- else {
- pr_debug("Getting calibration values from Speakerboost\n");
-
- /* Make sure the calibrateDone bit is set before getting the values from speakerboost!
- * This does not work for 72 (because the dsp cannot set this bit)
- */
- if (!tfa->is_probus_device) {
- /* poll xmem for calibrate always
- * calibrateDone = 0 means "calibrating",
- * calibrateDone = -1 (or 0xFFFFFF) means "fails"
- * calibrateDone = 1 means calibration done
- */
- calibrateDone = 0;
- while ((calibrateDone != 1) && (tries < TFA98XX_API_WAITRESULT_NTRIES)) {
- error = mem_read(tfa, TFA_FW_XMEM_CALIBRATION_DONE, 1, &calibrateDone);
- if (calibrateDone == 1)
- break;
- tries++;
- }
-
- if (calibrateDone != 1) {
- pr_err("Calibration failed! \n");
- error = Tfa98xx_Error_Bad_Parameter;
- }
- else if (tries == TFA98XX_API_WAITRESULT_NTRIES) {
- pr_debug("Calibration has timedout! \n");
- error = Tfa98xx_Error_StateTimedOut;
- }
- }
- /* SoftDSP interface differs from hw-dsp interfaces */
- if (tfa->is_probus_device && tfa->cnt->ndev > 1) {
- spkr_count = tfa->cnt->ndev;
- }
-
- nr_bytes = spkr_count * 3;
- error = tfa_dsp_cmd_id_write_read(tfa, MODULE_SPEAKERBOOST, SB_PARAM_GET_RE25C, nr_bytes, bytes);
- if (error == Tfa98xx_Error_Ok) {
- tfa98xx_convert_bytes2data(nr_bytes, bytes, data);
-
- for (i = 0; i < spkr_count; i++) {
-
- /* for probus devices, calibration values coming from soft-dsp speakerboost,
- are ordered in a different way. Re-align to standard representation. */
- cal_idx = i;
- if ((tfa->is_probus_device && tfa->dev_idx >= 1)) {
- cal_idx = 0;
- }
-
- /* signed data has a limit of 30 Ohm */
- scaled_data = data[i];
-
- if (tfa->tfa_family == 2)
- tfa->mohm[cal_idx] = (scaled_data * 1000) / TFA2_FW_ReZ_SCALE;
- else
- tfa->mohm[cal_idx] = (scaled_data * 1000) / TFA1_FW_ReZ_SCALE;
- }
- }
- }
-
- return error;
-}
-
-/* start count from 1, 0 is invalid */
-int tfa_dev_get_swprof(struct tfa_device *tfa)
-{
- return (tfa->dev_ops.get_swprof)(tfa);
-}
-
-int tfa_dev_set_swprof(struct tfa_device *tfa, unsigned short new_value)
-{
- return (tfa->dev_ops.set_swprof)(tfa, new_value + 1);
-}
-
-/* same value for all channels
- * start count from 1, 0 is invalid */
-int tfa_dev_get_swvstep(struct tfa_device *tfa)
-{
- return (tfa->dev_ops.get_swvstep)(tfa);
-}
-
-int tfa_dev_set_swvstep(struct tfa_device *tfa, unsigned short new_value)
-{
- return (tfa->dev_ops.set_swvstep)(tfa, new_value + 1);
-}
-
-/*
- function overload for MTPB
- */
-int tfa_dev_get_mtpb(struct tfa_device *tfa)
-{
- return (tfa->dev_ops.get_mtpb)(tfa);
-}
-
-int tfa_is_cold(struct tfa_device *tfa)
-{
- int value;
-
- /*
- * check for cold boot status
- */
- if (tfa->is_probus_device) {
- if (tfa->ext_dsp > 0) {
- if (tfa->ext_dsp == 2)
- value = 0; // warm
- else /* no dsp or cold */
- value = 1; // cold
- }
- else {
- value = (TFA_GET_BF(tfa, MANSCONF) == 0);
- }
- }
- else {
- value = TFA_GET_BF(tfa, ACS);
- }
-
- return value;
-}
-
-int tfa_needs_reset(struct tfa_device *tfa)
-{
- int value;
-
- /* checks if the DSP commands SetAlgoParams and SetMBDrc
- * need a DSP reset (now: at coldstart or during calibration)
- */
- if (tfa_is_cold(tfa) == 1 || tfa->needs_reset == 1)
- value = 1;
- else
- value = 0;
-
- return value;
-}
-
-int tfa_cf_enabled(struct tfa_device *tfa)
-{
- int value;
-
- /* For 72 there is no CF */
- if (tfa->is_probus_device) {
- value = (tfa->ext_dsp != 0);
- }
- else {
- value = TFA_GET_BF(tfa, CFE);
- }
-
- return value;
-}
-
-#define NR_COEFFS 6
-#define NR_BIQUADS 28
-#define BQ_SIZE (3 * NR_COEFFS)
-#define DSP_MSG_OVERHEAD 27
-
-#pragma pack (push, 1)
-struct dsp_msg_all_coeff {
- uint8_t select_eq[3];
- uint8_t biquad[NR_BIQUADS][NR_COEFFS][3];
-};
-#pragma pack (pop)
-
-/* number of biquads for each equalizer */
-static const int eq_biquads[] = {
- 10, 10, 2, 2, 2, 2
-};
-
-#define NR_EQ (int)(sizeof(eq_biquads) / sizeof(int))
-
-enum Tfa98xx_Error dsp_partial_coefficients(struct tfa_device *tfa, uint8_t *prev, uint8_t *next)
-{
- uint8_t bq, eq;
- int eq_offset;
- int new_cost, old_cost;
- uint32_t eq_biquad_mask[NR_EQ];
- enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
- struct dsp_msg_all_coeff *data1 = (struct dsp_msg_all_coeff *)prev;
- struct dsp_msg_all_coeff *data2 = (struct dsp_msg_all_coeff *)next;
-
- old_cost = DSP_MSG_OVERHEAD + 3 + sizeof(struct dsp_msg_all_coeff);
- new_cost = 0;
-
- eq_offset = 0;
- for (eq = 0; eq < NR_EQ; eq++) {
- uint8_t *eq1 = &data1->biquad[eq_offset][0][0];
- uint8_t *eq2 = &data2->biquad[eq_offset][0][0];
-
- eq_biquad_mask[eq] = 0;
-
- if (memcmp(eq1, eq2, BQ_SIZE*eq_biquads[eq]) != 0) {
- int nr_bq = 0;
- int bq_sz, eq_sz;
-
- for (bq = 0; bq < eq_biquads[eq]; bq++) {
- uint8_t *bq1 = &eq1[bq*BQ_SIZE];
- uint8_t *bq2 = &eq2[bq*BQ_SIZE];
-
- if (memcmp(bq1, bq2, BQ_SIZE) != 0) {
- eq_biquad_mask[eq] |= (1 << bq);
- nr_bq++;
- }
- }
-
- bq_sz = (2 * 3 + BQ_SIZE) * nr_bq;
- eq_sz = 2 * 3 + BQ_SIZE * eq_biquads[eq];
-
- /* dsp message i2c transaction overhead */
- bq_sz += DSP_MSG_OVERHEAD * nr_bq;
- eq_sz += DSP_MSG_OVERHEAD;
-
- if (bq_sz >= eq_sz) {
- eq_biquad_mask[eq] = 0xffffffff;
-
- new_cost += eq_sz;
-
- }
- else {
- new_cost += bq_sz;
- }
- }
- pr_debug("eq_biquad_mask[%d] = 0x%.8x\n", eq, eq_biquad_mask[eq]);
-
- eq_offset += eq_biquads[eq];
- }
-
- pr_debug("cost for writing all coefficients = %d\n", old_cost);
- pr_debug("cost for writing changed coefficients = %d\n", new_cost);
-
- if (new_cost >= old_cost) {
- const int buffer_sz = 3 + sizeof(struct dsp_msg_all_coeff);
- uint8_t *buffer;
-
- buffer = kmalloc(buffer_sz, GFP_KERNEL);
- if (buffer == NULL)
- return Tfa98xx_Error_Fail;
-
- /* cmd id */
- buffer[0] = 0x00;
- buffer[1] = 0x82;
- buffer[2] = 0x00;
-
- /* parameters */
- memcpy(&buffer[3], data2, sizeof(struct dsp_msg_all_coeff));
-
- err = dsp_msg(tfa, buffer_sz, (const char *)buffer);
-
- kfree(buffer);
- if (err)
- return err;
-
- }
- else {
- eq_offset = 0;
- for (eq = 0; eq < NR_EQ; eq++) {
- uint8_t *eq2 = &data2->biquad[eq_offset][0][0];
-
- if (eq_biquad_mask[eq] == 0xffffffff) {
- const int msg_sz = 6 + BQ_SIZE * eq_biquads[eq];
- uint8_t *msg;
-
- msg = kmalloc(msg_sz, GFP_KERNEL);
- if (msg == NULL)
- return Tfa98xx_Error_Fail;
-
- /* cmd id */
- msg[0] = 0x00;
- msg[1] = 0x82;
- msg[2] = 0x00;
-
- /* select eq and bq */
- msg[3] = 0x00;
- msg[4] = eq + 1;
- msg[5] = 0x00; /* all biquads */
-
- /* biquad parameters */
- memcpy(&msg[6], eq2, BQ_SIZE * eq_biquads[eq]);
-
- err = dsp_msg(tfa, msg_sz, (const char *)msg);
-
- kfree(msg);
- if (err)
- return err;
-
- }
- else if (eq_biquad_mask[eq] != 0) {
- for (bq = 0; bq < eq_biquads[eq]; bq++) {
-
- if (eq_biquad_mask[eq] & (1 << bq)) {
- uint8_t *bq2 = &eq2[bq*BQ_SIZE];
- const int msg_sz = 6 + BQ_SIZE;
- uint8_t *msg;
-
- msg = kmem_cache_alloc(tfa->cachep, GFP_KERNEL);
- if (msg == NULL)
- return Tfa98xx_Error_Fail;
-
- /* cmd id */
- msg[0] = 0x00;
- msg[1] = 0x82;
- msg[2] = 0x00;
-
- /* select eq and bq*/
- msg[3] = 0x00;
- msg[4] = eq + 1;
- msg[5] = bq + 1;
-
- /* biquad parameters */
- memcpy(&msg[6], bq2, BQ_SIZE);
-
- err = dsp_msg(tfa, msg_sz, (const char *)msg);
-
- kmem_cache_free(tfa->cachep, msg);
- if (err)
- return err;
- }
- }
- }
- eq_offset += eq_biquads[eq];
- }
- }
-
- return err;
-}
-
-/* fill context info */
-int tfa_dev_probe(int slave, struct tfa_device *tfa)
-{
- uint16_t rev;
-
- tfa->slave_address = (unsigned char)slave;
-
- /* read revid via low level hal, register 3 */
- if (tfa98xx_read_register16(tfa, 3, &rev) != Tfa98xx_Error_Ok) {
- PRINT("\nError: Unable to read revid from slave:0x%02x \n", slave);
- return -1;
- }
-
- tfa->rev = rev;
- tfa->dev_idx = -1;
- tfa->state = TFA_STATE_UNKNOWN;
- tfa->p_regInfo = NULL;
-
- tfa_set_query_info(tfa);
-
- tfa->in_use = 1;
-
- return 0;
-}
-
-enum tfa_error tfa_dev_set_state(struct tfa_device *tfa, enum tfa_state state, int is_calibration)
-{
- enum tfa_error err = tfa_error_ok;
- int loop = 50, ready = 0;
- int count;
-
- /* Base states */
- /* Do not change the order of setting bits as this is important! */
- switch (state & 0x0f) {
- case TFA_STATE_POWERDOWN: /* PLL in powerdown, Algo up */
- break;
- case TFA_STATE_INIT_HW: /* load I2C/PLL hardware setting (~wait2srcsettings) */
- break;
- case TFA_STATE_INIT_CF: /* coolflux HW access possible (~initcf) */
- /* Start with SBSL=0 to stay in initCF state */
- if (!tfa->is_probus_device)
- TFA_SET_BF(tfa, SBSL, 0);
-
- /* We want to leave Wait4SrcSettings state for max2 */
- if (tfa->tfa_family == 2)
- TFA_SET_BF(tfa, MANSCONF, 1);
-
- /* And finally set PWDN to 0 to leave powerdown state */
- TFA_SET_BF(tfa, PWDN, 0);
-
- /* Make sure the DSP is running! */
- do {
- err = tfa98xx_dsp_system_stable(tfa, &ready);
- if (err != tfa_error_ok)
- return err;
- if (ready)
- break;
- } while (loop--);
- if (((!tfa->is_probus_device) && (is_calibration)) || ((tfa->rev & 0xff) == 0x13))
- {
- /* Enable FAIM when clock is stable, to avoid MTP corruption */
- err = tfa98xx_faim_protect(tfa, 1);
- if (tfa->verbose) {
- pr_debug("FAIM enabled (err:%d).\n", err);
- }
- }
- break;
- case TFA_STATE_INIT_FW: /* DSP framework active (~patch loaded) */
- break;
- case TFA_STATE_OPERATING: /* Amp and Algo running */
- /* Depending on our previous state we need to set 3 bits */
- TFA_SET_BF(tfa, PWDN, 0); /* Coming from state 0 */
- TFA_SET_BF(tfa, MANSCONF, 1); /* Coming from state 1 */
- if (!tfa->is_probus_device)
- TFA_SET_BF(tfa, SBSL, 1); /* Coming from state 6 */
- else
- TFA_SET_BF(tfa, AMPE, 1); /* No SBSL for probus device, we set AMPE to 1 */
-
- /*
- * Disable MTP clock to protect memory.
- * However in case of calibration wait for DSP! (This should be case only during calibration).
- */
- if (TFA_GET_BF(tfa, MTPOTC) == 1 && tfa->tfa_family == 2) {
- count = MTPEX_WAIT_NTRIES * 4; /* Calibration takes a lot of time */
- while ((TFA_GET_BF(tfa, MTPEX) != 1) && count) {
- msleep_interruptible(10);
- count--;
- }
- }
- if (((!tfa->is_probus_device) && (is_calibration)) || ((tfa->rev & 0xff) == 0x13))
- {
- err = tfa98xx_faim_protect(tfa, 0);
- if (tfa->verbose) {
- pr_debug("FAIM disabled (err:%d).\n", err);
- }
- }
- /* Synchonize I/V delay on 96/97 at cold start */
- if (tfa->sync_iv_delay) {
- if (tfa->verbose)
- pr_debug("syncing I/V delay for %x\n",
- (tfa->rev & 0xff));
-
- /* wait for ACS to be cleared */
- count = 10;
- while ((TFA_GET_BF(tfa, ACS) == 1) &&
- (count-- > 0)) {
- msleep_interruptible(1);
- }
-
- tfa98xx_dsp_reset(tfa, 1);
- tfa98xx_dsp_reset(tfa, 0);
- tfa->sync_iv_delay = 0;
- }
- break;
- case TFA_STATE_FAULT: /* An alarm or error occurred */
- break;
- case TFA_STATE_RESET: /* I2C reset and ACS set */
- tfa98xx_init(tfa);
- break;
- default:
- if (state & 0x0f)
- return tfa_error_bad_param;
- }
-
- /* state modifiers */
-
- if (state & TFA_STATE_MUTE)
- tfa98xx_set_mute(tfa, Tfa98xx_Mute_Amplifier);
-
- if (state & TFA_STATE_UNMUTE)
- tfa98xx_set_mute(tfa, Tfa98xx_Mute_Off);
-
- tfa->state = state;
-
- return tfa_error_ok;
-}
-
-enum tfa_state tfa_dev_get_state(struct tfa_device *tfa)
-{
- int cold = 0;
- int manstate;
-
- /* different per family type */
- if (tfa->tfa_family == 1) {
- cold = TFA_GET_BF(tfa, ACS);
- if (cold && TFA_GET_BF(tfa, PWDN))
- tfa->state = TFA_STATE_RESET;
- else if (!cold && TFA_GET_BF(tfa, SWS))
- tfa->state = TFA_STATE_OPERATING;
- }
- else /* family 2 */ {
- if (is_94_N2_device(tfa))
- manstate = tfa_get_bf(tfa, TFA9894N2_BF_MANSTATE);
- else
- manstate = TFA_GET_BF(tfa, MANSTATE);
- switch (manstate) {
- case 0:
- tfa->state = TFA_STATE_POWERDOWN;
- break;
- case 8: /* if dsp reset if off assume framework is running */
- tfa->state = TFA_GET_BF(tfa, RST) ? TFA_STATE_INIT_CF : TFA_STATE_INIT_FW;
- break;
- case 9:
- tfa->state = TFA_STATE_OPERATING;
- break;
- default:
- break;
- }
- }
-
- return tfa->state;
-}
-
-int tfa_dev_mtp_get(struct tfa_device *tfa, enum tfa_mtp item)
-{
- int value = 0;
-
- switch (item) {
- case TFA_MTP_OTC:
- value = TFA_GET_BF(tfa, MTPOTC);
- break;
- case TFA_MTP_EX:
- value = TFA_GET_BF(tfa, MTPEX);
- break;
- case TFA_MTP_RE25:
- case TFA_MTP_RE25_PRIM:
- if (tfa->tfa_family == 2) {
- if ((tfa->rev & 0xFF) == 0x88)
- value = TFA_GET_BF(tfa, R25CL);
- else if ((tfa->rev & 0xFF) == 0x13)
- value = tfa_get_bf(tfa, TFA9912_BF_R25C);
- else
- value = TFA_GET_BF(tfa, R25C);
- }
- else {
- reg_read(tfa, 0x83, (unsigned short*)&value);
- }
- break;
- case TFA_MTP_RE25_SEC:
- if ((tfa->rev & 0xFF) == 0x88) {
- value = TFA_GET_BF(tfa, R25CR);
- }
- else {
- pr_debug("Error: Current device has no secondary Re25 channel \n");
- }
- break;
- case TFA_MTP_LOCK:
- break;
- }
-
- return value;
-}
-
-enum tfa_error tfa_dev_mtp_set(struct tfa_device *tfa, enum tfa_mtp item, int value)
-{
- enum tfa_error err = tfa_error_ok;
-
- switch (item) {
- case TFA_MTP_OTC:
- err = tfa98xx_set_mtp(tfa, (uint16_t)value, TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC_MSK);
- break;
- case TFA_MTP_EX:
- err = tfa98xx_set_mtp(tfa, (uint16_t)value, TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_MSK);
- break;
- case TFA_MTP_RE25:
- case TFA_MTP_RE25_PRIM:
- if (tfa->tfa_family == 2) {
- tfa98xx_key2(tfa, 0); /* unlock */
- if ((tfa->rev & 0xFF) == 0x88)
- TFA_SET_BF(tfa, R25CL, (uint16_t)value);
- else
- {
- if (tfa->is_probus_device == 1 && TFA_GET_BF(tfa, MTPOTC) == 1)
- tfa2_manual_mtp_cpy(tfa, 0xF4, value, 2);
- TFA_SET_BF(tfa, R25C, (uint16_t)value);
- }
- tfa98xx_key2(tfa, 1); /* lock */
- }
- break;
- case TFA_MTP_RE25_SEC:
- if ((tfa->rev & 0xFF) == 0x88) {
- TFA_SET_BF(tfa, R25CR, (uint16_t)value);
- }
- else {
- pr_debug("Error: Current device has no secondary Re25 channel \n");
- err = tfa_error_bad_param;
- }
- break;
- case TFA_MTP_LOCK:
- break;
- }
-
- return err;
-}
-
-int tfa_get_pga_gain(struct tfa_device *tfa)
-{
- return TFA_GET_BF(tfa, SAAMGAIN);
-}
-
-int tfa_set_pga_gain(struct tfa_device *tfa, uint16_t value)
-{
-
- return TFA_SET_BF(tfa, SAAMGAIN, value);
-}
-
-int tfa_get_noclk(struct tfa_device *tfa)
-{
- return TFA_GET_BF(tfa, NOCLK);
-}
-
-
-enum Tfa98xx_Error tfa_status(struct tfa_device *tfa)
-{
- int value;
- uint16_t val;
-
- /*
- * check IC status bits: cold start
- * and DSP watch dog bit to re init
- */
- value = TFA_READ_REG(tfa, VDDS); /* STATUSREG */
- if (value < 0)
- return -value;
- val = (uint16_t)value;
-
- /* pr_debug("SYS_STATUS0: 0x%04x\n", val); */
- if (TFA_GET_BF_VALUE(tfa, ACS, val) ||
- TFA_GET_BF_VALUE(tfa, WDS, val)) {
-
- if (TFA_GET_BF_VALUE(tfa, ACS, val))
- pr_err("ERROR: ACS\n");
- if (TFA_GET_BF_VALUE(tfa, WDS, val))
- pr_err("ERROR: WDS\n");
-
- return Tfa98xx_Error_DSP_not_running;
- }
-
- if (TFA_GET_BF_VALUE(tfa, SPKS, val))
- pr_err("ERROR: SPKS\n");
- if (!TFA_GET_BF_VALUE(tfa, SWS, val))
- pr_err("ERROR: SWS\n");
-
- /* Check secondary errors */
- if (!TFA_GET_BF_VALUE(tfa, CLKS, val) ||
- !TFA_GET_BF_VALUE(tfa, UVDS, val) ||
- !TFA_GET_BF_VALUE(tfa, OVDS, val) ||
- !TFA_GET_BF_VALUE(tfa, OTDS, val) ||
- !TFA_GET_BF_VALUE(tfa, PLLS, val) ||
- (!(tfa->daimap & Tfa98xx_DAI_TDM) &&
- !TFA_GET_BF_VALUE(tfa, VDDS, val)))
- pr_err("Misc errors detected: STATUS_FLAG0 = 0x%x\n", val);
-
- if ((tfa->daimap & Tfa98xx_DAI_TDM) && (tfa->tfa_family == 2)) {
- value = TFA_READ_REG(tfa, TDMERR); /* STATUS_FLAGS1 */
- if (value < 0)
- return -value;
- val = (uint16_t)value;
- if (TFA_GET_BF_VALUE(tfa, TDMERR, val) ||
- TFA_GET_BF_VALUE(tfa, TDMLUTER, val))
- pr_err("TDM related errors: STATUS_FLAG1 = 0x%x\n", val);
- }
-
- return Tfa98xx_Error_Ok;
-}
-
-int tfa_plop_noise_interrupt(struct tfa_device *tfa, int profile, int vstep)
-{
- enum Tfa98xx_Error err;
- int no_clk = 0;
-
- /* Remove sticky bit by reading it once */
- TFA_GET_BF(tfa, NOCLK);
-
- /* No clock detected */
- if (tfa_irq_get(tfa, tfa9912_irq_stnoclk)) {
- no_clk = TFA_GET_BF(tfa, NOCLK);
-
- /* Detect for clock is lost! (clock is not stable) */
- if (no_clk == 1) {
- /* Clock is lost. Set I2CR to remove POP noise */
- pr_info("No clock detected. Resetting the I2CR to avoid pop on 72! \n");
- err = tfa_dev_start(tfa, profile, vstep);
- if (err != Tfa98xx_Error_Ok) {
- pr_err("Error loading i2c registers (tfa_dev_start), err=%d\n", err);
- }
- else {
- pr_info("Setting i2c registers after I2CR succesfull\n");
- tfa_dev_set_state(tfa, TFA_STATE_UNMUTE, 0);
- }
-
- /* Remove sticky bit by reading it once */
- tfa_get_noclk(tfa);
-
- /* This is only for SAAM on the 72.
- Since the NOCLK interrupt is only enabled for 72 this is the place
- However: Not tested yet! But also does not harm normal flow!
- */
- if (strstr(tfaContProfileName(tfa->cnt, tfa->dev_idx, profile), ".saam")) {
- pr_info("Powering down from a SAAM profile, workaround PLMA4766 used! \n");
- TFA_SET_BF(tfa, PWDN, 1);
- TFA_SET_BF(tfa, AMPE, 0);
- TFA_SET_BF(tfa, SAMMODE, 0);
- }
- }
-
- /* If clk is stable set polarity to check for LOW (no clock)*/
- tfa_irq_set_pol(tfa, tfa9912_irq_stnoclk, (no_clk == 0));
-
- /* clear interrupt */
- tfa_irq_clear(tfa, tfa9912_irq_stnoclk);
- }
-
- /* return no_clk to know we called tfa_dev_start */
- return no_clk;
-}
-
-void tfa_lp_mode_interrupt(struct tfa_device *tfa)
-{
- const int irq_stclp0 = 36; /* FIXME: this 72 interrupt does not excist for 9912 */
- int lp0, lp1;
-
- if (tfa_irq_get(tfa, irq_stclp0)) {
- lp0 = TFA_GET_BF(tfa, LP0);
- if (lp0 > 0) {
- pr_info("lowpower mode 0 detected\n");
- }
- else {
- pr_info("lowpower mode 0 not detected\n");
- }
-
- tfa_irq_set_pol(tfa, irq_stclp0, (lp0 == 0));
-
- /* clear interrupt */
- tfa_irq_clear(tfa, irq_stclp0);
- }
-
- if (tfa_irq_get(tfa, tfa9912_irq_stclpr)) {
- lp1 = TFA_GET_BF(tfa, LP1);
- if (lp1 > 0) {
- pr_info("lowpower mode 1 detected\n");
- }
- else {
- pr_info("lowpower mode 1 not detected\n");
- }
-
- tfa_irq_set_pol(tfa, tfa9912_irq_stclpr, (lp1 == 0));
-
- /* clear interrupt */
- tfa_irq_clear(tfa, tfa9912_irq_stclpr);
- }
-}
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include "dbgprint.h"
+#include "tfa_container.h"
+#include "tfa.h"
+#include "tfa98xx_tfafieldnames.h"
+#include "tfa_internal.h"
+
+ /* handle macro for bitfield */
+#define TFA_MK_BF(reg, pos, len) ((reg<<8)|(pos<<4)|(len-1))
+
+/* abstract family for register */
+#define FAM_TFA98XX_CF_CONTROLS (TFA_FAM(tfa, RST) >> 8)
+#define FAM_TFA98XX_CF_MEM (TFA_FAM(tfa, MEMA) >> 8)
+#define FAM_TFA98XX_MTP0 (TFA_FAM(tfa, MTPOTC) >> 8)
+#define FAM_TFA98xx_INT_EN (TFA_FAM(tfa, INTENVDDS) >> 8)
+
+#define CF_STATUS_I2C_CMD_ACK 0x01
+
+/* Defines below are used for irq function (this removed the genregs include) */
+#define TFA98XX_INTERRUPT_ENABLE_REG1 0x48
+#define TFA98XX_INTERRUPT_IN_REG1 0x44
+#define TFA98XX_INTERRUPT_OUT_REG1 0x40
+#define TFA98XX_STATUS_POLARITY_REG1 0x4c
+#define TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_MSK 0x2
+#define TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC_MSK 0x1
+#define TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_POS 1
+#define TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC_POS 0
+#define ERR -1
+
+void tfanone_ops(struct tfa_device_ops *ops);
+void tfa9872_ops(struct tfa_device_ops *ops);
+void tfa9874_ops(struct tfa_device_ops *ops);
+void tfa9878_ops(struct tfa_device_ops *ops);
+void tfa9912_ops(struct tfa_device_ops *ops);
+void tfa9888_ops(struct tfa_device_ops *ops);
+void tfa9891_ops(struct tfa_device_ops *ops);
+void tfa9897_ops(struct tfa_device_ops *ops);
+void tfa9896_ops(struct tfa_device_ops *ops);
+void tfa9890_ops(struct tfa_device_ops *ops);
+void tfa9895_ops(struct tfa_device_ops *ops);
+void tfa9894_ops(struct tfa_device_ops *ops);
+
+#ifndef MIN
+#define MIN(A, B) (A < B?A:B)
+#endif
+
+/* retry values */
+#define CFSTABLE_TRIES 10
+#define AMPOFFWAIT_TRIES 50
+#define MTPBWAIT_TRIES 50
+#define MTPEX_WAIT_NTRIES 50
+
+/* calibration done executed */
+#define TFA_MTPEX_POS TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_POS /**/
+
+int tfa_get_calibration_info(struct tfa_device *tfa, int channel)
+{
+ return tfa->mohm[channel];
+}
+
+/* return sign extended tap pattern */
+int tfa_get_tap_pattern(struct tfa_device *tfa)
+{
+ int value = tfa_get_bf(tfa, TFA9912_BF_CFTAPPAT);
+ int bitshift;
+ /* length of bitfield */
+ uint8_t field_len = 1 + (TFA9912_BF_CFTAPPAT & 0x0f);
+
+ bitshift = 8 * sizeof(int) - field_len;
+ /* signextend */
+ value = (value << bitshift) >> bitshift;
+
+ return value;
+}
+/*
+ * interrupt bit function to clear
+ */
+int tfa_irq_clear(struct tfa_device *tfa, enum tfa9912_irq bit)
+{
+ unsigned char reg;
+
+ /* make bitfield enum */
+ if (bit == tfa9912_irq_all) {
+ /* operate on all bits */
+ for (reg = TFA98XX_INTERRUPT_IN_REG1;
+ reg < TFA98XX_INTERRUPT_IN_REG1 + 3; reg++)
+ reg_write(tfa, reg, 0xffff); /* all bits */
+ } else if (bit < tfa9912_irq_max) {
+ reg = (unsigned char)(TFA98XX_INTERRUPT_IN_REG1 + (bit >> 4));
+ reg_write(tfa, reg, 1 << (bit & 0x0f)); /* only this bit */
+ } else
+ return ERR;
+
+ return 0;
+}
+/*
+ * return state of irq or -1 if illegal bit
+ */
+int tfa_irq_get(struct tfa_device *tfa, enum tfa9912_irq bit)
+{
+ uint16_t value;
+ int reg, mask;
+
+ if (bit < tfa9912_irq_max) {
+ /* only this bit */
+ reg = TFA98XX_INTERRUPT_OUT_REG1 + (bit >> 4);
+ mask = 1 << (bit & 0x0f);
+ reg_read(tfa, (unsigned char)reg, &value);
+ } else
+ return ERR;
+
+ return (value & mask) != 0;
+}
+/*
+ * interrupt bit function that operates on the shadow regs in the handle
+ */
+
+int tfa_irq_ena(struct tfa_device *tfa, enum tfa9912_irq bit, int state)
+{
+ uint16_t value, new_value;
+ int reg = 0, mask;
+ /* */
+ if (bit == tfa9912_irq_all) {
+ /* operate on all bits */
+ for (reg = TFA98XX_INTERRUPT_ENABLE_REG1; reg <=
+ TFA98XX_INTERRUPT_ENABLE_REG1 + tfa9912_irq_max / 16; reg++) {
+ /* all bits */
+ reg_write(tfa, (unsigned char)reg, state ? 0xffff : 0);
+ tfa->interrupt_enable[reg - TFA98XX_INTERRUPT_ENABLE_REG1]
+ = state ? 0xffff : 0; /* all bits */
+ }
+ } else if (bit < tfa9912_irq_max) {
+ /* only this bit */
+ reg = TFA98XX_INTERRUPT_ENABLE_REG1 + (bit >> 4);
+ mask = 1 << (bit & 0x0f);
+ reg_read(tfa, (unsigned char)reg, &value);
+ if (state) //set
+ new_value = (uint16_t)(value | mask);
+ else // clear
+ new_value = value & ~mask;
+ if (new_value != value) {
+ reg_write(tfa, (unsigned char)reg, new_value); /* only this bit */
+ tfa->interrupt_enable[reg - TFA98XX_INTERRUPT_ENABLE_REG1]
+ = new_value;
+ }
+ } else
+ return ERR;
+
+ return 0;
+}
+
+/*
+ * mask interrupts by disabling them
+ */
+int tfa_irq_mask(struct tfa_device *tfa)
+{
+ int reg;
+
+ /* operate on all bits */
+ for (reg = TFA98XX_INTERRUPT_ENABLE_REG1; reg <=
+ TFA98XX_INTERRUPT_ENABLE_REG1 + tfa9912_irq_max / 16; reg++)
+ reg_write(tfa, (unsigned char)reg, 0);
+
+ return 0;
+}
+
+/*
+ * unmask interrupts by enabling them again
+ */
+int tfa_irq_unmask(struct tfa_device *tfa)
+{
+ int reg;
+
+ /* operate on all bits */
+ for (reg = TFA98XX_INTERRUPT_ENABLE_REG1; reg <=
+ TFA98XX_INTERRUPT_ENABLE_REG1 + tfa9912_irq_max / 16; reg++)
+ reg_write(tfa, (unsigned char)reg,
+ tfa->interrupt_enable[reg - TFA98XX_INTERRUPT_ENABLE_REG1]);
+
+ return 0;
+}
+
+/*
+ * interrupt bit function that sets the polarity
+ */
+
+int tfa_irq_set_pol(struct tfa_device *tfa, enum tfa9912_irq bit, int state)
+{
+ uint16_t value, new_value;
+ int reg = 0, mask;
+
+ if (bit == tfa9912_irq_all) {
+ /* operate on all bits */
+ for (reg = TFA98XX_STATUS_POLARITY_REG1; reg <=
+ TFA98XX_STATUS_POLARITY_REG1 + tfa9912_irq_max / 16; reg++) {
+ /* all bits */
+ reg_write(tfa, (unsigned char)reg, state ? 0xffff : 0);
+ }
+ } else if (bit < tfa9912_irq_max) {
+ /* only this bit */
+ reg = TFA98XX_STATUS_POLARITY_REG1 + (bit >> 4);
+ mask = 1 << (bit & 0x0f);
+ reg_read(tfa, (unsigned char)reg, &value);
+ if (state) /* Active High */
+ new_value = (uint16_t)(value | mask);
+ else /* Active Low */
+ new_value = value & ~mask;
+ if (new_value != value) {
+ reg_write(tfa, (unsigned char)reg, new_value); /* only this bit */
+ }
+ } else
+ return ERR;
+
+ return 0;
+}
+
+/*
+ * set device info and register device ops
+ */
+void tfa_set_query_info(struct tfa_device *tfa)
+{
+ /* invalidate device struct cached values */
+ tfa->hw_feature_bits = -1;
+ tfa->sw_feature_bits[0] = -1;
+ tfa->sw_feature_bits[1] = -1;
+ tfa->profile = -1;
+ tfa->vstep = -1;
+ /* defaults */
+ tfa->is_probus_device = 0;
+ tfa->advance_keys_handling = 0; /*artf65038*/
+ tfa->tfa_family = 1;
+ tfa->daimap = Tfa98xx_DAI_I2S; /* all others */
+ tfa->spkr_count = 1;
+ tfa->spkr_select = 0;
+ tfa->support_tcoef = supportYes;
+ tfa->supportDrc = supportNotSet;
+ tfa->support_saam = supportNotSet;
+ /* respond to external DSP: -1:none, 0:no_dsp, 1:cold, 2:warm */
+ tfa->ext_dsp = -1;
+ tfa->bus = 0;
+ tfa->partial_enable = 0;
+ tfa->convert_dsp32 = 0;
+ tfa->sync_iv_delay = 0;
+
+ /* TODO use the getfeatures() for retrieving the features [artf103523]
+ tfa->supportDrc = supportNotSet;*/
+
+ switch (tfa->rev & 0xff) {
+ case 0: /* tfanone : non-i2c external DSP device */
+ /* e.g. qc adsp */
+ tfa->supportDrc = supportYes;
+ tfa->tfa_family = 0;
+ tfa->spkr_count = 0;
+ tfa->daimap = 0;
+ tfanone_ops(&tfa->dev_ops); /* register device operations via tfa hal*/
+ tfa->bus = 1;
+ break;
+ case 0x72:
+ /* tfa9872 */
+ tfa->supportDrc = supportYes;
+ tfa->tfa_family = 2;
+ tfa->spkr_count = 1;
+ tfa->is_probus_device = 1;
+ tfa->daimap = Tfa98xx_DAI_TDM;
+ tfa9872_ops(&tfa->dev_ops); /* register device operations */
+ break;
+ case 0x74:
+ /* tfa9874 */
+ tfa->supportDrc = supportYes;
+ tfa->tfa_family = 2;
+ tfa->spkr_count = 1;
+ tfa->is_probus_device = 1;
+ tfa->daimap = Tfa98xx_DAI_TDM;
+ tfa9874_ops(&tfa->dev_ops); /* register device operations */
+ break;
+ case 0x78:
+ /* tfa9878 */
+ tfa->supportDrc = supportYes;
+ tfa->tfa_family = 2;
+ tfa->spkr_count = 1;
+ tfa->is_probus_device = 1;
+ tfa->advance_keys_handling = 1; /*artf65038*/
+ tfa->daimap = Tfa98xx_DAI_TDM;
+ tfa9878_ops(&tfa->dev_ops); /* register device operations */
+ break;
+ case 0x88:
+ /* tfa9888 */
+ tfa->tfa_family = 2;
+ tfa->spkr_count = 2;
+ tfa->daimap = Tfa98xx_DAI_TDM;
+ tfa9888_ops(&tfa->dev_ops); /* register device operations */
+ break;
+ case 0x97:
+ /* tfa9897 */
+ tfa->supportDrc = supportNo;
+ tfa->spkr_count = 1;
+ tfa->daimap = Tfa98xx_DAI_TDM;
+ tfa9897_ops(&tfa->dev_ops); /* register device operations */
+ break;
+ case 0x96:
+ /* tfa9896 */
+ tfa->supportDrc = supportNo;
+ tfa->spkr_count = 1;
+ tfa->daimap = Tfa98xx_DAI_TDM;
+ tfa9896_ops(&tfa->dev_ops); /* register device operations */
+ break;
+ case 0x92:
+ /* tfa9891 */
+ tfa->spkr_count = 1;
+ tfa->daimap = (Tfa98xx_DAI_PDM | Tfa98xx_DAI_I2S);
+ tfa9891_ops(&tfa->dev_ops); /* register device operations */
+ break;
+ case 0x91:
+ /* tfa9890B */
+ tfa->spkr_count = 1;
+ tfa->daimap = (Tfa98xx_DAI_PDM | Tfa98xx_DAI_I2S);
+ break;
+ case 0x80:
+ case 0x81:
+ /* tfa9890 */
+ tfa->spkr_count = 1;
+ tfa->daimap = Tfa98xx_DAI_I2S;
+ tfa->supportDrc = supportNo;
+ tfa->supportFramework = supportNo;
+ tfa9890_ops(&tfa->dev_ops); /* register device operations */
+ break;
+ case 0x12:
+ /* tfa9895 */
+ tfa->spkr_count = 1;
+ tfa->daimap = Tfa98xx_DAI_I2S;
+ tfa9895_ops(&tfa->dev_ops); /* register device operations */
+ break;
+ case 0x13:
+ /* tfa9912 */
+ tfa->tfa_family = 2;
+ tfa->spkr_count = 1;
+ tfa->daimap = Tfa98xx_DAI_TDM;
+ tfa9912_ops(&tfa->dev_ops); /* register device operations */
+ break;
+ case 0x94:
+ /* tfa9894 */
+ tfa->tfa_family = 2;
+ tfa->spkr_count = 1;
+ tfa->daimap = Tfa98xx_DAI_TDM;
+ tfa9894_ops(&tfa->dev_ops); /* register device operations */
+ break;
+
+ default:
+ pr_err("unknown device type : 0x%02x\n", tfa->rev);
+ _ASSERT(0);
+ break;
+ }
+}
+
+/*
+ * lookup the device type and return the family type
+ */
+int tfa98xx_dev2family(int dev_type)
+{
+ /* only look at the die ID part (lsb byte) */
+ switch (dev_type & 0xff) {
+ case 0x12:
+ case 0x80:
+ case 0x81:
+ case 0x91:
+ case 0x92:
+ case 0x97:
+ case 0x96:
+ return 1;
+ case 0x88:
+ case 0x72:
+ case 0x13:
+ case 0x74:
+ case 0x94:
+ return 2;
+ case 0x50:
+ return 3;
+ default:
+ return 0;
+ }
+}
+
+/*
+ * return the target address for the filter on this device
+
+ filter_index:
+ [0..9] reserved for EQ (not deployed, calc. is available)
+ [10..12] anti-alias filter
+ [13] integrator filter
+
+ */
+enum Tfa98xx_DMEM tfa98xx_filter_mem(struct tfa_device *tfa,
+ int filter_index, unsigned short *address, int channel)
+{
+ enum Tfa98xx_DMEM dmem = -1;
+ int idx;
+ unsigned short bq_table[7][4] = {
+ /* index: 10, 11, 12, 13 */
+ {346, 351, 356, 288}, //87 BRA_MAX_MRA4-2_7.00
+ {346, 351, 356, 288}, //90 BRA_MAX_MRA6_9.02
+ {467, 472, 477, 409}, //95 BRA_MAX_MRA7_10.02
+ {406, 411, 416, 348}, //97 BRA_MAX_MRA9_12.01
+ {467, 472, 477, 409}, //91 BRA_MAX_MRAA_13.02
+ {8832, 8837, 8842, 8847}, //88 part1
+ {8853, 8858, 8863, 8868} //88 part2
+ /* Since the 88 is stereo we have 2 parts.
+ * Every index has 5 values except index 13 this one
+ * has 6 values
+ */
+ };
+
+ if ((10 <= filter_index) && (filter_index <= 13)) {
+ dmem = Tfa98xx_DMEM_YMEM; /* for all devices */
+ idx = filter_index - 10;
+
+ switch (tfa->rev & 0xff) { // only compare lower byte
+ case 0x12:
+ *address = bq_table[2][idx];
+ break;
+ case 0x97:
+ *address = bq_table[3][idx];
+ break;
+ case 0x96:
+ *address = bq_table[3][idx];
+ break;
+ case 0x80:
+ case 0x81: // for the RAM version
+ case 0x91:
+ *address = bq_table[1][idx];
+ break;
+ case 0x92:
+ *address = bq_table[4][idx];
+ break;
+ case 0x88:
+ /* Channel 1 = primary, 2 = secondary */
+ if (channel == 1)
+ *address = bq_table[5][idx];
+ else
+ *address = bq_table[6][idx];
+ break;
+ case 0x72:
+ case 0x74:
+ case 0x13:
+ default:
+ /* unsupported case, possibly intermediate version */
+ return ERR;
+ _ASSERT(0);
+ }
+ }
+ return dmem;
+}
+
+/************************ query functions ******************************/
+/**
+* return revision
+* Used by the LTT
+*/
+void tfa98xx_rev(int *major, int *minor, int *revision)
+{
+ char version_str[] = TFA98XX_API_REV_STR;
+ sscanf(version_str, "v%d.%d.%d", major, minor, revision);
+}
+
+/**
+ * tfa_supported_speakers
+ * returns the number of the supported speaker count
+ */
+enum Tfa98xx_Error tfa_supported_speakers(struct tfa_device *tfa,
+ int *spkr_count)
+{
+ if (tfa->in_use == 0)
+ return Tfa98xx_Error_NotOpen;
+ else
+ *spkr_count = tfa->spkr_count;
+
+ return Tfa98xx_Error_Ok;
+}
+
+/*
+ * tfa98xx_supported_saam
+ * returns the supportedspeaker as microphone feature
+ */
+enum Tfa98xx_Error tfa98xx_supported_saam(struct tfa_device *tfa,
+ enum Tfa98xx_saam *saam)
+{
+ int features;
+ enum Tfa98xx_Error error;
+
+ if (tfa->support_saam == supportNotSet) {
+ error = tfa98xx_dsp_get_hw_feature_bits(tfa, &features);
+ if (error != Tfa98xx_Error_Ok)
+ return error;
+ tfa->support_saam =
+ (features & 0x8000) ? supportYes : supportNo; /* SAAM is bit15 */
+ }
+ *saam = tfa->support_saam == supportYes ? Tfa98xx_saam : Tfa98xx_saam_none;
+
+ return Tfa98xx_Error_Ok;
+}
+
+/*
+ * tfa98xx_compare_features
+ * Obtains features_from_MTP and features_from_cnt
+ */
+enum Tfa98xx_Error tfa98xx_compare_features(struct tfa_device *tfa,
+ int features_from_MTP[3], int features_from_cnt[3])
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ uint32_t value;
+ uint16_t mtpbf;
+ unsigned char bytes[3 * 2];
+ int status;
+
+ tfa98xx_dsp_system_stable(tfa, &status);
+ if (!status)
+ return Tfa98xx_Error_NoClock; // Only test when we have a clock.
+
+ /* Set proper MTP location per device: */
+ if (tfa->tfa_family == 1) {
+ mtpbf = 0x850f; /* MTP5 for tfa1,16 bits */
+ } else {
+ mtpbf = 0xf907; /* MTP9 for tfa2, 8 bits */
+ }
+
+ /* Read HW features from MTP: */
+ value = tfa_read_reg(tfa, mtpbf) & 0xffff;
+ features_from_MTP[0] = tfa->hw_feature_bits = value;
+
+ /* Read SW features: */
+ error = tfa_dsp_cmd_id_write_read(tfa, MODULE_FRAMEWORK,
+ FW_PAR_ID_GET_FEATURE_INFO, sizeof(bytes), bytes);
+ if (error != Tfa98xx_Error_Ok)
+ /* old ROM code may respond with Tfa98xx_Error_RpcParamId */
+ return error;
+
+ tfa98xx_convert_bytes2data(sizeof(bytes), bytes, &features_from_MTP[1]);
+
+ /* check if feature bits from MTP match feature bits from cnt file: */
+ get_hw_features_from_cnt(tfa, &features_from_cnt[0]);
+ get_sw_features_from_cnt(tfa, &features_from_cnt[1]);
+
+ return error;
+}
+
+/********************************* device specific ops **********************/
+/* the wrapper for DspReset, in case of full */
+enum Tfa98xx_Error tfa98xx_dsp_reset(struct tfa_device *tfa, int state)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+
+ error = (tfa->dev_ops.dsp_reset)(tfa, state);
+
+ return error;
+}
+
+/* the ops wrapper for tfa98xx_dsp_SystemStable */
+enum Tfa98xx_Error tfa98xx_dsp_system_stable(struct tfa_device *tfa,
+ int *ready)
+{
+ return (tfa->dev_ops.dsp_system_stable)(tfa, ready);
+}
+
+/* the ops wrapper for tfa98xx_dsp_system_stable */
+enum Tfa98xx_Error tfa98xx_auto_copy_mtp_to_iic(struct tfa_device *tfa)
+{
+ return (tfa->dev_ops.auto_copy_mtp_to_iic)(tfa);
+}
+
+/* the ops wrapper for tfa98xx_faim_protect */
+enum Tfa98xx_Error tfa98xx_faim_protect(struct tfa_device *tfa, int state)
+{
+ return (tfa->dev_ops.faim_protect)(tfa, state);
+}
+
+/*
+ * bring the device into a state similar to reset
+ */
+enum Tfa98xx_Error tfa98xx_init(struct tfa_device *tfa)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ uint16_t value = 0;
+
+ /* reset all i2C registers to default
+ * Write the register directly to avoid the read in the bitfield function.
+ * The I2CR bit may overwrite the full register because it is reset anyway.
+ * This will save a reg read transaction.
+ */
+ TFA_SET_BF_VALUE(tfa, I2CR, 1, &value);
+ TFA_WRITE_REG(tfa, I2CR, value);
+
+ /* Put DSP in reset */
+ tfa98xx_dsp_reset(tfa, 1); /* in pair of tfaRunStartDSP() */
+
+ /* some other registers must be set for optimal amplifier behaviour
+ * This is implemented in a file specific for the type number
+ */
+ if (tfa->dev_ops.tfa_init)
+ error = (tfa->dev_ops.tfa_init)(tfa);
+
+ return error;
+}
+
+enum Tfa98xx_Error tfa98xx_dsp_write_tables(struct tfa_device *tfa,
+ int sample_rate)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+
+ error = (tfa->dev_ops.dsp_write_tables)(tfa, sample_rate);
+
+ return error;
+}
+
+/** Set internal oscillator into power down mode.
+*
+* @param[in] tfa device description structure
+* @param[in] state new state 0 - oscillator is on, 1 oscillator is off.
+*
+* @return Tfa98xx_Error_Ok when successfull, error otherwise.
+*/
+enum Tfa98xx_Error tfa98xx_set_osc_powerdown(struct tfa_device *tfa, int state)
+{
+ if (tfa->dev_ops.set_osc_powerdown) {
+ return tfa->dev_ops.set_osc_powerdown(tfa, state);
+ }
+
+ return Tfa98xx_Error_Not_Implemented;
+}
+
+/** update low power mode of the device.
+*
+* @param[in] tfa device description structure
+* @param[in] state new state 0 - LPMODE is on, 1 LPMODE is off.
+*
+* @return Tfa98xx_Error_Ok when successfull, error otherwise.
+*/
+enum Tfa98xx_Error tfa98xx_update_lpm(struct tfa_device *tfa, int state)
+{
+ if (tfa->dev_ops.update_lpm) {
+ return tfa->dev_ops.update_lpm(tfa, state);
+ }
+
+ return Tfa98xx_Error_Not_Implemented;
+}
+/** Check presence of powerswitch=1 in configuration and optimal setting.
+*
+* @param[in] tfa device description structure
+*
+* @return -1 when error, 0 or 1 depends on switch settings.
+*/
+int tfa98xx_powerswitch_is_enabled(struct tfa_device *tfa)
+{
+ uint16_t value;
+ enum Tfa98xx_Error ret;
+
+ if (((tfa->rev & 0xff) == 0x13) || ((tfa->rev & 0xff) == 0x88)) {
+ ret = reg_read(tfa, 0xc6, &value);
+ if (ret != Tfa98xx_Error_Ok) {
+ return ERR;
+ }
+ /*
+ * PLMA5539: Check actual value of powerswitch. TODO: regmap v1.40
+ * should make this bit public.
+ */
+
+ return (int)(value & (1u << 6));
+ }
+
+ return 1;
+}
+
+/********************* new tfa2 ***************************************/
+/* newly added messaging for tfa2 tfa1? */
+enum Tfa98xx_Error tfa98xx_dsp_get_memory(struct tfa_device *tfa,
+ int memoryType, int offset, int length, unsigned char bytes[])
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ char msg[4 * 3];
+ int nr = 0;
+
+ msg[nr++] = 8;
+ msg[nr++] = MODULE_FRAMEWORK + 128;
+ msg[nr++] = FW_PAR_ID_GET_MEMORY;
+
+ msg[nr++] = 0;
+ msg[nr++] = 0;
+ msg[nr++] = (char)memoryType;
+
+ msg[nr++] = 0;
+ msg[nr++] = (offset >> 8) & 0xff;
+ msg[nr++] = offset & 0xff;
+
+ msg[nr++] = 0;
+ msg[nr++] = (length >> 8) & 0xff;
+ msg[nr++] = length & 0xff;
+
+ /* send msg */
+ error = dsp_msg(tfa, nr, (char *)msg);
+
+ if (error != Tfa98xx_Error_Ok)
+ return error;
+
+ /* read the data from the device (length * 3) */
+ error = dsp_msg_read(tfa, length * 3, bytes);
+
+ return error;
+}
+
+enum Tfa98xx_Error tfa98xx_dsp_set_memory(struct tfa_device *tfa,
+ int memoryType, int offset, int length, int value)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ int nr = 0;
+ char msg[5 * 3];
+
+ msg[nr++] = 8;
+ msg[nr++] = MODULE_FRAMEWORK + 128;
+ msg[nr++] = FW_PAR_ID_SET_MEMORY;
+
+ msg[nr++] = 0;
+ msg[nr++] = 0;
+ msg[nr++] = (char)memoryType;
+
+ msg[nr++] = 0;
+ msg[nr++] = (offset >> 8) & 0xff;
+ msg[nr++] = offset & 0xff;
+
+ msg[nr++] = 0;
+ msg[nr++] = (length >> 8) & 0xff;
+ msg[nr++] = length & 0xff;
+
+ msg[nr++] = (value >> 16) & 0xff;
+ msg[nr++] = (value >> 8) & 0xff;
+ msg[nr++] = value & 0xff;
+
+ /* send msg */
+ error = dsp_msg(tfa, nr, (char *)msg);
+
+ return error;
+}
+/****************************** calibration support **************************/
+/*
+ * get/set the mtp with user controllable values
+ *
+ * check if the relevant clocks are available
+ */
+enum Tfa98xx_Error tfa98xx_get_mtp(struct tfa_device *tfa, uint16_t *value)
+{
+ int status;
+ int result;
+
+ /* not possible if PLL in powerdown */
+ if (TFA_GET_BF(tfa, PWDN)) {
+ pr_debug("PLL in powerdown\n");
+ return Tfa98xx_Error_NoClock;
+ }
+
+ tfa98xx_dsp_system_stable(tfa, &status);
+ if (status == 0) {
+ pr_debug("PLL not running\n");
+ return Tfa98xx_Error_NoClock;
+ }
+
+ result = TFA_READ_REG(tfa, MTP0);
+ if (result < 0) {
+ return -result;
+ }
+ *value = (uint16_t)result;
+
+ return Tfa98xx_Error_Ok;
+}
+
+/*
+ * lock or unlock KEY2
+ * lock = 1 will lock
+ * lock = 0 will unlock
+ *
+ * note that on return all the hidden key will be off
+ */
+void tfa98xx_key2(struct tfa_device *tfa, int lock)
+{
+ /* unhide lock registers */
+ reg_write(tfa, (tfa->tfa_family == 1) ? 0x40 : 0x0F, 0x5A6B);
+ /* lock/unlock key2 MTPK */
+ TFA_WRITE_REG(tfa, MTPKEY2, lock ? 0 : 0x5A);
+ /* unhide lock registers */
+ if (!tfa->advance_keys_handling) /*artf65038*/
+ reg_write(tfa, (tfa->tfa_family == 1) ? 0x40 : 0x0F, 0);
+}
+void tfa2_manual_mtp_cpy(struct tfa_device *tfa, uint16_t reg_row_to_keep,
+ uint16_t reg_row_to_set, uint8_t row)///MCH_TO_TEST
+{
+ uint16_t value;
+ int loop = 0;
+ enum Tfa98xx_Error error;
+ /* Assure FAIM is enabled (enable it when neccesery) */
+ if (tfa->is_probus_device) {
+ error = tfa98xx_faim_protect(tfa, 1);
+ if (tfa->verbose) {
+ pr_debug("FAIM enabled (err:%d).\n", error);
+ }
+ }
+ reg_read(tfa, (unsigned char)reg_row_to_keep, &value);
+ if (!row) {
+ reg_write(tfa, 0xA7, value);
+ reg_write(tfa, 0xA8, reg_row_to_set);
+ } else {
+ reg_write(tfa, 0xA7, reg_row_to_set);
+ reg_write(tfa, 0xA8, value);
+ }
+ reg_write(tfa, 0xA3, 0x10 | row);
+ if (tfa->is_probus_device) {
+ /* Assure FAIM is enabled (enable it when neccesery) */
+ for (loop = 0; loop < 100 /*x10ms*/; loop++) {
+ msleep_interruptible(10); /* wait 10ms to avoid busload */
+ if (tfa_dev_get_mtpb(tfa) == 0)
+ break;
+ }
+ error = tfa98xx_faim_protect(tfa, 0);
+ if (tfa->verbose) {
+ pr_debug("FAIM disabled (err:%d).\n", error);
+ }
+ }
+}
+
+enum Tfa98xx_Error tfa98xx_set_mtp(struct tfa_device *tfa, uint16_t value,
+ uint16_t mask)
+{
+ unsigned short mtp_old, mtp_new;
+ int loop, status;
+ enum Tfa98xx_Error error;
+
+ error = tfa98xx_get_mtp(tfa, &mtp_old);
+
+ if (error != Tfa98xx_Error_Ok)
+ return error;
+
+ mtp_new = (value & mask) | (mtp_old & ~mask);
+
+ if (mtp_old == mtp_new) /* no change */ {
+ if (tfa->verbose)
+ pr_info("No change in MTP. Value not written! \n");
+ return Tfa98xx_Error_Ok;
+ }
+ error = tfa98xx_update_lpm(tfa, 1);
+ if (error) {
+ return error;
+ }
+ /* Assure FAIM is enabled (enable it when neccesery) */
+ error = tfa98xx_faim_protect(tfa, 1);
+ if (error) {
+ return error;
+ }
+ if (tfa->verbose) {
+ pr_debug("MTP clock enabled.\n");
+ }
+
+ /* assure that the clock is up, else we can't write MTP */
+ error = tfa98xx_dsp_system_stable(tfa, &status);
+ if (error) {
+ return error;
+ }
+ if (status == 0) {
+ return Tfa98xx_Error_NoClock;
+ }
+
+ tfa98xx_key2(tfa, 0); /* unlock */
+ TFA_WRITE_REG(tfa, MTP0, mtp_new); /* write to i2c shadow reg */
+ /* CIMTP=1 start copying all the data from i2c regs_mtp to mtp*/
+ if (tfa->tfa_family == 2)
+ tfa2_manual_mtp_cpy(tfa, 0xF1, mtp_new, 0);
+ else
+ TFA_SET_BF(tfa, CIMTP, 1);
+ /* wait until MTP write is done */
+ error = Tfa98xx_Error_StateTimedOut;
+ for (loop = 0; loop < 100 /*x10ms*/; loop++) {
+ msleep_interruptible(10); /* wait 10ms to avoid busload */
+ if (tfa_dev_get_mtpb(tfa) == 0) {
+ error = Tfa98xx_Error_Ok;
+ break;
+ }
+ }
+ tfa98xx_key2(tfa, 1); /* lock */
+ /* MTP setting failed due to timeout ?*/
+ if (error) {
+ tfa98xx_faim_protect(tfa, 0);
+ return error;
+ }
+
+ /* Disable the FAIM, if this is neccessary */
+ error = tfa98xx_faim_protect(tfa, 0);
+ if (error) {
+ return error;
+ }
+ if (tfa->verbose) {
+ pr_debug("MTP clock disabled.\n");
+ }
+ error = tfa98xx_update_lpm(tfa, 0);
+ if (error) {
+ return error;
+ }
+ return error;
+}
+/*
+ * clear mtpex
+ * set ACS
+ * start tfa
+ */
+int tfa_calibrate(struct tfa_device *tfa)
+{
+ enum Tfa98xx_Error error;
+
+ /* clear mtpex */
+ error = tfa98xx_set_mtp(tfa, 0, TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_MSK);
+ if (error)
+ return error;
+
+ /* set RST=1 to put the DSP in Reset */
+ TFA_SET_BF(tfa, RST, 1);
+
+ /* set ACS/coldboot state */
+ error = tfaRunColdboot(tfa, 1);
+
+ /* start tfa by playing */
+ return error;
+}
+
+static short twos(short x)
+{
+ return (x < 0) ? x + 512 : x;
+}
+
+void tfa98xx_set_exttemp(struct tfa_device *tfa, short ext_temp)
+{
+ if ((-256 <= ext_temp) && (ext_temp <= 255)) {
+ /* make twos complement */
+ pr_debug("Using ext temp %d C\n", twos(ext_temp));
+ TFA_SET_BF(tfa, TROS, 1);
+ TFA_SET_BF(tfa, EXTTS, twos(ext_temp));
+ } else {
+ pr_debug("Clearing ext temp settings\n");
+ TFA_SET_BF(tfa, TROS, 0);
+ }
+}
+short tfa98xx_get_exttemp(struct tfa_device *tfa)
+{
+ short ext_temp = (short)TFA_GET_BF(tfa, EXTTS);
+ return twos(ext_temp);
+}
+
+/******************* tfa simple bitfield interfacing *************************/
+/* convenience functions */
+enum Tfa98xx_Error tfa98xx_set_volume_level(struct tfa_device *tfa,
+ unsigned short vol)
+{
+ if (tfa->in_use == 0)
+ return Tfa98xx_Error_NotOpen;
+
+ if (vol > 255) /* restricted to 8 bits */
+ vol = 255;
+
+ /* 0x00 -> 0.0 dB
+ * 0x01 -> -0.5 dB
+ * ...
+ * 0xFE -> -127dB
+ * 0xFF -> muted
+ */
+
+ /* volume value is in the top 8 bits of the register */
+ return -TFA_SET_BF(tfa, VOL, (uint16_t)vol);
+}
+
+static enum Tfa98xx_Error
+tfa98xx_set_mute_tfa2(struct tfa_device *tfa, enum Tfa98xx_Mute mute)
+{
+ enum Tfa98xx_Error error;
+
+ if (tfa->dev_ops.set_mute == NULL)
+ return Tfa98xx_Error_Not_Supported;
+
+ switch (mute) {
+ case Tfa98xx_Mute_Off:
+ error = tfa->dev_ops.set_mute(tfa, 0);
+ TFA_SET_BF(tfa, AMPE, 1);
+ break;
+ case Tfa98xx_Mute_Amplifier:
+ case Tfa98xx_Mute_Digital:
+ error = tfa->dev_ops.set_mute(tfa, 1);
+ TFA_SET_BF(tfa, AMPE, 0);
+ break;
+ default:
+ return Tfa98xx_Error_Bad_Parameter;
+ }
+
+ return error;
+}
+
+static enum Tfa98xx_Error
+tfa98xx_set_mute_tfa1(struct tfa_device *tfa, enum Tfa98xx_Mute mute)
+{
+ enum Tfa98xx_Error error;
+ unsigned short audioctrl_value;
+ unsigned short sysctrl_value;
+ int value;
+
+ value = TFA_READ_REG(tfa, CFSM); /* audio control register */
+ if (value < 0)
+ return -value;
+ audioctrl_value = (unsigned short)value;
+ value = TFA_READ_REG(tfa, AMPE); /* system control register */
+ if (value < 0)
+ return -value;
+ sysctrl_value = (unsigned short)value;
+
+ switch (mute) {
+ case Tfa98xx_Mute_Off:
+ /* previous state can be digital or amplifier mute,
+ * clear the cf_mute and set the enbl_amplifier bits
+ *
+ * To reduce PLOP at power on it is needed to switch the
+ * amplifier on with the DCDC in follower mode
+ * (enbl_boost = 0 ?).
+ * This workaround is also needed when toggling the
+ * powerdown bit!
+ */
+ TFA_SET_BF_VALUE(tfa, CFSM, 0, &audioctrl_value);
+ TFA_SET_BF_VALUE(tfa, AMPE, 1, &sysctrl_value);
+ TFA_SET_BF_VALUE(tfa, DCA, 1, &sysctrl_value);
+ break;
+ case Tfa98xx_Mute_Digital:
+ /* expect the amplifier to run */
+ /* set the cf_mute bit */
+ TFA_SET_BF_VALUE(tfa, CFSM, 1, &audioctrl_value);
+ /* set the enbl_amplifier bit */
+ TFA_SET_BF_VALUE(tfa, AMPE, 1, &sysctrl_value);
+ /* clear active mode */
+ TFA_SET_BF_VALUE(tfa, DCA, 0, &sysctrl_value);
+ break;
+ case Tfa98xx_Mute_Amplifier:
+ /* clear the cf_mute bit */
+ TFA_SET_BF_VALUE(tfa, CFSM, 0, &audioctrl_value);
+ /* clear the enbl_amplifier bit and active mode */
+ TFA_SET_BF_VALUE(tfa, AMPE, 0, &sysctrl_value);
+ TFA_SET_BF_VALUE(tfa, DCA, 0, &sysctrl_value);
+ break;
+ default:
+ return Tfa98xx_Error_Bad_Parameter;
+ }
+
+ error = -TFA_WRITE_REG(tfa, CFSM, audioctrl_value);
+ if (error)
+ return error;
+ error = -TFA_WRITE_REG(tfa, AMPE, sysctrl_value);
+ return error;
+}
+
+enum Tfa98xx_Error
+ tfa98xx_set_mute(struct tfa_device *tfa, enum Tfa98xx_Mute mute)
+{
+ if (tfa->in_use == 0) {
+ pr_err("device is not opened \n");
+ return Tfa98xx_Error_NotOpen;
+ }
+
+ if (tfa->tfa_family == 1)
+ return tfa98xx_set_mute_tfa1(tfa, mute);
+ else
+ return tfa98xx_set_mute_tfa2(tfa, mute);
+}
+
+/****************** patching ***********************************************/
+static enum Tfa98xx_Error
+tfa98xx_process_patch_file(struct tfa_device *tfa, int length,
+ const unsigned char *bytes)
+{
+ unsigned short size;
+ int index = 0;
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+
+ while (index < length) {
+ size = bytes[index] + bytes[index + 1] * 256;
+ index += 2;
+ if ((index + size) > length) {
+ /* outside the buffer, error in the input data */
+ return Tfa98xx_Error_Bad_Parameter;
+ }
+
+ if (size > tfa->buffer_size) {
+ /* too big, must fit buffer */
+ return Tfa98xx_Error_Bad_Parameter;
+ }
+
+ error = tfa98xx_write_raw(tfa, size, &bytes[index]);
+ if (error != Tfa98xx_Error_Ok)
+ break;
+ index += size;
+ }
+ return error;
+}
+
+
+
+/* the patch contains a header with the following
+ * IC revision register: 1 byte, 0xFF means don't care
+ * XMEM address to check: 2 bytes, big endian, 0xFFFF means don't care
+ * XMEM value to expect: 3 bytes, big endian
+ */
+static enum Tfa98xx_Error
+tfa98xx_check_ic_rom_version(struct tfa_device *tfa,
+ const unsigned char patchheader[])
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ unsigned short checkrev, revid;
+ unsigned char lsb_revid;
+ unsigned short checkaddress;
+ int checkvalue;
+ int value = 0;
+ int status;
+ checkrev = patchheader[0];
+ lsb_revid = tfa->rev & 0xff; /* only compare lower byte */
+
+ if ((checkrev != 0xFF) && (checkrev != lsb_revid))
+ return Tfa98xx_Error_Not_Supported;
+
+ checkaddress = (patchheader[1] << 8) + patchheader[2];
+ checkvalue =
+ (patchheader[3] << 16) + (patchheader[4] << 8) + patchheader[5];
+ if (checkaddress != 0xFFFF) {
+ /* before reading XMEM, check if we can access the DSP */
+ error = tfa98xx_dsp_system_stable(tfa, &status);
+ if (error == Tfa98xx_Error_Ok) {
+ if (!status) {
+ /* DSP subsys not running */
+ error = Tfa98xx_Error_DSP_not_running;
+ }
+ }
+ /* read register to check the correct ROM version */
+ if (error == Tfa98xx_Error_Ok) {
+ error = mem_read(tfa, checkaddress, 1, &value);
+ }
+ if (error == Tfa98xx_Error_Ok) {
+ if (value != checkvalue) {
+ pr_err("patch file romid type check failed [0x%04x]: \
+ expected 0x%02x, actual 0x%02x\n",
+ checkaddress, value, checkvalue);
+ error = Tfa98xx_Error_Not_Supported;
+ }
+ }
+ } else { /* == 0xffff */
+ /* check if the revid subtype is in there */
+ if (checkvalue != 0xFFFFFF && checkvalue != 0) {
+ revid = patchheader[5] << 8 | patchheader[0]; /* full revid */
+ if (revid != tfa->rev) {
+ pr_err("patch file device type check failed: expected 0x%02x, actual 0x%02x\n",
+ tfa->rev, revid);
+ return Tfa98xx_Error_Not_Supported;
+ }
+ }
+ }
+
+ return error;
+}
+
+
+#define PATCH_HEADER_LENGTH 6
+enum Tfa98xx_Error
+ tfa_dsp_patch(struct tfa_device *tfa, int patchLength,
+ const unsigned char *patchBytes)
+{
+ enum Tfa98xx_Error error;
+ int status;
+ if (tfa->in_use == 0)
+ return Tfa98xx_Error_NotOpen;
+
+ if (patchLength < PATCH_HEADER_LENGTH)
+ return Tfa98xx_Error_Bad_Parameter;
+
+ error = tfa98xx_check_ic_rom_version(tfa, patchBytes);
+ if (Tfa98xx_Error_Ok != error) {
+ return error;
+ }
+ tfa98xx_dsp_system_stable(tfa, &status);
+ if (!status)
+ return Tfa98xx_Error_NoClock; // Only test when we have a clock.
+ /******MCH_TO_TEST**************/
+ if (error == Tfa98xx_Error_Ok) {
+ error = tfaRunColdboot(tfa, 1);
+ if (error)
+ return Tfa98xx_Error_DSP_not_running;
+ }
+ /**************************/
+ error =
+ tfa98xx_process_patch_file(tfa, patchLength - PATCH_HEADER_LENGTH,
+ patchBytes + PATCH_HEADER_LENGTH);
+
+ return error;
+}
+
+/****************** end patching *****************************************/
+
+TFA_INTERNAL enum Tfa98xx_Error
+tfa98xx_wait_result(struct tfa_device *tfa, int wait_retry_count)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ int cf_status; /* the contents of the CF_STATUS register */
+ int tries = 0;
+ do {
+ cf_status = TFA_GET_BF(tfa, ACK);
+ if (cf_status < 0)
+ error = -cf_status;
+ tries++;
+ }
+ // i2c_cmd_ack
+ /* don't wait forever, DSP is pretty quick to respond (< 1ms) */
+ while ((error == Tfa98xx_Error_Ok) &&
+ ((cf_status & CF_STATUS_I2C_CMD_ACK) == 0) && (tries < wait_retry_count));
+
+ if (tries >= wait_retry_count) {
+ /* something wrong with communication with DSP */
+ error = Tfa98xx_Error_DSP_not_running;
+ }
+ return error;
+}
+
+/*
+ * * support functions for data conversion
+ */
+ /**
+ convert memory bytes to signed 24 bit integers
+ input: bytes contains "num_bytes" byte elements
+ output: data contains "num_bytes/3" int24 elements
+ */
+void tfa98xx_convert_bytes2data(int num_bytes, const unsigned char bytes[],
+ int data[])
+{
+ int i; /* index for data */
+ int k; /* index for bytes */
+ int d;
+ int num_data = num_bytes / 3;
+ _ASSERT((num_bytes % 3) == 0);
+ for (i = 0, k = 0; i < num_data; ++i, k += 3) {
+ d = (bytes[k] << 16) | (bytes[k + 1] << 8) | (bytes[k + 2]);
+ _ASSERT(d >= 0);
+ _ASSERT(d < (1 << 24)); /* max 24 bits in use */
+ if (bytes[k] & 0x80) /* sign bit was set */
+ d = -((1 << 24) - d);
+
+ data[i] = d;
+ }
+}
+
+
+/**
+ convert signed 32 bit integers to 24 bit aligned bytes
+ input: data contains "num_data" int elements
+ output: bytes contains "3 * num_data" byte elements
+*/
+void tfa98xx_convert_data2bytes(int num_data, const int data[],
+ unsigned char bytes[])
+{
+ int i; /* index for data */
+ int k; /* index for bytes */
+ int d;
+ /* note: cannot just take the lowest 3 bytes from the 32 bit
+ * integer, because also need to take care of clipping any
+ * value > 2&23 */
+ for (i = 0, k = 0; i < num_data; ++i, k += 3) {
+ if (data[i] >= 0)
+ d = MIN(data[i], (1 << 23) - 1);
+ else {
+ /* 2's complement */
+ d = (1 << 24) - MIN(-data[i], 1 << 23);
+ }
+ _ASSERT(d >= 0);
+ _ASSERT(d < (1 << 24)); /* max 24 bits in use */
+ bytes[k] = (d >> 16) & 0xFF; /* MSB */
+ bytes[k + 1] = (d >> 8) & 0xFF;
+ bytes[k + 2] = (d) & 0xFF; /* LSB */
+ }
+}
+
+/*
+ * DSP RPC message support functions
+ * depending on framework to be up and running
+ * need base i2c of memaccess (tfa1=0x70/tfa2=0x90)
+ */
+
+
+ /* write dsp messages in function tfa_dsp_msg() */
+ /* note the 'old' write_parameter() was more efficient because all
+ * i2c was in one burst transaction
+ */
+
+ /*
+ * TODO properly handle bitfields: state should be restored!
+ * (now it will change eg dmesg field to xmem)
+ */
+enum Tfa98xx_Error tfa_dsp_msg_write(struct tfa_device *tfa, int length,
+ const char *buffer)
+{
+ int offset = 0;
+ /* XMEM word size */
+ int chunk_size = ROUND_DOWN(tfa->buffer_size, 3);
+ int remaining_bytes = length;
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ uint16_t cfctl;
+ int value;
+
+ value = TFA_READ_REG(tfa, DMEM);
+ if (value < 0) {
+ error = -value;
+ return error;
+ }
+ cfctl = (uint16_t)value;
+ /* assume no I2C errors from here */
+ /* set cf ctl to DMEM */
+ TFA_SET_BF_VALUE(tfa, DMEM, (uint16_t)Tfa98xx_DMEM_XMEM, &cfctl);
+ TFA_SET_BF_VALUE(tfa, AIF, 0, &cfctl); /* set to autoincrement */
+ TFA_WRITE_REG(tfa, DMEM, cfctl);
+
+ /* xmem[1] is start of message
+ * direct write to register to save cycles avoiding read-modify-write
+ */
+ TFA_WRITE_REG(tfa, MADD, 1);
+
+ /* due to autoincrement in cf_ctrl, next write will happen at
+ * the next address */
+ while ((error == Tfa98xx_Error_Ok) && (remaining_bytes > 0)) {
+ if (remaining_bytes < chunk_size)
+ chunk_size = remaining_bytes;
+ /* else chunk_size remains at initialize value above */
+ error = tfa98xx_write_data(tfa, FAM_TFA98XX_CF_MEM,
+ chunk_size, (const unsigned char *)buffer + offset);
+ remaining_bytes -= chunk_size;
+ offset += chunk_size;
+ }
+
+ /* notify the DSP */
+ if (error == Tfa98xx_Error_Ok) {
+ /* cf_int=0, cf_aif=0, cf_dmem=XMEM=01, cf_rst_dsp=0 */
+ /* set the cf_req1 and cf_int bit */
+ TFA_SET_BF_VALUE(tfa, REQCMD, 0x01, &cfctl); /* bit 0 */
+ TFA_SET_BF_VALUE(tfa, CFINT, 1, &cfctl);
+ error = -TFA_WRITE_REG(tfa, CFINT, cfctl);
+ }
+
+ return error;
+}
+
+enum Tfa98xx_Error tfa_dsp_msg_write_id(struct tfa_device *tfa, int length,
+ const char *buffer, uint8_t cmdid[3])
+{
+ int offset = 0;
+ int chunk_size = ROUND_DOWN(tfa->buffer_size, 3); /* XMEM word size */
+ int remaining_bytes = length;
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ uint16_t cfctl;
+ int value;
+
+ value = TFA_READ_REG(tfa, DMEM);
+ if (value < 0) {
+ error = -value;
+ return error;
+ }
+ cfctl = (uint16_t)value;
+ /* assume no I2C errors from here */
+ /* set cf ctl to DMEM */
+ TFA_SET_BF_VALUE(tfa, DMEM, (uint16_t)Tfa98xx_DMEM_XMEM, &cfctl);
+ TFA_SET_BF_VALUE(tfa, AIF, 0, &cfctl); /* set to autoincrement */
+ TFA_WRITE_REG(tfa, DMEM, cfctl);
+
+ /* xmem[1] is start of message
+ * direct write to register to save cycles avoiding read-modify-write
+ */
+ TFA_WRITE_REG(tfa, MADD, 1);
+
+ /* write cmd-id */
+ error = tfa98xx_write_data(tfa, FAM_TFA98XX_CF_MEM, 3,
+ (const unsigned char *)cmdid);
+
+ /* due to autoincrement in cf_ctrl, next write will happen at
+ * the next address */
+ while ((error == Tfa98xx_Error_Ok) && (remaining_bytes > 0)) {
+ if (remaining_bytes < chunk_size)
+ chunk_size = remaining_bytes;
+ /* else chunk_size remains at initialize value above */
+ error = tfa98xx_write_data(tfa, FAM_TFA98XX_CF_MEM,
+ chunk_size, (const unsigned char *)buffer + offset);
+ remaining_bytes -= chunk_size;
+ offset += chunk_size;
+ }
+
+ /* notify the DSP */
+ if (error == Tfa98xx_Error_Ok) {
+ /* cf_int=0, cf_aif=0, cf_dmem=XMEM=01, cf_rst_dsp=0 */
+ /* set the cf_req1 and cf_int bit */
+ TFA_SET_BF_VALUE(tfa, REQCMD, 0x01, &cfctl); /* bit 0 */
+ TFA_SET_BF_VALUE(tfa, CFINT, 1, &cfctl);
+ error = -TFA_WRITE_REG(tfa, CFINT, cfctl);
+ }
+
+ return error;
+}
+
+/*
+* status function used by tfa_dsp_msg() to retrieve command/msg status:
+* return a <0 status of the DSP did not ACK.
+*/
+enum Tfa98xx_Error tfa_dsp_msg_status(struct tfa_device *tfa, int *pRpcStatus)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+
+ error = tfa98xx_wait_result(tfa, 2); /* 2 is only one try */
+ if (error == Tfa98xx_Error_DSP_not_running) {
+ *pRpcStatus = -1;
+ return Tfa98xx_Error_Ok;
+ } else if (error != Tfa98xx_Error_Ok)
+ return error;
+
+ error = tfa98xx_check_rpc_status(tfa, pRpcStatus);
+
+ return error;
+}
+
+const char *tfa98xx_get_i2c_status_id_string(int status)
+{
+ const char *p_id_str;
+
+ switch (status) {
+ case Tfa98xx_DSP_Not_Running:
+ p_id_str = "No response from DSP";
+ break;
+ case Tfa98xx_I2C_Req_Done:
+ p_id_str = "Ok";
+ break;
+ case Tfa98xx_I2C_Req_Busy:
+ p_id_str = "Request is being processed";
+ break;
+ case Tfa98xx_I2C_Req_Invalid_M_ID:
+ p_id_str = "Provided M-ID does not fit in valid rang [0..2]";
+ break;
+ case Tfa98xx_I2C_Req_Invalid_P_ID:
+ p_id_str = "Provided P-ID is not valid in the given M-ID context";
+ break;
+ case Tfa98xx_I2C_Req_Invalid_CC:
+ p_id_str = "Invalid channel configuration bits (SC|DS|DP|DC) combination";
+ break;
+ case Tfa98xx_I2C_Req_Invalid_Seq:
+ p_id_str = "Invalid sequence of commands, in case the DSP expects some \
+ commands in a specific order";
+ break;
+ case Tfa98xx_I2C_Req_Invalid_Param:
+ p_id_str = "Generic error, invalid parameter";
+ break;
+ case Tfa98xx_I2C_Req_Buffer_Overflow:
+ p_id_str = "I2C buffer has overflowed: host has sent too many \
+ parameters, memory integrity is not guaranteed";
+ break;
+ case Tfa98xx_I2C_Req_Calib_Busy:
+ p_id_str = "Calibration not completed";
+ break;
+ case Tfa98xx_I2C_Req_Calib_Failed:
+ p_id_str = "Calibration failed";
+ break;
+
+ default:
+ p_id_str = "Unspecified error";
+ }
+
+ return p_id_str;
+}
+
+enum Tfa98xx_Error tfa_dsp_msg_read(struct tfa_device *tfa, int length,
+ unsigned char *bytes)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ int burst_size; /* number of words per burst size */
+ int bytes_per_word = 3;
+ int num_bytes;
+ int offset = 0;
+ unsigned short start_offset = 2; /* msg starts @xmem[2] ,[1]=cmd */
+
+ if (length > TFA2_MAX_PARAM_SIZE)
+ return Tfa98xx_Error_Bad_Parameter;
+
+ TFA_SET_BF(tfa, DMEM, (uint16_t)Tfa98xx_DMEM_XMEM);
+ error = -TFA_WRITE_REG(tfa, MADD, start_offset);
+ if (error != Tfa98xx_Error_Ok)
+ return error;
+
+ num_bytes = length; /* input param */
+ while (num_bytes > 0) {
+ burst_size = ROUND_DOWN(tfa->buffer_size, bytes_per_word);
+ if (num_bytes < burst_size)
+ burst_size = num_bytes;
+ error = tfa98xx_read_data(tfa, FAM_TFA98XX_CF_MEM, burst_size,
+ bytes + offset);
+ if (error != Tfa98xx_Error_Ok)
+ return error;
+
+ num_bytes -= burst_size;
+ offset += burst_size;
+ }
+
+ return error;
+}
+
+enum Tfa98xx_Error dsp_msg(struct tfa_device *tfa, int length24,
+ const char *buf24)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ int lastmessage = 0;
+ uint8_t *blob;
+ int i;
+ int *intbuf = NULL;
+ char *buf = (char *)buf24;
+ int length = length24;
+
+ if (tfa->convert_dsp32) {
+ int idx = 0;
+
+ length = 4 * length24 / 3;
+ intbuf = kmem_cache_alloc(tfa->cachep, GFP_KERNEL);
+ buf = (char *)intbuf;
+
+ /* convert 24 bit DSP messages to a 32 bit integer */
+ for (i = 0; i < length24; i += 3) {
+ int tmp = (buf24[i] << 16) + (buf24[i + 1] << 8) + buf24[i + 2];
+ /* Sign extend to 32-bit from 24-bit */
+ intbuf[idx++] = ((int32_t)tmp << 8) >> 8;
+ }
+ }
+
+ /* Only create multi-msg when the dsp is cold */
+ if (tfa->ext_dsp == 1) {
+ /* Creating the multi-msg */
+ error = tfa_tib_dsp_msgmulti(tfa, length, buf);
+ if (error == Tfa98xx_Error_Fail)
+ return Tfa98xx_Error_Fail;
+
+ /* if the buffer is full we need to send the existing message
+ * and add the current message
+ */
+ if (error == Tfa98xx_Error_Buffer_too_small) {
+ int len;
+
+ /* (a) send the existing (full) message */
+ blob = kmalloc(64 * 1024, GFP_KERNEL); // max length is 64k
+ len = tfa_tib_dsp_msgmulti(tfa, -1, (const char *)blob);
+ if (tfa->verbose) {
+ pr_debug("Multi-message buffer full. Sending multi-message,\
+ length=%d \n", len);
+ }
+ if (tfa->has_msg == 0) /* via i2c */ {
+ /* Send tot the target selected */
+ error = (tfa->dev_ops.dsp_msg)(tfa, len, (const char *)blob);
+ } else { /* via msg hal */
+ error = tfa98xx_write_dsp(tfa, len, (const char *)blob);
+ }
+ kfree(blob);
+
+ /* (b) add the current DSP message to a new multi-message */
+ error = tfa_tib_dsp_msgmulti(tfa, length, buf);
+ if (error == Tfa98xx_Error_Fail) {
+ return Tfa98xx_Error_Fail;
+ }
+ }
+
+ lastmessage = error;
+
+ /* When the lastmessage is done we can send the multi-msg to the target */
+ if (lastmessage == 1) {
+
+ /* Get the full multi-msg data */
+ blob = kmalloc(64 * 1024, GFP_KERNEL); //max length is 64k
+ length = tfa_tib_dsp_msgmulti(tfa, -1, (const char *)blob);
+
+ if (tfa->verbose)
+ pr_debug("Last message for the multi-message received.\
+ Multi-message length=%d \n", length);
+
+ if (tfa->has_msg == 0) /* via i2c */ {
+ /* Send tot the target selected */
+ error = (tfa->dev_ops.dsp_msg)(tfa, length, (const char *)blob);
+ } else { /* via msg hal */
+ error = tfa98xx_write_dsp(tfa, length, (const char *)blob);
+ }
+
+ kfree(blob); /* Free the kmalloc blob */
+ lastmessage = 0; /* reset to be able to re-start */
+ }
+ } else {
+ if (tfa->has_msg == 0) /* via i2c */ {
+ error = (tfa->dev_ops.dsp_msg)(tfa, length, buf);
+ } else { /* via msg hal */
+ error = tfa98xx_write_dsp(tfa, length, (const char *)buf);
+ }
+ }
+
+ if (error != Tfa98xx_Error_Ok)
+ /* Get actual error code from softDSP */
+ error = (enum Tfa98xx_Error) (error + Tfa98xx_Error_RpcBase);
+
+ /* DSP verbose has argument 0x04 */
+ if ((tfa->verbose & 0x04) != 0) {
+ pr_debug("DSP w [%d]: ", length);
+ for (i = 0; i < length; i++)
+ pr_debug("0x%02x ", (uint8_t)buf[i]);
+ pr_debug("\n");
+ }
+
+ if (tfa->convert_dsp32) {
+ kmem_cache_free(tfa->cachep, intbuf);
+ }
+
+ return error;
+}
+
+enum Tfa98xx_Error dsp_msg_read(struct tfa_device *tfa, int length24, unsigned char *bytes24)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ int i;
+ int length = length24;
+ unsigned char *bytes = bytes24;
+
+ if (tfa->convert_dsp32) {
+ length = 4 * length24 / 3;
+ bytes = kmem_cache_alloc(tfa->cachep, GFP_KERNEL);
+ }
+
+ if (tfa->has_msg == 0) /* via i2c */ {
+ error = (tfa->dev_ops.dsp_msg_read)(tfa, length, bytes);
+ } else { /* via msg hal */
+ error = tfa98xx_read_dsp(tfa, length, bytes);
+ }
+
+ if (error != Tfa98xx_Error_Ok)
+ error = (enum Tfa98xx_Error) (error + Tfa98xx_Error_RpcBase); /* Get actual error code from softDSP */
+
+ /* DSP verbose has argument 0x04 */
+ if ((tfa->verbose & 0x04) != 0) {
+ pr_debug("DSP R [%d]: ", length);
+ for (i = 0; i < length; i++)
+ pr_debug("0x%02x ", (uint8_t)bytes[i]);
+ pr_debug("\n");
+ }
+
+ if (tfa->convert_dsp32) {
+ int idx = 0;
+
+ /* convert 32 bit LE to 24 bit BE */
+ for (i = 0; i < length; i += 4) {
+ bytes24[idx++] = bytes[i + 2];
+ bytes24[idx++] = bytes[i + 1];
+ bytes24[idx++] = bytes[i + 0];
+ }
+
+ kmem_cache_free(tfa->cachep, bytes);
+ }
+
+ return error;
+}
+
+enum Tfa98xx_Error reg_read(struct tfa_device *tfa, unsigned char subaddress, unsigned short *value)
+{
+ enum Tfa98xx_Error error;
+
+ error = (tfa->dev_ops.reg_read)(tfa, subaddress, value);
+ if (error != Tfa98xx_Error_Ok)
+ error = (enum Tfa98xx_Error) (error + Tfa98xx_Error_RpcBase); /* Get actual error code from softDSP */
+
+ return error;
+}
+
+enum Tfa98xx_Error reg_write(struct tfa_device *tfa, unsigned char subaddress, unsigned short value)
+{
+ enum Tfa98xx_Error error;
+
+ error = (tfa->dev_ops.reg_write)(tfa, subaddress, value);
+ if (error != Tfa98xx_Error_Ok)
+ error = (enum Tfa98xx_Error) (error + Tfa98xx_Error_RpcBase); /* Get actual error code from softDSP */
+
+ return error;
+}
+
+enum Tfa98xx_Error mem_read(struct tfa_device *tfa, unsigned int start_offset, int num_words, int *pValues)
+{
+ enum Tfa98xx_Error error;
+
+ error = (tfa->dev_ops.mem_read)(tfa, start_offset, num_words, pValues);
+ if (error != Tfa98xx_Error_Ok)
+ error = (enum Tfa98xx_Error) (error + Tfa98xx_Error_RpcBase); /* Get actual error code from softDSP */
+
+ return error;
+}
+
+enum Tfa98xx_Error mem_write(struct tfa_device *tfa, unsigned short address, int value, int memtype)
+{
+ enum Tfa98xx_Error error;
+
+ error = (tfa->dev_ops.mem_write)(tfa, address, value, memtype);
+ if (error != Tfa98xx_Error_Ok)
+ error = (enum Tfa98xx_Error) (error + Tfa98xx_Error_RpcBase); /* Get actual error code from softDSP */
+
+ return error;
+}
+
+
+/*
+ * write/read raw msg functions :
+ * the buffer is provided in little endian format, each word occupying 3 bytes, length is in bytes.
+ * The functions will return immediately and do not not wait for DSP reponse.
+ */
+#define MAX_WORDS (300)
+enum Tfa98xx_Error tfa_dsp_msg(struct tfa_device *tfa, int length, const char *buf)
+{
+ enum Tfa98xx_Error error;
+ int tries, rpc_status = Tfa98xx_I2C_Req_Done;
+
+ /* write the message and notify the DSP */
+ error = tfa_dsp_msg_write(tfa, length, buf);
+ if (error != Tfa98xx_Error_Ok)
+ return error;
+
+ /* get the result from the DSP (polling) */
+ for (tries = TFA98XX_WAITRESULT_NTRIES; tries > 0; tries--) {
+ error = tfa_dsp_msg_status(tfa, &rpc_status);
+ if (error == Tfa98xx_Error_Ok && rpc_status == Tfa98xx_I2C_Req_Done)
+ break;
+ /* If the rpc status is a specific error we want to know it.
+ * If it is busy or not running it should retry
+ */
+ if (rpc_status != Tfa98xx_I2C_Req_Busy && rpc_status != Tfa98xx_DSP_Not_Running)
+ break;
+ }
+
+ if (rpc_status != Tfa98xx_I2C_Req_Done) {
+ /* DSP RPC call returned an error */
+ error = (enum Tfa98xx_Error) (rpc_status + Tfa98xx_Error_RpcBase);
+ pr_debug("DSP msg status: %d (%s)\n", rpc_status, tfa98xx_get_i2c_status_id_string(rpc_status));
+ }
+ return error;
+}
+
+/**
+ * write/read raw msg functions:
+ * the buffer is provided in little endian format, each word occupying 3 bytes, length is in bytes.
+ * The functions will return immediately and do not not wait for DSP reponse.
+ * An ID is added to modify the command-ID
+ */
+enum Tfa98xx_Error tfa_dsp_msg_id(struct tfa_device *tfa, int length, const char *buf, uint8_t cmdid[3])
+{
+ enum Tfa98xx_Error error;
+ int tries, rpc_status = Tfa98xx_I2C_Req_Done;
+
+ /* write the message and notify the DSP */
+ error = tfa_dsp_msg_write_id(tfa, length, buf, cmdid);
+ if (error != Tfa98xx_Error_Ok)
+ return error;
+
+ /* get the result from the DSP (polling) */
+ for (tries = TFA98XX_WAITRESULT_NTRIES; tries > 0; tries--) {
+ error = tfa_dsp_msg_status(tfa, &rpc_status);
+ if (error == Tfa98xx_Error_Ok && rpc_status == Tfa98xx_I2C_Req_Done)
+ break;
+ }
+
+ if (rpc_status != Tfa98xx_I2C_Req_Done) {
+ /* DSP RPC call returned an error */
+ error = (enum Tfa98xx_Error) (rpc_status + Tfa98xx_Error_RpcBase);
+ pr_debug("DSP msg status: %d (%s)\n", rpc_status, tfa98xx_get_i2c_status_id_string(rpc_status));
+ }
+ return error;
+}
+
+/* read the return code for the RPC call */
+TFA_INTERNAL enum Tfa98xx_Error
+tfa98xx_check_rpc_status(struct tfa_device *tfa, int *pRpcStatus)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ /* the value to sent to the * CF_CONTROLS register: cf_req=00000000,
+ * cf_int=0, cf_aif=0, cf_dmem=XMEM=01, cf_rst_dsp=0 */
+ unsigned short cf_ctrl = 0x0002;
+ /* memory address to be accessed (0: Status, 1: ID, 2: parameters) */
+ unsigned short cf_mad = 0x0000;
+
+ if (tfa->in_use == 0)
+ return Tfa98xx_Error_NotOpen;
+ if (pRpcStatus == NULL)
+ return Tfa98xx_Error_Bad_Parameter;
+
+ /* 1) write DMEM=XMEM to the DSP XMEM */
+ {
+ /* minimize the number of I2C transactions by making use of the autoincrement in I2C */
+ unsigned char buffer[4];
+ /* first the data for CF_CONTROLS */
+ buffer[0] = (unsigned char)((cf_ctrl >> 8) & 0xFF);
+ buffer[1] = (unsigned char)(cf_ctrl & 0xFF);
+ /* write the contents of CF_MAD which is the subaddress following CF_CONTROLS */
+ buffer[2] = (unsigned char)((cf_mad >> 8) & 0xFF);
+ buffer[3] = (unsigned char)(cf_mad & 0xFF);
+ error = tfa98xx_write_data(tfa, FAM_TFA98XX_CF_CONTROLS, sizeof(buffer), buffer);
+ }
+ if (error == Tfa98xx_Error_Ok) {
+ /* read 1 word (24 bit) from XMEM */
+ error = tfa98xx_dsp_read_mem(tfa, 0, 1, pRpcStatus);
+ }
+
+ return error;
+}
+
+/***************************** xmem only **********************************/
+enum Tfa98xx_Error
+ tfa98xx_dsp_read_mem(struct tfa_device *tfa,
+ unsigned int start_offset, int num_words, int *pValues)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ unsigned char *bytes;
+ int burst_size; /* number of words per burst size */
+ const int bytes_per_word = 3;
+ int dmem;
+ int num_bytes;
+ int *p;
+
+ bytes = (unsigned char *)kmem_cache_alloc(tfa->cachep, GFP_KERNEL);
+ if (bytes == NULL)
+ return Tfa98xx_Error_Fail;
+
+ /* If no offset is given, assume XMEM! */
+ if (((start_offset >> 16) & 0xf) > 0)
+ dmem = (start_offset >> 16) & 0xf;
+ else
+ dmem = Tfa98xx_DMEM_XMEM;
+
+ /* Remove offset from adress */
+ start_offset = start_offset & 0xffff;
+ num_bytes = num_words * bytes_per_word;
+ p = pValues;
+
+ TFA_SET_BF(tfa, DMEM, (uint16_t)dmem);
+ error = -TFA_WRITE_REG(tfa, MADD, (unsigned short)start_offset);
+ if (error != Tfa98xx_Error_Ok)
+ goto tfa98xx_dsp_read_mem_exit;
+
+ for (; num_bytes > 0;) {
+ burst_size = ROUND_DOWN(tfa->buffer_size, bytes_per_word);
+ if (num_bytes < burst_size)
+ burst_size = num_bytes;
+
+ _ASSERT(burst_size <= sizeof(bytes));
+ error = tfa98xx_read_data(tfa, FAM_TFA98XX_CF_MEM, burst_size, bytes);
+ if (error != Tfa98xx_Error_Ok)
+ goto tfa98xx_dsp_read_mem_exit;
+
+ tfa98xx_convert_bytes2data(burst_size, bytes, p);
+
+ num_bytes -= burst_size;
+ p += burst_size / bytes_per_word;
+ }
+
+tfa98xx_dsp_read_mem_exit:
+ kmem_cache_free(tfa->cachep, bytes);
+
+ return error;
+}
+
+
+enum Tfa98xx_Error
+ tfa98xx_dsp_write_mem_word(struct tfa_device *tfa, unsigned short address, int value, int memtype)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ unsigned char bytes[3];
+
+ TFA_SET_BF(tfa, DMEM, (uint16_t)memtype);
+
+ error = -TFA_WRITE_REG(tfa, MADD, address);
+ if (error != Tfa98xx_Error_Ok)
+ return error;
+
+ tfa98xx_convert_data2bytes(1, &value, bytes);
+ error = tfa98xx_write_data(tfa, FAM_TFA98XX_CF_MEM, 3, bytes);
+
+ return error;
+}
+
+enum Tfa98xx_Error tfa_cont_write_filterbank(struct tfa_device *tfa, nxpTfaFilter_t *filter)
+{
+ unsigned char biquad_index;
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+
+ for (biquad_index = 0; biquad_index < 10; biquad_index++) {
+ if (filter[biquad_index].enabled) {
+ error = tfa_dsp_cmd_id_write(tfa, MODULE_BIQUADFILTERBANK,
+ biquad_index + 1, //start @1
+ sizeof(filter[biquad_index].biquad.bytes),
+ filter[biquad_index].biquad.bytes);
+ } else {
+ error = Tfa98xx_DspBiquad_Disable(tfa, biquad_index + 1);
+ }
+ if (error)
+ return error;
+
+ }
+
+ return error;
+}
+
+enum Tfa98xx_Error
+ Tfa98xx_DspBiquad_Disable(struct tfa_device *tfa, int biquad_index)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ int coeff_buffer[BIQUAD_COEFF_SIZE];
+ unsigned char bytes[3 + BIQUAD_COEFF_SIZE * 3];
+ int nr = 0;
+
+ if (biquad_index > TFA98XX_BIQUAD_NUM)
+ return Tfa98xx_Error_Bad_Parameter;
+ if (biquad_index < 1)
+ return Tfa98xx_Error_Bad_Parameter;
+
+ /* make opcode */
+ bytes[nr++] = 0;
+ bytes[nr++] = MODULE_BIQUADFILTERBANK + 128;
+ bytes[nr++] = (unsigned char)biquad_index;
+
+
+ /* set in correct order and format for the DSP */
+ coeff_buffer[0] = (int)-8388608; /* -1.0f */
+ coeff_buffer[1] = 0;
+ coeff_buffer[2] = 0;
+ coeff_buffer[3] = 0;
+ coeff_buffer[4] = 0;
+ coeff_buffer[5] = 0;
+
+ /* convert to packed 24 */
+ tfa98xx_convert_data2bytes(BIQUAD_COEFF_SIZE, coeff_buffer, &bytes[nr]);
+ nr += BIQUAD_COEFF_SIZE * 3;
+
+ error = dsp_msg(tfa, nr, (char *)bytes);
+
+ return error;
+}
+
+/* wrapper for dsp_msg that adds opcode */
+enum Tfa98xx_Error tfa_dsp_cmd_id_write(struct tfa_device *tfa,
+ unsigned char module_id,
+ unsigned char param_id, int num_bytes,
+ const unsigned char data[])
+{
+ enum Tfa98xx_Error error;
+ unsigned char *buffer;
+ int nr = 0;
+
+ buffer = kmem_cache_alloc(tfa->cachep, GFP_KERNEL);
+ if (buffer == NULL)
+ return Tfa98xx_Error_Fail;
+
+ buffer[nr++] = tfa->spkr_select;
+ buffer[nr++] = module_id + 128;
+ buffer[nr++] = param_id;
+
+ memcpy(&buffer[nr], data, num_bytes);
+ nr += num_bytes;
+
+ error = dsp_msg(tfa, nr, (char *)buffer);
+
+ kmem_cache_free(tfa->cachep, buffer);
+
+ return error;
+}
+
+/* wrapper for dsp_msg that adds opcode */
+/* this is as the former tfa98xx_dsp_get_param() */
+enum Tfa98xx_Error tfa_dsp_cmd_id_write_read(struct tfa_device *tfa,
+ unsigned char module_id,
+ unsigned char param_id, int num_bytes,
+ unsigned char data[])
+{
+ enum Tfa98xx_Error error;
+ unsigned char buffer[3];
+ int nr = 0;
+
+ if (num_bytes <= 0) {
+ pr_debug("Error: The number of READ bytes is smaller or equal to 0! \n");
+ return Tfa98xx_Error_Fail;
+ }
+
+ if ((tfa->is_probus_device) && (tfa->cnt->ndev == 1) &&
+ (param_id == SB_PARAM_GET_RE25C ||
+ param_id == SB_PARAM_GET_LSMODEL ||
+ param_id == SB_PARAM_GET_ALGO_PARAMS)) {
+ /* Modifying the ID for GetRe25C */
+ buffer[nr++] = 4;
+ } else {
+ buffer[nr++] = tfa->spkr_select;
+ }
+ buffer[nr++] = module_id + 128;
+ buffer[nr++] = param_id;
+
+ error = dsp_msg(tfa, nr, (char *)buffer);
+ if (error != Tfa98xx_Error_Ok)
+ return error;
+
+ /* read the data from the dsp */
+ error = dsp_msg_read(tfa, num_bytes, data);
+ return error;
+}
+
+/* wrapper for dsp_msg that adds opcode and 3 bytes required for coefs */
+enum Tfa98xx_Error tfa_dsp_cmd_id_coefs(struct tfa_device *tfa,
+ unsigned char module_id,
+ unsigned char param_id, int num_bytes,
+ unsigned char data[])
+{
+ enum Tfa98xx_Error error;
+ unsigned char buffer[2 * 3];
+ int nr = 0;
+
+ buffer[nr++] = tfa->spkr_select;
+ buffer[nr++] = module_id + 128;
+ buffer[nr++] = param_id;
+
+ buffer[nr++] = 0;
+ buffer[nr++] = 0;
+ buffer[nr++] = 0;
+
+ error = dsp_msg(tfa, nr, (char *)buffer);
+ if (error != Tfa98xx_Error_Ok)
+ return error;
+
+ /* read the data from the dsp */
+ error = dsp_msg_read(tfa, num_bytes, data);
+
+ return error;
+}
+
+/* wrapper for dsp_msg that adds opcode and 3 bytes required for MBDrcDynamics */
+enum Tfa98xx_Error tfa_dsp_cmd_id_MBDrc_dynamics(struct tfa_device *tfa,
+ unsigned char module_id,
+ unsigned char param_id, int index_subband,
+ int num_bytes, unsigned char data[])
+{
+ enum Tfa98xx_Error error;
+ unsigned char buffer[2 * 3];
+ int nr = 0;
+
+ buffer[nr++] = tfa->spkr_select;
+ buffer[nr++] = module_id + 128;
+ buffer[nr++] = param_id;
+
+ buffer[nr++] = 0;
+ buffer[nr++] = 0;
+ buffer[nr++] = (unsigned char)index_subband;
+
+ error = dsp_msg(tfa, nr, (char *)buffer);
+ if (error != Tfa98xx_Error_Ok)
+ return error;
+
+ /* read the data from the dsp */
+ error = dsp_msg_read(tfa, num_bytes, data);
+
+ return error;
+}
+
+enum Tfa98xx_Error
+ tfa98xx_dsp_write_preset(struct tfa_device *tfa, int length,
+ const unsigned char *p_preset_bytes)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ if (p_preset_bytes != NULL) {
+ /* by design: keep the data opaque and no
+ * interpreting/calculation */
+ error = tfa_dsp_cmd_id_write(tfa, MODULE_SPEAKERBOOST,
+ SB_PARAM_SET_PRESET, length,
+ p_preset_bytes);
+ } else {
+ error = Tfa98xx_Error_Bad_Parameter;
+ }
+ return error;
+}
+
+/*
+ * get features from MTP
+ */
+enum Tfa98xx_Error
+ tfa98xx_dsp_get_hw_feature_bits(struct tfa_device *tfa, int *features)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ uint32_t value;
+ uint16_t mtpbf;
+
+ /* return the cache data if it's valid */
+ if (tfa->hw_feature_bits != -1) {
+ *features = tfa->hw_feature_bits;
+ } else {
+ /* for tfa1 check if we have clock */
+ if (tfa->tfa_family == 1) {
+ int status;
+ tfa98xx_dsp_system_stable(tfa, &status);
+ if (!status) {
+ get_hw_features_from_cnt(tfa, features);
+ /* skip reading MTP: */
+ return (*features == -1) ? Tfa98xx_Error_Fail : Tfa98xx_Error_Ok;
+ }
+ mtpbf = 0x850f; /* MTP5 for tfa1,16 bits */
+ } else
+ mtpbf = 0xf907; /* MTP9 for tfa2, 8 bits */
+ value = tfa_read_reg(tfa, mtpbf) & 0xffff;
+ *features = tfa->hw_feature_bits = value;
+ }
+
+ return error;
+}
+
+enum Tfa98xx_Error
+ tfa98xx_dsp_get_sw_feature_bits(struct tfa_device *tfa, int features[2])
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ const int byte_size = 2 * 3;
+ unsigned char bytes[2 * 3];
+
+ /* return the cache data if it's valid */
+ if (tfa->sw_feature_bits[0] != -1) {
+ features[0] = tfa->sw_feature_bits[0];
+ features[1] = tfa->sw_feature_bits[1];
+ } else {
+ /* for tfa1 check if we have clock */
+ if (tfa->tfa_family == 1) {
+ int status;
+ tfa98xx_dsp_system_stable(tfa, &status);
+ if (!status) {
+ get_sw_features_from_cnt(tfa, features);
+ /* skip reading MTP: */
+ return (features[0] == -1) ? Tfa98xx_Error_Fail : Tfa98xx_Error_Ok;
+ }
+ }
+ error = tfa_dsp_cmd_id_write_read(tfa, MODULE_FRAMEWORK,
+ FW_PAR_ID_GET_FEATURE_INFO, byte_size, bytes);
+
+ if (error != Tfa98xx_Error_Ok) {
+ /* old ROM code may respond with Tfa98xx_Error_RpcParamId */
+ return error;
+ }
+
+ tfa98xx_convert_bytes2data(byte_size, bytes, features);
+ }
+ return error;
+}
+
+enum Tfa98xx_Error tfa98xx_dsp_get_state_info(struct tfa_device *tfa, unsigned char bytes[], unsigned int *statesize)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ int bSupportFramework = 0;
+ unsigned int stateSize = 9;
+
+ err = tfa98xx_dsp_support_framework(tfa, &bSupportFramework);
+ if (err == Tfa98xx_Error_Ok) {
+ if (bSupportFramework) {
+ err = tfa_dsp_cmd_id_write_read(tfa, MODULE_FRAMEWORK,
+ FW_PARAM_GET_STATE, 3 * stateSize, bytes);
+ } else {
+ /* old ROM code, ask SpeakerBoost and only do first portion */
+ stateSize = 8;
+ err = tfa_dsp_cmd_id_write_read(tfa, MODULE_SPEAKERBOOST,
+ SB_PARAM_GET_STATE, 3 * stateSize, bytes);
+ }
+ }
+
+ *statesize = stateSize;
+
+ return err;
+}
+
+enum Tfa98xx_Error tfa98xx_dsp_support_drc(struct tfa_device *tfa, int *pbSupportDrc)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+
+ *pbSupportDrc = 0;
+
+ if (tfa->in_use == 0)
+ return Tfa98xx_Error_NotOpen;
+ if (tfa->supportDrc != supportNotSet) {
+ *pbSupportDrc = (tfa->supportDrc == supportYes);
+ } else {
+ int featureBits[2];
+
+ error = tfa98xx_dsp_get_sw_feature_bits(tfa, featureBits);
+ if (error == Tfa98xx_Error_Ok) {
+ /* easy case: new API available */
+ /* bit=0 means DRC enabled */
+ *pbSupportDrc = (featureBits[0] & FEATURE1_DRC) == 0;
+ } else if (error == Tfa98xx_Error_RpcParamId) {
+ /* older ROM code, doesn't support it */
+ *pbSupportDrc = 0;
+ error = Tfa98xx_Error_Ok;
+ }
+ /* else some other error, return transparently */
+ /* pbSupportDrc only changed when error == Tfa98xx_Error_Ok */
+
+ if (error == Tfa98xx_Error_Ok) {
+ tfa->supportDrc = *pbSupportDrc ? supportYes : supportNo;
+ }
+ }
+ return error;
+}
+
+enum Tfa98xx_Error
+ tfa98xx_dsp_support_framework(struct tfa_device *tfa, int *pbSupportFramework)
+{
+ int featureBits[2] = { 0, 0 };
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+
+ _ASSERT(pbSupportFramework != 0);
+
+ if (tfa->in_use == 0)
+ return Tfa98xx_Error_NotOpen;
+
+ if (tfa->supportFramework != supportNotSet) {
+ if (tfa->supportFramework == supportNo)
+ *pbSupportFramework = 0;
+ else
+ *pbSupportFramework = 1;
+ } else {
+ error = tfa98xx_dsp_get_sw_feature_bits(tfa, featureBits);
+ if (error == Tfa98xx_Error_Ok) {
+ *pbSupportFramework = 1;
+ tfa->supportFramework = supportYes;
+ } else {
+ *pbSupportFramework = 0;
+ tfa->supportFramework = supportNo;
+ error = Tfa98xx_Error_Ok;
+ }
+ }
+
+ /* *pbSupportFramework only changed when error == Tfa98xx_Error_Ok */
+ return error;
+}
+
+enum Tfa98xx_Error
+ tfa98xx_dsp_write_speaker_parameters(struct tfa_device *tfa,
+ int length, const unsigned char *p_speaker_bytes)
+{
+ enum Tfa98xx_Error error;
+ int bSupportDrc;
+
+ if (p_speaker_bytes != NULL) {
+ /* by design: keep the data opaque and no
+ * interpreting/calculation */
+ /* Use long WaitResult retry count */
+ error = tfa_dsp_cmd_id_write(
+ tfa,
+ MODULE_SPEAKERBOOST,
+ SB_PARAM_SET_LSMODEL, length,
+ p_speaker_bytes);
+ } else {
+ error = Tfa98xx_Error_Bad_Parameter;
+ }
+
+ if (error != Tfa98xx_Error_Ok)
+ return error;
+
+ error = tfa98xx_dsp_support_drc(tfa, &bSupportDrc);
+ if (error != Tfa98xx_Error_Ok)
+ return error;
+
+ if (bSupportDrc) {
+ /* Need to set AgcGainInsert back to PRE,
+ * as the SetConfig forces it to POST */
+ uint8_t bytes[3] = { 0, 0, 0 };
+
+ error = tfa_dsp_cmd_id_write(tfa,
+ MODULE_SPEAKERBOOST,
+ SB_PARAM_SET_AGCINS,
+ 3,
+ bytes);
+ }
+
+ return error;
+}
+
+enum Tfa98xx_Error
+ tfa98xx_dsp_write_config(struct tfa_device *tfa, int length,
+ const unsigned char *p_config_bytes)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ int bSupportDrc;
+
+ error = tfa_dsp_cmd_id_write(tfa,
+ MODULE_SPEAKERBOOST,
+ SB_PARAM_SET_CONFIG, length,
+ p_config_bytes);
+ if (error != Tfa98xx_Error_Ok)
+ return error;
+
+ error = tfa98xx_dsp_support_drc(tfa, &bSupportDrc);
+ if (error != Tfa98xx_Error_Ok)
+ return error;
+
+ if (bSupportDrc) {
+ /* Need to set AgcGainInsert back to PRE,
+ * as the SetConfig forces it to POST */
+ uint8_t bytes[3] = { 0, 0, 0 };
+
+ error = tfa_dsp_cmd_id_write(tfa,
+ MODULE_SPEAKERBOOST,
+ SB_PARAM_SET_AGCINS,
+ 3,
+ bytes);
+ }
+
+ return error;
+}
+
+/* load all the parameters for the DRC settings from a file */
+enum Tfa98xx_Error tfa98xx_dsp_write_drc(struct tfa_device *tfa,
+ int length, const unsigned char *p_drc_bytes)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ if (p_drc_bytes != NULL) {
+ error = tfa_dsp_cmd_id_write(tfa,
+ MODULE_SPEAKERBOOST,
+ SB_PARAM_SET_DRC, length,
+ p_drc_bytes);
+
+ } else {
+ error = Tfa98xx_Error_Bad_Parameter;
+ }
+ return error;
+}
+
+enum Tfa98xx_Error tfa98xx_powerdown(struct tfa_device *tfa, int powerdown)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+
+ if (tfa->in_use == 0)
+ return Tfa98xx_Error_NotOpen;
+
+ error = TFA_SET_BF(tfa, PWDN, (uint16_t)powerdown);
+
+ if (powerdown) {
+ /* Workaround for ticket PLMA5337 */
+ if (tfa->tfa_family == 2) {
+ TFA_SET_BF_VOLATILE(tfa, AMPE, 0);
+ }
+ }
+
+ return error;
+}
+
+enum Tfa98xx_Error
+ tfa98xx_select_mode(struct tfa_device *tfa, enum Tfa98xx_Mode mode)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+
+ if (tfa->in_use == 0)
+ return Tfa98xx_Error_NotOpen;
+
+ if (error == Tfa98xx_Error_Ok) {
+ switch (mode) {
+
+ default:
+ error = Tfa98xx_Error_Bad_Parameter;
+ }
+ }
+
+ return error;
+}
+
+int tfa_set_bf(struct tfa_device *tfa, const uint16_t bf, const uint16_t value)
+{
+ enum Tfa98xx_Error err;
+ uint16_t regvalue, msk, oldvalue;
+
+ /*
+ * bitfield enum:
+ * - 0..3 : len
+ * - 4..7 : pos
+ * - 8..15 : address
+ */
+ uint8_t len = bf & 0x0f;
+ uint8_t pos = (bf >> 4) & 0x0f;
+ uint8_t address = (bf >> 8) & 0xff;
+
+ err = reg_read(tfa, address, ®value);
+ if (err) {
+ pr_err("Error getting bf :%d \n", -err);
+ return -err;
+ }
+
+ oldvalue = regvalue;
+ msk = ((1 << (len + 1)) - 1) << pos;
+ regvalue &= ~msk;
+ regvalue |= value << pos;
+
+ /* Only write when the current register value is not the same as the new value */
+ if (oldvalue != regvalue) {
+ err = reg_write(tfa, address, regvalue);
+ if (err) {
+ pr_err("Error setting bf :%d \n", -err);
+ return -err;
+ }
+ }
+
+ return 0;
+}
+
+int tfa_set_bf_volatile(struct tfa_device *tfa, const uint16_t bf, const uint16_t value)
+{
+ enum Tfa98xx_Error err;
+ uint16_t regvalue, msk;
+
+ /*
+ * bitfield enum:
+ * - 0..3 : len
+ * - 4..7 : pos
+ * - 8..15 : address
+ */
+ uint8_t len = bf & 0x0f;
+ uint8_t pos = (bf >> 4) & 0x0f;
+ uint8_t address = (bf >> 8) & 0xff;
+
+ err = reg_read(tfa, address, ®value);
+ if (err) {
+ pr_err("Error getting bf :%d \n", -err);
+ return -err;
+ }
+
+ msk = ((1 << (len + 1)) - 1) << pos;
+ regvalue &= ~msk;
+ regvalue |= value << pos;
+
+ err = reg_write(tfa, address, regvalue);
+ if (err) {
+ pr_err("Error setting bf :%d \n", -err);
+ return -err;
+ }
+
+ return 0;
+}
+
+int tfa_get_bf(struct tfa_device *tfa, const uint16_t bf)
+{
+ enum Tfa98xx_Error err;
+ uint16_t regvalue, msk;
+ uint16_t value;
+
+ /*
+ * bitfield enum:
+ * - 0..3 : len
+ * - 4..7 : pos
+ * - 8..15 : address
+ */
+ uint8_t len = bf & 0x0f;
+ uint8_t pos = (bf >> 4) & 0x0f;
+ uint8_t address = (bf >> 8) & 0xff;
+
+ err = reg_read(tfa, address, ®value);
+ if (err) {
+ pr_err("Error getting bf :%d \n", -err);
+ return -err;
+ }
+
+ msk = ((1 << (len + 1)) - 1) << pos;
+ regvalue &= msk;
+ value = regvalue >> pos;
+
+ return value;
+}
+
+int tfa_set_bf_value(const uint16_t bf, const uint16_t bf_value, uint16_t *p_reg_value)
+{
+ uint16_t regvalue, msk;
+
+ /*
+ * bitfield enum:
+ * - 0..3 : len
+ * - 4..7 : pos
+ * - 8..15 : address
+ */
+ uint8_t len = bf & 0x0f;
+ uint8_t pos = (bf >> 4) & 0x0f;
+
+ regvalue = *p_reg_value;
+
+ msk = ((1 << (len + 1)) - 1) << pos;
+ regvalue &= ~msk;
+ regvalue |= bf_value << pos;
+
+ *p_reg_value = regvalue;
+
+ return 0;
+}
+
+uint16_t tfa_get_bf_value(const uint16_t bf, const uint16_t reg_value)
+{
+ uint16_t msk, value;
+
+ /*
+ * bitfield enum:
+ * - 0..3 : len
+ * - 4..7 : pos
+ * - 8..15 : address
+ */
+ uint8_t len = bf & 0x0f;
+ uint8_t pos = (bf >> 4) & 0x0f;
+
+ msk = ((1 << (len + 1)) - 1) << pos;
+ value = (reg_value & msk) >> pos;
+
+ return value;
+}
+
+
+int tfa_write_reg(struct tfa_device *tfa, const uint16_t bf, const uint16_t reg_value)
+{
+ enum Tfa98xx_Error err;
+
+ /* bitfield enum - 8..15 : address */
+ uint8_t address = (bf >> 8) & 0xff;
+
+ err = reg_write(tfa, address, reg_value);
+ if (err)
+ return -err;
+
+ return 0;
+}
+
+int tfa_read_reg(struct tfa_device *tfa, const uint16_t bf)
+{
+ enum Tfa98xx_Error err;
+ uint16_t regvalue;
+
+ /* bitfield enum - 8..15 : address */
+ uint8_t address = (bf >> 8) & 0xff;
+
+ err = reg_read(tfa, address, ®value);
+ if (err)
+ return -err;
+
+ return regvalue;
+}
+
+/*
+ * powerup the coolflux subsystem and wait for it
+ */
+enum Tfa98xx_Error tfa_cf_powerup(struct tfa_device *tfa)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ int tries, status;
+
+ /* power on the sub system */
+ TFA_SET_BF_VOLATILE(tfa, PWDN, 0);
+
+ // wait until everything is stable, in case clock has been off
+ if (tfa->verbose)
+ pr_info("Waiting for DSP system stable...\n");
+ for (tries = CFSTABLE_TRIES; tries > 0; tries--) {
+ err = tfa98xx_dsp_system_stable(tfa, &status);
+ _ASSERT(err == Tfa98xx_Error_Ok);
+ if (status)
+ break;
+ else
+ msleep_interruptible(10); /* wait 10ms to avoid busload */
+ }
+ if (tries == 0) {// timedout
+ pr_err("DSP subsystem start timed out\n");
+ return Tfa98xx_Error_StateTimedOut;
+ }
+
+ return err;
+}
+
+/*
+ * Enable/Disable the I2S output for TFA1 devices
+ * without TDM interface
+ */
+static enum Tfa98xx_Error tfa98xx_aec_output(struct tfa_device *tfa, int enable)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+
+ if ((tfa->daimap & Tfa98xx_DAI_TDM) == Tfa98xx_DAI_TDM)
+ return err;
+
+ if (tfa->tfa_family == 1)
+ err = -tfa_set_bf(tfa, TFA1_BF_I2SDOE, (enable != 0));
+ else {
+ pr_err("I2SDOE on unsupported family\n");
+ err = Tfa98xx_Error_Not_Supported;
+ }
+
+ return err;
+}
+
+/*
+ * Print the current state of the hardware manager
+ * Device manager status information, man_state from TFA9888_N1B_I2C_regmap_V12
+ */
+int is_94_N2_device(struct tfa_device *tfa)
+{
+ return ((((tfa->rev) & 0xff) == 0x94) && (((tfa->rev >> 8) & 0xff) > 0x1a));
+}
+enum Tfa98xx_Error show_current_state(struct tfa_device *tfa)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ int manstate = -1;
+
+ if (tfa->tfa_family == 2 && tfa->verbose) {
+ if (is_94_N2_device(tfa))
+ manstate = tfa_get_bf(tfa, TFA9894N2_BF_MANSTATE);
+ else
+ manstate = TFA_GET_BF(tfa, MANSTATE);
+ if (manstate < 0)
+ return -manstate;
+
+ pr_debug("Current HW manager state: ");
+
+ switch (manstate) {
+ case 0:
+ pr_debug("power_down_state \n");
+ break;
+ case 1:
+ pr_debug("wait_for_source_settings_state \n");
+ break;
+ case 2:
+ pr_debug("connnect_pll_input_state \n");
+ break;
+ case 3:
+ pr_debug("disconnect_pll_input_state \n");
+ break;
+ case 4:
+ pr_debug("enable_pll_state \n");
+ break;
+ case 5:
+ pr_debug("enable_cgu_state \n");
+ break;
+ case 6:
+ pr_debug("init_cf_state \n");
+ break;
+ case 7:
+ pr_debug("enable_amplifier_state \n");
+ break;
+ case 8:
+ pr_debug("alarm_state \n");
+ break;
+ case 9:
+ pr_debug("operating_state \n");
+ break;
+ case 10:
+ pr_debug("mute_audio_state \n");
+ break;
+ case 11:
+ pr_debug("disable_cgu_pll_state \n");
+ break;
+ default:
+ pr_debug("Unable to find current state \n");
+ break;
+ }
+ }
+
+ return err;
+}
+
+enum Tfa98xx_Error tfaGetFwApiVersion(struct tfa_device *tfa, unsigned char *pFirmwareVersion)
+{
+ enum Tfa98xx_Error err = 0;
+ char cmd_buf[4];
+ int cmd_len, res_len;
+
+ if (tfa == NULL)
+ return Tfa98xx_Error_Bad_Parameter;
+ if (!tfa->is_probus_device) {
+ err = mem_read(tfa, FW_VAR_API_VERSION, 1, (int *)pFirmwareVersion);
+ if (err) {
+ pr_debug("%s Error: Unable to get API Version from DSP \n", __FUNCTION__);
+ return err;
+ }
+ } else {
+ cmd_len = 0x03;
+
+ /* GetAPI: Command is 0x00 0x80 0xFE */
+ cmd_buf[0] = 0x00;
+ cmd_buf[1] = 0x80;
+ cmd_buf[2] = 0xFE;
+
+ /* Write the command.*/
+
+ err = tfa98xx_write_dsp(tfa, cmd_len, (const char *)cmd_buf);
+
+ /* Read the API Value.*/
+ if (err == 0) {
+ res_len = 3;
+ err = tfa98xx_read_dsp(tfa, res_len, (unsigned char *)pFirmwareVersion);
+
+ }
+ }
+ return err;
+
+}
+
+
+/*
+ * start the speakerboost algorithm
+ * this implies a full system startup when the system was not already started
+ *
+ */
+enum Tfa98xx_Error tfaRunSpeakerBoost(struct tfa_device *tfa, int force, int profile)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ int value;
+
+ if (force) {
+ err = tfaRunColdStartup(tfa, profile);
+ if (err)
+ return err;
+ }
+
+ /* Returns 1 when device is "cold" and 0 when device is warm */
+ value = tfa_is_cold(tfa);
+
+ pr_debug("Startup of device [%s] is a %sstart\n", tfaContDeviceName(tfa->cnt, tfa->dev_idx), value ? "cold" : "warm");
+ /* cold start and not tap profile */
+ if (value) {
+ /* Run startup and write all files */
+ err = tfaRunSpeakerStartup(tfa, force, profile);
+ if (err)
+ return err;
+
+ /* Save the current profile and set the vstep to 0 */
+ /* This needs to be overwriten even in CF bypass */
+ tfa_dev_set_swprof(tfa, (unsigned short)profile);
+ tfa_dev_set_swvstep(tfa, 0);
+
+ /* Synchonize I/V delay on 96/97 at cold start */
+ if ((tfa->tfa_family == 1) && (tfa->daimap == Tfa98xx_DAI_TDM))
+ tfa->sync_iv_delay = 1;
+ }
+
+ return err;
+}
+
+enum Tfa98xx_Error tfaRunSpeakerStartup(struct tfa_device *tfa, int force, int profile)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+
+ if (!force) { // in case of force CF already runnning
+ err = tfaRunStartup(tfa, profile);
+ PRINT_ASSERT(err);
+ if (err)
+ return err;
+
+ /* Startup with CF in bypass then return here */
+ if (tfa_cf_enabled(tfa) == 0)
+ return err;
+
+ /* respond to external DSP: -1:none, 0:no_dsp, 1:cold, 2:warm */
+ if (tfa->ext_dsp == -1) {
+ err = tfaRunStartDSP(tfa);
+ if (err)
+ return err;
+ }
+ }
+
+ /* Set auto_copy_mtp_to_iic (bit 5 of A3) to 1 */
+ tfa98xx_auto_copy_mtp_to_iic(tfa);
+
+ err = tfaGetFwApiVersion(tfa, (unsigned char *)&tfa->fw_itf_ver[0]);
+ if (err) {
+ pr_debug("[%s] cannot get FWAPI error = %d \n", __FUNCTION__, err);
+ return err;
+ }
+ /* write all the files from the device list */
+ err = tfaContWriteFiles(tfa);
+ if (err) {
+ pr_debug("[%s] tfaContWriteFiles error = %d \n", __FUNCTION__, err);
+ return err;
+ }
+
+ /* write all the files from the profile list (use volumstep 0) */
+ err = tfaContWriteFilesProf(tfa, profile, 0);
+ if (err) {
+ pr_debug("[%s] tfaContWriteFilesProf error = %d \n", __FUNCTION__, err);
+ return err;
+ }
+
+ return err;
+}
+
+/*
+ * Run calibration
+ */
+enum Tfa98xx_Error tfaRunSpeakerCalibration(struct tfa_device *tfa)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ int calibrateDone;
+
+ /* return if there is no audio running */
+ if ((tfa->tfa_family == 2) && TFA_GET_BF(tfa, NOCLK))
+ return Tfa98xx_Error_NoClock;
+
+ /* When MTPOTC is set (cal=once) unlock key2 */
+ if (TFA_GET_BF(tfa, MTPOTC) == 1) {
+ tfa98xx_key2(tfa, 0);
+ }
+
+ /* await calibration, this should return ok */
+ err = tfaRunWaitCalibration(tfa, &calibrateDone);
+ if (err == Tfa98xx_Error_Ok) {
+ err = tfa_dsp_get_calibration_impedance(tfa);
+ PRINT_ASSERT(err);
+ }
+
+ /* When MTPOTC is set (cal=once) re-lock key2 */
+ if (TFA_GET_BF(tfa, MTPOTC) == 1) {
+ tfa98xx_key2(tfa, 1);
+ }
+
+ return err;
+}
+
+enum Tfa98xx_Error tfaRunColdboot(struct tfa_device *tfa, int state)
+{
+#define CF_CONTROL 0x8100
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ int tries = 10;
+
+ /* repeat set ACS bit until set as requested */
+ while (state != TFA_GET_BF(tfa, ACS)) {
+ /* set colstarted in CF_CONTROL to force ACS */
+ err = mem_write(tfa, CF_CONTROL, state, Tfa98xx_DMEM_IOMEM);
+ PRINT_ASSERT(err);
+
+ if (tries-- == 0) {
+ pr_debug("coldboot (ACS) did not %s\n", state ? "set" : "clear");
+ return Tfa98xx_Error_Other;
+ }
+ }
+
+ return err;
+}
+
+
+
+/*
+ * load the patch if any
+ * else tell no loaded
+ */
+static enum Tfa98xx_Error tfa_run_load_patch(struct tfa_device *tfa)
+{
+ return tfaContWritePatch(tfa);
+}
+
+/*
+ * this will load the patch witch will implicitly start the DSP
+ * if no patch is available the DPS is started immediately
+ */
+enum Tfa98xx_Error tfaRunStartDSP(struct tfa_device *tfa)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+
+ err = tfa_run_load_patch(tfa);
+ if (err) { /* patch load is fatal so return immediately*/
+ return err;
+ }
+
+ /* Clear count_boot, should be reset to 0 before the DSP reset is released */
+ err = mem_write(tfa, 512, 0, Tfa98xx_DMEM_XMEM);
+ PRINT_ASSERT(err);
+
+ /* Reset DSP once for sure after initializing */
+ if (err == Tfa98xx_Error_Ok) {
+ err = tfa98xx_dsp_reset(tfa, 0);
+ PRINT_ASSERT(err);
+ }
+
+ /* Sample rate is needed to set the correct tables */
+ err = tfa98xx_dsp_write_tables(tfa, TFA_GET_BF(tfa, AUDFS));
+ PRINT_ASSERT(err);
+
+ return err;
+}
+
+/*
+ * start the clocks and wait until the AMP is switching
+ * on return the DSP sub system will be ready for loading
+ */
+enum Tfa98xx_Error tfaRunStartup(struct tfa_device *tfa, int profile)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ nxpTfaDeviceList_t *dev = tfaContDevice(tfa->cnt, tfa->dev_idx);
+ int i, noinit = 0, audfs = 0, fractdel = 0;
+
+ if (dev == NULL)
+ return Tfa98xx_Error_Fail;
+
+ if (dev->bus) /* no i2c device, do nothing */
+ return Tfa98xx_Error_Ok;
+
+ /* process the device list to see if the user implemented the noinit */
+ for (i = 0; i < dev->length; i++) {
+ if (dev->list[i].type == dscNoInit) {
+ noinit = 1;
+ break;
+ }
+ }
+
+ if (!noinit) {
+ /* Read AUDFS & FRACTDEL prior to (re)init. */
+ audfs = TFA_GET_BF(tfa, AUDFS);
+ fractdel = TFA_GET_BF(tfa, FRACTDEL);
+ /* load the optimal TFA98XX in HW settings */
+ err = tfa98xx_init(tfa);
+ PRINT_ASSERT(err);
+
+ /* Restore audfs & fractdel after coldboot, so we can calibrate with correct fs setting.
+ * in case something else was given in cnt file, profile below will apply this. */
+ TFA_SET_BF(tfa, AUDFS, audfs);
+ TFA_SET_BF(tfa, FRACTDEL, fractdel);
+ } else {
+ pr_debug("\nWarning: No init keyword found in the cnt file. Init is skipped! \n");
+ }
+
+ /* I2S settings to define the audio input properties
+ * these must be set before the subsys is up */
+ // this will run the list until a non-register item is encountered
+ err = tfaContWriteRegsDev(tfa); // write device register settings
+ PRINT_ASSERT(err);
+ // also write register the settings from the default profile
+ // NOTE we may still have ACS=1 so we can switch sample rate here
+ err = tfaContWriteRegsProf(tfa, profile);
+ PRINT_ASSERT(err);
+
+ /* Factory trimming for the Boost converter */
+ tfa98xx_factory_trimmer(tfa);
+
+ /* Go to the initCF state */
+ tfa_dev_set_state(tfa, TFA_STATE_INIT_CF, strstr(tfaContProfileName(tfa->cnt, tfa->dev_idx, profile), ".cal") != NULL);
+
+ err = show_current_state(tfa);
+
+ return err;
+}
+
+/*
+ * run the startup/init sequence and set ACS bit
+ */
+enum Tfa98xx_Error tfaRunColdStartup(struct tfa_device *tfa, int profile)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+
+ err = tfaRunStartup(tfa, profile);
+ PRINT_ASSERT(err);
+ if (err)
+ return err;
+
+ if (!tfa->is_probus_device) {
+ /* force cold boot */
+ err = tfaRunColdboot(tfa, 1); // set ACS
+ PRINT_ASSERT(err);
+ if (err)
+ return err;
+ }
+
+ /* start */
+ err = tfaRunStartDSP(tfa);
+ PRINT_ASSERT(err);
+
+ return err;
+}
+
+/*
+ *
+ */
+enum Tfa98xx_Error tfaRunMute(struct tfa_device *tfa)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ int status;
+ int tries = 0;
+
+ /* signal the TFA98XX to mute */
+ if (tfa->tfa_family == 1) {
+ err = tfa98xx_set_mute(tfa, Tfa98xx_Mute_Amplifier);
+
+ if (err == Tfa98xx_Error_Ok) {
+ /* now wait for the amplifier to turn off */
+ do {
+ status = TFA_GET_BF(tfa, SWS);
+ if (status != 0)
+ msleep_interruptible(10); /* wait 10ms to avoid busload */
+ else
+ break;
+ tries++;
+ } while (tries < AMPOFFWAIT_TRIES);
+
+
+ if (tfa->verbose)
+ pr_debug("-------------------- muted --------------------\n");
+
+ /*The amplifier is always switching*/
+ if (tries == AMPOFFWAIT_TRIES)
+ return Tfa98xx_Error_Other;
+ }
+ }
+
+ return err;
+}
+/*
+ *
+ */
+enum Tfa98xx_Error tfaRunUnmute(struct tfa_device *tfa)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+
+ /* signal the TFA98XX to mute */
+ err = tfa98xx_set_mute(tfa, Tfa98xx_Mute_Off);
+
+ if (tfa->verbose)
+ pr_debug("-------------------unmuted ------------------\n");
+
+ return err;
+}
+
+static void individual_calibration_results(struct tfa_device *tfa)
+{
+ int value_P, value_S;
+
+ /* Read the calibration result in xmem (529=primary channel) (530=secondary channel) */
+ mem_read(tfa, 529, 1, &value_P);
+ mem_read(tfa, 530, 1, &value_S);
+
+ if (value_P != 1 && value_S != 1)
+ pr_debug("Calibration failed on both channels! \n");
+ else if (value_P != 1) {
+ pr_debug("Calibration failed on Primary (Left) channel! \n");
+ TFA_SET_BF_VOLATILE(tfa, SSLEFTE, 0); /* Disable the sound for the left speaker */
+ } else if (value_S != 1) {
+ pr_debug("Calibration failed on Secondary (Right) channel! \n");
+ TFA_SET_BF_VOLATILE(tfa, SSRIGHTE, 0); /* Disable the sound for the right speaker */
+ }
+
+ TFA_SET_BF_VOLATILE(tfa, AMPINSEL, 0); /* Set amplifier input to TDM */
+ TFA_SET_BF_VOLATILE(tfa, SBSL, 1);
+}
+
+/*
+ * wait for calibrateDone
+ */
+enum Tfa98xx_Error tfaRunWaitCalibration(struct tfa_device *tfa, int *calibrateDone)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ int tries = 0, mtp_busy = 1, tries_mtp_busy = 0;
+
+ *calibrateDone = 0;
+
+ /* in case of calibrate once wait for MTPEX */
+ if (TFA_GET_BF(tfa, MTPOTC)) {
+ // Check if MTP_busy is clear!
+ while (tries_mtp_busy < MTPBWAIT_TRIES) {
+ mtp_busy = tfa_dev_get_mtpb(tfa);
+ if (mtp_busy == 1)
+ msleep_interruptible(10); /* wait 10ms to avoid busload */
+ else
+ break;
+ tries_mtp_busy++;
+ }
+
+ if (tries_mtp_busy < MTPBWAIT_TRIES) {
+ /* Because of the msleep TFA98XX_API_WAITRESULT_NTRIES is way to long!
+ * Setting this to 25 will take it atleast 25*50ms = 1.25 sec
+ */
+ while ((*calibrateDone == 0) && (tries < MTPEX_WAIT_NTRIES)) {
+ *calibrateDone = TFA_GET_BF(tfa, MTPEX);
+ if (*calibrateDone == 1)
+ break;
+ msleep_interruptible(50); /* wait 50ms to avoid busload */
+ tries++;
+ }
+
+ if (tries >= MTPEX_WAIT_NTRIES) {
+ tries = TFA98XX_API_WAITRESULT_NTRIES;
+ }
+ } else {
+ pr_err("MTP bussy after %d tries\n", MTPBWAIT_TRIES);
+ }
+ }
+
+ /* poll xmem for calibrate always
+ * calibrateDone = 0 means "calibrating",
+ * calibrateDone = -1 (or 0xFFFFFF) means "fails"
+ * calibrateDone = 1 means calibration done
+ */
+ while ((*calibrateDone != 1) && (tries < TFA98XX_API_WAITRESULT_NTRIES)) {
+ err = mem_read(tfa, TFA_FW_XMEM_CALIBRATION_DONE, 1, calibrateDone);
+ if (*calibrateDone == -1)
+ break;
+ tries++;
+ }
+
+ if (*calibrateDone != 1) {
+ pr_err("Calibration failed! \n");
+ err = Tfa98xx_Error_Bad_Parameter;
+ } else if (tries == TFA98XX_API_WAITRESULT_NTRIES) {
+ pr_debug("Calibration has timedout! \n");
+ err = Tfa98xx_Error_StateTimedOut;
+ } else if (tries_mtp_busy == 1000) {
+ pr_err("Calibrate Failed: MTP_busy stays high! \n");
+ err = Tfa98xx_Error_StateTimedOut;
+ }
+
+ /* Give reason why calibration failed! */
+ if (err != Tfa98xx_Error_Ok) {
+ if ((tfa->tfa_family == 2) && (TFA_GET_BF(tfa, REFCKSEL) == 1)) {
+ pr_err("Unable to calibrate the device with the internal clock! \n");
+ }
+ }
+
+ /* Check which speaker calibration failed. Only for 88C */
+ if ((err != Tfa98xx_Error_Ok) && ((tfa->rev & 0x0FFF) == 0xc88)) {
+ individual_calibration_results(tfa);
+ }
+
+ return err;
+}
+
+/*
+ * tfa_dev_start will only do the basics: Going from powerdown to operating or a profile switch.
+ * for calibrating or akoustic shock handling use the tfa98xxCalibration function.
+ */
+enum tfa_error tfa_dev_start(struct tfa_device *tfa, int next_profile, int vstep)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ int active_profile = -1;
+
+ /* Get currentprofile */
+ active_profile = tfa_dev_get_swprof(tfa);
+ if (active_profile == 0xff)
+ active_profile = -1;
+ /* TfaRun_SpeakerBoost implies un-mute */
+ pr_debug("Active_profile:%s, next_profile:%s\n",
+ tfaContProfileName(tfa->cnt, tfa->dev_idx, active_profile),
+ tfaContProfileName(tfa->cnt, tfa->dev_idx, next_profile));
+
+ err = show_current_state(tfa);
+
+ if (tfa->tfa_family == 1) { /* TODO move this to ini file */
+ /* Enable I2S output on TFA1 devices without TDM */
+ err = tfa98xx_aec_output(tfa, 1);
+ if (err != Tfa98xx_Error_Ok)
+ goto error_exit;
+ }
+
+ if (tfa->bus != 0) { /* non i2c */
+#ifndef __KERNEL__
+ tfadsp_fw_start(tfa, next_profile, vstep);
+#endif /* __KERNEL__ */
+ } else {
+ /* Check if we need coldstart or ACS is set */
+ err = tfaRunSpeakerBoost(tfa, 0, next_profile);
+ if (err != Tfa98xx_Error_Ok)
+ goto error_exit;
+
+ /* Make sure internal oscillator is running for DSP devices (non-dsp and max1 this is no-op) */
+ tfa98xx_set_osc_powerdown(tfa, 0);
+
+ /* Go to the Operating state */
+ tfa_dev_set_state(tfa, TFA_STATE_OPERATING | TFA_STATE_MUTE, 0);
+ }
+ active_profile = tfa_dev_get_swprof(tfa);
+
+ /* Profile switching */
+ if ((next_profile != active_profile && active_profile >= 0)) {
+ err = tfaContWriteProfile(tfa, next_profile, vstep);
+ if (err != Tfa98xx_Error_Ok)
+ goto error_exit;
+ }
+
+ /* If the profile contains the .standby suffix go to powerdown
+ * else we should be in operating state
+ */
+ if (strstr(tfaContProfileName(tfa->cnt, tfa->dev_idx, next_profile), ".standby") != NULL) {
+ tfa_dev_set_swprof(tfa, (unsigned short)next_profile);
+ tfa_dev_set_swvstep(tfa, (unsigned short)vstep);
+ goto error_exit;
+ }
+
+ err = show_current_state(tfa);
+
+ if ((TFA_GET_BF(tfa, CFE) != 0) && (vstep != tfa->vstep) && (vstep != -1)) {
+ err = tfaContWriteFilesVstep(tfa, next_profile, vstep);
+ if (err != Tfa98xx_Error_Ok)
+ goto error_exit;
+ }
+
+
+ /* Always search and apply filters after a startup */
+ err = tfa_set_filters(tfa, next_profile);
+ if (err != Tfa98xx_Error_Ok)
+ goto error_exit;
+
+ tfa_dev_set_swprof(tfa, (unsigned short)next_profile);
+ tfa_dev_set_swvstep(tfa, (unsigned short)vstep);
+
+ /* PLMA5539: Gives information about current setting of powerswitch */
+ if (tfa->verbose) {
+ if (!tfa98xx_powerswitch_is_enabled(tfa))
+ pr_info("Device start without powerswitch enabled!\n");
+ }
+
+error_exit:
+ show_current_state(tfa);
+
+ return (enum tfa_error)err;
+}
+
+enum tfa_error tfa_dev_stop(struct tfa_device *tfa)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+
+ /* mute */
+ tfaRunMute(tfa);
+
+ /* Make sure internal oscillator is not running for DSP devices (non-dsp and max1 this is no-op) */
+ tfa98xx_set_osc_powerdown(tfa, 1);
+
+ /* powerdown CF */
+ err = tfa98xx_powerdown(tfa, 1);
+ if (err != Tfa98xx_Error_Ok)
+ return (enum tfa_error)err;
+
+ /* disable I2S output on TFA1 devices without TDM */
+ err = tfa98xx_aec_output(tfa, 0);
+
+ return (enum tfa_error)err;
+}
+
+/*
+ * int registers and coldboot dsp
+ */
+int tfa_reset(struct tfa_device *tfa)
+{
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ int state = -1;
+ int retry_cnt = 0;
+
+ /* Check device state. Print warning if reset is done from other state than powerdown (when verbose) */
+ state = tfa_dev_get_state(tfa);
+ if (tfa->verbose) {
+ if (((tfa->tfa_family == 1) && state != TFA_STATE_RESET) ||
+ ((tfa->tfa_family == 2) && state != TFA_STATE_POWERDOWN)) {
+ pr_info("WARNING: Device reset should be performed in POWERDOWN state\n");
+ }
+ }
+
+ /* Split TFA1 behavior from TFA2*/
+ if (tfa->tfa_family == 1) {
+ err = TFA_SET_BF(tfa, I2CR, 1);
+ if (err)
+ return err;
+ err = tfa98xx_powerdown(tfa, 0);
+ if (err)
+ return err;
+ err = tfa_cf_powerup(tfa);
+ if (err)
+ return err;
+ err = tfaRunColdboot(tfa, 1);
+ if (err)
+ return err;
+ err = TFA_SET_BF(tfa, I2CR, 1);
+ } else {
+ /* Probus devices needs extra protection to ensure proper reset
+ behavior, this step is valid only in state other than powerdown */
+ if (tfa->is_probus_device && state != TFA_STATE_POWERDOWN) {
+ err = TFA_SET_BF_VOLATILE(tfa, AMPE, 0);
+ if (err)
+ return err;
+ err = tfa98xx_powerdown(tfa, 1);
+ if (err)
+ return err;
+ }
+
+ err = TFA_SET_BF_VOLATILE(tfa, I2CR, 1);
+ if (err)
+ return err;
+
+ /* Restore MANSCONF to POR state */
+ err = TFA_SET_BF_VOLATILE(tfa, MANSCONF, 0);
+ if (err)
+ return err;
+
+ /* Probus devices HW are already reseted here,
+ Last step is to send init message to softDSP */
+ if (tfa->is_probus_device) {
+ if (tfa->ext_dsp > 0) {
+ err = tfa98xx_init_dsp(tfa);
+ /* ext_dsp status from warm to cold after reset */
+ if (tfa->ext_dsp == 2) {
+ tfa->ext_dsp = 1;
+ }
+ }
+ } else {
+ /* Restore MANCOLD to POR state */
+ TFA_SET_BF_VOLATILE(tfa, MANCOLD, 1);
+
+ /* Coolflux has to be powered on to ensure proper ACS
+ bit state */
+
+ /* Powerup CF to access CF io */
+ err = tfa98xx_powerdown(tfa, 0);
+ if (err)
+ return err;
+
+ /* For clock */
+ err = tfa_cf_powerup(tfa);
+ if (err)
+ return err;
+
+ /* Force cold boot */
+ err = tfaRunColdboot(tfa, 1); /* Set ACS */
+ if (err)
+ return err;
+
+ /* Set PWDN = 1, this will transfer device into powerdown state */
+ err = TFA_SET_BF_VOLATILE(tfa, PWDN, 1);
+ if (err)
+ return err;
+
+ /* 88 needs SBSL on top of PWDN bit to start transition,
+ for 92 and 94 this doesn't matter */
+ err = TFA_SET_BF_VOLATILE(tfa, SBSL, 1);
+ if (err)
+ return err;
+
+ /* Powerdown state should be reached within 1ms */
+ for (retry_cnt = 0; retry_cnt < TFA98XX_WAITRESULT_NTRIES; retry_cnt++) {
+ if (is_94_N2_device(tfa))
+ state = tfa_get_bf(tfa, TFA9894N2_BF_MANSTATE);
+ else
+ state = TFA_GET_BF(tfa, MANSTATE);
+ if (state < 0) {
+ return err;
+ }
+
+ /* Check for MANSTATE=Powerdown (0) */
+ if (state == 0)
+ break;
+ msleep_interruptible(2);
+ }
+
+ /* Reset all I2C registers to default values,
+ now device state is consistent, same as after powerup */
+ err = TFA_SET_BF(tfa, I2CR, 1);
+ }
+ }
+
+ return err;
+}
+
+/*
+ * Write all the bytes specified by num_bytes and data
+ */
+enum Tfa98xx_Error
+ tfa98xx_write_data(struct tfa_device *tfa,
+ unsigned char subaddress, int num_bytes,
+ const unsigned char data[])
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ /* subaddress followed by data */
+ const int bytes2write = num_bytes + 1;
+ unsigned char *write_data;
+
+ if (num_bytes > TFA2_MAX_PARAM_SIZE)
+ return Tfa98xx_Error_Bad_Parameter;
+
+ write_data = (unsigned char *)kmem_cache_alloc(tfa->cachep, GFP_KERNEL);
+ if (write_data == NULL)
+ return Tfa98xx_Error_Fail;
+
+ write_data[0] = subaddress;
+ memcpy(&write_data[1], data, num_bytes);
+
+ error = tfa98xx_write_raw(tfa, bytes2write, write_data);
+
+ kmem_cache_free(tfa->cachep, write_data);
+ return error;
+}
+
+/*
+ * fill the calibration value as milli ohms in the struct
+ *
+ * assume that the device has been calibrated
+ */
+enum Tfa98xx_Error tfa_dsp_get_calibration_impedance(struct tfa_device *tfa)
+{
+ enum Tfa98xx_Error error = Tfa98xx_Error_Ok;
+ unsigned char bytes[3 * 2] = { 0 };
+ int nr_bytes, i, data[2], calibrateDone, spkr_count = 0, cal_idx = 0;
+ unsigned int scaled_data;
+ int tries = 0;
+
+ error = tfa_supported_speakers(tfa, &spkr_count);
+
+ if (tfa_dev_mtp_get(tfa, TFA_MTP_OTC)) {
+ pr_debug("Getting calibration values from MTP\n");
+
+ if ((tfa->rev & 0xFF) == 0x88) {
+ for (i = 0; i < spkr_count; i++) {
+ if (i == 0)
+ tfa->mohm[i] = tfa_dev_mtp_get(tfa, TFA_MTP_RE25_PRIM);
+ else
+ tfa->mohm[i] = tfa_dev_mtp_get(tfa, TFA_MTP_RE25_SEC);
+ }
+ } else {
+ tfa->mohm[0] = tfa_dev_mtp_get(tfa, TFA_MTP_RE25);
+ }
+ } else {
+ pr_debug("Getting calibration values from Speakerboost\n");
+
+ /* Make sure the calibrateDone bit is set before getting the values from speakerboost!
+ * This does not work for 72 (because the dsp cannot set this bit)
+ */
+ if (!tfa->is_probus_device) {
+ /* poll xmem for calibrate always
+ * calibrateDone = 0 means "calibrating",
+ * calibrateDone = -1 (or 0xFFFFFF) means "fails"
+ * calibrateDone = 1 means calibration done
+ */
+ calibrateDone = 0;
+ while ((calibrateDone != 1) && (tries < TFA98XX_API_WAITRESULT_NTRIES)) {
+ error = mem_read(tfa, TFA_FW_XMEM_CALIBRATION_DONE, 1, &calibrateDone);
+ if (calibrateDone == 1)
+ break;
+ tries++;
+ }
+
+ if (calibrateDone != 1) {
+ pr_err("Calibration failed! \n");
+ error = Tfa98xx_Error_Bad_Parameter;
+ } else if (tries == TFA98XX_API_WAITRESULT_NTRIES) {
+ pr_debug("Calibration has timedout! \n");
+ error = Tfa98xx_Error_StateTimedOut;
+ }
+ }
+ /* SoftDSP interface differs from hw-dsp interfaces */
+ if (tfa->is_probus_device && tfa->cnt->ndev > 1) {
+ spkr_count = tfa->cnt->ndev;
+ }
+
+ nr_bytes = spkr_count * 3;
+ error = tfa_dsp_cmd_id_write_read(tfa, MODULE_SPEAKERBOOST, SB_PARAM_GET_RE25C, nr_bytes, bytes);
+ if (error == Tfa98xx_Error_Ok) {
+ tfa98xx_convert_bytes2data(nr_bytes, bytes, data);
+
+ for (i = 0; i < spkr_count; i++) {
+
+ /* for probus devices, calibration values coming from soft-dsp speakerboost,
+ are ordered in a different way. Re-align to standard representation. */
+ cal_idx = i;
+ if ((tfa->is_probus_device && tfa->dev_idx >= 1)) {
+ cal_idx = 0;
+ }
+
+ /* signed data has a limit of 30 Ohm */
+ scaled_data = data[i];
+
+ if (tfa->tfa_family == 2)
+ tfa->mohm[cal_idx] = (scaled_data * 1000) / TFA2_FW_ReZ_SCALE;
+ else
+ tfa->mohm[cal_idx] = (scaled_data * 1000) / TFA1_FW_ReZ_SCALE;
+ }
+ }
+ }
+
+ return error;
+}
+
+/* start count from 1, 0 is invalid */
+int tfa_dev_get_swprof(struct tfa_device *tfa)
+{
+ return (tfa->dev_ops.get_swprof)(tfa);
+}
+
+int tfa_dev_set_swprof(struct tfa_device *tfa, unsigned short new_value)
+{
+ return (tfa->dev_ops.set_swprof)(tfa, new_value + 1);
+}
+
+/* same value for all channels
+ * start count from 1, 0 is invalid */
+int tfa_dev_get_swvstep(struct tfa_device *tfa)
+{
+ return (tfa->dev_ops.get_swvstep)(tfa);
+}
+
+int tfa_dev_set_swvstep(struct tfa_device *tfa, unsigned short new_value)
+{
+ return (tfa->dev_ops.set_swvstep)(tfa, new_value + 1);
+}
+
+/*
+ function overload for MTPB
+ */
+int tfa_dev_get_mtpb(struct tfa_device *tfa)
+{
+ return (tfa->dev_ops.get_mtpb)(tfa);
+}
+
+int tfa_is_cold(struct tfa_device *tfa)
+{
+ int value;
+
+ /*
+ * check for cold boot status
+ */
+ if (tfa->is_probus_device) {
+ if (tfa->ext_dsp > 0) {
+ if (tfa->ext_dsp == 2)
+ value = 0; // warm
+ else /* no dsp or cold */
+ value = 1; // cold
+ } else {
+ value = (TFA_GET_BF(tfa, MANSCONF) == 0);
+ }
+ } else {
+ value = TFA_GET_BF(tfa, ACS);
+ }
+
+ return value;
+}
+
+int tfa_needs_reset(struct tfa_device *tfa)
+{
+ int value;
+
+ /* checks if the DSP commands SetAlgoParams and SetMBDrc
+ * need a DSP reset (now: at coldstart or during calibration)
+ */
+ if (tfa_is_cold(tfa) == 1 || tfa->needs_reset == 1)
+ value = 1;
+ else
+ value = 0;
+
+ return value;
+}
+
+int tfa_cf_enabled(struct tfa_device *tfa)
+{
+ int value;
+
+ /* For 72 there is no CF */
+ if (tfa->is_probus_device) {
+ value = (tfa->ext_dsp != 0);
+ } else {
+ value = TFA_GET_BF(tfa, CFE);
+ }
+
+ return value;
+}
+
+#define NR_COEFFS 6
+#define NR_BIQUADS 28
+#define BQ_SIZE (3 * NR_COEFFS)
+#define DSP_MSG_OVERHEAD 27
+
+#pragma pack (push, 1)
+struct dsp_msg_all_coeff {
+ uint8_t select_eq[3];
+ uint8_t biquad[NR_BIQUADS][NR_COEFFS][3];
+};
+#pragma pack (pop)
+
+/* number of biquads for each equalizer */
+static const int eq_biquads[] = {
+ 10, 10, 2, 2, 2, 2
+};
+
+#define NR_EQ (int)(sizeof(eq_biquads) / sizeof(int))
+
+enum Tfa98xx_Error dsp_partial_coefficients(struct tfa_device *tfa, uint8_t *prev, uint8_t *next)
+{
+ uint8_t bq, eq;
+ int eq_offset;
+ int new_cost, old_cost;
+ uint32_t eq_biquad_mask[NR_EQ];
+ enum Tfa98xx_Error err = Tfa98xx_Error_Ok;
+ struct dsp_msg_all_coeff *data1 = (struct dsp_msg_all_coeff *)prev;
+ struct dsp_msg_all_coeff *data2 = (struct dsp_msg_all_coeff *)next;
+
+ old_cost = DSP_MSG_OVERHEAD + 3 + sizeof(struct dsp_msg_all_coeff);
+ new_cost = 0;
+
+ eq_offset = 0;
+ for (eq = 0; eq < NR_EQ; eq++) {
+ uint8_t *eq1 = &data1->biquad[eq_offset][0][0];
+ uint8_t *eq2 = &data2->biquad[eq_offset][0][0];
+
+ eq_biquad_mask[eq] = 0;
+
+ if (memcmp(eq1, eq2, BQ_SIZE*eq_biquads[eq]) != 0) {
+ int nr_bq = 0;
+ int bq_sz, eq_sz;
+
+ for (bq = 0; bq < eq_biquads[eq]; bq++) {
+ uint8_t *bq1 = &eq1[bq*BQ_SIZE];
+ uint8_t *bq2 = &eq2[bq*BQ_SIZE];
+
+ if (memcmp(bq1, bq2, BQ_SIZE) != 0) {
+ eq_biquad_mask[eq] |= (1 << bq);
+ nr_bq++;
+ }
+ }
+
+ bq_sz = (2 * 3 + BQ_SIZE) * nr_bq;
+ eq_sz = 2 * 3 + BQ_SIZE * eq_biquads[eq];
+
+ /* dsp message i2c transaction overhead */
+ bq_sz += DSP_MSG_OVERHEAD * nr_bq;
+ eq_sz += DSP_MSG_OVERHEAD;
+
+ if (bq_sz >= eq_sz) {
+ eq_biquad_mask[eq] = 0xffffffff;
+
+ new_cost += eq_sz;
+
+ } else {
+ new_cost += bq_sz;
+ }
+ }
+ pr_debug("eq_biquad_mask[%d] = 0x%.8x\n", eq, eq_biquad_mask[eq]);
+
+ eq_offset += eq_biquads[eq];
+ }
+
+ pr_debug("cost for writing all coefficients = %d\n", old_cost);
+ pr_debug("cost for writing changed coefficients = %d\n", new_cost);
+
+ if (new_cost >= old_cost) {
+ const int buffer_sz = 3 + sizeof(struct dsp_msg_all_coeff);
+ uint8_t *buffer;
+
+ buffer = kmalloc(buffer_sz, GFP_KERNEL);
+ if (buffer == NULL)
+ return Tfa98xx_Error_Fail;
+
+ /* cmd id */
+ buffer[0] = 0x00;
+ buffer[1] = 0x82;
+ buffer[2] = 0x00;
+
+ /* parameters */
+ memcpy(&buffer[3], data2, sizeof(struct dsp_msg_all_coeff));
+
+ err = dsp_msg(tfa, buffer_sz, (const char *)buffer);
+
+ kfree(buffer);
+ if (err)
+ return err;
+
+ } else {
+ eq_offset = 0;
+ for (eq = 0; eq < NR_EQ; eq++) {
+ uint8_t *eq2 = &data2->biquad[eq_offset][0][0];
+
+ if (eq_biquad_mask[eq] == 0xffffffff) {
+ const int msg_sz = 6 + BQ_SIZE * eq_biquads[eq];
+ uint8_t *msg;
+
+ msg = kmalloc(msg_sz, GFP_KERNEL);
+ if (msg == NULL)
+ return Tfa98xx_Error_Fail;
+
+ /* cmd id */
+ msg[0] = 0x00;
+ msg[1] = 0x82;
+ msg[2] = 0x00;
+
+ /* select eq and bq */
+ msg[3] = 0x00;
+ msg[4] = eq + 1;
+ msg[5] = 0x00; /* all biquads */
+
+ /* biquad parameters */
+ memcpy(&msg[6], eq2, BQ_SIZE * eq_biquads[eq]);
+
+ err = dsp_msg(tfa, msg_sz, (const char *)msg);
+
+ kfree(msg);
+ if (err)
+ return err;
+
+ } else if (eq_biquad_mask[eq] != 0) {
+ for (bq = 0; bq < eq_biquads[eq]; bq++) {
+
+ if (eq_biquad_mask[eq] & (1 << bq)) {
+ uint8_t *bq2 = &eq2[bq*BQ_SIZE];
+ const int msg_sz = 6 + BQ_SIZE;
+ uint8_t *msg;
+
+ msg = kmem_cache_alloc(tfa->cachep, GFP_KERNEL);
+ if (msg == NULL)
+ return Tfa98xx_Error_Fail;
+
+ /* cmd id */
+ msg[0] = 0x00;
+ msg[1] = 0x82;
+ msg[2] = 0x00;
+
+ /* select eq and bq*/
+ msg[3] = 0x00;
+ msg[4] = eq + 1;
+ msg[5] = bq + 1;
+
+ /* biquad parameters */
+ memcpy(&msg[6], bq2, BQ_SIZE);
+
+ err = dsp_msg(tfa, msg_sz, (const char *)msg);
+
+ kmem_cache_free(tfa->cachep, msg);
+ if (err)
+ return err;
+ }
+ }
+ }
+ eq_offset += eq_biquads[eq];
+ }
+ }
+
+ return err;
+}
+
+/* fill context info */
+int tfa_dev_probe(int slave, struct tfa_device *tfa)
+{
+ uint16_t rev;
+
+ tfa->slave_address = (unsigned char)slave;
+
+ /* read revid via low level hal, register 3 */
+ if (tfa98xx_read_register16(tfa, 3, &rev) != Tfa98xx_Error_Ok) {
+ PRINT("\nError: Unable to read revid from slave:0x%02x \n", slave);
+ return ERR;
+ }
+
+ tfa->rev = rev;
+ tfa->dev_idx = -1;
+ tfa->state = TFA_STATE_UNKNOWN;
+ tfa->p_regInfo = NULL;
+
+ tfa_set_query_info(tfa);
+
+ tfa->in_use = 1;
+
+ return 0;
+}
+
+enum tfa_error tfa_dev_set_state(struct tfa_device *tfa, enum tfa_state state, int is_calibration)
+{
+ enum tfa_error err = tfa_error_ok;
+ int loop = 50, ready = 0;
+ int count;
+
+ /* Base states */
+ /* Do not change the order of setting bits as this is important! */
+ switch (state & 0x0f) {
+ case TFA_STATE_POWERDOWN: /* PLL in powerdown, Algo up */
+ break;
+ case TFA_STATE_INIT_HW: /* load I2C/PLL hardware setting (~wait2srcsettings) */
+ break;
+ case TFA_STATE_INIT_CF: /* coolflux HW access possible (~initcf) */
+ /* Start with SBSL=0 to stay in initCF state */
+ if (!tfa->is_probus_device)
+ TFA_SET_BF(tfa, SBSL, 0);
+
+ /* We want to leave Wait4SrcSettings state for max2 */
+ if (tfa->tfa_family == 2)
+ TFA_SET_BF(tfa, MANSCONF, 1);
+
+ /* And finally set PWDN to 0 to leave powerdown state */
+ TFA_SET_BF(tfa, PWDN, 0);
+
+ /* Make sure the DSP is running! */
+ do {
+ err = (enum tfa_error)tfa98xx_dsp_system_stable(tfa,
+ &ready);
+ if (err != tfa_error_ok)
+ return err;
+ if (ready)
+ break;
+ } while (loop--);
+ if (((!tfa->is_probus_device) && (is_calibration)) || ((tfa->rev & 0xff) == 0x13)) {
+ /* Enable FAIM when clock is stable, to avoid MTP corruption */
+ err = (enum tfa_error)tfa98xx_faim_protect(tfa, 1);
+ if (tfa->verbose) {
+ pr_debug("FAIM enabled (err:%d).\n", err);
+ }
+ }
+ break;
+ case TFA_STATE_INIT_FW: /* DSP framework active (~patch loaded) */
+ break;
+ case TFA_STATE_OPERATING: /* Amp and Algo running */
+ /* Depending on our previous state we need to set 3 bits */
+ TFA_SET_BF(tfa, PWDN, 0); /* Coming from state 0 */
+ TFA_SET_BF(tfa, MANSCONF, 1); /* Coming from state 1 */
+ if (!tfa->is_probus_device)
+ TFA_SET_BF(tfa, SBSL, 1); /* Coming from state 6 */
+ else
+ TFA_SET_BF(tfa, AMPE, 1); /* No SBSL for probus device, we set AMPE to 1 */
+
+ /*
+ * Disable MTP clock to protect memory.
+ * However in case of calibration wait for DSP! (This should be case only during calibration).
+ */
+ if (TFA_GET_BF(tfa, MTPOTC) == 1 && tfa->tfa_family == 2) {
+ count = MTPEX_WAIT_NTRIES * 4; /* Calibration takes a lot of time */
+ while ((TFA_GET_BF(tfa, MTPEX) != 1) && count) {
+ msleep_interruptible(10);
+ count--;
+ }
+ }
+ if (((!tfa->is_probus_device) && (is_calibration)) || ((tfa->rev & 0xff) == 0x13)) {
+ err = (enum tfa_error)tfa98xx_faim_protect(tfa, 0);
+ if (tfa->verbose) {
+ pr_debug("FAIM disabled (err:%d).\n", err);
+ }
+ }
+ /* Synchonize I/V delay on 96/97 at cold start */
+ if (tfa->sync_iv_delay) {
+ if (tfa->verbose)
+ pr_debug("syncing I/V delay for %x\n",
+ (tfa->rev & 0xff));
+
+ /* wait for ACS to be cleared */
+ count = 10;
+ while ((TFA_GET_BF(tfa, ACS) == 1) &&
+ (count-- > 0)) {
+ msleep_interruptible(1);
+ }
+
+ tfa98xx_dsp_reset(tfa, 1);
+ tfa98xx_dsp_reset(tfa, 0);
+ tfa->sync_iv_delay = 0;
+ }
+ break;
+ case TFA_STATE_FAULT: /* An alarm or error occurred */
+ break;
+ case TFA_STATE_RESET: /* I2C reset and ACS set */
+ tfa98xx_init(tfa);
+ break;
+ default:
+ if (state & 0x0f)
+ return tfa_error_bad_param;
+ }
+
+ /* state modifiers */
+
+ if (state & TFA_STATE_MUTE)
+ tfa98xx_set_mute(tfa, Tfa98xx_Mute_Amplifier);
+
+ if (state & TFA_STATE_UNMUTE)
+ tfa98xx_set_mute(tfa, Tfa98xx_Mute_Off);
+
+ tfa->state = state;
+
+ return tfa_error_ok;
+}
+
+enum tfa_state tfa_dev_get_state(struct tfa_device *tfa)
+{
+ int cold = 0;
+ int manstate;
+
+ /* different per family type */
+ if (tfa->tfa_family == 1) {
+ cold = TFA_GET_BF(tfa, ACS);
+ if (cold && TFA_GET_BF(tfa, PWDN))
+ tfa->state = TFA_STATE_RESET;
+ else if (!cold && TFA_GET_BF(tfa, SWS))
+ tfa->state = TFA_STATE_OPERATING;
+ } else /* family 2 */ {
+ if (is_94_N2_device(tfa))
+ manstate = tfa_get_bf(tfa, TFA9894N2_BF_MANSTATE);
+ else
+ manstate = TFA_GET_BF(tfa, MANSTATE);
+ switch (manstate) {
+ case 0:
+ tfa->state = TFA_STATE_POWERDOWN;
+ break;
+ case 8: /* if dsp reset if off assume framework is running */
+ tfa->state = TFA_GET_BF(tfa, RST) ? TFA_STATE_INIT_CF : TFA_STATE_INIT_FW;
+ break;
+ case 9:
+ tfa->state = TFA_STATE_OPERATING;
+ break;
+ default:
+ break;
+ }
+ }
+
+ return tfa->state;
+}
+
+int tfa_dev_mtp_get(struct tfa_device *tfa, enum tfa_mtp item)
+{
+ int value = 0;
+
+ switch (item) {
+ case TFA_MTP_OTC:
+ value = TFA_GET_BF(tfa, MTPOTC);
+ break;
+ case TFA_MTP_EX:
+ value = TFA_GET_BF(tfa, MTPEX);
+ break;
+ case TFA_MTP_RE25:
+ case TFA_MTP_RE25_PRIM:
+ if (tfa->tfa_family == 2) {
+ if ((tfa->rev & 0xFF) == 0x88)
+ value = TFA_GET_BF(tfa, R25CL);
+ else if ((tfa->rev & 0xFF) == 0x13)
+ value = tfa_get_bf(tfa, TFA9912_BF_R25C);
+ else
+ value = TFA_GET_BF(tfa, R25C);
+ } else {
+ reg_read(tfa, 0x83, (unsigned short *)&value);
+ }
+ break;
+ case TFA_MTP_RE25_SEC:
+ if ((tfa->rev & 0xFF) == 0x88) {
+ value = TFA_GET_BF(tfa, R25CR);
+ } else {
+ pr_debug("Error: Current device has no secondary Re25 channel \n");
+ }
+ break;
+ case TFA_MTP_LOCK:
+ break;
+ }
+
+ return value;
+}
+
+enum tfa_error tfa_dev_mtp_set(struct tfa_device *tfa, enum tfa_mtp item,
+ int value)
+{
+ enum tfa_error err = tfa_error_ok;
+
+ switch (item) {
+ case TFA_MTP_OTC:
+ err = (enum tfa_error)tfa98xx_set_mtp(tfa, (uint16_t)value,
+ TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC_MSK);
+ break;
+ case TFA_MTP_EX:
+ err = (enum tfa_error)tfa98xx_set_mtp(tfa, (uint16_t)value,
+ TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_MSK);
+ break;
+ case TFA_MTP_RE25:
+ case TFA_MTP_RE25_PRIM:
+ if (tfa->tfa_family == 2) {
+ tfa98xx_key2(tfa, 0); /* unlock */
+ if ((tfa->rev & 0xFF) == 0x88)
+ TFA_SET_BF(tfa, R25CL, (uint16_t)value);
+ else {
+ if (tfa->is_probus_device == 1 && TFA_GET_BF(tfa, MTPOTC) == 1)
+ tfa2_manual_mtp_cpy(tfa, 0xF4, value, 2);
+ TFA_SET_BF(tfa, R25C, (uint16_t)value);
+ }
+ tfa98xx_key2(tfa, 1); /* lock */
+ }
+ break;
+ case TFA_MTP_RE25_SEC:
+ if ((tfa->rev & 0xFF) == 0x88) {
+ TFA_SET_BF(tfa, R25CR, (uint16_t)value);
+ } else {
+ pr_debug("Error: Current device has no secondary Re25 channel \n");
+ err = tfa_error_bad_param;
+ }
+ break;
+ case TFA_MTP_LOCK:
+ break;
+ }
+
+ return (enum tfa_error)err;
+}
+
+int tfa_get_pga_gain(struct tfa_device *tfa)
+{
+ return TFA_GET_BF(tfa, SAAMGAIN);
+}
+
+int tfa_set_pga_gain(struct tfa_device *tfa, uint16_t value)
+{
+
+ return TFA_SET_BF(tfa, SAAMGAIN, value);
+}
+
+int tfa_get_noclk(struct tfa_device *tfa)
+{
+ return TFA_GET_BF(tfa, NOCLK);
+}
+
+
+enum Tfa98xx_Error tfa_status(struct tfa_device *tfa)
+{
+ int value;
+ uint16_t val;
+
+ /*
+ * check IC status bits: cold start
+ * and DSP watch dog bit to re init
+ */
+ value = TFA_READ_REG(tfa, VDDS); /* STATUSREG */
+ if (value < 0)
+ return -value;
+ val = (uint16_t)value;
+
+ /* pr_debug("SYS_STATUS0: 0x%04x\n", val); */
+ if (TFA_GET_BF_VALUE(tfa, ACS, val) ||
+ TFA_GET_BF_VALUE(tfa, WDS, val)) {
+
+ if (TFA_GET_BF_VALUE(tfa, ACS, val))
+ pr_err("ERROR: ACS\n");
+ if (TFA_GET_BF_VALUE(tfa, WDS, val))
+ pr_err("ERROR: WDS\n");
+
+ return Tfa98xx_Error_DSP_not_running;
+ }
+
+ if (TFA_GET_BF_VALUE(tfa, SPKS, val))
+ pr_err("ERROR: SPKS\n");
+ if (!TFA_GET_BF_VALUE(tfa, SWS, val))
+ pr_err("ERROR: SWS\n");
+
+ /* Check secondary errors */
+ if (!TFA_GET_BF_VALUE(tfa, CLKS, val) ||
+ !TFA_GET_BF_VALUE(tfa, UVDS, val) ||
+ !TFA_GET_BF_VALUE(tfa, OVDS, val) ||
+ !TFA_GET_BF_VALUE(tfa, OTDS, val) ||
+ !TFA_GET_BF_VALUE(tfa, PLLS, val) ||
+ (!(tfa->daimap & Tfa98xx_DAI_TDM) &&
+ !TFA_GET_BF_VALUE(tfa, VDDS, val)))
+ pr_err("Misc errors detected: STATUS_FLAG0 = 0x%x\n", val);
+
+ if ((tfa->daimap & Tfa98xx_DAI_TDM) && (tfa->tfa_family == 2)) {
+ value = TFA_READ_REG(tfa, TDMERR); /* STATUS_FLAGS1 */
+ if (value < 0)
+ return -value;
+ val = (uint16_t)value;
+ if (TFA_GET_BF_VALUE(tfa, TDMERR, val) ||
+ TFA_GET_BF_VALUE(tfa, TDMLUTER, val))
+ pr_err("TDM related errors: STATUS_FLAG1 = 0x%x\n", val);
+ }
+
+ return Tfa98xx_Error_Ok;
+}
+
+int tfa_plop_noise_interrupt(struct tfa_device *tfa, int profile, int vstep)
+{
+ enum Tfa98xx_Error err;
+ int no_clk = 0;
+
+ /* Remove sticky bit by reading it once */
+ TFA_GET_BF(tfa, NOCLK);
+
+ /* No clock detected */
+ if (tfa_irq_get(tfa, tfa9912_irq_stnoclk)) {
+ no_clk = TFA_GET_BF(tfa, NOCLK);
+
+ /* Detect for clock is lost! (clock is not stable) */
+ if (no_clk == 1) {
+ /* Clock is lost. Set I2CR to remove POP noise */
+ pr_info("No clock detected. Resetting the I2CR to avoid pop on 72! \n");
+ err = (enum Tfa98xx_Error)tfa_dev_start(tfa, profile,
+ vstep);
+ if (err != Tfa98xx_Error_Ok) {
+ pr_err("Error loading i2c registers (tfa_dev_start), err=%d\n", err);
+ } else {
+ pr_info("Setting i2c registers after I2CR succesfull\n");
+ tfa_dev_set_state(tfa, TFA_STATE_UNMUTE, 0);
+ }
+
+ /* Remove sticky bit by reading it once */
+ tfa_get_noclk(tfa);
+
+ /* This is only for SAAM on the 72.
+ Since the NOCLK interrupt is only enabled for 72 this is the place
+ However: Not tested yet! But also does not harm normal flow!
+ */
+ if (strstr(tfaContProfileName(tfa->cnt, tfa->dev_idx, profile), ".saam")) {
+ pr_info("Powering down from a SAAM profile, workaround PLMA4766 used! \n");
+ TFA_SET_BF(tfa, PWDN, 1);
+ TFA_SET_BF(tfa, AMPE, 0);
+ TFA_SET_BF(tfa, SAMMODE, 0);
+ }
+ }
+
+ /* If clk is stable set polarity to check for LOW (no clock)*/
+ tfa_irq_set_pol(tfa, tfa9912_irq_stnoclk, (no_clk == 0));
+
+ /* clear interrupt */
+ tfa_irq_clear(tfa, tfa9912_irq_stnoclk);
+ }
+
+ /* return no_clk to know we called tfa_dev_start */
+ return no_clk;
+}
+
+void tfa_lp_mode_interrupt(struct tfa_device *tfa)
+{
+ const int irq_stclp0 = 36; /* FIXME: this 72 interrupt does not excist for 9912 */
+ int lp0, lp1;
+
+ if (tfa_irq_get(tfa, irq_stclp0)) {
+ lp0 = TFA_GET_BF(tfa, LP0);
+ if (lp0 > 0) {
+ pr_info("lowpower mode 0 detected\n");
+ } else {
+ pr_info("lowpower mode 0 not detected\n");
+ }
+
+ tfa_irq_set_pol(tfa, irq_stclp0, (lp0 == 0));
+
+ /* clear interrupt */
+ tfa_irq_clear(tfa, irq_stclp0);
+ }
+
+ if (tfa_irq_get(tfa, tfa9912_irq_stclpr)) {
+ lp1 = TFA_GET_BF(tfa, LP1);
+ if (lp1 > 0) {
+ pr_info("lowpower mode 1 detected\n");
+ } else {
+ pr_info("lowpower mode 1 not detected\n");
+ }
+
+ tfa_irq_set_pol(tfa, tfa9912_irq_stclpr, (lp1 == 0));
+
+ /* clear interrupt */
+ tfa_irq_clear(tfa, tfa9912_irq_stclpr);
+ }
+}
diff --git a/inc/tfa_dsp_fw.h b/sound/soc/codecs/tfa_dsp_fw.h
similarity index 95%
rename from inc/tfa_dsp_fw.h
rename to sound/soc/codecs/tfa_dsp_fw.h
index 1721e82..dd48949 100644
--- a/inc/tfa_dsp_fw.h
+++ b/sound/soc/codecs/tfa_dsp_fw.h
@@ -1,159 +1,159 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef TFA98XX_INTERNALS_H
-#define TFA98XX_INTERNALS_H
-
-#include "config.h"
-
-#include "tfa_service.h" //TODO cleanup for enum Tfa98xx_Status_ID
-
-/**
- * Return a text version of the firmware status ID code
- * @param status the given status ID code
- * @return the firmware status ID string
- */
-const char *tfadsp_fw_status_string(enum Tfa98xx_Status_ID status);
-int tfadsp_fw_start(struct tfa_device *tfa, int prof_idx, int vstep_idx);
-int tfadsp_fw_get_api_version(struct tfa_device *tfa, uint8_t *buffer);
-#define FW_MAXTAG 150
-int tfadsp_fw_get_tag(struct tfa_device *tfa, uint8_t *buffer);
-int tfadsp_fw_get_status_change(struct tfa_device *tfa, uint8_t *buffer);
-int tfadsp_fw_set_re25(struct tfa_device *tfa, int prim, int sec );
-int tfadsp_fw_get_re25(struct tfa_device *tfa, uint8_t *buffer);
-
-/*
- * the order matches the ACK bits order in TFA98XX_CF_STATUS
- */
-enum tfa_fw_event { /* not all available on each device */
- tfa_fw_i2c_cmd_ack,
- tfa_fw_reset_start,
- tfa_fw_short_on_mips,
- tfa_fw_soft_mute_ready,
- tfa_fw_volume_ready,
- tfa_fw_error_damage,
- tfa_fw_calibrate_done,
- tfa_fw_max
-};
-
-/* the following type mappings are compiler specific */
-#define subaddress_t unsigned char
-
-/* module Ids */
-#define MODULE_FRAMEWORK 0
-#define MODULE_SPEAKERBOOST 1
-#define MODULE_BIQUADFILTERBANK 2
-#define MODULE_TAPTRIGGER 5
-#define MODULE_SETRE 9
-
-/* RPC commands */
-/* SET */
-#define FW_PAR_ID_SET_MEMORY 0x03
-#define FW_PAR_ID_SET_SENSES_DELAY 0x04
-#define FW_PAR_ID_SETSENSESCAL 0x05
-#define FW_PAR_ID_SET_INPUT_SELECTOR 0x06
-#define FW_PAR_ID_SET_OUTPUT_SELECTOR 0x08
-#define FW_PAR_ID_SET_PROGRAM_CONFIG 0x09
-#define FW_PAR_ID_SET_GAINS 0x0A
-#define FW_PAR_ID_SET_MEMTRACK 0x0B
-#define FW_PAR_ID_SET_FWKUSECASE 0x11
-#define TFA1_FW_PAR_ID_SET_CURRENT_DELAY 0x03
-#define TFA1_FW_PAR_ID_SET_CURFRAC_DELAY 0x06
-/* GET */
-#define FW_PAR_ID_GET_MEMORY 0x83
-#define FW_PAR_ID_GLOBAL_GET_INFO 0x84
-#define FW_PAR_ID_GET_FEATURE_INFO 0x85
-#define FW_PAR_ID_GET_MEMTRACK 0x8B
-#define FW_PAR_ID_GET_TAG 0xFF
-#define FW_PAR_ID_GET_API_VERSION 0xFE
-#define FW_PAR_ID_GET_STATUS_CHANGE 0x8D
-
-/* Load a full model into SpeakerBoost. */
-/* SET */
-#define SB_PARAM_SET_ALGO_PARAMS 0x00
-#define SB_PARAM_SET_LAGW 0x01
-#define SB_PARAM_SET_ALGO_PARAMS_WITHOUT_RESET 0x02
-#define SB_PARAM_SET_RE25C 0x05
-#define SB_PARAM_SET_LSMODEL 0x06
-#define SB_PARAM_SET_MBDRC 0x07
-#define SB_PARAM_SET_MBDRC_WITHOUT_RESET 0x08
-#define SB_PARAM_SET_EXCURSION_FILTERS 0x0A
-#define SB_PARAM_SET_DRC 0x0F
-/* GET */
-#define SB_PARAM_GET_ALGO_PARAMS 0x80
-#define SB_PARAM_GET_LAGW 0x81
-#define SB_PARAM_GET_RE25C 0x85
-#define SB_PARAM_GET_LSMODEL 0x86
-#define SB_PARAM_GET_MBDRC 0x87
-#define SB_PARAM_GET_MBDRC_DYNAMICS 0x89
-#define SB_PARAM_GET_EXCURSION_FILTERS 0x8A
-#define SB_PARAM_GET_TAG 0xFF
-
-#define SB_PARAM_SET_EQ 0x0A /* 2 Equaliser Filters. */
-#define SB_PARAM_SET_PRESET 0x0D /* Load a preset */
-#define SB_PARAM_SET_CONFIG 0x0E /* Load a config */
-#define SB_PARAM_SET_AGCINS 0x10
-#define SB_PARAM_SET_CURRENT_DELAY 0x03
-#define SB_PARAM_GET_STATE 0xC0
-#define SB_PARAM_GET_XMODEL 0xC1 /* Gets current Excursion Model. */
-#define SB_PARAM_GET_XMODEL_COEFFS 0x8C /* Get coefficients for XModel */
-#define SB_PARAM_GET_EXCURSION_FILTERS 0x8A /* Get excursion filters */
-#define SB_PARAM_SET_EXCURSION_FILTERS 0x0A /* Set excursion filters */
-
-/* SET: TAPTRIGGER */
-#define TAP_PARAM_SET_ALGO_PARAMS 0x01
-#define TAP_PARAM_SET_DECIMATION_PARAMS 0x02
-
-/* GET: TAPTRIGGER*/
-#define TAP_PARAM_GET_ALGO_PARAMS 0x81
-#define TAP_PARAM_GET_TAP_RESULTS 0x84
-
-/* sets the speaker calibration impedance (@25 degrees celsius) */
-#define SB_PARAM_SET_RE0 0x89
-
-#define BFB_PAR_ID_SET_COEFS 0x00
-#define BFB_PAR_ID_GET_COEFS 0x80
-#define BFB_PAR_ID_GET_CONFIG 0x81
-
-/* for compatibility */
-#define FW_PARAM_GET_STATE FW_PAR_ID_GLOBAL_GET_INFO
-#define FW_PARAM_GET_FEATURE_BITS FW_PAR_ID_GET_FEATURE_BITS
-
-/* RPC Status results */
-#define STATUS_OK 0
-#define STATUS_INVALID_MODULE_ID 2
-#define STATUS_INVALID_PARAM_ID 3
-#define STATUS_INVALID_INFO_ID 4
-
-/* the maximum message length in the communication with the DSP */
-#define TFA2_MAX_PARAM_SIZE (507*3) /* TFA2 */
-#define TFA1_MAX_PARAM_SIZE (145*3) /* TFA1 */
-
-#define ROUND_DOWN(a,n) (((a)/(n))*(n))
-
-/* feature bits */
-#define FEATURE1_TCOEF 0x100 /* bit8 set means tCoefA expected */
-#define FEATURE1_DRC 0x200 /* bit9 NOT set means DRC expected */
-
-/* DSP firmware xmem defines */
-#define TFA1_FW_XMEM_CALIBRATION_DONE 231
-#define TFA2_FW_XMEM_CALIBRATION_DONE 516
-#define TFA1_FW_XMEM_COUNT_BOOT 0xa1
-#define TFA2_FW_XMEM_COUNT_BOOT 512
-#define TFA2_FW_XMEM_CMD_COUNT 520
-
-/* note that the following defs rely on the handle variable */
-#define TFA_FW_XMEM_CALIBRATION_DONE TFA_FAM_FW(tfa,XMEM_CALIBRATION_DONE)
-#define TFA_FW_XMEM_COUNT_BOOT TFA_FAM_FW(tfa,XMEM_COUNT_BOOT)
-#define TFA_FW_XMEM_CMD_COUNT TFA_FAM_FW(tfa,XMEM_CMD_COUNT)
-
-#define TFA2_FW_ReZ_SCALE 65536
-#define TFA1_FW_ReZ_SCALE 16384
-
-#endif /* TFA98XX_INTERNALS_H */
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef TFA98XX_INTERNALS_H
+#define TFA98XX_INTERNALS_H
+
+#include "config.h"
+
+#include "tfa_service.h" //TODO cleanup for enum Tfa98xx_Status_ID
+
+/**
+ * Return a text version of the firmware status ID code
+ * @param status the given status ID code
+ * @return the firmware status ID string
+ */
+const char *tfadsp_fw_status_string(enum Tfa98xx_Status_ID status);
+int tfadsp_fw_start(struct tfa_device *tfa, int prof_idx, int vstep_idx);
+int tfadsp_fw_get_api_version(struct tfa_device *tfa, uint8_t *buffer);
+#define FW_MAXTAG 150
+int tfadsp_fw_get_tag(struct tfa_device *tfa, uint8_t *buffer);
+int tfadsp_fw_get_status_change(struct tfa_device *tfa, uint8_t *buffer);
+int tfadsp_fw_set_re25(struct tfa_device *tfa, int prim, int sec);
+int tfadsp_fw_get_re25(struct tfa_device *tfa, uint8_t *buffer);
+
+/*
+ * the order matches the ACK bits order in TFA98XX_CF_STATUS
+ */
+enum tfa_fw_event { /* not all available on each device */
+ tfa_fw_i2c_cmd_ack,
+ tfa_fw_reset_start,
+ tfa_fw_short_on_mips,
+ tfa_fw_soft_mute_ready,
+ tfa_fw_volume_ready,
+ tfa_fw_error_damage,
+ tfa_fw_calibrate_done,
+ tfa_fw_max
+};
+
+/* the following type mappings are compiler specific */
+#define subaddress_t unsigned char
+
+/* module Ids */
+#define MODULE_FRAMEWORK 0
+#define MODULE_SPEAKERBOOST 1
+#define MODULE_BIQUADFILTERBANK 2
+#define MODULE_TAPTRIGGER 5
+#define MODULE_SETRE 9
+
+/* RPC commands */
+/* SET */
+#define FW_PAR_ID_SET_MEMORY 0x03
+#define FW_PAR_ID_SET_SENSES_DELAY 0x04
+#define FW_PAR_ID_SETSENSESCAL 0x05
+#define FW_PAR_ID_SET_INPUT_SELECTOR 0x06
+#define FW_PAR_ID_SET_OUTPUT_SELECTOR 0x08
+#define FW_PAR_ID_SET_PROGRAM_CONFIG 0x09
+#define FW_PAR_ID_SET_GAINS 0x0A
+#define FW_PAR_ID_SET_MEMTRACK 0x0B
+#define FW_PAR_ID_SET_FWKUSECASE 0x11
+#define TFA1_FW_PAR_ID_SET_CURRENT_DELAY 0x03
+#define TFA1_FW_PAR_ID_SET_CURFRAC_DELAY 0x06
+/* GET */
+#define FW_PAR_ID_GET_MEMORY 0x83
+#define FW_PAR_ID_GLOBAL_GET_INFO 0x84
+#define FW_PAR_ID_GET_FEATURE_INFO 0x85
+#define FW_PAR_ID_GET_MEMTRACK 0x8B
+#define FW_PAR_ID_GET_TAG 0xFF
+#define FW_PAR_ID_GET_API_VERSION 0xFE
+#define FW_PAR_ID_GET_STATUS_CHANGE 0x8D
+
+/* Load a full model into SpeakerBoost. */
+/* SET */
+#define SB_PARAM_SET_ALGO_PARAMS 0x00
+#define SB_PARAM_SET_LAGW 0x01
+#define SB_PARAM_SET_ALGO_PARAMS_WITHOUT_RESET 0x02
+#define SB_PARAM_SET_RE25C 0x05
+#define SB_PARAM_SET_LSMODEL 0x06
+#define SB_PARAM_SET_MBDRC 0x07
+#define SB_PARAM_SET_MBDRC_WITHOUT_RESET 0x08
+#define SB_PARAM_SET_EXCURSION_FILTERS 0x0A
+#define SB_PARAM_SET_DRC 0x0F
+/* GET */
+#define SB_PARAM_GET_ALGO_PARAMS 0x80
+#define SB_PARAM_GET_LAGW 0x81
+#define SB_PARAM_GET_RE25C 0x85
+#define SB_PARAM_GET_LSMODEL 0x86
+#define SB_PARAM_GET_MBDRC 0x87
+#define SB_PARAM_GET_MBDRC_DYNAMICS 0x89
+#define SB_PARAM_GET_EXCURSION_FILTERS 0x8A
+#define SB_PARAM_GET_TAG 0xFF
+
+#define SB_PARAM_SET_EQ 0x0A /* 2 Equaliser Filters. */
+#define SB_PARAM_SET_PRESET 0x0D /* Load a preset */
+#define SB_PARAM_SET_CONFIG 0x0E /* Load a config */
+#define SB_PARAM_SET_AGCINS 0x10
+#define SB_PARAM_SET_CURRENT_DELAY 0x03
+#define SB_PARAM_GET_STATE 0xC0
+#define SB_PARAM_GET_XMODEL 0xC1 /* Gets current Excursion Model. */
+#define SB_PARAM_GET_XMODEL_COEFFS 0x8C /* Get coefficients for XModel */
+#define SB_PARAM_GET_EXCURSION_FILTERS 0x8A /* Get excursion filters */
+#define SB_PARAM_SET_EXCURSION_FILTERS 0x0A /* Set excursion filters */
+
+/* SET: TAPTRIGGER */
+#define TAP_PARAM_SET_ALGO_PARAMS 0x01
+#define TAP_PARAM_SET_DECIMATION_PARAMS 0x02
+
+/* GET: TAPTRIGGER*/
+#define TAP_PARAM_GET_ALGO_PARAMS 0x81
+#define TAP_PARAM_GET_TAP_RESULTS 0x84
+
+/* sets the speaker calibration impedance (@25 degrees celsius) */
+#define SB_PARAM_SET_RE0 0x89
+
+#define BFB_PAR_ID_SET_COEFS 0x00
+#define BFB_PAR_ID_GET_COEFS 0x80
+#define BFB_PAR_ID_GET_CONFIG 0x81
+
+/* for compatibility */
+#define FW_PARAM_GET_STATE FW_PAR_ID_GLOBAL_GET_INFO
+#define FW_PARAM_GET_FEATURE_BITS FW_PAR_ID_GET_FEATURE_BITS
+
+/* RPC Status results */
+#define STATUS_OK 0
+#define STATUS_INVALID_MODULE_ID 2
+#define STATUS_INVALID_PARAM_ID 3
+#define STATUS_INVALID_INFO_ID 4
+
+/* the maximum message length in the communication with the DSP */
+#define TFA2_MAX_PARAM_SIZE (507*3) /* TFA2 */
+#define TFA1_MAX_PARAM_SIZE (145*3) /* TFA1 */
+
+#define ROUND_DOWN(a, n) (((a)/(n))*(n))
+
+/* feature bits */
+#define FEATURE1_TCOEF 0x100 /* bit8 set means tCoefA expected */
+#define FEATURE1_DRC 0x200 /* bit9 NOT set means DRC expected */
+
+/* DSP firmware xmem defines */
+#define TFA1_FW_XMEM_CALIBRATION_DONE 231
+#define TFA2_FW_XMEM_CALIBRATION_DONE 516
+#define TFA1_FW_XMEM_COUNT_BOOT 0xa1
+#define TFA2_FW_XMEM_COUNT_BOOT 512
+#define TFA2_FW_XMEM_CMD_COUNT 520
+
+/* note that the following defs rely on the handle variable */
+#define TFA_FW_XMEM_CALIBRATION_DONE TFA_FAM_FW(tfa, XMEM_CALIBRATION_DONE)
+#define TFA_FW_XMEM_COUNT_BOOT TFA_FAM_FW(tfa, XMEM_COUNT_BOOT)
+#define TFA_FW_XMEM_CMD_COUNT TFA_FAM_FW(tfa, XMEM_CMD_COUNT)
+
+#define TFA2_FW_ReZ_SCALE 65536
+#define TFA1_FW_ReZ_SCALE 16384
+
+#endif /* TFA98XX_INTERNALS_H */
diff --git a/inc/tfa_ext.h b/sound/soc/codecs/tfa_ext.h
similarity index 98%
rename from inc/tfa_ext.h
rename to sound/soc/codecs/tfa_ext.h
index 5d8a320..5ded093 100644
--- a/inc/tfa_ext.h
+++ b/sound/soc/codecs/tfa_ext.h
@@ -1,44 +1,43 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef TFA_SRC_TFA_EXT_H_
-#define TFA_SRC_TFA_EXT_H_
-
-#include "tfa_device.h"
-
-/*
- * events
- */
-/** Maximum value for enumerator */
-#define LVM_MAXENUM (0xffff)
-/**
-This enum type specifies the different events that may trigger a callback.
-*/
-enum tfadsp_event_en
-{
- TFADSP_CMD_ACK = 1, /**< Command handling is completed */
- TFADSP_SOFT_MUTE_READY = 8, /**< Muting completed */
- TFADSP_VOLUME_READY = 16, /**< Volume change completed */
- TFADSP_DAMAGED_SPEAKER = 32, /**< Damaged speaker was detected */
- TFADSP_CALIBRATE_DONE = 64, /**< Calibration is completed */
- TFADSP_SPARSESIG_DETECTED = 128, /**< Sparse signal detected */
- TFADSP_CMD_READY = 256, /**< Ready to receive commands */
- TFADSP_EXT_PWRUP = 0x8000,/**< DSP API has started, powered up */
- TFADSP_EXT_PWRDOWN = 0x8001,/**< DSP API stopped, power down */
- TFADSP_EVENT_DUMMY = LVM_MAXENUM
-} ;
-
-typedef int (*tfa_event_handler_t)(struct tfa_device *tfa, enum tfadsp_event_en tfadsp_event);
-typedef int (*dsp_send_message_t)(struct tfa_device *tfa, int length, const char *buf);
-typedef int (*dsp_read_message_t)(struct tfa_device *tfa, int length, char *buf);
-typedef int (*dsp_write_reg_t)(struct tfa_device *tfa, unsigned char subaddress, unsigned short value);
-
-int tfa_ext_register(dsp_write_reg_t tfa_write_reg, dsp_send_message_t tfa_send_message, dsp_read_message_t tfa_read_message, tfa_event_handler_t *tfa_event_handler);
-
-#endif /* TFA_SRC_TFA_EXT_H_ */
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef TFA_SRC_TFA_EXT_H_
+#define TFA_SRC_TFA_EXT_H_
+
+#include "tfa_device.h"
+
+/*
+ * events
+ */
+/** Maximum value for enumerator */
+#define LVM_MAXENUM (0xffff)
+/**
+This enum type specifies the different events that may trigger a callback.
+*/
+enum tfadsp_event_en {
+ TFADSP_CMD_ACK = 1, /**< Command handling is completed */
+ TFADSP_SOFT_MUTE_READY = 8, /**< Muting completed */
+ TFADSP_VOLUME_READY = 16, /**< Volume change completed */
+ TFADSP_DAMAGED_SPEAKER = 32, /**< Damaged speaker was detected */
+ TFADSP_CALIBRATE_DONE = 64, /**< Calibration is completed */
+ TFADSP_SPARSESIG_DETECTED = 128, /**< Sparse signal detected */
+ TFADSP_CMD_READY = 256, /**< Ready to receive commands */
+ TFADSP_EXT_PWRUP = 0x8000,/**< DSP API has started, powered up */
+ TFADSP_EXT_PWRDOWN = 0x8001,/**< DSP API stopped, power down */
+ TFADSP_EVENT_DUMMY = LVM_MAXENUM
+} ;
+
+typedef int (*tfa_event_handler_t)(struct tfa_device *tfa, enum tfadsp_event_en tfadsp_event);
+typedef int (*dsp_send_message_t)(struct tfa_device *tfa, int length, const char *buf);
+typedef int (*dsp_read_message_t)(struct tfa_device *tfa, int length, char *buf);
+typedef int (*dsp_write_reg_t)(struct tfa_device *tfa, unsigned char subaddress, unsigned short value);
+
+int tfa_ext_register(dsp_write_reg_t tfa_write_reg, dsp_send_message_t tfa_send_message, dsp_read_message_t tfa_read_message, tfa_event_handler_t *tfa_event_handler);
+
+#endif /* TFA_SRC_TFA_EXT_H_ */
diff --git a/src/tfa_init.c b/sound/soc/codecs/tfa_init.c
similarity index 94%
rename from src/tfa_init.c
rename to sound/soc/codecs/tfa_init.c
index 7e2f63d..e004b652 100644
--- a/src/tfa_init.c
+++ b/sound/soc/codecs/tfa_init.c
@@ -123,7 +123,7 @@ int tfa_set_swprofile(struct tfa_device *tfa, unsigned short new_value)
static int tfa_get_swprofile(struct tfa_device *tfa)
{
- return TFA_GET_BF(tfa, SWPROFIL) - 1;
+ return tfa->profile;
}
static int tfa_set_swvstep(struct tfa_device *tfa, unsigned short new_value)
@@ -155,7 +155,8 @@ static int tfa_get_swvstep(struct tfa_device *tfa)
return value - 1; /* invalid if 0 */
}
-static int tfa_get_mtpb(struct tfa_device *tfa) {
+static int tfa_get_mtpb(struct tfa_device *tfa)
+{
int value = 0;
@@ -322,8 +323,7 @@ static enum Tfa98xx_Error tfa9912_specific(struct tfa_device *tfa)
/* PLMA5505: MTP key open makes vulanable for MTP corruption */
tfa9912_faim_protect(tfa, 0);
- }
- else {
+ } else {
pr_info("Warning: Optimal settings not found for device with revid = 0x%x \n", tfa->rev);
}
@@ -351,21 +351,18 @@ static enum Tfa98xx_Error tfa9912_factory_trimmer(struct tfa_device *tfa)
TFA_SET_BF_VOLATILE(tfa, DCMCC, currentValue + delta);
if (tfa->verbose)
pr_debug("Max coil current is set to: %d \n", currentValue + delta);
- }
- else {
+ } else {
TFA_SET_BF_VOLATILE(tfa, DCMCC, 15);
if (tfa->verbose)
pr_debug("Max coil current is set to: 15 \n");
}
- }
- else if (result == 1) {
+ } else if (result == 1) {
/* Do not exceed the minimum value of 0 */
if (currentValue - delta > 0) {
TFA_SET_BF_VOLATILE(tfa, DCMCC, currentValue - delta);
if (tfa->verbose)
pr_debug("Max coil current is set to: %d \n", currentValue - delta);
- }
- else {
+ } else {
TFA_SET_BF_VOLATILE(tfa, DCMCC, 0);
if (tfa->verbose)
pr_debug("Max coil current is set to: 0 \n");
@@ -505,7 +502,7 @@ static enum Tfa98xx_Error tfa9912_set_osc_powerdown(struct tfa_device *tfa, int
*
* @param[in] tfa device description structure
* @param[in] state State of the low power mode1 detector control
-* 0 - low power mode1 detector control enabled,
+* 0 - low power mode1 detector control enabled,
* 1 - low power mode1 detector control disabled(low power mode is also disabled).
*
* @return Tfa98xx_Error_Ok when successfull, error otherwise.
@@ -818,7 +815,8 @@ static enum Tfa98xx_Error tfa9874_dsp_system_stable(struct tfa_device *tfa, int
return error;
}
-static int tfa9874_get_mtpb(struct tfa_device *tfa) {
+static int tfa9874_get_mtpb(struct tfa_device *tfa)
+{
int value;
value = tfa_get_bf(tfa, TFA9874_BF_MTPB);
@@ -960,7 +958,8 @@ static enum Tfa98xx_Error tfa9878_dsp_system_stable(struct tfa_device *tfa, int
return error;
}
-static int tfa9878_get_mtpb(struct tfa_device *tfa) {
+static int tfa9878_get_mtpb(struct tfa_device *tfa)
+{
int value;
value = tfa_get_bf(tfa, TFA9878_BF_MTPB);
@@ -1021,8 +1020,7 @@ static enum Tfa98xx_Error tfa9888_specific(struct tfa_device *tfa)
reg_write(tfa, 0x71, 0x1074); //POR=0x3074
reg_write(tfa, 0x83, 0x0014); //POR=0x0013
/* ----- generated code end ----- */
- }
- else {
+ } else {
pr_info("Warning: Optimal settings not found for device with revid = 0x%x \n", tfa->rev);
}
@@ -1114,21 +1112,18 @@ static enum Tfa98xx_Error tfa9888_factory_trimmer(struct tfa_device *tfa)
TFA_SET_BF_VOLATILE(tfa, DCMCC, currentValue + delta);
if (tfa->verbose)
pr_debug("Max coil current is set to: %d \n", currentValue + delta);
- }
- else {
+ } else {
TFA_SET_BF_VOLATILE(tfa, DCMCC, 15);
if (tfa->verbose)
pr_debug("Max coil current is set to: 15 \n");
}
- }
- else if (result == 1) {
+ } else if (result == 1) {
/* Do not exceed the minimum value of 0 */
if (currentValue - delta > 0) {
TFA_SET_BF_VOLATILE(tfa, DCMCC, currentValue - delta);
if (tfa->verbose)
pr_debug("Max coil current is set to: %d \n", currentValue - delta);
- }
- else {
+ } else {
TFA_SET_BF_VOLATILE(tfa, DCMCC, 0);
if (tfa->verbose)
pr_debug("Max coil current is set to: 0 \n");
@@ -1199,8 +1194,7 @@ static enum Tfa98xx_Error tfa9896_specific(struct tfa_device *tfa)
reg_write(tfa, 0x48, 0x0300); //POR=0x0308
reg_write(tfa, 0x88, 0x0100); //POR=0x0000
/* ----- generated code end ----- */
- }
- else if (tfa->rev == 0x2b96) {
+ } else if (tfa->rev == 0x2b96) {
/* ----- generated code start ----- v1*/
reg_write(tfa, 0x06, 0x000b); //POR=0x0001
reg_write(tfa, 0x07, 0x3e7f); //POR=0x1e7f
@@ -1208,8 +1202,7 @@ static enum Tfa98xx_Error tfa9896_specific(struct tfa_device *tfa)
reg_write(tfa, 0x48, 0x0300); //POR=0x0308
reg_write(tfa, 0x88, 0x0100); //POR=0x0000
/* ----- generated code end ----- */
- }
- else if (tfa->rev == 0x3b96) {
+ } else if (tfa->rev == 0x3b96) {
/* ----- generated code start ----- v1*/
reg_write(tfa, 0x06, 0x000b); //POR=0x0001
reg_write(tfa, 0x07, 0x3e7f); //POR=0x1e7f
@@ -1229,15 +1222,15 @@ static enum Tfa98xx_Error tfa9896_specific(struct tfa_device *tfa)
* the int24 values for the vsfw delay table
*/
static unsigned char tfa9896_vsfwdelay_table[] = {
- 0,0,2, /* Index 0 - Current/Volt Fractional Delay for 8KHz */
- 0,0,0, /* Index 1 - Current/Volt Fractional Delay for 11KHz */
- 0,0,0, /* Index 2 - Current/Volt Fractional Delay for 12KHz */
- 0,0,2, /* Index 3 - Current/Volt Fractional Delay for 16KHz */
- 0,0,2, /* Index 4 - Current/Volt Fractional Delay for 22KHz */
- 0,0,2, /* Index 5 - Current/Volt Fractional Delay for 24KHz */
- 0,0,2, /* Index 6 - Current/Volt Fractional Delay for 32KHz */
- 0,0,2, /* Index 7 - Current/Volt Fractional Delay for 44KHz */
- 0,0,3 /* Index 8 - Current/Volt Fractional Delay for 48KHz */
+ 0, 0, 2, /* Index 0 - Current/Volt Fractional Delay for 8KHz */
+ 0, 0, 0, /* Index 1 - Current/Volt Fractional Delay for 11KHz */
+ 0, 0, 0, /* Index 2 - Current/Volt Fractional Delay for 12KHz */
+ 0, 0, 2, /* Index 3 - Current/Volt Fractional Delay for 16KHz */
+ 0, 0, 2, /* Index 4 - Current/Volt Fractional Delay for 22KHz */
+ 0, 0, 2, /* Index 5 - Current/Volt Fractional Delay for 24KHz */
+ 0, 0, 2, /* Index 6 - Current/Volt Fractional Delay for 32KHz */
+ 0, 0, 2, /* Index 7 - Current/Volt Fractional Delay for 44KHz */
+ 0, 0, 3 /* Index 8 - Current/Volt Fractional Delay for 48KHz */
};
/*
@@ -1255,15 +1248,15 @@ static enum Tfa98xx_Error tfa9896_dsp_write_vsfwdelay_table(struct tfa_device *t
* For now applicable only for 8 and 48 kHz
*/
static unsigned char tfa9896_cvfracdelay_table[] = {
- 0,0,51, /* Index 0 - Current/Volt Fractional Delay for 8KHz */
- 0,0, 0, /* Index 1 - Current/Volt Fractional Delay for 11KHz */
- 0,0, 0, /* Index 2 - Current/Volt Fractional Delay for 12KHz */
- 0,0,38, /* Index 3 - Current/Volt Fractional Delay for 16KHz */
- 0,0,34, /* Index 4 - Current/Volt Fractional Delay for 22KHz */
- 0,0,33, /* Index 5 - Current/Volt Fractional Delay for 24KHz */
- 0,0,11, /* Index 6 - Current/Volt Fractional Delay for 32KHz */
- 0,0,2, /* Index 7 - Current/Volt Fractional Delay for 44KHz */
- 0,0,62 /* Index 8 - Current/Volt Fractional Delay for 48KHz */
+ 0, 0, 51, /* Index 0 - Current/Volt Fractional Delay for 8KHz */
+ 0, 0, 0, /* Index 1 - Current/Volt Fractional Delay for 11KHz */
+ 0, 0, 0, /* Index 2 - Current/Volt Fractional Delay for 12KHz */
+ 0, 0, 38, /* Index 3 - Current/Volt Fractional Delay for 16KHz */
+ 0, 0, 34, /* Index 4 - Current/Volt Fractional Delay for 22KHz */
+ 0, 0, 33, /* Index 5 - Current/Volt Fractional Delay for 24KHz */
+ 0, 0, 11, /* Index 6 - Current/Volt Fractional Delay for 32KHz */
+ 0, 0, 2, /* Index 7 - Current/Volt Fractional Delay for 44KHz */
+ 0, 0, 62 /* Index 8 - Current/Volt Fractional Delay for 48KHz */
};
static enum Tfa98xx_Error tfa9896_dsp_write_cvfracdelay_table(struct tfa_device *tfa)
@@ -1326,15 +1319,15 @@ static enum Tfa98xx_Error tfa9897_specific(struct tfa_device *tfa)
* the int24 values for the vsfw delay table
*/
static unsigned char tfa9897_vsfwdelay_table[] = {
- 0,0,2, /* Index 0 - Current/Volt Fractional Delay for 8KHz */
- 0,0,0, /* Index 1 - Current/Volt Fractional Delay for 11KHz */
- 0,0,0, /* Index 2 - Current/Volt Fractional Delay for 12KHz */
- 0,0,2, /* Index 3 - Current/Volt Fractional Delay for 16KHz */
- 0,0,2, /* Index 4 - Current/Volt Fractional Delay for 22KHz */
- 0,0,2, /* Index 5 - Current/Volt Fractional Delay for 24KHz */
- 0,0,2, /* Index 6 - Current/Volt Fractional Delay for 32KHz */
- 0,0,2, /* Index 7 - Current/Volt Fractional Delay for 44KHz */
- 0,0,3 /* Index 8 - Current/Volt Fractional Delay for 48KHz */
+ 0, 0, 2, /* Index 0 - Current/Volt Fractional Delay for 8KHz */
+ 0, 0, 0, /* Index 1 - Current/Volt Fractional Delay for 11KHz */
+ 0, 0, 0, /* Index 2 - Current/Volt Fractional Delay for 12KHz */
+ 0, 0, 2, /* Index 3 - Current/Volt Fractional Delay for 16KHz */
+ 0, 0, 2, /* Index 4 - Current/Volt Fractional Delay for 22KHz */
+ 0, 0, 2, /* Index 5 - Current/Volt Fractional Delay for 24KHz */
+ 0, 0, 2, /* Index 6 - Current/Volt Fractional Delay for 32KHz */
+ 0, 0, 2, /* Index 7 - Current/Volt Fractional Delay for 44KHz */
+ 0, 0, 3 /* Index 8 - Current/Volt Fractional Delay for 48KHz */
};
/*
@@ -1352,15 +1345,15 @@ static enum Tfa98xx_Error tfa9897_dsp_write_vsfwdelay_table(struct tfa_device *t
* For now applicable only for 8 and 48 kHz
*/
static unsigned char tfa9897_cvfracdelay_table[] = {
- 0,0,51, /* Index 0 - Current/Volt Fractional Delay for 8KHz */
- 0,0, 0, /* Index 1 - Current/Volt Fractional Delay for 11KHz */
- 0,0, 0, /* Index 2 - Current/Volt Fractional Delay for 12KHz */
- 0,0,38, /* Index 3 - Current/Volt Fractional Delay for 16KHz */
- 0,0,34, /* Index 4 - Current/Volt Fractional Delay for 22KHz */
- 0,0,33, /* Index 5 - Current/Volt Fractional Delay for 24KHz */
- 0,0,11, /* Index 6 - Current/Volt Fractional Delay for 32KHz */
- 0,0,2, /* Index 7 - Current/Volt Fractional Delay for 44KHz */
- 0,0,62 /* Index 8 - Current/Volt Fractional Delay for 48KHz */
+ 0, 0, 51, /* Index 0 - Current/Volt Fractional Delay for 8KHz */
+ 0, 0, 0, /* Index 1 - Current/Volt Fractional Delay for 11KHz */
+ 0, 0, 0, /* Index 2 - Current/Volt Fractional Delay for 12KHz */
+ 0, 0, 38, /* Index 3 - Current/Volt Fractional Delay for 16KHz */
+ 0, 0, 34, /* Index 4 - Current/Volt Fractional Delay for 22KHz */
+ 0, 0, 33, /* Index 5 - Current/Volt Fractional Delay for 24KHz */
+ 0, 0, 11, /* Index 6 - Current/Volt Fractional Delay for 32KHz */
+ 0, 0, 2, /* Index 7 - Current/Volt Fractional Delay for 44KHz */
+ 0, 0, 62 /* Index 8 - Current/Volt Fractional Delay for 48KHz */
};
static enum Tfa98xx_Error tfa9897_dsp_write_cvfracdelay_table(struct tfa_device *tfa)
@@ -1497,7 +1490,8 @@ static enum Tfa98xx_Error tfa9890_clockgating(struct tfa_device *tfa, int on)
/* for TFA9890 temporarily disable clock gating when dsp reset is used */
error = reg_read(tfa, TFA98XX_CURRENTSENSE4, &value);
- if (error) return error;
+ if (error)
+ return error;
if (Tfa98xx_Error_Ok == error) {
if (on) /* clock gating on - clear the bit */
@@ -1711,29 +1705,27 @@ static enum Tfa98xx_Error tfa9894_specific(struct tfa_device *tfa)
reg_write(tfa, 0x81, 0x5715); //POR=0x561a
reg_write(tfa, 0x82, 0x0104); //POR=0x0044
/* ----- generated code end ----- */
- }
- else if (tfa->rev == 0x1a94) {
+ } else if (tfa->rev == 0x1a94) {
/* V17 */
- /* ----- generated code start ----- */
- reg_write(tfa, 0x00, 0xa245); //POR=0x8245
+ /* ----- generated code start ----- */
+ reg_write(tfa, 0x00, 0xa245); //POR=0x8245
reg_write(tfa, 0x01, 0x15da); //POR=0x11ca
- reg_write(tfa, 0x02, 0x5288); //POR=0x55c8
- reg_write(tfa, 0x52, 0xbe17); //POR=0xb617
+ reg_write(tfa, 0x02, 0x5288); //POR=0x55c8
+ reg_write(tfa, 0x52, 0xbe17); //POR=0xb617
reg_write(tfa, 0x53, 0x0dbe); //POR=0x0d9e
- reg_write(tfa, 0x56, 0x05c3); //POR=0x07c3
- reg_write(tfa, 0x57, 0x0344); //POR=0x0366
- reg_write(tfa, 0x61, 0x0032); //POR=0x0073
- reg_write(tfa, 0x71, 0x00cf); //POR=0x018d
- reg_write(tfa, 0x72, 0x34a9); //POR=0x44e8
- reg_write(tfa, 0x73, 0x38c8); //POR=0x3806
- reg_write(tfa, 0x76, 0x0067); //POR=0x0065
- reg_write(tfa, 0x80, 0x0000); //POR=0x0003
- reg_write(tfa, 0x81, 0x5799); //POR=0x561a
+ reg_write(tfa, 0x56, 0x05c3); //POR=0x07c3
+ reg_write(tfa, 0x57, 0x0344); //POR=0x0366
+ reg_write(tfa, 0x61, 0x0032); //POR=0x0073
+ reg_write(tfa, 0x71, 0x00cf); //POR=0x018d
+ reg_write(tfa, 0x72, 0x34a9); //POR=0x44e8
+ reg_write(tfa, 0x73, 0x38c8); //POR=0x3806
+ reg_write(tfa, 0x76, 0x0067); //POR=0x0065
+ reg_write(tfa, 0x80, 0x0000); //POR=0x0003
+ reg_write(tfa, 0x81, 0x5799); //POR=0x561a
reg_write(tfa, 0x82, 0x0104); //POR=0x0044
/* ----- generated code end ----- */
- }
- else if (tfa->rev == 0x2a94 || tfa->rev == 0x3a94) {
+ } else if (tfa->rev == 0x2a94 || tfa->rev == 0x3a94) {
/* ----- generated code start ----- */
/* ----- version 25.00 ----- */
reg_write(tfa, 0x01, 0x15da); //POR=0x11ca
diff --git a/src/tfa_internal.h b/sound/soc/codecs/tfa_internal.h
similarity index 73%
rename from src/tfa_internal.h
rename to sound/soc/codecs/tfa_internal.h
index bdea9ea..fe6407e 100644
--- a/src/tfa_internal.h
+++ b/sound/soc/codecs/tfa_internal.h
@@ -1,32 +1,34 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-/*
- internal functions for TFA layer (not shared with SRV and HAL layer!)
-*/
-
-#ifndef __TFA_INTERNAL_H__
-#define __TFA_INTERNAL_H__
-
-#include "tfa_dsp_fw.h"
-#include "tfa_ext.h"
-
-#if __GNUC__ >= 4
- #define TFA_INTERNAL __attribute__ ((visibility ("hidden")))
-#else
- #define TFA_INTERNAL
-#endif
-
-#define TFA98XX_GENERIC_SLAVE_ADDRESS 0x1C
-
-TFA_INTERNAL enum Tfa98xx_Error tfa98xx_check_rpc_status(struct tfa_device *tfa, int *pRpcStatus);
-TFA_INTERNAL enum Tfa98xx_Error tfa98xx_wait_result(struct tfa_device *tfa, int waitRetryCount);
-
-#endif /* __TFA_INTERNAL_H__ */
-
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/*
+ * internal functions for TFA layer (not shared with SRV and HAL layer!)
+ */
+
+#ifndef __TFA_INTERNAL_H__
+#define __TFA_INTERNAL_H__
+
+#include "tfa_dsp_fw.h"
+#include "tfa_ext.h"
+
+#if __GNUC__ >= 4
+ #define TFA_INTERNAL __attribute__((visibility ("hidden")))
+#else
+ #define TFA_INTERNAL
+#endif
+
+#define TFA98XX_GENERIC_SLAVE_ADDRESS 0x1C
+
+TFA_INTERNAL enum Tfa98xx_Error tfa98xx_check_rpc_status(struct tfa_device *tfa,
+ int *pRpcStatus);
+TFA_INTERNAL enum Tfa98xx_Error tfa98xx_wait_result(struct tfa_device *tfa,
+ int waitRetryCount);
+
+#endif /* __TFA_INTERNAL_H__ */
+
diff --git a/inc/tfa_service.h b/sound/soc/codecs/tfa_service.h
similarity index 90%
rename from inc/tfa_service.h
rename to sound/soc/codecs/tfa_service.h
index 3fad561..240deb9 100644
--- a/inc/tfa_service.h
+++ b/sound/soc/codecs/tfa_service.h
@@ -1,1012 +1,1024 @@
-/*
- * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef TFA_SERVICE_H
-#define TFA_SERVICE_H
-
-#ifdef __KERNEL__
-#include <linux/types.h>
-#else
-#include <stdint.h>
-#endif
-#ifdef __cplusplus
-extern "C" {
-#include "NXP_I2C.h"
-#endif
-
-/* Linux kernel module defines TFA98XX_GIT_VERSIONS in the linux_driver/Makefile */
-#if !defined(TFA98XX_GIT_VERSIONS)
-#include "versions.h"
-#endif
-#ifdef TFA98XX_GIT_VERSIONS
- #define TFA98XX_API_REV_STR "v6.6.3"/*TFA98XX_GIT_VERSIONS*/
-#else
- #define TFA98XX_API_REV_STR "v6.6.3"
-#endif
-
-#include "tfa_device.h"
-
-/*
- * data previously defined in Tfa9888_dsp.h
- */
-#define MEMTRACK_MAX_WORDS 150
-#define LSMODEL_MAX_WORDS 150
-#define TFA98XX_MAXTAG (150)
-#define FW_VAR_API_VERSION (521)
-
-/* Indexes and scaling factors of GetLSmodel */
-#define tfa9888_fs_IDX 128
-#define tfa9888_leakageFactor_IDX 130
-#define tfa9888_ReCorrection_IDX 131
-#define tfa9888_Bl_IDX 132
-#define ReZ_IDX 147
-
-#define tfa9872_leakageFactor_IDX 128
-#define tfa9872_ReCorrection_IDX 129
-#define tfa9872_Bl_IDX 130
-
-#define fs_SCALE (double)1
-#define leakageFactor_SCALE (double)8388608
-#define ReCorrection_SCALE (double)8388608
-#define Bl_SCALE (double)2097152
-#define tCoef_SCALE (double)8388608
-
-/* ---------------------------- Max1 ---------------------------- */
-/* Headroom applied to the main input signal */
-#define SPKRBST_HEADROOM 7
-/* Exponent used for AGC Gain related variables */
-#define SPKRBST_AGCGAIN_EXP SPKRBST_HEADROOM
-#define SPKRBST_TEMPERATURE_EXP 9
-/* Exponent used for Gain Corection related variables */
-#define SPKRBST_LIMGAIN_EXP 4
-#define SPKRBST_TIMECTE_EXP 1
-#define DSP_MAX_GAIN_EXP 7
-/* -------------------------------------------------------------- */
-
-/* speaker related parameters */
-#define TFA2_SPEAKERPARAMETER_LENGTH (3*151) /* MAX2=450 */
-#define TFA1_SPEAKERPARAMETER_LENGTH (3*141) /* MAX1=423 */
-
-/* vstep related parameters */
-#define TFA2_ALGOPARAMETER_LENGTH (3*304) /* N1B = (304) 305 is including the cmd-id */
-#define TFA72_ALGOPARAMETER_LENGTH_MONO (3*183)
-#define TFA72_ALGOPARAMETER_LENGTH_STEREO (3*356)
-#define TFA2_MBDRCPARAMETER_LENGTH (3*152) /* 154 is including the cmd-id */
-#define TFA72_MBDRCPARAMETER_LENGTH (3*98)
-#define TFA1_PRESET_LENGTH 87
-#define TFA1_DRC_LENGTH 381 /* 127 words */
-#define TFA2_FILTERCOEFSPARAMETER_LENGTH (3*168) /* 170 is including the cmd-id */
-#define TFA72_FILTERCOEFSPARAMETER_LENGTH (3*156)
-
-/* Maximum number of retries for DSP result
- * Keep this value low!
- * If certain calls require longer wait conditions, the
- * application should poll, not the API
- * The total wait time depends on device settings. Those
- * are application specific.
- */
-#define TFA98XX_WAITRESULT_NTRIES 40
-#define TFA98XX_WAITRESULT_NTRIES_LONG 2000
-
-/* following lengths are in bytes */
-#define TFA98XX_PRESET_LENGTH 87
-#define TFA98XX_CONFIG_LENGTH 201
-#define TFA98XX_DRC_LENGTH 381 /* 127 words */
-
-typedef unsigned char Tfa98xx_Config_t[TFA98XX_CONFIG_LENGTH];
-typedef unsigned char Tfa98xx_Preset_t[TFA98XX_PRESET_LENGTH];
-typedef unsigned char Tfa98xx_DrcParameters_t[TFA98XX_DRC_LENGTH];
-
-/* Type containing all the possible errors that can occur
- *
- */
-enum Tfa98xx_Error {
- Tfa98xx_Error_Ok = 0,
- Tfa98xx_Error_Device, /* 1. Currently only used to keep in sync with tfa_error */
- Tfa98xx_Error_Bad_Parameter, /* 2. */
- Tfa98xx_Error_Fail, /* 3. generic failure, avoid mislead message */
- Tfa98xx_Error_NoClock, /* 4. no clock detected */
- Tfa98xx_Error_StateTimedOut, /* 5. */
- Tfa98xx_Error_DSP_not_running, /* 6. communication with the DSP failed */
- Tfa98xx_Error_AmpOn, /* 7. amp is still running */
- Tfa98xx_Error_NotOpen, /* 8. the given handle is not open */
- Tfa98xx_Error_InUse, /* 9. too many handles */
- Tfa98xx_Error_Buffer_too_small, /* 10. if a buffer is too small */
- /* the expected response did not occur within the expected time */
- Tfa98xx_Error_RpcBase = 100,
- Tfa98xx_Error_RpcBusy = 101,
- Tfa98xx_Error_RpcModId = 102,
- Tfa98xx_Error_RpcParamId = 103,
- Tfa98xx_Error_RpcInvalidCC = 104,
- Tfa98xx_Error_RpcInvalidSeq = 105,
- Tfa98xx_Error_RpcInvalidParam = 106,
- Tfa98xx_Error_RpcBufferOverflow = 107,
- Tfa98xx_Error_RpcCalibBusy = 108,
- Tfa98xx_Error_RpcCalibFailed = 109,
- Tfa98xx_Error_Not_Implemented,
- Tfa98xx_Error_Not_Supported,
- Tfa98xx_Error_I2C_Fatal, /* Fatal I2C error occurred */
- /* Nonfatal I2C error, and retry count reached */
- Tfa98xx_Error_I2C_NonFatal,
- Tfa98xx_Error_Other = 1000
-};
-
-/*
- * Type containing all the possible msg returns DSP can give
- * //TODO move to tfa_dsp_fw.h
- */
-enum Tfa98xx_Status_ID {
- Tfa98xx_DSP_Not_Running = -1, /* No response from DSP */
- Tfa98xx_I2C_Req_Done = 0, /* Request executed correctly and result, if any, is available for download */
- Tfa98xx_I2C_Req_Busy = 1, /* Request is being processed, just wait for result */
- Tfa98xx_I2C_Req_Invalid_M_ID = 2, /* Provided M-ID does not fit in valid rang [0..2] */
- Tfa98xx_I2C_Req_Invalid_P_ID = 3, /* Provided P-ID isn�t valid in the given M-ID context */
- Tfa98xx_I2C_Req_Invalid_CC = 4, /* Invalid channel configuration bits (SC|DS|DP|DC) combination */
- Tfa98xx_I2C_Req_Invalid_Seq = 5, /* Invalid sequence of commands, in case the DSP expects some commands in a specific order */
- Tfa98xx_I2C_Req_Invalid_Param = 6, /* Generic error */
- Tfa98xx_I2C_Req_Buffer_Overflow = 7, /* I2C buffer has overflowed: host has sent too many parameters, memory integrity is not guaranteed */
- Tfa98xx_I2C_Req_Calib_Busy = 8, /* Calibration not finished */
- Tfa98xx_I2C_Req_Calib_Failed = 9 /* Calibration failed */
-};
-
-/*
- * speaker as microphone
- */
-enum Tfa98xx_saam {
- Tfa98xx_saam_none, /*< SAAM feature not available */
- Tfa98xx_saam /*< SAAM feature available */
-};
-
-/*
- * config file subtypes
- */
-enum Tfa98xx_config_type {
- Tfa98xx_config_generic,
- Tfa98xx_config_sub1,
- Tfa98xx_config_sub2,
- Tfa98xx_config_sub3,
-};
-
-enum Tfa98xx_AmpInputSel {
- Tfa98xx_AmpInputSel_I2SLeft,
- Tfa98xx_AmpInputSel_I2SRight,
- Tfa98xx_AmpInputSel_DSP
-};
-
-enum Tfa98xx_OutputSel {
- Tfa98xx_I2SOutputSel_CurrentSense,
- Tfa98xx_I2SOutputSel_DSP_Gain,
- Tfa98xx_I2SOutputSel_DSP_AEC,
- Tfa98xx_I2SOutputSel_Amp,
- Tfa98xx_I2SOutputSel_DataI3R,
- Tfa98xx_I2SOutputSel_DataI3L,
- Tfa98xx_I2SOutputSel_DcdcFFwdCur,
-};
-
-enum Tfa98xx_StereoGainSel {
- Tfa98xx_StereoGainSel_Left,
- Tfa98xx_StereoGainSel_Right
-};
-
-#define TFA98XX_MAXPATCH_LENGTH (3*1024)
-
-/* the number of biquads supported */
-#define TFA98XX_BIQUAD_NUM 10
-
-enum Tfa98xx_Channel {
- Tfa98xx_Channel_L,
- Tfa98xx_Channel_R,
- Tfa98xx_Channel_L_R,
- Tfa98xx_Channel_Stereo
-};
-
-enum Tfa98xx_Mode {
- Tfa98xx_Mode_Normal = 0,
- Tfa98xx_Mode_RCV
-};
-
-enum Tfa98xx_Mute {
- Tfa98xx_Mute_Off,
- Tfa98xx_Mute_Digital,
- Tfa98xx_Mute_Amplifier
-};
-
-enum Tfa98xx_SpeakerBoostStatusFlags {
- Tfa98xx_SpeakerBoost_Activity = 0, /* Input signal activity. */
- Tfa98xx_SpeakerBoost_S_Ctrl, /* S Control triggers the limiter */
- Tfa98xx_SpeakerBoost_Muted, /* 1 when signal is muted */
- Tfa98xx_SpeakerBoost_X_Ctrl, /* X Control triggers the limiter */
- Tfa98xx_SpeakerBoost_T_Ctrl, /* T Control triggers the limiter */
- Tfa98xx_SpeakerBoost_NewModel, /* New model is available */
- Tfa98xx_SpeakerBoost_VolumeRdy, /* 0:stable vol, 1:still smoothing */
- Tfa98xx_SpeakerBoost_Damaged, /* Speaker Damage detected */
- Tfa98xx_SpeakerBoost_SignalClipping /* input clipping detected */
-};
-
-struct Tfa98xx_DrcStateInfo {
- float GRhighDrc1[2];
- float GRhighDrc2[2];
- float GRmidDrc1[2];
- float GRmidDrc2[2];
- float GRlowDrc1[2];
- float GRlowDrc2[2];
- float GRpostDrc1[2];
- float GRpostDrc2[2];
- float GRblDrc[2];
-};
-struct Tfa98xx_StateInfo {
- /* SpeakerBoost State */
- float agcGain; /* Current AGC Gain value */
- float limGain; /* Current Limiter Gain value */
- float sMax; /* Current Clip/Lim threshold */
- int T; /* Current Speaker Temperature value */
- int statusFlag; /* Masked bit word */
- float X1; /* estimated excursion caused by Spkrboost gain ctrl */
- float X2; /* estimated excursion caused by manual gain setting */
- float Re; /* Loudspeaker blocked resistance */
- /* Framework state */
- /* increments each time a MIPS problem is detected on the DSP */
- int shortOnMips;
- struct Tfa98xx_DrcStateInfo drcState; /* DRC state, when enabled */
-};
-
-typedef struct nxpTfaMsg {
- uint8_t msg_size;
- unsigned char cmdId[3];
- int data[9];
-} nxpTfaMsg_t;
-
-typedef struct nxp_vstep_msg {
- int fw_version;
- uint8_t no_of_vsteps;
- uint16_t reg_no;
- uint8_t *msg_reg;
- uint8_t msg_no;
- uint32_t algo_param_length;
- uint8_t *msg_algo_param;
- uint32_t filter_coef_length;
- uint8_t *msg_filter_coef;
- uint32_t mbdrc_length;
- uint8_t *msg_mbdrc;
-} nxp_vstep_msg_t;
-
-typedef struct nxpTfaGroup {
- uint8_t msg_size;
- uint8_t profileId[64];
-} nxpTfaGroup_t;
-
-
-struct nxpTfa98xx_Memtrack_data {
- int length;
- float mValues[MEMTRACK_MAX_WORDS];
- int mAdresses[MEMTRACK_MAX_WORDS];
- int trackers[MEMTRACK_MAX_WORDS];
- int scalingFactor[MEMTRACK_MAX_WORDS];
-};
-
-/* possible memory values for DMEM in CF_CONTROLs */
-enum Tfa98xx_DMEM {
- Tfa98xx_DMEM_ERR = -1,
- Tfa98xx_DMEM_PMEM = 0,
- Tfa98xx_DMEM_XMEM = 1,
- Tfa98xx_DMEM_YMEM = 2,
- Tfa98xx_DMEM_IOMEM = 3,
-};
-
-/**
- * lookup the device type and return the family type
- */
-int tfa98xx_dev2family(int dev_type);
-
-/**
- * register definition structure
- */
-struct regdef {
- unsigned char offset; /**< subaddress offset */
- unsigned short pwronDefault; /**< register contents after poweron */
- unsigned short pwronTestmask; /**< mask of bits not test */
- char *name; /**< short register name */
-};
-
-enum Tfa98xx_DMEM tfa98xx_filter_mem(struct tfa_device *tfa, int filter_index, unsigned short *address, int channel);
-
-/**
- * Load the default HW settings in the device
- * @param tfa the device struct pointer
- */
-enum Tfa98xx_Error tfa98xx_init(struct tfa_device *tfa);
-
-/**
- * If needed, this function can be used to get a text version of the status ID code
- * @param status the given status ID code
- * @return the I2C status ID string
- */
-const char *tfa98xx_get_i2c_status_id_string(int status);
-
-/* control the powerdown bit
- * @param tfa the device struct pointer
- * @param powerdown must be 1 or 0
- */
-enum Tfa98xx_Error tfa98xx_powerdown(struct tfa_device *tfa, int powerdown);
-
-/* indicates on which channel of DATAI2 the gain from the IC is set
- * @param tfa the device struct pointer
- * @param gain_sel, see Tfa98xx_StereoGainSel_t
- */
-enum Tfa98xx_Error tfa98xx_select_stereo_gain_channel(struct tfa_device *tfa,
- enum Tfa98xx_StereoGainSel gain_sel);
-
-/**
- * set the mtp with user controllable values
- * @param tfa the device struct pointer
- * @param value to be written
- * @param mask to be applied toi the bits affected
- */
-enum Tfa98xx_Error tfa98xx_set_mtp(struct tfa_device *tfa, uint16_t value, uint16_t mask);
-enum Tfa98xx_Error tfa98xx_get_mtp(struct tfa_device *tfa, uint16_t *value);
-
-/**
- * lock or unlock KEY2
- * lock = 1 will lock
- * lock = 0 will unlock
- * note that on return all the hidden key will be off
- */
-void tfa98xx_key2(struct tfa_device *tfa, int lock);
-
-int tfa_calibrate(struct tfa_device *tfa) ;
-void tfa98xx_set_exttemp(struct tfa_device *tfa, short ext_temp);
-short tfa98xx_get_exttemp(struct tfa_device *tfa);
-
-/* control the volume of the DSP
- * @param vol volume in bit field. It must be between 0 and 255
- */
-enum Tfa98xx_Error tfa98xx_set_volume_level(struct tfa_device *tfa,
- unsigned short vol);
-
-/* set the input channel to use
- * @param channel see Tfa98xx_Channel_t enumeration
- */
-enum Tfa98xx_Error tfa98xx_select_channel(struct tfa_device *tfa,
- enum Tfa98xx_Channel channel);
-
-/* set the mode for normal or receiver mode
- * @param mode see Tfa98xx_Mode enumeration
- */
-enum Tfa98xx_Error tfa98xx_select_mode(struct tfa_device *tfa, enum Tfa98xx_Mode mode );
-
-/* mute/unmute the audio
- * @param mute see Tfa98xx_Mute_t enumeration
- */
-enum Tfa98xx_Error tfa98xx_set_mute(struct tfa_device *tfa,
- enum Tfa98xx_Mute mute);
-
-/*
- * tfa_supported_speakers - required for SmartStudio initialization
- * returns the number of the supported speaker count
- */
-enum Tfa98xx_Error tfa_supported_speakers(struct tfa_device *tfa, int* spkr_count);
-
-/**
-* Return the tfa revision
-*/
-void tfa98xx_rev(int *major, int *minor, int *revision);
-
-/*
- * Return the feature bits from MTP and cnt file for comparison
- */
-enum Tfa98xx_Error
-tfa98xx_compare_features(struct tfa_device *tfa, int features_from_MTP[3], int features_from_cnt[3]);
-
-/*
- * return feature bits
- */
-enum Tfa98xx_Error
-tfa98xx_dsp_get_sw_feature_bits(struct tfa_device *tfa, int features[2]);
-enum Tfa98xx_Error
-tfa98xx_dsp_get_hw_feature_bits(struct tfa_device *tfa, int *features);
-
-/*
- * tfa98xx_supported_saam
- * returns the speaker as microphone feature
- * @param saam enum pointer
- * @return error code
- */
-enum Tfa98xx_Error tfa98xx_supported_saam(struct tfa_device *tfa, enum Tfa98xx_saam *saam);
-
-/* load the tables to the DSP
- * called after patch load is done
- * @return error code
- */
-enum Tfa98xx_Error tfa98xx_dsp_write_tables(struct tfa_device *tfa, int sample_rate);
-
-
-/* set or clear DSP reset signal
- * @param new state
- * @return error code
- */
-enum Tfa98xx_Error tfa98xx_dsp_reset(struct tfa_device *tfa, int state);
-
-/* check the state of the DSP subsystem
- * return ready = 1 when clocks are stable to allow safe DSP subsystem access
- * @param tfa the device struct pointer
- * @param ready pointer to state flag, non-zero if clocks are not stable
- * @return error code
- */
-enum Tfa98xx_Error tfa98xx_dsp_system_stable(struct tfa_device *tfa, int *ready);
-
-enum Tfa98xx_Error tfa98xx_auto_copy_mtp_to_iic(struct tfa_device *tfa);
-
-/**
- * check the state of the DSP coolflux
- * @param tfa the device struct pointer
- * @return the value of CFE
- */
-int tfa_cf_enabled(struct tfa_device *tfa);
-
-/* The following functions can only be called when the DSP is running
- * - I2S clock must be active,
- * - IC must be in operating mode
- */
-
-/**
- * patch the ROM code of the DSP
- * @param tfa the device struct pointer
- * @param patchLength the number of bytes of patchBytes
- * @param patchBytes pointer to the bytes to patch
- */
-enum Tfa98xx_Error tfa_dsp_patch(struct tfa_device *tfa,
- int patchLength,
- const unsigned char *patchBytes);
-
-/**
- * load explicitly the speaker parameters in case of free speaker,
- * or when using a saved speaker model
- */
-enum Tfa98xx_Error tfa98xx_dsp_write_speaker_parameters(
- struct tfa_device *tfa,
- int length,
- const unsigned char *pSpeakerBytes);
-
-/**
- * read the speaker parameters as used by the SpeakerBoost processing
- */
-enum Tfa98xx_Error tfa98xx_dsp_read_speaker_parameters(
- struct tfa_device *tfa,
- int length,
- unsigned char *pSpeakerBytes);
-
-/**
- * read the current status of the DSP, typically used for development,
- * not essential to be used in a product
- */
-enum Tfa98xx_Error tfa98xx_dsp_get_state_info(
- struct tfa_device *tfa,
- unsigned char bytes[],
- unsigned int *statesize);
-
-/**
- * Check whether the DSP supports DRC
- * pbSupportDrc=1 when DSP supports DRC,
- * pbSupportDrc=0 when DSP doesn't support it
- */
-enum Tfa98xx_Error tfa98xx_dsp_support_drc(struct tfa_device *tfa,
- int *pbSupportDrc);
-
-enum Tfa98xx_Error
-tfa98xx_dsp_support_framework(struct tfa_device *tfa, int *pbSupportFramework);
-
-/**
- * read the speaker excursion model as used by SpeakerBoost processing
- */
-enum Tfa98xx_Error tfa98xx_dsp_read_excursion_model(
- struct tfa_device *tfa,
- int length,
- unsigned char *pSpeakerBytes);
-
-/**
- * load all the parameters for a preset from a file
- */
-enum Tfa98xx_Error tfa98xx_dsp_write_preset(struct tfa_device *tfa,
- int length, const unsigned char
- *pPresetBytes);
-
-/**
- * wrapper for dsp_msg that adds opcode and only writes
- */
-enum Tfa98xx_Error tfa_dsp_cmd_id_write(struct tfa_device *tfa,
- unsigned char module_id,
- unsigned char param_id, int num_bytes,
- const unsigned char data[]);
-
-/**
- * wrapper for dsp_msg that writes opcode and reads back the data
- */
-enum Tfa98xx_Error tfa_dsp_cmd_id_write_read(struct tfa_device *tfa,
- unsigned char module_id,
- unsigned char param_id, int num_bytes,
- unsigned char data[]);
-
-/**
- * wrapper for dsp_msg that adds opcode and 3 bytes required for coefs
- */
-enum Tfa98xx_Error tfa_dsp_cmd_id_coefs(struct tfa_device *tfa,
- unsigned char module_id,
- unsigned char param_id, int num_bytes,
- unsigned char data[]);
-
-/**
- * wrapper for dsp_msg that adds opcode and 3 bytes required for MBDrcDynamics
- */
-enum Tfa98xx_Error tfa_dsp_cmd_id_MBDrc_dynamics(struct tfa_device *tfa,
- unsigned char module_id,
- unsigned char param_id, int index_subband,
- int num_bytes, unsigned char data[]);
-
-/**
- * Disable a certain biquad.
- * @param tfa the device struct pointer
- * @param biquad_index: 1-10 of the biquad that needs to be adressed
-*/
-enum Tfa98xx_Error Tfa98xx_DspBiquad_Disable(struct tfa_device *tfa,
- int biquad_index);
-
-/**
- * fill the calibration value as milli ohms in the struct
- * assume that the device has been calibrated
- */
-enum Tfa98xx_Error
-tfa_dsp_get_calibration_impedance(struct tfa_device *tfa);
-
-/*
- * return the mohm value
- */
-int tfa_get_calibration_info(struct tfa_device *tfa, int channel);
-
-/*
- * return sign extended tap pattern
- */
-int tfa_get_tap_pattern(struct tfa_device *tfa);
-
-/**
- * Reads a number of words from dsp memory
- * @param tfa the device struct pointer
- * @param subaddress write address to set in address register
- * @param pValue pointer to read data
-*/
-enum Tfa98xx_Error tfa98xx_read_register16(struct tfa_device *tfa,
- unsigned char subaddress,
- unsigned short *pValue);
-
-/**
- * Reads a number of words from dsp memory
- * @param tfa the device struct pointer
- * @param subaddress write address to set in address register
- * @param value value to write int the memory
-*/
-enum Tfa98xx_Error tfa98xx_write_register16(struct tfa_device *tfa,
- unsigned char subaddress,
- unsigned short value);
-
-/**
- * Intialise the dsp
- * @param tfa the device struct pointer
- * @return tfa error enum
-*/
-enum Tfa98xx_Error
-tfa98xx_init_dsp(struct tfa_device *tfa);
-
-/**
- * Get the status of the external DSP
- * @param tfa the device struct pointer
- * @return status
-*/
-int tfa98xx_get_dsp_status(struct tfa_device *tfa);
-
-/**
- * Write a command message (RPC) to the dsp
- * @param tfa the device struct pointer
- * @param num_bytes command buffer size in bytes
- * @param command_buffer
- * @return tfa error enum
-*/
-enum Tfa98xx_Error
-tfa98xx_write_dsp(struct tfa_device *tfa, int num_bytes, const char *command_buffer);
-
-/**
- * Read the result from the last message from the dsp
- * @param tfa the device struct pointer
- * @param num_bytes result buffer size in bytes
- * @param result_buffer
- * @return tfa error enum
-*/
-enum Tfa98xx_Error
-tfa98xx_read_dsp(struct tfa_device *tfa, int num_bytes, unsigned char *result_buffer);
-
-/**
- * Write a command message (RPC) to the dsp and return the result
- * @param tfa the device struct pointer
- * @param command_length command buffer size in bytes
- * @param command_buffer command buffer
- * @param result_length result buffer size in bytes
- * @param result_buffer result buffer
- * @return tfa error enum
-*/
-enum Tfa98xx_Error
-tfa98xx_writeread_dsp(struct tfa_device *tfa, int command_length, void *command_buffer,
- int result_length, void *result_buffer);
-
-/**
- * Reads a number of words from dsp memory
- * @param tfa the device struct pointer
- * @param start_offset offset from where to start reading
- * @param num_words number of words to read
- * @param pValues pointer to read data
-*/
-enum Tfa98xx_Error tfa98xx_dsp_read_mem(struct tfa_device *tfa,
- unsigned int start_offset,
- int num_words, int *pValues);
-/**
- * Write a value to dsp memory
- * @param tfa the device struct pointer
- * @param address write address to set in address register
- * @param value value to write int the memory
- * @param memtype type of memory to write to
-*/
-enum Tfa98xx_Error tfa98xx_dsp_write_mem_word(struct tfa_device *tfa,
- unsigned short address, int value, int memtype);
-
-/**
- * Read data from dsp memory
- * @param tfa the device struct pointer
- * @param subaddress write address to set in address register
- * @param num_bytes number of bytes to read from dsp
- * @param data the unsigned char buffer to read data into
-*/
-enum Tfa98xx_Error tfa98xx_read_data(struct tfa_device *tfa,
- unsigned char subaddress,
- int num_bytes, unsigned char data[]);
-
-/**
- * Write all the bytes specified by num_bytes and data to dsp memory
- * @param tfa the device struct pointer
- * @param subaddress the subaddress to write to
- * @param num_bytes number of bytes to write
- * @param data actual data to write
-*/
-enum Tfa98xx_Error tfa98xx_write_data(struct tfa_device *tfa,
- unsigned char subaddress,
- int num_bytes,
- const unsigned char data[]);
-
-enum Tfa98xx_Error tfa98xx_write_raw(struct tfa_device *tfa,
- int num_bytes,
- const unsigned char data[]);
-
-/* support for converting error codes into text */
-const char *tfa98xx_get_error_string(enum Tfa98xx_Error error);
-
-/**
- * convert signed 24 bit integers to 32bit aligned bytes
- * input: data contains "num_bytes/3" int24 elements
- * output: bytes contains "num_bytes" byte elements
- * @param num_data length of the input data array
- * @param data input data as integer array
- * @param bytes output data as unsigned char array
-*/
-void tfa98xx_convert_data2bytes(int num_data, const int data[],
- unsigned char bytes[]);
-
-/**
- * convert memory bytes to signed 24 bit integers
- * input: bytes contains "num_bytes" byte elements
- * output: data contains "num_bytes/3" int24 elements
- * @param num_bytes length of the input data array
- * @param bytes input data as unsigned char array
- * @param data output data as integer array
-*/
-void tfa98xx_convert_bytes2data(int num_bytes, const unsigned char bytes[],
- int data[]);
-
-/**
- * Read a part of the dsp memory
- * @param tfa the device struct pointer
- * @param memoryType indicator to the memory type
- * @param offset from where to start reading
- * @param length the number of bytes to read
- * @param bytes output data as unsigned char array
-*/
-enum Tfa98xx_Error tfa98xx_dsp_get_memory(struct tfa_device *tfa, int memoryType,
- int offset, int length, unsigned char bytes[]);
-
-/**
- * Write a value to the dsp memory
- * @param tfa the device struct pointer
- * @param memoryType indicator to the memory type
- * @param offset from where to start writing
- * @param length the number of bytes to write
- * @param value the value to write to the dsp
-*/
-enum Tfa98xx_Error tfa98xx_dsp_set_memory(struct tfa_device *tfa, int memoryType,
- int offset, int length, int value);
-
-enum Tfa98xx_Error tfa98xx_dsp_write_config(struct tfa_device *tfa, int length, const unsigned char *p_config_bytes);
-enum Tfa98xx_Error tfa98xx_dsp_write_drc(struct tfa_device *tfa, int length, const unsigned char *p_drc_bytes);
-
-/**
- * write/read raw msg functions :
- * the buffer is provided in little endian format, each word occupying 3 bytes, length is in bytes.
- * The functions will return immediately and do not not wait for DSP reponse.
- * @param tfa the device struct pointer
- * @param length length of the character buffer to write
- * @param buf character buffer to write
-*/
-enum Tfa98xx_Error tfa_dsp_msg(struct tfa_device *tfa, int length, const char *buf);
-
-
-/**
- * The wrapper functions to call the dsp msg, register and memory function for tfa or probus
- */
-enum Tfa98xx_Error dsp_msg(struct tfa_device *tfa, int length, const char *buf);
-enum Tfa98xx_Error dsp_msg_read(struct tfa_device *tfa, int length, unsigned char *bytes);
-enum Tfa98xx_Error reg_write(struct tfa_device *tfa, unsigned char subaddress, unsigned short value);
-enum Tfa98xx_Error reg_read(struct tfa_device *tfa, unsigned char subaddress, unsigned short *value);
-enum Tfa98xx_Error mem_write(struct tfa_device *tfa, unsigned short address, int value, int memtype);
-enum Tfa98xx_Error mem_read(struct tfa_device *tfa, unsigned int start_offset, int num_words, int *pValues);
-
-enum Tfa98xx_Error dsp_partial_coefficients(struct tfa_device *tfa, uint8_t *prev, uint8_t *next);
-int is_94_N2_device(struct tfa_device *tfa);
-/**
- * write/read raw msg functions:
- * the buffer is provided in little endian format, each word occupying 3 bytes, length is in bytes.
- * The functions will return immediately and do not not wait for DSP reponse.
- * An ID is added to modify the command-ID
- * @param tfa the device struct pointer
- * @param length length of the character buffer to write
- * @param buf character buffer to write
- * @param cmdid command identifier
-*/
-enum Tfa98xx_Error tfa_dsp_msg_id(struct tfa_device *tfa, int length, const char *buf, uint8_t cmdid[3]);
-
-/**
- * write raw dsp msg functions
- * @param tfa the device struct pointer
- * @param length length of the character buffer to write
- * @param buffer character buffer to write
-*/
-enum Tfa98xx_Error tfa_dsp_msg_write(struct tfa_device *tfa, int length, const char *buffer);
-
-/**
- * write raw dsp msg functions
- * @param tfa the device struct pointer
- * @param length length of the character buffer to write
- * @param buffer character buffer to write
- * @param cmdid command identifier
-*/
-enum Tfa98xx_Error tfa_dsp_msg_write_id(struct tfa_device *tfa, int length, const char *buffer, uint8_t cmdid[3]);
-
-/**
- * status function used by tfa_dsp_msg() to retrieve command/msg status:
- * return a <0 status of the DSP did not ACK.
- * @param tfa the device struct pointer
- * @param pRpcStatus status for remote processor communication
-*/
-enum Tfa98xx_Error tfa_dsp_msg_status(struct tfa_device *tfa, int *pRpcStatus);
-
-/**
- * Read a message from dsp
- * @param tfa the device struct pointer
- * @param length number of bytes of the message
- * @param bytes pointer to unsigned char buffer
-*/
-enum Tfa98xx_Error tfa_dsp_msg_read(struct tfa_device *tfa,int length, unsigned char *bytes);
-
-int tfa_set_bf(struct tfa_device *tfa, const uint16_t bf, const uint16_t value);
-int tfa_set_bf_volatile(struct tfa_device *tfa, const uint16_t bf, const uint16_t value);
-
-/**
- * Get the value of a given bitfield
- * @param tfa the device struct pointer
- * @param bf the value indicating which bitfield
- */
-int tfa_get_bf(struct tfa_device *tfa, const uint16_t bf);
-
-/**
- * Set the value of a given bitfield
- * @param bf the value indicating which bitfield
- * @param bf_value the value of the bitfield
- * @param p_reg_value a pointer to the register where to write the bitfield value
- */
-int tfa_set_bf_value(const uint16_t bf, const uint16_t bf_value, uint16_t *p_reg_value);
-
-uint16_t tfa_get_bf_value(const uint16_t bf, const uint16_t reg_value);
-int tfa_write_reg(struct tfa_device *tfa, const uint16_t bf, const uint16_t reg_value);
-int tfa_read_reg(struct tfa_device *tfa, const uint16_t bf);
-
-/* bitfield */
-/**
- * get the datasheet or bitfield name corresponding to the bitfield number
- * @param num is the number for which to get the bitfield name
- * @param rev is the device type
- */
-char *tfaContBfName(uint16_t num, unsigned short rev);
-
-/**
- * get the datasheet name corresponding to the bitfield number
- * @param num is the number for which to get the bitfield name
- * @param rev is the device type
- */
-char *tfaContDsName(uint16_t num, unsigned short rev);
-
-/**
- * get the bitfield name corresponding to the bitfield number
- * @param num is the number for which to get the bitfield name
- * @param rev is the device type
- */
-char *tfaContBitName(uint16_t num, unsigned short rev);
-
-/**
- * get the bitfield number corresponding to the bitfield name
- * @param name is the bitfield name for which to get the bitfield number
- * @param rev is the device type
- */
-uint16_t tfaContBfEnum(const char *name, unsigned short rev);
-
-/**
-* get the bitfield number corresponding to the bitfield name, checks for all devices
-* @param name is the bitfield name for which to get the bitfield number
- */
-uint16_t tfaContBfEnumAny(const char *name);
-
-#define TFA_FAM(tfa, fieldname) ((tfa->tfa_family == 1) ? TFA1_BF_##fieldname : TFA2_BF_##fieldname)
-#define TFA_FAM_FW(tfa, fwname) ((tfa->tfa_family == 1) ? TFA1_FW_##fwname : TFA2_FW_##fwname)
-
-/* set/get bit fields to HW register*/
-#define TFA_SET_BF(tfa, fieldname, value) tfa_set_bf(tfa, TFA_FAM(tfa, fieldname), value)
-#define TFA_SET_BF_VOLATILE(tfa, fieldname, value) tfa_set_bf_volatile(tfa, TFA_FAM(tfa, fieldname), value)
-#define TFA_GET_BF(tfa, fieldname) tfa_get_bf(tfa, TFA_FAM(tfa, fieldname))
-
-/* set/get bit field in variable */
-#define TFA_SET_BF_VALUE(tfa, fieldname, bf_value, p_reg_value) tfa_set_bf_value(TFA_FAM(tfa, fieldname), bf_value, p_reg_value)
-#define TFA_GET_BF_VALUE(tfa, fieldname, reg_value) tfa_get_bf_value(TFA_FAM(tfa, fieldname), reg_value)
-
-/* write/read registers using a bit field name to determine the register address */
-#define TFA_WRITE_REG(tfa, fieldname, value) tfa_write_reg(tfa, TFA_FAM(tfa, fieldname), value)
-#define TFA_READ_REG(tfa, fieldname) tfa_read_reg(tfa, TFA_FAM(tfa, fieldname))
-
-/* FOR CALIBRATION RETRIES */
-#define TFA98XX_API_WAITRESULT_NTRIES 3000 // defined in API
-
-/**
- * run the startup/init sequence and set ACS bit
- * @param tfa the device struct pointer
- * @param state the cold start state that is requested
- */
-enum Tfa98xx_Error tfaRunColdboot(struct tfa_device *tfa, int state);
-enum Tfa98xx_Error tfaRunMute(struct tfa_device *tfa);
-enum Tfa98xx_Error tfaRunUnmute(struct tfa_device *tfa);
-
-/**
- * wait for calibrateDone
- * @param tfa the device struct pointer
- * @param calibrateDone pointer to status of calibration
- */
-enum Tfa98xx_Error tfaRunWaitCalibration(struct tfa_device *tfa, int *calibrateDone);
-
-/**
- * run the startup/init sequence and set ACS bit
- * @param tfa the device struct pointer
- * @param profile the profile that should be loaded
- */
-enum Tfa98xx_Error tfaRunColdStartup(struct tfa_device *tfa, int profile);
-
-/**
- * this will load the patch witch will implicitly start the DSP
- * if no patch is available the DPS is started immediately
- * @param tfa the device struct pointer
- */
-enum Tfa98xx_Error tfaRunStartDSP(struct tfa_device *tfa);
-
-/**
- * start the clocks and wait until the AMP is switching
- * on return the DSP sub system will be ready for loading
- * @param tfa the device struct pointer
- * @param profile the profile that should be loaded on startup
- */
-enum Tfa98xx_Error tfaRunStartup(struct tfa_device *tfa, int profile);
-
-/**
- * start the maximus speakerboost algorithm
- * this implies a full system startup when the system was not already started
- * @param tfa the device struct pointer
- * @param force indicates wether a full system startup should be allowed
- * @param profile the profile that should be loaded
- */
-enum Tfa98xx_Error tfaRunSpeakerBoost(struct tfa_device *tfa, int force, int profile);
-
-/**
- * Startup the device and write all files from device and profile section
- * @param tfa the device struct pointer
- * @param force indicates wether a full system startup should be allowed
- * @param profile the profile that should be loaded on speaker startup
- */
-enum Tfa98xx_Error tfaRunSpeakerStartup(struct tfa_device *tfa, int force, int profile);
-
-/**
- * Run calibration
- * @param tfa the device struct pointer
- */
-enum Tfa98xx_Error tfaRunSpeakerCalibration(struct tfa_device *tfa);
-
-/**
- * startup all devices. all step until patch loading is handled
- * @param tfa the device struct pointer
- */
-int tfaRunStartupAll(struct tfa_device *tfa);
-
-/**
- * powerup the coolflux subsystem and wait for it
- * @param tfa the device struct pointer
- */
-enum Tfa98xx_Error tfa_cf_powerup(struct tfa_device *tfa);
-
-/*
- * print the current device manager state
- * @param tfa the device struct pointer
- */
-enum Tfa98xx_Error show_current_state(struct tfa_device *tfa);
-
-/**
- * Init registers and coldboot dsp
- * @param tfa the device struct pointer
- */
-int tfa_reset(struct tfa_device *tfa);
-
-/**
- * Get profile from a register
- * @param tfa the device struct pointer
- */
-int tfa_dev_get_swprof(struct tfa_device *tfa);
-
-/**
- * Save profile in a register
- */
-int tfa_dev_set_swprof(struct tfa_device *tfa, unsigned short new_value);
-
-int tfa_dev_get_swvstep(struct tfa_device *tfa);
-
-int tfa_dev_set_swvstep(struct tfa_device *tfa, unsigned short new_value);
-
-int tfa_needs_reset(struct tfa_device *tfa);
-
-int tfa_is_cold(struct tfa_device *tfa);
-
-void tfa_set_query_info(struct tfa_device *tfa);
-
-int tfa_get_pga_gain(struct tfa_device *tfa);
-int tfa_set_pga_gain(struct tfa_device *tfa, uint16_t value);
-int tfa_get_noclk(struct tfa_device *tfa);
-
-/**
- * Status of used for monitoring
- * @param tfa the device struct pointer
- * @return tfa error enum
- */
-
-enum Tfa98xx_Error tfa_status(struct tfa_device *tfa);
-
-/*
- * function overload for flag_mtp_busy
- */
-int tfa_dev_get_mtpb(struct tfa_device *tfa);
-
-enum Tfa98xx_Error tfaGetFwApiVersion(struct tfa_device *tfa, unsigned char *pFirmwareVersion);
-#ifdef __cplusplus
-}
-#endif
-#endif /* TFA_SERVICE_H */
+/*
+ * Copyright (C) 2014 NXP Semiconductors, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef TFA_SERVICE_H
+#define TFA_SERVICE_H
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
+#include <stdint.h>
+#endif
+#ifdef __cplusplus
+extern "C" {
+#include "NXP_I2C.h"
+#endif
+
+/*
+ * Linux kernel module defines TFA98XX_GIT_VERSIONS in the
+ * linux_driver/Makefile
+ */
+#ifdef TFA98XX_GIT_VERSIONS
+ #define TFA98XX_API_REV_STR "v6.6.3"/*TFA98XX_GIT_VERSIONS*/
+#else
+ #define TFA98XX_API_REV_STR "v6.6.3"
+#endif
+
+#include "tfa_device.h"
+
+/*
+ * data previously defined in Tfa9888_dsp.h
+ */
+#define MEMTRACK_MAX_WORDS 150
+#define LSMODEL_MAX_WORDS 150
+#define TFA98XX_MAXTAG (150)
+#define FW_VAR_API_VERSION (521)
+
+/* Indexes and scaling factors of GetLSmodel */
+#define tfa9888_fs_IDX 128
+#define tfa9888_leakageFactor_IDX 130
+#define tfa9888_ReCorrection_IDX 131
+#define tfa9888_Bl_IDX 132
+#define ReZ_IDX 147
+
+#define tfa9872_leakageFactor_IDX 128
+#define tfa9872_ReCorrection_IDX 129
+#define tfa9872_Bl_IDX 130
+
+#define fs_SCALE (double)1
+#define leakageFactor_SCALE (double)8388608
+#define ReCorrection_SCALE (double)8388608
+#define Bl_SCALE (double)2097152
+#define tCoef_SCALE (double)8388608
+
+/* ---------------------------- Max1 ---------------------------- */
+/* Headroom applied to the main input signal */
+#define SPKRBST_HEADROOM 7
+/* Exponent used for AGC Gain related variables */
+#define SPKRBST_AGCGAIN_EXP SPKRBST_HEADROOM
+#define SPKRBST_TEMPERATURE_EXP 9
+/* Exponent used for Gain Corection related variables */
+#define SPKRBST_LIMGAIN_EXP 4
+#define SPKRBST_TIMECTE_EXP 1
+#define DSP_MAX_GAIN_EXP 7
+/* -------------------------------------------------------------- */
+
+/* speaker related parameters */
+#define TFA2_SPEAKERPARAMETER_LENGTH (3*151) /* MAX2=450 */
+#define TFA1_SPEAKERPARAMETER_LENGTH (3*141) /* MAX1=423 */
+
+/* vstep related parameters */
+#define TFA2_ALGOPARAMETER_LENGTH (3*304) /* N1B = (304) 305 is including the cmd-id */
+#define TFA72_ALGOPARAMETER_LENGTH_MONO (3*183)
+#define TFA72_ALGOPARAMETER_LENGTH_STEREO (3*356)
+#define TFA2_MBDRCPARAMETER_LENGTH (3*152) /* 154 is including the cmd-id */
+#define TFA72_MBDRCPARAMETER_LENGTH (3*98)
+#define TFA1_PRESET_LENGTH 87
+#define TFA1_DRC_LENGTH 381 /* 127 words */
+#define TFA2_FILTERCOEFSPARAMETER_LENGTH (3*168) /* 170 is including the cmd-id */
+#define TFA72_FILTERCOEFSPARAMETER_LENGTH (3*156)
+
+/* Maximum number of retries for DSP result
+ * Keep this value low!
+ * If certain calls require longer wait conditions, the
+ * application should poll, not the API
+ * The total wait time depends on device settings. Those
+ * are application specific.
+ */
+#define TFA98XX_WAITRESULT_NTRIES 40
+#define TFA98XX_WAITRESULT_NTRIES_LONG 2000
+
+/* following lengths are in bytes */
+#define TFA98XX_PRESET_LENGTH 87
+#define TFA98XX_CONFIG_LENGTH 201
+#define TFA98XX_DRC_LENGTH 381 /* 127 words */
+
+typedef unsigned char Tfa98xx_Config_t[TFA98XX_CONFIG_LENGTH];
+typedef unsigned char Tfa98xx_Preset_t[TFA98XX_PRESET_LENGTH];
+typedef unsigned char Tfa98xx_DrcParameters_t[TFA98XX_DRC_LENGTH];
+
+/* Type containing all the possible errors that can occur */
+enum Tfa98xx_Error {
+ Tfa98xx_Error_Ok = 0,
+ Tfa98xx_Error_Device, /* 1. Currently only used to keep in sync with tfa_error */
+ Tfa98xx_Error_Bad_Parameter, /* 2. */
+ Tfa98xx_Error_Fail, /* 3. generic failure, avoid mislead message */
+ Tfa98xx_Error_NoClock, /* 4. no clock detected */
+ Tfa98xx_Error_StateTimedOut, /* 5. */
+ Tfa98xx_Error_DSP_not_running, /* 6. communication with the DSP failed */
+ Tfa98xx_Error_AmpOn, /* 7. amp is still running */
+ Tfa98xx_Error_NotOpen, /* 8. the given handle is not open */
+ Tfa98xx_Error_InUse, /* 9. too many handles */
+ Tfa98xx_Error_Buffer_too_small, /* 10. if a buffer is too small */
+ /* the expected response did not occur within the expected time */
+ Tfa98xx_Error_RpcBase = 100,
+ Tfa98xx_Error_RpcBusy = 101,
+ Tfa98xx_Error_RpcModId = 102,
+ Tfa98xx_Error_RpcParamId = 103,
+ Tfa98xx_Error_RpcInvalidCC = 104,
+ Tfa98xx_Error_RpcInvalidSeq = 105,
+ Tfa98xx_Error_RpcInvalidParam = 106,
+ Tfa98xx_Error_RpcBufferOverflow = 107,
+ Tfa98xx_Error_RpcCalibBusy = 108,
+ Tfa98xx_Error_RpcCalibFailed = 109,
+ Tfa98xx_Error_Not_Implemented,
+ Tfa98xx_Error_Not_Supported,
+ Tfa98xx_Error_I2C_Fatal, /* Fatal I2C error occurred */
+ /* Nonfatal I2C error, and retry count reached */
+ Tfa98xx_Error_I2C_NonFatal,
+ Tfa98xx_Error_Other = 1000
+};
+
+/*
+ * Type containing all the possible msg returns DSP can give
+ * //TODO move to tfa_dsp_fw.h
+ */
+enum Tfa98xx_Status_ID {
+ Tfa98xx_DSP_Not_Running = -1, /* No response from DSP */
+ Tfa98xx_I2C_Req_Done = 0, /* Request executed correctly and result, if any, is available for download */
+ Tfa98xx_I2C_Req_Busy = 1, /* Request is being processed, just wait for result */
+ Tfa98xx_I2C_Req_Invalid_M_ID = 2, /* Provided M-ID does not fit in valid rang [0..2] */
+ Tfa98xx_I2C_Req_Invalid_P_ID = 3, /* Provided P-ID isn�t valid in the given M-ID context */
+ Tfa98xx_I2C_Req_Invalid_CC = 4, /* Invalid channel configuration bits (SC|DS|DP|DC) combination */
+ Tfa98xx_I2C_Req_Invalid_Seq = 5, /* Invalid sequence of commands, in case the DSP expects some commands in a specific order */
+ Tfa98xx_I2C_Req_Invalid_Param = 6, /* Generic error */
+ Tfa98xx_I2C_Req_Buffer_Overflow = 7, /* I2C buffer has overflowed: host has sent too many parameters, memory integrity is not guaranteed */
+ Tfa98xx_I2C_Req_Calib_Busy = 8, /* Calibration not finished */
+ Tfa98xx_I2C_Req_Calib_Failed = 9 /* Calibration failed */
+};
+
+/*
+ * speaker as microphone
+ */
+enum Tfa98xx_saam {
+ Tfa98xx_saam_none, /*< SAAM feature not available */
+ Tfa98xx_saam /*< SAAM feature available */
+};
+
+/*
+ * config file subtypes
+ */
+enum Tfa98xx_config_type {
+ Tfa98xx_config_generic,
+ Tfa98xx_config_sub1,
+ Tfa98xx_config_sub2,
+ Tfa98xx_config_sub3,
+};
+
+enum Tfa98xx_AmpInputSel {
+ Tfa98xx_AmpInputSel_I2SLeft,
+ Tfa98xx_AmpInputSel_I2SRight,
+ Tfa98xx_AmpInputSel_DSP
+};
+
+enum Tfa98xx_OutputSel {
+ Tfa98xx_I2SOutputSel_CurrentSense,
+ Tfa98xx_I2SOutputSel_DSP_Gain,
+ Tfa98xx_I2SOutputSel_DSP_AEC,
+ Tfa98xx_I2SOutputSel_Amp,
+ Tfa98xx_I2SOutputSel_DataI3R,
+ Tfa98xx_I2SOutputSel_DataI3L,
+ Tfa98xx_I2SOutputSel_DcdcFFwdCur,
+};
+
+enum Tfa98xx_StereoGainSel {
+ Tfa98xx_StereoGainSel_Left,
+ Tfa98xx_StereoGainSel_Right
+};
+
+#define TFA98XX_MAXPATCH_LENGTH (3*1024)
+
+/* the number of biquads supported */
+#define TFA98XX_BIQUAD_NUM 10
+
+enum Tfa98xx_Channel {
+ Tfa98xx_Channel_L,
+ Tfa98xx_Channel_R,
+ Tfa98xx_Channel_L_R,
+ Tfa98xx_Channel_Stereo
+};
+
+enum Tfa98xx_Mode {
+ Tfa98xx_Mode_Normal = 0,
+ Tfa98xx_Mode_RCV
+};
+
+enum Tfa98xx_Mute {
+ Tfa98xx_Mute_Off,
+ Tfa98xx_Mute_Digital,
+ Tfa98xx_Mute_Amplifier
+};
+
+enum Tfa98xx_SpeakerBoostStatusFlags {
+ Tfa98xx_SpeakerBoost_Activity = 0, /* Input signal activity. */
+ Tfa98xx_SpeakerBoost_S_Ctrl, /* S Control triggers the limiter */
+ Tfa98xx_SpeakerBoost_Muted, /* 1 when signal is muted */
+ Tfa98xx_SpeakerBoost_X_Ctrl, /* X Control triggers the limiter */
+ Tfa98xx_SpeakerBoost_T_Ctrl, /* T Control triggers the limiter */
+ Tfa98xx_SpeakerBoost_NewModel, /* New model is available */
+ Tfa98xx_SpeakerBoost_VolumeRdy, /* 0:stable vol, 1:still smoothing */
+ Tfa98xx_SpeakerBoost_Damaged, /* Speaker Damage detected */
+ Tfa98xx_SpeakerBoost_SignalClipping /* input clipping detected */
+};
+
+struct Tfa98xx_DrcStateInfo {
+ float GRhighDrc1[2];
+ float GRhighDrc2[2];
+ float GRmidDrc1[2];
+ float GRmidDrc2[2];
+ float GRlowDrc1[2];
+ float GRlowDrc2[2];
+ float GRpostDrc1[2];
+ float GRpostDrc2[2];
+ float GRblDrc[2];
+};
+struct Tfa98xx_StateInfo {
+ /* SpeakerBoost State */
+ float agcGain; /* Current AGC Gain value */
+ float limGain; /* Current Limiter Gain value */
+ float sMax; /* Current Clip/Lim threshold */
+ int T; /* Current Speaker Temperature value */
+ int statusFlag; /* Masked bit word */
+ float X1; /* estimated excursion caused by Spkrboost gain ctrl */
+ float X2; /* estimated excursion caused by manual gain setting */
+ float Re; /* Loudspeaker blocked resistance */
+ /* Framework state */
+ /* increments each time a MIPS problem is detected on the DSP */
+ int shortOnMips;
+ struct Tfa98xx_DrcStateInfo drcState; /* DRC state, when enabled */
+};
+
+typedef struct nxpTfaMsg {
+ uint8_t msg_size;
+ unsigned char cmdId[3];
+ int data[9];
+} nxpTfaMsg_t;
+
+typedef struct nxp_vstep_msg {
+ int fw_version;
+ uint8_t no_of_vsteps;
+ uint16_t reg_no;
+ uint8_t *msg_reg;
+ uint8_t msg_no;
+ uint32_t algo_param_length;
+ uint8_t *msg_algo_param;
+ uint32_t filter_coef_length;
+ uint8_t *msg_filter_coef;
+ uint32_t mbdrc_length;
+ uint8_t *msg_mbdrc;
+} nxp_vstep_msg_t;
+
+typedef struct nxpTfaGroup {
+ uint8_t msg_size;
+ uint8_t profileId[64];
+} nxpTfaGroup_t;
+
+
+struct nxpTfa98xx_Memtrack_data {
+ int length;
+ float mValues[MEMTRACK_MAX_WORDS];
+ int mAdresses[MEMTRACK_MAX_WORDS];
+ int trackers[MEMTRACK_MAX_WORDS];
+ int scalingFactor[MEMTRACK_MAX_WORDS];
+};
+
+/* possible memory values for DMEM in CF_CONTROLs */
+enum Tfa98xx_DMEM {
+ Tfa98xx_DMEM_ERR = -1,
+ Tfa98xx_DMEM_PMEM = 0,
+ Tfa98xx_DMEM_XMEM = 1,
+ Tfa98xx_DMEM_YMEM = 2,
+ Tfa98xx_DMEM_IOMEM = 3,
+};
+
+/**
+ * lookup the device type and return the family type
+ */
+int tfa98xx_dev2family(int dev_type);
+
+/**
+ * register definition structure
+ */
+struct regdef {
+ unsigned char offset; /**< subaddress offset */
+ unsigned short pwronDefault; /**< register contents after poweron */
+ unsigned short pwronTestmask; /**< mask of bits not test */
+ char *name; /**< short register name */
+};
+
+enum Tfa98xx_DMEM tfa98xx_filter_mem(struct tfa_device *tfa, int filter_index, unsigned short *address, int channel);
+
+/**
+ * Load the default HW settings in the device
+ * @param tfa the device struct pointer
+ */
+enum Tfa98xx_Error tfa98xx_init(struct tfa_device *tfa);
+
+/**
+ * If needed, this function can be used to get a text version of the status ID code
+ * @param status the given status ID code
+ * @return the I2C status ID string
+ */
+const char *tfa98xx_get_i2c_status_id_string(int status);
+
+/* control the powerdown bit
+ * @param tfa the device struct pointer
+ * @param powerdown must be 1 or 0
+ */
+enum Tfa98xx_Error tfa98xx_powerdown(struct tfa_device *tfa, int powerdown);
+
+/* indicates on which channel of DATAI2 the gain from the IC is set
+ * @param tfa the device struct pointer
+ * @param gain_sel, see Tfa98xx_StereoGainSel_t
+ */
+enum Tfa98xx_Error tfa98xx_select_stereo_gain_channel(struct tfa_device *tfa,
+ enum Tfa98xx_StereoGainSel gain_sel);
+
+/**
+ * set the mtp with user controllable values
+ * @param tfa the device struct pointer
+ * @param value to be written
+ * @param mask to be applied toi the bits affected
+ */
+enum Tfa98xx_Error tfa98xx_set_mtp(struct tfa_device *tfa, uint16_t value, uint16_t mask);
+enum Tfa98xx_Error tfa98xx_get_mtp(struct tfa_device *tfa, uint16_t *value);
+
+/**
+ * lock or unlock KEY2
+ * lock = 1 will lock
+ * lock = 0 will unlock
+ * note that on return all the hidden key will be off
+ */
+void tfa98xx_key2(struct tfa_device *tfa, int lock);
+
+int tfa_calibrate(struct tfa_device *tfa) ;
+void tfa98xx_set_exttemp(struct tfa_device *tfa, short ext_temp);
+short tfa98xx_get_exttemp(struct tfa_device *tfa);
+
+/* control the volume of the DSP
+ * @param vol volume in bit field. It must be between 0 and 255
+ */
+enum Tfa98xx_Error tfa98xx_set_volume_level(struct tfa_device *tfa,
+ unsigned short vol);
+
+/* set the input channel to use
+ * @param channel see Tfa98xx_Channel_t enumeration
+ */
+enum Tfa98xx_Error tfa98xx_select_channel(struct tfa_device *tfa,
+ enum Tfa98xx_Channel channel);
+
+/* set the mode for normal or receiver mode
+ * @param mode see Tfa98xx_Mode enumeration
+ */
+enum Tfa98xx_Error tfa98xx_select_mode(struct tfa_device *tfa, enum Tfa98xx_Mode mode);
+
+/* mute/unmute the audio
+ * @param mute see Tfa98xx_Mute_t enumeration
+ */
+enum Tfa98xx_Error tfa98xx_set_mute(struct tfa_device *tfa,
+ enum Tfa98xx_Mute mute);
+
+/*
+ * tfa_supported_speakers - required for SmartStudio initialization
+ * returns the number of the supported speaker count
+ */
+enum Tfa98xx_Error tfa_supported_speakers(struct tfa_device *tfa, int *spkr_count);
+
+/**
+* Return the tfa revision
+*/
+void tfa98xx_rev(int *major, int *minor, int *revision);
+
+/*
+ * Return the feature bits from MTP and cnt file for comparison
+ */
+enum Tfa98xx_Error
+tfa98xx_compare_features(struct tfa_device *tfa, int features_from_MTP[3], int features_from_cnt[3]);
+
+/*
+ * return feature bits
+ */
+enum Tfa98xx_Error
+tfa98xx_dsp_get_sw_feature_bits(struct tfa_device *tfa, int features[2]);
+enum Tfa98xx_Error
+tfa98xx_dsp_get_hw_feature_bits(struct tfa_device *tfa, int *features);
+
+/*
+ * tfa98xx_supported_saam
+ * returns the speaker as microphone feature
+ * @param saam enum pointer
+ * @return error code
+ */
+enum Tfa98xx_Error tfa98xx_supported_saam(struct tfa_device *tfa, enum Tfa98xx_saam *saam);
+
+/* load the tables to the DSP
+ * called after patch load is done
+ * @return error code
+ */
+enum Tfa98xx_Error tfa98xx_dsp_write_tables(struct tfa_device *tfa, int sample_rate);
+
+
+/* set or clear DSP reset signal
+ * @param new state
+ * @return error code
+ */
+enum Tfa98xx_Error tfa98xx_dsp_reset(struct tfa_device *tfa, int state);
+
+/* check the state of the DSP subsystem
+ * return ready = 1 when clocks are stable to allow safe DSP subsystem access
+ * @param tfa the device struct pointer
+ * @param ready pointer to state flag, non-zero if clocks are not stable
+ * @return error code
+ */
+enum Tfa98xx_Error tfa98xx_dsp_system_stable(struct tfa_device *tfa, int *ready);
+
+enum Tfa98xx_Error tfa98xx_auto_copy_mtp_to_iic(struct tfa_device *tfa);
+
+/**
+ * check the state of the DSP coolflux
+ * @param tfa the device struct pointer
+ * @return the value of CFE
+ */
+int tfa_cf_enabled(struct tfa_device *tfa);
+
+/* The following functions can only be called when the DSP is running
+ * - I2S clock must be active,
+ * - IC must be in operating mode
+ */
+
+/**
+ * patch the ROM code of the DSP
+ * @param tfa the device struct pointer
+ * @param patchLength the number of bytes of patchBytes
+ * @param patchBytes pointer to the bytes to patch
+ */
+enum Tfa98xx_Error tfa_dsp_patch(struct tfa_device *tfa,
+ int patchLength,
+ const unsigned char *patchBytes);
+
+/**
+ * load explicitly the speaker parameters in case of free speaker,
+ * or when using a saved speaker model
+ */
+enum Tfa98xx_Error tfa98xx_dsp_write_speaker_parameters(
+ struct tfa_device *tfa,
+ int length,
+ const unsigned char *pSpeakerBytes);
+
+/**
+ * read the speaker parameters as used by the SpeakerBoost processing
+ */
+enum Tfa98xx_Error tfa98xx_dsp_read_speaker_parameters(
+ struct tfa_device *tfa,
+ int length,
+ unsigned char *pSpeakerBytes);
+
+/**
+ * read the current status of the DSP, typically used for development,
+ * not essential to be used in a product
+ */
+enum Tfa98xx_Error tfa98xx_dsp_get_state_info(
+ struct tfa_device *tfa,
+ unsigned char bytes[],
+ unsigned int *statesize);
+
+/**
+ * Check whether the DSP supports DRC
+ * pbSupportDrc=1 when DSP supports DRC,
+ * pbSupportDrc=0 when DSP doesn't support it
+ */
+enum Tfa98xx_Error tfa98xx_dsp_support_drc(struct tfa_device *tfa,
+ int *pbSupportDrc);
+
+enum Tfa98xx_Error
+tfa98xx_dsp_support_framework(struct tfa_device *tfa, int *pbSupportFramework);
+
+/**
+ * read the speaker excursion model as used by SpeakerBoost processing
+ */
+enum Tfa98xx_Error tfa98xx_dsp_read_excursion_model(
+ struct tfa_device *tfa,
+ int length,
+ unsigned char *pSpeakerBytes);
+
+/**
+ * load all the parameters for a preset from a file
+ */
+enum Tfa98xx_Error tfa98xx_dsp_write_preset(struct tfa_device *tfa,
+ int length, const unsigned char
+ *pPresetBytes);
+
+/**
+ * wrapper for dsp_msg that adds opcode and only writes
+ */
+enum Tfa98xx_Error tfa_dsp_cmd_id_write(struct tfa_device *tfa,
+ unsigned char module_id,
+ unsigned char param_id, int num_bytes,
+ const unsigned char data[]);
+
+/**
+ * wrapper for dsp_msg that writes opcode and reads back the data
+ */
+enum Tfa98xx_Error tfa_dsp_cmd_id_write_read(struct tfa_device *tfa,
+ unsigned char module_id,
+ unsigned char param_id, int num_bytes,
+ unsigned char data[]);
+
+/**
+ * wrapper for dsp_msg that adds opcode and 3 bytes required for coefs
+ */
+enum Tfa98xx_Error tfa_dsp_cmd_id_coefs(struct tfa_device *tfa,
+ unsigned char module_id,
+ unsigned char param_id, int num_bytes,
+ unsigned char data[]);
+
+/**
+ * wrapper for dsp_msg that adds opcode and 3 bytes required for MBDrcDynamics
+ */
+enum Tfa98xx_Error tfa_dsp_cmd_id_MBDrc_dynamics(struct tfa_device *tfa,
+ unsigned char module_id,
+ unsigned char param_id, int index_subband,
+ int num_bytes, unsigned char data[]);
+
+/**
+ * Disable a certain biquad.
+ * @param tfa the device struct pointer
+ * @param biquad_index: 1-10 of the biquad that needs to be adressed
+*/
+enum Tfa98xx_Error Tfa98xx_DspBiquad_Disable(struct tfa_device *tfa,
+ int biquad_index);
+
+/**
+ * fill the calibration value as milli ohms in the struct
+ * assume that the device has been calibrated
+ */
+enum Tfa98xx_Error
+tfa_dsp_get_calibration_impedance(struct tfa_device *tfa);
+
+/*
+ * return the mohm value
+ */
+int tfa_get_calibration_info(struct tfa_device *tfa, int channel);
+
+/*
+ * return sign extended tap pattern
+ */
+int tfa_get_tap_pattern(struct tfa_device *tfa);
+
+/**
+ * Reads a number of words from dsp memory
+ * @param tfa the device struct pointer
+ * @param subaddress write address to set in address register
+ * @param pValue pointer to read data
+*/
+enum Tfa98xx_Error tfa98xx_read_register16(struct tfa_device *tfa,
+ unsigned char subaddress,
+ unsigned short *pValue);
+
+/**
+ * Reads a number of words from dsp memory
+ * @param tfa the device struct pointer
+ * @param subaddress write address to set in address register
+ * @param value value to write int the memory
+*/
+enum Tfa98xx_Error tfa98xx_write_register16(struct tfa_device *tfa,
+ unsigned char subaddress,
+ unsigned short value);
+
+/**
+ * Intialise the dsp
+ * @param tfa the device struct pointer
+ * @return tfa error enum
+*/
+enum Tfa98xx_Error
+tfa98xx_init_dsp(struct tfa_device *tfa);
+
+/**
+ * Get the status of the external DSP
+ * @param tfa the device struct pointer
+ * @return status
+*/
+int tfa98xx_get_dsp_status(struct tfa_device *tfa);
+
+/**
+ * Write a command message (RPC) to the dsp
+ * @param tfa the device struct pointer
+ * @param num_bytes command buffer size in bytes
+ * @param command_buffer
+ * @return tfa error enum
+*/
+enum Tfa98xx_Error
+tfa98xx_write_dsp(struct tfa_device *tfa, int num_bytes, const char *command_buffer);
+
+/**
+ * Read the result from the last message from the dsp
+ * @param tfa the device struct pointer
+ * @param num_bytes result buffer size in bytes
+ * @param result_buffer
+ * @return tfa error enum
+*/
+enum Tfa98xx_Error
+tfa98xx_read_dsp(struct tfa_device *tfa, int num_bytes, unsigned char *result_buffer);
+
+/**
+ * Write a command message (RPC) to the dsp and return the result
+ * @param tfa the device struct pointer
+ * @param command_length command buffer size in bytes
+ * @param command_buffer command buffer
+ * @param result_length result buffer size in bytes
+ * @param result_buffer result buffer
+ * @return tfa error enum
+*/
+enum Tfa98xx_Error
+tfa98xx_writeread_dsp(struct tfa_device *tfa, int command_length, void *command_buffer,
+ int result_length, void *result_buffer);
+
+/**
+ * Reads a number of words from dsp memory
+ * @param tfa the device struct pointer
+ * @param start_offset offset from where to start reading
+ * @param num_words number of words to read
+ * @param pValues pointer to read data
+*/
+enum Tfa98xx_Error tfa98xx_dsp_read_mem(struct tfa_device *tfa,
+ unsigned int start_offset,
+ int num_words, int *pValues);
+/**
+ * Write a value to dsp memory
+ * @param tfa the device struct pointer
+ * @param address write address to set in address register
+ * @param value value to write int the memory
+ * @param memtype type of memory to write to
+*/
+enum Tfa98xx_Error tfa98xx_dsp_write_mem_word(struct tfa_device *tfa,
+ unsigned short address, int value, int memtype);
+
+/**
+ * Read data from dsp memory
+ * @param tfa the device struct pointer
+ * @param subaddress write address to set in address register
+ * @param num_bytes number of bytes to read from dsp
+ * @param data the unsigned char buffer to read data into
+*/
+enum Tfa98xx_Error tfa98xx_read_data(struct tfa_device *tfa,
+ unsigned char subaddress,
+ int num_bytes, unsigned char data[]);
+
+/**
+ * Write all the bytes specified by num_bytes and data to dsp memory
+ * @param tfa the device struct pointer
+ * @param subaddress the subaddress to write to
+ * @param num_bytes number of bytes to write
+ * @param data actual data to write
+*/
+enum Tfa98xx_Error tfa98xx_write_data(struct tfa_device *tfa,
+ unsigned char subaddress,
+ int num_bytes,
+ const unsigned char data[]);
+
+enum Tfa98xx_Error tfa98xx_write_raw(struct tfa_device *tfa,
+ int num_bytes,
+ const unsigned char data[]);
+
+/* support for converting error codes into text */
+const char *tfa98xx_get_error_string(enum Tfa98xx_Error error);
+
+/**
+ * convert signed 24 bit integers to 32bit aligned bytes
+ * input: data contains "num_bytes/3" int24 elements
+ * output: bytes contains "num_bytes" byte elements
+ * @param num_data length of the input data array
+ * @param data input data as integer array
+ * @param bytes output data as unsigned char array
+*/
+void tfa98xx_convert_data2bytes(int num_data, const int data[],
+ unsigned char bytes[]);
+
+/**
+ * convert memory bytes to signed 24 bit integers
+ * input: bytes contains "num_bytes" byte elements
+ * output: data contains "num_bytes/3" int24 elements
+ * @param num_bytes length of the input data array
+ * @param bytes input data as unsigned char array
+ * @param data output data as integer array
+*/
+void tfa98xx_convert_bytes2data(int num_bytes, const unsigned char bytes[],
+ int data[]);
+
+/**
+ * Read a part of the dsp memory
+ * @param tfa the device struct pointer
+ * @param memoryType indicator to the memory type
+ * @param offset from where to start reading
+ * @param length the number of bytes to read
+ * @param bytes output data as unsigned char array
+*/
+enum Tfa98xx_Error tfa98xx_dsp_get_memory(struct tfa_device *tfa,
+ int memoryType, int offset, int length,
+ unsigned char bytes[]);
+
+/**
+ * Write a value to the dsp memory
+ * @param tfa the device struct pointer
+ * @param memoryType indicator to the memory type
+ * @param offset from where to start writing
+ * @param length the number of bytes to write
+ * @param value the value to write to the dsp
+*/
+enum Tfa98xx_Error tfa98xx_dsp_set_memory(struct tfa_device *tfa,
+ int memoryType, int offset,
+ int length, int value);
+
+enum Tfa98xx_Error tfa98xx_dsp_write_config(struct tfa_device *tfa, int length,
+ const unsigned char *p_config_bytes);
+enum Tfa98xx_Error tfa98xx_dsp_write_drc(struct tfa_device *tfa, int length,
+ const unsigned char *p_drc_bytes);
+
+/**
+ * write/read raw msg functions :
+ * the buffer is provided in little endian format, each word occupying 3 bytes, length is in bytes
+ * The functions will return immediately and do not not wait for DSP response
+ * @param tfa the device struct pointer
+ * @param length length of the character buffer to write
+ * @param buf character buffer to write
+*/
+enum Tfa98xx_Error tfa_dsp_msg(struct tfa_device *tfa, int length, const char *buf);
+
+
+/**
+ * The wrapper functions to call the dsp msg, register and memory function for tfa or probus
+ */
+enum Tfa98xx_Error dsp_msg(struct tfa_device *tfa, int length, const char *buf);
+enum Tfa98xx_Error dsp_msg_read(struct tfa_device *tfa, int length, unsigned char *bytes);
+enum Tfa98xx_Error reg_write(struct tfa_device *tfa, unsigned char subaddress, unsigned short value);
+enum Tfa98xx_Error reg_read(struct tfa_device *tfa, unsigned char subaddress, unsigned short *value);
+enum Tfa98xx_Error mem_write(struct tfa_device *tfa, unsigned short address, int value, int memtype);
+enum Tfa98xx_Error mem_read(struct tfa_device *tfa, unsigned int start_offset, int num_words, int *pValues);
+
+enum Tfa98xx_Error dsp_partial_coefficients(struct tfa_device *tfa, uint8_t *prev, uint8_t *next);
+int is_94_N2_device(struct tfa_device *tfa);
+/**
+ * write/read raw msg functions:
+ * the buffer is provided in little endian format, each word occupying 3 bytes,
+ * length is in bytes The functions will return immediately and do not not wait
+ * for DSP response. An ID is added to modify the command-ID
+ * @param tfa the device struct pointer
+ * @param length length of the character buffer to write
+ * @param buf character buffer to write
+ * @param cmdid command identifier
+*/
+enum Tfa98xx_Error tfa_dsp_msg_id(struct tfa_device *tfa, int length,
+ const char *buf, uint8_t cmdid[3]);
+
+/**
+ * write raw dsp msg functions
+ * @param tfa the device struct pointer
+ * @param length length of the character buffer to write
+ * @param buffer character buffer to write
+*/
+enum Tfa98xx_Error tfa_dsp_msg_write(struct tfa_device *tfa, int length,
+ const char *buffer);
+
+/**
+ * write raw dsp msg functions
+ * @param tfa the device struct pointer
+ * @param length length of the character buffer to write
+ * @param buffer character buffer to write
+ * @param cmdid command identifier
+*/
+enum Tfa98xx_Error tfa_dsp_msg_write_id(struct tfa_device *tfa, int length,
+ const char *buffer, uint8_t cmdid[3]);
+
+/**
+ * status function used by tfa_dsp_msg() to retrieve command/msg status:
+ * return a <0 status of the DSP did not ACK.
+ * @param tfa the device struct pointer
+ * @param pRpcStatus status for remote processor communication
+*/
+enum Tfa98xx_Error tfa_dsp_msg_status(struct tfa_device *tfa, int *pRpcStatus);
+
+/**
+ * Read a message from dsp
+ * @param tfa the device struct pointer
+ * @param length number of bytes of the message
+ * @param bytes pointer to unsigned char buffer
+*/
+enum Tfa98xx_Error tfa_dsp_msg_read(struct tfa_device *tfa, int length,
+ unsigned char *bytes);
+
+int tfa_set_bf(struct tfa_device *tfa, const uint16_t bf, const uint16_t value);
+int tfa_set_bf_volatile(struct tfa_device *tfa, const uint16_t bf,
+ const uint16_t value);
+
+/**
+ * Get the value of a given bitfield
+ * @param tfa the device struct pointer
+ * @param bf the value indicating which bitfield
+ */
+int tfa_get_bf(struct tfa_device *tfa, const uint16_t bf);
+
+/**
+ * Set the value of a given bitfield
+ * @param bf the value indicating which bitfield
+ * @param bf_value the value of the bitfield
+ * @param p_reg_value a pointer to the register where to write the bitfield
+ * value
+ */
+int tfa_set_bf_value(const uint16_t bf, const uint16_t bf_value,
+ uint16_t *p_reg_value);
+
+uint16_t tfa_get_bf_value(const uint16_t bf, const uint16_t reg_value);
+int tfa_write_reg(struct tfa_device *tfa, const uint16_t bf,
+ const uint16_t reg_value);
+int tfa_read_reg(struct tfa_device *tfa, const uint16_t bf);
+
+/* bitfield */
+/**
+ * get the datasheet or bitfield name corresponding to the bitfield number
+ * @param num is the number for which to get the bitfield name
+ * @param rev is the device type
+ */
+char *tfaContBfName(uint16_t num, unsigned short rev);
+
+/**
+ * get the datasheet name corresponding to the bitfield number
+ * @param num is the number for which to get the bitfield name
+ * @param rev is the device type
+ */
+char *tfaContDsName(uint16_t num, unsigned short rev);
+
+/**
+ * get the bitfield name corresponding to the bitfield number
+ * @param num is the number for which to get the bitfield name
+ * @param rev is the device type
+ */
+char *tfaContBitName(uint16_t num, unsigned short rev);
+
+/**
+ * get the bitfield number corresponding to the bitfield name
+ * @param name is the bitfield name for which to get the bitfield number
+ * @param rev is the device type
+ */
+uint16_t tfaContBfEnum(const char *name, unsigned short rev);
+
+/**
+* get the bitfield number corresponding to the bitfield name, checks for all devices
+* @param name is the bitfield name for which to get the bitfield number
+ */
+uint16_t tfaContBfEnumAny(const char *name);
+
+#define TFA_FAM(tfa, fieldname) ((tfa->tfa_family == 1) ? TFA1_BF_##fieldname : TFA2_BF_##fieldname)
+#define TFA_FAM_FW(tfa, fwname) ((tfa->tfa_family == 1) ? TFA1_FW_##fwname : TFA2_FW_##fwname)
+
+/* set/get bit fields to HW register*/
+#define TFA_SET_BF(tfa, fieldname, value) tfa_set_bf(tfa, TFA_FAM(tfa, fieldname), value)
+#define TFA_SET_BF_VOLATILE(tfa, fieldname, value) tfa_set_bf_volatile(tfa, TFA_FAM(tfa, fieldname), value)
+#define TFA_GET_BF(tfa, fieldname) tfa_get_bf(tfa, TFA_FAM(tfa, fieldname))
+
+/* set/get bit field in variable */
+#define TFA_SET_BF_VALUE(tfa, fieldname, bf_value, p_reg_value) tfa_set_bf_value(TFA_FAM(tfa, fieldname), bf_value, p_reg_value)
+#define TFA_GET_BF_VALUE(tfa, fieldname, reg_value) tfa_get_bf_value(TFA_FAM(tfa, fieldname), reg_value)
+
+/* write/read registers using a bit field name to determine the register address */
+#define TFA_WRITE_REG(tfa, fieldname, value) tfa_write_reg(tfa, TFA_FAM(tfa, fieldname), value)
+#define TFA_READ_REG(tfa, fieldname) tfa_read_reg(tfa, TFA_FAM(tfa, fieldname))
+
+/* FOR CALIBRATION RETRIES */
+#define TFA98XX_API_WAITRESULT_NTRIES 3000 // defined in API
+
+/**
+ * run the startup/init sequence and set ACS bit
+ * @param tfa the device struct pointer
+ * @param state the cold start state that is requested
+ */
+enum Tfa98xx_Error tfaRunColdboot(struct tfa_device *tfa, int state);
+enum Tfa98xx_Error tfaRunMute(struct tfa_device *tfa);
+enum Tfa98xx_Error tfaRunUnmute(struct tfa_device *tfa);
+
+/**
+ * wait for calibrateDone
+ * @param tfa the device struct pointer
+ * @param calibrateDone pointer to status of calibration
+ */
+enum Tfa98xx_Error tfaRunWaitCalibration(struct tfa_device *tfa, int *calibrateDone);
+
+/**
+ * run the startup/init sequence and set ACS bit
+ * @param tfa the device struct pointer
+ * @param profile the profile that should be loaded
+ */
+enum Tfa98xx_Error tfaRunColdStartup(struct tfa_device *tfa, int profile);
+
+/**
+ * this will load the patch witch will implicitly start the DSP
+ * if no patch is available the DPS is started immediately
+ * @param tfa the device struct pointer
+ */
+enum Tfa98xx_Error tfaRunStartDSP(struct tfa_device *tfa);
+
+/**
+ * start the clocks and wait until the AMP is switching
+ * on return the DSP sub system will be ready for loading
+ * @param tfa the device struct pointer
+ * @param profile the profile that should be loaded on startup
+ */
+enum Tfa98xx_Error tfaRunStartup(struct tfa_device *tfa, int profile);
+
+/**
+ * start the maximus speakerboost algorithm
+ * this implies a full system startup when the system was not already started
+ * @param tfa the device struct pointer
+ * @param force indicates whether a full system startup should be allowed
+ * @param profile the profile that should be loaded
+ */
+enum Tfa98xx_Error tfaRunSpeakerBoost(struct tfa_device *tfa,
+ int force, int profile);
+
+/**
+ * Startup the device and write all files from device and profile section
+ * @param tfa the device struct pointer
+ * @param force indicates whether a full system startup should be allowed
+ * @param profile the profile that should be loaded on speaker startup
+ */
+enum Tfa98xx_Error tfaRunSpeakerStartup(struct tfa_device *tfa, int force,
+ int profile);
+
+/**
+ * Run calibration
+ * @param tfa the device struct pointer
+ */
+enum Tfa98xx_Error tfaRunSpeakerCalibration(struct tfa_device *tfa);
+
+/**
+ * startup all devices. all step until patch loading is handled
+ * @param tfa the device struct pointer
+ */
+int tfaRunStartupAll(struct tfa_device *tfa);
+
+/**
+ * powerup the coolflux subsystem and wait for it
+ * @param tfa the device struct pointer
+ */
+enum Tfa98xx_Error tfa_cf_powerup(struct tfa_device *tfa);
+
+/*
+ * print the current device manager state
+ * @param tfa the device struct pointer
+ */
+enum Tfa98xx_Error show_current_state(struct tfa_device *tfa);
+
+/**
+ * Init registers and coldboot dsp
+ * @param tfa the device struct pointer
+ */
+int tfa_reset(struct tfa_device *tfa);
+
+/**
+ * Get profile from a register
+ * @param tfa the device struct pointer
+ */
+int tfa_dev_get_swprof(struct tfa_device *tfa);
+
+/**
+ * Save profile in a register
+ */
+int tfa_dev_set_swprof(struct tfa_device *tfa, unsigned short new_value);
+
+int tfa_dev_get_swvstep(struct tfa_device *tfa);
+
+int tfa_dev_set_swvstep(struct tfa_device *tfa, unsigned short new_value);
+
+int tfa_needs_reset(struct tfa_device *tfa);
+
+int tfa_is_cold(struct tfa_device *tfa);
+
+void tfa_set_query_info(struct tfa_device *tfa);
+
+int tfa_get_pga_gain(struct tfa_device *tfa);
+int tfa_set_pga_gain(struct tfa_device *tfa, uint16_t value);
+int tfa_get_noclk(struct tfa_device *tfa);
+
+/**
+ * Status of used for monitoring
+ * @param tfa the device struct pointer
+ * @return tfa error enum
+ */
+
+enum Tfa98xx_Error tfa_status(struct tfa_device *tfa);
+
+/*
+ * function overload for flag_mtp_busy
+ */
+int tfa_dev_get_mtpb(struct tfa_device *tfa);
+
+enum Tfa98xx_Error tfaGetFwApiVersion(struct tfa_device *tfa, unsigned char *pFirmwareVersion);
+#ifdef __cplusplus
+}
+#endif
+#endif /* TFA_SERVICE_H */
diff --git a/sound/soc/soc-jack.c b/sound/soc/soc-jack.c
index fbaa1bb..00d7902 100644
--- a/sound/soc/soc-jack.c
+++ b/sound/soc/soc-jack.c
@@ -80,10 +80,9 @@ void snd_soc_jack_report(struct snd_soc_jack *jack, int status, int mask)
unsigned int sync = 0;
int enable;
- trace_snd_soc_jack_report(jack, mask, status);
-
if (!jack)
return;
+ trace_snd_soc_jack_report(jack, mask, status);
dapm = &jack->card->dapm;
diff --git a/tools/lib/traceevent/parse-filter.c b/tools/lib/traceevent/parse-filter.c
index 5e10ba7..569bcef 100644
--- a/tools/lib/traceevent/parse-filter.c
+++ b/tools/lib/traceevent/parse-filter.c
@@ -1492,8 +1492,10 @@ static int copy_filter_type(struct event_filter *filter,
if (strcmp(str, "TRUE") == 0 || strcmp(str, "FALSE") == 0) {
/* Add trivial event */
arg = allocate_arg();
- if (arg == NULL)
+ if (arg == NULL) {
+ free(str);
return -1;
+ }
arg->type = FILTER_ARG_BOOLEAN;
if (strcmp(str, "TRUE") == 0)
@@ -1502,8 +1504,11 @@ static int copy_filter_type(struct event_filter *filter,
arg->boolean.value = 0;
filter_type = add_filter_type(filter, event->id);
- if (filter_type == NULL)
+ if (filter_type == NULL) {
+ free(str);
+ free_arg(arg);
return -1;
+ }
filter_type->filter = arg;
diff --git a/tools/objtool/arch/x86/lib/x86-opcode-map.txt b/tools/objtool/arch/x86/lib/x86-opcode-map.txt
index 1754e09..0f7eb4f 100644
--- a/tools/objtool/arch/x86/lib/x86-opcode-map.txt
+++ b/tools/objtool/arch/x86/lib/x86-opcode-map.txt
@@ -333,7 +333,7 @@
06: CLTS
07: SYSRET (o64)
08: INVD
-09: WBINVD
+09: WBINVD | WBNOINVD (F3)
0a:
0b: UD2 (1B)
0c:
@@ -364,7 +364,7 @@
# a ModR/M byte.
1a: BNDCL Gv,Ev (F3) | BNDCU Gv,Ev (F2) | BNDMOV Gv,Ev (66) | BNDLDX Gv,Ev
1b: BNDCN Gv,Ev (F2) | BNDMOV Ev,Gv (66) | BNDMK Gv,Ev (F3) | BNDSTX Ev,Gv
-1c:
+1c: Grp20 (1A),(1C)
1d:
1e:
1f: NOP Ev
@@ -792,6 +792,8 @@
f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v)
f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v)
f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) | SHRX Gy,Ey,By (F2),(v)
+f8: MOVDIR64B Gv,Mdqq (66) | ENQCMD Gv,Mdqq (F2) | ENQCMDS Gv,Mdqq (F3)
+f9: MOVDIRI My,Gy
EndTable
Table: 3-byte opcode 2 (0x0f 0x3a)
@@ -943,9 +945,9 @@
EndTable
GrpTable: Grp7
-0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B)
-1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B)
-2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B)
+0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B) | PCONFIG (101),(11B) | ENCLV (000),(11B)
+1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B) | ENCLS (111),(11B)
+2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B) | ENCLU (111),(11B)
3: LIDT Ms
4: SMSW Mw/Rv
5: rdpkru (110),(11B) | wrpkru (111),(11B)
@@ -1011,7 +1013,7 @@
3: vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B)
4: XSAVE
5: XRSTOR | lfence (11B)
-6: XSAVEOPT | clwb (66) | mfence (11B)
+6: XSAVEOPT | clwb (66) | mfence (11B) | TPAUSE Rd (66),(11B) | UMONITOR Rv (F3),(11B) | UMWAIT Rd (F2),(11B)
7: clflush | clflushopt (66) | sfence (11B)
EndTable
@@ -1042,6 +1044,10 @@
6: vscatterpf1qps/d Wx (66),(ev)
EndTable
+GrpTable: Grp20
+0: cldemote Mb
+EndTable
+
# AMD's Prefetch Group
GrpTable: GrpP
0: PREFETCH
diff --git a/tools/perf/builtin-report.c b/tools/perf/builtin-report.c
index 6e88460..33ff5c8 100644
--- a/tools/perf/builtin-report.c
+++ b/tools/perf/builtin-report.c
@@ -292,6 +292,13 @@ static int report__setup_sample_type(struct report *rep)
PERF_SAMPLE_BRANCH_ANY))
rep->nonany_branch_mode = true;
+#ifndef HAVE_LIBUNWIND_SUPPORT
+ if (dwarf_callchain_users) {
+ ui__warning("Please install libunwind development packages "
+ "during the perf build.\n");
+ }
+#endif
+
return 0;
}
diff --git a/tools/perf/tests/task-exit.c b/tools/perf/tests/task-exit.c
index b0d005d..de2ddfe 100644
--- a/tools/perf/tests/task-exit.c
+++ b/tools/perf/tests/task-exit.c
@@ -98,6 +98,7 @@ int test__task_exit(int subtest __maybe_unused)
if (perf_evlist__mmap(evlist, 128, true) < 0) {
pr_debug("failed to mmap events: %d (%s)\n", errno,
str_error_r(errno, sbuf, sizeof(sbuf)));
+ err = -1;
goto out_delete_evlist;
}
diff --git a/tools/perf/util/dwarf-aux.c b/tools/perf/util/dwarf-aux.c
index 41e068e..fb4e1d2 100644
--- a/tools/perf/util/dwarf-aux.c
+++ b/tools/perf/util/dwarf-aux.c
@@ -318,20 +318,50 @@ bool die_is_func_def(Dwarf_Die *dw_die)
}
/**
+ * die_entrypc - Returns entry PC (the lowest address) of a DIE
+ * @dw_die: a DIE
+ * @addr: where to store entry PC
+ *
+ * Since dwarf_entrypc() does not return entry PC if the DIE has only address
+ * range, we have to use this to retrieve the lowest address from the address
+ * range attribute.
+ */
+int die_entrypc(Dwarf_Die *dw_die, Dwarf_Addr *addr)
+{
+ Dwarf_Addr base, end;
+
+ if (!addr)
+ return -EINVAL;
+
+ if (dwarf_entrypc(dw_die, addr) == 0)
+ return 0;
+
+ return dwarf_ranges(dw_die, 0, &base, addr, &end) < 0 ? -ENOENT : 0;
+}
+
+/**
* die_is_func_instance - Ensure that this DIE is an instance of a subprogram
* @dw_die: a DIE
*
* Ensure that this DIE is an instance (which has an entry address).
- * This returns true if @dw_die is a function instance. If not, you need to
- * call die_walk_instances() to find actual instances.
+ * This returns true if @dw_die is a function instance. If not, the @dw_die
+ * must be a prototype. You can use die_walk_instances() to find actual
+ * instances.
**/
bool die_is_func_instance(Dwarf_Die *dw_die)
{
Dwarf_Addr tmp;
+ Dwarf_Attribute attr_mem;
+ int tag = dwarf_tag(dw_die);
- /* Actually gcc optimizes non-inline as like as inlined */
- return !dwarf_func_inline(dw_die) && dwarf_entrypc(dw_die, &tmp) == 0;
+ if (tag != DW_TAG_subprogram &&
+ tag != DW_TAG_inlined_subroutine)
+ return false;
+
+ return dwarf_entrypc(dw_die, &tmp) == 0 ||
+ dwarf_attr(dw_die, DW_AT_ranges, &attr_mem) != NULL;
}
+
/**
* die_get_data_member_location - Get the data-member offset
* @mb_die: a DIE of a member of a data structure
@@ -608,6 +638,9 @@ static int __die_walk_instances_cb(Dwarf_Die *inst, void *data)
Dwarf_Die *origin;
int tmp;
+ if (!die_is_func_instance(inst))
+ return DIE_FIND_CB_CONTINUE;
+
attr = dwarf_attr(inst, DW_AT_abstract_origin, &attr_mem);
if (attr == NULL)
return DIE_FIND_CB_CONTINUE;
@@ -679,15 +712,14 @@ static int __die_walk_funclines_cb(Dwarf_Die *in_die, void *data)
if (dwarf_tag(in_die) == DW_TAG_inlined_subroutine) {
fname = die_get_call_file(in_die);
lineno = die_get_call_lineno(in_die);
- if (fname && lineno > 0 && dwarf_entrypc(in_die, &addr) == 0) {
+ if (fname && lineno > 0 && die_entrypc(in_die, &addr) == 0) {
lw->retval = lw->callback(fname, lineno, addr, lw->data);
if (lw->retval != 0)
return DIE_FIND_CB_END;
}
+ if (!lw->recursive)
+ return DIE_FIND_CB_SIBLING;
}
- if (!lw->recursive)
- /* Don't need to search recursively */
- return DIE_FIND_CB_SIBLING;
if (addr) {
fname = dwarf_decl_file(in_die);
@@ -720,7 +752,7 @@ static int __die_walk_funclines(Dwarf_Die *sp_die, bool recursive,
/* Handle function declaration line */
fname = dwarf_decl_file(sp_die);
if (fname && dwarf_decl_line(sp_die, &lineno) == 0 &&
- dwarf_entrypc(sp_die, &addr) == 0) {
+ die_entrypc(sp_die, &addr) == 0) {
lw.retval = callback(fname, lineno, addr, data);
if (lw.retval != 0)
goto done;
@@ -734,6 +766,10 @@ static int __die_walk_culines_cb(Dwarf_Die *sp_die, void *data)
{
struct __line_walk_param *lw = data;
+ /*
+ * Since inlined function can include another inlined function in
+ * the same file, we need to walk in it recursively.
+ */
lw->retval = __die_walk_funclines(sp_die, true, lw->callback, lw->data);
if (lw->retval != 0)
return DWARF_CB_ABORT;
@@ -758,11 +794,12 @@ int die_walk_lines(Dwarf_Die *rt_die, line_walk_callback_t callback, void *data)
Dwarf_Lines *lines;
Dwarf_Line *line;
Dwarf_Addr addr;
- const char *fname, *decf = NULL;
+ const char *fname, *decf = NULL, *inf = NULL;
int lineno, ret = 0;
int decl = 0, inl;
Dwarf_Die die_mem, *cu_die;
size_t nlines, i;
+ bool flag;
/* Get the CU die */
if (dwarf_tag(rt_die) != DW_TAG_compile_unit) {
@@ -793,6 +830,12 @@ int die_walk_lines(Dwarf_Die *rt_die, line_walk_callback_t callback, void *data)
"Possible error in debuginfo.\n");
continue;
}
+ /* Skip end-of-sequence */
+ if (dwarf_lineendsequence(line, &flag) != 0 || flag)
+ continue;
+ /* Skip Non statement line-info */
+ if (dwarf_linebeginstatement(line, &flag) != 0 || !flag)
+ continue;
/* Filter lines based on address */
if (rt_die != cu_die) {
/*
@@ -802,13 +845,21 @@ int die_walk_lines(Dwarf_Die *rt_die, line_walk_callback_t callback, void *data)
*/
if (!dwarf_haspc(rt_die, addr))
continue;
+
if (die_find_inlinefunc(rt_die, addr, &die_mem)) {
+ /* Call-site check */
+ inf = die_get_call_file(&die_mem);
+ if ((inf && !strcmp(inf, decf)) &&
+ die_get_call_lineno(&die_mem) == lineno)
+ goto found;
+
dwarf_decl_line(&die_mem, &inl);
if (inl != decl ||
decf != dwarf_decl_file(&die_mem))
continue;
}
}
+found:
/* Get source line */
fname = dwarf_linesrc(line, NULL, NULL);
@@ -823,8 +874,9 @@ int die_walk_lines(Dwarf_Die *rt_die, line_walk_callback_t callback, void *data)
*/
if (rt_die != cu_die)
/*
- * Don't need walk functions recursively, because nested
- * inlined functions don't have lines of the specified DIE.
+ * Don't need walk inlined functions recursively, because
+ * inner inlined functions don't have the lines of the
+ * specified function.
*/
ret = __die_walk_funclines(rt_die, false, callback, data);
else {
@@ -999,7 +1051,7 @@ static int die_get_var_innermost_scope(Dwarf_Die *sp_die, Dwarf_Die *vr_die,
bool first = true;
const char *name;
- ret = dwarf_entrypc(sp_die, &entry);
+ ret = die_entrypc(sp_die, &entry);
if (ret)
return ret;
@@ -1062,7 +1114,7 @@ int die_get_var_range(Dwarf_Die *sp_die, Dwarf_Die *vr_die, struct strbuf *buf)
bool first = true;
const char *name;
- ret = dwarf_entrypc(sp_die, &entry);
+ ret = die_entrypc(sp_die, &entry);
if (ret)
return ret;
diff --git a/tools/perf/util/dwarf-aux.h b/tools/perf/util/dwarf-aux.h
index 8ac53bf..ee15fac4 100644
--- a/tools/perf/util/dwarf-aux.h
+++ b/tools/perf/util/dwarf-aux.h
@@ -41,6 +41,9 @@ int cu_walk_functions_at(Dwarf_Die *cu_die, Dwarf_Addr addr,
/* Get DW_AT_linkage_name (should be NULL for C binary) */
const char *die_get_linkage_name(Dwarf_Die *dw_die);
+/* Get the lowest PC in DIE (including range list) */
+int die_entrypc(Dwarf_Die *dw_die, Dwarf_Addr *addr);
+
/* Ensure that this DIE is a subprogram and definition (not declaration) */
bool die_is_func_def(Dwarf_Die *dw_die);
diff --git a/tools/perf/util/perf_regs.h b/tools/perf/util/perf_regs.h
index 679d6e4..e632439 100644
--- a/tools/perf/util/perf_regs.h
+++ b/tools/perf/util/perf_regs.h
@@ -26,7 +26,7 @@ int perf_reg_value(u64 *valp, struct regs_dump *regs, int id);
static inline const char *perf_reg_name(int id __maybe_unused)
{
- return NULL;
+ return "unknown";
}
static inline int perf_reg_value(u64 *valp __maybe_unused,
diff --git a/tools/perf/util/probe-finder.c b/tools/perf/util/probe-finder.c
index 0d9d6e0..6ca804a 100644
--- a/tools/perf/util/probe-finder.c
+++ b/tools/perf/util/probe-finder.c
@@ -764,6 +764,16 @@ static int find_best_scope_cb(Dwarf_Die *fn_die, void *data)
return 0;
}
+/* Return innermost DIE */
+static int find_inner_scope_cb(Dwarf_Die *fn_die, void *data)
+{
+ struct find_scope_param *fsp = data;
+
+ memcpy(fsp->die_mem, fn_die, sizeof(Dwarf_Die));
+ fsp->found = true;
+ return 1;
+}
+
/* Find an appropriate scope fits to given conditions */
static Dwarf_Die *find_best_scope(struct probe_finder *pf, Dwarf_Die *die_mem)
{
@@ -775,8 +785,13 @@ static Dwarf_Die *find_best_scope(struct probe_finder *pf, Dwarf_Die *die_mem)
.die_mem = die_mem,
.found = false,
};
+ int ret;
- cu_walk_functions_at(&pf->cu_die, pf->addr, find_best_scope_cb, &fsp);
+ ret = cu_walk_functions_at(&pf->cu_die, pf->addr, find_best_scope_cb,
+ &fsp);
+ if (!ret && !fsp.found)
+ cu_walk_functions_at(&pf->cu_die, pf->addr,
+ find_inner_scope_cb, &fsp);
return fsp.found ? die_mem : NULL;
}
@@ -950,7 +965,7 @@ static int probe_point_inline_cb(Dwarf_Die *in_die, void *data)
ret = find_probe_point_lazy(in_die, pf);
else {
/* Get probe address */
- if (dwarf_entrypc(in_die, &addr) != 0) {
+ if (die_entrypc(in_die, &addr) != 0) {
pr_warning("Failed to get entry address of %s.\n",
dwarf_diename(in_die));
return -ENOENT;
@@ -1002,7 +1017,7 @@ static int probe_point_search_cb(Dwarf_Die *sp_die, void *data)
param->retval = find_probe_point_by_line(pf);
} else if (die_is_func_instance(sp_die)) {
/* Instances always have the entry address */
- dwarf_entrypc(sp_die, &pf->addr);
+ die_entrypc(sp_die, &pf->addr);
/* But in some case the entry address is 0 */
if (pf->addr == 0) {
pr_debug("%s has no entry PC. Skipped\n",
@@ -1414,6 +1429,18 @@ static int collect_variables_cb(Dwarf_Die *die_mem, void *data)
return DIE_FIND_CB_END;
}
+static bool available_var_finder_overlap(struct available_var_finder *af)
+{
+ int i;
+
+ for (i = 0; i < af->nvls; i++) {
+ if (af->pf.addr == af->vls[i].point.address)
+ return true;
+ }
+ return false;
+
+}
+
/* Add a found vars into available variables list */
static int add_available_vars(Dwarf_Die *sc_die, struct probe_finder *pf)
{
@@ -1424,6 +1451,14 @@ static int add_available_vars(Dwarf_Die *sc_die, struct probe_finder *pf)
Dwarf_Die die_mem;
int ret;
+ /*
+ * For some reason (e.g. different column assigned to same address),
+ * this callback can be called with the address which already passed.
+ * Ignore it first.
+ */
+ if (available_var_finder_overlap(af))
+ return 0;
+
/* Check number of tevs */
if (af->nvls == af->max_vls) {
pr_warning("Too many( > %d) probe point found.\n", af->max_vls);
@@ -1567,7 +1602,7 @@ int debuginfo__find_probe_point(struct debuginfo *dbg, unsigned long addr,
/* Get function entry information */
func = basefunc = dwarf_diename(&spdie);
if (!func ||
- dwarf_entrypc(&spdie, &baseaddr) != 0 ||
+ die_entrypc(&spdie, &baseaddr) != 0 ||
dwarf_decl_line(&spdie, &baseline) != 0) {
lineno = 0;
goto post;
@@ -1584,7 +1619,7 @@ int debuginfo__find_probe_point(struct debuginfo *dbg, unsigned long addr,
while (die_find_top_inlinefunc(&spdie, (Dwarf_Addr)addr,
&indie)) {
/* There is an inline function */
- if (dwarf_entrypc(&indie, &_addr) == 0 &&
+ if (die_entrypc(&indie, &_addr) == 0 &&
_addr == addr) {
/*
* addr is at an inline function entry.
diff --git a/tools/perf/util/strbuf.c b/tools/perf/util/strbuf.c
index 842cf3f..d7e5c24 100644
--- a/tools/perf/util/strbuf.c
+++ b/tools/perf/util/strbuf.c
@@ -116,7 +116,6 @@ static int strbuf_addv(struct strbuf *sb, const char *fmt, va_list ap)
return ret;
}
len = vsnprintf(sb->buf + sb->len, sb->alloc - sb->len, fmt, ap_saved);
- va_end(ap_saved);
if (len > strbuf_avail(sb)) {
pr_debug("this should not happen, your vsnprintf is broken");
va_end(ap_saved);
diff --git a/tools/power/cpupower/utils/idle_monitor/hsw_ext_idle.c b/tools/power/cpupower/utils/idle_monitor/hsw_ext_idle.c
index ebeaba6..475e18e 100644
--- a/tools/power/cpupower/utils/idle_monitor/hsw_ext_idle.c
+++ b/tools/power/cpupower/utils/idle_monitor/hsw_ext_idle.c
@@ -40,7 +40,6 @@ static cstate_t hsw_ext_cstates[HSW_EXT_CSTATE_COUNT] = {
{
.name = "PC9",
.desc = N_("Processor Package C9"),
- .desc = N_("Processor Package C2"),
.id = PC9,
.range = RANGE_PACKAGE,
.get_count_percent = hsw_ext_get_count_percent,