MIPS: Octeon: Implement delays with cycle counter.
Power throttling make deterministic delay loops impossible.
Re-implement delays using the cycle counter. This also allows us to
get rid of the code that calculates loops per jiffy.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1317/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 8c81a5c..7216fbd 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -594,13 +594,13 @@
* the filesystem. Also specify the calibration delay
* to avoid calculating it every time.
*/
- strcat(arcs_cmdline, " rw root=1f00"
- " lpj=60176 slram=root,0x40000000,+1073741824");
+ strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824");
}
mips_hpt_frequency = octeon_get_clock_rate();
octeon_init_cvmcount();
+ octeon_setup_delays();
_machine_restart = octeon_restart;
_machine_halt = octeon_halt;