tree a1a133a87129f779abad37eaa3861b84f7ddc816
parent 54acbd9688e6324470671525c7916011f1ff8081
author Chew, Chiau Ee <chiau.ee.chew@intel.com> 1385662391 +0800
committer Mark Brown <broonie@linaro.org> 1385637817 +0000

spi/pxa2xx: Restore private register bits.

The Intel LPSS SPI private register bits have to be restored
when system resume from S3 suspend.

Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Mark Brown <broonie@linaro.org>