tree e51e0b1abaf22aa3a3c462590c89103048a694cb
parent 0312af84164215a452f2a94957ebd9bce86e0204
author Thomas Gleixner <tglx@linutronix.de> 1244446241 +0200
committer Ingo Molnar <mingo@elte.hu> 1244452707 +0200

perf_counter, x86: Implement generalized cache event types, add Atom support

Fill in core2_hw_cache_event_id[] with the Atom model specific events.

The events can be used in all the tools via the -e (--event) parameter,
for example "-e l1-misses" or -"-e l2-accesses" or "-e l2-write-misses".

( Note: these are straight from the Intel manuals - not tested yet.)

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>