drivers: GICv3: Add mb() after the read of GIC registers
As per the GICv3 architecture spec section "Observability
of GIC Register Accesses", architecture execution of the "DSB"
gurantees the read/write access to ICC_PMR_EL1 and ICC_SGI1R_EL1
are observed by the associated restributor.
Change-Id: I9c7bcdee51f71d369e2a6f04faf7a22c3c1381bc
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
[abhimany: relocate mb()'s to header files]
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
[ckadabi: remove sync of some of register that is already upstream]
Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index 8ec88e5..7c975a1 100644
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -132,6 +132,8 @@
static inline void gic_write_pmr(u32 val)
{
asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" ((u64)val));
+ /* As per the architecture specification */
+ mb();
}
static inline void gic_write_ctlr(u32 val)
@@ -149,6 +151,8 @@
static inline void gic_write_sgi1r(u64 val)
{
asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
+ /* As per the architecture specification */
+ mb();
}
static inline u32 gic_read_sre(void)