commit | 88b4bd7071ac06e321b4bf4bdb8c69db40182c5a | [log] [tgz] |
---|---|---|
author | Andrew Bresticker <abrestic@chromium.org> | Thu Dec 26 16:44:26 2013 -0800 |
committer | Peter De Schrijver <pdeschrijver@nvidia.com> | Mon Feb 17 16:18:28 2014 +0200 |
tree | d7eb0c0bb43d499be95386347f6560a08b17ff95 | |
parent | 20e7c323abac390deb35248705807bd844590048 [diff] |
clk: tegra: cclk_lp has a pllx/2 divider When pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines whether cclk_lp output is divided by 2. Set TEGRA_DIVIDER_2 so that the clk_super driver is aware of this. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>