tree 618f6ef4d1b4a35bba74af004a0aabdde4f315e2
parent cf36df6bfb49fd265a39f676bfc9718029fef160
author Clemens Ladisch <clemens@ladisch.de> 1268820475 +0100
committer Stefan Richter <stefanr@s5r6.in-berlin.de> 1268864682 +0100

firewire: ohci: add cycle timer quirk for the TI TSB12LV22

Among the many entries in the TSB12LV22 errata list (TI literature
number SLLS312) is the following:

  PCI Slave reads of the Cycle Timer register may occasionally get an
  incorrect value.
  Software may be able to validate value by reading the register
  multiple times rapidly and evaluating for a reasonable difference.

Signed-off-by: Clemens Ladisch <clemens@ladisch.de> (untested)
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de> (added #define)