tree 0c9a829ca83489a35631d43e3f124bfcd35eb7d5
parent 0e766c2d9fc8cd2ad0e0fe97ff4e264cb686fc32
author Mark Zhang <markz@nvidia.com> 1388105064 -0800
committer Peter De Schrijver <pdeschrijver@nvidia.com> 1392646696 +0200

clk: tegra: fix host1x clock on Tegra124

The host1x clock on Tegra124 is a 3-bit wide mux with 6 parents.
Change thte id to tegra_clk_host1x_8 so that the correct clock gets
registered.

Signed-off-by: Mark Zhang <markz@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>