tree 1b3d7352466b01abdc09c7581ddcec19507237ce
parent c9eaa447e77efe77b7fa4c953bd62de8297fd6c5
author Qipan Li <Qipan.Li@csr.com> 1397456997 +0800
committer Mark Brown <broonie@linaro.org> 1397505710 +0100

spi: sirf: correct TXFIFO empty interrupt status bit

the old code uses wrong marco - SIRFSOC_SPI_FIFO_FULL is not for
FIFO interrupt status, it is for FIFO status. here in the ISR,
SIRFSOC_SPI_TXFIFO_EMPTY is the right bit for SPI TXFIFO interrupt
status.

Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Mark Brown <broonie@linaro.org>