soc: qcom: Add debug reset sequnce for modem before collecting minidump
Debug reset sequnce is special reset sequence where PBL directly jumps
to q6 start address and boot q6. This requirement is part of minidump
requirement.
Change-Id: Ic2821ba19d449f76c63ddb22887c319b8afd0a98
Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
diff --git a/drivers/soc/qcom/pil-msa.c b/drivers/soc/qcom/pil-msa.c
index e0f912d..03f54f9 100644
--- a/drivers/soc/qcom/pil-msa.c
+++ b/drivers/soc/qcom/pil-msa.c
@@ -35,6 +35,7 @@
/* Q6 Register Offsets */
#define QDSP6SS_RST_EVB 0x010
#define QDSP6SS_DBG_CFG 0x018
+#define QDSP6SS_NMI_CFG 0x40
/* AXI Halting Registers */
#define MSS_Q6_HALT_BASE 0x180
@@ -366,10 +367,10 @@ int pil_mss_shutdown(struct pil_desc *pil)
ret);
}
- pil_mss_assert_resets(drv);
+ pil_mss_restart_reg(drv, true);
/* Wait 6 32kHz sleep cycles for reset */
udelay(200);
- ret = pil_mss_deassert_resets(drv);
+ ret = pil_mss_restart_reg(drv, false);
if (drv->is_booted) {
pil_mss_disable_clks(drv);
@@ -777,6 +778,60 @@ int pil_mss_reset_load_mba(struct pil_desc *pil)
return ret;
}
+int pil_mss_debug_reset(struct pil_desc *pil)
+{
+ struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc);
+ int ret;
+
+ if (!pil->minidump)
+ return 0;
+ /*
+ * Bring subsystem out of reset and enable required
+ * regulators and clocks.
+ */
+ ret = pil_mss_enable_clks(drv);
+ if (ret)
+ return ret;
+
+ if (pil->minidump) {
+ writel_relaxed(0x1, drv->reg_base + QDSP6SS_NMI_CFG);
+ /* Let write complete before proceeding */
+ mb();
+ udelay(2);
+ }
+ /* Assert reset to subsystem */
+ pil_mss_restart_reg(drv, true);
+ /* Wait 6 32kHz sleep cycles for reset */
+ udelay(200);
+ ret = pil_mss_restart_reg(drv, false);
+ if (ret)
+ goto err_restart;
+ /* Let write complete before proceeding */
+ mb();
+ udelay(200);
+ ret = pil_q6v5_reset(pil);
+ /*
+ * Need to Wait for timeout for debug reset sequence to
+ * complete before returning
+ */
+ pr_debug("Minidump: waiting encryption to complete\n");
+ msleep(30000);
+ if (pil->minidump) {
+ writel_relaxed(0x2, drv->reg_base + QDSP6SS_NMI_CFG);
+ /* Let write complete before proceeding */
+ mb();
+ udelay(200);
+ }
+ if (ret)
+ goto err_restart;
+ return 0;
+err_restart:
+ pil_mss_disable_clks(drv);
+ if (drv->ahb_clk_vote)
+ clk_disable_unprepare(drv->ahb_clk);
+ return ret;
+}
+
static int pil_msa_auth_modem_mdt(struct pil_desc *pil, const u8 *metadata,
size_t size, phys_addr_t region_start,
void *region)
diff --git a/drivers/soc/qcom/pil-msa.h b/drivers/soc/qcom/pil-msa.h
index 177d63a..a302a14 100644
--- a/drivers/soc/qcom/pil-msa.h
+++ b/drivers/soc/qcom/pil-msa.h
@@ -47,4 +47,5 @@ int pil_mss_deinit_image(struct pil_desc *pil);
int __pil_mss_deinit_image(struct pil_desc *pil, bool err_path);
int pil_mss_assert_resets(struct q6v5_data *drv);
int pil_mss_deassert_resets(struct q6v5_data *drv);
+int pil_mss_debug_reset(struct pil_desc *pil);
#endif
diff --git a/drivers/soc/qcom/pil-q6v5-mss.c b/drivers/soc/qcom/pil-q6v5-mss.c
index 9cb62ce..721124c 100644
--- a/drivers/soc/qcom/pil-q6v5-mss.c
+++ b/drivers/soc/qcom/pil-q6v5-mss.c
@@ -163,6 +163,10 @@ static int modem_ramdump(int enable, const struct subsys_desc *subsys)
if (ret)
return ret;
+ ret = pil_mss_debug_reset(&drv->q6->desc);
+ if (ret)
+ return ret;
+
ret = pil_mss_reset_load_mba(&drv->q6->desc);
if (ret)
return ret;