tree d1ae92626aa29eceb3dd91d9a6e0b45cd4912126
parent 727b020d14c42df981a539ae52964f222fed8bb8
author Rakesh Naidu Bhaviripudi <quic_rakeshb@quicinc.com> 1708421516 +0530
committer Harshitha Sai Neelati <quic_hsaineel@quicinc.com> 1713781314 +0530

msm: kgsl: Update the protect register list

Update the protect register list as per the latest recommendation. Since
we are now relying on last-span-unbound feature, following are changed.

1. Last-span-unbound feature covers GMU_AO block, we have to replace
A6XX_GMU_ALWAYS_ON_COUNTER_L with A6XX_CP_ALWAYS_ON_COUNTER_LO
while accessing from GPU.

2. GMU power perf counters are unused and we are out of register address
protection spans to make them available for on older targets.

3. Remove PWR counter group safely for a6xx targets and setup the
counters internally.

4. IFPC counters are moved to part of target specific code and enabled
with ADRENO feature flag.

Change-Id: Ifcff462b669bbf9da8e4d53c87affdc8a9fcb740
Signed-off-by: Rakesh Naidu Bhaviripudi <quic_rakeshb@quicinc.com>