spi: spi-geni-qcom: Introduce new driver for GENI based core
Introduce a new SPI driver for Qualcomm Techonologies Inc's (QTI) GENI
based serial engine cores.
The driver can currently do FIFO mode of data transfer, here the driver
writes/reads data to/from the HW FIFO directly.
Change-Id: I3d14bdf0acf6a8c1f7772d8f3f4e1cd17f44c78e
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
diff --git a/include/linux/qcom-geni-se.h b/include/linux/qcom-geni-se.h
index f3ce6b4..e1ad51e 100644
--- a/include/linux/qcom-geni-se.h
+++ b/include/linux/qcom-geni-se.h
@@ -49,6 +49,7 @@ struct se_geni_rsc {
#define PINCTRL_DEFAULT "default"
#define PINCTRL_SLEEP "sleep"
+/* Common SE registers */
#define GENI_INIT_CFG_REVISION (0x0)
#define GENI_S_INIT_CFG_REVISION (0x4)
#define GENI_FORCE_DEFAULT_REG (0x20)
@@ -126,6 +127,9 @@ struct se_geni_rsc {
#define FW_REV_PROTOCOL_MSK (GENMASK(15, 8))
#define FW_REV_PROTOCOL_SHFT (8)
+/* GENI_CLK_SEL fields */
+#define CLK_SEL_MSK (GENMASK(2, 0))
+
/* SE_GENI_DMA_MODE_EN */
#define GENI_DMA_MODE_EN (BIT(0))
@@ -280,9 +284,10 @@ static inline int se_geni_irq_en(void __iomem *base, int mode)
switch (mode) {
case FIFO_MODE:
{
- if (proto == I2C) {
+ if (proto != UART) {
common_geni_m_irq_en |=
- (M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
+ (M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN |
+ M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
common_geni_s_irq_en |= S_CMD_DONE_EN;
}
break;