MIPS: Code clean-ups for the GIC.
Fix whitespace, beautify the code and remove debug statements.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
index 18124c3..770c075 100644
--- a/arch/mips/kernel/irq-gic.c
+++ b/arch/mips/kernel/irq-gic.c
@@ -1,5 +1,11 @@
-#undef DEBUG
-
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
+ */
#include <linux/bitmap.h>
#include <linux/init.h>
#include <linux/smp.h>
@@ -11,7 +17,6 @@
#include <linux/hardirq.h>
#include <asm-generic/bitops/find.h>
-
unsigned long _gic_base;
unsigned int gic_irq_base;
unsigned int gic_irq_flags[GIC_NUM_INTRS];
@@ -22,17 +27,15 @@
void gic_send_ipi(unsigned int intr)
{
- pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__,
- read_c0_status());
GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
}
-/* This is Malta specific and needs to be exported */
static void __init vpe_local_setup(unsigned int numvpes)
{
- int i;
- unsigned long timer_interrupt = 5, perf_interrupt = 5;
+ unsigned long timer_interrupt = GIC_INT_TMR;
+ unsigned long perf_interrupt = GIC_INT_PERFCTR;
unsigned int vpe_ctl;
+ int i;
/*
* Setup the default performance counter timer interrupts
@@ -79,40 +82,30 @@
bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);
- i = find_first_bit(pending, GIC_NUM_INTRS);
-
- pr_debug("CPU%d: %s pend=%d\n", smp_processor_id(), __func__, i);
-
- return i;
+ return find_first_bit(pending, GIC_NUM_INTRS);
}
static void gic_mask_irq(struct irq_data *d)
{
- unsigned int irq = d->irq - gic_irq_base;
- pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
- GIC_CLR_INTR_MASK(irq);
+ GIC_CLR_INTR_MASK(d->irq - gic_irq_base);
}
static void gic_unmask_irq(struct irq_data *d)
{
- unsigned int irq = d->irq - gic_irq_base;
- pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
- GIC_SET_INTR_MASK(irq);
+ GIC_SET_INTR_MASK(d->irq - gic_irq_base);
}
#ifdef CONFIG_SMP
-
static DEFINE_SPINLOCK(gic_lock);
static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
bool force)
{
- unsigned int irq = d->irq - gic_irq_base;
+ unsigned int irq = (d->irq - gic_irq_base);
cpumask_t tmp = CPU_MASK_NONE;
unsigned long flags;
int i;
- pr_debug("%s(%d) called\n", __func__, irq);
cpumask_and(&tmp, cpumask, cpu_online_mask);
if (cpus_empty(tmp))
return -1;
@@ -176,6 +169,7 @@
/* Init Intr Masks */
GIC_CLR_INTR_MASK(intr);
+
/* Initialise per-cpu Interrupt software masks */
if (flags & GIC_FLAG_IPI)
set_bit(intr, pcpu_masks[cpu].pcpu_mask);
@@ -237,8 +231,6 @@
numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
GIC_SH_CONFIG_NUMVPES_SHF;
- pr_debug("%s called\n", __func__);
-
gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);
gic_platform_init(numintrs, &gic_irq_controller);