| commit | fa7fadf78e064d1d73d21d0487e2a31a394a88ae | [log] [tgz] |
|---|---|---|
| author | Star Zeng <star.zeng@intel.com> | Fri Aug 22 01:23:28 2014 +0000 |
| committer | lzeng14 <lzeng14@6f19259b-4bc3-4df7-8a09-765794883524> | Fri Aug 22 01:23:28 2014 +0000 |
| tree | 7728a00768a68ae5314c4063cfd1d18e90fbd5e5 | |
| parent | acedecdd5ec4f45c9b7d456d01017c43e9fd2fb2 [diff] |
IntelFspPkg BaseCacheLib: State CacheAsRamLib in its inf, because it consumes DisableCacheAsRam() that is the interface of CacheAsRamLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15877 6f19259b-4bc3-4df7-8a09-765794883524