| commit | c01dc29b86784fc54619e7f8010daf109f0af5c5 | [log] [tgz] |
|---|---|---|
| author | Evgeny Astigeevich <evgeny.astigeevich@linaro.org> | Wed Dec 12 15:32:57 2018 +0000 |
| committer | Vladimir Marko <vmarko@google.com> | Tue Dec 18 08:50:38 2018 +0000 |
| tree | 4a2b47201172a515c72b7e86524055b381cd1d13 | |
| parent | ea1550c1722a283ce6b7f87027c51d5c078d202b [diff] |
ART: Optimize use of registers for CRC32.update intrinsic Use a VIXL scratch register and specify the output register does not overlap with input registers. Test: m test-art-target-gtest Test: m test-art-host-gtest Test: art/test.py --target --optimizing Test: art/test.py --host --optimizing Test: 580-crc32 Change-Id: If2f4b65eb1dfd5aace385dd3e571376a9867c662