| commit | 99ad7230ccaace93bf323dea9790f35fe991a4a2 | [log] [tgz] |
|---|---|---|
| author | Razvan A Lupusoru <razvan.a.lupusoru@intel.com> | Tue Feb 25 17:41:08 2014 -0800 |
| committer | Ian Rogers <irogers@google.com> | Wed Mar 26 16:20:09 2014 -0700 |
| tree | 095705c674703953bf4c50f6a30a105420b770b5 | |
| parent | a9e3d2ccfdbf7f4c7b1508bcb2b774037399b1d4 [diff] |
Relaxed memory barriers for x86 X86 provides stronger memory guarantees and thus the memory barriers can be optimized. This patch ensures that all memory barriers for x86 are treated as scheduling barriers. And in cases where a barrier is needed (StoreLoad case), an mfence is used. Change-Id: I13d02bf3f152083ba9f358052aedb583b0d48640 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>