Fix JNI compiler for mips64

Fix assembly instructions in JNI stub to store the right size. Fix
callee-saves in JNI calling convention to reflect return registers.
Fix pointer size in mips64 assembler.

Change-Id: I4eccd1f56f62fa9119918192ec424e9073398bc7
diff --git a/compiler/driver/compiler_driver.cc b/compiler/driver/compiler_driver.cc
index f52f50e..b32e1f2 100644
--- a/compiler/driver/compiler_driver.cc
+++ b/compiler/driver/compiler_driver.cc
@@ -2214,10 +2214,8 @@
         InstructionSetHasGenericJniStub(instruction_set_)) {
       // Leaving this empty will trigger the generic JNI version
     } else {
-      if (instruction_set_ != kMips64) {  // Use generic JNI for Mips64 (temporarily).
-        compiled_method = compiler_->JniCompile(access_flags, method_idx, dex_file);
-        CHECK(compiled_method != nullptr);
-      }
+      compiled_method = compiler_->JniCompile(access_flags, method_idx, dex_file);
+      CHECK(compiled_method != nullptr);
     }
   } else if ((access_flags & kAccAbstract) != 0) {
     // Abstract methods don't have code.
diff --git a/compiler/jni/quick/mips64/calling_convention_mips64.cc b/compiler/jni/quick/mips64/calling_convention_mips64.cc
index 17325d6..d446867 100644
--- a/compiler/jni/quick/mips64/calling_convention_mips64.cc
+++ b/compiler/jni/quick/mips64/calling_convention_mips64.cc
@@ -126,25 +126,20 @@
 Mips64JniCallingConvention::Mips64JniCallingConvention(bool is_static, bool is_synchronized,
                                                        const char* shorty)
     : JniCallingConvention(is_static, is_synchronized, shorty, kFramePointerSize) {
-  callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S0));
-  callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S1));
   callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S2));
   callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S3));
   callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S4));
   callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S5));
   callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S6));
   callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S7));
-
   callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(GP));
-  callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(SP));
   callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S8));
 }
 
 uint32_t Mips64JniCallingConvention::CoreSpillMask() const {
   // Compute spill mask to agree with callee saves initialized in the constructor
   uint32_t result = 0;
-  result = 1 << S0 | 1 << S1 | 1 << S2 | 1 << S3 | 1 << S4 | 1 << S5 | 1 << S6 |
-           1 << S7 | 1 << GP | 1 << SP | 1 << S8;
+  result = 1 << S2 | 1 << S3 | 1 << S4 | 1 << S5 | 1 << S6 | 1 << S7 | 1 << GP | 1 << S8 | 1 << RA;
   return result;
 }
 
diff --git a/compiler/utils/mips64/assembler_mips64.cc b/compiler/utils/mips64/assembler_mips64.cc
index 233ae7d..388d274 100644
--- a/compiler/utils/mips64/assembler_mips64.cc
+++ b/compiler/utils/mips64/assembler_mips64.cc
@@ -1025,7 +1025,7 @@
   __ Move(A0, scratch_.AsGpuRegister());
   // Set up call to Thread::Current()->pDeliverException
   __ LoadFromOffset(kLoadDoubleword, T9, S1,
-                    QUICK_ENTRYPOINT_OFFSET(4, pDeliverException).Int32Value());
+                    QUICK_ENTRYPOINT_OFFSET(8, pDeliverException).Int32Value());
   __ Jr(T9);
   // Call never returns
   __ Break();
diff --git a/runtime/arch/mips64/jni_entrypoints_mips64.S b/runtime/arch/mips64/jni_entrypoints_mips64.S
index 90fd3ee..1085666 100644
--- a/runtime/arch/mips64/jni_entrypoints_mips64.S
+++ b/runtime/arch/mips64/jni_entrypoints_mips64.S
@@ -28,21 +28,21 @@
     .cfi_adjust_cfa_offset 80
     sd     $ra, 64($sp)
     .cfi_rel_offset 31, 64
-    sw     $a7, 56($sp)
+    sd     $a7, 56($sp)
     .cfi_rel_offset 11, 56
-    sw     $a6, 48($sp)
+    sd     $a6, 48($sp)
     .cfi_rel_offset 10, 48
-    sw     $a5, 40($sp)
+    sd     $a5, 40($sp)
     .cfi_rel_offset 9, 40
-    sw     $a4, 32($sp)
+    sd     $a4, 32($sp)
     .cfi_rel_offset 8, 32
-    sw     $a3, 24($sp)
+    sd     $a3, 24($sp)
     .cfi_rel_offset 7, 24
-    sw     $a2, 16($sp)
+    sd     $a2, 16($sp)
     .cfi_rel_offset 6, 16
-    sw     $a1, 8($sp)
+    sd     $a1, 8($sp)
     .cfi_rel_offset 5, 8
-    sw     $a0, 0($sp)
+    sd     $a0, 0($sp)
     .cfi_rel_offset 4, 0
     jal    artFindNativeMethod  # (Thread*)
     move   $a0, $s1             # pass Thread::Current()