commit 6ac6f987086150877f0729f271f8a158a0c2c405
author rsun3 <rsun3@6f19259b-4bc3-4df7-8a09-765794883524> Wed Dec 22 02:34:45 2010 +0000
committer rsun3 <rsun3@6f19259b-4bc3-4df7-8a09-765794883524> Wed Dec 22 02:34:45 2010 +0000
tree 3fbd1848892e2a753a94937c82c3469695c60171
parent 36e8c955576ebe4a7f564c4a18ae0c1fa391f737

Update definition of EFI_SMM_CPU_SAVE_STATE to exclude Itanium save state. Note this is an inconsistency with the Framework SMM CIS spec.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11187 6f19259b-4bc3-4df7-8a09-765794883524

IntelFrameworkPkg/Include/Framework/SmmCis.h

diff --git a/IntelFrameworkPkg/Include/Framework/SmmCis.h b/IntelFrameworkPkg/Include/Framework/SmmCis.h
index 6991074..7aefd5b 100644
--- a/IntelFrameworkPkg/Include/Framework/SmmCis.h
+++ b/IntelFrameworkPkg/Include/Framework/SmmCis.h
@@ -307,9 +307,11 @@
   ///

   EFI_SMI_CPU_SAVE_STATE     Ia32SaveState;

   ///

+  /// Note: Inconsistency with the Framework SMM CIS spec - Itanium save state not included.

+  ///

   /// The processor save-state information for Itanium processors.

   ///

-  EFI_PMI_SYSTEM_CONTEXT     ItaniumSaveState;

+  /// EFI_PMI_SYSTEM_CONTEXT ItaniumSaveState;

 } EFI_SMM_CPU_SAVE_STATE;

 

 ///